1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4 #include <linux/etherdevice.h> 5 #include <linux/netdevice.h> 6 #include <linux/if_ether.h> 7 #include <linux/if_vlan.h> 8 #include <linux/iopoll.h> 9 #include <linux/pci.h> 10 11 #include "wx_type.h" 12 #include "wx_lib.h" 13 #include "wx_sriov.h" 14 #include "wx_hw.h" 15 16 static int wx_phy_read_reg_mdi(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 17 { 18 struct wx *wx = bus->priv; 19 u32 command, val; 20 int ret; 21 22 /* setup and write the address cycle command */ 23 command = WX_MSCA_RA(regnum) | 24 WX_MSCA_PA(phy_addr) | 25 WX_MSCA_DA(devnum); 26 wr32(wx, WX_MSCA, command); 27 28 command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY; 29 if (wx->mac.type == wx_mac_em) 30 command |= WX_MDIO_CLK(6); 31 wr32(wx, WX_MSCC, command); 32 33 /* wait to complete */ 34 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 35 100000, false, wx, WX_MSCC); 36 if (ret) { 37 wx_err(wx, "Mdio read c22 command did not complete.\n"); 38 return ret; 39 } 40 41 return (u16)rd32(wx, WX_MSCC); 42 } 43 44 static int wx_phy_write_reg_mdi(struct mii_bus *bus, int phy_addr, 45 int devnum, int regnum, u16 value) 46 { 47 struct wx *wx = bus->priv; 48 u32 command, val; 49 int ret; 50 51 /* setup and write the address cycle command */ 52 command = WX_MSCA_RA(regnum) | 53 WX_MSCA_PA(phy_addr) | 54 WX_MSCA_DA(devnum); 55 wr32(wx, WX_MSCA, command); 56 57 command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY; 58 if (wx->mac.type == wx_mac_em) 59 command |= WX_MDIO_CLK(6); 60 wr32(wx, WX_MSCC, command); 61 62 /* wait to complete */ 63 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 64 100000, false, wx, WX_MSCC); 65 if (ret) 66 wx_err(wx, "Mdio write c22 command did not complete.\n"); 67 68 return ret; 69 } 70 71 int wx_phy_read_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum) 72 { 73 struct wx *wx = bus->priv; 74 75 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 76 return wx_phy_read_reg_mdi(bus, phy_addr, 0, regnum); 77 } 78 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c22); 79 80 int wx_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum, u16 value) 81 { 82 struct wx *wx = bus->priv; 83 84 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 85 return wx_phy_write_reg_mdi(bus, phy_addr, 0, regnum, value); 86 } 87 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c22); 88 89 int wx_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 90 { 91 struct wx *wx = bus->priv; 92 93 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 94 return wx_phy_read_reg_mdi(bus, phy_addr, devnum, regnum); 95 } 96 EXPORT_SYMBOL(wx_phy_read_reg_mdi_c45); 97 98 int wx_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr, 99 int devnum, int regnum, u16 value) 100 { 101 struct wx *wx = bus->priv; 102 103 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 104 return wx_phy_write_reg_mdi(bus, phy_addr, devnum, regnum, value); 105 } 106 EXPORT_SYMBOL(wx_phy_write_reg_mdi_c45); 107 108 static void wx_intr_disable(struct wx *wx, u64 qmask) 109 { 110 u32 mask; 111 112 mask = (qmask & U32_MAX); 113 if (mask) 114 wr32(wx, WX_PX_IMS(0), mask); 115 116 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 117 mask = (qmask >> 32); 118 if (mask) 119 wr32(wx, WX_PX_IMS(1), mask); 120 } 121 } 122 123 void wx_intr_enable(struct wx *wx, u64 qmask) 124 { 125 u32 mask; 126 127 mask = (qmask & U32_MAX); 128 if (mask) 129 wr32(wx, WX_PX_IMC(0), mask); 130 131 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 132 mask = (qmask >> 32); 133 if (mask) 134 wr32(wx, WX_PX_IMC(1), mask); 135 } 136 } 137 EXPORT_SYMBOL(wx_intr_enable); 138 139 /** 140 * wx_irq_disable - Mask off interrupt generation on the NIC 141 * @wx: board private structure 142 **/ 143 void wx_irq_disable(struct wx *wx) 144 { 145 struct pci_dev *pdev = wx->pdev; 146 147 wr32(wx, WX_PX_MISC_IEN, 0); 148 wx_intr_disable(wx, WX_INTR_ALL); 149 150 if (pdev->msix_enabled) { 151 int vector; 152 153 for (vector = 0; vector < wx->num_q_vectors; vector++) 154 synchronize_irq(wx->msix_q_entries[vector].vector); 155 156 synchronize_irq(wx->msix_entry->vector); 157 } else { 158 synchronize_irq(pdev->irq); 159 } 160 } 161 EXPORT_SYMBOL(wx_irq_disable); 162 163 /* cmd_addr is used for some special command: 164 * 1. to be sector address, when implemented erase sector command 165 * 2. to be flash address when implemented read, write flash address 166 */ 167 static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr) 168 { 169 u32 cmd_val = 0, val = 0; 170 171 cmd_val = WX_SPI_CMD_CMD(cmd) | 172 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) | 173 cmd_addr; 174 wr32(wx, WX_SPI_CMD, cmd_val); 175 176 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, 177 false, wx, WX_SPI_STATUS); 178 } 179 180 static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data) 181 { 182 int ret = 0; 183 184 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr); 185 if (ret < 0) 186 return ret; 187 188 *data = rd32(wx, WX_SPI_DATA); 189 190 return ret; 191 } 192 193 int wx_check_flash_load(struct wx *hw, u32 check_bit) 194 { 195 u32 reg = 0; 196 int err = 0; 197 198 /* if there's flash existing */ 199 if (!(rd32(hw, WX_SPI_STATUS) & 200 WX_SPI_STATUS_FLASH_BYPASS)) { 201 /* wait hw load flash done */ 202 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, 203 false, hw, WX_SPI_ILDR_STATUS); 204 if (err < 0) 205 wx_err(hw, "Check flash load timeout.\n"); 206 } 207 208 return err; 209 } 210 EXPORT_SYMBOL(wx_check_flash_load); 211 212 void wx_control_hw(struct wx *wx, bool drv) 213 { 214 /* True : Let firmware know the driver has taken over 215 * False : Let firmware take over control of hw 216 */ 217 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD, 218 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0); 219 } 220 EXPORT_SYMBOL(wx_control_hw); 221 222 /** 223 * wx_mng_present - returns 0 when management capability is present 224 * @wx: pointer to hardware structure 225 */ 226 int wx_mng_present(struct wx *wx) 227 { 228 u32 fwsm; 229 230 fwsm = rd32(wx, WX_MIS_ST); 231 if (fwsm & WX_MIS_ST_MNG_INIT_DN) 232 return 0; 233 else 234 return -EACCES; 235 } 236 EXPORT_SYMBOL(wx_mng_present); 237 238 /* Software lock to be held while software semaphore is being accessed. */ 239 static DEFINE_MUTEX(wx_sw_sync_lock); 240 241 /** 242 * wx_release_sw_sync - Release SW semaphore 243 * @wx: pointer to hardware structure 244 * @mask: Mask to specify which semaphore to release 245 * 246 * Releases the SW semaphore for the specified 247 * function (CSR, PHY0, PHY1, EEPROM, Flash) 248 **/ 249 static void wx_release_sw_sync(struct wx *wx, u32 mask) 250 { 251 mutex_lock(&wx_sw_sync_lock); 252 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0); 253 mutex_unlock(&wx_sw_sync_lock); 254 } 255 256 /** 257 * wx_acquire_sw_sync - Acquire SW semaphore 258 * @wx: pointer to hardware structure 259 * @mask: Mask to specify which semaphore to acquire 260 * 261 * Acquires the SW semaphore for the specified 262 * function (CSR, PHY0, PHY1, EEPROM, Flash) 263 **/ 264 static int wx_acquire_sw_sync(struct wx *wx, u32 mask) 265 { 266 u32 sem = 0; 267 int ret = 0; 268 269 mutex_lock(&wx_sw_sync_lock); 270 ret = read_poll_timeout(rd32, sem, !(sem & mask), 271 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC); 272 if (!ret) { 273 sem |= mask; 274 wr32(wx, WX_MNG_SWFW_SYNC, sem); 275 } else { 276 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem); 277 } 278 mutex_unlock(&wx_sw_sync_lock); 279 280 return ret; 281 } 282 283 static int wx_host_interface_command_s(struct wx *wx, u32 *buffer, 284 u32 length, u32 timeout, bool return_data) 285 { 286 u32 hdr_size = sizeof(struct wx_hic_hdr); 287 u32 hicr, i, bi, buf[64] = {}; 288 int status = 0; 289 u32 dword_len; 290 u16 buf_len; 291 292 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 293 if (status != 0) 294 return status; 295 296 dword_len = length >> 2; 297 298 /* The device driver writes the relevant command block 299 * into the ram area. 300 */ 301 for (i = 0; i < dword_len; i++) { 302 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 303 /* write flush */ 304 buf[i] = rd32a(wx, WX_MNG_MBOX, i); 305 } 306 /* Setting this bit tells the ARC that a new command is pending. */ 307 wr32m(wx, WX_MNG_MBOX_CTL, 308 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY); 309 310 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, 311 timeout * 1000, false, wx, WX_MNG_MBOX_CTL); 312 313 buf[0] = rd32(wx, WX_MNG_MBOX); 314 if ((buf[0] & 0xff0000) >> 16 == 0x80) { 315 wx_err(wx, "Unknown FW command: 0x%x\n", buffer[0] & 0xff); 316 status = -EINVAL; 317 goto rel_out; 318 } 319 320 /* Check command completion */ 321 if (status) { 322 wx_err(wx, "Command has failed with no status valid.\n"); 323 wx_dbg(wx, "write value:\n"); 324 for (i = 0; i < dword_len; i++) 325 wx_dbg(wx, "%x ", buffer[i]); 326 wx_dbg(wx, "read value:\n"); 327 for (i = 0; i < dword_len; i++) 328 wx_dbg(wx, "%x ", buf[i]); 329 wx_dbg(wx, "\ncheck: %x %x\n", buffer[0] & 0xff, ~buf[0] >> 24); 330 331 goto rel_out; 332 } 333 334 if (!return_data) 335 goto rel_out; 336 337 /* Calculate length in DWORDs */ 338 dword_len = hdr_size >> 2; 339 340 /* first pull in the header so we know the buffer length */ 341 for (bi = 0; bi < dword_len; bi++) { 342 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 343 le32_to_cpus(&buffer[bi]); 344 } 345 346 /* If there is any thing in data position pull it in */ 347 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; 348 if (buf_len == 0) 349 goto rel_out; 350 351 if (length < buf_len + hdr_size) { 352 wx_err(wx, "Buffer not large enough for reply message.\n"); 353 status = -EFAULT; 354 goto rel_out; 355 } 356 357 /* Calculate length in DWORDs, add 3 for odd lengths */ 358 dword_len = (buf_len + 3) >> 2; 359 360 /* Pull in the rest of the buffer (bi is where we left off) */ 361 for (; bi <= dword_len; bi++) { 362 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 363 le32_to_cpus(&buffer[bi]); 364 } 365 366 rel_out: 367 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 368 return status; 369 } 370 371 static bool wx_poll_fw_reply(struct wx *wx, u32 *buffer, u8 send_cmd) 372 { 373 u32 dword_len = sizeof(struct wx_hic_hdr) >> 2; 374 struct wx_hic_hdr *recv_hdr; 375 u32 i; 376 377 /* read hdr */ 378 for (i = 0; i < dword_len; i++) { 379 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 380 le32_to_cpus(&buffer[i]); 381 } 382 383 /* check hdr */ 384 recv_hdr = (struct wx_hic_hdr *)buffer; 385 if (recv_hdr->cmd == send_cmd && 386 recv_hdr->index == wx->swfw_index) 387 return true; 388 389 return false; 390 } 391 392 static int wx_host_interface_command_r(struct wx *wx, u32 *buffer, 393 u32 length, u32 timeout, bool return_data) 394 { 395 struct wx_hic_hdr *hdr = (struct wx_hic_hdr *)buffer; 396 u32 hdr_size = sizeof(struct wx_hic_hdr); 397 bool busy, reply; 398 u32 dword_len; 399 u16 buf_len; 400 int err = 0; 401 u8 send_cmd; 402 u32 i; 403 404 /* wait to get lock */ 405 might_sleep(); 406 err = read_poll_timeout(test_and_set_bit, busy, !busy, 1000, timeout * 1000, 407 false, WX_STATE_SWFW_BUSY, wx->state); 408 if (err) 409 return err; 410 411 /* index to unique seq id for each mbox message */ 412 hdr->index = wx->swfw_index; 413 send_cmd = hdr->cmd; 414 415 dword_len = length >> 2; 416 /* write data to SW-FW mbox array */ 417 for (i = 0; i < dword_len; i++) { 418 wr32a(wx, WX_SW2FW_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 419 /* write flush */ 420 rd32a(wx, WX_SW2FW_MBOX, i); 421 } 422 423 /* generate interrupt to notify FW */ 424 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, 0); 425 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, WX_SW2FW_MBOX_CMD_VLD); 426 427 /* polling reply from FW */ 428 err = read_poll_timeout(wx_poll_fw_reply, reply, reply, 2000, 429 timeout * 1000, true, wx, buffer, send_cmd); 430 if (err) { 431 wx_err(wx, "Polling from FW messages timeout, cmd: 0x%x, index: %d\n", 432 send_cmd, wx->swfw_index); 433 goto rel_out; 434 } 435 436 if (hdr->cmd_or_resp.ret_status == 0x80) { 437 wx_err(wx, "Unknown FW command: 0x%x\n", send_cmd); 438 err = -EINVAL; 439 goto rel_out; 440 } 441 442 /* expect no reply from FW then return */ 443 if (!return_data) 444 goto rel_out; 445 446 /* If there is any thing in data position pull it in */ 447 buf_len = hdr->buf_len; 448 if (buf_len == 0) 449 goto rel_out; 450 451 if (length < buf_len + hdr_size) { 452 wx_err(wx, "Buffer not large enough for reply message.\n"); 453 err = -EFAULT; 454 goto rel_out; 455 } 456 457 /* Calculate length in DWORDs, add 3 for odd lengths */ 458 dword_len = (buf_len + 3) >> 2; 459 for (i = hdr_size >> 2; i <= dword_len; i++) { 460 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 461 le32_to_cpus(&buffer[i]); 462 } 463 464 rel_out: 465 /* index++, index replace wx_hic_hdr.checksum */ 466 if (wx->swfw_index == WX_HIC_HDR_INDEX_MAX) 467 wx->swfw_index = 0; 468 else 469 wx->swfw_index++; 470 471 clear_bit(WX_STATE_SWFW_BUSY, wx->state); 472 return err; 473 } 474 475 /** 476 * wx_host_interface_command - Issue command to manageability block 477 * @wx: pointer to the HW structure 478 * @buffer: contains the command to write and where the return status will 479 * be placed 480 * @length: length of buffer, must be multiple of 4 bytes 481 * @timeout: time in ms to wait for command completion 482 * @return_data: read and return data from the buffer (true) or not (false) 483 * Needed because FW structures are big endian and decoding of 484 * these fields can be 8 bit or 16 bit based on command. Decoding 485 * is not easily understood without making a table of commands. 486 * So we will leave this up to the caller to read back the data 487 * in these cases. 488 **/ 489 int wx_host_interface_command(struct wx *wx, u32 *buffer, 490 u32 length, u32 timeout, bool return_data) 491 { 492 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) { 493 wx_err(wx, "Buffer length failure buffersize=%d.\n", length); 494 return -EINVAL; 495 } 496 497 /* Calculate length in DWORDs. We must be DWORD aligned */ 498 if ((length % (sizeof(u32))) != 0) { 499 wx_err(wx, "Buffer length failure, not aligned to dword"); 500 return -EINVAL; 501 } 502 503 if (test_bit(WX_FLAG_SWFW_RING, wx->flags)) 504 return wx_host_interface_command_r(wx, buffer, length, 505 timeout, return_data); 506 507 return wx_host_interface_command_s(wx, buffer, length, timeout, return_data); 508 } 509 EXPORT_SYMBOL(wx_host_interface_command); 510 511 int wx_set_pps(struct wx *wx, bool enable, u64 nsec, u64 cycles) 512 { 513 struct wx_hic_set_pps pps_cmd; 514 515 pps_cmd.hdr.cmd = FW_PPS_SET_CMD; 516 pps_cmd.hdr.buf_len = FW_PPS_SET_LEN; 517 pps_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 518 pps_cmd.lan_id = wx->bus.func; 519 pps_cmd.enable = (u8)enable; 520 pps_cmd.nsec = nsec; 521 pps_cmd.cycles = cycles; 522 pps_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 523 524 return wx_host_interface_command(wx, (u32 *)&pps_cmd, 525 sizeof(pps_cmd), 526 WX_HI_COMMAND_TIMEOUT, 527 false); 528 } 529 530 /** 531 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd 532 * assuming that the semaphore is already obtained. 533 * @wx: pointer to hardware structure 534 * @offset: offset of word in the EEPROM to read 535 * @data: word read from the EEPROM 536 * 537 * Reads a 16 bit word from the EEPROM using the hostif. 538 **/ 539 static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data) 540 { 541 struct wx_hic_read_shadow_ram buffer; 542 int status; 543 544 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 545 buffer.hdr.req.buf_lenh = 0; 546 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 547 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 548 549 /* convert offset from words to bytes */ 550 buffer.address = (__force u32)cpu_to_be32(offset * 2); 551 /* one word */ 552 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 553 554 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer), 555 WX_HI_COMMAND_TIMEOUT, false); 556 557 if (status != 0) 558 return status; 559 560 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 561 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET); 562 else 563 *data = (u16)rd32a(wx, WX_FW2SW_MBOX, FW_NVM_DATA_OFFSET); 564 565 return status; 566 } 567 568 /** 569 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd 570 * @wx: pointer to hardware structure 571 * @offset: offset of word in the EEPROM to read 572 * @data: word read from the EEPROM 573 * 574 * Reads a 16 bit word from the EEPROM using the hostif. 575 **/ 576 int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data) 577 { 578 int status = 0; 579 580 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 581 if (status == 0) { 582 status = wx_read_ee_hostif_data(wx, offset, data); 583 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 584 } 585 586 return status; 587 } 588 EXPORT_SYMBOL(wx_read_ee_hostif); 589 590 /** 591 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif 592 * @wx: pointer to hardware structure 593 * @offset: offset of word in the EEPROM to read 594 * @words: number of words 595 * @data: word(s) read from the EEPROM 596 * 597 * Reads a 16 bit word(s) from the EEPROM using the hostif. 598 **/ 599 int wx_read_ee_hostif_buffer(struct wx *wx, 600 u16 offset, u16 words, u16 *data) 601 { 602 struct wx_hic_read_shadow_ram buffer; 603 u32 current_word = 0; 604 u16 words_to_read; 605 u32 value = 0; 606 int status; 607 u32 mbox; 608 u32 i; 609 610 /* Take semaphore for the entire operation. */ 611 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 612 if (status != 0) 613 return status; 614 615 while (words) { 616 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 617 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 618 else 619 words_to_read = words; 620 621 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 622 buffer.hdr.req.buf_lenh = 0; 623 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 624 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 625 626 /* convert offset from words to bytes */ 627 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2); 628 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 629 630 status = wx_host_interface_command(wx, (u32 *)&buffer, 631 sizeof(buffer), 632 WX_HI_COMMAND_TIMEOUT, 633 false); 634 635 if (status != 0) { 636 wx_err(wx, "Host interface command failed\n"); 637 goto out; 638 } 639 640 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 641 mbox = WX_MNG_MBOX; 642 else 643 mbox = WX_FW2SW_MBOX; 644 for (i = 0; i < words_to_read; i++) { 645 u32 reg = mbox + (FW_NVM_DATA_OFFSET << 2) + 2 * i; 646 647 value = rd32(wx, reg); 648 data[current_word] = (u16)(value & 0xffff); 649 current_word++; 650 i++; 651 if (i < words_to_read) { 652 value >>= 16; 653 data[current_word] = (u16)(value & 0xffff); 654 current_word++; 655 } 656 } 657 words -= words_to_read; 658 } 659 660 out: 661 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 662 return status; 663 } 664 EXPORT_SYMBOL(wx_read_ee_hostif_buffer); 665 666 /** 667 * wx_init_eeprom_params - Initialize EEPROM params 668 * @wx: pointer to hardware structure 669 * 670 * Initializes the EEPROM parameters wx_eeprom_info within the 671 * wx_hw struct in order to set up EEPROM access. 672 **/ 673 void wx_init_eeprom_params(struct wx *wx) 674 { 675 struct wx_eeprom_info *eeprom = &wx->eeprom; 676 u16 eeprom_size; 677 u16 data = 0x80; 678 679 if (eeprom->type == wx_eeprom_uninitialized) { 680 eeprom->semaphore_delay = 10; 681 eeprom->type = wx_eeprom_none; 682 683 if (!(rd32(wx, WX_SPI_STATUS) & 684 WX_SPI_STATUS_FLASH_BYPASS)) { 685 eeprom->type = wx_flash; 686 687 eeprom_size = 4096; 688 eeprom->word_size = eeprom_size >> 1; 689 690 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n", 691 eeprom->type, eeprom->word_size); 692 } 693 } 694 695 switch (wx->mac.type) { 696 case wx_mac_sp: 697 case wx_mac_aml: 698 case wx_mac_aml40: 699 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) { 700 wx_err(wx, "NVM Read Error\n"); 701 return; 702 } 703 data = data >> 1; 704 break; 705 default: 706 break; 707 } 708 709 eeprom->sw_region_offset = data; 710 } 711 EXPORT_SYMBOL(wx_init_eeprom_params); 712 713 /** 714 * wx_get_mac_addr - Generic get MAC address 715 * @wx: pointer to hardware structure 716 * @mac_addr: Adapter MAC address 717 * 718 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 719 * A reset of the adapter must be performed prior to calling this function 720 * in order for the MAC address to have been loaded from the EEPROM into RAR0 721 **/ 722 void wx_get_mac_addr(struct wx *wx, u8 *mac_addr) 723 { 724 u32 rar_high; 725 u32 rar_low; 726 u16 i; 727 728 wr32(wx, WX_PSR_MAC_SWC_IDX, 0); 729 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H); 730 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L); 731 732 for (i = 0; i < 2; i++) 733 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 734 735 for (i = 0; i < 4; i++) 736 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 737 } 738 EXPORT_SYMBOL(wx_get_mac_addr); 739 740 /** 741 * wx_set_rar - Set Rx address register 742 * @wx: pointer to hardware structure 743 * @index: Receive address register to write 744 * @addr: Address to put into receive address register 745 * @pools: VMDq "set" or "pool" index 746 * @enable_addr: set flag that address is active 747 * 748 * Puts an ethernet address into a receive address register. 749 **/ 750 static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools, 751 u32 enable_addr) 752 { 753 u32 rar_entries = wx->mac.num_rar_entries; 754 u32 rar_low, rar_high; 755 756 /* Make sure we are using a valid rar index range */ 757 if (index >= rar_entries) { 758 wx_err(wx, "RAR index %d is out of range.\n", index); 759 return -EINVAL; 760 } 761 762 /* select the MAC address */ 763 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 764 765 /* setup VMDq pool mapping */ 766 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); 767 768 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) 769 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32); 770 771 /* HW expects these in little endian so we reverse the byte 772 * order from network order (big endian) to little endian 773 * 774 * Some parts put the VMDq setting in the extra RAH bits, 775 * so save everything except the lower 16 bits that hold part 776 * of the address and the address valid bit. 777 */ 778 rar_low = ((u32)addr[5] | 779 ((u32)addr[4] << 8) | 780 ((u32)addr[3] << 16) | 781 ((u32)addr[2] << 24)); 782 rar_high = ((u32)addr[1] | 783 ((u32)addr[0] << 8)); 784 if (enable_addr != 0) 785 rar_high |= WX_PSR_MAC_SWC_AD_H_AV; 786 787 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low); 788 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 789 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 790 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 791 WX_PSR_MAC_SWC_AD_H_AV), 792 rar_high); 793 794 return 0; 795 } 796 797 /** 798 * wx_clear_rar - Remove Rx address register 799 * @wx: pointer to hardware structure 800 * @index: Receive address register to write 801 * 802 * Clears an ethernet address from a receive address register. 803 **/ 804 static int wx_clear_rar(struct wx *wx, u32 index) 805 { 806 u32 rar_entries = wx->mac.num_rar_entries; 807 808 /* Make sure we are using a valid rar index range */ 809 if (index >= rar_entries) { 810 wx_err(wx, "RAR index %d is out of range.\n", index); 811 return -EINVAL; 812 } 813 814 /* Some parts put the VMDq setting in the extra RAH bits, 815 * so save everything except the lower 16 bits that hold part 816 * of the address and the address valid bit. 817 */ 818 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 819 820 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0); 821 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0); 822 823 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 824 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 825 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 826 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 827 WX_PSR_MAC_SWC_AD_H_AV), 828 0); 829 830 return 0; 831 } 832 833 /** 834 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address 835 * @wx: pointer to hardware struct 836 * @rar: receive address register index to disassociate 837 * @vmdq: VMDq pool index to remove from the rar 838 **/ 839 static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq) 840 { 841 u32 rar_entries = wx->mac.num_rar_entries; 842 u32 mpsar_lo, mpsar_hi; 843 844 /* Make sure we are using a valid rar index range */ 845 if (rar >= rar_entries) { 846 wx_err(wx, "RAR index %d is out of range.\n", rar); 847 return -EINVAL; 848 } 849 850 wr32(wx, WX_PSR_MAC_SWC_IDX, rar); 851 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L); 852 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H); 853 854 if (!mpsar_lo && !mpsar_hi) 855 return 0; 856 857 /* was that the last pool using this rar? */ 858 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 859 wx_clear_rar(wx, rar); 860 861 return 0; 862 } 863 864 /** 865 * wx_init_uta_tables - Initialize the Unicast Table Array 866 * @wx: pointer to hardware structure 867 **/ 868 static void wx_init_uta_tables(struct wx *wx) 869 { 870 int i; 871 872 wx_dbg(wx, " Clearing UTA\n"); 873 874 for (i = 0; i < 128; i++) 875 wr32(wx, WX_PSR_UC_TBL(i), 0); 876 } 877 878 /** 879 * wx_init_rx_addrs - Initializes receive address filters. 880 * @wx: pointer to hardware structure 881 * 882 * Places the MAC address in receive address register 0 and clears the rest 883 * of the receive address registers. Clears the multicast table. Assumes 884 * the receiver is in reset when the routine is called. 885 **/ 886 void wx_init_rx_addrs(struct wx *wx) 887 { 888 u32 rar_entries = wx->mac.num_rar_entries; 889 u32 psrctl; 890 int i; 891 892 /* If the current mac address is valid, assume it is a software override 893 * to the permanent address. 894 * Otherwise, use the permanent address from the eeprom. 895 */ 896 if (!is_valid_ether_addr(wx->mac.addr)) { 897 /* Get the MAC address from the RAR0 for later reference */ 898 wx_get_mac_addr(wx, wx->mac.addr); 899 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr); 900 } else { 901 /* Setup the receive address. */ 902 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n"); 903 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr); 904 905 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV); 906 907 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 908 /* clear VMDq pool/queue selection for RAR 0 */ 909 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL); 910 } 911 } 912 913 /* Zero out the other receive addresses. */ 914 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1); 915 for (i = 1; i < rar_entries; i++) { 916 wr32(wx, WX_PSR_MAC_SWC_IDX, i); 917 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 918 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0); 919 } 920 921 /* Clear the MTA */ 922 wx->addr_ctrl.mta_in_use = 0; 923 psrctl = rd32(wx, WX_PSR_CTL); 924 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 925 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT; 926 wr32(wx, WX_PSR_CTL, psrctl); 927 wx_dbg(wx, " Clearing MTA\n"); 928 for (i = 0; i < wx->mac.mcft_size; i++) 929 wr32(wx, WX_PSR_MC_TBL(i), 0); 930 931 wx_init_uta_tables(wx); 932 } 933 EXPORT_SYMBOL(wx_init_rx_addrs); 934 935 static void wx_sync_mac_table(struct wx *wx) 936 { 937 int i; 938 939 for (i = 0; i < wx->mac.num_rar_entries; i++) { 940 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) { 941 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 942 wx_set_rar(wx, i, 943 wx->mac_table[i].addr, 944 wx->mac_table[i].pools, 945 WX_PSR_MAC_SWC_AD_H_AV); 946 } else { 947 wx_clear_rar(wx, i); 948 } 949 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 950 } 951 } 952 } 953 954 static void wx_full_sync_mac_table(struct wx *wx) 955 { 956 int i; 957 958 for (i = 0; i < wx->mac.num_rar_entries; i++) { 959 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 960 wx_set_rar(wx, i, 961 wx->mac_table[i].addr, 962 wx->mac_table[i].pools, 963 WX_PSR_MAC_SWC_AD_H_AV); 964 } else { 965 wx_clear_rar(wx, i); 966 } 967 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 968 } 969 } 970 971 /* this function destroys the first RAR entry */ 972 void wx_mac_set_default_filter(struct wx *wx, u8 *addr) 973 { 974 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN); 975 wx->mac_table[0].pools = BIT(VMDQ_P(0)); 976 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE); 977 wx_set_rar(wx, 0, wx->mac_table[0].addr, 978 wx->mac_table[0].pools, 979 WX_PSR_MAC_SWC_AD_H_AV); 980 } 981 EXPORT_SYMBOL(wx_mac_set_default_filter); 982 983 void wx_flush_sw_mac_table(struct wx *wx) 984 { 985 u32 i; 986 987 for (i = 0; i < wx->mac.num_rar_entries; i++) { 988 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE)) 989 continue; 990 991 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 992 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 993 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 994 wx->mac_table[i].pools = 0; 995 } 996 wx_sync_mac_table(wx); 997 } 998 EXPORT_SYMBOL(wx_flush_sw_mac_table); 999 1000 int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool) 1001 { 1002 u32 i; 1003 1004 if (is_zero_ether_addr(addr)) 1005 return -EINVAL; 1006 1007 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1008 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 1009 if (ether_addr_equal(addr, wx->mac_table[i].addr)) { 1010 if (wx->mac_table[i].pools != (1ULL << pool)) { 1011 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1012 wx->mac_table[i].pools |= (1ULL << pool); 1013 wx_sync_mac_table(wx); 1014 return i; 1015 } 1016 } 1017 } 1018 1019 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) 1020 continue; 1021 wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED | 1022 WX_MAC_STATE_IN_USE); 1023 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1024 wx->mac_table[i].pools |= (1ULL << pool); 1025 wx_sync_mac_table(wx); 1026 return i; 1027 } 1028 return -ENOMEM; 1029 } 1030 1031 int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool) 1032 { 1033 u32 i; 1034 1035 if (is_zero_ether_addr(addr)) 1036 return -EINVAL; 1037 1038 /* search table for addr, if found, set to 0 and sync */ 1039 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1040 if (!ether_addr_equal(addr, wx->mac_table[i].addr)) 1041 continue; 1042 1043 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 1044 wx->mac_table[i].pools &= ~(1ULL << pool); 1045 if (!wx->mac_table[i].pools) { 1046 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 1047 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 1048 } 1049 wx_sync_mac_table(wx); 1050 return 0; 1051 } 1052 return -ENOMEM; 1053 } 1054 1055 static int wx_available_rars(struct wx *wx) 1056 { 1057 u32 i, count = 0; 1058 1059 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1060 if (wx->mac_table[i].state == 0) 1061 count++; 1062 } 1063 1064 return count; 1065 } 1066 1067 /** 1068 * wx_write_uc_addr_list - write unicast addresses to RAR table 1069 * @netdev: network interface device structure 1070 * @pool: index for mac table 1071 * 1072 * Writes unicast address list to the RAR table. 1073 * Returns: -ENOMEM on failure/insufficient address space 1074 * 0 on no addresses written 1075 * X on writing X addresses to the RAR table 1076 **/ 1077 static int wx_write_uc_addr_list(struct net_device *netdev, int pool) 1078 { 1079 struct wx *wx = netdev_priv(netdev); 1080 int count = 0; 1081 1082 /* return ENOMEM indicating insufficient memory for addresses */ 1083 if (netdev_uc_count(netdev) > wx_available_rars(wx)) 1084 return -ENOMEM; 1085 1086 if (!netdev_uc_empty(netdev)) { 1087 struct netdev_hw_addr *ha; 1088 1089 netdev_for_each_uc_addr(ha, netdev) { 1090 wx_del_mac_filter(wx, ha->addr, pool); 1091 wx_add_mac_filter(wx, ha->addr, pool); 1092 count++; 1093 } 1094 } 1095 return count; 1096 } 1097 1098 /** 1099 * wx_mta_vector - Determines bit-vector in multicast table to set 1100 * @wx: pointer to private structure 1101 * @mc_addr: the multicast address 1102 * 1103 * Extracts the 12 bits, from a multicast address, to determine which 1104 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1105 * incoming rx multicast addresses, to determine the bit-vector to check in 1106 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1107 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1108 * to mc_filter_type. 1109 **/ 1110 static u32 wx_mta_vector(struct wx *wx, u8 *mc_addr) 1111 { 1112 u32 vector = 0; 1113 1114 switch (wx->mac.mc_filter_type) { 1115 case 0: /* use bits [47:36] of the address */ 1116 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1117 break; 1118 case 1: /* use bits [46:35] of the address */ 1119 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1120 break; 1121 case 2: /* use bits [45:34] of the address */ 1122 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1123 break; 1124 case 3: /* use bits [43:32] of the address */ 1125 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1126 break; 1127 default: /* Invalid mc_filter_type */ 1128 wx_err(wx, "MC filter type param set incorrectly\n"); 1129 break; 1130 } 1131 1132 /* vector can only be 12-bits or boundary will be exceeded */ 1133 vector &= 0xFFF; 1134 return vector; 1135 } 1136 1137 /** 1138 * wx_set_mta - Set bit-vector in multicast table 1139 * @wx: pointer to private structure 1140 * @mc_addr: Multicast address 1141 * 1142 * Sets the bit-vector in the multicast table. 1143 **/ 1144 static void wx_set_mta(struct wx *wx, u8 *mc_addr) 1145 { 1146 u32 vector, vector_bit, vector_reg; 1147 1148 wx->addr_ctrl.mta_in_use++; 1149 1150 vector = wx_mta_vector(wx, mc_addr); 1151 wx_dbg(wx, " bit-vector = 0x%03X\n", vector); 1152 1153 /* The MTA is a register array of 128 32-bit registers. It is treated 1154 * like an array of 4096 bits. We want to set bit 1155 * BitArray[vector_value]. So we figure out what register the bit is 1156 * in, read it, OR in the new bit, then write back the new value. The 1157 * register is determined by the upper 7 bits of the vector value and 1158 * the bit within that register are determined by the lower 5 bits of 1159 * the value. 1160 */ 1161 vector_reg = (vector >> 5) & 0x7F; 1162 vector_bit = vector & 0x1F; 1163 wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1164 } 1165 1166 /** 1167 * wx_update_mc_addr_list - Updates MAC list of multicast addresses 1168 * @wx: pointer to private structure 1169 * @netdev: pointer to net device structure 1170 * 1171 * The given list replaces any existing list. Clears the MC addrs from receive 1172 * address registers and the multicast table. Uses unused receive address 1173 * registers for the first multicast addresses, and hashes the rest into the 1174 * multicast table. 1175 **/ 1176 static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev) 1177 { 1178 struct netdev_hw_addr *ha; 1179 u32 i, psrctl; 1180 1181 /* Set the new number of MC addresses that we are being requested to 1182 * use. 1183 */ 1184 wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 1185 wx->addr_ctrl.mta_in_use = 0; 1186 1187 /* Clear mta_shadow */ 1188 wx_dbg(wx, " Clearing MTA\n"); 1189 memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow)); 1190 1191 /* Update mta_shadow */ 1192 netdev_for_each_mc_addr(ha, netdev) { 1193 wx_dbg(wx, " Adding the multicast addresses:\n"); 1194 wx_set_mta(wx, ha->addr); 1195 } 1196 1197 /* Enable mta */ 1198 for (i = 0; i < wx->mac.mcft_size; i++) 1199 wr32a(wx, WX_PSR_MC_TBL(0), i, 1200 wx->mac.mta_shadow[i]); 1201 1202 if (wx->addr_ctrl.mta_in_use > 0) { 1203 psrctl = rd32(wx, WX_PSR_CTL); 1204 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 1205 psrctl |= WX_PSR_CTL_MFE | 1206 (wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT); 1207 wr32(wx, WX_PSR_CTL, psrctl); 1208 } 1209 1210 wx_dbg(wx, "Update mc addr list Complete\n"); 1211 } 1212 1213 static void wx_restore_vf_multicasts(struct wx *wx) 1214 { 1215 u32 i, j, vector_bit, vector_reg; 1216 struct vf_data_storage *vfinfo; 1217 1218 for (i = 0; i < wx->num_vfs; i++) { 1219 u32 vmolr = rd32(wx, WX_PSR_VM_L2CTL(i)); 1220 1221 vfinfo = &wx->vfinfo[i]; 1222 for (j = 0; j < vfinfo->num_vf_mc_hashes; j++) { 1223 wx->addr_ctrl.mta_in_use++; 1224 vector_reg = WX_PSR_MC_TBL_REG(vfinfo->vf_mc_hashes[j]); 1225 vector_bit = WX_PSR_MC_TBL_BIT(vfinfo->vf_mc_hashes[j]); 1226 wr32m(wx, WX_PSR_MC_TBL(vector_reg), 1227 BIT(vector_bit), BIT(vector_bit)); 1228 /* errata 5: maintain a copy of the reg table conf */ 1229 wx->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 1230 } 1231 if (vfinfo->num_vf_mc_hashes) 1232 vmolr |= WX_PSR_VM_L2CTL_ROMPE; 1233 else 1234 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1235 wr32(wx, WX_PSR_VM_L2CTL(i), vmolr); 1236 } 1237 1238 /* Restore any VF macvlans */ 1239 wx_full_sync_mac_table(wx); 1240 } 1241 1242 /** 1243 * wx_write_mc_addr_list - write multicast addresses to MTA 1244 * @netdev: network interface device structure 1245 * 1246 * Writes multicast address list to the MTA hash table. 1247 * Returns: 0 on no addresses written 1248 * X on writing X addresses to MTA 1249 **/ 1250 static int wx_write_mc_addr_list(struct net_device *netdev) 1251 { 1252 struct wx *wx = netdev_priv(netdev); 1253 1254 if (!netif_running(netdev)) 1255 return 0; 1256 1257 wx_update_mc_addr_list(wx, netdev); 1258 1259 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1260 wx_restore_vf_multicasts(wx); 1261 1262 return netdev_mc_count(netdev); 1263 } 1264 1265 /** 1266 * wx_set_mac - Change the Ethernet Address of the NIC 1267 * @netdev: network interface device structure 1268 * @p: pointer to an address structure 1269 * 1270 * Returns 0 on success, negative on failure 1271 **/ 1272 int wx_set_mac(struct net_device *netdev, void *p) 1273 { 1274 struct wx *wx = netdev_priv(netdev); 1275 struct sockaddr *addr = p; 1276 int retval; 1277 1278 retval = eth_prepare_mac_addr_change(netdev, addr); 1279 if (retval) 1280 return retval; 1281 1282 wx_del_mac_filter(wx, wx->mac.addr, VMDQ_P(0)); 1283 eth_hw_addr_set(netdev, addr->sa_data); 1284 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len); 1285 1286 wx_mac_set_default_filter(wx, wx->mac.addr); 1287 1288 return 0; 1289 } 1290 EXPORT_SYMBOL(wx_set_mac); 1291 1292 void wx_disable_rx(struct wx *wx) 1293 { 1294 u32 pfdtxgswc; 1295 u32 rxctrl; 1296 1297 rxctrl = rd32(wx, WX_RDB_PB_CTL); 1298 if (rxctrl & WX_RDB_PB_CTL_RXEN) { 1299 pfdtxgswc = rd32(wx, WX_PSR_CTL); 1300 if (pfdtxgswc & WX_PSR_CTL_SW_EN) { 1301 pfdtxgswc &= ~WX_PSR_CTL_SW_EN; 1302 wr32(wx, WX_PSR_CTL, pfdtxgswc); 1303 wx->mac.set_lben = true; 1304 } else { 1305 wx->mac.set_lben = false; 1306 } 1307 rxctrl &= ~WX_RDB_PB_CTL_RXEN; 1308 wr32(wx, WX_RDB_PB_CTL, rxctrl); 1309 1310 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 1311 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 1312 /* disable mac receiver */ 1313 wr32m(wx, WX_MAC_RX_CFG, 1314 WX_MAC_RX_CFG_RE, 0); 1315 } 1316 } 1317 } 1318 EXPORT_SYMBOL(wx_disable_rx); 1319 1320 static void wx_enable_rx(struct wx *wx) 1321 { 1322 u32 psrctl; 1323 1324 /* enable mac receiver */ 1325 wr32m(wx, WX_MAC_RX_CFG, 1326 WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 1327 1328 wr32m(wx, WX_RDB_PB_CTL, 1329 WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN); 1330 1331 if (wx->mac.set_lben) { 1332 psrctl = rd32(wx, WX_PSR_CTL); 1333 psrctl |= WX_PSR_CTL_SW_EN; 1334 wr32(wx, WX_PSR_CTL, psrctl); 1335 wx->mac.set_lben = false; 1336 } 1337 } 1338 1339 /** 1340 * wx_set_rxpba - Initialize Rx packet buffer 1341 * @wx: pointer to private structure 1342 **/ 1343 static void wx_set_rxpba(struct wx *wx) 1344 { 1345 u32 rxpktsize, txpktsize, txpbthresh; 1346 u32 pbsize = wx->mac.rx_pb_size; 1347 1348 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 1349 if (test_bit(WX_FLAG_FDIR_HASH, wx->flags) || 1350 test_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 1351 pbsize -= 64; /* Default 64KB */ 1352 } 1353 1354 rxpktsize = pbsize << WX_RDB_PB_SZ_SHIFT; 1355 wr32(wx, WX_RDB_PB_SZ(0), rxpktsize); 1356 1357 /* Only support an equally distributed Tx packet buffer strategy. */ 1358 txpktsize = wx->mac.tx_pb_size; 1359 txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX; 1360 wr32(wx, WX_TDB_PB_SZ(0), txpktsize); 1361 wr32(wx, WX_TDM_PB_THRE(0), txpbthresh); 1362 } 1363 1364 #define WX_ETH_FRAMING 20 1365 1366 /** 1367 * wx_hpbthresh - calculate high water mark for flow control 1368 * 1369 * @wx: board private structure to calculate for 1370 **/ 1371 static int wx_hpbthresh(struct wx *wx) 1372 { 1373 struct net_device *dev = wx->netdev; 1374 int link, tc, kb, marker; 1375 u32 dv_id, rx_pba; 1376 1377 /* Calculate max LAN frame size */ 1378 link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + WX_ETH_FRAMING; 1379 tc = link; 1380 1381 /* Calculate delay value for device */ 1382 dv_id = WX_DV(link, tc); 1383 1384 /* Loopback switch introduces additional latency */ 1385 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1386 dv_id += WX_B2BT(tc); 1387 1388 /* Delay value is calculated in bit times convert to KB */ 1389 kb = WX_BT2KB(dv_id); 1390 rx_pba = rd32(wx, WX_RDB_PB_SZ(0)) >> WX_RDB_PB_SZ_SHIFT; 1391 1392 marker = rx_pba - kb; 1393 1394 /* It is possible that the packet buffer is not large enough 1395 * to provide required headroom. In this case throw an error 1396 * to user and a do the best we can. 1397 */ 1398 if (marker < 0) { 1399 dev_warn(&wx->pdev->dev, 1400 "Packet Buffer can not provide enough headroom to support flow control. Decrease MTU or number of traffic classes\n"); 1401 marker = tc + 1; 1402 } 1403 1404 return marker; 1405 } 1406 1407 /** 1408 * wx_lpbthresh - calculate low water mark for flow control 1409 * 1410 * @wx: board private structure to calculate for 1411 **/ 1412 static int wx_lpbthresh(struct wx *wx) 1413 { 1414 struct net_device *dev = wx->netdev; 1415 u32 dv_id; 1416 int tc; 1417 1418 /* Calculate max LAN frame size */ 1419 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 1420 1421 /* Calculate delay value for device */ 1422 dv_id = WX_LOW_DV(tc); 1423 1424 /* Delay value is calculated in bit times convert to KB */ 1425 return WX_BT2KB(dv_id); 1426 } 1427 1428 /** 1429 * wx_pbthresh_setup - calculate and setup high low water marks 1430 * 1431 * @wx: board private structure to calculate for 1432 **/ 1433 static void wx_pbthresh_setup(struct wx *wx) 1434 { 1435 wx->fc.high_water = wx_hpbthresh(wx); 1436 wx->fc.low_water = wx_lpbthresh(wx); 1437 1438 /* Low water marks must not be larger than high water marks */ 1439 if (wx->fc.low_water > wx->fc.high_water) 1440 wx->fc.low_water = 0; 1441 } 1442 1443 static void wx_set_ethertype_anti_spoofing(struct wx *wx, bool enable, int vf) 1444 { 1445 u32 pfvfspoof, reg_offset, vf_shift; 1446 1447 vf_shift = WX_VF_IND_SHIFT(vf); 1448 reg_offset = WX_VF_REG_OFFSET(vf); 1449 1450 pfvfspoof = rd32(wx, WX_TDM_ETYPE_AS(reg_offset)); 1451 if (enable) 1452 pfvfspoof |= BIT(vf_shift); 1453 else 1454 pfvfspoof &= ~BIT(vf_shift); 1455 wr32(wx, WX_TDM_ETYPE_AS(reg_offset), pfvfspoof); 1456 } 1457 1458 int wx_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting) 1459 { 1460 u32 index = WX_VF_REG_OFFSET(vf), vf_bit = WX_VF_IND_SHIFT(vf); 1461 struct wx *wx = netdev_priv(netdev); 1462 u32 regval; 1463 1464 if (vf >= wx->num_vfs) 1465 return -EINVAL; 1466 1467 wx->vfinfo[vf].spoofchk_enabled = setting; 1468 1469 regval = (setting << vf_bit); 1470 wr32m(wx, WX_TDM_MAC_AS(index), regval | BIT(vf_bit), regval); 1471 1472 if (wx->vfinfo[vf].vlan_count) 1473 wr32m(wx, WX_TDM_VLAN_AS(index), regval | BIT(vf_bit), regval); 1474 1475 return 0; 1476 } 1477 1478 static void wx_configure_virtualization(struct wx *wx) 1479 { 1480 u16 pool = wx->num_rx_pools; 1481 u32 reg_offset, vf_shift; 1482 u32 i; 1483 1484 if (!test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1485 return; 1486 1487 wr32m(wx, WX_PSR_VM_CTL, 1488 WX_PSR_VM_CTL_POOL_MASK | WX_PSR_VM_CTL_REPLEN, 1489 FIELD_PREP(WX_PSR_VM_CTL_POOL_MASK, VMDQ_P(0)) | 1490 WX_PSR_VM_CTL_REPLEN); 1491 while (pool--) 1492 wr32m(wx, WX_PSR_VM_L2CTL(pool), 1493 WX_PSR_VM_L2CTL_AUPE, WX_PSR_VM_L2CTL_AUPE); 1494 1495 if (!test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1496 vf_shift = BIT(VMDQ_P(0)); 1497 /* Enable only the PF pools for Tx/Rx */ 1498 wr32(wx, WX_RDM_VF_RE(0), vf_shift); 1499 wr32(wx, WX_TDM_VF_TE(0), vf_shift); 1500 } else { 1501 vf_shift = WX_VF_IND_SHIFT(VMDQ_P(0)); 1502 reg_offset = WX_VF_REG_OFFSET(VMDQ_P(0)); 1503 1504 /* Enable only the PF pools for Tx/Rx */ 1505 wr32(wx, WX_RDM_VF_RE(reg_offset), GENMASK(31, vf_shift)); 1506 wr32(wx, WX_RDM_VF_RE(reg_offset ^ 1), reg_offset - 1); 1507 wr32(wx, WX_TDM_VF_TE(reg_offset), GENMASK(31, vf_shift)); 1508 wr32(wx, WX_TDM_VF_TE(reg_offset ^ 1), reg_offset - 1); 1509 } 1510 1511 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1512 clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1513 1514 for (i = 0; i < wx->num_vfs; i++) { 1515 if (!wx->vfinfo[i].spoofchk_enabled) 1516 wx_set_vf_spoofchk(wx->netdev, i, false); 1517 /* enable ethertype anti spoofing if hw supports it */ 1518 wx_set_ethertype_anti_spoofing(wx, true, i); 1519 } 1520 } 1521 1522 static void wx_configure_port(struct wx *wx) 1523 { 1524 u32 value, i; 1525 1526 if (!test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1527 value = (wx->num_vfs == 0) ? 1528 WX_CFG_PORT_CTL_NUM_VT_NONE : 1529 WX_CFG_PORT_CTL_NUM_VT_8; 1530 } else { 1531 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) { 1532 if (wx->ring_feature[RING_F_RSS].indices == 4) 1533 value = WX_CFG_PORT_CTL_NUM_VT_32; 1534 else 1535 value = WX_CFG_PORT_CTL_NUM_VT_64; 1536 } else { 1537 value = 0; 1538 } 1539 } 1540 1541 value |= WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ; 1542 wr32m(wx, WX_CFG_PORT_CTL, 1543 WX_CFG_PORT_CTL_NUM_VT_MASK | 1544 WX_CFG_PORT_CTL_D_VLAN | 1545 WX_CFG_PORT_CTL_QINQ, 1546 value); 1547 1548 wr32(wx, WX_CFG_TAG_TPID(0), 1549 ETH_P_8021Q | ETH_P_8021AD << 16); 1550 wx->tpid[0] = ETH_P_8021Q; 1551 wx->tpid[1] = ETH_P_8021AD; 1552 for (i = 1; i < 4; i++) 1553 wr32(wx, WX_CFG_TAG_TPID(i), 1554 ETH_P_8021Q | ETH_P_8021Q << 16); 1555 for (i = 2; i < 8; i++) 1556 wx->tpid[i] = ETH_P_8021Q; 1557 } 1558 1559 /** 1560 * wx_disable_sec_rx_path - Stops the receive data path 1561 * @wx: pointer to private structure 1562 * 1563 * Stops the receive data path and waits for the HW to internally empty 1564 * the Rx security block 1565 **/ 1566 int wx_disable_sec_rx_path(struct wx *wx) 1567 { 1568 u32 secrx; 1569 1570 wr32m(wx, WX_RSC_CTL, 1571 WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS); 1572 1573 return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY, 1574 1000, 40000, false, wx, WX_RSC_ST); 1575 } 1576 EXPORT_SYMBOL(wx_disable_sec_rx_path); 1577 1578 /** 1579 * wx_enable_sec_rx_path - Enables the receive data path 1580 * @wx: pointer to private structure 1581 * 1582 * Enables the receive data path. 1583 **/ 1584 void wx_enable_sec_rx_path(struct wx *wx) 1585 { 1586 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0); 1587 WX_WRITE_FLUSH(wx); 1588 } 1589 EXPORT_SYMBOL(wx_enable_sec_rx_path); 1590 1591 static void wx_vlan_strip_control(struct wx *wx, bool enable) 1592 { 1593 int i, j; 1594 1595 for (i = 0; i < wx->num_rx_queues; i++) { 1596 struct wx_ring *ring = wx->rx_ring[i]; 1597 1598 j = ring->reg_idx; 1599 wr32m(wx, WX_PX_RR_CFG(j), WX_PX_RR_CFG_VLAN, 1600 enable ? WX_PX_RR_CFG_VLAN : 0); 1601 } 1602 } 1603 1604 static void wx_vlan_promisc_enable(struct wx *wx) 1605 { 1606 u32 vlnctrl, i, vind, bits, reg_idx; 1607 1608 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1609 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) { 1610 /* we need to keep the VLAN filter on in SRIOV */ 1611 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1612 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1613 } else { 1614 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1615 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1616 return; 1617 } 1618 /* We are already in VLAN promisc, nothing to do */ 1619 if (test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) 1620 return; 1621 /* Set flag so we don't redo unnecessary work */ 1622 set_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1623 /* Add PF to all active pools */ 1624 for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) { 1625 wr32(wx, WX_PSR_VLAN_SWC_IDX, i); 1626 vind = WX_VF_IND_SHIFT(VMDQ_P(0)); 1627 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); 1628 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); 1629 bits |= BIT(vind); 1630 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); 1631 } 1632 /* Set all bits in the VLAN filter table array */ 1633 for (i = 0; i < wx->mac.vft_size; i++) 1634 wr32(wx, WX_PSR_VLAN_TBL(i), U32_MAX); 1635 } 1636 1637 static void wx_scrub_vfta(struct wx *wx) 1638 { 1639 u32 i, vid, bits, vfta, vind, vlvf, reg_idx; 1640 1641 for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) { 1642 wr32(wx, WX_PSR_VLAN_SWC_IDX, i); 1643 vlvf = rd32(wx, WX_PSR_VLAN_SWC_IDX); 1644 /* pull VLAN ID from VLVF */ 1645 vid = vlvf & ~WX_PSR_VLAN_SWC_VIEN; 1646 if (vlvf & WX_PSR_VLAN_SWC_VIEN) { 1647 /* if PF is part of this then continue */ 1648 if (test_bit(vid, wx->active_vlans)) 1649 continue; 1650 } 1651 /* remove PF from the pool */ 1652 vind = WX_VF_IND_SHIFT(VMDQ_P(0)); 1653 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); 1654 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); 1655 bits &= ~BIT(vind); 1656 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); 1657 } 1658 /* extract values from vft_shadow and write back to VFTA */ 1659 for (i = 0; i < wx->mac.vft_size; i++) { 1660 vfta = wx->mac.vft_shadow[i]; 1661 wr32(wx, WX_PSR_VLAN_TBL(i), vfta); 1662 } 1663 } 1664 1665 static void wx_vlan_promisc_disable(struct wx *wx) 1666 { 1667 u32 vlnctrl; 1668 1669 /* configure vlan filtering */ 1670 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1671 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1672 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1673 /* We are not in VLAN promisc, nothing to do */ 1674 if (!test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) 1675 return; 1676 /* Set flag so we don't redo unnecessary work */ 1677 clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1678 wx_scrub_vfta(wx); 1679 } 1680 1681 void wx_set_rx_mode(struct net_device *netdev) 1682 { 1683 struct wx *wx = netdev_priv(netdev); 1684 netdev_features_t features; 1685 u32 fctrl, vmolr, vlnctrl; 1686 int count; 1687 1688 features = netdev->features; 1689 1690 /* Check for Promiscuous and All Multicast modes */ 1691 fctrl = rd32(wx, WX_PSR_CTL); 1692 fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE); 1693 vmolr = rd32(wx, WX_PSR_VM_L2CTL(VMDQ_P(0))); 1694 vmolr &= ~(WX_PSR_VM_L2CTL_UPE | 1695 WX_PSR_VM_L2CTL_MPE | 1696 WX_PSR_VM_L2CTL_ROPE | 1697 WX_PSR_VM_L2CTL_ROMPE); 1698 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1699 vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN); 1700 1701 /* set all bits that we expect to always be set */ 1702 fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE; 1703 vmolr |= WX_PSR_VM_L2CTL_BAM | 1704 WX_PSR_VM_L2CTL_AUPE | 1705 WX_PSR_VM_L2CTL_VACC; 1706 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1707 1708 wx->addr_ctrl.user_set_promisc = false; 1709 if (netdev->flags & IFF_PROMISC) { 1710 wx->addr_ctrl.user_set_promisc = true; 1711 fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE; 1712 /* pf don't want packets routing to vf, so clear UPE */ 1713 vmolr |= WX_PSR_VM_L2CTL_MPE; 1714 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags) && 1715 test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1716 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1717 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 1718 } 1719 1720 if (netdev->flags & IFF_ALLMULTI) { 1721 fctrl |= WX_PSR_CTL_MPE; 1722 vmolr |= WX_PSR_VM_L2CTL_MPE; 1723 } 1724 1725 if (netdev->features & NETIF_F_RXALL) { 1726 vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE); 1727 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1728 /* receive bad packets */ 1729 wr32m(wx, WX_RSC_CTL, 1730 WX_RSC_CTL_SAVE_MAC_ERR, 1731 WX_RSC_CTL_SAVE_MAC_ERR); 1732 } else { 1733 vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE; 1734 } 1735 1736 /* Write addresses to available RAR registers, if there is not 1737 * sufficient space to store all the addresses then enable 1738 * unicast promiscuous mode 1739 */ 1740 count = wx_write_uc_addr_list(netdev, VMDQ_P(0)); 1741 if (count < 0) { 1742 vmolr &= ~WX_PSR_VM_L2CTL_ROPE; 1743 vmolr |= WX_PSR_VM_L2CTL_UPE; 1744 } 1745 1746 /* Write addresses to the MTA, if the attempt fails 1747 * then we should just turn on promiscuous mode so 1748 * that we can at least receive multicast traffic 1749 */ 1750 count = wx_write_mc_addr_list(netdev); 1751 if (count < 0) { 1752 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1753 vmolr |= WX_PSR_VM_L2CTL_MPE; 1754 } 1755 1756 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1757 wr32(wx, WX_PSR_CTL, fctrl); 1758 wr32(wx, WX_PSR_VM_L2CTL(VMDQ_P(0)), vmolr); 1759 1760 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && 1761 (features & NETIF_F_HW_VLAN_STAG_RX)) 1762 wx_vlan_strip_control(wx, true); 1763 else 1764 wx_vlan_strip_control(wx, false); 1765 1766 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1767 wx_vlan_promisc_disable(wx); 1768 else 1769 wx_vlan_promisc_enable(wx); 1770 } 1771 EXPORT_SYMBOL(wx_set_rx_mode); 1772 1773 static void wx_set_rx_buffer_len(struct wx *wx) 1774 { 1775 struct net_device *netdev = wx->netdev; 1776 u32 mhadd, max_frame; 1777 1778 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 1779 /* adjust max frame to be at least the size of a standard frame */ 1780 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 1781 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 1782 1783 mhadd = rd32(wx, WX_PSR_MAX_SZ); 1784 if (max_frame != mhadd) 1785 wr32(wx, WX_PSR_MAX_SZ, max_frame); 1786 } 1787 1788 /** 1789 * wx_change_mtu - Change the Maximum Transfer Unit 1790 * @netdev: network interface device structure 1791 * @new_mtu: new value for maximum frame size 1792 * 1793 * Returns 0 on success, negative on failure 1794 **/ 1795 int wx_change_mtu(struct net_device *netdev, int new_mtu) 1796 { 1797 struct wx *wx = netdev_priv(netdev); 1798 1799 WRITE_ONCE(netdev->mtu, new_mtu); 1800 wx_set_rx_buffer_len(wx); 1801 1802 return 0; 1803 } 1804 EXPORT_SYMBOL(wx_change_mtu); 1805 1806 /* Disable the specified rx queue */ 1807 void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring) 1808 { 1809 u8 reg_idx = ring->reg_idx; 1810 u32 rxdctl; 1811 int ret; 1812 1813 /* write value back with RRCFG.EN bit cleared */ 1814 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1815 WX_PX_RR_CFG_RR_EN, 0); 1816 1817 /* the hardware may take up to 100us to really disable the rx queue */ 1818 ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN), 1819 10, 100, true, wx, WX_PX_RR_CFG(reg_idx)); 1820 1821 if (ret == -ETIMEDOUT) { 1822 /* Just for information */ 1823 wx_err(wx, 1824 "RRCFG.EN on Rx queue %d not cleared within the polling period\n", 1825 reg_idx); 1826 } 1827 } 1828 EXPORT_SYMBOL(wx_disable_rx_queue); 1829 1830 static void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring) 1831 { 1832 u8 reg_idx = ring->reg_idx; 1833 u32 rxdctl; 1834 int ret; 1835 1836 ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN, 1837 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx)); 1838 1839 if (ret == -ETIMEDOUT) { 1840 /* Just for information */ 1841 wx_err(wx, 1842 "RRCFG.EN on Rx queue %d not set within the polling period\n", 1843 reg_idx); 1844 } 1845 } 1846 1847 static void wx_configure_srrctl(struct wx *wx, 1848 struct wx_ring *rx_ring) 1849 { 1850 u16 reg_idx = rx_ring->reg_idx; 1851 u32 srrctl; 1852 1853 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1854 srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ | 1855 WX_PX_RR_CFG_RR_BUF_SZ | 1856 WX_PX_RR_CFG_SPLIT_MODE); 1857 /* configure header buffer length, needed for RSC */ 1858 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT; 1859 1860 /* configure the packet buffer length */ 1861 srrctl |= WX_RX_BUFSZ >> WX_PX_RR_CFG_BSIZEPKT_SHIFT; 1862 1863 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 1864 } 1865 1866 static void wx_configure_tx_ring(struct wx *wx, 1867 struct wx_ring *ring) 1868 { 1869 u32 txdctl = WX_PX_TR_CFG_ENABLE; 1870 u8 reg_idx = ring->reg_idx; 1871 u64 tdba = ring->dma; 1872 int ret; 1873 1874 /* disable queue to avoid issues while updating state */ 1875 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); 1876 WX_WRITE_FLUSH(wx); 1877 1878 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32)); 1879 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba)); 1880 1881 /* reset head and tail pointers */ 1882 wr32(wx, WX_PX_TR_RP(reg_idx), 0); 1883 wr32(wx, WX_PX_TR_WP(reg_idx), 0); 1884 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx); 1885 1886 if (ring->count < WX_MAX_TXD) 1887 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT; 1888 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT; 1889 1890 ring->atr_count = 0; 1891 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && 1892 test_bit(WX_FLAG_FDIR_HASH, wx->flags)) 1893 ring->atr_sample_rate = wx->atr_sample_rate; 1894 else 1895 ring->atr_sample_rate = 0; 1896 1897 /* reinitialize tx_buffer_info */ 1898 memset(ring->tx_buffer_info, 0, 1899 sizeof(struct wx_tx_buffer) * ring->count); 1900 1901 /* enable queue */ 1902 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl); 1903 1904 /* poll to verify queue is enabled */ 1905 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE, 1906 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx)); 1907 if (ret == -ETIMEDOUT) 1908 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx); 1909 } 1910 1911 static void wx_configure_rx_ring(struct wx *wx, 1912 struct wx_ring *ring) 1913 { 1914 u16 reg_idx = ring->reg_idx; 1915 u64 rdba = ring->dma; 1916 u32 rxdctl; 1917 1918 /* disable queue to avoid issues while updating state */ 1919 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1920 wx_disable_rx_queue(wx, ring); 1921 1922 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32)); 1923 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba)); 1924 1925 if (ring->count == WX_MAX_RXD) 1926 rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1927 else 1928 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1929 1930 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT; 1931 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl); 1932 1933 /* reset head and tail pointers */ 1934 wr32(wx, WX_PX_RR_RP(reg_idx), 0); 1935 wr32(wx, WX_PX_RR_WP(reg_idx), 0); 1936 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx); 1937 1938 wx_configure_srrctl(wx, ring); 1939 1940 /* initialize rx_buffer_info */ 1941 memset(ring->rx_buffer_info, 0, 1942 sizeof(struct wx_rx_buffer) * ring->count); 1943 1944 /* reset ntu and ntc to place SW in sync with hardware */ 1945 ring->next_to_clean = 0; 1946 ring->next_to_use = 0; 1947 1948 /* enable receive descriptor ring */ 1949 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1950 WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN); 1951 1952 wx_enable_rx_queue(wx, ring); 1953 wx_alloc_rx_buffers(ring, wx_desc_unused(ring)); 1954 } 1955 1956 /** 1957 * wx_configure_tx - Configure Transmit Unit after Reset 1958 * @wx: pointer to private structure 1959 * 1960 * Configure the Tx unit of the MAC after a reset. 1961 **/ 1962 static void wx_configure_tx(struct wx *wx) 1963 { 1964 u32 i; 1965 1966 /* TDM_CTL.TE must be before Tx queues are enabled */ 1967 wr32m(wx, WX_TDM_CTL, 1968 WX_TDM_CTL_TE, WX_TDM_CTL_TE); 1969 1970 /* Setup the HW Tx Head and Tail descriptor pointers */ 1971 for (i = 0; i < wx->num_tx_queues; i++) 1972 wx_configure_tx_ring(wx, wx->tx_ring[i]); 1973 1974 wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10); 1975 1976 if (wx->mac.type == wx_mac_em) 1977 wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1); 1978 1979 /* enable mac transmitter */ 1980 wr32m(wx, WX_MAC_TX_CFG, 1981 WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE); 1982 } 1983 1984 static void wx_restore_vlan(struct wx *wx) 1985 { 1986 u16 vid = 1; 1987 1988 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), 0); 1989 1990 for_each_set_bit_from(vid, wx->active_vlans, VLAN_N_VID) 1991 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), vid); 1992 } 1993 1994 static void wx_store_reta(struct wx *wx) 1995 { 1996 u8 *indir_tbl = wx->rss_indir_tbl; 1997 u32 reta = 0; 1998 u32 i; 1999 2000 /* Fill out the redirection table as follows: 2001 * - 8 bit wide entries containing 4 bit RSS index 2002 */ 2003 for (i = 0; i < WX_MAX_RETA_ENTRIES; i++) { 2004 reta |= indir_tbl[i] << (i & 0x3) * 8; 2005 if ((i & 3) == 3) { 2006 wr32(wx, WX_RDB_RSSTBL(i >> 2), reta); 2007 reta = 0; 2008 } 2009 } 2010 } 2011 2012 static void wx_setup_reta(struct wx *wx) 2013 { 2014 u16 rss_i = wx->ring_feature[RING_F_RSS].indices; 2015 u32 random_key_size = WX_RSS_KEY_SIZE / 4; 2016 u32 i, j; 2017 2018 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) { 2019 if (wx->mac.type == wx_mac_em) 2020 rss_i = 1; 2021 else 2022 rss_i = rss_i < 4 ? 4 : rss_i; 2023 } 2024 2025 /* Fill out hash function seeds */ 2026 for (i = 0; i < random_key_size; i++) 2027 wr32(wx, WX_RDB_RSSRK(i), wx->rss_key[i]); 2028 2029 /* Fill out redirection table */ 2030 memset(wx->rss_indir_tbl, 0, sizeof(wx->rss_indir_tbl)); 2031 2032 for (i = 0, j = 0; i < WX_MAX_RETA_ENTRIES; i++, j++) { 2033 if (j == rss_i) 2034 j = 0; 2035 2036 wx->rss_indir_tbl[i] = j; 2037 } 2038 2039 wx_store_reta(wx); 2040 } 2041 2042 #define WX_RDB_RSS_PL_2 FIELD_PREP(GENMASK(31, 29), 1) 2043 #define WX_RDB_RSS_PL_4 FIELD_PREP(GENMASK(31, 29), 2) 2044 static void wx_setup_psrtype(struct wx *wx) 2045 { 2046 int rss_i = wx->ring_feature[RING_F_RSS].indices; 2047 u32 psrtype; 2048 int pool; 2049 2050 psrtype = WX_RDB_PL_CFG_L4HDR | 2051 WX_RDB_PL_CFG_L3HDR | 2052 WX_RDB_PL_CFG_L2HDR | 2053 WX_RDB_PL_CFG_TUN_OUTL2HDR | 2054 WX_RDB_PL_CFG_TUN_TUNHDR; 2055 2056 if (!test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2057 for_each_set_bit(pool, &wx->fwd_bitmask, 8) 2058 wr32(wx, WX_RDB_PL_CFG(VMDQ_P(pool)), psrtype); 2059 } else { 2060 if (rss_i > 3) 2061 psrtype |= WX_RDB_RSS_PL_4; 2062 else if (rss_i > 1) 2063 psrtype |= WX_RDB_RSS_PL_2; 2064 2065 for_each_set_bit(pool, &wx->fwd_bitmask, 32) 2066 wr32(wx, WX_RDB_PL_CFG(VMDQ_P(pool)), psrtype); 2067 } 2068 } 2069 2070 static void wx_setup_mrqc(struct wx *wx) 2071 { 2072 u32 rss_field = 0; 2073 2074 /* VT, and RSS do not coexist at the same time */ 2075 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) 2076 return; 2077 2078 /* Disable indicating checksum in descriptor, enables RSS hash */ 2079 wr32m(wx, WX_PSR_CTL, WX_PSR_CTL_PCSD, WX_PSR_CTL_PCSD); 2080 2081 /* Perform hash on these packet types */ 2082 rss_field = WX_RDB_RA_CTL_RSS_IPV4 | 2083 WX_RDB_RA_CTL_RSS_IPV4_TCP | 2084 WX_RDB_RA_CTL_RSS_IPV4_UDP | 2085 WX_RDB_RA_CTL_RSS_IPV6 | 2086 WX_RDB_RA_CTL_RSS_IPV6_TCP | 2087 WX_RDB_RA_CTL_RSS_IPV6_UDP; 2088 2089 netdev_rss_key_fill(wx->rss_key, sizeof(wx->rss_key)); 2090 2091 wx_setup_reta(wx); 2092 2093 if (wx->rss_enabled) 2094 rss_field |= WX_RDB_RA_CTL_RSS_EN; 2095 2096 wr32(wx, WX_RDB_RA_CTL, rss_field); 2097 } 2098 2099 /** 2100 * wx_configure_rx - Configure Receive Unit after Reset 2101 * @wx: pointer to private structure 2102 * 2103 * Configure the Rx unit of the MAC after a reset. 2104 **/ 2105 void wx_configure_rx(struct wx *wx) 2106 { 2107 int ret; 2108 u32 i; 2109 2110 wx_disable_rx(wx); 2111 wx_setup_psrtype(wx); 2112 2113 /* enable hw crc stripping */ 2114 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP); 2115 2116 if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 2117 u32 psrctl; 2118 2119 /* RSC Setup */ 2120 psrctl = rd32(wx, WX_PSR_CTL); 2121 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */ 2122 psrctl |= WX_PSR_CTL_RSC_DIS; 2123 wr32(wx, WX_PSR_CTL, psrctl); 2124 } 2125 2126 wx_setup_mrqc(wx); 2127 2128 /* set_rx_buffer_len must be called before ring initialization */ 2129 wx_set_rx_buffer_len(wx); 2130 2131 /* Setup the HW Rx Head and Tail Descriptor Pointers and 2132 * the Base and Length of the Rx Descriptor Ring 2133 */ 2134 for (i = 0; i < wx->num_rx_queues; i++) 2135 wx_configure_rx_ring(wx, wx->rx_ring[i]); 2136 2137 /* Enable all receives, disable security engine prior to block traffic */ 2138 ret = wx_disable_sec_rx_path(wx); 2139 if (ret < 0) 2140 wx_err(wx, "The register status is abnormal, please check device."); 2141 2142 wx_enable_rx(wx); 2143 wx_enable_sec_rx_path(wx); 2144 } 2145 EXPORT_SYMBOL(wx_configure_rx); 2146 2147 static void wx_configure_isb(struct wx *wx) 2148 { 2149 /* set ISB Address */ 2150 wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32)); 2151 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 2152 wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma)); 2153 } 2154 2155 void wx_configure(struct wx *wx) 2156 { 2157 wx_set_rxpba(wx); 2158 wx_pbthresh_setup(wx); 2159 wx_configure_virtualization(wx); 2160 wx_configure_port(wx); 2161 2162 wx_set_rx_mode(wx->netdev); 2163 wx_restore_vlan(wx); 2164 2165 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) 2166 wx->configure_fdir(wx); 2167 2168 wx_configure_tx(wx); 2169 wx_configure_rx(wx); 2170 wx_configure_isb(wx); 2171 } 2172 EXPORT_SYMBOL(wx_configure); 2173 2174 /** 2175 * wx_disable_pcie_master - Disable PCI-express master access 2176 * @wx: pointer to hardware structure 2177 * 2178 * Disables PCI-Express master access and verifies there are no pending 2179 * requests. 2180 **/ 2181 int wx_disable_pcie_master(struct wx *wx) 2182 { 2183 int status = 0; 2184 u32 val; 2185 2186 /* Always set this bit to ensure any future transactions are blocked */ 2187 pci_clear_master(wx->pdev); 2188 2189 /* Exit if master requests are blocked */ 2190 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING))) 2191 return 0; 2192 2193 /* Poll for master request bit to clear */ 2194 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, 2195 false, wx, WX_PX_TRANSACTION_PENDING); 2196 if (status < 0) 2197 wx_err(wx, "PCIe transaction pending bit did not clear.\n"); 2198 2199 return status; 2200 } 2201 EXPORT_SYMBOL(wx_disable_pcie_master); 2202 2203 /** 2204 * wx_stop_adapter - Generic stop Tx/Rx units 2205 * @wx: pointer to hardware structure 2206 * 2207 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, 2208 * disables transmit and receive units. The adapter_stopped flag is used by 2209 * the shared code and drivers to determine if the adapter is in a stopped 2210 * state and should not touch the hardware. 2211 **/ 2212 int wx_stop_adapter(struct wx *wx) 2213 { 2214 u16 i; 2215 2216 /* Set the adapter_stopped flag so other driver functions stop touching 2217 * the hardware 2218 */ 2219 wx->adapter_stopped = true; 2220 2221 /* Disable the receive unit */ 2222 wx_disable_rx(wx); 2223 2224 /* Set interrupt mask to stop interrupts from being generated */ 2225 wx_intr_disable(wx, WX_INTR_ALL); 2226 2227 /* Clear any pending interrupts, flush previous writes */ 2228 wr32(wx, WX_PX_MISC_IC, 0xffffffff); 2229 wr32(wx, WX_BME_CTL, 0x3); 2230 2231 /* Disable the transmit unit. Each queue must be disabled. */ 2232 for (i = 0; i < wx->mac.max_tx_queues; i++) { 2233 wr32m(wx, WX_PX_TR_CFG(i), 2234 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE, 2235 WX_PX_TR_CFG_SWFLSH); 2236 } 2237 2238 /* Disable the receive unit by stopping each queue */ 2239 for (i = 0; i < wx->mac.max_rx_queues; i++) { 2240 wr32m(wx, WX_PX_RR_CFG(i), 2241 WX_PX_RR_CFG_RR_EN, 0); 2242 } 2243 2244 /* flush all queues disables */ 2245 WX_WRITE_FLUSH(wx); 2246 2247 /* Prevent the PCI-E bus from hanging by disabling PCI-E master 2248 * access and verify no pending requests 2249 */ 2250 return wx_disable_pcie_master(wx); 2251 } 2252 EXPORT_SYMBOL(wx_stop_adapter); 2253 2254 void wx_reset_mac(struct wx *wx) 2255 { 2256 /* receive packets that size > 2048 */ 2257 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE); 2258 2259 /* clear counters on read */ 2260 wr32m(wx, WX_MMC_CONTROL, 2261 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD); 2262 2263 wr32m(wx, WX_MAC_RX_FLOW_CTRL, 2264 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE); 2265 2266 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 2267 } 2268 EXPORT_SYMBOL(wx_reset_mac); 2269 2270 void wx_reset_misc(struct wx *wx) 2271 { 2272 int i; 2273 2274 wx_reset_mac(wx); 2275 2276 wr32m(wx, WX_MIS_RST_ST, 2277 WX_MIS_RST_ST_RST_INIT, 0x1E00); 2278 2279 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 2280 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0); 2281 for (i = 0; i < 16; i++) { 2282 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0); 2283 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0); 2284 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0); 2285 } 2286 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0); 2287 for (i = 0; i < 16; i++) { 2288 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0); 2289 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0); 2290 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0); 2291 } 2292 2293 /* set pause frame dst mac addr */ 2294 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001); 2295 wr32(wx, WX_RDB_PFCMACDAH, 0x0180); 2296 } 2297 EXPORT_SYMBOL(wx_reset_misc); 2298 2299 /** 2300 * wx_get_pcie_msix_counts - Gets MSI-X vector count 2301 * @wx: pointer to hardware structure 2302 * @msix_count: number of MSI interrupts that can be obtained 2303 * @max_msix_count: number of MSI interrupts that mac need 2304 * 2305 * Read PCIe configuration space, and get the MSI-X vector count from 2306 * the capabilities table. 2307 **/ 2308 int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count) 2309 { 2310 struct pci_dev *pdev = wx->pdev; 2311 struct device *dev = &pdev->dev; 2312 int pos; 2313 2314 *msix_count = 1; 2315 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 2316 if (!pos) { 2317 dev_err(dev, "Unable to find MSI-X Capabilities\n"); 2318 return -EINVAL; 2319 } 2320 pci_read_config_word(pdev, 2321 pos + PCI_MSIX_FLAGS, 2322 msix_count); 2323 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; 2324 /* MSI-X count is zero-based in HW */ 2325 *msix_count += 1; 2326 2327 if (*msix_count > max_msix_count) 2328 *msix_count = max_msix_count; 2329 2330 return 0; 2331 } 2332 EXPORT_SYMBOL(wx_get_pcie_msix_counts); 2333 2334 /** 2335 * wx_init_rss_key - Initialize wx RSS key 2336 * @wx: device handle 2337 * 2338 * Allocates and initializes the RSS key if it is not allocated. 2339 **/ 2340 static int wx_init_rss_key(struct wx *wx) 2341 { 2342 u32 *rss_key; 2343 2344 if (!wx->rss_key) { 2345 rss_key = kzalloc(WX_RSS_KEY_SIZE, GFP_KERNEL); 2346 if (unlikely(!rss_key)) 2347 return -ENOMEM; 2348 2349 netdev_rss_key_fill(rss_key, WX_RSS_KEY_SIZE); 2350 wx->rss_key = rss_key; 2351 } 2352 2353 return 0; 2354 } 2355 2356 int wx_sw_init(struct wx *wx) 2357 { 2358 struct pci_dev *pdev = wx->pdev; 2359 u32 ssid = 0; 2360 int err = 0; 2361 2362 wx->vendor_id = pdev->vendor; 2363 wx->device_id = pdev->device; 2364 wx->revision_id = pdev->revision; 2365 wx->oem_svid = pdev->subsystem_vendor; 2366 wx->oem_ssid = pdev->subsystem_device; 2367 wx->bus.device = PCI_SLOT(pdev->devfn); 2368 wx->bus.func = PCI_FUNC(pdev->devfn); 2369 2370 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN) { 2371 wx->subsystem_vendor_id = pdev->subsystem_vendor; 2372 wx->subsystem_device_id = pdev->subsystem_device; 2373 } else { 2374 err = wx_flash_read_dword(wx, 0xfffdc, &ssid); 2375 if (err < 0) { 2376 wx_err(wx, "read of internal subsystem device id failed\n"); 2377 return err; 2378 } 2379 2380 wx->subsystem_device_id = swab16((u16)ssid); 2381 } 2382 2383 err = wx_init_rss_key(wx); 2384 if (err < 0) { 2385 wx_err(wx, "rss key allocation failed\n"); 2386 return err; 2387 } 2388 2389 wx->mac_table = kcalloc(wx->mac.num_rar_entries, 2390 sizeof(struct wx_mac_addr), 2391 GFP_KERNEL); 2392 if (!wx->mac_table) { 2393 wx_err(wx, "mac_table allocation failed\n"); 2394 kfree(wx->rss_key); 2395 return -ENOMEM; 2396 } 2397 2398 bitmap_zero(wx->state, WX_STATE_NBITS); 2399 bitmap_zero(wx->flags, WX_PF_FLAGS_NBITS); 2400 wx->misc_irq_domain = false; 2401 2402 return 0; 2403 } 2404 EXPORT_SYMBOL(wx_sw_init); 2405 2406 /** 2407 * wx_find_vlvf_slot - find the vlanid or the first empty slot 2408 * @wx: pointer to hardware structure 2409 * @vlan: VLAN id to write to VLAN filter 2410 * 2411 * return the VLVF index where this VLAN id should be placed 2412 * 2413 **/ 2414 static int wx_find_vlvf_slot(struct wx *wx, u32 vlan) 2415 { 2416 u32 bits = 0, first_empty_slot = 0; 2417 int regindex; 2418 2419 /* short cut the special case */ 2420 if (vlan == 0) 2421 return 0; 2422 2423 /* Search for the vlan id in the VLVF entries. Save off the first empty 2424 * slot found along the way 2425 */ 2426 for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) { 2427 wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex); 2428 bits = rd32(wx, WX_PSR_VLAN_SWC); 2429 if (!bits && !(first_empty_slot)) 2430 first_empty_slot = regindex; 2431 else if ((bits & 0x0FFF) == vlan) 2432 break; 2433 } 2434 2435 if (regindex >= WX_PSR_VLAN_SWC_ENTRIES) { 2436 if (first_empty_slot) 2437 regindex = first_empty_slot; 2438 else 2439 regindex = -ENOMEM; 2440 } 2441 2442 return regindex; 2443 } 2444 2445 /** 2446 * wx_set_vlvf - Set VLAN Pool Filter 2447 * @wx: pointer to hardware structure 2448 * @vlan: VLAN id to write to VLAN filter 2449 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2450 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2451 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 2452 * should be changed 2453 * 2454 * Turn on/off specified bit in VLVF table. 2455 **/ 2456 static int wx_set_vlvf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on, 2457 bool *vfta_changed) 2458 { 2459 int vlvf_index; 2460 u32 vt, bits; 2461 2462 /* If VT Mode is set 2463 * Either vlan_on 2464 * make sure the vlan is in VLVF 2465 * set the vind bit in the matching VLVFB 2466 * Or !vlan_on 2467 * clear the pool bit and possibly the vind 2468 */ 2469 vt = rd32(wx, WX_CFG_PORT_CTL); 2470 if (!(vt & WX_CFG_PORT_CTL_NUM_VT_MASK)) 2471 return 0; 2472 2473 vlvf_index = wx_find_vlvf_slot(wx, vlan); 2474 if (vlvf_index < 0) 2475 return vlvf_index; 2476 2477 wr32(wx, WX_PSR_VLAN_SWC_IDX, vlvf_index); 2478 if (vlan_on) { 2479 /* set the pool bit */ 2480 if (vind < 32) { 2481 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2482 bits |= (1 << vind); 2483 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2484 } else { 2485 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2486 bits |= (1 << (vind - 32)); 2487 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2488 } 2489 } else { 2490 /* clear the pool bit */ 2491 if (vind < 32) { 2492 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2493 bits &= ~(1 << vind); 2494 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2495 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2496 } else { 2497 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2498 bits &= ~(1 << (vind - 32)); 2499 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2500 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2501 } 2502 } 2503 2504 if (bits) { 2505 wr32(wx, WX_PSR_VLAN_SWC, (WX_PSR_VLAN_SWC_VIEN | vlan)); 2506 if (!vlan_on && vfta_changed) 2507 *vfta_changed = false; 2508 } else { 2509 wr32(wx, WX_PSR_VLAN_SWC, 0); 2510 } 2511 2512 return 0; 2513 } 2514 2515 /** 2516 * wx_set_vfta - Set VLAN filter table 2517 * @wx: pointer to hardware structure 2518 * @vlan: VLAN id to write to VLAN filter 2519 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2520 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2521 * 2522 * Turn on/off specified VLAN in the VLAN filter table. 2523 **/ 2524 int wx_set_vfta(struct wx *wx, u32 vlan, u32 vind, bool vlan_on) 2525 { 2526 u32 bitindex, vfta, targetbit; 2527 bool vfta_changed = false; 2528 int regindex, ret; 2529 2530 /* this is a 2 part operation - first the VFTA, then the 2531 * VLVF and VLVFB if VT Mode is set 2532 * We don't write the VFTA until we know the VLVF part succeeded. 2533 */ 2534 2535 /* Part 1 2536 * The VFTA is a bitstring made up of 128 32-bit registers 2537 * that enable the particular VLAN id, much like the MTA: 2538 * bits[11-5]: which register 2539 * bits[4-0]: which bit in the register 2540 */ 2541 regindex = (vlan >> 5) & 0x7F; 2542 bitindex = vlan & 0x1F; 2543 targetbit = (1 << bitindex); 2544 /* errata 5 */ 2545 vfta = wx->mac.vft_shadow[regindex]; 2546 if (vlan_on) { 2547 if (!(vfta & targetbit)) { 2548 vfta |= targetbit; 2549 vfta_changed = true; 2550 } 2551 } else { 2552 if ((vfta & targetbit)) { 2553 vfta &= ~targetbit; 2554 vfta_changed = true; 2555 } 2556 } 2557 /* Part 2 2558 * Call wx_set_vlvf to set VLVFB and VLVF 2559 */ 2560 ret = wx_set_vlvf(wx, vlan, vind, vlan_on, &vfta_changed); 2561 if (ret != 0) 2562 return ret; 2563 2564 if (vfta_changed) 2565 wr32(wx, WX_PSR_VLAN_TBL(regindex), vfta); 2566 wx->mac.vft_shadow[regindex] = vfta; 2567 2568 return 0; 2569 } 2570 2571 /** 2572 * wx_clear_vfta - Clear VLAN filter table 2573 * @wx: pointer to hardware structure 2574 * 2575 * Clears the VLAN filer table, and the VMDq index associated with the filter 2576 **/ 2577 static void wx_clear_vfta(struct wx *wx) 2578 { 2579 u32 offset; 2580 2581 for (offset = 0; offset < wx->mac.vft_size; offset++) { 2582 wr32(wx, WX_PSR_VLAN_TBL(offset), 0); 2583 wx->mac.vft_shadow[offset] = 0; 2584 } 2585 2586 for (offset = 0; offset < WX_PSR_VLAN_SWC_ENTRIES; offset++) { 2587 wr32(wx, WX_PSR_VLAN_SWC_IDX, offset); 2588 wr32(wx, WX_PSR_VLAN_SWC, 0); 2589 wr32(wx, WX_PSR_VLAN_SWC_VM_L, 0); 2590 wr32(wx, WX_PSR_VLAN_SWC_VM_H, 0); 2591 } 2592 } 2593 2594 int wx_vlan_rx_add_vid(struct net_device *netdev, 2595 __be16 proto, u16 vid) 2596 { 2597 struct wx *wx = netdev_priv(netdev); 2598 2599 /* add VID to filter table */ 2600 wx_set_vfta(wx, vid, VMDQ_P(0), true); 2601 set_bit(vid, wx->active_vlans); 2602 2603 return 0; 2604 } 2605 EXPORT_SYMBOL(wx_vlan_rx_add_vid); 2606 2607 int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2608 { 2609 struct wx *wx = netdev_priv(netdev); 2610 2611 /* remove VID from filter table */ 2612 if (vid) 2613 wx_set_vfta(wx, vid, VMDQ_P(0), false); 2614 clear_bit(vid, wx->active_vlans); 2615 2616 return 0; 2617 } 2618 EXPORT_SYMBOL(wx_vlan_rx_kill_vid); 2619 2620 static void wx_enable_rx_drop(struct wx *wx, struct wx_ring *ring) 2621 { 2622 u16 reg_idx = ring->reg_idx; 2623 u32 srrctl; 2624 2625 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2626 srrctl |= WX_PX_RR_CFG_DROP_EN; 2627 2628 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2629 } 2630 2631 static void wx_disable_rx_drop(struct wx *wx, struct wx_ring *ring) 2632 { 2633 u16 reg_idx = ring->reg_idx; 2634 u32 srrctl; 2635 2636 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2637 srrctl &= ~WX_PX_RR_CFG_DROP_EN; 2638 2639 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2640 } 2641 2642 int wx_fc_enable(struct wx *wx, bool tx_pause, bool rx_pause) 2643 { 2644 u16 pause_time = WX_DEFAULT_FCPAUSE; 2645 u32 mflcn_reg, fccfg_reg, reg; 2646 u32 fcrtl, fcrth; 2647 int i; 2648 2649 /* Low water mark of zero causes XOFF floods */ 2650 if (tx_pause && wx->fc.high_water) { 2651 if (!wx->fc.low_water || wx->fc.low_water >= wx->fc.high_water) { 2652 wx_err(wx, "Invalid water mark configuration\n"); 2653 return -EINVAL; 2654 } 2655 } 2656 2657 /* Disable any previous flow control settings */ 2658 mflcn_reg = rd32(wx, WX_MAC_RX_FLOW_CTRL); 2659 mflcn_reg &= ~WX_MAC_RX_FLOW_CTRL_RFE; 2660 2661 fccfg_reg = rd32(wx, WX_RDB_RFCC); 2662 fccfg_reg &= ~WX_RDB_RFCC_RFCE_802_3X; 2663 2664 if (rx_pause) 2665 mflcn_reg |= WX_MAC_RX_FLOW_CTRL_RFE; 2666 if (tx_pause) 2667 fccfg_reg |= WX_RDB_RFCC_RFCE_802_3X; 2668 2669 /* Set 802.3x based flow control settings. */ 2670 wr32(wx, WX_MAC_RX_FLOW_CTRL, mflcn_reg); 2671 wr32(wx, WX_RDB_RFCC, fccfg_reg); 2672 2673 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2674 if (tx_pause && wx->fc.high_water) { 2675 fcrtl = (wx->fc.low_water << 10) | WX_RDB_RFCL_XONE; 2676 wr32(wx, WX_RDB_RFCL, fcrtl); 2677 fcrth = (wx->fc.high_water << 10) | WX_RDB_RFCH_XOFFE; 2678 } else { 2679 wr32(wx, WX_RDB_RFCL, 0); 2680 /* In order to prevent Tx hangs when the internal Tx 2681 * switch is enabled we must set the high water mark 2682 * to the Rx packet buffer size - 24KB. This allows 2683 * the Tx switch to function even under heavy Rx 2684 * workloads. 2685 */ 2686 fcrth = rd32(wx, WX_RDB_PB_SZ(0)) - 24576; 2687 } 2688 2689 wr32(wx, WX_RDB_RFCH, fcrth); 2690 2691 /* Configure pause time */ 2692 reg = pause_time * 0x00010001; 2693 wr32(wx, WX_RDB_RFCV, reg); 2694 2695 /* Configure flow control refresh threshold value */ 2696 wr32(wx, WX_RDB_RFCRT, pause_time / 2); 2697 2698 /* We should set the drop enable bit if: 2699 * Number of Rx queues > 1 and flow control is disabled 2700 * 2701 * This allows us to avoid head of line blocking for security 2702 * and performance reasons. 2703 */ 2704 if (wx->num_rx_queues > 1 && !tx_pause) { 2705 for (i = 0; i < wx->num_rx_queues; i++) 2706 wx_enable_rx_drop(wx, wx->rx_ring[i]); 2707 } else { 2708 for (i = 0; i < wx->num_rx_queues; i++) 2709 wx_disable_rx_drop(wx, wx->rx_ring[i]); 2710 } 2711 2712 return 0; 2713 } 2714 EXPORT_SYMBOL(wx_fc_enable); 2715 2716 /** 2717 * wx_update_stats - Update the board statistics counters. 2718 * @wx: board private structure 2719 **/ 2720 void wx_update_stats(struct wx *wx) 2721 { 2722 struct wx_hw_stats *hwstats = &wx->stats; 2723 2724 u64 non_eop_descs = 0, alloc_rx_buff_failed = 0; 2725 u64 hw_csum_rx_good = 0, hw_csum_rx_error = 0; 2726 u64 restart_queue = 0, tx_busy = 0; 2727 u32 i; 2728 2729 /* gather some stats to the wx struct that are per queue */ 2730 for (i = 0; i < wx->num_rx_queues; i++) { 2731 struct wx_ring *rx_ring = wx->rx_ring[i]; 2732 2733 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 2734 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 2735 hw_csum_rx_good += rx_ring->rx_stats.csum_good_cnt; 2736 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 2737 } 2738 wx->non_eop_descs = non_eop_descs; 2739 wx->alloc_rx_buff_failed = alloc_rx_buff_failed; 2740 wx->hw_csum_rx_error = hw_csum_rx_error; 2741 wx->hw_csum_rx_good = hw_csum_rx_good; 2742 2743 for (i = 0; i < wx->num_tx_queues; i++) { 2744 struct wx_ring *tx_ring = wx->tx_ring[i]; 2745 2746 restart_queue += tx_ring->tx_stats.restart_queue; 2747 tx_busy += tx_ring->tx_stats.tx_busy; 2748 } 2749 wx->restart_queue = restart_queue; 2750 wx->tx_busy = tx_busy; 2751 2752 hwstats->gprc += rd32(wx, WX_RDM_PKT_CNT); 2753 hwstats->gptc += rd32(wx, WX_TDM_PKT_CNT); 2754 hwstats->gorc += rd64(wx, WX_RDM_BYTE_CNT_LSB); 2755 hwstats->gotc += rd64(wx, WX_TDM_BYTE_CNT_LSB); 2756 hwstats->tpr += rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2757 hwstats->tpt += rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2758 hwstats->crcerrs += rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2759 hwstats->rlec += rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2760 hwstats->bprc += rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2761 hwstats->bptc += rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2762 hwstats->mprc += rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2763 hwstats->mptc += rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2764 hwstats->roc += rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2765 hwstats->ruc += rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2766 hwstats->lxonoffrxc += rd32(wx, WX_MAC_LXONOFFRXC); 2767 hwstats->lxontxc += rd32(wx, WX_RDB_LXONTXC); 2768 hwstats->lxofftxc += rd32(wx, WX_RDB_LXOFFTXC); 2769 hwstats->o2bgptc += rd32(wx, WX_TDM_OS2BMC_CNT); 2770 hwstats->b2ospc += rd32(wx, WX_MNG_BMC2OS_CNT); 2771 hwstats->o2bspc += rd32(wx, WX_MNG_OS2BMC_CNT); 2772 hwstats->b2ogprc += rd32(wx, WX_RDM_BMC2OS_CNT); 2773 hwstats->rdmdrop += rd32(wx, WX_RDM_DRP_PKT); 2774 2775 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 2776 hwstats->fdirmatch += rd32(wx, WX_RDB_FDIR_MATCH); 2777 hwstats->fdirmiss += rd32(wx, WX_RDB_FDIR_MISS); 2778 } 2779 2780 /* qmprc is not cleared on read, manual reset it */ 2781 hwstats->qmprc = 0; 2782 for (i = wx->num_vfs * wx->num_rx_queues_per_pool; 2783 i < wx->mac.max_rx_queues; i++) 2784 hwstats->qmprc += rd32(wx, WX_PX_MPRC(i)); 2785 } 2786 EXPORT_SYMBOL(wx_update_stats); 2787 2788 /** 2789 * wx_clear_hw_cntrs - Generic clear hardware counters 2790 * @wx: board private structure 2791 * 2792 * Clears all hardware statistics counters by reading them from the hardware 2793 * Statistics counters are clear on read. 2794 **/ 2795 void wx_clear_hw_cntrs(struct wx *wx) 2796 { 2797 u16 i = 0; 2798 2799 for (i = 0; i < wx->mac.max_rx_queues; i++) 2800 wr32(wx, WX_PX_MPRC(i), 0); 2801 2802 rd32(wx, WX_RDM_PKT_CNT); 2803 rd32(wx, WX_TDM_PKT_CNT); 2804 rd64(wx, WX_RDM_BYTE_CNT_LSB); 2805 rd32(wx, WX_TDM_BYTE_CNT_LSB); 2806 rd32(wx, WX_RDM_DRP_PKT); 2807 rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2808 rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2809 rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2810 rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2811 rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2812 rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2813 rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2814 rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2815 rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2816 rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2817 rd32(wx, WX_RDB_LXONTXC); 2818 rd32(wx, WX_RDB_LXOFFTXC); 2819 rd32(wx, WX_MAC_LXONOFFRXC); 2820 } 2821 EXPORT_SYMBOL(wx_clear_hw_cntrs); 2822 2823 /** 2824 * wx_start_hw - Prepare hardware for Tx/Rx 2825 * @wx: pointer to hardware structure 2826 * 2827 * Starts the hardware using the generic start_hw function 2828 * and the generation start_hw function. 2829 * Then performs revision-specific operations, if any. 2830 **/ 2831 void wx_start_hw(struct wx *wx) 2832 { 2833 int i; 2834 2835 /* Clear the VLAN filter table */ 2836 wx_clear_vfta(wx); 2837 WX_WRITE_FLUSH(wx); 2838 /* Clear the rate limiters */ 2839 for (i = 0; i < wx->mac.max_tx_queues; i++) { 2840 wr32(wx, WX_TDM_RP_IDX, i); 2841 wr32(wx, WX_TDM_RP_RATE, 0); 2842 } 2843 } 2844 EXPORT_SYMBOL(wx_start_hw); 2845 2846 MODULE_LICENSE("GPL"); 2847