1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (c) 1996, 2003 VIA Networking Technologies, Inc. 4 * All rights reserved. 5 * 6 * File: via-velocity.h 7 * 8 * Purpose: Header file to define driver's private structures. 9 * 10 * Author: Chuang Liang-Shing, AJ Jiang 11 * 12 * Date: Jan 24, 2003 13 */ 14 15 16 #ifndef VELOCITY_H 17 #define VELOCITY_H 18 19 #define VELOCITY_TX_CSUM_SUPPORT 20 21 #define VELOCITY_NAME "via-velocity" 22 #define VELOCITY_FULL_DRV_NAM "VIA Networking Velocity Family Gigabit Ethernet Adapter Driver" 23 #define VELOCITY_VERSION "1.15" 24 25 #define VELOCITY_IO_SIZE 256 26 27 #define PKT_BUF_SZ 1540 28 29 #define MAX_UNITS 8 30 #define OPTION_DEFAULT { [0 ... MAX_UNITS-1] = -1} 31 32 #define REV_ID_VT6110 (0) 33 34 #define BYTE_REG_BITS_ON(x,p) do { writeb(readb((p))|(x),(p));} while (0) 35 #define WORD_REG_BITS_ON(x,p) do { writew(readw((p))|(x),(p));} while (0) 36 #define DWORD_REG_BITS_ON(x,p) do { writel(readl((p))|(x),(p));} while (0) 37 38 #define BYTE_REG_BITS_IS_ON(x,p) (readb((p)) & (x)) 39 #define WORD_REG_BITS_IS_ON(x,p) (readw((p)) & (x)) 40 #define DWORD_REG_BITS_IS_ON(x,p) (readl((p)) & (x)) 41 42 #define BYTE_REG_BITS_OFF(x,p) do { writeb(readb((p)) & (~(x)),(p));} while (0) 43 #define WORD_REG_BITS_OFF(x,p) do { writew(readw((p)) & (~(x)),(p));} while (0) 44 #define DWORD_REG_BITS_OFF(x,p) do { writel(readl((p)) & (~(x)),(p));} while (0) 45 46 #define BYTE_REG_BITS_SET(x,m,p) do { writeb( (readb((p)) & (~(m))) |(x),(p));} while (0) 47 #define WORD_REG_BITS_SET(x,m,p) do { writew( (readw((p)) & (~(m))) |(x),(p));} while (0) 48 #define DWORD_REG_BITS_SET(x,m,p) do { writel( (readl((p)) & (~(m)))|(x),(p));} while (0) 49 50 #define VAR_USED(p) do {(p)=(p);} while (0) 51 52 /* 53 * Purpose: Structures for MAX RX/TX descriptors. 54 */ 55 56 57 #define B_OWNED_BY_CHIP 1 58 #define B_OWNED_BY_HOST 0 59 60 /* 61 * Bits in the RSR0 register 62 */ 63 64 #define RSR_DETAG cpu_to_le16(0x0080) 65 #define RSR_SNTAG cpu_to_le16(0x0040) 66 #define RSR_RXER cpu_to_le16(0x0020) 67 #define RSR_RL cpu_to_le16(0x0010) 68 #define RSR_CE cpu_to_le16(0x0008) 69 #define RSR_FAE cpu_to_le16(0x0004) 70 #define RSR_CRC cpu_to_le16(0x0002) 71 #define RSR_VIDM cpu_to_le16(0x0001) 72 73 /* 74 * Bits in the RSR1 register 75 */ 76 77 #define RSR_RXOK cpu_to_le16(0x8000) // rx OK 78 #define RSR_PFT cpu_to_le16(0x4000) // Perfect filtering address match 79 #define RSR_MAR cpu_to_le16(0x2000) // MAC accept multicast address packet 80 #define RSR_BAR cpu_to_le16(0x1000) // MAC accept broadcast address packet 81 #define RSR_PHY cpu_to_le16(0x0800) // MAC accept physical address packet 82 #define RSR_VTAG cpu_to_le16(0x0400) // 802.1p/1q tagging packet indicator 83 #define RSR_STP cpu_to_le16(0x0200) // start of packet 84 #define RSR_EDP cpu_to_le16(0x0100) // end of packet 85 86 /* 87 * Bits in the CSM register 88 */ 89 90 #define CSM_IPOK 0x40 //IP Checksum validation ok 91 #define CSM_TUPOK 0x20 //TCP/UDP Checksum validation ok 92 #define CSM_FRAG 0x10 //Fragment IP datagram 93 #define CSM_IPKT 0x04 //Received an IP packet 94 #define CSM_TCPKT 0x02 //Received a TCP packet 95 #define CSM_UDPKT 0x01 //Received a UDP packet 96 97 /* 98 * Bits in the TSR0 register 99 */ 100 101 #define TSR0_ABT cpu_to_le16(0x0080) // Tx abort because of excessive collision 102 #define TSR0_OWT cpu_to_le16(0x0040) // Jumbo frame Tx abort 103 #define TSR0_OWC cpu_to_le16(0x0020) // Out of window collision 104 #define TSR0_COLS cpu_to_le16(0x0010) // experience collision in this transmit event 105 #define TSR0_NCR3 cpu_to_le16(0x0008) // collision retry counter[3] 106 #define TSR0_NCR2 cpu_to_le16(0x0004) // collision retry counter[2] 107 #define TSR0_NCR1 cpu_to_le16(0x0002) // collision retry counter[1] 108 #define TSR0_NCR0 cpu_to_le16(0x0001) // collision retry counter[0] 109 #define TSR0_TERR cpu_to_le16(0x8000) // 110 #define TSR0_FDX cpu_to_le16(0x4000) // current transaction is serviced by full duplex mode 111 #define TSR0_GMII cpu_to_le16(0x2000) // current transaction is serviced by GMII mode 112 #define TSR0_LNKFL cpu_to_le16(0x1000) // packet serviced during link down 113 #define TSR0_SHDN cpu_to_le16(0x0400) // shutdown case 114 #define TSR0_CRS cpu_to_le16(0x0200) // carrier sense lost 115 #define TSR0_CDH cpu_to_le16(0x0100) // AQE test fail (CD heartbeat) 116 117 // 118 // Bits in the TCR0 register 119 // 120 #define TCR0_TIC 0x80 // assert interrupt immediately while descriptor has been send complete 121 #define TCR0_PIC 0x40 // priority interrupt request, INA# is issued over adaptive interrupt scheme 122 #define TCR0_VETAG 0x20 // enable VLAN tag 123 #define TCR0_IPCK 0x10 // request IP checksum calculation. 124 #define TCR0_UDPCK 0x08 // request UDP checksum calculation. 125 #define TCR0_TCPCK 0x04 // request TCP checksum calculation. 126 #define TCR0_JMBO 0x02 // indicate a jumbo packet in GMAC side 127 #define TCR0_CRC 0x01 // disable CRC generation 128 129 #define TCPLS_NORMAL 3 130 #define TCPLS_START 2 131 #define TCPLS_END 1 132 #define TCPLS_MED 0 133 134 135 // max transmit or receive buffer size 136 #define CB_RX_BUF_SIZE 2048UL // max buffer size 137 // NOTE: must be multiple of 4 138 139 #define CB_MAX_RD_NUM 512 // MAX # of RD 140 #define CB_MAX_TD_NUM 256 // MAX # of TD 141 142 #define CB_INIT_RD_NUM_3119 128 // init # of RD, for setup VT3119 143 #define CB_INIT_TD_NUM_3119 64 // init # of TD, for setup VT3119 144 145 #define CB_INIT_RD_NUM 128 // init # of RD, for setup default 146 #define CB_INIT_TD_NUM 64 // init # of TD, for setup default 147 148 // for 3119 149 #define CB_TD_RING_NUM 4 // # of TD rings. 150 #define CB_MAX_SEG_PER_PKT 7 // max data seg per packet (Tx) 151 152 153 /* 154 * If collisions excess 15 times , tx will abort, and 155 * if tx fifo underflow, tx will fail 156 * we should try to resend it 157 */ 158 159 #define CB_MAX_TX_ABORT_RETRY 3 160 161 /* 162 * Receive descriptor 163 */ 164 165 struct rdesc0 { 166 __le16 RSR; /* Receive status */ 167 __le16 len; /* bits 0--13; bit 15 - owner */ 168 }; 169 170 struct rdesc1 { 171 __le16 PQTAG; 172 u8 CSM; 173 u8 IPKT; 174 }; 175 176 enum { 177 RX_INTEN = cpu_to_le16(0x8000) 178 }; 179 180 struct rx_desc { 181 struct rdesc0 rdesc0; 182 struct rdesc1 rdesc1; 183 __le32 pa_low; /* Low 32 bit PCI address */ 184 __le16 pa_high; /* Next 16 bit PCI address (48 total) */ 185 __le16 size; /* bits 0--14 - frame size, bit 15 - enable int. */ 186 } __packed; 187 188 /* 189 * Transmit descriptor 190 */ 191 192 struct tdesc0 { 193 __le16 TSR; /* Transmit status register */ 194 __le16 len; /* bits 0--13 - size of frame, bit 15 - owner */ 195 }; 196 197 struct tdesc1 { 198 __le16 vlan; 199 u8 TCR; 200 u8 cmd; /* bits 0--1 - TCPLS, bits 4--7 - CMDZ */ 201 } __packed; 202 203 enum { 204 TD_QUEUE = cpu_to_le16(0x8000) 205 }; 206 207 struct td_buf { 208 __le32 pa_low; 209 __le16 pa_high; 210 __le16 size; /* bits 0--13 - size, bit 15 - queue */ 211 } __packed; 212 213 struct tx_desc { 214 struct tdesc0 tdesc0; 215 struct tdesc1 tdesc1; 216 struct td_buf td_buf[7]; 217 }; 218 219 struct velocity_rd_info { 220 struct sk_buff *skb; 221 dma_addr_t skb_dma; 222 }; 223 224 /* 225 * Used to track transmit side buffers. 226 */ 227 228 struct velocity_td_info { 229 struct sk_buff *skb; 230 int nskb_dma; 231 dma_addr_t skb_dma[7]; 232 }; 233 234 enum velocity_owner { 235 OWNED_BY_HOST = 0, 236 OWNED_BY_NIC = cpu_to_le16(0x8000) 237 }; 238 239 240 /* 241 * MAC registers and macros. 242 */ 243 244 245 #define MCAM_SIZE 64 246 #define VCAM_SIZE 64 247 #define TX_QUEUE_NO 4 248 249 #define MAX_HW_MIB_COUNTER 32 250 #define VELOCITY_MIN_MTU (64) 251 #define VELOCITY_MAX_MTU (9000) 252 253 /* 254 * Registers in the MAC 255 */ 256 257 #define MAC_REG_PAR 0x00 // physical address 258 #define MAC_REG_RCR 0x06 259 #define MAC_REG_TCR 0x07 260 #define MAC_REG_CR0_SET 0x08 261 #define MAC_REG_CR1_SET 0x09 262 #define MAC_REG_CR2_SET 0x0A 263 #define MAC_REG_CR3_SET 0x0B 264 #define MAC_REG_CR0_CLR 0x0C 265 #define MAC_REG_CR1_CLR 0x0D 266 #define MAC_REG_CR2_CLR 0x0E 267 #define MAC_REG_CR3_CLR 0x0F 268 #define MAC_REG_MAR 0x10 269 #define MAC_REG_CAM 0x10 270 #define MAC_REG_DEC_BASE_HI 0x18 271 #define MAC_REG_DBF_BASE_HI 0x1C 272 #define MAC_REG_ISR_CTL 0x20 273 #define MAC_REG_ISR_HOTMR 0x20 274 #define MAC_REG_ISR_TSUPTHR 0x20 275 #define MAC_REG_ISR_RSUPTHR 0x20 276 #define MAC_REG_ISR_CTL1 0x21 277 #define MAC_REG_TXE_SR 0x22 278 #define MAC_REG_RXE_SR 0x23 279 #define MAC_REG_ISR 0x24 280 #define MAC_REG_ISR0 0x24 281 #define MAC_REG_ISR1 0x25 282 #define MAC_REG_ISR2 0x26 283 #define MAC_REG_ISR3 0x27 284 #define MAC_REG_IMR 0x28 285 #define MAC_REG_IMR0 0x28 286 #define MAC_REG_IMR1 0x29 287 #define MAC_REG_IMR2 0x2A 288 #define MAC_REG_IMR3 0x2B 289 #define MAC_REG_TDCSR_SET 0x30 290 #define MAC_REG_RDCSR_SET 0x32 291 #define MAC_REG_TDCSR_CLR 0x34 292 #define MAC_REG_RDCSR_CLR 0x36 293 #define MAC_REG_RDBASE_LO 0x38 294 #define MAC_REG_RDINDX 0x3C 295 #define MAC_REG_TDBASE_LO 0x40 296 #define MAC_REG_RDCSIZE 0x50 297 #define MAC_REG_TDCSIZE 0x52 298 #define MAC_REG_TDINDX 0x54 299 #define MAC_REG_TDIDX0 0x54 300 #define MAC_REG_TDIDX1 0x56 301 #define MAC_REG_TDIDX2 0x58 302 #define MAC_REG_TDIDX3 0x5A 303 #define MAC_REG_PAUSE_TIMER 0x5C 304 #define MAC_REG_RBRDU 0x5E 305 #define MAC_REG_FIFO_TEST0 0x60 306 #define MAC_REG_FIFO_TEST1 0x64 307 #define MAC_REG_CAMADDR 0x68 308 #define MAC_REG_CAMCR 0x69 309 #define MAC_REG_GFTEST 0x6A 310 #define MAC_REG_FTSTCMD 0x6B 311 #define MAC_REG_MIICFG 0x6C 312 #define MAC_REG_MIISR 0x6D 313 #define MAC_REG_PHYSR0 0x6E 314 #define MAC_REG_PHYSR1 0x6F 315 #define MAC_REG_MIICR 0x70 316 #define MAC_REG_MIIADR 0x71 317 #define MAC_REG_MIIDATA 0x72 318 #define MAC_REG_SOFT_TIMER0 0x74 319 #define MAC_REG_SOFT_TIMER1 0x76 320 #define MAC_REG_CFGA 0x78 321 #define MAC_REG_CFGB 0x79 322 #define MAC_REG_CFGC 0x7A 323 #define MAC_REG_CFGD 0x7B 324 #define MAC_REG_DCFG0 0x7C 325 #define MAC_REG_DCFG1 0x7D 326 #define MAC_REG_MCFG0 0x7E 327 #define MAC_REG_MCFG1 0x7F 328 329 #define MAC_REG_TBIST 0x80 330 #define MAC_REG_RBIST 0x81 331 #define MAC_REG_PMCC 0x82 332 #define MAC_REG_STICKHW 0x83 333 #define MAC_REG_MIBCR 0x84 334 #define MAC_REG_EERSV 0x85 335 #define MAC_REG_REVID 0x86 336 #define MAC_REG_MIBREAD 0x88 337 #define MAC_REG_BPMA 0x8C 338 #define MAC_REG_EEWR_DATA 0x8C 339 #define MAC_REG_BPMD_WR 0x8F 340 #define MAC_REG_BPCMD 0x90 341 #define MAC_REG_BPMD_RD 0x91 342 #define MAC_REG_EECHKSUM 0x92 343 #define MAC_REG_EECSR 0x93 344 #define MAC_REG_EERD_DATA 0x94 345 #define MAC_REG_EADDR 0x96 346 #define MAC_REG_EMBCMD 0x97 347 #define MAC_REG_JMPSR0 0x98 348 #define MAC_REG_JMPSR1 0x99 349 #define MAC_REG_JMPSR2 0x9A 350 #define MAC_REG_JMPSR3 0x9B 351 #define MAC_REG_CHIPGSR 0x9C 352 #define MAC_REG_TESTCFG 0x9D 353 #define MAC_REG_DEBUG 0x9E 354 #define MAC_REG_CHIPGCR 0x9F /* Chip Operation and Diagnostic Control */ 355 #define MAC_REG_WOLCR0_SET 0xA0 356 #define MAC_REG_WOLCR1_SET 0xA1 357 #define MAC_REG_PWCFG_SET 0xA2 358 #define MAC_REG_WOLCFG_SET 0xA3 359 #define MAC_REG_WOLCR0_CLR 0xA4 360 #define MAC_REG_WOLCR1_CLR 0xA5 361 #define MAC_REG_PWCFG_CLR 0xA6 362 #define MAC_REG_WOLCFG_CLR 0xA7 363 #define MAC_REG_WOLSR0_SET 0xA8 364 #define MAC_REG_WOLSR1_SET 0xA9 365 #define MAC_REG_WOLSR0_CLR 0xAC 366 #define MAC_REG_WOLSR1_CLR 0xAD 367 #define MAC_REG_PATRN_CRC0 0xB0 368 #define MAC_REG_PATRN_CRC1 0xB2 369 #define MAC_REG_PATRN_CRC2 0xB4 370 #define MAC_REG_PATRN_CRC3 0xB6 371 #define MAC_REG_PATRN_CRC4 0xB8 372 #define MAC_REG_PATRN_CRC5 0xBA 373 #define MAC_REG_PATRN_CRC6 0xBC 374 #define MAC_REG_PATRN_CRC7 0xBE 375 #define MAC_REG_BYTEMSK0_0 0xC0 376 #define MAC_REG_BYTEMSK0_1 0xC4 377 #define MAC_REG_BYTEMSK0_2 0xC8 378 #define MAC_REG_BYTEMSK0_3 0xCC 379 #define MAC_REG_BYTEMSK1_0 0xD0 380 #define MAC_REG_BYTEMSK1_1 0xD4 381 #define MAC_REG_BYTEMSK1_2 0xD8 382 #define MAC_REG_BYTEMSK1_3 0xDC 383 #define MAC_REG_BYTEMSK2_0 0xE0 384 #define MAC_REG_BYTEMSK2_1 0xE4 385 #define MAC_REG_BYTEMSK2_2 0xE8 386 #define MAC_REG_BYTEMSK2_3 0xEC 387 #define MAC_REG_BYTEMSK3_0 0xF0 388 #define MAC_REG_BYTEMSK3_1 0xF4 389 #define MAC_REG_BYTEMSK3_2 0xF8 390 #define MAC_REG_BYTEMSK3_3 0xFC 391 392 /* 393 * Bits in the RCR register 394 */ 395 396 #define RCR_AS 0x80 397 #define RCR_AP 0x40 398 #define RCR_AL 0x20 399 #define RCR_PROM 0x10 400 #define RCR_AB 0x08 401 #define RCR_AM 0x04 402 #define RCR_AR 0x02 403 #define RCR_SEP 0x01 404 405 /* 406 * Bits in the TCR register 407 */ 408 409 #define TCR_TB2BDIS 0x80 410 #define TCR_COLTMC1 0x08 411 #define TCR_COLTMC0 0x04 412 #define TCR_LB1 0x02 /* loopback[1] */ 413 #define TCR_LB0 0x01 /* loopback[0] */ 414 415 /* 416 * Bits in the CR0 register 417 */ 418 419 #define CR0_TXON 0x00000008UL 420 #define CR0_RXON 0x00000004UL 421 #define CR0_STOP 0x00000002UL /* stop MAC, default = 1 */ 422 #define CR0_STRT 0x00000001UL /* start MAC */ 423 #define CR0_SFRST 0x00008000UL /* software reset */ 424 #define CR0_TM1EN 0x00004000UL 425 #define CR0_TM0EN 0x00002000UL 426 #define CR0_DPOLL 0x00000800UL /* disable rx/tx auto polling */ 427 #define CR0_DISAU 0x00000100UL 428 #define CR0_XONEN 0x00800000UL 429 #define CR0_FDXTFCEN 0x00400000UL /* full-duplex TX flow control enable */ 430 #define CR0_FDXRFCEN 0x00200000UL /* full-duplex RX flow control enable */ 431 #define CR0_HDXFCEN 0x00100000UL /* half-duplex flow control enable */ 432 #define CR0_XHITH1 0x00080000UL /* TX XON high threshold 1 */ 433 #define CR0_XHITH0 0x00040000UL /* TX XON high threshold 0 */ 434 #define CR0_XLTH1 0x00020000UL /* TX pause frame low threshold 1 */ 435 #define CR0_XLTH0 0x00010000UL /* TX pause frame low threshold 0 */ 436 #define CR0_GSPRST 0x80000000UL 437 #define CR0_FORSRST 0x40000000UL 438 #define CR0_FPHYRST 0x20000000UL 439 #define CR0_DIAG 0x10000000UL 440 #define CR0_INTPCTL 0x04000000UL 441 #define CR0_GINTMSK1 0x02000000UL 442 #define CR0_GINTMSK0 0x01000000UL 443 444 /* 445 * Bits in the CR1 register 446 */ 447 448 #define CR1_SFRST 0x80 /* software reset */ 449 #define CR1_TM1EN 0x40 450 #define CR1_TM0EN 0x20 451 #define CR1_DPOLL 0x08 /* disable rx/tx auto polling */ 452 #define CR1_DISAU 0x01 453 454 /* 455 * Bits in the CR2 register 456 */ 457 458 #define CR2_XONEN 0x80 459 #define CR2_FDXTFCEN 0x40 /* full-duplex TX flow control enable */ 460 #define CR2_FDXRFCEN 0x20 /* full-duplex RX flow control enable */ 461 #define CR2_HDXFCEN 0x10 /* half-duplex flow control enable */ 462 #define CR2_XHITH1 0x08 /* TX XON high threshold 1 */ 463 #define CR2_XHITH0 0x04 /* TX XON high threshold 0 */ 464 #define CR2_XLTH1 0x02 /* TX pause frame low threshold 1 */ 465 #define CR2_XLTH0 0x01 /* TX pause frame low threshold 0 */ 466 467 /* 468 * Bits in the CR3 register 469 */ 470 471 #define CR3_GSPRST 0x80 472 #define CR3_FORSRST 0x40 473 #define CR3_FPHYRST 0x20 474 #define CR3_DIAG 0x10 475 #define CR3_INTPCTL 0x04 476 #define CR3_GINTMSK1 0x02 477 #define CR3_GINTMSK0 0x01 478 479 #define ISRCTL_UDPINT 0x8000 480 #define ISRCTL_TSUPDIS 0x4000 481 #define ISRCTL_RSUPDIS 0x2000 482 #define ISRCTL_PMSK1 0x1000 483 #define ISRCTL_PMSK0 0x0800 484 #define ISRCTL_INTPD 0x0400 485 #define ISRCTL_HCRLD 0x0200 486 #define ISRCTL_SCRLD 0x0100 487 488 /* 489 * Bits in the ISR_CTL1 register 490 */ 491 492 #define ISRCTL1_UDPINT 0x80 493 #define ISRCTL1_TSUPDIS 0x40 494 #define ISRCTL1_RSUPDIS 0x20 495 #define ISRCTL1_PMSK1 0x10 496 #define ISRCTL1_PMSK0 0x08 497 #define ISRCTL1_INTPD 0x04 498 #define ISRCTL1_HCRLD 0x02 499 #define ISRCTL1_SCRLD 0x01 500 501 /* 502 * Bits in the TXE_SR register 503 */ 504 505 #define TXESR_TFDBS 0x08 506 #define TXESR_TDWBS 0x04 507 #define TXESR_TDRBS 0x02 508 #define TXESR_TDSTR 0x01 509 510 /* 511 * Bits in the RXE_SR register 512 */ 513 514 #define RXESR_RFDBS 0x08 515 #define RXESR_RDWBS 0x04 516 #define RXESR_RDRBS 0x02 517 #define RXESR_RDSTR 0x01 518 519 /* 520 * Bits in the ISR register 521 */ 522 523 #define ISR_ISR3 0x80000000UL 524 #define ISR_ISR2 0x40000000UL 525 #define ISR_ISR1 0x20000000UL 526 #define ISR_ISR0 0x10000000UL 527 #define ISR_TXSTLI 0x02000000UL 528 #define ISR_RXSTLI 0x01000000UL 529 #define ISR_HFLD 0x00800000UL 530 #define ISR_UDPI 0x00400000UL 531 #define ISR_MIBFI 0x00200000UL 532 #define ISR_SHDNI 0x00100000UL 533 #define ISR_PHYI 0x00080000UL 534 #define ISR_PWEI 0x00040000UL 535 #define ISR_TMR1I 0x00020000UL 536 #define ISR_TMR0I 0x00010000UL 537 #define ISR_SRCI 0x00008000UL 538 #define ISR_LSTPEI 0x00004000UL 539 #define ISR_LSTEI 0x00002000UL 540 #define ISR_OVFI 0x00001000UL 541 #define ISR_FLONI 0x00000800UL 542 #define ISR_RACEI 0x00000400UL 543 #define ISR_TXWB1I 0x00000200UL 544 #define ISR_TXWB0I 0x00000100UL 545 #define ISR_PTX3I 0x00000080UL 546 #define ISR_PTX2I 0x00000040UL 547 #define ISR_PTX1I 0x00000020UL 548 #define ISR_PTX0I 0x00000010UL 549 #define ISR_PTXI 0x00000008UL 550 #define ISR_PRXI 0x00000004UL 551 #define ISR_PPTXI 0x00000002UL 552 #define ISR_PPRXI 0x00000001UL 553 554 /* 555 * Bits in the IMR register 556 */ 557 558 #define IMR_TXSTLM 0x02000000UL 559 #define IMR_UDPIM 0x00400000UL 560 #define IMR_MIBFIM 0x00200000UL 561 #define IMR_SHDNIM 0x00100000UL 562 #define IMR_PHYIM 0x00080000UL 563 #define IMR_PWEIM 0x00040000UL 564 #define IMR_TMR1IM 0x00020000UL 565 #define IMR_TMR0IM 0x00010000UL 566 567 #define IMR_SRCIM 0x00008000UL 568 #define IMR_LSTPEIM 0x00004000UL 569 #define IMR_LSTEIM 0x00002000UL 570 #define IMR_OVFIM 0x00001000UL 571 #define IMR_FLONIM 0x00000800UL 572 #define IMR_RACEIM 0x00000400UL 573 #define IMR_TXWB1IM 0x00000200UL 574 #define IMR_TXWB0IM 0x00000100UL 575 576 #define IMR_PTX3IM 0x00000080UL 577 #define IMR_PTX2IM 0x00000040UL 578 #define IMR_PTX1IM 0x00000020UL 579 #define IMR_PTX0IM 0x00000010UL 580 #define IMR_PTXIM 0x00000008UL 581 #define IMR_PRXIM 0x00000004UL 582 #define IMR_PPTXIM 0x00000002UL 583 #define IMR_PPRXIM 0x00000001UL 584 585 /* 0x0013FB0FUL = initial value of IMR */ 586 587 #define INT_MASK_DEF (IMR_PPTXIM|IMR_PPRXIM|IMR_PTXIM|IMR_PRXIM|\ 588 IMR_PWEIM|IMR_TXWB0IM|IMR_TXWB1IM|IMR_FLONIM|\ 589 IMR_OVFIM|IMR_LSTEIM|IMR_LSTPEIM|IMR_SRCIM|IMR_MIBFIM|\ 590 IMR_SHDNIM|IMR_TMR1IM|IMR_TMR0IM|IMR_TXSTLM) 591 592 /* 593 * Bits in the TDCSR0/1, RDCSR0 register 594 */ 595 596 #define TRDCSR_DEAD 0x0008 597 #define TRDCSR_WAK 0x0004 598 #define TRDCSR_ACT 0x0002 599 #define TRDCSR_RUN 0x0001 600 601 /* 602 * Bits in the CAMADDR register 603 */ 604 605 #define CAMADDR_CAMEN 0x80 606 #define CAMADDR_VCAMSL 0x40 607 608 /* 609 * Bits in the CAMCR register 610 */ 611 612 #define CAMCR_PS1 0x80 613 #define CAMCR_PS0 0x40 614 #define CAMCR_AITRPKT 0x20 615 #define CAMCR_AITR16 0x10 616 #define CAMCR_CAMRD 0x08 617 #define CAMCR_CAMWR 0x04 618 #define CAMCR_PS_CAM_MASK 0x40 619 #define CAMCR_PS_CAM_DATA 0x80 620 #define CAMCR_PS_MAR 0x00 621 622 /* 623 * Bits in the MIICFG register 624 */ 625 626 #define MIICFG_MPO1 0x80 627 #define MIICFG_MPO0 0x40 628 #define MIICFG_MFDC 0x20 629 630 /* 631 * Bits in the MIISR register 632 */ 633 634 #define MIISR_MIDLE 0x80 635 636 /* 637 * Bits in the PHYSR0 register 638 */ 639 640 #define PHYSR0_PHYRST 0x80 641 #define PHYSR0_LINKGD 0x40 642 #define PHYSR0_FDPX 0x10 643 #define PHYSR0_SPDG 0x08 644 #define PHYSR0_SPD10 0x04 645 #define PHYSR0_RXFLC 0x02 646 #define PHYSR0_TXFLC 0x01 647 648 /* 649 * Bits in the PHYSR1 register 650 */ 651 652 #define PHYSR1_PHYTBI 0x01 653 654 /* 655 * Bits in the MIICR register 656 */ 657 658 #define MIICR_MAUTO 0x80 659 #define MIICR_RCMD 0x40 660 #define MIICR_WCMD 0x20 661 #define MIICR_MDPM 0x10 662 #define MIICR_MOUT 0x08 663 #define MIICR_MDO 0x04 664 #define MIICR_MDI 0x02 665 #define MIICR_MDC 0x01 666 667 /* 668 * Bits in the MIIADR register 669 */ 670 671 #define MIIADR_SWMPL 0x80 672 673 /* 674 * Bits in the CFGA register 675 */ 676 677 #define CFGA_PMHCTG 0x08 678 #define CFGA_GPIO1PD 0x04 679 #define CFGA_ABSHDN 0x02 680 #define CFGA_PACPI 0x01 681 682 /* 683 * Bits in the CFGB register 684 */ 685 686 #define CFGB_GTCKOPT 0x80 687 #define CFGB_MIIOPT 0x40 688 #define CFGB_CRSEOPT 0x20 689 #define CFGB_OFSET 0x10 690 #define CFGB_CRANDOM 0x08 691 #define CFGB_CAP 0x04 692 #define CFGB_MBA 0x02 693 #define CFGB_BAKOPT 0x01 694 695 /* 696 * Bits in the CFGC register 697 */ 698 699 #define CFGC_EELOAD 0x80 700 #define CFGC_BROPT 0x40 701 #define CFGC_DLYEN 0x20 702 #define CFGC_DTSEL 0x10 703 #define CFGC_BTSEL 0x08 704 #define CFGC_BPS2 0x04 /* bootrom select[2] */ 705 #define CFGC_BPS1 0x02 /* bootrom select[1] */ 706 #define CFGC_BPS0 0x01 /* bootrom select[0] */ 707 708 /* 709 * Bits in the CFGD register 710 */ 711 712 #define CFGD_IODIS 0x80 713 #define CFGD_MSLVDACEN 0x40 714 #define CFGD_CFGDACEN 0x20 715 #define CFGD_PCI64EN 0x10 716 #define CFGD_HTMRL4 0x08 717 718 /* 719 * Bits in the DCFG1 register 720 */ 721 722 #define DCFG_XMWI 0x8000 723 #define DCFG_XMRM 0x4000 724 #define DCFG_XMRL 0x2000 725 #define DCFG_PERDIS 0x1000 726 #define DCFG_MRWAIT 0x0400 727 #define DCFG_MWWAIT 0x0200 728 #define DCFG_LATMEN 0x0100 729 730 /* 731 * Bits in the MCFG0 register 732 */ 733 734 #define MCFG_RXARB 0x0080 735 #define MCFG_RFT1 0x0020 736 #define MCFG_RFT0 0x0010 737 #define MCFG_LOWTHOPT 0x0008 738 #define MCFG_PQEN 0x0004 739 #define MCFG_RTGOPT 0x0002 740 #define MCFG_VIDFR 0x0001 741 742 /* 743 * Bits in the MCFG1 register 744 */ 745 746 #define MCFG_TXARB 0x8000 747 #define MCFG_TXQBK1 0x0800 748 #define MCFG_TXQBK0 0x0400 749 #define MCFG_TXQNOBK 0x0200 750 #define MCFG_SNAPOPT 0x0100 751 752 /* 753 * Bits in the PMCC register 754 */ 755 756 #define PMCC_DSI 0x80 757 #define PMCC_D2_DIS 0x40 758 #define PMCC_D1_DIS 0x20 759 #define PMCC_D3C_EN 0x10 760 #define PMCC_D3H_EN 0x08 761 #define PMCC_D2_EN 0x04 762 #define PMCC_D1_EN 0x02 763 #define PMCC_D0_EN 0x01 764 765 /* 766 * Bits in STICKHW 767 */ 768 769 #define STICKHW_SWPTAG 0x10 770 #define STICKHW_WOLSR 0x08 771 #define STICKHW_WOLEN 0x04 772 #define STICKHW_DS1 0x02 /* R/W by software/cfg cycle */ 773 #define STICKHW_DS0 0x01 /* suspend well DS write port */ 774 775 /* 776 * Bits in the MIBCR register 777 */ 778 779 #define MIBCR_MIBISTOK 0x80 780 #define MIBCR_MIBISTGO 0x40 781 #define MIBCR_MIBINC 0x20 782 #define MIBCR_MIBHI 0x10 783 #define MIBCR_MIBFRZ 0x08 784 #define MIBCR_MIBFLSH 0x04 785 #define MIBCR_MPTRINI 0x02 786 #define MIBCR_MIBCLR 0x01 787 788 /* 789 * Bits in the EERSV register 790 */ 791 792 #define EERSV_BOOT_RPL ((u8) 0x01) /* Boot method selection for VT6110 */ 793 794 #define EERSV_BOOT_MASK ((u8) 0x06) 795 #define EERSV_BOOT_INT19 ((u8) 0x00) 796 #define EERSV_BOOT_INT18 ((u8) 0x02) 797 #define EERSV_BOOT_LOCAL ((u8) 0x04) 798 #define EERSV_BOOT_BEV ((u8) 0x06) 799 800 801 /* 802 * Bits in BPCMD 803 */ 804 805 #define BPCMD_BPDNE 0x80 806 #define BPCMD_EBPWR 0x02 807 #define BPCMD_EBPRD 0x01 808 809 /* 810 * Bits in the EECSR register 811 */ 812 813 #define EECSR_EMBP 0x40 /* eeprom embedded programming */ 814 #define EECSR_RELOAD 0x20 /* eeprom content reload */ 815 #define EECSR_DPM 0x10 /* eeprom direct programming */ 816 #define EECSR_ECS 0x08 /* eeprom CS pin */ 817 #define EECSR_ECK 0x04 /* eeprom CK pin */ 818 #define EECSR_EDI 0x02 /* eeprom DI pin */ 819 #define EECSR_EDO 0x01 /* eeprom DO pin */ 820 821 /* 822 * Bits in the EMBCMD register 823 */ 824 825 #define EMBCMD_EDONE 0x80 826 #define EMBCMD_EWDIS 0x08 827 #define EMBCMD_EWEN 0x04 828 #define EMBCMD_EWR 0x02 829 #define EMBCMD_ERD 0x01 830 831 /* 832 * Bits in TESTCFG register 833 */ 834 835 #define TESTCFG_HBDIS 0x80 836 837 /* 838 * Bits in CHIPGCR register 839 */ 840 841 #define CHIPGCR_FCGMII 0x80 /* force GMII (else MII only) */ 842 #define CHIPGCR_FCFDX 0x40 /* force full duplex */ 843 #define CHIPGCR_FCRESV 0x20 844 #define CHIPGCR_FCMODE 0x10 /* enable MAC forced mode */ 845 #define CHIPGCR_LPSOPT 0x08 846 #define CHIPGCR_TM1US 0x04 847 #define CHIPGCR_TM0US 0x02 848 #define CHIPGCR_PHYINTEN 0x01 849 850 /* 851 * Bits in WOLCR0 852 */ 853 854 #define WOLCR_MSWOLEN7 0x0080 /* enable pattern match filtering */ 855 #define WOLCR_MSWOLEN6 0x0040 856 #define WOLCR_MSWOLEN5 0x0020 857 #define WOLCR_MSWOLEN4 0x0010 858 #define WOLCR_MSWOLEN3 0x0008 859 #define WOLCR_MSWOLEN2 0x0004 860 #define WOLCR_MSWOLEN1 0x0002 861 #define WOLCR_MSWOLEN0 0x0001 862 #define WOLCR_ARP_EN 0x0001 863 864 /* 865 * Bits in WOLCR1 866 */ 867 868 #define WOLCR_LINKOFF_EN 0x0800 /* link off detected enable */ 869 #define WOLCR_LINKON_EN 0x0400 /* link on detected enable */ 870 #define WOLCR_MAGIC_EN 0x0200 /* magic packet filter enable */ 871 #define WOLCR_UNICAST_EN 0x0100 /* unicast filter enable */ 872 873 874 /* 875 * Bits in PWCFG 876 */ 877 878 #define PWCFG_PHYPWOPT 0x80 /* internal MII I/F timing */ 879 #define PWCFG_PCISTICK 0x40 /* PCI sticky R/W enable */ 880 #define PWCFG_WOLTYPE 0x20 /* pulse(1) or button (0) */ 881 #define PWCFG_LEGCY_WOL 0x10 882 #define PWCFG_PMCSR_PME_SR 0x08 883 #define PWCFG_PMCSR_PME_EN 0x04 /* control by PCISTICK */ 884 #define PWCFG_LEGACY_WOLSR 0x02 /* Legacy WOL_SR shadow */ 885 #define PWCFG_LEGACY_WOLEN 0x01 /* Legacy WOL_EN shadow */ 886 887 /* 888 * Bits in WOLCFG 889 */ 890 891 #define WOLCFG_PMEOVR 0x80 /* for legacy use, force PMEEN always */ 892 #define WOLCFG_SAM 0x20 /* accept multicast case reset, default=0 */ 893 #define WOLCFG_SAB 0x10 /* accept broadcast case reset, default=0 */ 894 #define WOLCFG_SMIIACC 0x08 /* ?? */ 895 #define WOLCFG_SGENWH 0x02 896 #define WOLCFG_PHYINTEN 0x01 /* 0:PHYINT trigger enable, 1:use internal MII 897 to report status change */ 898 /* 899 * Bits in WOLSR1 900 */ 901 902 #define WOLSR_LINKOFF_INT 0x0800 903 #define WOLSR_LINKON_INT 0x0400 904 #define WOLSR_MAGIC_INT 0x0200 905 #define WOLSR_UNICAST_INT 0x0100 906 907 /* 908 * Ethernet address filter type 909 */ 910 911 #define PKT_TYPE_NONE 0x0000 /* Turn off receiver */ 912 #define PKT_TYPE_DIRECTED 0x0001 /* obselete, directed address is always accepted */ 913 #define PKT_TYPE_MULTICAST 0x0002 914 #define PKT_TYPE_ALL_MULTICAST 0x0004 915 #define PKT_TYPE_BROADCAST 0x0008 916 #define PKT_TYPE_PROMISCUOUS 0x0020 917 #define PKT_TYPE_LONG 0x2000 /* NOTE.... the definition of LONG is >2048 bytes in our chip */ 918 #define PKT_TYPE_RUNT 0x4000 919 #define PKT_TYPE_ERROR 0x8000 /* Accept error packets, e.g. CRC error */ 920 921 /* 922 * Loopback mode 923 */ 924 925 #define MAC_LB_NONE 0x00 926 #define MAC_LB_INTERNAL 0x01 927 #define MAC_LB_EXTERNAL 0x02 928 929 /* 930 * Enabled mask value of irq 931 */ 932 933 #if defined(_SIM) 934 #define IMR_MASK_VALUE 0x0033FF0FUL /* initial value of IMR 935 set IMR0 to 0x0F according to spec */ 936 937 #else 938 #define IMR_MASK_VALUE 0x0013FB0FUL /* initial value of IMR 939 ignore MIBFI,RACEI to 940 reduce intr. frequency 941 NOTE.... do not enable NoBuf int mask at driver 942 when (1) NoBuf -> RxThreshold = SF 943 (2) OK -> RxThreshold = original value 944 */ 945 #endif 946 947 /* 948 * Revision id 949 */ 950 951 #define REV_ID_VT3119_A0 0x00 952 #define REV_ID_VT3119_A1 0x01 953 #define REV_ID_VT3216_A0 0x10 954 955 /* 956 * Max time out delay time 957 */ 958 959 #define W_MAX_TIMEOUT 0x0FFFU 960 961 962 /* 963 * MAC registers as a structure. Cannot be directly accessed this 964 * way but generates offsets for readl/writel() calls 965 */ 966 967 struct mac_regs { 968 volatile u8 PAR[6]; /* 0x00 */ 969 volatile u8 RCR; 970 volatile u8 TCR; 971 972 volatile __le32 CR0Set; /* 0x08 */ 973 volatile __le32 CR0Clr; /* 0x0C */ 974 975 volatile u8 MARCAM[8]; /* 0x10 */ 976 977 volatile __le32 DecBaseHi; /* 0x18 */ 978 volatile __le16 DbfBaseHi; /* 0x1C */ 979 volatile __le16 reserved_1E; 980 981 volatile __le16 ISRCTL; /* 0x20 */ 982 volatile u8 TXESR; 983 volatile u8 RXESR; 984 985 volatile __le32 ISR; /* 0x24 */ 986 volatile __le32 IMR; 987 988 volatile __le32 TDStatusPort; /* 0x2C */ 989 990 volatile __le16 TDCSRSet; /* 0x30 */ 991 volatile u8 RDCSRSet; 992 volatile u8 reserved_33; 993 volatile __le16 TDCSRClr; 994 volatile u8 RDCSRClr; 995 volatile u8 reserved_37; 996 997 volatile __le32 RDBaseLo; /* 0x38 */ 998 volatile __le16 RDIdx; /* 0x3C */ 999 volatile u8 TQETMR; /* 0x3E, VT3216 and above only */ 1000 volatile u8 RQETMR; /* 0x3F, VT3216 and above only */ 1001 1002 volatile __le32 TDBaseLo[4]; /* 0x40 */ 1003 1004 volatile __le16 RDCSize; /* 0x50 */ 1005 volatile __le16 TDCSize; /* 0x52 */ 1006 volatile __le16 TDIdx[4]; /* 0x54 */ 1007 volatile __le16 tx_pause_timer; /* 0x5C */ 1008 volatile __le16 RBRDU; /* 0x5E */ 1009 1010 volatile __le32 FIFOTest0; /* 0x60 */ 1011 volatile __le32 FIFOTest1; /* 0x64 */ 1012 1013 volatile u8 CAMADDR; /* 0x68 */ 1014 volatile u8 CAMCR; /* 0x69 */ 1015 volatile u8 GFTEST; /* 0x6A */ 1016 volatile u8 FTSTCMD; /* 0x6B */ 1017 1018 volatile u8 MIICFG; /* 0x6C */ 1019 volatile u8 MIISR; 1020 volatile u8 PHYSR0; 1021 volatile u8 PHYSR1; 1022 volatile u8 MIICR; 1023 volatile u8 MIIADR; 1024 volatile __le16 MIIDATA; 1025 1026 volatile __le16 SoftTimer0; /* 0x74 */ 1027 volatile __le16 SoftTimer1; 1028 1029 volatile u8 CFGA; /* 0x78 */ 1030 volatile u8 CFGB; 1031 volatile u8 CFGC; 1032 volatile u8 CFGD; 1033 1034 volatile __le16 DCFG; /* 0x7C */ 1035 volatile __le16 MCFG; 1036 1037 volatile u8 TBIST; /* 0x80 */ 1038 volatile u8 RBIST; 1039 volatile u8 PMCPORT; 1040 volatile u8 STICKHW; 1041 1042 volatile u8 MIBCR; /* 0x84 */ 1043 volatile u8 reserved_85; 1044 volatile u8 rev_id; 1045 volatile u8 PORSTS; 1046 1047 volatile __le32 MIBData; /* 0x88 */ 1048 1049 volatile __le16 EEWrData; 1050 1051 volatile u8 reserved_8E; 1052 volatile u8 BPMDWr; 1053 volatile u8 BPCMD; 1054 volatile u8 BPMDRd; 1055 1056 volatile u8 EECHKSUM; /* 0x92 */ 1057 volatile u8 EECSR; 1058 1059 volatile __le16 EERdData; /* 0x94 */ 1060 volatile u8 EADDR; 1061 volatile u8 EMBCMD; 1062 1063 1064 volatile u8 JMPSR0; /* 0x98 */ 1065 volatile u8 JMPSR1; 1066 volatile u8 JMPSR2; 1067 volatile u8 JMPSR3; 1068 volatile u8 CHIPGSR; /* 0x9C */ 1069 volatile u8 TESTCFG; 1070 volatile u8 DEBUG; 1071 volatile u8 CHIPGCR; 1072 1073 volatile __le16 WOLCRSet; /* 0xA0 */ 1074 volatile u8 PWCFGSet; 1075 volatile u8 WOLCFGSet; 1076 1077 volatile __le16 WOLCRClr; /* 0xA4 */ 1078 volatile u8 PWCFGCLR; 1079 volatile u8 WOLCFGClr; 1080 1081 volatile __le16 WOLSRSet; /* 0xA8 */ 1082 volatile __le16 reserved_AA; 1083 1084 volatile __le16 WOLSRClr; /* 0xAC */ 1085 volatile __le16 reserved_AE; 1086 1087 volatile __le16 PatternCRC[8]; /* 0xB0 */ 1088 volatile __le32 ByteMask[4][4]; /* 0xC0 */ 1089 }; 1090 1091 1092 enum hw_mib { 1093 HW_MIB_ifRxAllPkts = 0, 1094 HW_MIB_ifRxOkPkts, 1095 HW_MIB_ifTxOkPkts, 1096 HW_MIB_ifRxErrorPkts, 1097 HW_MIB_ifRxRuntOkPkt, 1098 HW_MIB_ifRxRuntErrPkt, 1099 HW_MIB_ifRx64Pkts, 1100 HW_MIB_ifTx64Pkts, 1101 HW_MIB_ifRx65To127Pkts, 1102 HW_MIB_ifTx65To127Pkts, 1103 HW_MIB_ifRx128To255Pkts, 1104 HW_MIB_ifTx128To255Pkts, 1105 HW_MIB_ifRx256To511Pkts, 1106 HW_MIB_ifTx256To511Pkts, 1107 HW_MIB_ifRx512To1023Pkts, 1108 HW_MIB_ifTx512To1023Pkts, 1109 HW_MIB_ifRx1024To1518Pkts, 1110 HW_MIB_ifTx1024To1518Pkts, 1111 HW_MIB_ifTxEtherCollisions, 1112 HW_MIB_ifRxPktCRCE, 1113 HW_MIB_ifRxJumboPkts, 1114 HW_MIB_ifTxJumboPkts, 1115 HW_MIB_ifRxMacControlFrames, 1116 HW_MIB_ifTxMacControlFrames, 1117 HW_MIB_ifRxPktFAE, 1118 HW_MIB_ifRxLongOkPkt, 1119 HW_MIB_ifRxLongPktErrPkt, 1120 HW_MIB_ifTXSQEErrors, 1121 HW_MIB_ifRxNobuf, 1122 HW_MIB_ifRxSymbolErrors, 1123 HW_MIB_ifInRangeLengthErrors, 1124 HW_MIB_ifLateCollisions, 1125 HW_MIB_SIZE 1126 }; 1127 1128 enum chip_type { 1129 CHIP_TYPE_VT6110 = 1, 1130 }; 1131 1132 struct velocity_info_tbl { 1133 enum chip_type chip_id; 1134 const char *name; 1135 int txqueue; 1136 u32 flags; 1137 }; 1138 1139 #define mac_hw_mibs_init(regs) {\ 1140 BYTE_REG_BITS_ON(MIBCR_MIBFRZ,&((regs)->MIBCR));\ 1141 BYTE_REG_BITS_ON(MIBCR_MIBCLR,&((regs)->MIBCR));\ 1142 do {}\ 1143 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBCLR,&((regs)->MIBCR)));\ 1144 BYTE_REG_BITS_OFF(MIBCR_MIBFRZ,&((regs)->MIBCR));\ 1145 } 1146 1147 #define mac_read_isr(regs) readl(&((regs)->ISR)) 1148 #define mac_write_isr(regs, x) writel((x),&((regs)->ISR)) 1149 #define mac_clear_isr(regs) writel(0xffffffffL,&((regs)->ISR)) 1150 1151 #define mac_write_int_mask(mask, regs) writel((mask),&((regs)->IMR)); 1152 #define mac_disable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Clr)) 1153 #define mac_enable_int(regs) writel(CR0_GINTMSK1,&((regs)->CR0Set)) 1154 1155 #define mac_set_dma_length(regs, n) {\ 1156 BYTE_REG_BITS_SET((n),0x07,&((regs)->DCFG));\ 1157 } 1158 1159 #define mac_set_rx_thresh(regs, n) {\ 1160 BYTE_REG_BITS_SET((n),(MCFG_RFT0|MCFG_RFT1),&((regs)->MCFG));\ 1161 } 1162 1163 #define mac_rx_queue_run(regs) {\ 1164 writeb(TRDCSR_RUN, &((regs)->RDCSRSet));\ 1165 } 1166 1167 #define mac_rx_queue_wake(regs) {\ 1168 writeb(TRDCSR_WAK, &((regs)->RDCSRSet));\ 1169 } 1170 1171 #define mac_tx_queue_run(regs, n) {\ 1172 writew(TRDCSR_RUN<<((n)*4),&((regs)->TDCSRSet));\ 1173 } 1174 1175 #define mac_tx_queue_wake(regs, n) {\ 1176 writew(TRDCSR_WAK<<(n*4),&((regs)->TDCSRSet));\ 1177 } 1178 1179 static inline void mac_eeprom_reload(struct mac_regs __iomem * regs) { 1180 int i=0; 1181 1182 BYTE_REG_BITS_ON(EECSR_RELOAD,&(regs->EECSR)); 1183 do { 1184 udelay(10); 1185 if (i++>0x1000) 1186 break; 1187 } while (BYTE_REG_BITS_IS_ON(EECSR_RELOAD,&(regs->EECSR))); 1188 } 1189 1190 /* 1191 * Header for WOL definitions. Used to compute hashes 1192 */ 1193 1194 typedef u8 MCAM_ADDR[ETH_ALEN]; 1195 1196 struct arp_packet { 1197 u8 dest_mac[ETH_ALEN]; 1198 u8 src_mac[ETH_ALEN]; 1199 __be16 type; 1200 __be16 ar_hrd; 1201 __be16 ar_pro; 1202 u8 ar_hln; 1203 u8 ar_pln; 1204 __be16 ar_op; 1205 u8 ar_sha[ETH_ALEN]; 1206 u8 ar_sip[4]; 1207 u8 ar_tha[ETH_ALEN]; 1208 u8 ar_tip[4]; 1209 } __packed; 1210 1211 struct _magic_packet { 1212 u8 dest_mac[6]; 1213 u8 src_mac[6]; 1214 __be16 type; 1215 u8 MAC[16][6]; 1216 u8 password[6]; 1217 } __packed; 1218 1219 /* 1220 * Store for chip context when saving and restoring status. Not 1221 * all fields are saved/restored currently. 1222 */ 1223 1224 struct velocity_context { 1225 u8 mac_reg[256]; 1226 MCAM_ADDR cam_addr[MCAM_SIZE]; 1227 u16 vcam[VCAM_SIZE]; 1228 u32 cammask[2]; 1229 u32 patcrc[2]; 1230 u32 pattern[8]; 1231 }; 1232 1233 /* 1234 * Registers in the MII (offset unit is WORD) 1235 */ 1236 1237 // Marvell 88E1000/88E1000S 1238 #define MII_REG_PSCR 0x10 // PHY specific control register 1239 1240 // 1241 // Bits in the Silicon revision register 1242 // 1243 1244 #define TCSR_ECHODIS 0x2000 // 1245 #define AUXCR_MDPPS 0x0004 // 1246 1247 // Bits in the PLED register 1248 #define PLED_LALBE 0x0004 // 1249 1250 // Marvell 88E1000/88E1000S Bits in the PHY specific control register (10h) 1251 #define PSCR_ACRSTX 0x0800 // Assert CRS on Transmit 1252 1253 #define PHYID_CICADA_CS8201 0x000FC410UL 1254 #define PHYID_VT3216_32BIT 0x000FC610UL 1255 #define PHYID_VT3216_64BIT 0x000FC600UL 1256 #define PHYID_MARVELL_1000 0x01410C50UL 1257 #define PHYID_MARVELL_1000S 0x01410C40UL 1258 #define PHYID_ICPLUS_IP101A 0x02430C54UL 1259 #define PHYID_REV_ID_MASK 0x0000000FUL 1260 1261 #define PHYID_GET_PHY_ID(i) ((i) & ~PHYID_REV_ID_MASK) 1262 1263 #define MII_REG_BITS_ON(x,i,p) do {\ 1264 u16 w;\ 1265 velocity_mii_read((p),(i),&(w));\ 1266 (w)|=(x);\ 1267 velocity_mii_write((p),(i),(w));\ 1268 } while (0) 1269 1270 #define MII_REG_BITS_OFF(x,i,p) do {\ 1271 u16 w;\ 1272 velocity_mii_read((p),(i),&(w));\ 1273 (w)&=(~(x));\ 1274 velocity_mii_write((p),(i),(w));\ 1275 } while (0) 1276 1277 #define MII_REG_BITS_IS_ON(x,i,p) ({\ 1278 u16 w;\ 1279 velocity_mii_read((p),(i),&(w));\ 1280 ((int) ((w) & (x)));}) 1281 1282 #define MII_GET_PHY_ID(p) ({\ 1283 u32 id;\ 1284 velocity_mii_read((p),MII_PHYSID2,(u16 *) &id);\ 1285 velocity_mii_read((p),MII_PHYSID1,((u16 *) &id)+1);\ 1286 (id);}) 1287 1288 #define VELOCITY_WOL_MAGIC 0x00000000UL 1289 #define VELOCITY_WOL_PHY 0x00000001UL 1290 #define VELOCITY_WOL_ARP 0x00000002UL 1291 #define VELOCITY_WOL_UCAST 0x00000004UL 1292 #define VELOCITY_WOL_BCAST 0x00000010UL 1293 #define VELOCITY_WOL_MCAST 0x00000020UL 1294 #define VELOCITY_WOL_MAGIC_SEC 0x00000040UL 1295 1296 /* 1297 * Flags for options 1298 */ 1299 1300 #define VELOCITY_FLAGS_TAGGING 0x00000001UL 1301 #define VELOCITY_FLAGS_RX_CSUM 0x00000004UL 1302 #define VELOCITY_FLAGS_IP_ALIGN 0x00000008UL 1303 #define VELOCITY_FLAGS_VAL_PKT_LEN 0x00000010UL 1304 1305 #define VELOCITY_FLAGS_FLOW_CTRL 0x01000000UL 1306 1307 /* 1308 * Flags for driver status 1309 */ 1310 1311 #define VELOCITY_FLAGS_OPENED 0x00010000UL 1312 #define VELOCITY_FLAGS_VMNS_CONNECTED 0x00020000UL 1313 #define VELOCITY_FLAGS_VMNS_COMMITTED 0x00040000UL 1314 #define VELOCITY_FLAGS_WOL_ENABLED 0x00080000UL 1315 1316 /* 1317 * Flags for MII status 1318 */ 1319 1320 #define VELOCITY_LINK_FAIL 0x00000001UL 1321 #define VELOCITY_SPEED_10 0x00000002UL 1322 #define VELOCITY_SPEED_100 0x00000004UL 1323 #define VELOCITY_SPEED_1000 0x00000008UL 1324 #define VELOCITY_DUPLEX_FULL 0x00000010UL 1325 #define VELOCITY_AUTONEG_ENABLE 0x00000020UL 1326 #define VELOCITY_FORCED_BY_EEPROM 0x00000040UL 1327 1328 /* 1329 * For velocity_set_media_duplex 1330 */ 1331 1332 #define VELOCITY_LINK_CHANGE 0x00000001UL 1333 1334 enum speed_opt { 1335 SPD_DPX_AUTO = 0, 1336 SPD_DPX_100_HALF = 1, 1337 SPD_DPX_100_FULL = 2, 1338 SPD_DPX_10_HALF = 3, 1339 SPD_DPX_10_FULL = 4, 1340 SPD_DPX_1000_FULL = 5 1341 }; 1342 1343 enum velocity_init_type { 1344 VELOCITY_INIT_COLD = 0, 1345 VELOCITY_INIT_RESET, 1346 VELOCITY_INIT_WOL 1347 }; 1348 1349 enum velocity_flow_cntl_type { 1350 FLOW_CNTL_DEFAULT = 1, 1351 FLOW_CNTL_TX, 1352 FLOW_CNTL_RX, 1353 FLOW_CNTL_TX_RX, 1354 FLOW_CNTL_DISABLE, 1355 }; 1356 1357 struct velocity_opt { 1358 int numrx; /* Number of RX descriptors */ 1359 int numtx; /* Number of TX descriptors */ 1360 enum speed_opt spd_dpx; /* Media link mode */ 1361 1362 int DMA_length; /* DMA length */ 1363 int rx_thresh; /* RX_THRESH */ 1364 int flow_cntl; 1365 int wol_opts; /* Wake on lan options */ 1366 int td_int_count; 1367 int int_works; 1368 int rx_bandwidth_hi; 1369 int rx_bandwidth_lo; 1370 int rx_bandwidth_en; 1371 int rxqueue_timer; 1372 int txqueue_timer; 1373 int tx_intsup; 1374 int rx_intsup; 1375 u32 flags; 1376 }; 1377 1378 #define AVAIL_TD(p,q) ((p)->options.numtx-((p)->tx.used[(q)])) 1379 1380 #define GET_RD_BY_IDX(vptr, idx) (vptr->rd_ring[idx]) 1381 1382 struct velocity_info { 1383 struct device *dev; 1384 struct pci_dev *pdev; 1385 struct net_device *netdev; 1386 bool no_eeprom; 1387 1388 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 1389 u8 ip_addr[4]; 1390 enum chip_type chip_id; 1391 1392 struct mac_regs __iomem * mac_regs; 1393 unsigned long memaddr; 1394 unsigned long ioaddr; 1395 1396 struct tx_info { 1397 int numq; 1398 1399 /* FIXME: the locality of the data seems rather poor. */ 1400 int used[TX_QUEUE_NO]; 1401 int curr[TX_QUEUE_NO]; 1402 int tail[TX_QUEUE_NO]; 1403 struct tx_desc *rings[TX_QUEUE_NO]; 1404 struct velocity_td_info *infos[TX_QUEUE_NO]; 1405 dma_addr_t pool_dma[TX_QUEUE_NO]; 1406 } tx; 1407 1408 struct rx_info { 1409 int buf_sz; 1410 1411 int dirty; 1412 int curr; 1413 u32 filled; 1414 struct rx_desc *ring; 1415 struct velocity_rd_info *info; /* It's an array */ 1416 dma_addr_t pool_dma; 1417 } rx; 1418 1419 u32 mib_counter[MAX_HW_MIB_COUNTER]; 1420 struct velocity_opt options; 1421 1422 u32 int_mask; 1423 1424 u32 flags; 1425 1426 u32 mii_status; 1427 u32 phy_id; 1428 int multicast_limit; 1429 1430 u8 vCAMmask[(VCAM_SIZE / 8)]; 1431 u8 mCAMmask[(MCAM_SIZE / 8)]; 1432 1433 spinlock_t lock; 1434 1435 int wol_opts; 1436 u8 wol_passwd[6]; 1437 1438 struct velocity_context context; 1439 1440 u32 ticks; 1441 u32 ethtool_ops_nesting; 1442 1443 u8 rev_id; 1444 1445 struct napi_struct napi; 1446 }; 1447 1448 /** 1449 * velocity_get_ip - find an IP address for the device 1450 * @vptr: Velocity to query 1451 * 1452 * Dig out an IP address for this interface so that we can 1453 * configure wakeup with WOL for ARP. If there are multiple IP 1454 * addresses on this chain then we use the first - multi-IP WOL is not 1455 * supported. 1456 * 1457 */ 1458 1459 static inline int velocity_get_ip(struct velocity_info *vptr) 1460 { 1461 struct in_device *in_dev; 1462 struct in_ifaddr *ifa; 1463 int res = -ENOENT; 1464 1465 rcu_read_lock(); 1466 in_dev = __in_dev_get_rcu(vptr->netdev); 1467 if (in_dev != NULL) { 1468 ifa = rcu_dereference(in_dev->ifa_list); 1469 if (ifa != NULL) { 1470 memcpy(vptr->ip_addr, &ifa->ifa_address, 4); 1471 res = 0; 1472 } 1473 } 1474 rcu_read_unlock(); 1475 return res; 1476 } 1477 1478 /** 1479 * velocity_update_hw_mibs - fetch MIB counters from chip 1480 * @vptr: velocity to update 1481 * 1482 * The velocity hardware keeps certain counters in the hardware 1483 * side. We need to read these when the user asks for statistics 1484 * or when they overflow (causing an interrupt). The read of the 1485 * statistic clears it, so we keep running master counters in user 1486 * space. 1487 */ 1488 1489 static inline void velocity_update_hw_mibs(struct velocity_info *vptr) 1490 { 1491 u32 tmp; 1492 int i; 1493 BYTE_REG_BITS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR)); 1494 1495 while (BYTE_REG_BITS_IS_ON(MIBCR_MIBFLSH, &(vptr->mac_regs->MIBCR))); 1496 1497 BYTE_REG_BITS_ON(MIBCR_MPTRINI, &(vptr->mac_regs->MIBCR)); 1498 for (i = 0; i < HW_MIB_SIZE; i++) { 1499 tmp = readl(&(vptr->mac_regs->MIBData)) & 0x00FFFFFFUL; 1500 vptr->mib_counter[i] += tmp; 1501 } 1502 } 1503 1504 /** 1505 * init_flow_control_register - set up flow control 1506 * @vptr: velocity to configure 1507 * 1508 * Configure the flow control registers for this velocity device. 1509 */ 1510 1511 static inline void init_flow_control_register(struct velocity_info *vptr) 1512 { 1513 struct mac_regs __iomem * regs = vptr->mac_regs; 1514 1515 /* Set {XHITH1, XHITH0, XLTH1, XLTH0} in FlowCR1 to {1, 0, 1, 1} 1516 depend on RD=64, and Turn on XNOEN in FlowCR1 */ 1517 writel((CR0_XONEN | CR0_XHITH1 | CR0_XLTH1 | CR0_XLTH0), ®s->CR0Set); 1518 writel((CR0_FDXTFCEN | CR0_FDXRFCEN | CR0_HDXFCEN | CR0_XHITH0), ®s->CR0Clr); 1519 1520 /* Set TxPauseTimer to 0xFFFF */ 1521 writew(0xFFFF, ®s->tx_pause_timer); 1522 1523 /* Initialize RBRDU to Rx buffer count. */ 1524 writew(vptr->options.numrx, ®s->RBRDU); 1525 } 1526 1527 1528 #endif 1529