1 /* 2 * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux. 3 * 4 * Based on skelton.c by Donald Becker. 5 * 6 * This driver is a replacement of older and less maintained version. 7 * This is a header of the older version: 8 * -----<snip>----- 9 * Copyright 2001 MontaVista Software Inc. 10 * Author: MontaVista Software, Inc. 11 * ahennessy@mvista.com 12 * Copyright (C) 2000-2001 Toshiba Corporation 13 * static const char *version = 14 * "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n"; 15 * -----<snip>----- 16 * 17 * This file is subject to the terms and conditions of the GNU General Public 18 * License. See the file "COPYING" in the main directory of this archive 19 * for more details. 20 * 21 * (C) Copyright TOSHIBA CORPORATION 2004-2005 22 * All Rights Reserved. 23 */ 24 25 #define DRV_VERSION "1.39" 26 static const char *version = "tc35815.c:v" DRV_VERSION "\n"; 27 #define MODNAME "tc35815" 28 29 #include <linux/module.h> 30 #include <linux/kernel.h> 31 #include <linux/types.h> 32 #include <linux/fcntl.h> 33 #include <linux/interrupt.h> 34 #include <linux/ioport.h> 35 #include <linux/in.h> 36 #include <linux/if_vlan.h> 37 #include <linux/slab.h> 38 #include <linux/string.h> 39 #include <linux/spinlock.h> 40 #include <linux/errno.h> 41 #include <linux/init.h> 42 #include <linux/netdevice.h> 43 #include <linux/etherdevice.h> 44 #include <linux/skbuff.h> 45 #include <linux/delay.h> 46 #include <linux/pci.h> 47 #include <linux/phy.h> 48 #include <linux/workqueue.h> 49 #include <linux/platform_device.h> 50 #include <linux/prefetch.h> 51 #include <asm/io.h> 52 #include <asm/byteorder.h> 53 54 enum tc35815_chiptype { 55 TC35815CF = 0, 56 TC35815_NWU, 57 TC35815_TX4939, 58 }; 59 60 /* indexed by tc35815_chiptype, above */ 61 static const struct { 62 const char *name; 63 } chip_info[] = { 64 { "TOSHIBA TC35815CF 10/100BaseTX" }, 65 { "TOSHIBA TC35815 with Wake on LAN" }, 66 { "TOSHIBA TC35815/TX4939" }, 67 }; 68 69 static DEFINE_PCI_DEVICE_TABLE(tc35815_pci_tbl) = { 70 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF }, 71 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU }, 72 {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 }, 73 {0,} 74 }; 75 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl); 76 77 /* see MODULE_PARM_DESC */ 78 static struct tc35815_options { 79 int speed; 80 int duplex; 81 } options; 82 83 /* 84 * Registers 85 */ 86 struct tc35815_regs { 87 __u32 DMA_Ctl; /* 0x00 */ 88 __u32 TxFrmPtr; 89 __u32 TxThrsh; 90 __u32 TxPollCtr; 91 __u32 BLFrmPtr; 92 __u32 RxFragSize; 93 __u32 Int_En; 94 __u32 FDA_Bas; 95 __u32 FDA_Lim; /* 0x20 */ 96 __u32 Int_Src; 97 __u32 unused0[2]; 98 __u32 PauseCnt; 99 __u32 RemPauCnt; 100 __u32 TxCtlFrmStat; 101 __u32 unused1; 102 __u32 MAC_Ctl; /* 0x40 */ 103 __u32 CAM_Ctl; 104 __u32 Tx_Ctl; 105 __u32 Tx_Stat; 106 __u32 Rx_Ctl; 107 __u32 Rx_Stat; 108 __u32 MD_Data; 109 __u32 MD_CA; 110 __u32 CAM_Adr; /* 0x60 */ 111 __u32 CAM_Data; 112 __u32 CAM_Ena; 113 __u32 PROM_Ctl; 114 __u32 PROM_Data; 115 __u32 Algn_Cnt; 116 __u32 CRC_Cnt; 117 __u32 Miss_Cnt; 118 }; 119 120 /* 121 * Bit assignments 122 */ 123 /* DMA_Ctl bit assign ------------------------------------------------------- */ 124 #define DMA_RxAlign 0x00c00000 /* 1:Reception Alignment */ 125 #define DMA_RxAlign_1 0x00400000 126 #define DMA_RxAlign_2 0x00800000 127 #define DMA_RxAlign_3 0x00c00000 128 #define DMA_M66EnStat 0x00080000 /* 1:66MHz Enable State */ 129 #define DMA_IntMask 0x00040000 /* 1:Interrupt mask */ 130 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */ 131 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */ 132 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */ 133 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */ 134 #define DMA_TestMode 0x00002000 /* 1:Test Mode */ 135 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */ 136 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */ 137 138 /* RxFragSize bit assign ---------------------------------------------------- */ 139 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */ 140 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */ 141 142 /* MAC_Ctl bit assign ------------------------------------------------------- */ 143 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */ 144 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */ 145 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */ 146 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */ 147 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */ 148 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/ 149 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */ 150 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */ 151 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */ 152 #define MAC_Reset 0x00000004 /* 1:Software Reset */ 153 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */ 154 #define MAC_HaltReq 0x00000001 /* 1:Halt request */ 155 156 /* PROM_Ctl bit assign ------------------------------------------------------ */ 157 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */ 158 #define PROM_Read 0x00004000 /*10:Read operation */ 159 #define PROM_Write 0x00002000 /*01:Write operation */ 160 #define PROM_Erase 0x00006000 /*11:Erase operation */ 161 /*00:Enable or Disable Writting, */ 162 /* as specified in PROM_Addr. */ 163 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */ 164 /*00xxxx: disable */ 165 166 /* CAM_Ctl bit assign ------------------------------------------------------- */ 167 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */ 168 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/ 169 /* accept other */ 170 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */ 171 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */ 172 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */ 173 174 /* CAM_Ena bit assign ------------------------------------------------------- */ 175 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */ 176 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */ 177 #define CAM_Ena_Bit(index) (1 << (index)) 178 #define CAM_ENTRY_DESTINATION 0 179 #define CAM_ENTRY_SOURCE 1 180 #define CAM_ENTRY_MACCTL 20 181 182 /* Tx_Ctl bit assign -------------------------------------------------------- */ 183 #define Tx_En 0x00000001 /* 1:Transmit enable */ 184 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */ 185 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */ 186 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */ 187 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */ 188 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */ 189 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */ 190 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */ 191 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */ 192 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */ 193 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */ 194 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */ 195 196 /* Tx_Stat bit assign ------------------------------------------------------- */ 197 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */ 198 #define Tx_ExColl 0x00000010 /* Excessive Collision */ 199 #define Tx_TXDefer 0x00000020 /* Transmit Defered */ 200 #define Tx_Paused 0x00000040 /* Transmit Paused */ 201 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */ 202 #define Tx_Under 0x00000100 /* Underrun */ 203 #define Tx_Defer 0x00000200 /* Deferral */ 204 #define Tx_NCarr 0x00000400 /* No Carrier */ 205 #define Tx_10Stat 0x00000800 /* 10Mbps Status */ 206 #define Tx_LateColl 0x00001000 /* Late Collision */ 207 #define Tx_TxPar 0x00002000 /* Tx Parity Error */ 208 #define Tx_Comp 0x00004000 /* Completion */ 209 #define Tx_Halted 0x00008000 /* Tx Halted */ 210 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */ 211 212 /* Rx_Ctl bit assign -------------------------------------------------------- */ 213 #define Rx_EnGood 0x00004000 /* 1:Enable Good */ 214 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */ 215 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */ 216 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */ 217 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */ 218 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */ 219 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */ 220 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */ 221 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */ 222 #define Rx_LongEn 0x00000004 /* 1:Long Enable */ 223 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */ 224 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */ 225 226 /* Rx_Stat bit assign ------------------------------------------------------- */ 227 #define Rx_Halted 0x00008000 /* Rx Halted */ 228 #define Rx_Good 0x00004000 /* Rx Good */ 229 #define Rx_RxPar 0x00002000 /* Rx Parity Error */ 230 #define Rx_TypePkt 0x00001000 /* Rx Type Packet */ 231 #define Rx_LongErr 0x00000800 /* Rx Long Error */ 232 #define Rx_Over 0x00000400 /* Rx Overflow */ 233 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */ 234 #define Rx_Align 0x00000100 /* Rx Alignment Error */ 235 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */ 236 #define Rx_IntRx 0x00000040 /* Rx Interrupt */ 237 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */ 238 #define Rx_InLenErr 0x00000010 /* Rx In Range Frame Length Error */ 239 240 #define Rx_Stat_Mask 0x0000FFF0 /* Rx All Status Mask */ 241 242 /* Int_En bit assign -------------------------------------------------------- */ 243 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */ 244 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Ctl Complete Enable */ 245 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */ 246 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */ 247 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */ 248 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */ 249 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */ 250 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */ 251 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */ 252 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */ 253 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */ 254 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */ 255 /* Exhausted Enable */ 256 257 /* Int_Src bit assign ------------------------------------------------------- */ 258 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */ 259 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */ 260 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */ 261 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */ 262 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */ 263 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */ 264 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */ 265 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */ 266 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */ 267 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */ 268 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */ 269 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */ 270 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */ 271 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */ 272 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */ 273 274 /* MD_CA bit assign --------------------------------------------------------- */ 275 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Suppress */ 276 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */ 277 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */ 278 279 280 /* 281 * Descriptors 282 */ 283 284 /* Frame descripter */ 285 struct FDesc { 286 volatile __u32 FDNext; 287 volatile __u32 FDSystem; 288 volatile __u32 FDStat; 289 volatile __u32 FDCtl; 290 }; 291 292 /* Buffer descripter */ 293 struct BDesc { 294 volatile __u32 BuffData; 295 volatile __u32 BDCtl; 296 }; 297 298 #define FD_ALIGN 16 299 300 /* Frame Descripter bit assign ---------------------------------------------- */ 301 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */ 302 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */ 303 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */ 304 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */ 305 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */ 306 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */ 307 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */ 308 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */ 309 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */ 310 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */ 311 #define FD_BDCnt_SHIFT 16 312 313 /* Buffer Descripter bit assign --------------------------------------------- */ 314 #define BD_BuffLength_MASK 0x0000FFFF /* Receive Data Size */ 315 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */ 316 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */ 317 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */ 318 #define BD_RxBDID_SHIFT 16 319 #define BD_RxBDSeqN_SHIFT 24 320 321 322 /* Some useful constants. */ 323 324 #define TX_CTL_CMD (Tx_EnTxPar | Tx_EnLateColl | \ 325 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \ 326 Tx_En) /* maybe 0x7b01 */ 327 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */ 328 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \ 329 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */ 330 #define INT_EN_CMD (Int_NRAbtEn | \ 331 Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \ 332 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \ 333 Int_STargAbtEn | \ 334 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/ 335 #define DMA_CTL_CMD DMA_BURST_SIZE 336 #define HAVE_DMA_RXALIGN(lp) likely((lp)->chiptype != TC35815CF) 337 338 /* Tuning parameters */ 339 #define DMA_BURST_SIZE 32 340 #define TX_THRESHOLD 1024 341 /* used threshold with packet max byte for low pci transfer ability.*/ 342 #define TX_THRESHOLD_MAX 1536 343 /* setting threshold max value when overrun error occurred this count. */ 344 #define TX_THRESHOLD_KEEP_LIMIT 10 345 346 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */ 347 #define FD_PAGE_NUM 4 348 #define RX_BUF_NUM 128 /* < 256 */ 349 #define RX_FD_NUM 256 /* >= 32 */ 350 #define TX_FD_NUM 128 351 #if RX_CTL_CMD & Rx_LongEn 352 #define RX_BUF_SIZE PAGE_SIZE 353 #elif RX_CTL_CMD & Rx_StripCRC 354 #define RX_BUF_SIZE \ 355 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN) 356 #else 357 #define RX_BUF_SIZE \ 358 L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN) 359 #endif 360 #define RX_FD_RESERVE (2 / 2) /* max 2 BD per RxFD */ 361 #define NAPI_WEIGHT 16 362 363 struct TxFD { 364 struct FDesc fd; 365 struct BDesc bd; 366 struct BDesc unused; 367 }; 368 369 struct RxFD { 370 struct FDesc fd; 371 struct BDesc bd[0]; /* variable length */ 372 }; 373 374 struct FrFD { 375 struct FDesc fd; 376 struct BDesc bd[RX_BUF_NUM]; 377 }; 378 379 380 #define tc_readl(addr) ioread32(addr) 381 #define tc_writel(d, addr) iowrite32(d, addr) 382 383 #define TC35815_TX_TIMEOUT msecs_to_jiffies(400) 384 385 /* Information that need to be kept for each controller. */ 386 struct tc35815_local { 387 struct pci_dev *pci_dev; 388 389 struct net_device *dev; 390 struct napi_struct napi; 391 392 /* statistics */ 393 struct { 394 int max_tx_qlen; 395 int tx_ints; 396 int rx_ints; 397 int tx_underrun; 398 } lstats; 399 400 /* Tx control lock. This protects the transmit buffer ring 401 * state along with the "tx full" state of the driver. This 402 * means all netif_queue flow control actions are protected 403 * by this lock as well. 404 */ 405 spinlock_t lock; 406 spinlock_t rx_lock; 407 408 struct mii_bus *mii_bus; 409 struct phy_device *phy_dev; 410 int duplex; 411 int speed; 412 int link; 413 struct work_struct restart_work; 414 415 /* 416 * Transmitting: Batch Mode. 417 * 1 BD in 1 TxFD. 418 * Receiving: Non-Packing Mode. 419 * 1 circular FD for Free Buffer List. 420 * RX_BUF_NUM BD in Free Buffer FD. 421 * One Free Buffer BD has ETH_FRAME_LEN data buffer. 422 */ 423 void *fd_buf; /* for TxFD, RxFD, FrFD */ 424 dma_addr_t fd_buf_dma; 425 struct TxFD *tfd_base; 426 unsigned int tfd_start; 427 unsigned int tfd_end; 428 struct RxFD *rfd_base; 429 struct RxFD *rfd_limit; 430 struct RxFD *rfd_cur; 431 struct FrFD *fbl_ptr; 432 unsigned int fbl_count; 433 struct { 434 struct sk_buff *skb; 435 dma_addr_t skb_dma; 436 } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM]; 437 u32 msg_enable; 438 enum tc35815_chiptype chiptype; 439 }; 440 441 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt) 442 { 443 return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf); 444 } 445 #ifdef DEBUG 446 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus) 447 { 448 return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma)); 449 } 450 #endif 451 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev, 452 struct pci_dev *hwdev, 453 dma_addr_t *dma_handle) 454 { 455 struct sk_buff *skb; 456 skb = netdev_alloc_skb(dev, RX_BUF_SIZE); 457 if (!skb) 458 return NULL; 459 *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE, 460 PCI_DMA_FROMDEVICE); 461 if (pci_dma_mapping_error(hwdev, *dma_handle)) { 462 dev_kfree_skb_any(skb); 463 return NULL; 464 } 465 skb_reserve(skb, 2); /* make IP header 4byte aligned */ 466 return skb; 467 } 468 469 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle) 470 { 471 pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE, 472 PCI_DMA_FROMDEVICE); 473 dev_kfree_skb_any(skb); 474 } 475 476 /* Index to functions, as function prototypes. */ 477 478 static int tc35815_open(struct net_device *dev); 479 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev); 480 static irqreturn_t tc35815_interrupt(int irq, void *dev_id); 481 static int tc35815_rx(struct net_device *dev, int limit); 482 static int tc35815_poll(struct napi_struct *napi, int budget); 483 static void tc35815_txdone(struct net_device *dev); 484 static int tc35815_close(struct net_device *dev); 485 static struct net_device_stats *tc35815_get_stats(struct net_device *dev); 486 static void tc35815_set_multicast_list(struct net_device *dev); 487 static void tc35815_tx_timeout(struct net_device *dev); 488 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 489 #ifdef CONFIG_NET_POLL_CONTROLLER 490 static void tc35815_poll_controller(struct net_device *dev); 491 #endif 492 static const struct ethtool_ops tc35815_ethtool_ops; 493 494 /* Example routines you must write ;->. */ 495 static void tc35815_chip_reset(struct net_device *dev); 496 static void tc35815_chip_init(struct net_device *dev); 497 498 #ifdef DEBUG 499 static void panic_queues(struct net_device *dev); 500 #endif 501 502 static void tc35815_restart_work(struct work_struct *work); 503 504 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 505 { 506 struct net_device *dev = bus->priv; 507 struct tc35815_regs __iomem *tr = 508 (struct tc35815_regs __iomem *)dev->base_addr; 509 unsigned long timeout = jiffies + HZ; 510 511 tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA); 512 udelay(12); /* it takes 32 x 400ns at least */ 513 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { 514 if (time_after(jiffies, timeout)) 515 return -EIO; 516 cpu_relax(); 517 } 518 return tc_readl(&tr->MD_Data) & 0xffff; 519 } 520 521 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val) 522 { 523 struct net_device *dev = bus->priv; 524 struct tc35815_regs __iomem *tr = 525 (struct tc35815_regs __iomem *)dev->base_addr; 526 unsigned long timeout = jiffies + HZ; 527 528 tc_writel(val, &tr->MD_Data); 529 tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f), 530 &tr->MD_CA); 531 udelay(12); /* it takes 32 x 400ns at least */ 532 while (tc_readl(&tr->MD_CA) & MD_CA_Busy) { 533 if (time_after(jiffies, timeout)) 534 return -EIO; 535 cpu_relax(); 536 } 537 return 0; 538 } 539 540 static void tc_handle_link_change(struct net_device *dev) 541 { 542 struct tc35815_local *lp = netdev_priv(dev); 543 struct phy_device *phydev = lp->phy_dev; 544 unsigned long flags; 545 int status_change = 0; 546 547 spin_lock_irqsave(&lp->lock, flags); 548 if (phydev->link && 549 (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) { 550 struct tc35815_regs __iomem *tr = 551 (struct tc35815_regs __iomem *)dev->base_addr; 552 u32 reg; 553 554 reg = tc_readl(&tr->MAC_Ctl); 555 reg |= MAC_HaltReq; 556 tc_writel(reg, &tr->MAC_Ctl); 557 if (phydev->duplex == DUPLEX_FULL) 558 reg |= MAC_FullDup; 559 else 560 reg &= ~MAC_FullDup; 561 tc_writel(reg, &tr->MAC_Ctl); 562 reg &= ~MAC_HaltReq; 563 tc_writel(reg, &tr->MAC_Ctl); 564 565 /* 566 * TX4939 PCFG.SPEEDn bit will be changed on 567 * NETDEV_CHANGE event. 568 */ 569 /* 570 * WORKAROUND: enable LostCrS only if half duplex 571 * operation. 572 * (TX4939 does not have EnLCarr) 573 */ 574 if (phydev->duplex == DUPLEX_HALF && 575 lp->chiptype != TC35815_TX4939) 576 tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr, 577 &tr->Tx_Ctl); 578 579 lp->speed = phydev->speed; 580 lp->duplex = phydev->duplex; 581 status_change = 1; 582 } 583 584 if (phydev->link != lp->link) { 585 if (phydev->link) { 586 /* delayed promiscuous enabling */ 587 if (dev->flags & IFF_PROMISC) 588 tc35815_set_multicast_list(dev); 589 } else { 590 lp->speed = 0; 591 lp->duplex = -1; 592 } 593 lp->link = phydev->link; 594 595 status_change = 1; 596 } 597 spin_unlock_irqrestore(&lp->lock, flags); 598 599 if (status_change && netif_msg_link(lp)) { 600 phy_print_status(phydev); 601 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n", 602 dev->name, 603 phy_read(phydev, MII_BMCR), 604 phy_read(phydev, MII_BMSR), 605 phy_read(phydev, MII_LPA)); 606 } 607 } 608 609 static int tc_mii_probe(struct net_device *dev) 610 { 611 struct tc35815_local *lp = netdev_priv(dev); 612 struct phy_device *phydev = NULL; 613 int phy_addr; 614 u32 dropmask; 615 616 /* find the first phy */ 617 for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { 618 if (lp->mii_bus->phy_map[phy_addr]) { 619 if (phydev) { 620 printk(KERN_ERR "%s: multiple PHYs found\n", 621 dev->name); 622 return -EINVAL; 623 } 624 phydev = lp->mii_bus->phy_map[phy_addr]; 625 break; 626 } 627 } 628 629 if (!phydev) { 630 printk(KERN_ERR "%s: no PHY found\n", dev->name); 631 return -ENODEV; 632 } 633 634 /* attach the mac to the phy */ 635 phydev = phy_connect(dev, dev_name(&phydev->dev), 636 &tc_handle_link_change, 637 lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII); 638 if (IS_ERR(phydev)) { 639 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name); 640 return PTR_ERR(phydev); 641 } 642 printk(KERN_INFO "%s: attached PHY driver [%s] " 643 "(mii_bus:phy_addr=%s, id=%x)\n", 644 dev->name, phydev->drv->name, dev_name(&phydev->dev), 645 phydev->phy_id); 646 647 /* mask with MAC supported features */ 648 phydev->supported &= PHY_BASIC_FEATURES; 649 dropmask = 0; 650 if (options.speed == 10) 651 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full; 652 else if (options.speed == 100) 653 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full; 654 if (options.duplex == 1) 655 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full; 656 else if (options.duplex == 2) 657 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half; 658 phydev->supported &= ~dropmask; 659 phydev->advertising = phydev->supported; 660 661 lp->link = 0; 662 lp->speed = 0; 663 lp->duplex = -1; 664 lp->phy_dev = phydev; 665 666 return 0; 667 } 668 669 static int tc_mii_init(struct net_device *dev) 670 { 671 struct tc35815_local *lp = netdev_priv(dev); 672 int err; 673 int i; 674 675 lp->mii_bus = mdiobus_alloc(); 676 if (lp->mii_bus == NULL) { 677 err = -ENOMEM; 678 goto err_out; 679 } 680 681 lp->mii_bus->name = "tc35815_mii_bus"; 682 lp->mii_bus->read = tc_mdio_read; 683 lp->mii_bus->write = tc_mdio_write; 684 snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x", 685 (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn); 686 lp->mii_bus->priv = dev; 687 lp->mii_bus->parent = &lp->pci_dev->dev; 688 lp->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 689 if (!lp->mii_bus->irq) { 690 err = -ENOMEM; 691 goto err_out_free_mii_bus; 692 } 693 694 for (i = 0; i < PHY_MAX_ADDR; i++) 695 lp->mii_bus->irq[i] = PHY_POLL; 696 697 err = mdiobus_register(lp->mii_bus); 698 if (err) 699 goto err_out_free_mdio_irq; 700 err = tc_mii_probe(dev); 701 if (err) 702 goto err_out_unregister_bus; 703 return 0; 704 705 err_out_unregister_bus: 706 mdiobus_unregister(lp->mii_bus); 707 err_out_free_mdio_irq: 708 kfree(lp->mii_bus->irq); 709 err_out_free_mii_bus: 710 mdiobus_free(lp->mii_bus); 711 err_out: 712 return err; 713 } 714 715 #ifdef CONFIG_CPU_TX49XX 716 /* 717 * Find a platform_device providing a MAC address. The platform code 718 * should provide a "tc35815-mac" device with a MAC address in its 719 * platform_data. 720 */ 721 static int tc35815_mac_match(struct device *dev, void *data) 722 { 723 struct platform_device *plat_dev = to_platform_device(dev); 724 struct pci_dev *pci_dev = data; 725 unsigned int id = pci_dev->irq; 726 return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id; 727 } 728 729 static int tc35815_read_plat_dev_addr(struct net_device *dev) 730 { 731 struct tc35815_local *lp = netdev_priv(dev); 732 struct device *pd = bus_find_device(&platform_bus_type, NULL, 733 lp->pci_dev, tc35815_mac_match); 734 if (pd) { 735 if (pd->platform_data) 736 memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN); 737 put_device(pd); 738 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV; 739 } 740 return -ENODEV; 741 } 742 #else 743 static int tc35815_read_plat_dev_addr(struct net_device *dev) 744 { 745 return -ENODEV; 746 } 747 #endif 748 749 static int tc35815_init_dev_addr(struct net_device *dev) 750 { 751 struct tc35815_regs __iomem *tr = 752 (struct tc35815_regs __iomem *)dev->base_addr; 753 int i; 754 755 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) 756 ; 757 for (i = 0; i < 6; i += 2) { 758 unsigned short data; 759 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl); 760 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy) 761 ; 762 data = tc_readl(&tr->PROM_Data); 763 dev->dev_addr[i] = data & 0xff; 764 dev->dev_addr[i+1] = data >> 8; 765 } 766 if (!is_valid_ether_addr(dev->dev_addr)) 767 return tc35815_read_plat_dev_addr(dev); 768 return 0; 769 } 770 771 static const struct net_device_ops tc35815_netdev_ops = { 772 .ndo_open = tc35815_open, 773 .ndo_stop = tc35815_close, 774 .ndo_start_xmit = tc35815_send_packet, 775 .ndo_get_stats = tc35815_get_stats, 776 .ndo_set_rx_mode = tc35815_set_multicast_list, 777 .ndo_tx_timeout = tc35815_tx_timeout, 778 .ndo_do_ioctl = tc35815_ioctl, 779 .ndo_validate_addr = eth_validate_addr, 780 .ndo_change_mtu = eth_change_mtu, 781 .ndo_set_mac_address = eth_mac_addr, 782 #ifdef CONFIG_NET_POLL_CONTROLLER 783 .ndo_poll_controller = tc35815_poll_controller, 784 #endif 785 }; 786 787 static int tc35815_init_one(struct pci_dev *pdev, 788 const struct pci_device_id *ent) 789 { 790 void __iomem *ioaddr = NULL; 791 struct net_device *dev; 792 struct tc35815_local *lp; 793 int rc; 794 795 static int printed_version; 796 if (!printed_version++) { 797 printk(version); 798 dev_printk(KERN_DEBUG, &pdev->dev, 799 "speed:%d duplex:%d\n", 800 options.speed, options.duplex); 801 } 802 803 if (!pdev->irq) { 804 dev_warn(&pdev->dev, "no IRQ assigned.\n"); 805 return -ENODEV; 806 } 807 808 /* dev zeroed in alloc_etherdev */ 809 dev = alloc_etherdev(sizeof(*lp)); 810 if (dev == NULL) 811 return -ENOMEM; 812 813 SET_NETDEV_DEV(dev, &pdev->dev); 814 lp = netdev_priv(dev); 815 lp->dev = dev; 816 817 /* enable device (incl. PCI PM wakeup), and bus-mastering */ 818 rc = pcim_enable_device(pdev); 819 if (rc) 820 goto err_out; 821 rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME); 822 if (rc) 823 goto err_out; 824 pci_set_master(pdev); 825 ioaddr = pcim_iomap_table(pdev)[1]; 826 827 /* Initialize the device structure. */ 828 dev->netdev_ops = &tc35815_netdev_ops; 829 dev->ethtool_ops = &tc35815_ethtool_ops; 830 dev->watchdog_timeo = TC35815_TX_TIMEOUT; 831 netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT); 832 833 dev->irq = pdev->irq; 834 dev->base_addr = (unsigned long)ioaddr; 835 836 INIT_WORK(&lp->restart_work, tc35815_restart_work); 837 spin_lock_init(&lp->lock); 838 spin_lock_init(&lp->rx_lock); 839 lp->pci_dev = pdev; 840 lp->chiptype = ent->driver_data; 841 842 lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK; 843 pci_set_drvdata(pdev, dev); 844 845 /* Soft reset the chip. */ 846 tc35815_chip_reset(dev); 847 848 /* Retrieve the ethernet address. */ 849 if (tc35815_init_dev_addr(dev)) { 850 dev_warn(&pdev->dev, "not valid ether addr\n"); 851 eth_hw_addr_random(dev); 852 } 853 854 rc = register_netdev(dev); 855 if (rc) 856 goto err_out; 857 858 printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n", 859 dev->name, 860 chip_info[ent->driver_data].name, 861 dev->base_addr, 862 dev->dev_addr, 863 dev->irq); 864 865 rc = tc_mii_init(dev); 866 if (rc) 867 goto err_out_unregister; 868 869 return 0; 870 871 err_out_unregister: 872 unregister_netdev(dev); 873 err_out: 874 free_netdev(dev); 875 return rc; 876 } 877 878 879 static void tc35815_remove_one(struct pci_dev *pdev) 880 { 881 struct net_device *dev = pci_get_drvdata(pdev); 882 struct tc35815_local *lp = netdev_priv(dev); 883 884 phy_disconnect(lp->phy_dev); 885 mdiobus_unregister(lp->mii_bus); 886 kfree(lp->mii_bus->irq); 887 mdiobus_free(lp->mii_bus); 888 unregister_netdev(dev); 889 free_netdev(dev); 890 } 891 892 static int 893 tc35815_init_queues(struct net_device *dev) 894 { 895 struct tc35815_local *lp = netdev_priv(dev); 896 int i; 897 unsigned long fd_addr; 898 899 if (!lp->fd_buf) { 900 BUG_ON(sizeof(struct FDesc) + 901 sizeof(struct BDesc) * RX_BUF_NUM + 902 sizeof(struct FDesc) * RX_FD_NUM + 903 sizeof(struct TxFD) * TX_FD_NUM > 904 PAGE_SIZE * FD_PAGE_NUM); 905 906 lp->fd_buf = pci_alloc_consistent(lp->pci_dev, 907 PAGE_SIZE * FD_PAGE_NUM, 908 &lp->fd_buf_dma); 909 if (!lp->fd_buf) 910 return -ENOMEM; 911 for (i = 0; i < RX_BUF_NUM; i++) { 912 lp->rx_skbs[i].skb = 913 alloc_rxbuf_skb(dev, lp->pci_dev, 914 &lp->rx_skbs[i].skb_dma); 915 if (!lp->rx_skbs[i].skb) { 916 while (--i >= 0) { 917 free_rxbuf_skb(lp->pci_dev, 918 lp->rx_skbs[i].skb, 919 lp->rx_skbs[i].skb_dma); 920 lp->rx_skbs[i].skb = NULL; 921 } 922 pci_free_consistent(lp->pci_dev, 923 PAGE_SIZE * FD_PAGE_NUM, 924 lp->fd_buf, 925 lp->fd_buf_dma); 926 lp->fd_buf = NULL; 927 return -ENOMEM; 928 } 929 } 930 printk(KERN_DEBUG "%s: FD buf %p DataBuf", 931 dev->name, lp->fd_buf); 932 printk("\n"); 933 } else { 934 for (i = 0; i < FD_PAGE_NUM; i++) 935 clear_page((void *)((unsigned long)lp->fd_buf + 936 i * PAGE_SIZE)); 937 } 938 fd_addr = (unsigned long)lp->fd_buf; 939 940 /* Free Descriptors (for Receive) */ 941 lp->rfd_base = (struct RxFD *)fd_addr; 942 fd_addr += sizeof(struct RxFD) * RX_FD_NUM; 943 for (i = 0; i < RX_FD_NUM; i++) 944 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD); 945 lp->rfd_cur = lp->rfd_base; 946 lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1); 947 948 /* Transmit Descriptors */ 949 lp->tfd_base = (struct TxFD *)fd_addr; 950 fd_addr += sizeof(struct TxFD) * TX_FD_NUM; 951 for (i = 0; i < TX_FD_NUM; i++) { 952 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1])); 953 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 954 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0); 955 } 956 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0])); 957 lp->tfd_start = 0; 958 lp->tfd_end = 0; 959 960 /* Buffer List (for Receive) */ 961 lp->fbl_ptr = (struct FrFD *)fd_addr; 962 lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr)); 963 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD); 964 /* 965 * move all allocated skbs to head of rx_skbs[] array. 966 * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in 967 * tc35815_rx() had failed. 968 */ 969 lp->fbl_count = 0; 970 for (i = 0; i < RX_BUF_NUM; i++) { 971 if (lp->rx_skbs[i].skb) { 972 if (i != lp->fbl_count) { 973 lp->rx_skbs[lp->fbl_count].skb = 974 lp->rx_skbs[i].skb; 975 lp->rx_skbs[lp->fbl_count].skb_dma = 976 lp->rx_skbs[i].skb_dma; 977 } 978 lp->fbl_count++; 979 } 980 } 981 for (i = 0; i < RX_BUF_NUM; i++) { 982 if (i >= lp->fbl_count) { 983 lp->fbl_ptr->bd[i].BuffData = 0; 984 lp->fbl_ptr->bd[i].BDCtl = 0; 985 continue; 986 } 987 lp->fbl_ptr->bd[i].BuffData = 988 cpu_to_le32(lp->rx_skbs[i].skb_dma); 989 /* BDID is index of FrFD.bd[] */ 990 lp->fbl_ptr->bd[i].BDCtl = 991 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | 992 RX_BUF_SIZE); 993 } 994 995 printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n", 996 dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr); 997 return 0; 998 } 999 1000 static void 1001 tc35815_clear_queues(struct net_device *dev) 1002 { 1003 struct tc35815_local *lp = netdev_priv(dev); 1004 int i; 1005 1006 for (i = 0; i < TX_FD_NUM; i++) { 1007 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); 1008 struct sk_buff *skb = 1009 fdsystem != 0xffffffff ? 1010 lp->tx_skbs[fdsystem].skb : NULL; 1011 #ifdef DEBUG 1012 if (lp->tx_skbs[i].skb != skb) { 1013 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); 1014 panic_queues(dev); 1015 } 1016 #else 1017 BUG_ON(lp->tx_skbs[i].skb != skb); 1018 #endif 1019 if (skb) { 1020 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); 1021 lp->tx_skbs[i].skb = NULL; 1022 lp->tx_skbs[i].skb_dma = 0; 1023 dev_kfree_skb_any(skb); 1024 } 1025 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 1026 } 1027 1028 tc35815_init_queues(dev); 1029 } 1030 1031 static void 1032 tc35815_free_queues(struct net_device *dev) 1033 { 1034 struct tc35815_local *lp = netdev_priv(dev); 1035 int i; 1036 1037 if (lp->tfd_base) { 1038 for (i = 0; i < TX_FD_NUM; i++) { 1039 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem); 1040 struct sk_buff *skb = 1041 fdsystem != 0xffffffff ? 1042 lp->tx_skbs[fdsystem].skb : NULL; 1043 #ifdef DEBUG 1044 if (lp->tx_skbs[i].skb != skb) { 1045 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i); 1046 panic_queues(dev); 1047 } 1048 #else 1049 BUG_ON(lp->tx_skbs[i].skb != skb); 1050 #endif 1051 if (skb) { 1052 dev_kfree_skb(skb); 1053 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE); 1054 lp->tx_skbs[i].skb = NULL; 1055 lp->tx_skbs[i].skb_dma = 0; 1056 } 1057 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff); 1058 } 1059 } 1060 1061 lp->rfd_base = NULL; 1062 lp->rfd_limit = NULL; 1063 lp->rfd_cur = NULL; 1064 lp->fbl_ptr = NULL; 1065 1066 for (i = 0; i < RX_BUF_NUM; i++) { 1067 if (lp->rx_skbs[i].skb) { 1068 free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb, 1069 lp->rx_skbs[i].skb_dma); 1070 lp->rx_skbs[i].skb = NULL; 1071 } 1072 } 1073 if (lp->fd_buf) { 1074 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM, 1075 lp->fd_buf, lp->fd_buf_dma); 1076 lp->fd_buf = NULL; 1077 } 1078 } 1079 1080 static void 1081 dump_txfd(struct TxFD *fd) 1082 { 1083 printk("TxFD(%p): %08x %08x %08x %08x\n", fd, 1084 le32_to_cpu(fd->fd.FDNext), 1085 le32_to_cpu(fd->fd.FDSystem), 1086 le32_to_cpu(fd->fd.FDStat), 1087 le32_to_cpu(fd->fd.FDCtl)); 1088 printk("BD: "); 1089 printk(" %08x %08x", 1090 le32_to_cpu(fd->bd.BuffData), 1091 le32_to_cpu(fd->bd.BDCtl)); 1092 printk("\n"); 1093 } 1094 1095 static int 1096 dump_rxfd(struct RxFD *fd) 1097 { 1098 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; 1099 if (bd_count > 8) 1100 bd_count = 8; 1101 printk("RxFD(%p): %08x %08x %08x %08x\n", fd, 1102 le32_to_cpu(fd->fd.FDNext), 1103 le32_to_cpu(fd->fd.FDSystem), 1104 le32_to_cpu(fd->fd.FDStat), 1105 le32_to_cpu(fd->fd.FDCtl)); 1106 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD) 1107 return 0; 1108 printk("BD: "); 1109 for (i = 0; i < bd_count; i++) 1110 printk(" %08x %08x", 1111 le32_to_cpu(fd->bd[i].BuffData), 1112 le32_to_cpu(fd->bd[i].BDCtl)); 1113 printk("\n"); 1114 return bd_count; 1115 } 1116 1117 #ifdef DEBUG 1118 static void 1119 dump_frfd(struct FrFD *fd) 1120 { 1121 int i; 1122 printk("FrFD(%p): %08x %08x %08x %08x\n", fd, 1123 le32_to_cpu(fd->fd.FDNext), 1124 le32_to_cpu(fd->fd.FDSystem), 1125 le32_to_cpu(fd->fd.FDStat), 1126 le32_to_cpu(fd->fd.FDCtl)); 1127 printk("BD: "); 1128 for (i = 0; i < RX_BUF_NUM; i++) 1129 printk(" %08x %08x", 1130 le32_to_cpu(fd->bd[i].BuffData), 1131 le32_to_cpu(fd->bd[i].BDCtl)); 1132 printk("\n"); 1133 } 1134 1135 static void 1136 panic_queues(struct net_device *dev) 1137 { 1138 struct tc35815_local *lp = netdev_priv(dev); 1139 int i; 1140 1141 printk("TxFD base %p, start %u, end %u\n", 1142 lp->tfd_base, lp->tfd_start, lp->tfd_end); 1143 printk("RxFD base %p limit %p cur %p\n", 1144 lp->rfd_base, lp->rfd_limit, lp->rfd_cur); 1145 printk("FrFD %p\n", lp->fbl_ptr); 1146 for (i = 0; i < TX_FD_NUM; i++) 1147 dump_txfd(&lp->tfd_base[i]); 1148 for (i = 0; i < RX_FD_NUM; i++) { 1149 int bd_count = dump_rxfd(&lp->rfd_base[i]); 1150 i += (bd_count + 1) / 2; /* skip BDs */ 1151 } 1152 dump_frfd(lp->fbl_ptr); 1153 panic("%s: Illegal queue state.", dev->name); 1154 } 1155 #endif 1156 1157 static void print_eth(const u8 *add) 1158 { 1159 printk(KERN_DEBUG "print_eth(%p)\n", add); 1160 printk(KERN_DEBUG " %pM => %pM : %02x%02x\n", 1161 add + 6, add, add[12], add[13]); 1162 } 1163 1164 static int tc35815_tx_full(struct net_device *dev) 1165 { 1166 struct tc35815_local *lp = netdev_priv(dev); 1167 return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end; 1168 } 1169 1170 static void tc35815_restart(struct net_device *dev) 1171 { 1172 struct tc35815_local *lp = netdev_priv(dev); 1173 1174 if (lp->phy_dev) { 1175 int timeout; 1176 1177 phy_write(lp->phy_dev, MII_BMCR, BMCR_RESET); 1178 timeout = 100; 1179 while (--timeout) { 1180 if (!(phy_read(lp->phy_dev, MII_BMCR) & BMCR_RESET)) 1181 break; 1182 udelay(1); 1183 } 1184 if (!timeout) 1185 printk(KERN_ERR "%s: BMCR reset failed.\n", dev->name); 1186 } 1187 1188 spin_lock_bh(&lp->rx_lock); 1189 spin_lock_irq(&lp->lock); 1190 tc35815_chip_reset(dev); 1191 tc35815_clear_queues(dev); 1192 tc35815_chip_init(dev); 1193 /* Reconfigure CAM again since tc35815_chip_init() initialize it. */ 1194 tc35815_set_multicast_list(dev); 1195 spin_unlock_irq(&lp->lock); 1196 spin_unlock_bh(&lp->rx_lock); 1197 1198 netif_wake_queue(dev); 1199 } 1200 1201 static void tc35815_restart_work(struct work_struct *work) 1202 { 1203 struct tc35815_local *lp = 1204 container_of(work, struct tc35815_local, restart_work); 1205 struct net_device *dev = lp->dev; 1206 1207 tc35815_restart(dev); 1208 } 1209 1210 static void tc35815_schedule_restart(struct net_device *dev) 1211 { 1212 struct tc35815_local *lp = netdev_priv(dev); 1213 struct tc35815_regs __iomem *tr = 1214 (struct tc35815_regs __iomem *)dev->base_addr; 1215 unsigned long flags; 1216 1217 /* disable interrupts */ 1218 spin_lock_irqsave(&lp->lock, flags); 1219 tc_writel(0, &tr->Int_En); 1220 tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl); 1221 schedule_work(&lp->restart_work); 1222 spin_unlock_irqrestore(&lp->lock, flags); 1223 } 1224 1225 static void tc35815_tx_timeout(struct net_device *dev) 1226 { 1227 struct tc35815_regs __iomem *tr = 1228 (struct tc35815_regs __iomem *)dev->base_addr; 1229 1230 printk(KERN_WARNING "%s: transmit timed out, status %#x\n", 1231 dev->name, tc_readl(&tr->Tx_Stat)); 1232 1233 /* Try to restart the adaptor. */ 1234 tc35815_schedule_restart(dev); 1235 dev->stats.tx_errors++; 1236 } 1237 1238 /* 1239 * Open/initialize the controller. This is called (in the current kernel) 1240 * sometime after booting when the 'ifconfig' program is run. 1241 * 1242 * This routine should set everything up anew at each open, even 1243 * registers that "should" only need to be set once at boot, so that 1244 * there is non-reboot way to recover if something goes wrong. 1245 */ 1246 static int 1247 tc35815_open(struct net_device *dev) 1248 { 1249 struct tc35815_local *lp = netdev_priv(dev); 1250 1251 /* 1252 * This is used if the interrupt line can turned off (shared). 1253 * See 3c503.c for an example of selecting the IRQ at config-time. 1254 */ 1255 if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED, 1256 dev->name, dev)) 1257 return -EAGAIN; 1258 1259 tc35815_chip_reset(dev); 1260 1261 if (tc35815_init_queues(dev) != 0) { 1262 free_irq(dev->irq, dev); 1263 return -EAGAIN; 1264 } 1265 1266 napi_enable(&lp->napi); 1267 1268 /* Reset the hardware here. Don't forget to set the station address. */ 1269 spin_lock_irq(&lp->lock); 1270 tc35815_chip_init(dev); 1271 spin_unlock_irq(&lp->lock); 1272 1273 netif_carrier_off(dev); 1274 /* schedule a link state check */ 1275 phy_start(lp->phy_dev); 1276 1277 /* We are now ready to accept transmit requeusts from 1278 * the queueing layer of the networking. 1279 */ 1280 netif_start_queue(dev); 1281 1282 return 0; 1283 } 1284 1285 /* This will only be invoked if your driver is _not_ in XOFF state. 1286 * What this means is that you need not check it, and that this 1287 * invariant will hold if you make sure that the netif_*_queue() 1288 * calls are done at the proper times. 1289 */ 1290 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev) 1291 { 1292 struct tc35815_local *lp = netdev_priv(dev); 1293 struct TxFD *txfd; 1294 unsigned long flags; 1295 1296 /* If some error occurs while trying to transmit this 1297 * packet, you should return '1' from this function. 1298 * In such a case you _may not_ do anything to the 1299 * SKB, it is still owned by the network queueing 1300 * layer when an error is returned. This means you 1301 * may not modify any SKB fields, you may not free 1302 * the SKB, etc. 1303 */ 1304 1305 /* This is the most common case for modern hardware. 1306 * The spinlock protects this code from the TX complete 1307 * hardware interrupt handler. Queue flow control is 1308 * thus managed under this lock as well. 1309 */ 1310 spin_lock_irqsave(&lp->lock, flags); 1311 1312 /* failsafe... (handle txdone now if half of FDs are used) */ 1313 if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM > 1314 TX_FD_NUM / 2) 1315 tc35815_txdone(dev); 1316 1317 if (netif_msg_pktdata(lp)) 1318 print_eth(skb->data); 1319 #ifdef DEBUG 1320 if (lp->tx_skbs[lp->tfd_start].skb) { 1321 printk("%s: tx_skbs conflict.\n", dev->name); 1322 panic_queues(dev); 1323 } 1324 #else 1325 BUG_ON(lp->tx_skbs[lp->tfd_start].skb); 1326 #endif 1327 lp->tx_skbs[lp->tfd_start].skb = skb; 1328 lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE); 1329 1330 /*add to ring */ 1331 txfd = &lp->tfd_base[lp->tfd_start]; 1332 txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma); 1333 txfd->bd.BDCtl = cpu_to_le32(skb->len); 1334 txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start); 1335 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT)); 1336 1337 if (lp->tfd_start == lp->tfd_end) { 1338 struct tc35815_regs __iomem *tr = 1339 (struct tc35815_regs __iomem *)dev->base_addr; 1340 /* Start DMA Transmitter. */ 1341 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL); 1342 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); 1343 if (netif_msg_tx_queued(lp)) { 1344 printk("%s: starting TxFD.\n", dev->name); 1345 dump_txfd(txfd); 1346 } 1347 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); 1348 } else { 1349 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL); 1350 if (netif_msg_tx_queued(lp)) { 1351 printk("%s: queueing TxFD.\n", dev->name); 1352 dump_txfd(txfd); 1353 } 1354 } 1355 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM; 1356 1357 /* If we just used up the very last entry in the 1358 * TX ring on this device, tell the queueing 1359 * layer to send no more. 1360 */ 1361 if (tc35815_tx_full(dev)) { 1362 if (netif_msg_tx_queued(lp)) 1363 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name); 1364 netif_stop_queue(dev); 1365 } 1366 1367 /* When the TX completion hw interrupt arrives, this 1368 * is when the transmit statistics are updated. 1369 */ 1370 1371 spin_unlock_irqrestore(&lp->lock, flags); 1372 return NETDEV_TX_OK; 1373 } 1374 1375 #define FATAL_ERROR_INT \ 1376 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt) 1377 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status) 1378 { 1379 static int count; 1380 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):", 1381 dev->name, status); 1382 if (status & Int_IntPCI) 1383 printk(" IntPCI"); 1384 if (status & Int_DmParErr) 1385 printk(" DmParErr"); 1386 if (status & Int_IntNRAbt) 1387 printk(" IntNRAbt"); 1388 printk("\n"); 1389 if (count++ > 100) 1390 panic("%s: Too many fatal errors.", dev->name); 1391 printk(KERN_WARNING "%s: Resetting ...\n", dev->name); 1392 /* Try to restart the adaptor. */ 1393 tc35815_schedule_restart(dev); 1394 } 1395 1396 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit) 1397 { 1398 struct tc35815_local *lp = netdev_priv(dev); 1399 int ret = -1; 1400 1401 /* Fatal errors... */ 1402 if (status & FATAL_ERROR_INT) { 1403 tc35815_fatal_error_interrupt(dev, status); 1404 return 0; 1405 } 1406 /* recoverable errors */ 1407 if (status & Int_IntFDAEx) { 1408 if (netif_msg_rx_err(lp)) 1409 dev_warn(&dev->dev, 1410 "Free Descriptor Area Exhausted (%#x).\n", 1411 status); 1412 dev->stats.rx_dropped++; 1413 ret = 0; 1414 } 1415 if (status & Int_IntBLEx) { 1416 if (netif_msg_rx_err(lp)) 1417 dev_warn(&dev->dev, 1418 "Buffer List Exhausted (%#x).\n", 1419 status); 1420 dev->stats.rx_dropped++; 1421 ret = 0; 1422 } 1423 if (status & Int_IntExBD) { 1424 if (netif_msg_rx_err(lp)) 1425 dev_warn(&dev->dev, 1426 "Excessive Buffer Descriptiors (%#x).\n", 1427 status); 1428 dev->stats.rx_length_errors++; 1429 ret = 0; 1430 } 1431 1432 /* normal notification */ 1433 if (status & Int_IntMacRx) { 1434 /* Got a packet(s). */ 1435 ret = tc35815_rx(dev, limit); 1436 lp->lstats.rx_ints++; 1437 } 1438 if (status & Int_IntMacTx) { 1439 /* Transmit complete. */ 1440 lp->lstats.tx_ints++; 1441 spin_lock_irq(&lp->lock); 1442 tc35815_txdone(dev); 1443 spin_unlock_irq(&lp->lock); 1444 if (ret < 0) 1445 ret = 0; 1446 } 1447 return ret; 1448 } 1449 1450 /* 1451 * The typical workload of the driver: 1452 * Handle the network interface interrupts. 1453 */ 1454 static irqreturn_t tc35815_interrupt(int irq, void *dev_id) 1455 { 1456 struct net_device *dev = dev_id; 1457 struct tc35815_local *lp = netdev_priv(dev); 1458 struct tc35815_regs __iomem *tr = 1459 (struct tc35815_regs __iomem *)dev->base_addr; 1460 u32 dmactl = tc_readl(&tr->DMA_Ctl); 1461 1462 if (!(dmactl & DMA_IntMask)) { 1463 /* disable interrupts */ 1464 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl); 1465 if (napi_schedule_prep(&lp->napi)) 1466 __napi_schedule(&lp->napi); 1467 else { 1468 printk(KERN_ERR "%s: interrupt taken in poll\n", 1469 dev->name); 1470 BUG(); 1471 } 1472 (void)tc_readl(&tr->Int_Src); /* flush */ 1473 return IRQ_HANDLED; 1474 } 1475 return IRQ_NONE; 1476 } 1477 1478 #ifdef CONFIG_NET_POLL_CONTROLLER 1479 static void tc35815_poll_controller(struct net_device *dev) 1480 { 1481 disable_irq(dev->irq); 1482 tc35815_interrupt(dev->irq, dev); 1483 enable_irq(dev->irq); 1484 } 1485 #endif 1486 1487 /* We have a good packet(s), get it/them out of the buffers. */ 1488 static int 1489 tc35815_rx(struct net_device *dev, int limit) 1490 { 1491 struct tc35815_local *lp = netdev_priv(dev); 1492 unsigned int fdctl; 1493 int i; 1494 int received = 0; 1495 1496 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) { 1497 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat); 1498 int pkt_len = fdctl & FD_FDLength_MASK; 1499 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT; 1500 #ifdef DEBUG 1501 struct RxFD *next_rfd; 1502 #endif 1503 #if (RX_CTL_CMD & Rx_StripCRC) == 0 1504 pkt_len -= ETH_FCS_LEN; 1505 #endif 1506 1507 if (netif_msg_rx_status(lp)) 1508 dump_rxfd(lp->rfd_cur); 1509 if (status & Rx_Good) { 1510 struct sk_buff *skb; 1511 unsigned char *data; 1512 int cur_bd; 1513 1514 if (--limit < 0) 1515 break; 1516 BUG_ON(bd_count > 1); 1517 cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl) 1518 & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; 1519 #ifdef DEBUG 1520 if (cur_bd >= RX_BUF_NUM) { 1521 printk("%s: invalid BDID.\n", dev->name); 1522 panic_queues(dev); 1523 } 1524 BUG_ON(lp->rx_skbs[cur_bd].skb_dma != 1525 (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3)); 1526 if (!lp->rx_skbs[cur_bd].skb) { 1527 printk("%s: NULL skb.\n", dev->name); 1528 panic_queues(dev); 1529 } 1530 #else 1531 BUG_ON(cur_bd >= RX_BUF_NUM); 1532 #endif 1533 skb = lp->rx_skbs[cur_bd].skb; 1534 prefetch(skb->data); 1535 lp->rx_skbs[cur_bd].skb = NULL; 1536 pci_unmap_single(lp->pci_dev, 1537 lp->rx_skbs[cur_bd].skb_dma, 1538 RX_BUF_SIZE, PCI_DMA_FROMDEVICE); 1539 if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN) 1540 memmove(skb->data, skb->data - NET_IP_ALIGN, 1541 pkt_len); 1542 data = skb_put(skb, pkt_len); 1543 if (netif_msg_pktdata(lp)) 1544 print_eth(data); 1545 skb->protocol = eth_type_trans(skb, dev); 1546 netif_receive_skb(skb); 1547 received++; 1548 dev->stats.rx_packets++; 1549 dev->stats.rx_bytes += pkt_len; 1550 } else { 1551 dev->stats.rx_errors++; 1552 if (netif_msg_rx_err(lp)) 1553 dev_info(&dev->dev, "Rx error (status %x)\n", 1554 status & Rx_Stat_Mask); 1555 /* WORKAROUND: LongErr and CRCErr means Overflow. */ 1556 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) { 1557 status &= ~(Rx_LongErr|Rx_CRCErr); 1558 status |= Rx_Over; 1559 } 1560 if (status & Rx_LongErr) 1561 dev->stats.rx_length_errors++; 1562 if (status & Rx_Over) 1563 dev->stats.rx_fifo_errors++; 1564 if (status & Rx_CRCErr) 1565 dev->stats.rx_crc_errors++; 1566 if (status & Rx_Align) 1567 dev->stats.rx_frame_errors++; 1568 } 1569 1570 if (bd_count > 0) { 1571 /* put Free Buffer back to controller */ 1572 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl); 1573 unsigned char id = 1574 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT; 1575 #ifdef DEBUG 1576 if (id >= RX_BUF_NUM) { 1577 printk("%s: invalid BDID.\n", dev->name); 1578 panic_queues(dev); 1579 } 1580 #else 1581 BUG_ON(id >= RX_BUF_NUM); 1582 #endif 1583 /* free old buffers */ 1584 lp->fbl_count--; 1585 while (lp->fbl_count < RX_BUF_NUM) 1586 { 1587 unsigned char curid = 1588 (id + 1 + lp->fbl_count) % RX_BUF_NUM; 1589 struct BDesc *bd = &lp->fbl_ptr->bd[curid]; 1590 #ifdef DEBUG 1591 bdctl = le32_to_cpu(bd->BDCtl); 1592 if (bdctl & BD_CownsBD) { 1593 printk("%s: Freeing invalid BD.\n", 1594 dev->name); 1595 panic_queues(dev); 1596 } 1597 #endif 1598 /* pass BD to controller */ 1599 if (!lp->rx_skbs[curid].skb) { 1600 lp->rx_skbs[curid].skb = 1601 alloc_rxbuf_skb(dev, 1602 lp->pci_dev, 1603 &lp->rx_skbs[curid].skb_dma); 1604 if (!lp->rx_skbs[curid].skb) 1605 break; /* try on next reception */ 1606 bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma); 1607 } 1608 /* Note: BDLength was modified by chip. */ 1609 bd->BDCtl = cpu_to_le32(BD_CownsBD | 1610 (curid << BD_RxBDID_SHIFT) | 1611 RX_BUF_SIZE); 1612 lp->fbl_count++; 1613 } 1614 } 1615 1616 /* put RxFD back to controller */ 1617 #ifdef DEBUG 1618 next_rfd = fd_bus_to_virt(lp, 1619 le32_to_cpu(lp->rfd_cur->fd.FDNext)); 1620 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) { 1621 printk("%s: RxFD FDNext invalid.\n", dev->name); 1622 panic_queues(dev); 1623 } 1624 #endif 1625 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) { 1626 /* pass FD to controller */ 1627 #ifdef DEBUG 1628 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); 1629 #else 1630 lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL); 1631 #endif 1632 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD); 1633 lp->rfd_cur++; 1634 } 1635 if (lp->rfd_cur > lp->rfd_limit) 1636 lp->rfd_cur = lp->rfd_base; 1637 #ifdef DEBUG 1638 if (lp->rfd_cur != next_rfd) 1639 printk("rfd_cur = %p, next_rfd %p\n", 1640 lp->rfd_cur, next_rfd); 1641 #endif 1642 } 1643 1644 return received; 1645 } 1646 1647 static int tc35815_poll(struct napi_struct *napi, int budget) 1648 { 1649 struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi); 1650 struct net_device *dev = lp->dev; 1651 struct tc35815_regs __iomem *tr = 1652 (struct tc35815_regs __iomem *)dev->base_addr; 1653 int received = 0, handled; 1654 u32 status; 1655 1656 spin_lock(&lp->rx_lock); 1657 status = tc_readl(&tr->Int_Src); 1658 do { 1659 /* BLEx, FDAEx will be cleared later */ 1660 tc_writel(status & ~(Int_BLEx | Int_FDAEx), 1661 &tr->Int_Src); /* write to clear */ 1662 1663 handled = tc35815_do_interrupt(dev, status, budget - received); 1664 if (status & (Int_BLEx | Int_FDAEx)) 1665 tc_writel(status & (Int_BLEx | Int_FDAEx), 1666 &tr->Int_Src); 1667 if (handled >= 0) { 1668 received += handled; 1669 if (received >= budget) 1670 break; 1671 } 1672 status = tc_readl(&tr->Int_Src); 1673 } while (status); 1674 spin_unlock(&lp->rx_lock); 1675 1676 if (received < budget) { 1677 napi_complete(napi); 1678 /* enable interrupts */ 1679 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl); 1680 } 1681 return received; 1682 } 1683 1684 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr) 1685 1686 static void 1687 tc35815_check_tx_stat(struct net_device *dev, int status) 1688 { 1689 struct tc35815_local *lp = netdev_priv(dev); 1690 const char *msg = NULL; 1691 1692 /* count collisions */ 1693 if (status & Tx_ExColl) 1694 dev->stats.collisions += 16; 1695 if (status & Tx_TxColl_MASK) 1696 dev->stats.collisions += status & Tx_TxColl_MASK; 1697 1698 /* TX4939 does not have NCarr */ 1699 if (lp->chiptype == TC35815_TX4939) 1700 status &= ~Tx_NCarr; 1701 /* WORKAROUND: ignore LostCrS in full duplex operation */ 1702 if (!lp->link || lp->duplex == DUPLEX_FULL) 1703 status &= ~Tx_NCarr; 1704 1705 if (!(status & TX_STA_ERR)) { 1706 /* no error. */ 1707 dev->stats.tx_packets++; 1708 return; 1709 } 1710 1711 dev->stats.tx_errors++; 1712 if (status & Tx_ExColl) { 1713 dev->stats.tx_aborted_errors++; 1714 msg = "Excessive Collision."; 1715 } 1716 if (status & Tx_Under) { 1717 dev->stats.tx_fifo_errors++; 1718 msg = "Tx FIFO Underrun."; 1719 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) { 1720 lp->lstats.tx_underrun++; 1721 if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) { 1722 struct tc35815_regs __iomem *tr = 1723 (struct tc35815_regs __iomem *)dev->base_addr; 1724 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh); 1725 msg = "Tx FIFO Underrun.Change Tx threshold to max."; 1726 } 1727 } 1728 } 1729 if (status & Tx_Defer) { 1730 dev->stats.tx_fifo_errors++; 1731 msg = "Excessive Deferral."; 1732 } 1733 if (status & Tx_NCarr) { 1734 dev->stats.tx_carrier_errors++; 1735 msg = "Lost Carrier Sense."; 1736 } 1737 if (status & Tx_LateColl) { 1738 dev->stats.tx_aborted_errors++; 1739 msg = "Late Collision."; 1740 } 1741 if (status & Tx_TxPar) { 1742 dev->stats.tx_fifo_errors++; 1743 msg = "Transmit Parity Error."; 1744 } 1745 if (status & Tx_SQErr) { 1746 dev->stats.tx_heartbeat_errors++; 1747 msg = "Signal Quality Error."; 1748 } 1749 if (msg && netif_msg_tx_err(lp)) 1750 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status); 1751 } 1752 1753 /* This handles TX complete events posted by the device 1754 * via interrupts. 1755 */ 1756 static void 1757 tc35815_txdone(struct net_device *dev) 1758 { 1759 struct tc35815_local *lp = netdev_priv(dev); 1760 struct TxFD *txfd; 1761 unsigned int fdctl; 1762 1763 txfd = &lp->tfd_base[lp->tfd_end]; 1764 while (lp->tfd_start != lp->tfd_end && 1765 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) { 1766 int status = le32_to_cpu(txfd->fd.FDStat); 1767 struct sk_buff *skb; 1768 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext); 1769 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem); 1770 1771 if (netif_msg_tx_done(lp)) { 1772 printk("%s: complete TxFD.\n", dev->name); 1773 dump_txfd(txfd); 1774 } 1775 tc35815_check_tx_stat(dev, status); 1776 1777 skb = fdsystem != 0xffffffff ? 1778 lp->tx_skbs[fdsystem].skb : NULL; 1779 #ifdef DEBUG 1780 if (lp->tx_skbs[lp->tfd_end].skb != skb) { 1781 printk("%s: tx_skbs mismatch.\n", dev->name); 1782 panic_queues(dev); 1783 } 1784 #else 1785 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb); 1786 #endif 1787 if (skb) { 1788 dev->stats.tx_bytes += skb->len; 1789 pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE); 1790 lp->tx_skbs[lp->tfd_end].skb = NULL; 1791 lp->tx_skbs[lp->tfd_end].skb_dma = 0; 1792 dev_kfree_skb_any(skb); 1793 } 1794 txfd->fd.FDSystem = cpu_to_le32(0xffffffff); 1795 1796 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM; 1797 txfd = &lp->tfd_base[lp->tfd_end]; 1798 #ifdef DEBUG 1799 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) { 1800 printk("%s: TxFD FDNext invalid.\n", dev->name); 1801 panic_queues(dev); 1802 } 1803 #endif 1804 if (fdnext & FD_Next_EOL) { 1805 /* DMA Transmitter has been stopping... */ 1806 if (lp->tfd_end != lp->tfd_start) { 1807 struct tc35815_regs __iomem *tr = 1808 (struct tc35815_regs __iomem *)dev->base_addr; 1809 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM; 1810 struct TxFD *txhead = &lp->tfd_base[head]; 1811 int qlen = (lp->tfd_start + TX_FD_NUM 1812 - lp->tfd_end) % TX_FD_NUM; 1813 1814 #ifdef DEBUG 1815 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) { 1816 printk("%s: TxFD FDCtl invalid.\n", dev->name); 1817 panic_queues(dev); 1818 } 1819 #endif 1820 /* log max queue length */ 1821 if (lp->lstats.max_tx_qlen < qlen) 1822 lp->lstats.max_tx_qlen = qlen; 1823 1824 1825 /* start DMA Transmitter again */ 1826 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL); 1827 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx); 1828 if (netif_msg_tx_queued(lp)) { 1829 printk("%s: start TxFD on queue.\n", 1830 dev->name); 1831 dump_txfd(txfd); 1832 } 1833 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr); 1834 } 1835 break; 1836 } 1837 } 1838 1839 /* If we had stopped the queue due to a "tx full" 1840 * condition, and space has now been made available, 1841 * wake up the queue. 1842 */ 1843 if (netif_queue_stopped(dev) && !tc35815_tx_full(dev)) 1844 netif_wake_queue(dev); 1845 } 1846 1847 /* The inverse routine to tc35815_open(). */ 1848 static int 1849 tc35815_close(struct net_device *dev) 1850 { 1851 struct tc35815_local *lp = netdev_priv(dev); 1852 1853 netif_stop_queue(dev); 1854 napi_disable(&lp->napi); 1855 if (lp->phy_dev) 1856 phy_stop(lp->phy_dev); 1857 cancel_work_sync(&lp->restart_work); 1858 1859 /* Flush the Tx and disable Rx here. */ 1860 tc35815_chip_reset(dev); 1861 free_irq(dev->irq, dev); 1862 1863 tc35815_free_queues(dev); 1864 1865 return 0; 1866 1867 } 1868 1869 /* 1870 * Get the current statistics. 1871 * This may be called with the card open or closed. 1872 */ 1873 static struct net_device_stats *tc35815_get_stats(struct net_device *dev) 1874 { 1875 struct tc35815_regs __iomem *tr = 1876 (struct tc35815_regs __iomem *)dev->base_addr; 1877 if (netif_running(dev)) 1878 /* Update the statistics from the device registers. */ 1879 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt); 1880 1881 return &dev->stats; 1882 } 1883 1884 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr) 1885 { 1886 struct tc35815_local *lp = netdev_priv(dev); 1887 struct tc35815_regs __iomem *tr = 1888 (struct tc35815_regs __iomem *)dev->base_addr; 1889 int cam_index = index * 6; 1890 u32 cam_data; 1891 u32 saved_addr; 1892 1893 saved_addr = tc_readl(&tr->CAM_Adr); 1894 1895 if (netif_msg_hw(lp)) 1896 printk(KERN_DEBUG "%s: CAM %d: %pM\n", 1897 dev->name, index, addr); 1898 if (index & 1) { 1899 /* read modify write */ 1900 tc_writel(cam_index - 2, &tr->CAM_Adr); 1901 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000; 1902 cam_data |= addr[0] << 8 | addr[1]; 1903 tc_writel(cam_data, &tr->CAM_Data); 1904 /* write whole word */ 1905 tc_writel(cam_index + 2, &tr->CAM_Adr); 1906 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5]; 1907 tc_writel(cam_data, &tr->CAM_Data); 1908 } else { 1909 /* write whole word */ 1910 tc_writel(cam_index, &tr->CAM_Adr); 1911 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]; 1912 tc_writel(cam_data, &tr->CAM_Data); 1913 /* read modify write */ 1914 tc_writel(cam_index + 4, &tr->CAM_Adr); 1915 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff; 1916 cam_data |= addr[4] << 24 | (addr[5] << 16); 1917 tc_writel(cam_data, &tr->CAM_Data); 1918 } 1919 1920 tc_writel(saved_addr, &tr->CAM_Adr); 1921 } 1922 1923 1924 /* 1925 * Set or clear the multicast filter for this adaptor. 1926 * num_addrs == -1 Promiscuous mode, receive all packets 1927 * num_addrs == 0 Normal mode, clear multicast list 1928 * num_addrs > 0 Multicast mode, receive normal and MC packets, 1929 * and do best-effort filtering. 1930 */ 1931 static void 1932 tc35815_set_multicast_list(struct net_device *dev) 1933 { 1934 struct tc35815_regs __iomem *tr = 1935 (struct tc35815_regs __iomem *)dev->base_addr; 1936 1937 if (dev->flags & IFF_PROMISC) { 1938 /* With some (all?) 100MHalf HUB, controller will hang 1939 * if we enabled promiscuous mode before linkup... */ 1940 struct tc35815_local *lp = netdev_priv(dev); 1941 1942 if (!lp->link) 1943 return; 1944 /* Enable promiscuous mode */ 1945 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl); 1946 } else if ((dev->flags & IFF_ALLMULTI) || 1947 netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) { 1948 /* CAM 0, 1, 20 are reserved. */ 1949 /* Disable promiscuous mode, use normal mode. */ 1950 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl); 1951 } else if (!netdev_mc_empty(dev)) { 1952 struct netdev_hw_addr *ha; 1953 int i; 1954 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE); 1955 1956 tc_writel(0, &tr->CAM_Ctl); 1957 /* Walk the address list, and load the filter */ 1958 i = 0; 1959 netdev_for_each_mc_addr(ha, dev) { 1960 /* entry 0,1 is reserved. */ 1961 tc35815_set_cam_entry(dev, i + 2, ha->addr); 1962 ena_bits |= CAM_Ena_Bit(i + 2); 1963 i++; 1964 } 1965 tc_writel(ena_bits, &tr->CAM_Ena); 1966 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 1967 } else { 1968 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); 1969 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 1970 } 1971 } 1972 1973 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 1974 { 1975 struct tc35815_local *lp = netdev_priv(dev); 1976 1977 strlcpy(info->driver, MODNAME, sizeof(info->driver)); 1978 strlcpy(info->version, DRV_VERSION, sizeof(info->version)); 1979 strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info)); 1980 } 1981 1982 static int tc35815_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1983 { 1984 struct tc35815_local *lp = netdev_priv(dev); 1985 1986 if (!lp->phy_dev) 1987 return -ENODEV; 1988 return phy_ethtool_gset(lp->phy_dev, cmd); 1989 } 1990 1991 static int tc35815_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 1992 { 1993 struct tc35815_local *lp = netdev_priv(dev); 1994 1995 if (!lp->phy_dev) 1996 return -ENODEV; 1997 return phy_ethtool_sset(lp->phy_dev, cmd); 1998 } 1999 2000 static u32 tc35815_get_msglevel(struct net_device *dev) 2001 { 2002 struct tc35815_local *lp = netdev_priv(dev); 2003 return lp->msg_enable; 2004 } 2005 2006 static void tc35815_set_msglevel(struct net_device *dev, u32 datum) 2007 { 2008 struct tc35815_local *lp = netdev_priv(dev); 2009 lp->msg_enable = datum; 2010 } 2011 2012 static int tc35815_get_sset_count(struct net_device *dev, int sset) 2013 { 2014 struct tc35815_local *lp = netdev_priv(dev); 2015 2016 switch (sset) { 2017 case ETH_SS_STATS: 2018 return sizeof(lp->lstats) / sizeof(int); 2019 default: 2020 return -EOPNOTSUPP; 2021 } 2022 } 2023 2024 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) 2025 { 2026 struct tc35815_local *lp = netdev_priv(dev); 2027 data[0] = lp->lstats.max_tx_qlen; 2028 data[1] = lp->lstats.tx_ints; 2029 data[2] = lp->lstats.rx_ints; 2030 data[3] = lp->lstats.tx_underrun; 2031 } 2032 2033 static struct { 2034 const char str[ETH_GSTRING_LEN]; 2035 } ethtool_stats_keys[] = { 2036 { "max_tx_qlen" }, 2037 { "tx_ints" }, 2038 { "rx_ints" }, 2039 { "tx_underrun" }, 2040 }; 2041 2042 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data) 2043 { 2044 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys)); 2045 } 2046 2047 static const struct ethtool_ops tc35815_ethtool_ops = { 2048 .get_drvinfo = tc35815_get_drvinfo, 2049 .get_settings = tc35815_get_settings, 2050 .set_settings = tc35815_set_settings, 2051 .get_link = ethtool_op_get_link, 2052 .get_msglevel = tc35815_get_msglevel, 2053 .set_msglevel = tc35815_set_msglevel, 2054 .get_strings = tc35815_get_strings, 2055 .get_sset_count = tc35815_get_sset_count, 2056 .get_ethtool_stats = tc35815_get_ethtool_stats, 2057 }; 2058 2059 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2060 { 2061 struct tc35815_local *lp = netdev_priv(dev); 2062 2063 if (!netif_running(dev)) 2064 return -EINVAL; 2065 if (!lp->phy_dev) 2066 return -ENODEV; 2067 return phy_mii_ioctl(lp->phy_dev, rq, cmd); 2068 } 2069 2070 static void tc35815_chip_reset(struct net_device *dev) 2071 { 2072 struct tc35815_regs __iomem *tr = 2073 (struct tc35815_regs __iomem *)dev->base_addr; 2074 int i; 2075 /* reset the controller */ 2076 tc_writel(MAC_Reset, &tr->MAC_Ctl); 2077 udelay(4); /* 3200ns */ 2078 i = 0; 2079 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) { 2080 if (i++ > 100) { 2081 printk(KERN_ERR "%s: MAC reset failed.\n", dev->name); 2082 break; 2083 } 2084 mdelay(1); 2085 } 2086 tc_writel(0, &tr->MAC_Ctl); 2087 2088 /* initialize registers to default value */ 2089 tc_writel(0, &tr->DMA_Ctl); 2090 tc_writel(0, &tr->TxThrsh); 2091 tc_writel(0, &tr->TxPollCtr); 2092 tc_writel(0, &tr->RxFragSize); 2093 tc_writel(0, &tr->Int_En); 2094 tc_writel(0, &tr->FDA_Bas); 2095 tc_writel(0, &tr->FDA_Lim); 2096 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */ 2097 tc_writel(0, &tr->CAM_Ctl); 2098 tc_writel(0, &tr->Tx_Ctl); 2099 tc_writel(0, &tr->Rx_Ctl); 2100 tc_writel(0, &tr->CAM_Ena); 2101 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */ 2102 2103 /* initialize internal SRAM */ 2104 tc_writel(DMA_TestMode, &tr->DMA_Ctl); 2105 for (i = 0; i < 0x1000; i += 4) { 2106 tc_writel(i, &tr->CAM_Adr); 2107 tc_writel(0, &tr->CAM_Data); 2108 } 2109 tc_writel(0, &tr->DMA_Ctl); 2110 } 2111 2112 static void tc35815_chip_init(struct net_device *dev) 2113 { 2114 struct tc35815_local *lp = netdev_priv(dev); 2115 struct tc35815_regs __iomem *tr = 2116 (struct tc35815_regs __iomem *)dev->base_addr; 2117 unsigned long txctl = TX_CTL_CMD; 2118 2119 /* load station address to CAM */ 2120 tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr); 2121 2122 /* Enable CAM (broadcast and unicast) */ 2123 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena); 2124 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl); 2125 2126 /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */ 2127 if (HAVE_DMA_RXALIGN(lp)) 2128 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl); 2129 else 2130 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl); 2131 tc_writel(0, &tr->TxPollCtr); /* Batch mode */ 2132 tc_writel(TX_THRESHOLD, &tr->TxThrsh); 2133 tc_writel(INT_EN_CMD, &tr->Int_En); 2134 2135 /* set queues */ 2136 tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas); 2137 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base, 2138 &tr->FDA_Lim); 2139 /* 2140 * Activation method: 2141 * First, enable the MAC Transmitter and the DMA Receive circuits. 2142 * Then enable the DMA Transmitter and the MAC Receive circuits. 2143 */ 2144 tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */ 2145 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */ 2146 2147 /* start MAC transmitter */ 2148 /* TX4939 does not have EnLCarr */ 2149 if (lp->chiptype == TC35815_TX4939) 2150 txctl &= ~Tx_EnLCarr; 2151 /* WORKAROUND: ignore LostCrS in full duplex operation */ 2152 if (!lp->phy_dev || !lp->link || lp->duplex == DUPLEX_FULL) 2153 txctl &= ~Tx_EnLCarr; 2154 tc_writel(txctl, &tr->Tx_Ctl); 2155 } 2156 2157 #ifdef CONFIG_PM 2158 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state) 2159 { 2160 struct net_device *dev = pci_get_drvdata(pdev); 2161 struct tc35815_local *lp = netdev_priv(dev); 2162 unsigned long flags; 2163 2164 pci_save_state(pdev); 2165 if (!netif_running(dev)) 2166 return 0; 2167 netif_device_detach(dev); 2168 if (lp->phy_dev) 2169 phy_stop(lp->phy_dev); 2170 spin_lock_irqsave(&lp->lock, flags); 2171 tc35815_chip_reset(dev); 2172 spin_unlock_irqrestore(&lp->lock, flags); 2173 pci_set_power_state(pdev, PCI_D3hot); 2174 return 0; 2175 } 2176 2177 static int tc35815_resume(struct pci_dev *pdev) 2178 { 2179 struct net_device *dev = pci_get_drvdata(pdev); 2180 struct tc35815_local *lp = netdev_priv(dev); 2181 2182 pci_restore_state(pdev); 2183 if (!netif_running(dev)) 2184 return 0; 2185 pci_set_power_state(pdev, PCI_D0); 2186 tc35815_restart(dev); 2187 netif_carrier_off(dev); 2188 if (lp->phy_dev) 2189 phy_start(lp->phy_dev); 2190 netif_device_attach(dev); 2191 return 0; 2192 } 2193 #endif /* CONFIG_PM */ 2194 2195 static struct pci_driver tc35815_pci_driver = { 2196 .name = MODNAME, 2197 .id_table = tc35815_pci_tbl, 2198 .probe = tc35815_init_one, 2199 .remove = tc35815_remove_one, 2200 #ifdef CONFIG_PM 2201 .suspend = tc35815_suspend, 2202 .resume = tc35815_resume, 2203 #endif 2204 }; 2205 2206 module_param_named(speed, options.speed, int, 0); 2207 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps"); 2208 module_param_named(duplex, options.duplex, int, 0); 2209 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full"); 2210 2211 module_pci_driver(tc35815_pci_driver); 2212 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver"); 2213 MODULE_LICENSE("GPL"); 2214