1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * XGE PCSR module initialisation 4 * 5 * Copyright (C) 2014 Texas Instruments Incorporated 6 * Authors: Sandeep Nair <sandeep_n@ti.com> 7 * WingMan Kwok <w-kwok2@ti.com> 8 * 9 */ 10 #include "netcp.h" 11 12 /* XGBE registers */ 13 #define XGBE_CTRL_OFFSET 0x0c 14 #define XGBE_SGMII_1_OFFSET 0x0114 15 #define XGBE_SGMII_2_OFFSET 0x0214 16 17 /* PCS-R registers */ 18 #define PCSR_CPU_CTRL_OFFSET 0x1fd0 19 #define POR_EN BIT(29) 20 21 #define reg_rmw(addr, value, mask) \ 22 writel(((readl(addr) & (~(mask))) | \ 23 (value & (mask))), (addr)) 24 25 /* bit mask of width w at offset s */ 26 #define MASK_WID_SH(w, s) (((1 << w) - 1) << s) 27 28 /* shift value v to offset s */ 29 #define VAL_SH(v, s) (v << s) 30 31 #define PHY_A(serdes) 0 32 33 struct serdes_cfg { 34 u32 ofs; 35 u32 val; 36 u32 mask; 37 }; 38 39 static struct serdes_cfg cfg_phyb_1p25g_156p25mhz_cmu0[] = { 40 {0x0000, 0x00800002, 0x00ff00ff}, 41 {0x0014, 0x00003838, 0x0000ffff}, 42 {0x0060, 0x1c44e438, 0xffffffff}, 43 {0x0064, 0x00c18400, 0x00ffffff}, 44 {0x0068, 0x17078200, 0xffffff00}, 45 {0x006c, 0x00000014, 0x000000ff}, 46 {0x0078, 0x0000c000, 0x0000ff00}, 47 {0x0000, 0x00000003, 0x000000ff}, 48 }; 49 50 static struct serdes_cfg cfg_phyb_10p3125g_156p25mhz_cmu1[] = { 51 {0x0c00, 0x00030002, 0x00ff00ff}, 52 {0x0c14, 0x00005252, 0x0000ffff}, 53 {0x0c28, 0x80000000, 0xff000000}, 54 {0x0c2c, 0x000000f6, 0x000000ff}, 55 {0x0c3c, 0x04000405, 0xff00ffff}, 56 {0x0c40, 0xc0800000, 0xffff0000}, 57 {0x0c44, 0x5a202062, 0xffffffff}, 58 {0x0c48, 0x40040424, 0xffffffff}, 59 {0x0c4c, 0x00004002, 0x0000ffff}, 60 {0x0c50, 0x19001c00, 0xff00ff00}, 61 {0x0c54, 0x00002100, 0x0000ff00}, 62 {0x0c58, 0x00000060, 0x000000ff}, 63 {0x0c60, 0x80131e7c, 0xffffffff}, 64 {0x0c64, 0x8400cb02, 0xff00ffff}, 65 {0x0c68, 0x17078200, 0xffffff00}, 66 {0x0c6c, 0x00000016, 0x000000ff}, 67 {0x0c74, 0x00000400, 0x0000ff00}, 68 {0x0c78, 0x0000c000, 0x0000ff00}, 69 {0x0c00, 0x00000003, 0x000000ff}, 70 }; 71 72 static struct serdes_cfg cfg_phyb_10p3125g_16bit_lane[] = { 73 {0x0204, 0x00000080, 0x000000ff}, 74 {0x0208, 0x0000920d, 0x0000ffff}, 75 {0x0204, 0xfc000000, 0xff000000}, 76 {0x0208, 0x00009104, 0x0000ffff}, 77 {0x0210, 0x1a000000, 0xff000000}, 78 {0x0214, 0x00006b58, 0x00ffffff}, 79 {0x0218, 0x75800084, 0xffff00ff}, 80 {0x022c, 0x00300000, 0x00ff0000}, 81 {0x0230, 0x00003800, 0x0000ff00}, 82 {0x024c, 0x008f0000, 0x00ff0000}, 83 {0x0250, 0x30000000, 0xff000000}, 84 {0x0260, 0x00000002, 0x000000ff}, 85 {0x0264, 0x00000057, 0x000000ff}, 86 {0x0268, 0x00575700, 0x00ffff00}, 87 {0x0278, 0xff000000, 0xff000000}, 88 {0x0280, 0x00500050, 0x00ff00ff}, 89 {0x0284, 0x00001f15, 0x0000ffff}, 90 {0x028c, 0x00006f00, 0x0000ff00}, 91 {0x0294, 0x00000000, 0xffffff00}, 92 {0x0298, 0x00002640, 0xff00ffff}, 93 {0x029c, 0x00000003, 0x000000ff}, 94 {0x02a4, 0x00000f13, 0x0000ffff}, 95 {0x02a8, 0x0001b600, 0x00ffff00}, 96 {0x0380, 0x00000030, 0x000000ff}, 97 {0x03c0, 0x00000200, 0x0000ff00}, 98 {0x03cc, 0x00000018, 0x000000ff}, 99 {0x03cc, 0x00000000, 0x000000ff}, 100 }; 101 102 static struct serdes_cfg cfg_phyb_10p3125g_comlane[] = { 103 {0x0a00, 0x00000800, 0x0000ff00}, 104 {0x0a84, 0x00000000, 0x000000ff}, 105 {0x0a8c, 0x00130000, 0x00ff0000}, 106 {0x0a90, 0x77a00000, 0xffff0000}, 107 {0x0a94, 0x00007777, 0x0000ffff}, 108 {0x0b08, 0x000f0000, 0xffff0000}, 109 {0x0b0c, 0x000f0000, 0x00ffffff}, 110 {0x0b10, 0xbe000000, 0xff000000}, 111 {0x0b14, 0x000000ff, 0x000000ff}, 112 {0x0b18, 0x00000014, 0x000000ff}, 113 {0x0b5c, 0x981b0000, 0xffff0000}, 114 {0x0b64, 0x00001100, 0x0000ff00}, 115 {0x0b78, 0x00000c00, 0x0000ff00}, 116 {0x0abc, 0xff000000, 0xff000000}, 117 {0x0ac0, 0x0000008b, 0x000000ff}, 118 }; 119 120 static struct serdes_cfg cfg_cm_c1_c2[] = { 121 {0x0208, 0x00000000, 0x00000f00}, 122 {0x0208, 0x00000000, 0x0000001f}, 123 {0x0204, 0x00000000, 0x00040000}, 124 {0x0208, 0x000000a0, 0x000000e0}, 125 }; 126 127 static void netcp_xgbe_serdes_cmu_init(void __iomem *serdes_regs) 128 { 129 int i; 130 131 /* cmu0 setup */ 132 for (i = 0; i < ARRAY_SIZE(cfg_phyb_1p25g_156p25mhz_cmu0); i++) { 133 reg_rmw(serdes_regs + cfg_phyb_1p25g_156p25mhz_cmu0[i].ofs, 134 cfg_phyb_1p25g_156p25mhz_cmu0[i].val, 135 cfg_phyb_1p25g_156p25mhz_cmu0[i].mask); 136 } 137 138 /* cmu1 setup */ 139 for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_156p25mhz_cmu1); i++) { 140 reg_rmw(serdes_regs + cfg_phyb_10p3125g_156p25mhz_cmu1[i].ofs, 141 cfg_phyb_10p3125g_156p25mhz_cmu1[i].val, 142 cfg_phyb_10p3125g_156p25mhz_cmu1[i].mask); 143 } 144 } 145 146 /* lane is 0 based */ 147 static void netcp_xgbe_serdes_lane_config( 148 void __iomem *serdes_regs, int lane) 149 { 150 int i; 151 152 /* lane setup */ 153 for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_16bit_lane); i++) { 154 reg_rmw(serdes_regs + 155 cfg_phyb_10p3125g_16bit_lane[i].ofs + 156 (0x200 * lane), 157 cfg_phyb_10p3125g_16bit_lane[i].val, 158 cfg_phyb_10p3125g_16bit_lane[i].mask); 159 } 160 161 /* disable auto negotiation*/ 162 reg_rmw(serdes_regs + (0x200 * lane) + 0x0380, 163 0x00000000, 0x00000010); 164 165 /* disable link training */ 166 reg_rmw(serdes_regs + (0x200 * lane) + 0x03c0, 167 0x00000000, 0x00000200); 168 } 169 170 static void netcp_xgbe_serdes_com_enable(void __iomem *serdes_regs) 171 { 172 int i; 173 174 for (i = 0; i < ARRAY_SIZE(cfg_phyb_10p3125g_comlane); i++) { 175 reg_rmw(serdes_regs + cfg_phyb_10p3125g_comlane[i].ofs, 176 cfg_phyb_10p3125g_comlane[i].val, 177 cfg_phyb_10p3125g_comlane[i].mask); 178 } 179 } 180 181 static void netcp_xgbe_serdes_lane_enable( 182 void __iomem *serdes_regs, int lane) 183 { 184 /* Set Lane Control Rate */ 185 writel(0xe0e9e038, serdes_regs + 0x1fe0 + (4 * lane)); 186 } 187 188 static void netcp_xgbe_serdes_phyb_rst_clr(void __iomem *serdes_regs) 189 { 190 reg_rmw(serdes_regs + 0x0a00, 0x0000001f, 0x000000ff); 191 } 192 193 static void netcp_xgbe_serdes_pll_disable(void __iomem *serdes_regs) 194 { 195 writel(0x88000000, serdes_regs + 0x1ff4); 196 } 197 198 static void netcp_xgbe_serdes_pll_enable(void __iomem *serdes_regs) 199 { 200 netcp_xgbe_serdes_phyb_rst_clr(serdes_regs); 201 writel(0xee000000, serdes_regs + 0x1ff4); 202 } 203 204 static int netcp_xgbe_wait_pll_locked(void __iomem *sw_regs) 205 { 206 unsigned long timeout; 207 int ret = 0; 208 u32 val_1, val_0; 209 210 timeout = jiffies + msecs_to_jiffies(500); 211 do { 212 val_0 = (readl(sw_regs + XGBE_SGMII_1_OFFSET) & BIT(4)); 213 val_1 = (readl(sw_regs + XGBE_SGMII_2_OFFSET) & BIT(4)); 214 215 if (val_1 && val_0) 216 return 0; 217 218 if (time_after(jiffies, timeout)) { 219 ret = -ETIMEDOUT; 220 break; 221 } 222 223 cpu_relax(); 224 } while (true); 225 226 pr_err("XGBE serdes not locked: time out.\n"); 227 return ret; 228 } 229 230 static void netcp_xgbe_serdes_enable_xgmii_port(void __iomem *sw_regs) 231 { 232 writel(0x03, sw_regs + XGBE_CTRL_OFFSET); 233 } 234 235 static u32 netcp_xgbe_serdes_read_tbus_val(void __iomem *serdes_regs) 236 { 237 u32 tmp; 238 239 if (PHY_A(serdes_regs)) { 240 tmp = (readl(serdes_regs + 0x0ec) >> 24) & 0x0ff; 241 tmp |= ((readl(serdes_regs + 0x0fc) >> 16) & 0x00f00); 242 } else { 243 tmp = (readl(serdes_regs + 0x0f8) >> 16) & 0x0fff; 244 } 245 246 return tmp; 247 } 248 249 static void netcp_xgbe_serdes_write_tbus_addr(void __iomem *serdes_regs, 250 int select, int ofs) 251 { 252 if (PHY_A(serdes_regs)) { 253 reg_rmw(serdes_regs + 0x0008, ((select << 5) + ofs) << 24, 254 ~0x00ffffff); 255 return; 256 } 257 258 /* For 2 lane Phy-B, lane0 is actually lane1 */ 259 switch (select) { 260 case 1: 261 select = 2; 262 break; 263 case 2: 264 select = 3; 265 break; 266 default: 267 return; 268 } 269 270 reg_rmw(serdes_regs + 0x00fc, ((select << 8) + ofs) << 16, ~0xf800ffff); 271 } 272 273 static u32 netcp_xgbe_serdes_read_select_tbus(void __iomem *serdes_regs, 274 int select, int ofs) 275 { 276 /* Set tbus address */ 277 netcp_xgbe_serdes_write_tbus_addr(serdes_regs, select, ofs); 278 /* Get TBUS Value */ 279 return netcp_xgbe_serdes_read_tbus_val(serdes_regs); 280 } 281 282 static void netcp_xgbe_serdes_reset_cdr(void __iomem *serdes_regs, 283 void __iomem *sig_detect_reg, int lane) 284 { 285 u32 tmp, dlpf, tbus; 286 287 /*Get the DLPF values */ 288 tmp = netcp_xgbe_serdes_read_select_tbus( 289 serdes_regs, lane + 1, 5); 290 291 dlpf = tmp >> 2; 292 293 if (dlpf < 400 || dlpf > 700) { 294 reg_rmw(sig_detect_reg, VAL_SH(2, 1), MASK_WID_SH(2, 1)); 295 mdelay(1); 296 reg_rmw(sig_detect_reg, VAL_SH(0, 1), MASK_WID_SH(2, 1)); 297 } else { 298 tbus = netcp_xgbe_serdes_read_select_tbus(serdes_regs, lane + 299 1, 0xe); 300 301 pr_debug("XGBE: CDR centered, DLPF: %4d,%d,%d.\n", 302 tmp >> 2, tmp & 3, (tbus >> 2) & 3); 303 } 304 } 305 306 /* Call every 100 ms */ 307 static int netcp_xgbe_check_link_status(void __iomem *serdes_regs, 308 void __iomem *sw_regs, u32 lanes, 309 u32 *current_state, u32 *lane_down) 310 { 311 void __iomem *pcsr_base = sw_regs + 0x0600; 312 void __iomem *sig_detect_reg; 313 u32 pcsr_rx_stat, blk_lock, blk_errs; 314 int loss, i, status = 1; 315 316 for (i = 0; i < lanes; i++) { 317 /* Get the Loss bit */ 318 loss = readl(serdes_regs + 0x1fc0 + 0x20 + (i * 0x04)) & 0x1; 319 320 /* Get Block Errors and Block Lock bits */ 321 pcsr_rx_stat = readl(pcsr_base + 0x0c + (i * 0x80)); 322 blk_lock = (pcsr_rx_stat >> 30) & 0x1; 323 blk_errs = (pcsr_rx_stat >> 16) & 0x0ff; 324 325 /* Get Signal Detect Overlay Address */ 326 sig_detect_reg = serdes_regs + (i * 0x200) + 0x200 + 0x04; 327 328 /* If Block errors maxed out, attempt recovery! */ 329 if (blk_errs == 0x0ff) 330 blk_lock = 0; 331 332 switch (current_state[i]) { 333 case 0: 334 /* if good link lock the signal detect ON! */ 335 if (!loss && blk_lock) { 336 pr_debug("XGBE PCSR Linked Lane: %d\n", i); 337 reg_rmw(sig_detect_reg, VAL_SH(3, 1), 338 MASK_WID_SH(2, 1)); 339 current_state[i] = 1; 340 } else if (!blk_lock) { 341 /* if no lock, then reset CDR */ 342 pr_debug("XGBE PCSR Recover Lane: %d\n", i); 343 netcp_xgbe_serdes_reset_cdr(serdes_regs, 344 sig_detect_reg, i); 345 } 346 break; 347 348 case 1: 349 if (!blk_lock) { 350 /* Link Lost? */ 351 lane_down[i] = 1; 352 current_state[i] = 2; 353 } 354 break; 355 356 case 2: 357 if (blk_lock) 358 /* Nope just noise */ 359 current_state[i] = 1; 360 else { 361 /* Lost the block lock, reset CDR if it is 362 * not centered and go back to sync state 363 */ 364 netcp_xgbe_serdes_reset_cdr(serdes_regs, 365 sig_detect_reg, i); 366 current_state[i] = 0; 367 } 368 break; 369 370 default: 371 pr_err("XGBE: unknown current_state[%d] %d\n", 372 i, current_state[i]); 373 break; 374 } 375 376 if (blk_errs > 0) { 377 /* Reset the Error counts! */ 378 reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x19, 0), 379 MASK_WID_SH(8, 0)); 380 381 reg_rmw(pcsr_base + 0x08 + (i * 0x80), VAL_SH(0x00, 0), 382 MASK_WID_SH(8, 0)); 383 } 384 385 status &= (current_state[i] == 1); 386 } 387 388 return status; 389 } 390 391 static int netcp_xgbe_serdes_check_lane(void __iomem *serdes_regs, 392 void __iomem *sw_regs) 393 { 394 u32 current_state[2] = {0, 0}; 395 int retries = 0, link_up; 396 u32 lane_down[2]; 397 398 do { 399 lane_down[0] = 0; 400 lane_down[1] = 0; 401 402 link_up = netcp_xgbe_check_link_status(serdes_regs, sw_regs, 2, 403 current_state, 404 lane_down); 405 406 /* if we did not get link up then wait 100ms before calling 407 * it again 408 */ 409 if (link_up) 410 break; 411 412 if (lane_down[0]) 413 pr_debug("XGBE: detected link down on lane 0\n"); 414 415 if (lane_down[1]) 416 pr_debug("XGBE: detected link down on lane 1\n"); 417 418 if (++retries > 1) { 419 pr_debug("XGBE: timeout waiting for serdes link up\n"); 420 return -ETIMEDOUT; 421 } 422 mdelay(100); 423 } while (!link_up); 424 425 pr_debug("XGBE: PCSR link is up\n"); 426 return 0; 427 } 428 429 static void netcp_xgbe_serdes_setup_cm_c1_c2(void __iomem *serdes_regs, 430 int lane, int cm, int c1, int c2) 431 { 432 int i; 433 434 for (i = 0; i < ARRAY_SIZE(cfg_cm_c1_c2); i++) { 435 reg_rmw(serdes_regs + cfg_cm_c1_c2[i].ofs + (0x200 * lane), 436 cfg_cm_c1_c2[i].val, 437 cfg_cm_c1_c2[i].mask); 438 } 439 } 440 441 static void netcp_xgbe_reset_serdes(void __iomem *serdes_regs) 442 { 443 /* Toggle the POR_EN bit in CONFIG.CPU_CTRL */ 444 /* enable POR_EN bit */ 445 reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, POR_EN, POR_EN); 446 usleep_range(10, 100); 447 448 /* disable POR_EN bit */ 449 reg_rmw(serdes_regs + PCSR_CPU_CTRL_OFFSET, 0, POR_EN); 450 usleep_range(10, 100); 451 } 452 453 static int netcp_xgbe_serdes_config(void __iomem *serdes_regs, 454 void __iomem *sw_regs) 455 { 456 u32 ret, i; 457 458 netcp_xgbe_serdes_pll_disable(serdes_regs); 459 netcp_xgbe_serdes_cmu_init(serdes_regs); 460 461 for (i = 0; i < 2; i++) 462 netcp_xgbe_serdes_lane_config(serdes_regs, i); 463 464 netcp_xgbe_serdes_com_enable(serdes_regs); 465 /* This is EVM + RTM-BOC specific */ 466 for (i = 0; i < 2; i++) 467 netcp_xgbe_serdes_setup_cm_c1_c2(serdes_regs, i, 0, 0, 5); 468 469 netcp_xgbe_serdes_pll_enable(serdes_regs); 470 for (i = 0; i < 2; i++) 471 netcp_xgbe_serdes_lane_enable(serdes_regs, i); 472 473 /* SB PLL Status Poll */ 474 ret = netcp_xgbe_wait_pll_locked(sw_regs); 475 if (ret) 476 return ret; 477 478 netcp_xgbe_serdes_enable_xgmii_port(sw_regs); 479 netcp_xgbe_serdes_check_lane(serdes_regs, sw_regs); 480 return ret; 481 } 482 483 int netcp_xgbe_serdes_init(void __iomem *serdes_regs, void __iomem *xgbe_regs) 484 { 485 u32 val; 486 487 /* read COMLANE bits 4:0 */ 488 val = readl(serdes_regs + 0xa00); 489 if (val & 0x1f) { 490 pr_debug("XGBE: serdes already in operation - reset\n"); 491 netcp_xgbe_reset_serdes(serdes_regs); 492 } 493 return netcp_xgbe_serdes_config(serdes_regs, xgbe_regs); 494 } 495