1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (C) 2015-2021 Texas Instruments Incorporated - https://www.ti.com 4 */ 5 6 #ifndef __ICSS_SWITCH_H 7 #define __ICSS_SWITCH_H 8 9 /* Basic Switch Parameters 10 * Used to auto compute offset addresses on L3 OCMC RAM. Do not modify these 11 * without changing firmware accordingly 12 */ 13 #define SWITCH_BUFFER_SIZE (64 * 1024) /* L3 buffer */ 14 #define ICSS_BLOCK_SIZE 32 /* data bytes per BD */ 15 #define BD_SIZE 4 /* byte buffer descriptor */ 16 #define NUM_QUEUES 4 /* Queues on Port 0/1/2 */ 17 18 #define PORT_LINK_MASK 0x1 19 #define PORT_IS_HD_MASK 0x2 20 21 /* Physical Port queue size (number of BDs). Same for both ports */ 22 #define QUEUE_1_SIZE 97 /* Network Management high */ 23 #define QUEUE_2_SIZE 97 /* Network Management low */ 24 #define QUEUE_3_SIZE 97 /* Protocol specific */ 25 #define QUEUE_4_SIZE 97 /* NRT (IP,ARP, ICMP) */ 26 27 /* Host queue size (number of BDs). Each BD points to data buffer of 32 bytes. 28 * HOST PORT QUEUES can buffer up to 4 full sized frames per queue 29 */ 30 #define HOST_QUEUE_1_SIZE 194 /* Protocol and VLAN priority 7 & 6 */ 31 #define HOST_QUEUE_2_SIZE 194 /* Protocol mid */ 32 #define HOST_QUEUE_3_SIZE 194 /* Protocol low */ 33 #define HOST_QUEUE_4_SIZE 194 /* NRT (IP, ARP, ICMP) */ 34 35 #define COL_QUEUE_SIZE 0 36 37 /* NRT Buffer descriptor definition 38 * Each buffer descriptor points to a max 32 byte block and has 32 bit in size 39 * to have atomic operation. 40 * PRU can address bytewise into memory. 41 * Definition of 32 bit descriptor is as follows 42 * 43 * Bits Name Meaning 44 * ============================================================================= 45 * 0..7 Index points to index in buffer queue, max 256 x 32 46 * byte blocks can be addressed 47 * 6 LookupSuccess For switch, FDB lookup was successful (source 48 * MAC address found in FDB). 49 * For RED, NodeTable lookup was successful. 50 * 7 Flood Packet should be flooded (destination MAC 51 * address found in FDB). For switch only. 52 * 8..12 Block_length number of valid bytes in this specific block. 53 * Will be <=32 bytes on last block of packet 54 * 13 More "More" bit indicating that there are more blocks 55 * 14 Shadow indicates that "index" is pointing into shadow 56 * buffer 57 * 15 TimeStamp indicates that this packet has time stamp in 58 * separate buffer - only needed if PTP runs on 59 * host 60 * 16..17 Port different meaning for ingress and egress, 61 * Ingress: Port = 0 indicates phy port 1 and 62 * Port = 1 indicates phy port 2. 63 * Egress: 0 sends on phy port 1 and 1 sends on 64 * phy port 2. Port = 2 goes over MAC table 65 * look-up 66 * 18..28 Length 11 bit of total packet length which is put into 67 * first BD only so that host access only one BD 68 * 29 VlanTag indicates that packet has Length/Type field of 69 * 0x08100 with VLAN tag in following byte 70 * 30 Broadcast indicates that packet goes out on both physical 71 * ports, there will be two bd but only one buffer 72 * 31 Error indicates there was an error in the packet 73 */ 74 #define PRUETH_BD_START_FLAG_MASK BIT(0) 75 #define PRUETH_BD_START_FLAG_SHIFT 0 76 77 #define PRUETH_BD_HSR_FRAME_MASK BIT(4) 78 #define PRUETH_BD_HSR_FRAME_SHIFT 4 79 80 #define PRUETH_BD_SUP_HSR_FRAME_MASK BIT(5) 81 #define PRUETH_BD_SUP_HSR_FRAME_SHIFT 5 82 83 #define PRUETH_BD_LOOKUP_SUCCESS_MASK BIT(6) 84 #define PRUETH_BD_LOOKUP_SUCCESS_SHIFT 6 85 86 #define PRUETH_BD_SW_FLOOD_MASK BIT(7) 87 #define PRUETH_BD_SW_FLOOD_SHIFT 7 88 89 #define PRUETH_BD_SHADOW_MASK BIT(14) 90 #define PRUETH_BD_SHADOW_SHIFT 14 91 92 #define PRUETH_BD_TIMESTAMP_MASK BIT(15) 93 #define PRUETH_BD_TIMESTAMP_SHIFT 15 94 95 #define PRUETH_BD_PORT_MASK GENMASK(17, 16) 96 #define PRUETH_BD_PORT_SHIFT 16 97 98 #define PRUETH_BD_LENGTH_MASK GENMASK(28, 18) 99 #define PRUETH_BD_LENGTH_SHIFT 18 100 101 #define PRUETH_BD_BROADCAST_MASK BIT(30) 102 #define PRUETH_BD_BROADCAST_SHIFT 30 103 104 #define PRUETH_BD_ERROR_MASK BIT(31) 105 #define PRUETH_BD_ERROR_SHIFT 31 106 107 /* The following offsets indicate which sections of the memory are used 108 * for EMAC internal tasks 109 */ 110 #define DRAM_START_OFFSET 0x1E98 111 #define SRAM_START_OFFSET 0x400 112 113 /* General Purpose Statistics 114 * These are present on both PRU0 and PRU1 DRAM 115 */ 116 /* base statistics offset */ 117 #define STATISTICS_OFFSET 0x1F00 118 #define STAT_SIZE 0x98 119 120 /* The following offsets indicate which sections of the memory are used 121 * for switch internal tasks 122 */ 123 #define SWITCH_SPECIFIC_DRAM0_START_SIZE 0x100 124 #define SWITCH_SPECIFIC_DRAM0_START_OFFSET 0x1F00 125 126 #define SWITCH_SPECIFIC_DRAM1_START_SIZE 0x300 127 #define SWITCH_SPECIFIC_DRAM1_START_OFFSET 0x1D00 128 129 /* Offset for storing 130 * 1. Storm Prevention Params 131 * 2. PHY Speed Offset 132 * 3. Port Status Offset 133 * These are present on both PRU0 and PRU1 134 */ 135 /* 4 bytes */ 136 #define STORM_PREVENTION_OFFSET_BC (STATISTICS_OFFSET + STAT_SIZE) 137 /* 4 bytes */ 138 #define PHY_SPEED_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 4) 139 /* 1 byte */ 140 #define PORT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 8) 141 /* 1 byte */ 142 #define COLLISION_COUNTER (STATISTICS_OFFSET + STAT_SIZE + 9) 143 /* 4 bytes */ 144 #define RX_PKT_SIZE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 10) 145 /* 4 bytes */ 146 #define PORT_CONTROL_ADDR (STATISTICS_OFFSET + STAT_SIZE + 14) 147 /* 6 bytes */ 148 #define PORT_MAC_ADDR (STATISTICS_OFFSET + STAT_SIZE + 18) 149 /* 1 byte */ 150 #define RX_INT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 24) 151 /* 4 bytes */ 152 #define STORM_PREVENTION_OFFSET_MC (STATISTICS_OFFSET + STAT_SIZE + 25) 153 /* 4 bytes */ 154 #define STORM_PREVENTION_OFFSET_UC (STATISTICS_OFFSET + STAT_SIZE + 29) 155 /* 4 bytes ? */ 156 #define STP_INVALID_STATE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 33) 157 158 /* DRAM1 Offsets for Switch */ 159 /* 4 queue descriptors for port 0 (host receive) */ 160 #define P0_QUEUE_DESC_OFFSET 0x1E7C 161 #define P1_QUEUE_DESC_OFFSET 0x1E9C 162 #define P2_QUEUE_DESC_OFFSET 0x1EBC 163 /* collision descriptor of port 0 */ 164 #define P0_COL_QUEUE_DESC_OFFSET 0x1E64 165 #define P1_COL_QUEUE_DESC_OFFSET 0x1E6C 166 #define P2_COL_QUEUE_DESC_OFFSET 0x1E74 167 /* Collision Status Register 168 * P0: bit 0 is pending flag, bit 1..2 indicates which queue, 169 * P1: bit 8 is pending flag, 9..10 is queue number 170 * P2: bit 16 is pending flag, 17..18 is queue number, remaining bits are 0. 171 */ 172 #define COLLISION_STATUS_ADDR 0x1E60 173 174 #define INTERFACE_MAC_ADDR 0x1E58 175 #define P2_MAC_ADDR 0x1E50 176 #define P1_MAC_ADDR 0x1E48 177 178 #define QUEUE_SIZE_ADDR 0x1E30 179 #define QUEUE_OFFSET_ADDR 0x1E18 180 #define QUEUE_DESCRIPTOR_OFFSET_ADDR 0x1E00 181 182 #define COL_RX_CONTEXT_P2_OFFSET_ADDR (COL_RX_CONTEXT_P1_OFFSET_ADDR + 12) 183 #define COL_RX_CONTEXT_P1_OFFSET_ADDR (COL_RX_CONTEXT_P0_OFFSET_ADDR + 12) 184 #define COL_RX_CONTEXT_P0_OFFSET_ADDR (P2_Q4_RX_CONTEXT_OFFSET + 8) 185 186 /* Port 2 Rx Context */ 187 #define P2_Q4_RX_CONTEXT_OFFSET (P2_Q3_RX_CONTEXT_OFFSET + 8) 188 #define P2_Q3_RX_CONTEXT_OFFSET (P2_Q2_RX_CONTEXT_OFFSET + 8) 189 #define P2_Q2_RX_CONTEXT_OFFSET (P2_Q1_RX_CONTEXT_OFFSET + 8) 190 #define P2_Q1_RX_CONTEXT_OFFSET RX_CONTEXT_P2_Q1_OFFSET_ADDR 191 #define RX_CONTEXT_P2_Q1_OFFSET_ADDR (P1_Q4_RX_CONTEXT_OFFSET + 8) 192 193 /* Port 1 Rx Context */ 194 #define P1_Q4_RX_CONTEXT_OFFSET (P1_Q3_RX_CONTEXT_OFFSET + 8) 195 #define P1_Q3_RX_CONTEXT_OFFSET (P1_Q2_RX_CONTEXT_OFFSET + 8) 196 #define P1_Q2_RX_CONTEXT_OFFSET (P1_Q1_RX_CONTEXT_OFFSET + 8) 197 #define P1_Q1_RX_CONTEXT_OFFSET (RX_CONTEXT_P1_Q1_OFFSET_ADDR) 198 #define RX_CONTEXT_P1_Q1_OFFSET_ADDR (P0_Q4_RX_CONTEXT_OFFSET + 8) 199 200 /* Host Port Rx Context */ 201 #define P0_Q4_RX_CONTEXT_OFFSET (P0_Q3_RX_CONTEXT_OFFSET + 8) 202 #define P0_Q3_RX_CONTEXT_OFFSET (P0_Q2_RX_CONTEXT_OFFSET + 8) 203 #define P0_Q2_RX_CONTEXT_OFFSET (P0_Q1_RX_CONTEXT_OFFSET + 8) 204 #define P0_Q1_RX_CONTEXT_OFFSET RX_CONTEXT_P0_Q1_OFFSET_ADDR 205 #define RX_CONTEXT_P0_Q1_OFFSET_ADDR (COL_TX_CONTEXT_P2_Q1_OFFSET_ADDR + 8) 206 207 /* Port 2 Tx Collision Context */ 208 #define COL_TX_CONTEXT_P2_Q1_OFFSET_ADDR (COL_TX_CONTEXT_P1_Q1_OFFSET_ADDR + 8) 209 /* Port 1 Tx Collision Context */ 210 #define COL_TX_CONTEXT_P1_Q1_OFFSET_ADDR (P2_Q4_TX_CONTEXT_OFFSET + 8) 211 212 /* Port 2 */ 213 #define P2_Q4_TX_CONTEXT_OFFSET (P2_Q3_TX_CONTEXT_OFFSET + 8) 214 #define P2_Q3_TX_CONTEXT_OFFSET (P2_Q2_TX_CONTEXT_OFFSET + 8) 215 #define P2_Q2_TX_CONTEXT_OFFSET (P2_Q1_TX_CONTEXT_OFFSET + 8) 216 #define P2_Q1_TX_CONTEXT_OFFSET TX_CONTEXT_P2_Q1_OFFSET_ADDR 217 #define TX_CONTEXT_P2_Q1_OFFSET_ADDR (P1_Q4_TX_CONTEXT_OFFSET + 8) 218 219 /* Port 1 */ 220 #define P1_Q4_TX_CONTEXT_OFFSET (P1_Q3_TX_CONTEXT_OFFSET + 8) 221 #define P1_Q3_TX_CONTEXT_OFFSET (P1_Q2_TX_CONTEXT_OFFSET + 8) 222 #define P1_Q2_TX_CONTEXT_OFFSET (P1_Q1_TX_CONTEXT_OFFSET + 8) 223 #define P1_Q1_TX_CONTEXT_OFFSET TX_CONTEXT_P1_Q1_OFFSET_ADDR 224 #define TX_CONTEXT_P1_Q1_OFFSET_ADDR SWITCH_SPECIFIC_DRAM1_START_OFFSET 225 226 /* DRAM Offsets for EMAC 227 * Present on Both DRAM0 and DRAM1 228 */ 229 230 /* 4 queue descriptors for port tx = 32 bytes */ 231 #define TX_CONTEXT_Q1_OFFSET_ADDR (PORT_QUEUE_DESC_OFFSET + 32) 232 #define PORT_QUEUE_DESC_OFFSET (ICSS_EMAC_TTS_CYC_TX_SOF + 8) 233 234 /* EMAC Time Triggered Send Offsets */ 235 #define ICSS_EMAC_TTS_CYC_TX_SOF (ICSS_EMAC_TTS_PREV_TX_SOF + 8) 236 #define ICSS_EMAC_TTS_PREV_TX_SOF \ 237 (ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET + 4) 238 #define ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET (ICSS_EMAC_TTS_STATUS_OFFSET \ 239 + 4) 240 #define ICSS_EMAC_TTS_STATUS_OFFSET (ICSS_EMAC_TTS_CFG_TIME_OFFSET + 4) 241 #define ICSS_EMAC_TTS_CFG_TIME_OFFSET (ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET + 4) 242 #define ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET \ 243 (ICSS_EMAC_TTS_CYCLE_START_OFFSET + 8) 244 #define ICSS_EMAC_TTS_CYCLE_START_OFFSET ICSS_EMAC_TTS_BASE_OFFSET 245 #define ICSS_EMAC_TTS_BASE_OFFSET DRAM_START_OFFSET 246 247 /* Shared RAM offsets for EMAC */ 248 249 /* Queue Descriptors */ 250 251 /* 4 queue descriptors for port 0 (host receive). 32 bytes */ 252 #define HOST_QUEUE_DESC_OFFSET (HOST_QUEUE_SIZE_ADDR + 16) 253 254 /* table offset for queue size: 255 * 3 ports * 4 Queues * 1 byte offset = 12 bytes 256 */ 257 #define HOST_QUEUE_SIZE_ADDR (HOST_QUEUE_OFFSET_ADDR + 8) 258 /* table offset for queue: 259 * 4 Queues * 2 byte offset = 8 bytes 260 */ 261 #define HOST_QUEUE_OFFSET_ADDR (HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR + 8) 262 /* table offset for Host queue descriptors: 263 * 1 ports * 4 Queues * 2 byte offset = 8 bytes 264 */ 265 #define HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR (HOST_Q4_RX_CONTEXT_OFFSET + 8) 266 267 /* Host Port Rx Context */ 268 #define HOST_Q4_RX_CONTEXT_OFFSET (HOST_Q3_RX_CONTEXT_OFFSET + 8) 269 #define HOST_Q3_RX_CONTEXT_OFFSET (HOST_Q2_RX_CONTEXT_OFFSET + 8) 270 #define HOST_Q2_RX_CONTEXT_OFFSET (HOST_Q1_RX_CONTEXT_OFFSET + 8) 271 #define HOST_Q1_RX_CONTEXT_OFFSET (EMAC_PROMISCUOUS_MODE_OFFSET + 4) 272 273 /* Promiscuous mode control */ 274 #define EMAC_P1_PROMISCUOUS_BIT BIT(0) 275 #define EMAC_P2_PROMISCUOUS_BIT BIT(1) 276 #define EMAC_PROMISCUOUS_MODE_OFFSET (EMAC_RESERVED + 4) 277 #define EMAC_RESERVED EOF_48K_BUFFER_BD 278 279 /* allow for max 48k buffer which spans the descriptors up to 0x1800 6kB */ 280 #define EOF_48K_BUFFER_BD (P0_BUFFER_DESC_OFFSET + HOST_BD_SIZE + \ 281 PORT_BD_SIZE) 282 283 #define HOST_BD_SIZE ((HOST_QUEUE_1_SIZE + \ 284 HOST_QUEUE_2_SIZE + HOST_QUEUE_3_SIZE + \ 285 HOST_QUEUE_4_SIZE) * BD_SIZE) 286 #define PORT_BD_SIZE ((QUEUE_1_SIZE + QUEUE_2_SIZE + \ 287 QUEUE_3_SIZE + QUEUE_4_SIZE) * 2 * BD_SIZE) 288 289 #define END_OF_BD_POOL (P2_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE) 290 #define P2_Q4_BD_OFFSET (P2_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE) 291 #define P2_Q3_BD_OFFSET (P2_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE) 292 #define P2_Q2_BD_OFFSET (P2_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE) 293 #define P2_Q1_BD_OFFSET (P1_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE) 294 #define P1_Q4_BD_OFFSET (P1_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE) 295 #define P1_Q3_BD_OFFSET (P1_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE) 296 #define P1_Q2_BD_OFFSET (P1_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE) 297 #define P1_Q1_BD_OFFSET (P0_Q4_BD_OFFSET + HOST_QUEUE_4_SIZE * BD_SIZE) 298 #define P0_Q4_BD_OFFSET (P0_Q3_BD_OFFSET + HOST_QUEUE_3_SIZE * BD_SIZE) 299 #define P0_Q3_BD_OFFSET (P0_Q2_BD_OFFSET + HOST_QUEUE_2_SIZE * BD_SIZE) 300 #define P0_Q2_BD_OFFSET (P0_Q1_BD_OFFSET + HOST_QUEUE_1_SIZE * BD_SIZE) 301 #define P0_Q1_BD_OFFSET P0_BUFFER_DESC_OFFSET 302 #define P0_BUFFER_DESC_OFFSET SRAM_START_OFFSET 303 304 /* Memory Usage of L3 OCMC RAM */ 305 306 /* L3 64KB Memory - mainly buffer Pool */ 307 #define END_OF_BUFFER_POOL (P2_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \ 308 ICSS_BLOCK_SIZE) 309 #define P2_Q4_BUFFER_OFFSET (P2_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \ 310 ICSS_BLOCK_SIZE) 311 #define P2_Q3_BUFFER_OFFSET (P2_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \ 312 ICSS_BLOCK_SIZE) 313 #define P2_Q2_BUFFER_OFFSET (P2_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \ 314 ICSS_BLOCK_SIZE) 315 #define P2_Q1_BUFFER_OFFSET (P1_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \ 316 ICSS_BLOCK_SIZE) 317 #define P1_Q4_BUFFER_OFFSET (P1_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \ 318 ICSS_BLOCK_SIZE) 319 #define P1_Q3_BUFFER_OFFSET (P1_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \ 320 ICSS_BLOCK_SIZE) 321 #define P1_Q2_BUFFER_OFFSET (P1_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \ 322 ICSS_BLOCK_SIZE) 323 #define P1_Q1_BUFFER_OFFSET (P0_Q4_BUFFER_OFFSET + HOST_QUEUE_4_SIZE * \ 324 ICSS_BLOCK_SIZE) 325 #define P0_Q4_BUFFER_OFFSET (P0_Q3_BUFFER_OFFSET + HOST_QUEUE_3_SIZE * \ 326 ICSS_BLOCK_SIZE) 327 #define P0_Q3_BUFFER_OFFSET (P0_Q2_BUFFER_OFFSET + HOST_QUEUE_2_SIZE * \ 328 ICSS_BLOCK_SIZE) 329 #define P0_Q2_BUFFER_OFFSET (P0_Q1_BUFFER_OFFSET + HOST_QUEUE_1_SIZE * \ 330 ICSS_BLOCK_SIZE) 331 #define P0_COL_BUFFER_OFFSET 0xEE00 332 #define P0_Q1_BUFFER_OFFSET 0x0000 333 334 #define V2_1_FDB_TBL_LOC PRUETH_MEM_SHARED_RAM 335 #define V2_1_FDB_TBL_OFFSET 0x2000 336 337 #define FDB_INDEX_TBL_MAX_ENTRIES 256 338 #define FDB_MAC_TBL_MAX_ENTRIES 256 339 340 #define FDB_INDEX_TBL_OFFSET V2_1_FDB_TBL_OFFSET 341 #define FDB_INDEX_TBL_SIZE (FDB_INDEX_TBL_MAX_ENTRIES * \ 342 sizeof(struct fdb_index_tbl_entry)) 343 344 #define FDB_MAC_TBL_OFFSET (FDB_INDEX_TBL_OFFSET + FDB_INDEX_TBL_SIZE) 345 #define FDB_MAC_TBL_SIZE (FDB_MAC_TBL_MAX_ENTRIES * \ 346 sizeof(struct fdb_mac_tbl_entry)) 347 348 #define FDB_PORT1_STP_CFG_OFFSET (FDB_MAC_TBL_OFFSET + FDB_MAC_TBL_SIZE) 349 #define FDB_PORT_STP_CFG_SIZE sizeof(struct fdb_stp_config) 350 #define FDB_PORT2_STP_CFG_OFFSET (FDB_PORT1_STP_CFG_OFFSET + \ 351 FDB_PORT_STP_CFG_SIZE) 352 353 #define FDB_FLOOD_ENABLE_FLAGS_OFFSET (FDB_PORT2_STP_CFG_OFFSET + \ 354 FDB_PORT_STP_CFG_SIZE) 355 #define FDB_FLOOD_ENABLE_FLAGS_SIZE sizeof(struct fdb_flood_config) 356 357 #define FDB_LOCKS_OFFSET (FDB_FLOOD_ENABLE_FLAGS_OFFSET + \ 358 FDB_FLOOD_ENABLE_FLAGS_SIZE) 359 360 #endif /* __ICSS_SWITCH_H */ 361