1 /* SPDX-License-Identifier: GPL-2.0 */ 2 3 /* Copyright (C) 2015-2021 Texas Instruments Incorporated - https://www.ti.com 4 */ 5 6 #ifndef __ICSS_SWITCH_H 7 #define __ICSS_SWITCH_H 8 9 /* Basic Switch Parameters 10 * Used to auto compute offset addresses on L3 OCMC RAM. Do not modify these 11 * without changing firmware accordingly 12 */ 13 #define SWITCH_BUFFER_SIZE (64 * 1024) /* L3 buffer */ 14 #define ICSS_BLOCK_SIZE 32 /* data bytes per BD */ 15 #define BD_SIZE 4 /* byte buffer descriptor */ 16 #define NUM_QUEUES 4 /* Queues on Port 0/1/2 */ 17 18 #define PORT_LINK_MASK 0x1 19 #define PORT_IS_HD_MASK 0x2 20 21 /* Physical Port queue size (number of BDs). Same for both ports */ 22 #define QUEUE_1_SIZE 97 /* Network Management high */ 23 #define QUEUE_2_SIZE 97 /* Network Management low */ 24 #define QUEUE_3_SIZE 97 /* Protocol specific */ 25 #define QUEUE_4_SIZE 97 /* NRT (IP,ARP, ICMP) */ 26 27 /* Host queue size (number of BDs). Each BD points to data buffer of 32 bytes. 28 * HOST PORT QUEUES can buffer up to 4 full sized frames per queue 29 */ 30 #define HOST_QUEUE_1_SIZE 194 /* Protocol and VLAN priority 7 & 6 */ 31 #define HOST_QUEUE_2_SIZE 194 /* Protocol mid */ 32 #define HOST_QUEUE_3_SIZE 194 /* Protocol low */ 33 #define HOST_QUEUE_4_SIZE 194 /* NRT (IP, ARP, ICMP) */ 34 35 #define COL_QUEUE_SIZE 0 36 37 /* NRT Buffer descriptor definition 38 * Each buffer descriptor points to a max 32 byte block and has 32 bit in size 39 * to have atomic operation. 40 * PRU can address bytewise into memory. 41 * Definition of 32 bit descriptor is as follows 42 * 43 * Bits Name Meaning 44 * ============================================================================= 45 * 0..7 Index points to index in buffer queue, max 256 x 32 46 * byte blocks can be addressed 47 * 6 LookupSuccess For switch, FDB lookup was successful (source 48 * MAC address found in FDB). 49 * For RED, NodeTable lookup was successful. 50 * 7 Flood Packet should be flooded (destination MAC 51 * address found in FDB). For switch only. 52 * 8..12 Block_length number of valid bytes in this specific block. 53 * Will be <=32 bytes on last block of packet 54 * 13 More "More" bit indicating that there are more blocks 55 * 14 Shadow indicates that "index" is pointing into shadow 56 * buffer 57 * 15 TimeStamp indicates that this packet has time stamp in 58 * separate buffer - only needed if PTP runs on 59 * host 60 * 16..17 Port different meaning for ingress and egress, 61 * Ingress: Port = 0 indicates phy port 1 and 62 * Port = 1 indicates phy port 2. 63 * Egress: 0 sends on phy port 1 and 1 sends on 64 * phy port 2. Port = 2 goes over MAC table 65 * look-up 66 * 18..28 Length 11 bit of total packet length which is put into 67 * first BD only so that host access only one BD 68 * 29 VlanTag indicates that packet has Length/Type field of 69 * 0x08100 with VLAN tag in following byte 70 * 30 Broadcast indicates that packet goes out on both physical 71 * ports, there will be two bd but only one buffer 72 * 31 Error indicates there was an error in the packet 73 */ 74 #define PRUETH_BD_START_FLAG_MASK BIT(0) 75 #define PRUETH_BD_START_FLAG_SHIFT 0 76 77 #define PRUETH_BD_HSR_FRAME_MASK BIT(4) 78 #define PRUETH_BD_HSR_FRAME_SHIFT 4 79 80 #define PRUETH_BD_SUP_HSR_FRAME_MASK BIT(5) 81 #define PRUETH_BD_SUP_HSR_FRAME_SHIFT 5 82 83 #define PRUETH_BD_LOOKUP_SUCCESS_MASK BIT(6) 84 #define PRUETH_BD_LOOKUP_SUCCESS_SHIFT 6 85 86 #define PRUETH_BD_SW_FLOOD_MASK BIT(7) 87 #define PRUETH_BD_SW_FLOOD_SHIFT 7 88 89 #define PRUETH_BD_SHADOW_MASK BIT(14) 90 #define PRUETH_BD_SHADOW_SHIFT 14 91 92 #define PRUETH_BD_TIMESTAMP_MASK BIT(15) 93 #define PRUETH_BD_TIMESTAMP_SHIFT 15 94 95 #define PRUETH_BD_PORT_MASK GENMASK(17, 16) 96 #define PRUETH_BD_PORT_SHIFT 16 97 98 #define PRUETH_BD_LENGTH_MASK GENMASK(28, 18) 99 #define PRUETH_BD_LENGTH_SHIFT 18 100 101 #define PRUETH_BD_BROADCAST_MASK BIT(30) 102 #define PRUETH_BD_BROADCAST_SHIFT 30 103 104 #define PRUETH_BD_ERROR_MASK BIT(31) 105 #define PRUETH_BD_ERROR_SHIFT 31 106 107 /* The following offsets indicate which sections of the memory are used 108 * for EMAC internal tasks 109 */ 110 #define DRAM_START_OFFSET 0x1E98 111 #define SRAM_START_OFFSET 0x400 112 113 /* General Purpose Statistics 114 * These are present on both PRU0 and PRU1 DRAM 115 */ 116 /* base statistics offset */ 117 #define STATISTICS_OFFSET 0x1F00 118 #define STAT_SIZE 0x98 119 120 /* Offset for storing 121 * 1. Storm Prevention Params 122 * 2. PHY Speed Offset 123 * 3. Port Status Offset 124 * These are present on both PRU0 and PRU1 125 */ 126 /* 4 bytes */ 127 #define STORM_PREVENTION_OFFSET_BC (STATISTICS_OFFSET + STAT_SIZE) 128 /* 4 bytes */ 129 #define PHY_SPEED_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 4) 130 /* 1 byte */ 131 #define PORT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 8) 132 /* 1 byte */ 133 #define COLLISION_COUNTER (STATISTICS_OFFSET + STAT_SIZE + 9) 134 /* 4 bytes */ 135 #define RX_PKT_SIZE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 10) 136 /* 4 bytes */ 137 #define PORT_CONTROL_ADDR (STATISTICS_OFFSET + STAT_SIZE + 14) 138 /* 6 bytes */ 139 #define PORT_MAC_ADDR (STATISTICS_OFFSET + STAT_SIZE + 18) 140 /* 1 byte */ 141 #define RX_INT_STATUS_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 24) 142 /* 4 bytes */ 143 #define STORM_PREVENTION_OFFSET_MC (STATISTICS_OFFSET + STAT_SIZE + 25) 144 /* 4 bytes */ 145 #define STORM_PREVENTION_OFFSET_UC (STATISTICS_OFFSET + STAT_SIZE + 29) 146 /* 4 bytes ? */ 147 #define STP_INVALID_STATE_OFFSET (STATISTICS_OFFSET + STAT_SIZE + 33) 148 149 /* DRAM Offsets for EMAC 150 * Present on Both DRAM0 and DRAM1 151 */ 152 153 /* 4 queue descriptors for port tx = 32 bytes */ 154 #define TX_CONTEXT_Q1_OFFSET_ADDR (PORT_QUEUE_DESC_OFFSET + 32) 155 #define PORT_QUEUE_DESC_OFFSET (ICSS_EMAC_TTS_CYC_TX_SOF + 8) 156 157 /* EMAC Time Triggered Send Offsets */ 158 #define ICSS_EMAC_TTS_CYC_TX_SOF (ICSS_EMAC_TTS_PREV_TX_SOF + 8) 159 #define ICSS_EMAC_TTS_PREV_TX_SOF \ 160 (ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET + 4) 161 #define ICSS_EMAC_TTS_MISSED_CYCLE_CNT_OFFSET (ICSS_EMAC_TTS_STATUS_OFFSET \ 162 + 4) 163 #define ICSS_EMAC_TTS_STATUS_OFFSET (ICSS_EMAC_TTS_CFG_TIME_OFFSET + 4) 164 #define ICSS_EMAC_TTS_CFG_TIME_OFFSET (ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET + 4) 165 #define ICSS_EMAC_TTS_CYCLE_PERIOD_OFFSET \ 166 (ICSS_EMAC_TTS_CYCLE_START_OFFSET + 8) 167 #define ICSS_EMAC_TTS_CYCLE_START_OFFSET ICSS_EMAC_TTS_BASE_OFFSET 168 #define ICSS_EMAC_TTS_BASE_OFFSET DRAM_START_OFFSET 169 170 /* Shared RAM offsets for EMAC */ 171 172 /* Queue Descriptors */ 173 174 /* 4 queue descriptors for port 0 (host receive). 32 bytes */ 175 #define HOST_QUEUE_DESC_OFFSET (HOST_QUEUE_SIZE_ADDR + 16) 176 177 /* table offset for queue size: 178 * 3 ports * 4 Queues * 1 byte offset = 12 bytes 179 */ 180 #define HOST_QUEUE_SIZE_ADDR (HOST_QUEUE_OFFSET_ADDR + 8) 181 /* table offset for queue: 182 * 4 Queues * 2 byte offset = 8 bytes 183 */ 184 #define HOST_QUEUE_OFFSET_ADDR (HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR + 8) 185 /* table offset for Host queue descriptors: 186 * 1 ports * 4 Queues * 2 byte offset = 8 bytes 187 */ 188 #define HOST_QUEUE_DESCRIPTOR_OFFSET_ADDR (HOST_Q4_RX_CONTEXT_OFFSET + 8) 189 190 /* Host Port Rx Context */ 191 #define HOST_Q4_RX_CONTEXT_OFFSET (HOST_Q3_RX_CONTEXT_OFFSET + 8) 192 #define HOST_Q3_RX_CONTEXT_OFFSET (HOST_Q2_RX_CONTEXT_OFFSET + 8) 193 #define HOST_Q2_RX_CONTEXT_OFFSET (HOST_Q1_RX_CONTEXT_OFFSET + 8) 194 #define HOST_Q1_RX_CONTEXT_OFFSET (EMAC_PROMISCUOUS_MODE_OFFSET + 4) 195 196 /* Promiscuous mode control */ 197 #define EMAC_P1_PROMISCUOUS_BIT BIT(0) 198 #define EMAC_P2_PROMISCUOUS_BIT BIT(1) 199 #define EMAC_PROMISCUOUS_MODE_OFFSET (EMAC_RESERVED + 4) 200 #define EMAC_RESERVED EOF_48K_BUFFER_BD 201 202 /* allow for max 48k buffer which spans the descriptors up to 0x1800 6kB */ 203 #define EOF_48K_BUFFER_BD (P0_BUFFER_DESC_OFFSET + HOST_BD_SIZE + \ 204 PORT_BD_SIZE) 205 206 #define HOST_BD_SIZE ((HOST_QUEUE_1_SIZE + \ 207 HOST_QUEUE_2_SIZE + HOST_QUEUE_3_SIZE + \ 208 HOST_QUEUE_4_SIZE) * BD_SIZE) 209 #define PORT_BD_SIZE ((QUEUE_1_SIZE + QUEUE_2_SIZE + \ 210 QUEUE_3_SIZE + QUEUE_4_SIZE) * 2 * BD_SIZE) 211 212 #define END_OF_BD_POOL (P2_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE) 213 #define P2_Q4_BD_OFFSET (P2_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE) 214 #define P2_Q3_BD_OFFSET (P2_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE) 215 #define P2_Q2_BD_OFFSET (P2_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE) 216 #define P2_Q1_BD_OFFSET (P1_Q4_BD_OFFSET + QUEUE_4_SIZE * BD_SIZE) 217 #define P1_Q4_BD_OFFSET (P1_Q3_BD_OFFSET + QUEUE_3_SIZE * BD_SIZE) 218 #define P1_Q3_BD_OFFSET (P1_Q2_BD_OFFSET + QUEUE_2_SIZE * BD_SIZE) 219 #define P1_Q2_BD_OFFSET (P1_Q1_BD_OFFSET + QUEUE_1_SIZE * BD_SIZE) 220 #define P1_Q1_BD_OFFSET (P0_Q4_BD_OFFSET + HOST_QUEUE_4_SIZE * BD_SIZE) 221 #define P0_Q4_BD_OFFSET (P0_Q3_BD_OFFSET + HOST_QUEUE_3_SIZE * BD_SIZE) 222 #define P0_Q3_BD_OFFSET (P0_Q2_BD_OFFSET + HOST_QUEUE_2_SIZE * BD_SIZE) 223 #define P0_Q2_BD_OFFSET (P0_Q1_BD_OFFSET + HOST_QUEUE_1_SIZE * BD_SIZE) 224 #define P0_Q1_BD_OFFSET P0_BUFFER_DESC_OFFSET 225 #define P0_BUFFER_DESC_OFFSET SRAM_START_OFFSET 226 227 /* Memory Usage of L3 OCMC RAM */ 228 229 /* L3 64KB Memory - mainly buffer Pool */ 230 #define END_OF_BUFFER_POOL (P2_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \ 231 ICSS_BLOCK_SIZE) 232 #define P2_Q4_BUFFER_OFFSET (P2_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \ 233 ICSS_BLOCK_SIZE) 234 #define P2_Q3_BUFFER_OFFSET (P2_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \ 235 ICSS_BLOCK_SIZE) 236 #define P2_Q2_BUFFER_OFFSET (P2_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \ 237 ICSS_BLOCK_SIZE) 238 #define P2_Q1_BUFFER_OFFSET (P1_Q4_BUFFER_OFFSET + QUEUE_4_SIZE * \ 239 ICSS_BLOCK_SIZE) 240 #define P1_Q4_BUFFER_OFFSET (P1_Q3_BUFFER_OFFSET + QUEUE_3_SIZE * \ 241 ICSS_BLOCK_SIZE) 242 #define P1_Q3_BUFFER_OFFSET (P1_Q2_BUFFER_OFFSET + QUEUE_2_SIZE * \ 243 ICSS_BLOCK_SIZE) 244 #define P1_Q2_BUFFER_OFFSET (P1_Q1_BUFFER_OFFSET + QUEUE_1_SIZE * \ 245 ICSS_BLOCK_SIZE) 246 #define P1_Q1_BUFFER_OFFSET (P0_Q4_BUFFER_OFFSET + HOST_QUEUE_4_SIZE * \ 247 ICSS_BLOCK_SIZE) 248 #define P0_Q4_BUFFER_OFFSET (P0_Q3_BUFFER_OFFSET + HOST_QUEUE_3_SIZE * \ 249 ICSS_BLOCK_SIZE) 250 #define P0_Q3_BUFFER_OFFSET (P0_Q2_BUFFER_OFFSET + HOST_QUEUE_2_SIZE * \ 251 ICSS_BLOCK_SIZE) 252 #define P0_Q2_BUFFER_OFFSET (P0_Q1_BUFFER_OFFSET + HOST_QUEUE_1_SIZE * \ 253 ICSS_BLOCK_SIZE) 254 #define P0_COL_BUFFER_OFFSET 0xEE00 255 #define P0_Q1_BUFFER_OFFSET 0x0000 256 257 #endif /* __ICSS_SWITCH_H */ 258