1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com 4 */ 5 #ifndef PRUETH_PTP_H 6 #define PRUETH_PTP_H 7 8 #define RX_SYNC_TIMESTAMP_OFFSET_P1 0x8 /* 8 bytes */ 9 #define RX_PDELAY_REQ_TIMESTAMP_OFFSET_P1 0x14 /* 12 bytes */ 10 11 #define DISABLE_PTP_FRAME_FORWARDING_CTRL_OFFSET 0x14 /* 1 byte */ 12 13 #define RX_PDELAY_RESP_TIMESTAMP_OFFSET_P1 0x20 /* 12 bytes */ 14 #define RX_SYNC_TIMESTAMP_OFFSET_P2 0x2c /* 12 bytes */ 15 #define RX_PDELAY_REQ_TIMESTAMP_OFFSET_P2 0x38 /* 12 bytes */ 16 #define RX_PDELAY_RESP_TIMESTAMP_OFFSET_P2 0x44 /* 12 bytes */ 17 #define TIMESYNC_DOMAIN_NUMBER_LIST 0x50 /* 2 bytes */ 18 #define P1_SMA_LINE_DELAY_OFFSET 0x52 /* 4 bytes */ 19 #define P2_SMA_LINE_DELAY_OFFSET 0x56 /* 4 bytes */ 20 #define TIMESYNC_SECONDS_COUNT_OFFSET 0x5a /* 6 bytes */ 21 #define TIMESYNC_TC_RCF_OFFSET 0x60 /* 4 bytes */ 22 #define DUT_IS_MASTER_OFFSET 0x64 /* 1 byte */ 23 #define MASTER_PORT_NUM_OFFSET 0x65 /* 1 byte */ 24 #define SYNC_MASTER_MAC_OFFSET 0x66 /* 6 bytes */ 25 #define TX_TS_NOTIFICATION_OFFSET_SYNC_P1 0x6c /* 1 byte */ 26 #define TX_TS_NOTIFICATION_OFFSET_PDEL_REQ_P1 0x6d /* 1 byte */ 27 #define TX_TS_NOTIFICATION_OFFSET_PDEL_RES_P1 0x6e /* 1 byte */ 28 #define TX_TS_NOTIFICATION_OFFSET_SYNC_P2 0x6f /* 1 byte */ 29 #define TX_TS_NOTIFICATION_OFFSET_PDEL_REQ_P2 0x70 /* 1 byte */ 30 #define TX_TS_NOTIFICATION_OFFSET_PDEL_RES_P2 0x71 /* 1 byte */ 31 #define TX_SYNC_TIMESTAMP_OFFSET_P1 0x72 /* 12 bytes */ 32 #define TX_PDELAY_REQ_TIMESTAMP_OFFSET_P1 0x7e /* 12 bytes */ 33 #define TX_PDELAY_RESP_TIMESTAMP_OFFSET_P1 0x8a /* 12 bytes */ 34 #define TX_SYNC_TIMESTAMP_OFFSET_P2 0x96 /* 12 bytes */ 35 #define TX_PDELAY_REQ_TIMESTAMP_OFFSET_P2 0xa2 /* 12 bytes */ 36 #define TX_PDELAY_RESP_TIMESTAMP_OFFSET_P2 0xae /* 12 bytes */ 37 #define TIMESYNC_CTRL_VAR_OFFSET 0xba /* 1 byte */ 38 #define DISABLE_SWITCH_SYNC_RELAY_OFFSET 0xbb /* 1 byte */ 39 #define MII_RX_CORRECTION_OFFSET 0xbc /* 2 bytes */ 40 #define MII_TX_CORRECTION_OFFSET 0xbe /* 2 bytes */ 41 #define TIMESYNC_CMP1_CMP_OFFSET 0xc0 /* 8 bytes */ 42 #define TIMESYNC_SYNC0_CMP_OFFSET 0xc8 /* 8 bytes */ 43 #define TIMESYNC_CMP1_PERIOD_OFFSET 0xd0 /* 4 bytes */ 44 #define TIMESYNC_SYNC0_WIDTH_OFFSET 0xd4 /* 4 bytes */ 45 #define SINGLE_STEP_IEP_OFFSET_P1 0xd8 /* 8 bytes */ 46 #define SINGLE_STEP_SECONDS_OFFSET_P1 0xe0 /* 8 bytes */ 47 #define SINGLE_STEP_IEP_OFFSET_P2 0xe8 /* 8 bytes */ 48 #define SINGLE_STEP_SECONDS_OFFSET_P2 0xf0 /* 8 bytes */ 49 #define LINK_LOCAL_FRAME_HAS_HSR_TAG 0xf8 /* 1 bytes */ 50 #define PTP_PREV_TX_TIMESTAMP_P1 0xf9 /* 8 bytes */ 51 #define PTP_PREV_TX_TIMESTAMP_P2 0x101 /* 8 bytes */ 52 #define PTP_CLK_IDENTITY_OFFSET 0x109 /* 8 bytes */ 53 #define PTP_SCRATCH_MEM 0x111 /* 16 byte */ 54 #define PTP_IPV4_UDP_E2E_ENABLE 0x121 /* 1 byte */ 55 56 enum { 57 PRUETH_PTP_SYNC, 58 PRUETH_PTP_DLY_REQ, 59 PRUETH_PTP_DLY_RESP, 60 PRUETH_PTP_TS_EVENTS, 61 }; 62 63 #define PRUETH_PTP_TS_SIZE 12 64 #define PRUETH_PTP_TS_NOTIFY_SIZE 1 65 #define PRUETH_PTP_TS_NOTIFY_MASK 0xff 66 67 /* Bit definitions for TIMESYNC_CTRL */ 68 #define TIMESYNC_CTRL_BG_ENABLE BIT(0) 69 #define TIMESYNC_CTRL_FORCED_2STEP BIT(1) 70 71 static inline u32 icssm_prueth_tx_ts_offs_get(u8 port, u8 event) 72 { 73 return TX_SYNC_TIMESTAMP_OFFSET_P1 + port * 74 PRUETH_PTP_TS_EVENTS * PRUETH_PTP_TS_SIZE + 75 event * PRUETH_PTP_TS_SIZE; 76 } 77 78 static inline u32 icssm_prueth_tx_ts_notify_offs_get(u8 port, u8 event) 79 { 80 return TX_TS_NOTIFICATION_OFFSET_SYNC_P1 + 81 PRUETH_PTP_TS_EVENTS * PRUETH_PTP_TS_NOTIFY_SIZE * port + 82 event * PRUETH_PTP_TS_NOTIFY_SIZE; 83 } 84 85 #endif /* PRUETH_PTP_H */ 86