1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Texas Instruments ICSSG Ethernet Driver 4 * 5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 * 7 */ 8 9 #include <linux/bitops.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dma/ti-cppi5.h> 14 #include <linux/etherdevice.h> 15 #include <linux/genalloc.h> 16 #include <linux/if_vlan.h> 17 #include <linux/interrupt.h> 18 #include <linux/kernel.h> 19 #include <linux/mfd/syscon.h> 20 #include <linux/module.h> 21 #include <linux/of.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/platform_device.h> 25 #include <linux/phy.h> 26 #include <linux/property.h> 27 #include <linux/remoteproc/pruss.h> 28 #include <linux/regmap.h> 29 #include <linux/remoteproc.h> 30 31 #include "icssg_prueth.h" 32 #include "icssg_mii_rt.h" 33 #include "../k3-cppi-desc-pool.h" 34 35 #define PRUETH_MODULE_DESCRIPTION "PRUSS ICSSG Ethernet driver" 36 37 /* CTRLMMR_ICSSG_RGMII_CTRL register bits */ 38 #define ICSSG_CTRL_RGMII_ID_MODE BIT(24) 39 40 static int emac_get_tx_ts(struct prueth_emac *emac, 41 struct emac_tx_ts_response *rsp) 42 { 43 struct prueth *prueth = emac->prueth; 44 int slice = prueth_emac_slice(emac); 45 int addr; 46 47 addr = icssg_queue_pop(prueth, slice == 0 ? 48 ICSSG_TS_POP_SLICE0 : ICSSG_TS_POP_SLICE1); 49 if (addr < 0) 50 return addr; 51 52 memcpy_fromio(rsp, prueth->shram.va + addr, sizeof(*rsp)); 53 /* return buffer back for to pool */ 54 icssg_queue_push(prueth, slice == 0 ? 55 ICSSG_TS_PUSH_SLICE0 : ICSSG_TS_PUSH_SLICE1, addr); 56 57 return 0; 58 } 59 60 static void tx_ts_work(struct prueth_emac *emac) 61 { 62 struct skb_shared_hwtstamps ssh; 63 struct emac_tx_ts_response tsr; 64 struct sk_buff *skb; 65 int ret = 0; 66 u32 hi_sw; 67 u64 ns; 68 69 /* There may be more than one pending requests */ 70 while (1) { 71 ret = emac_get_tx_ts(emac, &tsr); 72 if (ret) /* nothing more */ 73 break; 74 75 if (tsr.cookie >= PRUETH_MAX_TX_TS_REQUESTS || 76 !emac->tx_ts_skb[tsr.cookie]) { 77 netdev_err(emac->ndev, "Invalid TX TS cookie 0x%x\n", 78 tsr.cookie); 79 break; 80 } 81 82 skb = emac->tx_ts_skb[tsr.cookie]; 83 emac->tx_ts_skb[tsr.cookie] = NULL; /* free slot */ 84 if (!skb) { 85 netdev_err(emac->ndev, "Driver Bug! got NULL skb\n"); 86 break; 87 } 88 89 hi_sw = readl(emac->prueth->shram.va + 90 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 91 ns = icssg_ts_to_ns(hi_sw, tsr.hi_ts, tsr.lo_ts, 92 IEP_DEFAULT_CYCLE_TIME_NS); 93 94 memset(&ssh, 0, sizeof(ssh)); 95 ssh.hwtstamp = ns_to_ktime(ns); 96 97 skb_tstamp_tx(skb, &ssh); 98 dev_consume_skb_any(skb); 99 100 if (atomic_dec_and_test(&emac->tx_ts_pending)) /* no more? */ 101 break; 102 } 103 } 104 105 static irqreturn_t prueth_tx_ts_irq(int irq, void *dev_id) 106 { 107 struct prueth_emac *emac = dev_id; 108 109 /* currently only TX timestamp is being returned */ 110 tx_ts_work(emac); 111 112 return IRQ_HANDLED; 113 } 114 115 static struct icssg_firmwares icssg_emac_firmwares[] = { 116 { 117 .pru = "ti-pruss/am65x-sr2-pru0-prueth-fw.elf", 118 .rtu = "ti-pruss/am65x-sr2-rtu0-prueth-fw.elf", 119 .txpru = "ti-pruss/am65x-sr2-txpru0-prueth-fw.elf", 120 }, 121 { 122 .pru = "ti-pruss/am65x-sr2-pru1-prueth-fw.elf", 123 .rtu = "ti-pruss/am65x-sr2-rtu1-prueth-fw.elf", 124 .txpru = "ti-pruss/am65x-sr2-txpru1-prueth-fw.elf", 125 } 126 }; 127 128 static int prueth_emac_start(struct prueth *prueth, struct prueth_emac *emac) 129 { 130 struct icssg_firmwares *firmwares; 131 struct device *dev = prueth->dev; 132 int slice, ret; 133 134 firmwares = icssg_emac_firmwares; 135 136 slice = prueth_emac_slice(emac); 137 if (slice < 0) { 138 netdev_err(emac->ndev, "invalid port\n"); 139 return -EINVAL; 140 } 141 142 ret = icssg_config(prueth, emac, slice); 143 if (ret) 144 return ret; 145 146 ret = rproc_set_firmware(prueth->pru[slice], firmwares[slice].pru); 147 ret = rproc_boot(prueth->pru[slice]); 148 if (ret) { 149 dev_err(dev, "failed to boot PRU%d: %d\n", slice, ret); 150 return -EINVAL; 151 } 152 153 ret = rproc_set_firmware(prueth->rtu[slice], firmwares[slice].rtu); 154 ret = rproc_boot(prueth->rtu[slice]); 155 if (ret) { 156 dev_err(dev, "failed to boot RTU%d: %d\n", slice, ret); 157 goto halt_pru; 158 } 159 160 ret = rproc_set_firmware(prueth->txpru[slice], firmwares[slice].txpru); 161 ret = rproc_boot(prueth->txpru[slice]); 162 if (ret) { 163 dev_err(dev, "failed to boot TX_PRU%d: %d\n", slice, ret); 164 goto halt_rtu; 165 } 166 167 emac->fw_running = 1; 168 return 0; 169 170 halt_rtu: 171 rproc_shutdown(prueth->rtu[slice]); 172 173 halt_pru: 174 rproc_shutdown(prueth->pru[slice]); 175 176 return ret; 177 } 178 179 /* called back by PHY layer if there is change in link state of hw port*/ 180 static void emac_adjust_link(struct net_device *ndev) 181 { 182 struct prueth_emac *emac = netdev_priv(ndev); 183 struct phy_device *phydev = ndev->phydev; 184 struct prueth *prueth = emac->prueth; 185 bool new_state = false; 186 unsigned long flags; 187 188 if (phydev->link) { 189 /* check the mode of operation - full/half duplex */ 190 if (phydev->duplex != emac->duplex) { 191 new_state = true; 192 emac->duplex = phydev->duplex; 193 } 194 if (phydev->speed != emac->speed) { 195 new_state = true; 196 emac->speed = phydev->speed; 197 } 198 if (!emac->link) { 199 new_state = true; 200 emac->link = 1; 201 } 202 } else if (emac->link) { 203 new_state = true; 204 emac->link = 0; 205 206 /* f/w should support 100 & 1000 */ 207 emac->speed = SPEED_1000; 208 209 /* half duplex may not be supported by f/w */ 210 emac->duplex = DUPLEX_FULL; 211 } 212 213 if (new_state) { 214 phy_print_status(phydev); 215 216 /* update RGMII and MII configuration based on PHY negotiated 217 * values 218 */ 219 if (emac->link) { 220 if (emac->duplex == DUPLEX_HALF) 221 icssg_config_half_duplex(emac); 222 /* Set the RGMII cfg for gig en and full duplex */ 223 icssg_update_rgmii_cfg(prueth->miig_rt, emac); 224 225 /* update the Tx IPG based on 100M/1G speed */ 226 spin_lock_irqsave(&emac->lock, flags); 227 icssg_config_ipg(emac); 228 spin_unlock_irqrestore(&emac->lock, flags); 229 icssg_config_set_speed(emac); 230 emac_set_port_state(emac, ICSSG_EMAC_PORT_FORWARD); 231 232 } else { 233 emac_set_port_state(emac, ICSSG_EMAC_PORT_DISABLE); 234 } 235 } 236 237 if (emac->link) { 238 /* reactivate the transmit queue */ 239 netif_tx_wake_all_queues(ndev); 240 } else { 241 netif_tx_stop_all_queues(ndev); 242 prueth_cleanup_tx_ts(emac); 243 } 244 } 245 246 static int emac_phy_connect(struct prueth_emac *emac) 247 { 248 struct prueth *prueth = emac->prueth; 249 struct net_device *ndev = emac->ndev; 250 /* connect PHY */ 251 ndev->phydev = of_phy_connect(emac->ndev, emac->phy_node, 252 &emac_adjust_link, 0, 253 emac->phy_if); 254 if (!ndev->phydev) { 255 dev_err(prueth->dev, "couldn't connect to phy %s\n", 256 emac->phy_node->full_name); 257 return -ENODEV; 258 } 259 260 if (!emac->half_duplex) { 261 dev_dbg(prueth->dev, "half duplex mode is not supported\n"); 262 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_10baseT_Half_BIT); 263 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_100baseT_Half_BIT); 264 } 265 266 /* remove unsupported modes */ 267 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_1000baseT_Half_BIT); 268 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Pause_BIT); 269 phy_remove_link_mode(ndev->phydev, ETHTOOL_LINK_MODE_Asym_Pause_BIT); 270 271 if (emac->phy_if == PHY_INTERFACE_MODE_MII) 272 phy_set_max_speed(ndev->phydev, SPEED_100); 273 274 return 0; 275 } 276 277 static u64 prueth_iep_gettime(void *clockops_data, struct ptp_system_timestamp *sts) 278 { 279 u32 hi_rollover_count, hi_rollover_count_r; 280 struct prueth_emac *emac = clockops_data; 281 struct prueth *prueth = emac->prueth; 282 void __iomem *fw_hi_r_count_addr; 283 void __iomem *fw_count_hi_addr; 284 u32 iepcount_hi, iepcount_hi_r; 285 unsigned long flags; 286 u32 iepcount_lo; 287 u64 ts = 0; 288 289 fw_count_hi_addr = prueth->shram.va + TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET; 290 fw_hi_r_count_addr = prueth->shram.va + TIMESYNC_FW_WC_HI_ROLLOVER_COUNT_OFFSET; 291 292 local_irq_save(flags); 293 do { 294 iepcount_hi = icss_iep_get_count_hi(emac->iep); 295 iepcount_hi += readl(fw_count_hi_addr); 296 hi_rollover_count = readl(fw_hi_r_count_addr); 297 ptp_read_system_prets(sts); 298 iepcount_lo = icss_iep_get_count_low(emac->iep); 299 ptp_read_system_postts(sts); 300 301 iepcount_hi_r = icss_iep_get_count_hi(emac->iep); 302 iepcount_hi_r += readl(fw_count_hi_addr); 303 hi_rollover_count_r = readl(fw_hi_r_count_addr); 304 } while ((iepcount_hi_r != iepcount_hi) || 305 (hi_rollover_count != hi_rollover_count_r)); 306 local_irq_restore(flags); 307 308 ts = ((u64)hi_rollover_count) << 23 | iepcount_hi; 309 ts = ts * (u64)IEP_DEFAULT_CYCLE_TIME_NS + iepcount_lo; 310 311 return ts; 312 } 313 314 static void prueth_iep_settime(void *clockops_data, u64 ns) 315 { 316 struct icssg_setclock_desc __iomem *sc_descp; 317 struct prueth_emac *emac = clockops_data; 318 struct icssg_setclock_desc sc_desc; 319 u64 cyclecount; 320 u32 cycletime; 321 int timeout; 322 323 if (!emac->fw_running) 324 return; 325 326 sc_descp = emac->prueth->shram.va + TIMESYNC_FW_WC_SETCLOCK_DESC_OFFSET; 327 328 cycletime = IEP_DEFAULT_CYCLE_TIME_NS; 329 cyclecount = ns / cycletime; 330 331 memset(&sc_desc, 0, sizeof(sc_desc)); 332 sc_desc.margin = cycletime - 1000; 333 sc_desc.cyclecounter0_set = cyclecount & GENMASK(31, 0); 334 sc_desc.cyclecounter1_set = (cyclecount & GENMASK(63, 32)) >> 32; 335 sc_desc.iepcount_set = ns % cycletime; 336 sc_desc.CMP0_current = cycletime - 4; //Count from 0 to (cycle time)-4 337 338 memcpy_toio(sc_descp, &sc_desc, sizeof(sc_desc)); 339 340 writeb(1, &sc_descp->request); 341 342 timeout = 5; /* fw should take 2-3 ms */ 343 while (timeout--) { 344 if (readb(&sc_descp->acknowledgment)) 345 return; 346 347 usleep_range(500, 1000); 348 } 349 350 dev_err(emac->prueth->dev, "settime timeout\n"); 351 } 352 353 static int prueth_perout_enable(void *clockops_data, 354 struct ptp_perout_request *req, int on, 355 u64 *cmp) 356 { 357 struct prueth_emac *emac = clockops_data; 358 u32 reduction_factor = 0, offset = 0; 359 struct timespec64 ts; 360 u64 ns_period; 361 362 if (!on) 363 return 0; 364 365 /* Any firmware specific stuff for PPS/PEROUT handling */ 366 ts.tv_sec = req->period.sec; 367 ts.tv_nsec = req->period.nsec; 368 ns_period = timespec64_to_ns(&ts); 369 370 /* f/w doesn't support period less than cycle time */ 371 if (ns_period < IEP_DEFAULT_CYCLE_TIME_NS) 372 return -ENXIO; 373 374 reduction_factor = ns_period / IEP_DEFAULT_CYCLE_TIME_NS; 375 offset = ns_period % IEP_DEFAULT_CYCLE_TIME_NS; 376 377 /* f/w requires at least 1uS within a cycle so CMP 378 * can trigger after SYNC is enabled 379 */ 380 if (offset < 5 * NSEC_PER_USEC) 381 offset = 5 * NSEC_PER_USEC; 382 383 /* if offset is close to cycle time then we will miss 384 * the CMP event for last tick when IEP rolls over. 385 * In normal mode, IEP tick is 4ns. 386 * In slow compensation it could be 0ns or 8ns at 387 * every slow compensation cycle. 388 */ 389 if (offset > IEP_DEFAULT_CYCLE_TIME_NS - 8) 390 offset = IEP_DEFAULT_CYCLE_TIME_NS - 8; 391 392 /* we're in shadow mode so need to set upper 32-bits */ 393 *cmp = (u64)offset << 32; 394 395 writel(reduction_factor, emac->prueth->shram.va + 396 TIMESYNC_FW_WC_SYNCOUT_REDUCTION_FACTOR_OFFSET); 397 398 writel(0, emac->prueth->shram.va + 399 TIMESYNC_FW_WC_SYNCOUT_START_TIME_CYCLECOUNT_OFFSET); 400 401 return 0; 402 } 403 404 const struct icss_iep_clockops prueth_iep_clockops = { 405 .settime = prueth_iep_settime, 406 .gettime = prueth_iep_gettime, 407 .perout_enable = prueth_perout_enable, 408 }; 409 410 /** 411 * emac_ndo_open - EMAC device open 412 * @ndev: network adapter device 413 * 414 * Called when system wants to start the interface. 415 * 416 * Return: 0 for a successful open, or appropriate error code 417 */ 418 static int emac_ndo_open(struct net_device *ndev) 419 { 420 struct prueth_emac *emac = netdev_priv(ndev); 421 int ret, i, num_data_chn = emac->tx_ch_num; 422 struct prueth *prueth = emac->prueth; 423 int slice = prueth_emac_slice(emac); 424 struct device *dev = prueth->dev; 425 int max_rx_flows; 426 int rx_flow; 427 428 /* clear SMEM and MSMC settings for all slices */ 429 if (!prueth->emacs_initialized) { 430 memset_io(prueth->msmcram.va, 0, prueth->msmcram.size); 431 memset_io(prueth->shram.va, 0, ICSSG_CONFIG_OFFSET_SLICE1 * PRUETH_NUM_MACS); 432 } 433 434 /* set h/w MAC as user might have re-configured */ 435 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 436 437 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 438 icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); 439 440 icssg_class_default(prueth->miig_rt, slice, 0, false); 441 442 /* Notify the stack of the actual queue counts. */ 443 ret = netif_set_real_num_tx_queues(ndev, num_data_chn); 444 if (ret) { 445 dev_err(dev, "cannot set real number of tx queues\n"); 446 return ret; 447 } 448 449 init_completion(&emac->cmd_complete); 450 ret = prueth_init_tx_chns(emac); 451 if (ret) { 452 dev_err(dev, "failed to init tx channel: %d\n", ret); 453 return ret; 454 } 455 456 max_rx_flows = PRUETH_MAX_RX_FLOWS; 457 ret = prueth_init_rx_chns(emac, &emac->rx_chns, "rx", 458 max_rx_flows, PRUETH_MAX_RX_DESC); 459 if (ret) { 460 dev_err(dev, "failed to init rx channel: %d\n", ret); 461 goto cleanup_tx; 462 } 463 464 ret = prueth_ndev_add_tx_napi(emac); 465 if (ret) 466 goto cleanup_rx; 467 468 /* we use only the highest priority flow for now i.e. @irq[3] */ 469 rx_flow = PRUETH_RX_FLOW_DATA; 470 ret = request_irq(emac->rx_chns.irq[rx_flow], prueth_rx_irq, 471 IRQF_TRIGGER_HIGH, dev_name(dev), emac); 472 if (ret) { 473 dev_err(dev, "unable to request RX IRQ\n"); 474 goto cleanup_napi; 475 } 476 477 /* reset and start PRU firmware */ 478 ret = prueth_emac_start(prueth, emac); 479 if (ret) 480 goto free_rx_irq; 481 482 icssg_mii_update_mtu(prueth->mii_rt, slice, ndev->max_mtu); 483 484 if (!prueth->emacs_initialized) { 485 ret = icss_iep_init(emac->iep, &prueth_iep_clockops, 486 emac, IEP_DEFAULT_CYCLE_TIME_NS); 487 } 488 489 ret = request_threaded_irq(emac->tx_ts_irq, NULL, prueth_tx_ts_irq, 490 IRQF_ONESHOT, dev_name(dev), emac); 491 if (ret) 492 goto stop; 493 494 /* Prepare RX */ 495 ret = prueth_prepare_rx_chan(emac, &emac->rx_chns, PRUETH_MAX_PKT_SIZE); 496 if (ret) 497 goto free_tx_ts_irq; 498 499 ret = k3_udma_glue_enable_rx_chn(emac->rx_chns.rx_chn); 500 if (ret) 501 goto reset_rx_chn; 502 503 for (i = 0; i < emac->tx_ch_num; i++) { 504 ret = k3_udma_glue_enable_tx_chn(emac->tx_chns[i].tx_chn); 505 if (ret) 506 goto reset_tx_chan; 507 } 508 509 /* Enable NAPI in Tx and Rx direction */ 510 for (i = 0; i < emac->tx_ch_num; i++) 511 napi_enable(&emac->tx_chns[i].napi_tx); 512 napi_enable(&emac->napi_rx); 513 514 /* start PHY */ 515 phy_start(ndev->phydev); 516 517 prueth->emacs_initialized++; 518 519 queue_work(system_long_wq, &emac->stats_work.work); 520 521 return 0; 522 523 reset_tx_chan: 524 /* Since interface is not yet up, there is wouldn't be 525 * any SKB for completion. So set false to free_skb 526 */ 527 prueth_reset_tx_chan(emac, i, false); 528 reset_rx_chn: 529 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, false); 530 free_tx_ts_irq: 531 free_irq(emac->tx_ts_irq, emac); 532 stop: 533 prueth_emac_stop(emac); 534 free_rx_irq: 535 free_irq(emac->rx_chns.irq[rx_flow], emac); 536 cleanup_napi: 537 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 538 cleanup_rx: 539 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 540 cleanup_tx: 541 prueth_cleanup_tx_chns(emac); 542 543 return ret; 544 } 545 546 /** 547 * emac_ndo_stop - EMAC device stop 548 * @ndev: network adapter device 549 * 550 * Called when system wants to stop or down the interface. 551 * 552 * Return: Always 0 (Success) 553 */ 554 static int emac_ndo_stop(struct net_device *ndev) 555 { 556 struct prueth_emac *emac = netdev_priv(ndev); 557 struct prueth *prueth = emac->prueth; 558 int rx_flow = PRUETH_RX_FLOW_DATA; 559 int max_rx_flows; 560 int ret, i; 561 562 /* inform the upper layers. */ 563 netif_tx_stop_all_queues(ndev); 564 565 /* block packets from wire */ 566 if (ndev->phydev) 567 phy_stop(ndev->phydev); 568 569 icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac)); 570 571 atomic_set(&emac->tdown_cnt, emac->tx_ch_num); 572 /* ensure new tdown_cnt value is visible */ 573 smp_mb__after_atomic(); 574 /* tear down and disable UDMA channels */ 575 reinit_completion(&emac->tdown_complete); 576 for (i = 0; i < emac->tx_ch_num; i++) 577 k3_udma_glue_tdown_tx_chn(emac->tx_chns[i].tx_chn, false); 578 579 ret = wait_for_completion_timeout(&emac->tdown_complete, 580 msecs_to_jiffies(1000)); 581 if (!ret) 582 netdev_err(ndev, "tx teardown timeout\n"); 583 584 prueth_reset_tx_chan(emac, emac->tx_ch_num, true); 585 for (i = 0; i < emac->tx_ch_num; i++) 586 napi_disable(&emac->tx_chns[i].napi_tx); 587 588 max_rx_flows = PRUETH_MAX_RX_FLOWS; 589 k3_udma_glue_tdown_rx_chn(emac->rx_chns.rx_chn, true); 590 591 prueth_reset_rx_chan(&emac->rx_chns, max_rx_flows, true); 592 593 napi_disable(&emac->napi_rx); 594 595 cancel_work_sync(&emac->rx_mode_work); 596 597 /* Destroying the queued work in ndo_stop() */ 598 cancel_delayed_work_sync(&emac->stats_work); 599 600 if (prueth->emacs_initialized == 1) 601 icss_iep_exit(emac->iep); 602 603 /* stop PRUs */ 604 prueth_emac_stop(emac); 605 606 free_irq(emac->tx_ts_irq, emac); 607 608 free_irq(emac->rx_chns.irq[rx_flow], emac); 609 prueth_ndev_del_tx_napi(emac, emac->tx_ch_num); 610 611 prueth_cleanup_rx_chns(emac, &emac->rx_chns, max_rx_flows); 612 prueth_cleanup_tx_chns(emac); 613 614 prueth->emacs_initialized--; 615 616 return 0; 617 } 618 619 static void emac_ndo_set_rx_mode_work(struct work_struct *work) 620 { 621 struct prueth_emac *emac = container_of(work, struct prueth_emac, rx_mode_work); 622 struct net_device *ndev = emac->ndev; 623 bool promisc, allmulti; 624 625 if (!netif_running(ndev)) 626 return; 627 628 promisc = ndev->flags & IFF_PROMISC; 629 allmulti = ndev->flags & IFF_ALLMULTI; 630 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_DISABLE); 631 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_DISABLE); 632 633 if (promisc) { 634 emac_set_port_state(emac, ICSSG_EMAC_PORT_UC_FLOODING_ENABLE); 635 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 636 return; 637 } 638 639 if (allmulti) { 640 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 641 return; 642 } 643 644 if (!netdev_mc_empty(ndev)) { 645 emac_set_port_state(emac, ICSSG_EMAC_PORT_MC_FLOODING_ENABLE); 646 return; 647 } 648 } 649 650 /** 651 * emac_ndo_set_rx_mode - EMAC set receive mode function 652 * @ndev: The EMAC network adapter 653 * 654 * Called when system wants to set the receive mode of the device. 655 * 656 */ 657 static void emac_ndo_set_rx_mode(struct net_device *ndev) 658 { 659 struct prueth_emac *emac = netdev_priv(ndev); 660 661 queue_work(emac->cmd_wq, &emac->rx_mode_work); 662 } 663 664 static const struct net_device_ops emac_netdev_ops = { 665 .ndo_open = emac_ndo_open, 666 .ndo_stop = emac_ndo_stop, 667 .ndo_start_xmit = emac_ndo_start_xmit, 668 .ndo_set_mac_address = eth_mac_addr, 669 .ndo_validate_addr = eth_validate_addr, 670 .ndo_tx_timeout = emac_ndo_tx_timeout, 671 .ndo_set_rx_mode = emac_ndo_set_rx_mode, 672 .ndo_eth_ioctl = emac_ndo_ioctl, 673 .ndo_get_stats64 = emac_ndo_get_stats64, 674 .ndo_get_phys_port_name = emac_ndo_get_phys_port_name, 675 }; 676 677 static int prueth_netdev_init(struct prueth *prueth, 678 struct device_node *eth_node) 679 { 680 int ret, num_tx_chn = PRUETH_MAX_TX_QUEUES; 681 struct prueth_emac *emac; 682 struct net_device *ndev; 683 enum prueth_port port; 684 const char *irq_name; 685 enum prueth_mac mac; 686 687 port = prueth_node_port(eth_node); 688 if (port == PRUETH_PORT_INVALID) 689 return -EINVAL; 690 691 mac = prueth_node_mac(eth_node); 692 if (mac == PRUETH_MAC_INVALID) 693 return -EINVAL; 694 695 ndev = alloc_etherdev_mq(sizeof(*emac), num_tx_chn); 696 if (!ndev) 697 return -ENOMEM; 698 699 emac = netdev_priv(ndev); 700 emac->prueth = prueth; 701 emac->ndev = ndev; 702 emac->port_id = port; 703 emac->cmd_wq = create_singlethread_workqueue("icssg_cmd_wq"); 704 if (!emac->cmd_wq) { 705 ret = -ENOMEM; 706 goto free_ndev; 707 } 708 INIT_WORK(&emac->rx_mode_work, emac_ndo_set_rx_mode_work); 709 710 INIT_DELAYED_WORK(&emac->stats_work, emac_stats_work_handler); 711 712 ret = pruss_request_mem_region(prueth->pruss, 713 port == PRUETH_PORT_MII0 ? 714 PRUSS_MEM_DRAM0 : PRUSS_MEM_DRAM1, 715 &emac->dram); 716 if (ret) { 717 dev_err(prueth->dev, "unable to get DRAM: %d\n", ret); 718 ret = -ENOMEM; 719 goto free_wq; 720 } 721 722 emac->tx_ch_num = 1; 723 724 irq_name = "tx_ts0"; 725 if (emac->port_id == PRUETH_PORT_MII1) 726 irq_name = "tx_ts1"; 727 emac->tx_ts_irq = platform_get_irq_byname_optional(prueth->pdev, irq_name); 728 if (emac->tx_ts_irq < 0) { 729 ret = dev_err_probe(prueth->dev, emac->tx_ts_irq, "could not get tx_ts_irq\n"); 730 goto free; 731 } 732 733 SET_NETDEV_DEV(ndev, prueth->dev); 734 spin_lock_init(&emac->lock); 735 mutex_init(&emac->cmd_lock); 736 737 emac->phy_node = of_parse_phandle(eth_node, "phy-handle", 0); 738 if (!emac->phy_node && !of_phy_is_fixed_link(eth_node)) { 739 dev_err(prueth->dev, "couldn't find phy-handle\n"); 740 ret = -ENODEV; 741 goto free; 742 } else if (of_phy_is_fixed_link(eth_node)) { 743 ret = of_phy_register_fixed_link(eth_node); 744 if (ret) { 745 ret = dev_err_probe(prueth->dev, ret, 746 "failed to register fixed-link phy\n"); 747 goto free; 748 } 749 750 emac->phy_node = eth_node; 751 } 752 753 ret = of_get_phy_mode(eth_node, &emac->phy_if); 754 if (ret) { 755 dev_err(prueth->dev, "could not get phy-mode property\n"); 756 goto free; 757 } 758 759 if (emac->phy_if != PHY_INTERFACE_MODE_MII && 760 !phy_interface_mode_is_rgmii(emac->phy_if)) { 761 dev_err(prueth->dev, "PHY mode unsupported %s\n", phy_modes(emac->phy_if)); 762 ret = -EINVAL; 763 goto free; 764 } 765 766 /* AM65 SR2.0 has TX Internal delay always enabled by hardware 767 * and it is not possible to disable TX Internal delay. The below 768 * switch case block describes how we handle different phy modes 769 * based on hardware restriction. 770 */ 771 switch (emac->phy_if) { 772 case PHY_INTERFACE_MODE_RGMII_ID: 773 emac->phy_if = PHY_INTERFACE_MODE_RGMII_RXID; 774 break; 775 case PHY_INTERFACE_MODE_RGMII_TXID: 776 emac->phy_if = PHY_INTERFACE_MODE_RGMII; 777 break; 778 case PHY_INTERFACE_MODE_RGMII: 779 case PHY_INTERFACE_MODE_RGMII_RXID: 780 dev_err(prueth->dev, "RGMII mode without TX delay is not supported"); 781 ret = -EINVAL; 782 goto free; 783 default: 784 break; 785 } 786 787 /* get mac address from DT and set private and netdev addr */ 788 ret = of_get_ethdev_address(eth_node, ndev); 789 if (!is_valid_ether_addr(ndev->dev_addr)) { 790 eth_hw_addr_random(ndev); 791 dev_warn(prueth->dev, "port %d: using random MAC addr: %pM\n", 792 port, ndev->dev_addr); 793 } 794 ether_addr_copy(emac->mac_addr, ndev->dev_addr); 795 796 ndev->min_mtu = PRUETH_MIN_PKT_SIZE; 797 ndev->max_mtu = PRUETH_MAX_MTU; 798 ndev->netdev_ops = &emac_netdev_ops; 799 ndev->ethtool_ops = &icssg_ethtool_ops; 800 ndev->hw_features = NETIF_F_SG; 801 ndev->features = ndev->hw_features; 802 803 netif_napi_add(ndev, &emac->napi_rx, emac_napi_rx_poll); 804 prueth->emac[mac] = emac; 805 806 return 0; 807 808 free: 809 pruss_release_mem_region(prueth->pruss, &emac->dram); 810 free_wq: 811 destroy_workqueue(emac->cmd_wq); 812 free_ndev: 813 emac->ndev = NULL; 814 prueth->emac[mac] = NULL; 815 free_netdev(ndev); 816 817 return ret; 818 } 819 820 static int prueth_probe(struct platform_device *pdev) 821 { 822 struct device_node *eth_node, *eth_ports_node; 823 struct device_node *eth0_node = NULL; 824 struct device_node *eth1_node = NULL; 825 struct genpool_data_align gp_data = { 826 .align = SZ_64K, 827 }; 828 struct device *dev = &pdev->dev; 829 struct device_node *np; 830 struct prueth *prueth; 831 struct pruss *pruss; 832 u32 msmc_ram_size; 833 int i, ret; 834 835 np = dev->of_node; 836 837 prueth = devm_kzalloc(dev, sizeof(*prueth), GFP_KERNEL); 838 if (!prueth) 839 return -ENOMEM; 840 841 dev_set_drvdata(dev, prueth); 842 prueth->pdev = pdev; 843 prueth->pdata = *(const struct prueth_pdata *)device_get_match_data(dev); 844 845 prueth->dev = dev; 846 eth_ports_node = of_get_child_by_name(np, "ethernet-ports"); 847 if (!eth_ports_node) 848 return -ENOENT; 849 850 for_each_child_of_node(eth_ports_node, eth_node) { 851 u32 reg; 852 853 if (strcmp(eth_node->name, "port")) 854 continue; 855 ret = of_property_read_u32(eth_node, "reg", ®); 856 if (ret < 0) { 857 dev_err(dev, "%pOF error reading port_id %d\n", 858 eth_node, ret); 859 } 860 861 of_node_get(eth_node); 862 863 if (reg == 0) { 864 eth0_node = eth_node; 865 if (!of_device_is_available(eth0_node)) { 866 of_node_put(eth0_node); 867 eth0_node = NULL; 868 } 869 } else if (reg == 1) { 870 eth1_node = eth_node; 871 if (!of_device_is_available(eth1_node)) { 872 of_node_put(eth1_node); 873 eth1_node = NULL; 874 } 875 } else { 876 dev_err(dev, "port reg should be 0 or 1\n"); 877 } 878 } 879 880 of_node_put(eth_ports_node); 881 882 /* At least one node must be present and available else we fail */ 883 if (!eth0_node && !eth1_node) { 884 dev_err(dev, "neither port0 nor port1 node available\n"); 885 return -ENODEV; 886 } 887 888 if (eth0_node == eth1_node) { 889 dev_err(dev, "port0 and port1 can't have same reg\n"); 890 of_node_put(eth0_node); 891 return -ENODEV; 892 } 893 894 prueth->eth_node[PRUETH_MAC0] = eth0_node; 895 prueth->eth_node[PRUETH_MAC1] = eth1_node; 896 897 prueth->miig_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-g-rt"); 898 if (IS_ERR(prueth->miig_rt)) { 899 dev_err(dev, "couldn't get ti,mii-g-rt syscon regmap\n"); 900 return -ENODEV; 901 } 902 903 prueth->mii_rt = syscon_regmap_lookup_by_phandle(np, "ti,mii-rt"); 904 if (IS_ERR(prueth->mii_rt)) { 905 dev_err(dev, "couldn't get ti,mii-rt syscon regmap\n"); 906 return -ENODEV; 907 } 908 909 if (eth0_node) { 910 ret = prueth_get_cores(prueth, ICSS_SLICE0, false); 911 if (ret) 912 goto put_cores; 913 } 914 915 if (eth1_node) { 916 ret = prueth_get_cores(prueth, ICSS_SLICE1, false); 917 if (ret) 918 goto put_cores; 919 } 920 921 pruss = pruss_get(eth0_node ? 922 prueth->pru[ICSS_SLICE0] : prueth->pru[ICSS_SLICE1]); 923 if (IS_ERR(pruss)) { 924 ret = PTR_ERR(pruss); 925 dev_err(dev, "unable to get pruss handle\n"); 926 goto put_cores; 927 } 928 929 prueth->pruss = pruss; 930 931 ret = pruss_request_mem_region(pruss, PRUSS_MEM_SHRD_RAM2, 932 &prueth->shram); 933 if (ret) { 934 dev_err(dev, "unable to get PRUSS SHRD RAM2: %d\n", ret); 935 goto put_pruss; 936 } 937 938 prueth->sram_pool = of_gen_pool_get(np, "sram", 0); 939 if (!prueth->sram_pool) { 940 dev_err(dev, "unable to get SRAM pool\n"); 941 ret = -ENODEV; 942 943 goto put_mem; 944 } 945 946 msmc_ram_size = MSMC_RAM_SIZE; 947 948 /* NOTE: FW bug needs buffer base to be 64KB aligned */ 949 prueth->msmcram.va = 950 (void __iomem *)gen_pool_alloc_algo(prueth->sram_pool, 951 msmc_ram_size, 952 gen_pool_first_fit_align, 953 &gp_data); 954 955 if (!prueth->msmcram.va) { 956 ret = -ENOMEM; 957 dev_err(dev, "unable to allocate MSMC resource\n"); 958 goto put_mem; 959 } 960 prueth->msmcram.pa = gen_pool_virt_to_phys(prueth->sram_pool, 961 (unsigned long)prueth->msmcram.va); 962 prueth->msmcram.size = msmc_ram_size; 963 memset_io(prueth->msmcram.va, 0, msmc_ram_size); 964 dev_dbg(dev, "sram: pa %llx va %p size %zx\n", prueth->msmcram.pa, 965 prueth->msmcram.va, prueth->msmcram.size); 966 967 prueth->iep0 = icss_iep_get_idx(np, 0); 968 if (IS_ERR(prueth->iep0)) { 969 ret = dev_err_probe(dev, PTR_ERR(prueth->iep0), "iep0 get failed\n"); 970 prueth->iep0 = NULL; 971 goto free_pool; 972 } 973 974 prueth->iep1 = icss_iep_get_idx(np, 1); 975 if (IS_ERR(prueth->iep1)) { 976 ret = dev_err_probe(dev, PTR_ERR(prueth->iep1), "iep1 get failed\n"); 977 goto put_iep0; 978 } 979 980 if (prueth->pdata.quirk_10m_link_issue) { 981 /* Enable IEP1 for FW in 64bit mode as W/A for 10M FD link detect issue under TX 982 * traffic. 983 */ 984 icss_iep_init_fw(prueth->iep1); 985 } 986 987 /* setup netdev interfaces */ 988 if (eth0_node) { 989 ret = prueth_netdev_init(prueth, eth0_node); 990 if (ret) { 991 dev_err_probe(dev, ret, "netdev init %s failed\n", 992 eth0_node->name); 993 goto exit_iep; 994 } 995 996 if (of_find_property(eth0_node, "ti,half-duplex-capable", NULL)) 997 prueth->emac[PRUETH_MAC0]->half_duplex = 1; 998 999 prueth->emac[PRUETH_MAC0]->iep = prueth->iep0; 1000 } 1001 1002 if (eth1_node) { 1003 ret = prueth_netdev_init(prueth, eth1_node); 1004 if (ret) { 1005 dev_err_probe(dev, ret, "netdev init %s failed\n", 1006 eth1_node->name); 1007 goto netdev_exit; 1008 } 1009 1010 if (of_find_property(eth1_node, "ti,half-duplex-capable", NULL)) 1011 prueth->emac[PRUETH_MAC1]->half_duplex = 1; 1012 1013 prueth->emac[PRUETH_MAC1]->iep = prueth->iep0; 1014 } 1015 1016 /* register the network devices */ 1017 if (eth0_node) { 1018 ret = register_netdev(prueth->emac[PRUETH_MAC0]->ndev); 1019 if (ret) { 1020 dev_err(dev, "can't register netdev for port MII0"); 1021 goto netdev_exit; 1022 } 1023 1024 prueth->registered_netdevs[PRUETH_MAC0] = prueth->emac[PRUETH_MAC0]->ndev; 1025 1026 emac_phy_connect(prueth->emac[PRUETH_MAC0]); 1027 phy_attached_info(prueth->emac[PRUETH_MAC0]->ndev->phydev); 1028 } 1029 1030 if (eth1_node) { 1031 ret = register_netdev(prueth->emac[PRUETH_MAC1]->ndev); 1032 if (ret) { 1033 dev_err(dev, "can't register netdev for port MII1"); 1034 goto netdev_unregister; 1035 } 1036 1037 prueth->registered_netdevs[PRUETH_MAC1] = prueth->emac[PRUETH_MAC1]->ndev; 1038 emac_phy_connect(prueth->emac[PRUETH_MAC1]); 1039 phy_attached_info(prueth->emac[PRUETH_MAC1]->ndev->phydev); 1040 } 1041 1042 dev_info(dev, "TI PRU ethernet driver initialized: %s EMAC mode\n", 1043 (!eth0_node || !eth1_node) ? "single" : "dual"); 1044 1045 if (eth1_node) 1046 of_node_put(eth1_node); 1047 if (eth0_node) 1048 of_node_put(eth0_node); 1049 return 0; 1050 1051 netdev_unregister: 1052 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1053 if (!prueth->registered_netdevs[i]) 1054 continue; 1055 if (prueth->emac[i]->ndev->phydev) { 1056 phy_disconnect(prueth->emac[i]->ndev->phydev); 1057 prueth->emac[i]->ndev->phydev = NULL; 1058 } 1059 unregister_netdev(prueth->registered_netdevs[i]); 1060 } 1061 1062 netdev_exit: 1063 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1064 eth_node = prueth->eth_node[i]; 1065 if (!eth_node) 1066 continue; 1067 1068 prueth_netdev_exit(prueth, eth_node); 1069 } 1070 1071 exit_iep: 1072 if (prueth->pdata.quirk_10m_link_issue) 1073 icss_iep_exit_fw(prueth->iep1); 1074 icss_iep_put(prueth->iep1); 1075 1076 put_iep0: 1077 icss_iep_put(prueth->iep0); 1078 prueth->iep0 = NULL; 1079 prueth->iep1 = NULL; 1080 1081 free_pool: 1082 gen_pool_free(prueth->sram_pool, 1083 (unsigned long)prueth->msmcram.va, msmc_ram_size); 1084 1085 put_mem: 1086 pruss_release_mem_region(prueth->pruss, &prueth->shram); 1087 1088 put_pruss: 1089 pruss_put(prueth->pruss); 1090 1091 put_cores: 1092 if (eth1_node) { 1093 prueth_put_cores(prueth, ICSS_SLICE1); 1094 of_node_put(eth1_node); 1095 } 1096 1097 if (eth0_node) { 1098 prueth_put_cores(prueth, ICSS_SLICE0); 1099 of_node_put(eth0_node); 1100 } 1101 1102 return ret; 1103 } 1104 1105 static void prueth_remove(struct platform_device *pdev) 1106 { 1107 struct prueth *prueth = platform_get_drvdata(pdev); 1108 struct device_node *eth_node; 1109 int i; 1110 1111 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1112 if (!prueth->registered_netdevs[i]) 1113 continue; 1114 phy_stop(prueth->emac[i]->ndev->phydev); 1115 phy_disconnect(prueth->emac[i]->ndev->phydev); 1116 prueth->emac[i]->ndev->phydev = NULL; 1117 unregister_netdev(prueth->registered_netdevs[i]); 1118 } 1119 1120 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1121 eth_node = prueth->eth_node[i]; 1122 if (!eth_node) 1123 continue; 1124 1125 prueth_netdev_exit(prueth, eth_node); 1126 } 1127 1128 if (prueth->pdata.quirk_10m_link_issue) 1129 icss_iep_exit_fw(prueth->iep1); 1130 1131 icss_iep_put(prueth->iep1); 1132 icss_iep_put(prueth->iep0); 1133 1134 gen_pool_free(prueth->sram_pool, 1135 (unsigned long)prueth->msmcram.va, 1136 MSMC_RAM_SIZE); 1137 1138 pruss_release_mem_region(prueth->pruss, &prueth->shram); 1139 1140 pruss_put(prueth->pruss); 1141 1142 if (prueth->eth_node[PRUETH_MAC1]) 1143 prueth_put_cores(prueth, ICSS_SLICE1); 1144 1145 if (prueth->eth_node[PRUETH_MAC0]) 1146 prueth_put_cores(prueth, ICSS_SLICE0); 1147 } 1148 1149 static const struct prueth_pdata am654_icssg_pdata = { 1150 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 1151 .quirk_10m_link_issue = 1, 1152 }; 1153 1154 static const struct prueth_pdata am64x_icssg_pdata = { 1155 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 1156 }; 1157 1158 static const struct of_device_id prueth_dt_match[] = { 1159 { .compatible = "ti,am654-icssg-prueth", .data = &am654_icssg_pdata }, 1160 { .compatible = "ti,am642-icssg-prueth", .data = &am64x_icssg_pdata }, 1161 { /* sentinel */ } 1162 }; 1163 MODULE_DEVICE_TABLE(of, prueth_dt_match); 1164 1165 static struct platform_driver prueth_driver = { 1166 .probe = prueth_probe, 1167 .remove_new = prueth_remove, 1168 .driver = { 1169 .name = "icssg-prueth", 1170 .of_match_table = prueth_dt_match, 1171 .pm = &prueth_dev_pm_ops, 1172 }, 1173 }; 1174 module_platform_driver(prueth_driver); 1175 1176 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); 1177 MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>"); 1178 MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver"); 1179 MODULE_LICENSE("GPL"); 1180