1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_CONFIG_H 9 #define __NET_TI_ICSSG_CONFIG_H 10 11 struct icssg_buffer_pool_cfg { 12 __le32 addr; 13 __le32 len; 14 } __packed; 15 16 struct icssg_flow_cfg { 17 __le16 rx_base_flow; 18 __le16 mgm_base_flow; 19 } __packed; 20 21 #define PRUETH_PKT_TYPE_CMD 0x10 22 #define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */ 23 #define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */ 24 #define PRUETH_MAX_TX_DESC 512 25 #define PRUETH_MAX_RX_DESC 512 26 #define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */ 27 #define PRUETH_RX_FLOW_DATA 0 28 29 #define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K 30 #define PRUETH_EMAC_POOLS_PER_SLICE 24 31 #define PRUETH_EMAC_BUF_POOL_START 8 32 #define PRUETH_NUM_BUF_POOLS 8 33 #define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */ 34 #define MSMC_RAM_SIZE \ 35 (2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \ 36 PRUETH_EMAC_RX_CTX_BUF_SIZE * 2)) 37 38 #define PRUETH_SW_BUF_POOL_SIZE_HOST SZ_4K 39 #define PRUETH_SW_NUM_BUF_POOLS_HOST 8 40 #define PRUETH_SW_NUM_BUF_POOLS_PER_PRU 4 41 #define MSMC_RAM_SIZE_SWITCH_MODE \ 42 (MSMC_RAM_SIZE + \ 43 (2 * PRUETH_SW_BUF_POOL_SIZE_HOST * PRUETH_SW_NUM_BUF_POOLS_HOST)) 44 45 #define PRUETH_SWITCH_FDB_MASK ((SIZE_OF_FDB / NUMBER_OF_FDB_BUCKET_ENTRIES) - 1) 46 47 struct icssg_rxq_ctx { 48 __le32 start[3]; 49 __le32 end; 50 } __packed; 51 52 /* Load time Fiwmware Configuration */ 53 54 #define ICSSG_FW_MGMT_CMD_HEADER 0x81 55 #define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 56 #define ICSSG_FW_MGMT_CMD_TYPE 0x04 57 #define ICSSG_FW_MGMT_PKT 0x80000000 58 59 struct icssg_r30_cmd { 60 u32 cmd[4]; 61 } __packed; 62 63 enum icssg_port_state_cmd { 64 ICSSG_EMAC_PORT_DISABLE = 0, 65 ICSSG_EMAC_PORT_BLOCK, 66 ICSSG_EMAC_PORT_FORWARD, 67 ICSSG_EMAC_PORT_FORWARD_WO_LEARNING, 68 ICSSG_EMAC_PORT_ACCEPT_ALL, 69 ICSSG_EMAC_PORT_ACCEPT_TAGGED, 70 ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO, 71 ICSSG_EMAC_PORT_TAS_TRIGGER, 72 ICSSG_EMAC_PORT_TAS_ENABLE, 73 ICSSG_EMAC_PORT_TAS_RESET, 74 ICSSG_EMAC_PORT_TAS_DISABLE, 75 ICSSG_EMAC_PORT_UC_FLOODING_ENABLE, 76 ICSSG_EMAC_PORT_UC_FLOODING_DISABLE, 77 ICSSG_EMAC_PORT_MC_FLOODING_ENABLE, 78 ICSSG_EMAC_PORT_MC_FLOODING_DISABLE, 79 ICSSG_EMAC_PORT_PREMPT_TX_ENABLE, 80 ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, 81 ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE, 82 ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE, 83 ICSSG_EMAC_PORT_MAX_COMMANDS 84 }; 85 86 #define EMAC_NONE 0xffff0000 87 #define EMAC_PRU0_P_DI 0xffff0004 88 #define EMAC_PRU1_P_DI 0xffff0040 89 #define EMAC_TX_P_DI 0xffff0100 90 91 #define EMAC_PRU0_P_EN 0xfffb0000 92 #define EMAC_PRU1_P_EN 0xffbf0000 93 #define EMAC_TX_P_EN 0xfeff0000 94 95 #define EMAC_P_BLOCK 0xffff0040 96 #define EMAC_TX_P_BLOCK 0xffff0200 97 #define EMAC_P_UNBLOCK 0xffbf0000 98 #define EMAC_TX_P_UNBLOCK 0xfdff0000 99 #define EMAC_LEAN_EN 0xfff70000 100 #define EMAC_LEAN_DI 0xffff0008 101 102 #define EMAC_ACCEPT_ALL 0xffff0001 103 #define EMAC_ACCEPT_TAG 0xfffe0002 104 #define EMAC_ACCEPT_PRIOR 0xfffc0000 105 106 /* Config area lies in DRAM */ 107 #define ICSSG_CONFIG_OFFSET 0x0 108 109 /* Config area lies in shared RAM */ 110 #define ICSSG_CONFIG_OFFSET_SLICE0 0 111 #define ICSSG_CONFIG_OFFSET_SLICE1 0x8000 112 113 #define ICSSG_NUM_NORMAL_PDS 64 114 #define ICSSG_NUM_SPECIAL_PDS 16 115 116 #define ICSSG_NORMAL_PD_SIZE 8 117 #define ICSSG_SPECIAL_PD_SIZE 20 118 119 #define ICSSG_FLAG_MASK 0xff00ffff 120 121 /* SR1.0-specific bits */ 122 #define PRUETH_MAX_RX_FLOWS_SR1 4 /* excluding default flow */ 123 #define PRUETH_RX_FLOW_DATA_SR1 3 /* highest priority flow */ 124 #define PRUETH_MAX_RX_MGM_DESC_SR1 8 125 #define PRUETH_MAX_RX_MGM_FLOWS_SR1 2 /* excluding default flow */ 126 #define PRUETH_RX_MGM_FLOW_RESPONSE_SR1 0 127 #define PRUETH_RX_MGM_FLOW_TIMESTAMP_SR1 1 128 129 #define PRUETH_NUM_BUF_POOLS_SR1 16 130 #define PRUETH_EMAC_BUF_POOL_START_SR1 8 131 #define PRUETH_EMAC_BUF_POOL_MIN_SIZE_SR1 128 132 #define PRUETH_EMAC_BUF_SIZE_SR1 1536 133 #define PRUETH_EMAC_NUM_BUF_SR1 4 134 #define PRUETH_EMAC_BUF_POOL_SIZE_SR1 (PRUETH_EMAC_NUM_BUF_SR1 * \ 135 PRUETH_EMAC_BUF_SIZE_SR1) 136 #define MSMC_RAM_SIZE_SR1 (SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */ 137 138 struct icssg_sr1_config { 139 __le32 status; /* Firmware status */ 140 __le32 addr_lo; /* MSMC Buffer pool base address low. */ 141 __le32 addr_hi; /* MSMC Buffer pool base address high. Must be 0 */ 142 __le32 tx_buf_sz[16]; /* Array of buffer pool sizes */ 143 __le32 num_tx_threads; /* Number of active egress threads, 1 to 4 */ 144 __le32 tx_rate_lim_en; /* Bitmask: Egress rate limit en per thread */ 145 __le32 rx_flow_id; /* RX flow id for first rx ring */ 146 __le32 rx_mgr_flow_id; /* RX flow id for the first management ring */ 147 __le32 flags; /* TBD */ 148 __le32 n_burst; /* for debug */ 149 __le32 rtu_status; /* RTU status */ 150 __le32 info; /* reserved */ 151 __le32 reserve; 152 __le32 rand_seed; /* Used for the random number generation at fw */ 153 } __packed; 154 155 /* SR1.0 shutdown command to stop processing at firmware. 156 * Command format: 0x8101ss00, where 157 * - ss: sequence number. Currently not used by driver. 158 */ 159 #define ICSSG_SHUTDOWN_CMD_SR1 0x81010000 160 161 /* SR1.0 pstate speed/duplex command to set speed and duplex settings 162 * in firmware. 163 * Command format: 0x8102ssPN, where 164 * - ss: sequence number. Currently not used by driver. 165 * - P: port number (for switch mode). 166 * - N: Speed/Duplex state: 167 * 0x0 - 10Mbps/Half duplex; 168 * 0x8 - 10Mbps/Full duplex; 169 * 0x2 - 100Mbps/Half duplex; 170 * 0xa - 100Mbps/Full duplex; 171 * 0xc - 1Gbps/Full duplex; 172 * NOTE: The above are the same value as bits [3..1](slice 0) 173 * or bits [7..5](slice 1) of RGMII CFG register. 174 */ 175 #define ICSSG_PSTATE_SPEED_DUPLEX_CMD_SR1 0x81020000 176 177 struct icssg_setclock_desc { 178 u8 request; 179 u8 restore; 180 u8 acknowledgment; 181 u8 cmp_status; 182 u32 margin; 183 u32 cyclecounter0_set; 184 u32 cyclecounter1_set; 185 u32 iepcount_set; 186 u32 rsvd1; 187 u32 rsvd2; 188 u32 CMP0_current; 189 u32 iepcount_current; 190 u32 difference; 191 u32 cyclecounter0_new; 192 u32 cyclecounter1_new; 193 u32 CMP0_new; 194 } __packed; 195 196 #define ICSSG_CMD_POP_SLICE0 56 197 #define ICSSG_CMD_POP_SLICE1 60 198 199 #define ICSSG_CMD_PUSH_SLICE0 57 200 #define ICSSG_CMD_PUSH_SLICE1 61 201 202 #define ICSSG_RSP_POP_SLICE0 58 203 #define ICSSG_RSP_POP_SLICE1 62 204 205 #define ICSSG_RSP_PUSH_SLICE0 56 206 #define ICSSG_RSP_PUSH_SLICE1 60 207 208 #define ICSSG_TS_POP_SLICE0 59 209 #define ICSSG_TS_POP_SLICE1 63 210 211 #define ICSSG_TS_PUSH_SLICE0 40 212 #define ICSSG_TS_PUSH_SLICE1 41 213 214 struct mgmt_cmd { 215 u8 param; 216 u8 seqnum; 217 u8 type; 218 u8 header; 219 u32 cmd_args[3]; 220 }; 221 222 struct mgmt_cmd_rsp { 223 u32 reserved; 224 u8 status; 225 u8 seqnum; 226 u8 type; 227 u8 header; 228 u32 cmd_args[3]; 229 }; 230 231 /* FDB FID_C2 flag definitions */ 232 /* Indicates host port membership.*/ 233 #define ICSSG_FDB_ENTRY_P0_MEMBERSHIP BIT(0) 234 /* Indicates that MAC ID is connected to physical port 1 */ 235 #define ICSSG_FDB_ENTRY_P1_MEMBERSHIP BIT(1) 236 /* Indicates that MAC ID is connected to physical port 2 */ 237 #define ICSSG_FDB_ENTRY_P2_MEMBERSHIP BIT(2) 238 /* Ageable bit is set for learned entries and cleared for static entries */ 239 #define ICSSG_FDB_ENTRY_AGEABLE BIT(3) 240 /* If set for DA then packet is determined to be a special packet */ 241 #define ICSSG_FDB_ENTRY_BLOCK BIT(4) 242 /* If set for DA then the SA from the packet is not learned */ 243 #define ICSSG_FDB_ENTRY_SECURE BIT(5) 244 /* If set, it means packet has been seen recently with source address + FID 245 * matching MAC address/FID of entry 246 */ 247 #define ICSSG_FDB_ENTRY_TOUCHED BIT(6) 248 /* Set if entry is valid */ 249 #define ICSSG_FDB_ENTRY_VALID BIT(7) 250 251 /** 252 * struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM 253 * @fid_c1: membership and forwarding rules flag to this table. See 254 * above to defines for bit definitions 255 * @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID) 256 */ 257 struct prueth_vlan_tbl { 258 u8 fid_c1; 259 u8 fid; 260 } __packed; 261 262 /** 263 * struct prueth_fdb_slot - Result of FDB slot lookup 264 * @mac: MAC address 265 * @fid: fid to be associated with MAC 266 * @fid_c2: FID_C2 entry for this MAC 267 */ 268 struct prueth_fdb_slot { 269 u8 mac[ETH_ALEN]; 270 u8 fid; 271 u8 fid_c2; 272 } __packed; 273 274 enum icssg_ietfpe_verify_states { 275 ICSSG_IETFPE_STATE_UNKNOWN = 0, 276 ICSSG_IETFPE_STATE_INITIAL, 277 ICSSG_IETFPE_STATE_VERIFYING, 278 ICSSG_IETFPE_STATE_SUCCEEDED, 279 ICSSG_IETFPE_STATE_FAILED, 280 ICSSG_IETFPE_STATE_DISABLED 281 }; 282 #endif /* __NET_TI_ICSSG_CONFIG_H */ 283