1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_CONFIG_H 9 #define __NET_TI_ICSSG_CONFIG_H 10 11 struct icssg_buffer_pool_cfg { 12 __le32 addr; 13 __le32 len; 14 } __packed; 15 16 struct icssg_flow_cfg { 17 __le16 rx_base_flow; 18 __le16 mgm_base_flow; 19 } __packed; 20 21 #define PRUETH_PKT_TYPE_CMD 0x10 22 #define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */ 23 #define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */ 24 #define PRUETH_MAX_TX_DESC 512 25 #define PRUETH_MAX_RX_DESC 512 26 #define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */ 27 #define PRUETH_RX_FLOW_DATA 0 28 29 #define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K 30 #define PRUETH_EMAC_POOLS_PER_SLICE 24 31 #define PRUETH_EMAC_BUF_POOL_START 8 32 #define PRUETH_NUM_BUF_POOLS 8 33 #define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */ 34 #define MSMC_RAM_SIZE \ 35 (2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \ 36 PRUETH_EMAC_RX_CTX_BUF_SIZE * 2)) 37 38 struct icssg_rxq_ctx { 39 __le32 start[3]; 40 __le32 end; 41 } __packed; 42 43 /* Load time Fiwmware Configuration */ 44 45 #define ICSSG_FW_MGMT_CMD_HEADER 0x81 46 #define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 47 #define ICSSG_FW_MGMT_CMD_TYPE 0x04 48 #define ICSSG_FW_MGMT_PKT 0x80000000 49 50 struct icssg_r30_cmd { 51 u32 cmd[4]; 52 } __packed; 53 54 enum icssg_port_state_cmd { 55 ICSSG_EMAC_PORT_DISABLE = 0, 56 ICSSG_EMAC_PORT_BLOCK, 57 ICSSG_EMAC_PORT_FORWARD, 58 ICSSG_EMAC_PORT_FORWARD_WO_LEARNING, 59 ICSSG_EMAC_PORT_ACCEPT_ALL, 60 ICSSG_EMAC_PORT_ACCEPT_TAGGED, 61 ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO, 62 ICSSG_EMAC_PORT_TAS_TRIGGER, 63 ICSSG_EMAC_PORT_TAS_ENABLE, 64 ICSSG_EMAC_PORT_TAS_RESET, 65 ICSSG_EMAC_PORT_TAS_DISABLE, 66 ICSSG_EMAC_PORT_UC_FLOODING_ENABLE, 67 ICSSG_EMAC_PORT_UC_FLOODING_DISABLE, 68 ICSSG_EMAC_PORT_MC_FLOODING_ENABLE, 69 ICSSG_EMAC_PORT_MC_FLOODING_DISABLE, 70 ICSSG_EMAC_PORT_PREMPT_TX_ENABLE, 71 ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, 72 ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE, 73 ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE, 74 ICSSG_EMAC_PORT_MAX_COMMANDS 75 }; 76 77 #define EMAC_NONE 0xffff0000 78 #define EMAC_PRU0_P_DI 0xffff0004 79 #define EMAC_PRU1_P_DI 0xffff0040 80 #define EMAC_TX_P_DI 0xffff0100 81 82 #define EMAC_PRU0_P_EN 0xfffb0000 83 #define EMAC_PRU1_P_EN 0xffbf0000 84 #define EMAC_TX_P_EN 0xfeff0000 85 86 #define EMAC_P_BLOCK 0xffff0040 87 #define EMAC_TX_P_BLOCK 0xffff0200 88 #define EMAC_P_UNBLOCK 0xffbf0000 89 #define EMAC_TX_P_UNBLOCK 0xfdff0000 90 #define EMAC_LEAN_EN 0xfff70000 91 #define EMAC_LEAN_DI 0xffff0008 92 93 #define EMAC_ACCEPT_ALL 0xffff0001 94 #define EMAC_ACCEPT_TAG 0xfffe0002 95 #define EMAC_ACCEPT_PRIOR 0xfffc0000 96 97 /* Config area lies in DRAM */ 98 #define ICSSG_CONFIG_OFFSET 0x0 99 100 /* Config area lies in shared RAM */ 101 #define ICSSG_CONFIG_OFFSET_SLICE0 0 102 #define ICSSG_CONFIG_OFFSET_SLICE1 0x8000 103 104 #define ICSSG_NUM_NORMAL_PDS 64 105 #define ICSSG_NUM_SPECIAL_PDS 16 106 107 #define ICSSG_NORMAL_PD_SIZE 8 108 #define ICSSG_SPECIAL_PD_SIZE 20 109 110 #define ICSSG_FLAG_MASK 0xff00ffff 111 112 /* SR1.0-specific bits */ 113 #define PRUETH_MAX_RX_FLOWS_SR1 4 /* excluding default flow */ 114 #define PRUETH_RX_FLOW_DATA_SR1 3 /* highest priority flow */ 115 #define PRUETH_MAX_RX_MGM_DESC_SR1 8 116 #define PRUETH_MAX_RX_MGM_FLOWS_SR1 2 /* excluding default flow */ 117 #define PRUETH_RX_MGM_FLOW_RESPONSE_SR1 0 118 #define PRUETH_RX_MGM_FLOW_TIMESTAMP_SR1 1 119 120 #define PRUETH_NUM_BUF_POOLS_SR1 16 121 #define PRUETH_EMAC_BUF_POOL_START_SR1 8 122 #define PRUETH_EMAC_BUF_POOL_MIN_SIZE_SR1 128 123 #define PRUETH_EMAC_BUF_SIZE_SR1 1536 124 #define PRUETH_EMAC_NUM_BUF_SR1 4 125 #define PRUETH_EMAC_BUF_POOL_SIZE_SR1 (PRUETH_EMAC_NUM_BUF_SR1 * \ 126 PRUETH_EMAC_BUF_SIZE_SR1) 127 #define MSMC_RAM_SIZE_SR1 (SZ_64K + SZ_32K + SZ_2K) /* 0x1880 x 8 x 2 */ 128 129 struct icssg_sr1_config { 130 __le32 status; /* Firmware status */ 131 __le32 addr_lo; /* MSMC Buffer pool base address low. */ 132 __le32 addr_hi; /* MSMC Buffer pool base address high. Must be 0 */ 133 __le32 tx_buf_sz[16]; /* Array of buffer pool sizes */ 134 __le32 num_tx_threads; /* Number of active egress threads, 1 to 4 */ 135 __le32 tx_rate_lim_en; /* Bitmask: Egress rate limit en per thread */ 136 __le32 rx_flow_id; /* RX flow id for first rx ring */ 137 __le32 rx_mgr_flow_id; /* RX flow id for the first management ring */ 138 __le32 flags; /* TBD */ 139 __le32 n_burst; /* for debug */ 140 __le32 rtu_status; /* RTU status */ 141 __le32 info; /* reserved */ 142 __le32 reserve; 143 __le32 rand_seed; /* Used for the random number generation at fw */ 144 } __packed; 145 146 /* SR1.0 shutdown command to stop processing at firmware. 147 * Command format: 0x8101ss00, where 148 * - ss: sequence number. Currently not used by driver. 149 */ 150 #define ICSSG_SHUTDOWN_CMD_SR1 0x81010000 151 152 /* SR1.0 pstate speed/duplex command to set speed and duplex settings 153 * in firmware. 154 * Command format: 0x8102ssPN, where 155 * - ss: sequence number. Currently not used by driver. 156 * - P: port number (for switch mode). 157 * - N: Speed/Duplex state: 158 * 0x0 - 10Mbps/Half duplex; 159 * 0x8 - 10Mbps/Full duplex; 160 * 0x2 - 100Mbps/Half duplex; 161 * 0xa - 100Mbps/Full duplex; 162 * 0xc - 1Gbps/Full duplex; 163 * NOTE: The above are the same value as bits [3..1](slice 0) 164 * or bits [7..5](slice 1) of RGMII CFG register. 165 */ 166 #define ICSSG_PSTATE_SPEED_DUPLEX_CMD_SR1 0x81020000 167 168 struct icssg_setclock_desc { 169 u8 request; 170 u8 restore; 171 u8 acknowledgment; 172 u8 cmp_status; 173 u32 margin; 174 u32 cyclecounter0_set; 175 u32 cyclecounter1_set; 176 u32 iepcount_set; 177 u32 rsvd1; 178 u32 rsvd2; 179 u32 CMP0_current; 180 u32 iepcount_current; 181 u32 difference; 182 u32 cyclecounter0_new; 183 u32 cyclecounter1_new; 184 u32 CMP0_new; 185 } __packed; 186 187 #define ICSSG_CMD_POP_SLICE0 56 188 #define ICSSG_CMD_POP_SLICE1 60 189 190 #define ICSSG_CMD_PUSH_SLICE0 57 191 #define ICSSG_CMD_PUSH_SLICE1 61 192 193 #define ICSSG_RSP_POP_SLICE0 58 194 #define ICSSG_RSP_POP_SLICE1 62 195 196 #define ICSSG_RSP_PUSH_SLICE0 56 197 #define ICSSG_RSP_PUSH_SLICE1 60 198 199 #define ICSSG_TS_POP_SLICE0 59 200 #define ICSSG_TS_POP_SLICE1 63 201 202 #define ICSSG_TS_PUSH_SLICE0 40 203 #define ICSSG_TS_PUSH_SLICE1 41 204 205 /* FDB FID_C2 flag definitions */ 206 /* Indicates host port membership.*/ 207 #define ICSSG_FDB_ENTRY_P0_MEMBERSHIP BIT(0) 208 /* Indicates that MAC ID is connected to physical port 1 */ 209 #define ICSSG_FDB_ENTRY_P1_MEMBERSHIP BIT(1) 210 /* Indicates that MAC ID is connected to physical port 2 */ 211 #define ICSSG_FDB_ENTRY_P2_MEMBERSHIP BIT(2) 212 /* Ageable bit is set for learned entries and cleared for static entries */ 213 #define ICSSG_FDB_ENTRY_AGEABLE BIT(3) 214 /* If set for DA then packet is determined to be a special packet */ 215 #define ICSSG_FDB_ENTRY_BLOCK BIT(4) 216 /* If set for DA then the SA from the packet is not learned */ 217 #define ICSSG_FDB_ENTRY_SECURE BIT(5) 218 /* If set, it means packet has been seen recently with source address + FID 219 * matching MAC address/FID of entry 220 */ 221 #define ICSSG_FDB_ENTRY_TOUCHED BIT(6) 222 /* Set if entry is valid */ 223 #define ICSSG_FDB_ENTRY_VALID BIT(7) 224 225 /** 226 * struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM 227 * @fid_c1: membership and forwarding rules flag to this table. See 228 * above to defines for bit definitions 229 * @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID) 230 */ 231 struct prueth_vlan_tbl { 232 u8 fid_c1; 233 u8 fid; 234 } __packed; 235 236 /** 237 * struct prueth_fdb_slot - Result of FDB slot lookup 238 * @mac: MAC address 239 * @fid: fid to be associated with MAC 240 * @fid_c2: FID_C2 entry for this MAC 241 */ 242 struct prueth_fdb_slot { 243 u8 mac[ETH_ALEN]; 244 u8 fid; 245 u8 fid_c2; 246 } __packed; 247 248 enum icssg_ietfpe_verify_states { 249 ICSSG_IETFPE_STATE_UNKNOWN = 0, 250 ICSSG_IETFPE_STATE_INITIAL, 251 ICSSG_IETFPE_STATE_VERIFYING, 252 ICSSG_IETFPE_STATE_SUCCEEDED, 253 ICSSG_IETFPE_STATE_FAILED, 254 ICSSG_IETFPE_STATE_DISABLED 255 }; 256 #endif /* __NET_TI_ICSSG_CONFIG_H */ 257