1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Texas Instruments ICSSG Ethernet Driver 4 * 5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 * Copyright (C) Siemens AG, 2024 7 * 8 */ 9 10 #include <linux/dma-mapping.h> 11 #include <linux/dma/ti-cppi5.h> 12 #include <linux/etherdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/of_mdio.h> 17 #include <linux/phy.h> 18 #include <linux/remoteproc/pruss.h> 19 #include <linux/regmap.h> 20 #include <linux/remoteproc.h> 21 22 #include "icssg_prueth.h" 23 #include "../k3-cppi-desc-pool.h" 24 25 /* Netif debug messages possible */ 26 #define PRUETH_EMAC_DEBUG (NETIF_MSG_DRV | \ 27 NETIF_MSG_PROBE | \ 28 NETIF_MSG_LINK | \ 29 NETIF_MSG_TIMER | \ 30 NETIF_MSG_IFDOWN | \ 31 NETIF_MSG_IFUP | \ 32 NETIF_MSG_RX_ERR | \ 33 NETIF_MSG_TX_ERR | \ 34 NETIF_MSG_TX_QUEUED | \ 35 NETIF_MSG_INTR | \ 36 NETIF_MSG_TX_DONE | \ 37 NETIF_MSG_RX_STATUS | \ 38 NETIF_MSG_PKTDATA | \ 39 NETIF_MSG_HW | \ 40 NETIF_MSG_WOL) 41 42 #define prueth_napi_to_emac(napi) container_of(napi, struct prueth_emac, napi_rx) 43 44 void prueth_cleanup_rx_chns(struct prueth_emac *emac, 45 struct prueth_rx_chn *rx_chn, 46 int max_rflows) 47 { 48 if (rx_chn->pg_pool) { 49 page_pool_destroy(rx_chn->pg_pool); 50 rx_chn->pg_pool = NULL; 51 } 52 53 if (rx_chn->desc_pool) 54 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 55 56 if (rx_chn->rx_chn) 57 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 58 } 59 EXPORT_SYMBOL_GPL(prueth_cleanup_rx_chns); 60 61 void prueth_cleanup_tx_chns(struct prueth_emac *emac) 62 { 63 int i; 64 65 for (i = 0; i < emac->tx_ch_num; i++) { 66 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 67 68 if (tx_chn->desc_pool) 69 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 70 71 if (tx_chn->tx_chn) 72 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 73 74 /* Assume prueth_cleanup_tx_chns() is called at the 75 * end after all channel resources are freed 76 */ 77 memset(tx_chn, 0, sizeof(*tx_chn)); 78 } 79 } 80 EXPORT_SYMBOL_GPL(prueth_cleanup_tx_chns); 81 82 void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num) 83 { 84 int i; 85 86 for (i = 0; i < num; i++) { 87 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 88 89 if (tx_chn->irq) 90 free_irq(tx_chn->irq, tx_chn); 91 netif_napi_del(&tx_chn->napi_tx); 92 } 93 } 94 EXPORT_SYMBOL_GPL(prueth_ndev_del_tx_napi); 95 96 void prueth_xmit_free(struct prueth_tx_chn *tx_chn, 97 struct cppi5_host_desc_t *desc) 98 { 99 struct cppi5_host_desc_t *first_desc, *next_desc; 100 dma_addr_t buf_dma, next_desc_dma; 101 struct prueth_swdata *swdata; 102 struct page *page; 103 u32 buf_dma_len; 104 105 first_desc = desc; 106 next_desc = first_desc; 107 108 swdata = cppi5_hdesc_get_swdata(desc); 109 if (swdata->type == PRUETH_SWDATA_PAGE) { 110 page = swdata->data.page; 111 page_pool_recycle_direct(page->pp, swdata->data.page); 112 goto free_desc; 113 } 114 115 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 116 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 117 118 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, 119 DMA_TO_DEVICE); 120 121 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 122 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 123 while (next_desc_dma) { 124 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 125 next_desc_dma); 126 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 127 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 128 129 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 130 DMA_TO_DEVICE); 131 132 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 133 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 134 135 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 136 } 137 138 free_desc: 139 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 140 } 141 EXPORT_SYMBOL_GPL(prueth_xmit_free); 142 143 int emac_tx_complete_packets(struct prueth_emac *emac, int chn, 144 int budget, bool *tdown) 145 { 146 struct net_device *ndev = emac->ndev; 147 struct cppi5_host_desc_t *desc_tx; 148 struct netdev_queue *netif_txq; 149 struct prueth_swdata *swdata; 150 struct prueth_tx_chn *tx_chn; 151 unsigned int total_bytes = 0; 152 struct xdp_frame *xdpf; 153 struct sk_buff *skb; 154 dma_addr_t desc_dma; 155 int res, num_tx = 0; 156 157 tx_chn = &emac->tx_chns[chn]; 158 159 while (true) { 160 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 161 if (res == -ENODATA) 162 break; 163 164 /* teardown completion */ 165 if (cppi5_desc_is_tdcm(desc_dma)) { 166 if (atomic_dec_and_test(&emac->tdown_cnt)) 167 complete(&emac->tdown_complete); 168 *tdown = true; 169 break; 170 } 171 172 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 173 desc_dma); 174 swdata = cppi5_hdesc_get_swdata(desc_tx); 175 176 switch (swdata->type) { 177 case PRUETH_SWDATA_SKB: 178 skb = swdata->data.skb; 179 dev_sw_netstats_tx_add(skb->dev, 1, skb->len); 180 total_bytes += skb->len; 181 napi_consume_skb(skb, budget); 182 break; 183 case PRUETH_SWDATA_XDPF: 184 xdpf = swdata->data.xdpf; 185 dev_sw_netstats_tx_add(ndev, 1, xdpf->len); 186 total_bytes += xdpf->len; 187 xdp_return_frame(xdpf); 188 break; 189 default: 190 netdev_err(ndev, "tx_complete: invalid swdata type %d\n", swdata->type); 191 prueth_xmit_free(tx_chn, desc_tx); 192 ndev->stats.tx_dropped++; 193 continue; 194 } 195 196 prueth_xmit_free(tx_chn, desc_tx); 197 num_tx++; 198 } 199 200 if (!num_tx) 201 return 0; 202 203 netif_txq = netdev_get_tx_queue(ndev, chn); 204 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 205 206 if (netif_tx_queue_stopped(netif_txq)) { 207 /* If the TX queue was stopped, wake it now 208 * if we have enough room. 209 */ 210 __netif_tx_lock(netif_txq, smp_processor_id()); 211 if (netif_running(ndev) && 212 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 213 MAX_SKB_FRAGS)) 214 netif_tx_wake_queue(netif_txq); 215 __netif_tx_unlock(netif_txq); 216 } 217 218 return num_tx; 219 } 220 221 static enum hrtimer_restart emac_tx_timer_callback(struct hrtimer *timer) 222 { 223 struct prueth_tx_chn *tx_chns = 224 container_of(timer, struct prueth_tx_chn, tx_hrtimer); 225 226 enable_irq(tx_chns->irq); 227 return HRTIMER_NORESTART; 228 } 229 230 static int emac_napi_tx_poll(struct napi_struct *napi_tx, int budget) 231 { 232 struct prueth_tx_chn *tx_chn = prueth_napi_to_tx_chn(napi_tx); 233 struct prueth_emac *emac = tx_chn->emac; 234 bool tdown = false; 235 int num_tx_packets; 236 237 num_tx_packets = emac_tx_complete_packets(emac, tx_chn->id, budget, 238 &tdown); 239 240 if (num_tx_packets >= budget) 241 return budget; 242 243 if (napi_complete_done(napi_tx, num_tx_packets)) { 244 if (unlikely(tx_chn->tx_pace_timeout_ns && !tdown)) { 245 hrtimer_start(&tx_chn->tx_hrtimer, 246 ns_to_ktime(tx_chn->tx_pace_timeout_ns), 247 HRTIMER_MODE_REL_PINNED); 248 } else { 249 enable_irq(tx_chn->irq); 250 } 251 } 252 253 return num_tx_packets; 254 } 255 256 static irqreturn_t prueth_tx_irq(int irq, void *dev_id) 257 { 258 struct prueth_tx_chn *tx_chn = dev_id; 259 260 disable_irq_nosync(irq); 261 napi_schedule(&tx_chn->napi_tx); 262 263 return IRQ_HANDLED; 264 } 265 266 int prueth_ndev_add_tx_napi(struct prueth_emac *emac) 267 { 268 struct prueth *prueth = emac->prueth; 269 int i, ret; 270 271 for (i = 0; i < emac->tx_ch_num; i++) { 272 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 273 274 netif_napi_add_tx(emac->ndev, &tx_chn->napi_tx, emac_napi_tx_poll); 275 hrtimer_setup(&tx_chn->tx_hrtimer, &emac_tx_timer_callback, CLOCK_MONOTONIC, 276 HRTIMER_MODE_REL_PINNED); 277 ret = request_irq(tx_chn->irq, prueth_tx_irq, 278 IRQF_TRIGGER_HIGH, tx_chn->name, 279 tx_chn); 280 if (ret) { 281 netif_napi_del(&tx_chn->napi_tx); 282 dev_err(prueth->dev, "unable to request TX IRQ %d\n", 283 tx_chn->irq); 284 goto fail; 285 } 286 } 287 288 return 0; 289 fail: 290 prueth_ndev_del_tx_napi(emac, i); 291 return ret; 292 } 293 EXPORT_SYMBOL_GPL(prueth_ndev_add_tx_napi); 294 295 int prueth_init_tx_chns(struct prueth_emac *emac) 296 { 297 static const struct k3_ring_cfg ring_cfg = { 298 .elm_size = K3_RINGACC_RING_ELSIZE_8, 299 .mode = K3_RINGACC_RING_MODE_RING, 300 .flags = 0, 301 .size = PRUETH_MAX_TX_DESC, 302 }; 303 struct k3_udma_glue_tx_channel_cfg tx_cfg; 304 struct device *dev = emac->prueth->dev; 305 struct net_device *ndev = emac->ndev; 306 int ret, slice, i; 307 u32 hdesc_size; 308 309 slice = prueth_emac_slice(emac); 310 if (slice < 0) 311 return slice; 312 313 init_completion(&emac->tdown_complete); 314 315 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 316 PRUETH_NAV_SW_DATA_SIZE); 317 memset(&tx_cfg, 0, sizeof(tx_cfg)); 318 tx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 319 tx_cfg.tx_cfg = ring_cfg; 320 tx_cfg.txcq_cfg = ring_cfg; 321 322 for (i = 0; i < emac->tx_ch_num; i++) { 323 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 324 325 /* To differentiate channels for SLICE0 vs SLICE1 */ 326 snprintf(tx_chn->name, sizeof(tx_chn->name), 327 "tx%d-%d", slice, i); 328 329 tx_chn->emac = emac; 330 tx_chn->id = i; 331 tx_chn->descs_num = PRUETH_MAX_TX_DESC; 332 333 tx_chn->tx_chn = 334 k3_udma_glue_request_tx_chn(dev, tx_chn->name, 335 &tx_cfg); 336 if (IS_ERR(tx_chn->tx_chn)) { 337 ret = PTR_ERR(tx_chn->tx_chn); 338 tx_chn->tx_chn = NULL; 339 netdev_err(ndev, 340 "Failed to request tx dma ch: %d\n", ret); 341 goto fail; 342 } 343 344 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 345 tx_chn->desc_pool = 346 k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 347 tx_chn->descs_num, 348 hdesc_size, 349 tx_chn->name); 350 if (IS_ERR(tx_chn->desc_pool)) { 351 ret = PTR_ERR(tx_chn->desc_pool); 352 tx_chn->desc_pool = NULL; 353 netdev_err(ndev, "Failed to create tx pool: %d\n", ret); 354 goto fail; 355 } 356 357 ret = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 358 if (ret < 0) { 359 netdev_err(ndev, "failed to get tx irq\n"); 360 goto fail; 361 } 362 tx_chn->irq = ret; 363 364 snprintf(tx_chn->name, sizeof(tx_chn->name), "%s-tx%d", 365 dev_name(dev), tx_chn->id); 366 } 367 368 return 0; 369 370 fail: 371 prueth_cleanup_tx_chns(emac); 372 return ret; 373 } 374 EXPORT_SYMBOL_GPL(prueth_init_tx_chns); 375 376 int prueth_init_rx_chns(struct prueth_emac *emac, 377 struct prueth_rx_chn *rx_chn, 378 char *name, u32 max_rflows, 379 u32 max_desc_num) 380 { 381 struct k3_udma_glue_rx_channel_cfg rx_cfg; 382 struct device *dev = emac->prueth->dev; 383 struct net_device *ndev = emac->ndev; 384 u32 fdqring_id, hdesc_size; 385 int i, ret = 0, slice; 386 int flow_id_base; 387 388 slice = prueth_emac_slice(emac); 389 if (slice < 0) 390 return slice; 391 392 /* To differentiate channels for SLICE0 vs SLICE1 */ 393 snprintf(rx_chn->name, sizeof(rx_chn->name), "%s%d", name, slice); 394 395 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 396 PRUETH_NAV_SW_DATA_SIZE); 397 memset(&rx_cfg, 0, sizeof(rx_cfg)); 398 rx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 399 rx_cfg.flow_id_num = max_rflows; 400 rx_cfg.flow_id_base = -1; /* udmax will auto select flow id base */ 401 402 /* init all flows */ 403 rx_chn->dev = dev; 404 rx_chn->descs_num = max_desc_num; 405 406 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, rx_chn->name, 407 &rx_cfg); 408 if (IS_ERR(rx_chn->rx_chn)) { 409 ret = PTR_ERR(rx_chn->rx_chn); 410 rx_chn->rx_chn = NULL; 411 netdev_err(ndev, "Failed to request rx dma ch: %d\n", ret); 412 goto fail; 413 } 414 415 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 416 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 417 rx_chn->descs_num, 418 hdesc_size, 419 rx_chn->name); 420 if (IS_ERR(rx_chn->desc_pool)) { 421 ret = PTR_ERR(rx_chn->desc_pool); 422 rx_chn->desc_pool = NULL; 423 netdev_err(ndev, "Failed to create rx pool: %d\n", ret); 424 goto fail; 425 } 426 427 flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 428 if (emac->is_sr1 && !strcmp(name, "rxmgm")) { 429 emac->rx_mgm_flow_id_base = flow_id_base; 430 netdev_dbg(ndev, "mgm flow id base = %d\n", flow_id_base); 431 } else { 432 emac->rx_flow_id_base = flow_id_base; 433 netdev_dbg(ndev, "flow id base = %d\n", flow_id_base); 434 } 435 436 fdqring_id = K3_RINGACC_RING_ID_ANY; 437 for (i = 0; i < rx_cfg.flow_id_num; i++) { 438 struct k3_ring_cfg rxring_cfg = { 439 .elm_size = K3_RINGACC_RING_ELSIZE_8, 440 .mode = K3_RINGACC_RING_MODE_RING, 441 .flags = 0, 442 }; 443 struct k3_ring_cfg fdqring_cfg = { 444 .elm_size = K3_RINGACC_RING_ELSIZE_8, 445 .flags = K3_RINGACC_RING_SHARED, 446 }; 447 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 448 .rx_cfg = rxring_cfg, 449 .rxfdq_cfg = fdqring_cfg, 450 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 451 .src_tag_lo_sel = 452 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 453 }; 454 455 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 456 rx_flow_cfg.rx_cfg.size = max_desc_num; 457 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 458 rx_flow_cfg.rxfdq_cfg.mode = emac->prueth->pdata.fdqring_mode; 459 460 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 461 i, &rx_flow_cfg); 462 if (ret) { 463 netdev_err(ndev, "Failed to init rx flow%d %d\n", 464 i, ret); 465 goto fail; 466 } 467 if (!i) 468 fdqring_id = k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 469 i); 470 ret = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 471 if (ret < 0) { 472 netdev_err(ndev, "Failed to get rx dma irq"); 473 goto fail; 474 } 475 rx_chn->irq[i] = ret; 476 } 477 478 return 0; 479 480 fail: 481 prueth_cleanup_rx_chns(emac, rx_chn, max_rflows); 482 return ret; 483 } 484 EXPORT_SYMBOL_GPL(prueth_init_rx_chns); 485 486 int prueth_dma_rx_push_mapped(struct prueth_emac *emac, 487 struct prueth_rx_chn *rx_chn, 488 struct page *page, u32 buf_len) 489 { 490 struct net_device *ndev = emac->ndev; 491 struct cppi5_host_desc_t *desc_rx; 492 struct prueth_swdata *swdata; 493 dma_addr_t desc_dma; 494 dma_addr_t buf_dma; 495 496 buf_dma = page_pool_get_dma_addr(page) + PRUETH_HEADROOM; 497 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 498 if (!desc_rx) { 499 netdev_err(ndev, "rx push: failed to allocate descriptor\n"); 500 return -ENOMEM; 501 } 502 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 503 504 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 505 PRUETH_NAV_PS_DATA_SIZE); 506 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 507 cppi5_hdesc_attach_buf(desc_rx, buf_dma, buf_len, buf_dma, buf_len); 508 509 swdata = cppi5_hdesc_get_swdata(desc_rx); 510 swdata->type = PRUETH_SWDATA_PAGE; 511 swdata->data.page = page; 512 513 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, PRUETH_RX_FLOW_DATA, 514 desc_rx, desc_dma); 515 } 516 EXPORT_SYMBOL_GPL(prueth_dma_rx_push_mapped); 517 518 u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns) 519 { 520 u32 iepcount_lo, iepcount_hi, hi_rollover_count; 521 u64 ns; 522 523 iepcount_lo = lo & GENMASK(19, 0); 524 iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20; 525 hi_rollover_count = hi >> 11; 526 527 ns = ((u64)hi_rollover_count) << 23 | (iepcount_hi + hi_sw); 528 ns = ns * cycle_time_ns + iepcount_lo; 529 530 return ns; 531 } 532 EXPORT_SYMBOL_GPL(icssg_ts_to_ns); 533 534 void emac_rx_timestamp(struct prueth_emac *emac, 535 struct sk_buff *skb, u32 *psdata) 536 { 537 struct skb_shared_hwtstamps *ssh; 538 u64 ns; 539 540 if (emac->is_sr1) { 541 ns = (u64)psdata[1] << 32 | psdata[0]; 542 } else { 543 u32 hi_sw = readl(emac->prueth->shram.va + 544 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 545 ns = icssg_ts_to_ns(hi_sw, psdata[1], psdata[0], 546 IEP_DEFAULT_CYCLE_TIME_NS); 547 } 548 549 ssh = skb_hwtstamps(skb); 550 memset(ssh, 0, sizeof(*ssh)); 551 ssh->hwtstamp = ns_to_ktime(ns); 552 } 553 554 /** 555 * emac_xmit_xdp_frame - transmits an XDP frame 556 * @emac: emac device 557 * @xdpf: data to transmit 558 * @page: page from page pool if already DMA mapped 559 * @q_idx: queue id 560 * 561 * Return: XDP state 562 */ 563 u32 emac_xmit_xdp_frame(struct prueth_emac *emac, 564 struct xdp_frame *xdpf, 565 struct page *page, 566 unsigned int q_idx) 567 { 568 struct cppi5_host_desc_t *first_desc; 569 struct net_device *ndev = emac->ndev; 570 struct prueth_tx_chn *tx_chn; 571 dma_addr_t desc_dma, buf_dma; 572 struct prueth_swdata *swdata; 573 u32 *epib; 574 int ret; 575 576 if (q_idx >= PRUETH_MAX_TX_QUEUES) { 577 netdev_err(ndev, "xdp tx: invalid q_id %d\n", q_idx); 578 return ICSSG_XDP_CONSUMED; /* drop */ 579 } 580 581 tx_chn = &emac->tx_chns[q_idx]; 582 583 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 584 if (!first_desc) { 585 netdev_dbg(ndev, "xdp tx: failed to allocate descriptor\n"); 586 goto drop_free_descs; /* drop */ 587 } 588 589 if (page) { /* already DMA mapped by page_pool */ 590 buf_dma = page_pool_get_dma_addr(page); 591 buf_dma += xdpf->headroom + sizeof(struct xdp_frame); 592 } else { /* Map the linear buffer */ 593 buf_dma = dma_map_single(tx_chn->dma_dev, xdpf->data, xdpf->len, DMA_TO_DEVICE); 594 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 595 netdev_err(ndev, "xdp tx: failed to map data buffer\n"); 596 goto drop_free_descs; /* drop */ 597 } 598 } 599 600 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 601 PRUETH_NAV_PS_DATA_SIZE); 602 cppi5_hdesc_set_pkttype(first_desc, 0); 603 epib = first_desc->epib; 604 epib[0] = 0; 605 epib[1] = 0; 606 607 /* set dst tag to indicate internal qid at the firmware which is at 608 * bit8..bit15. bit0..bit7 indicates port num for directed 609 * packets in case of switch mode operation 610 */ 611 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8))); 612 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 613 cppi5_hdesc_attach_buf(first_desc, buf_dma, xdpf->len, buf_dma, xdpf->len); 614 swdata = cppi5_hdesc_get_swdata(first_desc); 615 if (page) { 616 swdata->type = PRUETH_SWDATA_PAGE; 617 swdata->data.page = page; 618 } else { 619 swdata->type = PRUETH_SWDATA_XDPF; 620 swdata->data.xdpf = xdpf; 621 } 622 623 cppi5_hdesc_set_pktlen(first_desc, xdpf->len); 624 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 625 626 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 627 if (ret) { 628 netdev_err(ndev, "xdp tx: push failed: %d\n", ret); 629 goto drop_free_descs; 630 } 631 632 return ICSSG_XDP_TX; 633 634 drop_free_descs: 635 prueth_xmit_free(tx_chn, first_desc); 636 return ICSSG_XDP_CONSUMED; 637 } 638 EXPORT_SYMBOL_GPL(emac_xmit_xdp_frame); 639 640 /** 641 * emac_run_xdp - run an XDP program 642 * @emac: emac device 643 * @xdp: XDP buffer containing the frame 644 * @page: page with RX data if already DMA mapped 645 * @len: Rx descriptor packet length 646 * 647 * Return: XDP state 648 */ 649 static u32 emac_run_xdp(struct prueth_emac *emac, struct xdp_buff *xdp, 650 struct page *page, u32 *len) 651 { 652 struct net_device *ndev = emac->ndev; 653 struct bpf_prog *xdp_prog; 654 struct xdp_frame *xdpf; 655 u32 pkt_len = *len; 656 u32 act, result; 657 int q_idx, err; 658 659 xdp_prog = READ_ONCE(emac->xdp_prog); 660 act = bpf_prog_run_xdp(xdp_prog, xdp); 661 switch (act) { 662 case XDP_PASS: 663 return ICSSG_XDP_PASS; 664 case XDP_TX: 665 /* Send packet to TX ring for immediate transmission */ 666 xdpf = xdp_convert_buff_to_frame(xdp); 667 if (unlikely(!xdpf)) { 668 ndev->stats.tx_dropped++; 669 goto drop; 670 } 671 672 q_idx = smp_processor_id() % emac->tx_ch_num; 673 result = emac_xmit_xdp_frame(emac, xdpf, page, q_idx); 674 if (result == ICSSG_XDP_CONSUMED) 675 goto drop; 676 677 dev_sw_netstats_rx_add(ndev, xdpf->len); 678 return result; 679 case XDP_REDIRECT: 680 err = xdp_do_redirect(emac->ndev, xdp, xdp_prog); 681 if (err) 682 goto drop; 683 684 dev_sw_netstats_rx_add(ndev, pkt_len); 685 return ICSSG_XDP_REDIR; 686 default: 687 bpf_warn_invalid_xdp_action(emac->ndev, xdp_prog, act); 688 fallthrough; 689 case XDP_ABORTED: 690 drop: 691 trace_xdp_exception(emac->ndev, xdp_prog, act); 692 fallthrough; /* handle aborts by dropping packet */ 693 case XDP_DROP: 694 ndev->stats.rx_dropped++; 695 page_pool_recycle_direct(emac->rx_chns.pg_pool, page); 696 return ICSSG_XDP_CONSUMED; 697 } 698 } 699 700 static int emac_rx_packet(struct prueth_emac *emac, u32 flow_id, u32 *xdp_state) 701 { 702 struct prueth_rx_chn *rx_chn = &emac->rx_chns; 703 u32 buf_dma_len, pkt_len, port_id = 0; 704 struct net_device *ndev = emac->ndev; 705 struct cppi5_host_desc_t *desc_rx; 706 struct prueth_swdata *swdata; 707 dma_addr_t desc_dma, buf_dma; 708 struct page *page, *new_page; 709 struct page_pool *pool; 710 struct sk_buff *skb; 711 struct xdp_buff xdp; 712 u32 *psdata; 713 void *pa; 714 int ret; 715 716 *xdp_state = 0; 717 pool = rx_chn->pg_pool; 718 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_id, &desc_dma); 719 if (ret) { 720 if (ret != -ENODATA) 721 netdev_err(ndev, "rx pop: failed: %d\n", ret); 722 return ret; 723 } 724 725 if (cppi5_desc_is_tdcm(desc_dma)) /* Teardown ? */ 726 return 0; 727 728 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 729 swdata = cppi5_hdesc_get_swdata(desc_rx); 730 if (swdata->type != PRUETH_SWDATA_PAGE) { 731 netdev_err(ndev, "rx_pkt: invalid swdata->type %d\n", swdata->type); 732 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 733 return 0; 734 } 735 736 page = swdata->data.page; 737 page_pool_dma_sync_for_cpu(pool, page, 0, PAGE_SIZE); 738 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 739 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 740 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 741 /* firmware adds 4 CRC bytes, strip them */ 742 pkt_len -= 4; 743 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 744 745 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 746 747 /* if allocation fails we drop the packet but push the 748 * descriptor back to the ring with old page to prevent a stall 749 */ 750 new_page = page_pool_dev_alloc_pages(pool); 751 if (unlikely(!new_page)) { 752 new_page = page; 753 ndev->stats.rx_dropped++; 754 goto requeue; 755 } 756 757 pa = page_address(page); 758 if (emac->xdp_prog) { 759 xdp_init_buff(&xdp, PAGE_SIZE, &rx_chn->xdp_rxq); 760 xdp_prepare_buff(&xdp, pa, PRUETH_HEADROOM, pkt_len, false); 761 762 *xdp_state = emac_run_xdp(emac, &xdp, page, &pkt_len); 763 if (*xdp_state == ICSSG_XDP_PASS) 764 skb = xdp_build_skb_from_buff(&xdp); 765 else 766 goto requeue; 767 } else { 768 /* prepare skb and send to n/w stack */ 769 skb = napi_build_skb(pa, PAGE_SIZE); 770 } 771 772 if (!skb) { 773 ndev->stats.rx_dropped++; 774 page_pool_recycle_direct(pool, page); 775 goto requeue; 776 } 777 778 skb_reserve(skb, PRUETH_HEADROOM); 779 skb_put(skb, pkt_len); 780 skb->dev = ndev; 781 782 psdata = cppi5_hdesc_get_psdata(desc_rx); 783 /* RX HW timestamp */ 784 if (emac->rx_ts_enabled) 785 emac_rx_timestamp(emac, skb, psdata); 786 787 if (emac->prueth->is_switch_mode) 788 skb->offload_fwd_mark = emac->offload_fwd_mark; 789 skb->protocol = eth_type_trans(skb, ndev); 790 791 skb_mark_for_recycle(skb); 792 napi_gro_receive(&emac->napi_rx, skb); 793 ndev->stats.rx_bytes += pkt_len; 794 ndev->stats.rx_packets++; 795 796 requeue: 797 /* queue another RX DMA */ 798 ret = prueth_dma_rx_push_mapped(emac, &emac->rx_chns, new_page, 799 PRUETH_MAX_PKT_SIZE); 800 if (WARN_ON(ret < 0)) { 801 page_pool_recycle_direct(pool, new_page); 802 ndev->stats.rx_errors++; 803 ndev->stats.rx_dropped++; 804 } 805 806 return ret; 807 } 808 809 static void prueth_rx_cleanup(void *data, dma_addr_t desc_dma) 810 { 811 struct prueth_rx_chn *rx_chn = data; 812 struct cppi5_host_desc_t *desc_rx; 813 struct prueth_swdata *swdata; 814 struct page_pool *pool; 815 struct page *page; 816 817 pool = rx_chn->pg_pool; 818 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 819 swdata = cppi5_hdesc_get_swdata(desc_rx); 820 if (swdata->type == PRUETH_SWDATA_PAGE) { 821 page = swdata->data.page; 822 page_pool_recycle_direct(pool, page); 823 } 824 825 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 826 } 827 828 static int prueth_tx_ts_cookie_get(struct prueth_emac *emac) 829 { 830 int i; 831 832 /* search and get the next free slot */ 833 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 834 if (!emac->tx_ts_skb[i]) { 835 emac->tx_ts_skb[i] = ERR_PTR(-EBUSY); /* reserve slot */ 836 return i; 837 } 838 } 839 840 return -EBUSY; 841 } 842 843 /** 844 * icssg_ndo_start_xmit - EMAC Transmit function 845 * @skb: SKB pointer 846 * @ndev: EMAC network adapter 847 * 848 * Called by the system to transmit a packet - we queue the packet in 849 * EMAC hardware transmit queue 850 * Doesn't wait for completion we'll check for TX completion in 851 * emac_tx_complete_packets(). 852 * 853 * Return: enum netdev_tx 854 */ 855 enum netdev_tx icssg_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev) 856 { 857 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 858 struct prueth_emac *emac = netdev_priv(ndev); 859 struct prueth *prueth = emac->prueth; 860 struct netdev_queue *netif_txq; 861 struct prueth_swdata *swdata; 862 struct prueth_tx_chn *tx_chn; 863 dma_addr_t desc_dma, buf_dma; 864 u32 pkt_len, dst_tag_id; 865 int i, ret = 0, q_idx; 866 bool in_tx_ts = 0; 867 int tx_ts_cookie; 868 u32 *epib; 869 870 pkt_len = skb_headlen(skb); 871 q_idx = skb_get_queue_mapping(skb); 872 873 tx_chn = &emac->tx_chns[q_idx]; 874 netif_txq = netdev_get_tx_queue(ndev, q_idx); 875 876 /* Map the linear buffer */ 877 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, DMA_TO_DEVICE); 878 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 879 netdev_err(ndev, "tx: failed to map skb buffer\n"); 880 ret = NETDEV_TX_OK; 881 goto drop_free_skb; 882 } 883 884 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 885 if (!first_desc) { 886 netdev_dbg(ndev, "tx: failed to allocate descriptor\n"); 887 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, DMA_TO_DEVICE); 888 goto drop_stop_q_busy; 889 } 890 891 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 892 PRUETH_NAV_PS_DATA_SIZE); 893 cppi5_hdesc_set_pkttype(first_desc, 0); 894 epib = first_desc->epib; 895 epib[0] = 0; 896 epib[1] = 0; 897 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 898 emac->tx_ts_enabled) { 899 tx_ts_cookie = prueth_tx_ts_cookie_get(emac); 900 if (tx_ts_cookie >= 0) { 901 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 902 /* Request TX timestamp */ 903 epib[0] = (u32)tx_ts_cookie; 904 epib[1] = 0x80000000; /* TX TS request */ 905 emac->tx_ts_skb[tx_ts_cookie] = skb_get(skb); 906 in_tx_ts = 1; 907 } 908 } 909 910 /* set dst tag to indicate internal qid at the firmware which is at 911 * bit8..bit15. bit0..bit7 indicates port num for directed 912 * packets in case of switch mode operation and port num 0 913 * for undirected packets in case of HSR offload mode 914 */ 915 dst_tag_id = emac->port_id | (q_idx << 8); 916 917 if (prueth->is_hsr_offload_mode && 918 (ndev->features & NETIF_F_HW_HSR_DUP)) 919 dst_tag_id = PRUETH_UNDIRECTED_PKT_DST_TAG; 920 921 if (prueth->is_hsr_offload_mode && 922 (ndev->features & NETIF_F_HW_HSR_TAG_INS)) 923 epib[1] |= PRUETH_UNDIRECTED_PKT_TAG_INS; 924 925 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, dst_tag_id); 926 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 927 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 928 swdata = cppi5_hdesc_get_swdata(first_desc); 929 swdata->type = PRUETH_SWDATA_SKB; 930 swdata->data.skb = skb; 931 932 /* Handle the case where skb is fragmented in pages */ 933 cur_desc = first_desc; 934 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 935 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 936 u32 frag_size = skb_frag_size(frag); 937 938 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 939 if (!next_desc) { 940 netdev_err(ndev, 941 "tx: failed to allocate frag. descriptor\n"); 942 goto free_desc_stop_q_busy_cleanup_tx_ts; 943 } 944 945 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 946 DMA_TO_DEVICE); 947 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 948 netdev_err(ndev, "tx: Failed to map skb page\n"); 949 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 950 ret = NETDEV_TX_OK; 951 goto cleanup_tx_ts; 952 } 953 954 cppi5_hdesc_reset_hbdesc(next_desc); 955 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 956 cppi5_hdesc_attach_buf(next_desc, 957 buf_dma, frag_size, buf_dma, frag_size); 958 959 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 960 next_desc); 961 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 962 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 963 964 pkt_len += frag_size; 965 cur_desc = next_desc; 966 } 967 WARN_ON_ONCE(pkt_len != skb->len); 968 969 /* report bql before sending packet */ 970 netdev_tx_sent_queue(netif_txq, pkt_len); 971 972 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 973 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 974 /* cppi5_desc_dump(first_desc, 64); */ 975 976 skb_tx_timestamp(skb); /* SW timestamp if SKBTX_IN_PROGRESS not set */ 977 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 978 if (ret) { 979 netdev_err(ndev, "tx: push failed: %d\n", ret); 980 goto drop_free_descs; 981 } 982 983 if (in_tx_ts) 984 atomic_inc(&emac->tx_ts_pending); 985 986 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 987 netif_tx_stop_queue(netif_txq); 988 /* Barrier, so that stop_queue visible to other cpus */ 989 smp_mb__after_atomic(); 990 991 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 992 MAX_SKB_FRAGS) 993 netif_tx_wake_queue(netif_txq); 994 } 995 996 return NETDEV_TX_OK; 997 998 cleanup_tx_ts: 999 if (in_tx_ts) { 1000 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 1001 emac->tx_ts_skb[tx_ts_cookie] = NULL; 1002 } 1003 1004 drop_free_descs: 1005 prueth_xmit_free(tx_chn, first_desc); 1006 1007 drop_free_skb: 1008 dev_kfree_skb_any(skb); 1009 1010 /* error */ 1011 ndev->stats.tx_dropped++; 1012 netdev_err(ndev, "tx: error: %d\n", ret); 1013 1014 return ret; 1015 1016 free_desc_stop_q_busy_cleanup_tx_ts: 1017 if (in_tx_ts) { 1018 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 1019 emac->tx_ts_skb[tx_ts_cookie] = NULL; 1020 } 1021 prueth_xmit_free(tx_chn, first_desc); 1022 1023 drop_stop_q_busy: 1024 netif_tx_stop_queue(netif_txq); 1025 return NETDEV_TX_BUSY; 1026 } 1027 EXPORT_SYMBOL_GPL(icssg_ndo_start_xmit); 1028 1029 static void prueth_tx_cleanup(void *data, dma_addr_t desc_dma) 1030 { 1031 struct prueth_tx_chn *tx_chn = data; 1032 struct cppi5_host_desc_t *desc_tx; 1033 struct prueth_swdata *swdata; 1034 struct xdp_frame *xdpf; 1035 struct sk_buff *skb; 1036 1037 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 1038 swdata = cppi5_hdesc_get_swdata(desc_tx); 1039 1040 switch (swdata->type) { 1041 case PRUETH_SWDATA_SKB: 1042 skb = swdata->data.skb; 1043 dev_kfree_skb_any(skb); 1044 break; 1045 case PRUETH_SWDATA_XDPF: 1046 xdpf = swdata->data.xdpf; 1047 xdp_return_frame(xdpf); 1048 break; 1049 default: 1050 break; 1051 } 1052 1053 prueth_xmit_free(tx_chn, desc_tx); 1054 } 1055 1056 irqreturn_t prueth_rx_irq(int irq, void *dev_id) 1057 { 1058 struct prueth_emac *emac = dev_id; 1059 1060 disable_irq_nosync(irq); 1061 napi_schedule(&emac->napi_rx); 1062 1063 return IRQ_HANDLED; 1064 } 1065 EXPORT_SYMBOL_GPL(prueth_rx_irq); 1066 1067 void prueth_cleanup_tx_ts(struct prueth_emac *emac) 1068 { 1069 int i; 1070 1071 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 1072 if (emac->tx_ts_skb[i]) { 1073 dev_kfree_skb_any(emac->tx_ts_skb[i]); 1074 emac->tx_ts_skb[i] = NULL; 1075 } 1076 } 1077 } 1078 EXPORT_SYMBOL_GPL(prueth_cleanup_tx_ts); 1079 1080 int icssg_napi_rx_poll(struct napi_struct *napi_rx, int budget) 1081 { 1082 struct prueth_emac *emac = prueth_napi_to_emac(napi_rx); 1083 int rx_flow = emac->is_sr1 ? 1084 PRUETH_RX_FLOW_DATA_SR1 : PRUETH_RX_FLOW_DATA; 1085 int flow = emac->is_sr1 ? 1086 PRUETH_MAX_RX_FLOWS_SR1 : PRUETH_MAX_RX_FLOWS; 1087 int xdp_state_or = 0; 1088 int num_rx = 0; 1089 int cur_budget; 1090 u32 xdp_state; 1091 int ret; 1092 1093 while (flow--) { 1094 cur_budget = budget - num_rx; 1095 1096 while (cur_budget--) { 1097 ret = emac_rx_packet(emac, flow, &xdp_state); 1098 xdp_state_or |= xdp_state; 1099 if (ret) 1100 break; 1101 num_rx++; 1102 } 1103 1104 if (num_rx >= budget) 1105 break; 1106 } 1107 1108 if (xdp_state_or & ICSSG_XDP_REDIR) 1109 xdp_do_flush(); 1110 1111 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1112 if (unlikely(emac->rx_pace_timeout_ns)) { 1113 hrtimer_start(&emac->rx_hrtimer, 1114 ns_to_ktime(emac->rx_pace_timeout_ns), 1115 HRTIMER_MODE_REL_PINNED); 1116 } else { 1117 enable_irq(emac->rx_chns.irq[rx_flow]); 1118 } 1119 } 1120 1121 return num_rx; 1122 } 1123 EXPORT_SYMBOL_GPL(icssg_napi_rx_poll); 1124 1125 static struct page_pool *prueth_create_page_pool(struct prueth_emac *emac, 1126 struct device *dma_dev, 1127 int size) 1128 { 1129 struct page_pool_params pp_params = { 0 }; 1130 struct page_pool *pool; 1131 1132 pp_params.order = 0; 1133 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1134 pp_params.pool_size = size; 1135 pp_params.nid = dev_to_node(emac->prueth->dev); 1136 pp_params.dma_dir = DMA_BIDIRECTIONAL; 1137 pp_params.dev = dma_dev; 1138 pp_params.napi = &emac->napi_rx; 1139 pp_params.max_len = PAGE_SIZE; 1140 1141 pool = page_pool_create(&pp_params); 1142 if (IS_ERR(pool)) 1143 netdev_err(emac->ndev, "cannot create rx page pool\n"); 1144 1145 return pool; 1146 } 1147 1148 int prueth_prepare_rx_chan(struct prueth_emac *emac, 1149 struct prueth_rx_chn *chn, 1150 int buf_size) 1151 { 1152 struct page_pool *pool; 1153 struct page *page; 1154 int i, ret; 1155 1156 pool = prueth_create_page_pool(emac, chn->dma_dev, chn->descs_num); 1157 if (IS_ERR(pool)) 1158 return PTR_ERR(pool); 1159 1160 chn->pg_pool = pool; 1161 1162 for (i = 0; i < chn->descs_num; i++) { 1163 /* NOTE: we're not using memory efficiently here. 1164 * 1 full page (4KB?) used here instead of 1165 * PRUETH_MAX_PKT_SIZE (~1.5KB?) 1166 */ 1167 page = page_pool_dev_alloc_pages(pool); 1168 if (!page) { 1169 netdev_err(emac->ndev, "couldn't allocate rx page\n"); 1170 ret = -ENOMEM; 1171 goto recycle_alloc_pg; 1172 } 1173 1174 ret = prueth_dma_rx_push_mapped(emac, chn, page, buf_size); 1175 if (ret < 0) { 1176 netdev_err(emac->ndev, 1177 "cannot submit page for rx chan %s ret %d\n", 1178 chn->name, ret); 1179 page_pool_recycle_direct(pool, page); 1180 goto recycle_alloc_pg; 1181 } 1182 } 1183 1184 return 0; 1185 1186 recycle_alloc_pg: 1187 prueth_reset_rx_chan(&emac->rx_chns, PRUETH_MAX_RX_FLOWS, false); 1188 1189 return ret; 1190 } 1191 EXPORT_SYMBOL_GPL(prueth_prepare_rx_chan); 1192 1193 void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num, 1194 bool free_skb) 1195 { 1196 int i; 1197 1198 for (i = 0; i < ch_num; i++) { 1199 if (free_skb) 1200 k3_udma_glue_reset_tx_chn(emac->tx_chns[i].tx_chn, 1201 &emac->tx_chns[i], 1202 prueth_tx_cleanup); 1203 k3_udma_glue_disable_tx_chn(emac->tx_chns[i].tx_chn); 1204 } 1205 } 1206 EXPORT_SYMBOL_GPL(prueth_reset_tx_chan); 1207 1208 void prueth_reset_rx_chan(struct prueth_rx_chn *chn, 1209 int num_flows, bool disable) 1210 { 1211 int i; 1212 1213 for (i = 0; i < num_flows; i++) 1214 k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn, 1215 prueth_rx_cleanup); 1216 if (disable) 1217 k3_udma_glue_disable_rx_chn(chn->rx_chn); 1218 1219 page_pool_destroy(chn->pg_pool); 1220 chn->pg_pool = NULL; 1221 } 1222 EXPORT_SYMBOL_GPL(prueth_reset_rx_chan); 1223 1224 void icssg_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1225 { 1226 ndev->stats.tx_errors++; 1227 } 1228 EXPORT_SYMBOL_GPL(icssg_ndo_tx_timeout); 1229 1230 static int emac_set_ts_config(struct net_device *ndev, struct ifreq *ifr) 1231 { 1232 struct prueth_emac *emac = netdev_priv(ndev); 1233 struct hwtstamp_config config; 1234 1235 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 1236 return -EFAULT; 1237 1238 switch (config.tx_type) { 1239 case HWTSTAMP_TX_OFF: 1240 emac->tx_ts_enabled = 0; 1241 break; 1242 case HWTSTAMP_TX_ON: 1243 emac->tx_ts_enabled = 1; 1244 break; 1245 default: 1246 return -ERANGE; 1247 } 1248 1249 switch (config.rx_filter) { 1250 case HWTSTAMP_FILTER_NONE: 1251 emac->rx_ts_enabled = 0; 1252 break; 1253 case HWTSTAMP_FILTER_ALL: 1254 case HWTSTAMP_FILTER_SOME: 1255 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1256 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1257 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1258 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1259 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1260 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1261 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1262 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1263 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1264 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1265 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1266 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1267 case HWTSTAMP_FILTER_NTP_ALL: 1268 emac->rx_ts_enabled = 1; 1269 config.rx_filter = HWTSTAMP_FILTER_ALL; 1270 break; 1271 default: 1272 return -ERANGE; 1273 } 1274 1275 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1276 -EFAULT : 0; 1277 } 1278 1279 static int emac_get_ts_config(struct net_device *ndev, struct ifreq *ifr) 1280 { 1281 struct prueth_emac *emac = netdev_priv(ndev); 1282 struct hwtstamp_config config; 1283 1284 config.flags = 0; 1285 config.tx_type = emac->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1286 config.rx_filter = emac->rx_ts_enabled ? HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1287 1288 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1289 -EFAULT : 0; 1290 } 1291 1292 int icssg_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1293 { 1294 switch (cmd) { 1295 case SIOCGHWTSTAMP: 1296 return emac_get_ts_config(ndev, ifr); 1297 case SIOCSHWTSTAMP: 1298 return emac_set_ts_config(ndev, ifr); 1299 default: 1300 break; 1301 } 1302 1303 return phy_do_ioctl(ndev, ifr, cmd); 1304 } 1305 EXPORT_SYMBOL_GPL(icssg_ndo_ioctl); 1306 1307 void icssg_ndo_get_stats64(struct net_device *ndev, 1308 struct rtnl_link_stats64 *stats) 1309 { 1310 struct prueth_emac *emac = netdev_priv(ndev); 1311 1312 emac_update_hardware_stats(emac); 1313 1314 stats->rx_packets = emac_get_stat_by_name(emac, "rx_packets"); 1315 stats->rx_bytes = emac_get_stat_by_name(emac, "rx_bytes"); 1316 stats->tx_packets = emac_get_stat_by_name(emac, "tx_packets"); 1317 stats->tx_bytes = emac_get_stat_by_name(emac, "tx_bytes"); 1318 stats->rx_crc_errors = emac_get_stat_by_name(emac, "rx_crc_errors"); 1319 stats->rx_over_errors = emac_get_stat_by_name(emac, "rx_over_errors"); 1320 stats->multicast = emac_get_stat_by_name(emac, "rx_multicast_frames"); 1321 1322 stats->rx_errors = ndev->stats.rx_errors; 1323 stats->rx_dropped = ndev->stats.rx_dropped; 1324 stats->tx_errors = ndev->stats.tx_errors; 1325 stats->tx_dropped = ndev->stats.tx_dropped; 1326 } 1327 EXPORT_SYMBOL_GPL(icssg_ndo_get_stats64); 1328 1329 int icssg_ndo_get_phys_port_name(struct net_device *ndev, char *name, 1330 size_t len) 1331 { 1332 struct prueth_emac *emac = netdev_priv(ndev); 1333 int ret; 1334 1335 ret = snprintf(name, len, "p%d", emac->port_id); 1336 if (ret >= len) 1337 return -EINVAL; 1338 1339 return 0; 1340 } 1341 EXPORT_SYMBOL_GPL(icssg_ndo_get_phys_port_name); 1342 1343 /* get emac_port corresponding to eth_node name */ 1344 int prueth_node_port(struct device_node *eth_node) 1345 { 1346 u32 port_id; 1347 int ret; 1348 1349 ret = of_property_read_u32(eth_node, "reg", &port_id); 1350 if (ret) 1351 return ret; 1352 1353 if (port_id == 0) 1354 return PRUETH_PORT_MII0; 1355 else if (port_id == 1) 1356 return PRUETH_PORT_MII1; 1357 else 1358 return PRUETH_PORT_INVALID; 1359 } 1360 EXPORT_SYMBOL_GPL(prueth_node_port); 1361 1362 /* get MAC instance corresponding to eth_node name */ 1363 int prueth_node_mac(struct device_node *eth_node) 1364 { 1365 u32 port_id; 1366 int ret; 1367 1368 ret = of_property_read_u32(eth_node, "reg", &port_id); 1369 if (ret) 1370 return ret; 1371 1372 if (port_id == 0) 1373 return PRUETH_MAC0; 1374 else if (port_id == 1) 1375 return PRUETH_MAC1; 1376 else 1377 return PRUETH_MAC_INVALID; 1378 } 1379 EXPORT_SYMBOL_GPL(prueth_node_mac); 1380 1381 void prueth_netdev_exit(struct prueth *prueth, 1382 struct device_node *eth_node) 1383 { 1384 struct prueth_emac *emac; 1385 enum prueth_mac mac; 1386 1387 mac = prueth_node_mac(eth_node); 1388 if (mac == PRUETH_MAC_INVALID) 1389 return; 1390 1391 emac = prueth->emac[mac]; 1392 if (!emac) 1393 return; 1394 1395 if (of_phy_is_fixed_link(emac->phy_node)) 1396 of_phy_deregister_fixed_link(emac->phy_node); 1397 1398 netif_napi_del(&emac->napi_rx); 1399 1400 pruss_release_mem_region(prueth->pruss, &emac->dram); 1401 destroy_workqueue(emac->cmd_wq); 1402 free_netdev(emac->ndev); 1403 prueth->emac[mac] = NULL; 1404 } 1405 EXPORT_SYMBOL_GPL(prueth_netdev_exit); 1406 1407 int prueth_get_cores(struct prueth *prueth, int slice, bool is_sr1) 1408 { 1409 struct device *dev = prueth->dev; 1410 enum pruss_pru_id pruss_id; 1411 struct device_node *np; 1412 int idx = -1, ret; 1413 1414 np = dev->of_node; 1415 1416 switch (slice) { 1417 case ICSS_SLICE0: 1418 idx = 0; 1419 break; 1420 case ICSS_SLICE1: 1421 idx = is_sr1 ? 2 : 3; 1422 break; 1423 default: 1424 return -EINVAL; 1425 } 1426 1427 prueth->pru[slice] = pru_rproc_get(np, idx, &pruss_id); 1428 if (IS_ERR(prueth->pru[slice])) { 1429 ret = PTR_ERR(prueth->pru[slice]); 1430 prueth->pru[slice] = NULL; 1431 return dev_err_probe(dev, ret, "unable to get PRU%d\n", slice); 1432 } 1433 prueth->pru_id[slice] = pruss_id; 1434 1435 idx++; 1436 prueth->rtu[slice] = pru_rproc_get(np, idx, NULL); 1437 if (IS_ERR(prueth->rtu[slice])) { 1438 ret = PTR_ERR(prueth->rtu[slice]); 1439 prueth->rtu[slice] = NULL; 1440 return dev_err_probe(dev, ret, "unable to get RTU%d\n", slice); 1441 } 1442 1443 if (is_sr1) 1444 return 0; 1445 1446 idx++; 1447 prueth->txpru[slice] = pru_rproc_get(np, idx, NULL); 1448 if (IS_ERR(prueth->txpru[slice])) { 1449 ret = PTR_ERR(prueth->txpru[slice]); 1450 prueth->txpru[slice] = NULL; 1451 return dev_err_probe(dev, ret, "unable to get TX_PRU%d\n", slice); 1452 } 1453 1454 return 0; 1455 } 1456 EXPORT_SYMBOL_GPL(prueth_get_cores); 1457 1458 void prueth_put_cores(struct prueth *prueth, int slice) 1459 { 1460 if (prueth->txpru[slice]) 1461 pru_rproc_put(prueth->txpru[slice]); 1462 1463 if (prueth->rtu[slice]) 1464 pru_rproc_put(prueth->rtu[slice]); 1465 1466 if (prueth->pru[slice]) 1467 pru_rproc_put(prueth->pru[slice]); 1468 } 1469 EXPORT_SYMBOL_GPL(prueth_put_cores); 1470 1471 #ifdef CONFIG_PM_SLEEP 1472 static int prueth_suspend(struct device *dev) 1473 { 1474 struct prueth *prueth = dev_get_drvdata(dev); 1475 struct net_device *ndev; 1476 int i, ret; 1477 1478 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1479 ndev = prueth->registered_netdevs[i]; 1480 1481 if (!ndev) 1482 continue; 1483 1484 if (netif_running(ndev)) { 1485 netif_device_detach(ndev); 1486 ret = ndev->netdev_ops->ndo_stop(ndev); 1487 if (ret < 0) { 1488 netdev_err(ndev, "failed to stop: %d", ret); 1489 return ret; 1490 } 1491 } 1492 } 1493 1494 return 0; 1495 } 1496 1497 static int prueth_resume(struct device *dev) 1498 { 1499 struct prueth *prueth = dev_get_drvdata(dev); 1500 struct net_device *ndev; 1501 int i, ret; 1502 1503 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1504 ndev = prueth->registered_netdevs[i]; 1505 1506 if (!ndev) 1507 continue; 1508 1509 if (netif_running(ndev)) { 1510 ret = ndev->netdev_ops->ndo_open(ndev); 1511 if (ret < 0) { 1512 netdev_err(ndev, "failed to start: %d", ret); 1513 return ret; 1514 } 1515 netif_device_attach(ndev); 1516 } 1517 } 1518 1519 return 0; 1520 } 1521 #endif /* CONFIG_PM_SLEEP */ 1522 1523 const struct dev_pm_ops prueth_dev_pm_ops = { 1524 SET_SYSTEM_SLEEP_PM_OPS(prueth_suspend, prueth_resume) 1525 }; 1526 EXPORT_SYMBOL_GPL(prueth_dev_pm_ops); 1527 1528 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); 1529 MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>"); 1530 MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver Common Module"); 1531 MODULE_LICENSE("GPL"); 1532