1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Texas Instruments ICSSG Ethernet Driver 4 * 5 * Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/ 6 * Copyright (C) Siemens AG, 2024 7 * 8 */ 9 10 #include <linux/dma-mapping.h> 11 #include <linux/dma/ti-cppi5.h> 12 #include <linux/etherdevice.h> 13 #include <linux/interrupt.h> 14 #include <linux/kernel.h> 15 #include <linux/of.h> 16 #include <linux/of_mdio.h> 17 #include <linux/phy.h> 18 #include <linux/remoteproc/pruss.h> 19 #include <linux/regmap.h> 20 #include <linux/remoteproc.h> 21 22 #include "icssg_prueth.h" 23 #include "../k3-cppi-desc-pool.h" 24 25 /* Netif debug messages possible */ 26 #define PRUETH_EMAC_DEBUG (NETIF_MSG_DRV | \ 27 NETIF_MSG_PROBE | \ 28 NETIF_MSG_LINK | \ 29 NETIF_MSG_TIMER | \ 30 NETIF_MSG_IFDOWN | \ 31 NETIF_MSG_IFUP | \ 32 NETIF_MSG_RX_ERR | \ 33 NETIF_MSG_TX_ERR | \ 34 NETIF_MSG_TX_QUEUED | \ 35 NETIF_MSG_INTR | \ 36 NETIF_MSG_TX_DONE | \ 37 NETIF_MSG_RX_STATUS | \ 38 NETIF_MSG_PKTDATA | \ 39 NETIF_MSG_HW | \ 40 NETIF_MSG_WOL) 41 42 #define prueth_napi_to_emac(napi) container_of(napi, struct prueth_emac, napi_rx) 43 44 void prueth_cleanup_rx_chns(struct prueth_emac *emac, 45 struct prueth_rx_chn *rx_chn, 46 int max_rflows) 47 { 48 if (rx_chn->desc_pool) 49 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 50 51 if (rx_chn->rx_chn) 52 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 53 } 54 EXPORT_SYMBOL_GPL(prueth_cleanup_rx_chns); 55 56 void prueth_cleanup_tx_chns(struct prueth_emac *emac) 57 { 58 int i; 59 60 for (i = 0; i < emac->tx_ch_num; i++) { 61 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 62 63 if (tx_chn->desc_pool) 64 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 65 66 if (tx_chn->tx_chn) 67 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 68 69 /* Assume prueth_cleanup_tx_chns() is called at the 70 * end after all channel resources are freed 71 */ 72 memset(tx_chn, 0, sizeof(*tx_chn)); 73 } 74 } 75 EXPORT_SYMBOL_GPL(prueth_cleanup_tx_chns); 76 77 void prueth_ndev_del_tx_napi(struct prueth_emac *emac, int num) 78 { 79 int i; 80 81 for (i = 0; i < num; i++) { 82 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 83 84 if (tx_chn->irq) 85 free_irq(tx_chn->irq, tx_chn); 86 netif_napi_del(&tx_chn->napi_tx); 87 } 88 } 89 EXPORT_SYMBOL_GPL(prueth_ndev_del_tx_napi); 90 91 void prueth_xmit_free(struct prueth_tx_chn *tx_chn, 92 struct cppi5_host_desc_t *desc) 93 { 94 struct cppi5_host_desc_t *first_desc, *next_desc; 95 dma_addr_t buf_dma, next_desc_dma; 96 u32 buf_dma_len; 97 98 first_desc = desc; 99 next_desc = first_desc; 100 101 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 102 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 103 104 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, 105 DMA_TO_DEVICE); 106 107 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 108 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 109 while (next_desc_dma) { 110 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 111 next_desc_dma); 112 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 113 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 114 115 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 116 DMA_TO_DEVICE); 117 118 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 119 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 120 121 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 122 } 123 124 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 125 } 126 EXPORT_SYMBOL_GPL(prueth_xmit_free); 127 128 int emac_tx_complete_packets(struct prueth_emac *emac, int chn, 129 int budget, bool *tdown) 130 { 131 struct net_device *ndev = emac->ndev; 132 struct cppi5_host_desc_t *desc_tx; 133 struct netdev_queue *netif_txq; 134 struct prueth_tx_chn *tx_chn; 135 unsigned int total_bytes = 0; 136 struct sk_buff *skb; 137 dma_addr_t desc_dma; 138 int res, num_tx = 0; 139 void **swdata; 140 141 tx_chn = &emac->tx_chns[chn]; 142 143 while (true) { 144 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 145 if (res == -ENODATA) 146 break; 147 148 /* teardown completion */ 149 if (cppi5_desc_is_tdcm(desc_dma)) { 150 if (atomic_dec_and_test(&emac->tdown_cnt)) 151 complete(&emac->tdown_complete); 152 *tdown = true; 153 break; 154 } 155 156 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 157 desc_dma); 158 swdata = cppi5_hdesc_get_swdata(desc_tx); 159 160 /* was this command's TX complete? */ 161 if (emac->is_sr1 && *(swdata) == emac->cmd_data) { 162 prueth_xmit_free(tx_chn, desc_tx); 163 continue; 164 } 165 166 skb = *(swdata); 167 prueth_xmit_free(tx_chn, desc_tx); 168 169 ndev = skb->dev; 170 ndev->stats.tx_packets++; 171 ndev->stats.tx_bytes += skb->len; 172 total_bytes += skb->len; 173 napi_consume_skb(skb, budget); 174 num_tx++; 175 } 176 177 if (!num_tx) 178 return 0; 179 180 netif_txq = netdev_get_tx_queue(ndev, chn); 181 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 182 183 if (netif_tx_queue_stopped(netif_txq)) { 184 /* If the TX queue was stopped, wake it now 185 * if we have enough room. 186 */ 187 __netif_tx_lock(netif_txq, smp_processor_id()); 188 if (netif_running(ndev) && 189 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 190 MAX_SKB_FRAGS)) 191 netif_tx_wake_queue(netif_txq); 192 __netif_tx_unlock(netif_txq); 193 } 194 195 return num_tx; 196 } 197 198 static enum hrtimer_restart emac_tx_timer_callback(struct hrtimer *timer) 199 { 200 struct prueth_tx_chn *tx_chns = 201 container_of(timer, struct prueth_tx_chn, tx_hrtimer); 202 203 enable_irq(tx_chns->irq); 204 return HRTIMER_NORESTART; 205 } 206 207 static int emac_napi_tx_poll(struct napi_struct *napi_tx, int budget) 208 { 209 struct prueth_tx_chn *tx_chn = prueth_napi_to_tx_chn(napi_tx); 210 struct prueth_emac *emac = tx_chn->emac; 211 bool tdown = false; 212 int num_tx_packets; 213 214 num_tx_packets = emac_tx_complete_packets(emac, tx_chn->id, budget, 215 &tdown); 216 217 if (num_tx_packets >= budget) 218 return budget; 219 220 if (napi_complete_done(napi_tx, num_tx_packets)) { 221 if (unlikely(tx_chn->tx_pace_timeout_ns && !tdown)) { 222 hrtimer_start(&tx_chn->tx_hrtimer, 223 ns_to_ktime(tx_chn->tx_pace_timeout_ns), 224 HRTIMER_MODE_REL_PINNED); 225 } else { 226 enable_irq(tx_chn->irq); 227 } 228 } 229 230 return num_tx_packets; 231 } 232 233 static irqreturn_t prueth_tx_irq(int irq, void *dev_id) 234 { 235 struct prueth_tx_chn *tx_chn = dev_id; 236 237 disable_irq_nosync(irq); 238 napi_schedule(&tx_chn->napi_tx); 239 240 return IRQ_HANDLED; 241 } 242 243 int prueth_ndev_add_tx_napi(struct prueth_emac *emac) 244 { 245 struct prueth *prueth = emac->prueth; 246 int i, ret; 247 248 for (i = 0; i < emac->tx_ch_num; i++) { 249 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 250 251 netif_napi_add_tx(emac->ndev, &tx_chn->napi_tx, emac_napi_tx_poll); 252 hrtimer_init(&tx_chn->tx_hrtimer, CLOCK_MONOTONIC, 253 HRTIMER_MODE_REL_PINNED); 254 tx_chn->tx_hrtimer.function = &emac_tx_timer_callback; 255 ret = request_irq(tx_chn->irq, prueth_tx_irq, 256 IRQF_TRIGGER_HIGH, tx_chn->name, 257 tx_chn); 258 if (ret) { 259 netif_napi_del(&tx_chn->napi_tx); 260 dev_err(prueth->dev, "unable to request TX IRQ %d\n", 261 tx_chn->irq); 262 goto fail; 263 } 264 } 265 266 return 0; 267 fail: 268 prueth_ndev_del_tx_napi(emac, i); 269 return ret; 270 } 271 EXPORT_SYMBOL_GPL(prueth_ndev_add_tx_napi); 272 273 int prueth_init_tx_chns(struct prueth_emac *emac) 274 { 275 static const struct k3_ring_cfg ring_cfg = { 276 .elm_size = K3_RINGACC_RING_ELSIZE_8, 277 .mode = K3_RINGACC_RING_MODE_RING, 278 .flags = 0, 279 .size = PRUETH_MAX_TX_DESC, 280 }; 281 struct k3_udma_glue_tx_channel_cfg tx_cfg; 282 struct device *dev = emac->prueth->dev; 283 struct net_device *ndev = emac->ndev; 284 int ret, slice, i; 285 u32 hdesc_size; 286 287 slice = prueth_emac_slice(emac); 288 if (slice < 0) 289 return slice; 290 291 init_completion(&emac->tdown_complete); 292 293 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 294 PRUETH_NAV_SW_DATA_SIZE); 295 memset(&tx_cfg, 0, sizeof(tx_cfg)); 296 tx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 297 tx_cfg.tx_cfg = ring_cfg; 298 tx_cfg.txcq_cfg = ring_cfg; 299 300 for (i = 0; i < emac->tx_ch_num; i++) { 301 struct prueth_tx_chn *tx_chn = &emac->tx_chns[i]; 302 303 /* To differentiate channels for SLICE0 vs SLICE1 */ 304 snprintf(tx_chn->name, sizeof(tx_chn->name), 305 "tx%d-%d", slice, i); 306 307 tx_chn->emac = emac; 308 tx_chn->id = i; 309 tx_chn->descs_num = PRUETH_MAX_TX_DESC; 310 311 tx_chn->tx_chn = 312 k3_udma_glue_request_tx_chn(dev, tx_chn->name, 313 &tx_cfg); 314 if (IS_ERR(tx_chn->tx_chn)) { 315 ret = PTR_ERR(tx_chn->tx_chn); 316 tx_chn->tx_chn = NULL; 317 netdev_err(ndev, 318 "Failed to request tx dma ch: %d\n", ret); 319 goto fail; 320 } 321 322 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 323 tx_chn->desc_pool = 324 k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 325 tx_chn->descs_num, 326 hdesc_size, 327 tx_chn->name); 328 if (IS_ERR(tx_chn->desc_pool)) { 329 ret = PTR_ERR(tx_chn->desc_pool); 330 tx_chn->desc_pool = NULL; 331 netdev_err(ndev, "Failed to create tx pool: %d\n", ret); 332 goto fail; 333 } 334 335 ret = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 336 if (ret < 0) { 337 netdev_err(ndev, "failed to get tx irq\n"); 338 goto fail; 339 } 340 tx_chn->irq = ret; 341 342 snprintf(tx_chn->name, sizeof(tx_chn->name), "%s-tx%d", 343 dev_name(dev), tx_chn->id); 344 } 345 346 return 0; 347 348 fail: 349 prueth_cleanup_tx_chns(emac); 350 return ret; 351 } 352 EXPORT_SYMBOL_GPL(prueth_init_tx_chns); 353 354 int prueth_init_rx_chns(struct prueth_emac *emac, 355 struct prueth_rx_chn *rx_chn, 356 char *name, u32 max_rflows, 357 u32 max_desc_num) 358 { 359 struct k3_udma_glue_rx_channel_cfg rx_cfg; 360 struct device *dev = emac->prueth->dev; 361 struct net_device *ndev = emac->ndev; 362 u32 fdqring_id, hdesc_size; 363 int i, ret = 0, slice; 364 int flow_id_base; 365 366 slice = prueth_emac_slice(emac); 367 if (slice < 0) 368 return slice; 369 370 /* To differentiate channels for SLICE0 vs SLICE1 */ 371 snprintf(rx_chn->name, sizeof(rx_chn->name), "%s%d", name, slice); 372 373 hdesc_size = cppi5_hdesc_calc_size(true, PRUETH_NAV_PS_DATA_SIZE, 374 PRUETH_NAV_SW_DATA_SIZE); 375 memset(&rx_cfg, 0, sizeof(rx_cfg)); 376 rx_cfg.swdata_size = PRUETH_NAV_SW_DATA_SIZE; 377 rx_cfg.flow_id_num = max_rflows; 378 rx_cfg.flow_id_base = -1; /* udmax will auto select flow id base */ 379 380 /* init all flows */ 381 rx_chn->dev = dev; 382 rx_chn->descs_num = max_desc_num; 383 384 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, rx_chn->name, 385 &rx_cfg); 386 if (IS_ERR(rx_chn->rx_chn)) { 387 ret = PTR_ERR(rx_chn->rx_chn); 388 rx_chn->rx_chn = NULL; 389 netdev_err(ndev, "Failed to request rx dma ch: %d\n", ret); 390 goto fail; 391 } 392 393 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 394 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 395 rx_chn->descs_num, 396 hdesc_size, 397 rx_chn->name); 398 if (IS_ERR(rx_chn->desc_pool)) { 399 ret = PTR_ERR(rx_chn->desc_pool); 400 rx_chn->desc_pool = NULL; 401 netdev_err(ndev, "Failed to create rx pool: %d\n", ret); 402 goto fail; 403 } 404 405 flow_id_base = k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 406 if (emac->is_sr1 && !strcmp(name, "rxmgm")) { 407 emac->rx_mgm_flow_id_base = flow_id_base; 408 netdev_dbg(ndev, "mgm flow id base = %d\n", flow_id_base); 409 } else { 410 emac->rx_flow_id_base = flow_id_base; 411 netdev_dbg(ndev, "flow id base = %d\n", flow_id_base); 412 } 413 414 fdqring_id = K3_RINGACC_RING_ID_ANY; 415 for (i = 0; i < rx_cfg.flow_id_num; i++) { 416 struct k3_ring_cfg rxring_cfg = { 417 .elm_size = K3_RINGACC_RING_ELSIZE_8, 418 .mode = K3_RINGACC_RING_MODE_RING, 419 .flags = 0, 420 }; 421 struct k3_ring_cfg fdqring_cfg = { 422 .elm_size = K3_RINGACC_RING_ELSIZE_8, 423 .flags = K3_RINGACC_RING_SHARED, 424 }; 425 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 426 .rx_cfg = rxring_cfg, 427 .rxfdq_cfg = fdqring_cfg, 428 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 429 .src_tag_lo_sel = 430 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 431 }; 432 433 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 434 rx_flow_cfg.rx_cfg.size = max_desc_num; 435 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 436 rx_flow_cfg.rxfdq_cfg.mode = emac->prueth->pdata.fdqring_mode; 437 438 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 439 i, &rx_flow_cfg); 440 if (ret) { 441 netdev_err(ndev, "Failed to init rx flow%d %d\n", 442 i, ret); 443 goto fail; 444 } 445 if (!i) 446 fdqring_id = k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 447 i); 448 ret = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 449 if (ret < 0) { 450 netdev_err(ndev, "Failed to get rx dma irq"); 451 goto fail; 452 } 453 rx_chn->irq[i] = ret; 454 } 455 456 return 0; 457 458 fail: 459 prueth_cleanup_rx_chns(emac, rx_chn, max_rflows); 460 return ret; 461 } 462 EXPORT_SYMBOL_GPL(prueth_init_rx_chns); 463 464 int prueth_dma_rx_push(struct prueth_emac *emac, 465 struct sk_buff *skb, 466 struct prueth_rx_chn *rx_chn) 467 { 468 struct net_device *ndev = emac->ndev; 469 struct cppi5_host_desc_t *desc_rx; 470 u32 pkt_len = skb_tailroom(skb); 471 dma_addr_t desc_dma; 472 dma_addr_t buf_dma; 473 void **swdata; 474 475 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 476 if (!desc_rx) { 477 netdev_err(ndev, "rx push: failed to allocate descriptor\n"); 478 return -ENOMEM; 479 } 480 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 481 482 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, DMA_FROM_DEVICE); 483 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 484 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 485 netdev_err(ndev, "rx push: failed to map rx pkt buffer\n"); 486 return -EINVAL; 487 } 488 489 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 490 PRUETH_NAV_PS_DATA_SIZE); 491 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 492 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 493 494 swdata = cppi5_hdesc_get_swdata(desc_rx); 495 *swdata = skb; 496 497 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, 498 desc_rx, desc_dma); 499 } 500 EXPORT_SYMBOL_GPL(prueth_dma_rx_push); 501 502 u64 icssg_ts_to_ns(u32 hi_sw, u32 hi, u32 lo, u32 cycle_time_ns) 503 { 504 u32 iepcount_lo, iepcount_hi, hi_rollover_count; 505 u64 ns; 506 507 iepcount_lo = lo & GENMASK(19, 0); 508 iepcount_hi = (hi & GENMASK(11, 0)) << 12 | lo >> 20; 509 hi_rollover_count = hi >> 11; 510 511 ns = ((u64)hi_rollover_count) << 23 | (iepcount_hi + hi_sw); 512 ns = ns * cycle_time_ns + iepcount_lo; 513 514 return ns; 515 } 516 EXPORT_SYMBOL_GPL(icssg_ts_to_ns); 517 518 void emac_rx_timestamp(struct prueth_emac *emac, 519 struct sk_buff *skb, u32 *psdata) 520 { 521 struct skb_shared_hwtstamps *ssh; 522 u64 ns; 523 524 if (emac->is_sr1) { 525 ns = (u64)psdata[1] << 32 | psdata[0]; 526 } else { 527 u32 hi_sw = readl(emac->prueth->shram.va + 528 TIMESYNC_FW_WC_COUNT_HI_SW_OFFSET_OFFSET); 529 ns = icssg_ts_to_ns(hi_sw, psdata[1], psdata[0], 530 IEP_DEFAULT_CYCLE_TIME_NS); 531 } 532 533 ssh = skb_hwtstamps(skb); 534 memset(ssh, 0, sizeof(*ssh)); 535 ssh->hwtstamp = ns_to_ktime(ns); 536 } 537 538 static int emac_rx_packet(struct prueth_emac *emac, u32 flow_id) 539 { 540 struct prueth_rx_chn *rx_chn = &emac->rx_chns; 541 u32 buf_dma_len, pkt_len, port_id = 0; 542 struct net_device *ndev = emac->ndev; 543 struct cppi5_host_desc_t *desc_rx; 544 struct sk_buff *skb, *new_skb; 545 dma_addr_t desc_dma, buf_dma; 546 void **swdata; 547 u32 *psdata; 548 int ret; 549 550 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_id, &desc_dma); 551 if (ret) { 552 if (ret != -ENODATA) 553 netdev_err(ndev, "rx pop: failed: %d\n", ret); 554 return ret; 555 } 556 557 if (cppi5_desc_is_tdcm(desc_dma)) /* Teardown ? */ 558 return 0; 559 560 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 561 562 swdata = cppi5_hdesc_get_swdata(desc_rx); 563 skb = *swdata; 564 565 psdata = cppi5_hdesc_get_psdata(desc_rx); 566 /* RX HW timestamp */ 567 if (emac->rx_ts_enabled) 568 emac_rx_timestamp(emac, skb, psdata); 569 570 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 571 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 572 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 573 /* firmware adds 4 CRC bytes, strip them */ 574 pkt_len -= 4; 575 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 576 577 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 578 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 579 580 skb->dev = ndev; 581 new_skb = netdev_alloc_skb_ip_align(ndev, PRUETH_MAX_PKT_SIZE); 582 /* if allocation fails we drop the packet but push the 583 * descriptor back to the ring with old skb to prevent a stall 584 */ 585 if (!new_skb) { 586 ndev->stats.rx_dropped++; 587 new_skb = skb; 588 } else { 589 /* send the filled skb up the n/w stack */ 590 skb_put(skb, pkt_len); 591 if (emac->prueth->is_switch_mode) 592 skb->offload_fwd_mark = emac->offload_fwd_mark; 593 skb->protocol = eth_type_trans(skb, ndev); 594 napi_gro_receive(&emac->napi_rx, skb); 595 ndev->stats.rx_bytes += pkt_len; 596 ndev->stats.rx_packets++; 597 } 598 599 /* queue another RX DMA */ 600 ret = prueth_dma_rx_push(emac, new_skb, &emac->rx_chns); 601 if (WARN_ON(ret < 0)) { 602 dev_kfree_skb_any(new_skb); 603 ndev->stats.rx_errors++; 604 ndev->stats.rx_dropped++; 605 } 606 607 return ret; 608 } 609 610 static void prueth_rx_cleanup(void *data, dma_addr_t desc_dma) 611 { 612 struct prueth_rx_chn *rx_chn = data; 613 struct cppi5_host_desc_t *desc_rx; 614 struct sk_buff *skb; 615 dma_addr_t buf_dma; 616 u32 buf_dma_len; 617 void **swdata; 618 619 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 620 swdata = cppi5_hdesc_get_swdata(desc_rx); 621 skb = *swdata; 622 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 623 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 624 625 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, 626 DMA_FROM_DEVICE); 627 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 628 629 dev_kfree_skb_any(skb); 630 } 631 632 static int prueth_tx_ts_cookie_get(struct prueth_emac *emac) 633 { 634 int i; 635 636 /* search and get the next free slot */ 637 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 638 if (!emac->tx_ts_skb[i]) { 639 emac->tx_ts_skb[i] = ERR_PTR(-EBUSY); /* reserve slot */ 640 return i; 641 } 642 } 643 644 return -EBUSY; 645 } 646 647 /** 648 * icssg_ndo_start_xmit - EMAC Transmit function 649 * @skb: SKB pointer 650 * @ndev: EMAC network adapter 651 * 652 * Called by the system to transmit a packet - we queue the packet in 653 * EMAC hardware transmit queue 654 * Doesn't wait for completion we'll check for TX completion in 655 * emac_tx_complete_packets(). 656 * 657 * Return: enum netdev_tx 658 */ 659 enum netdev_tx icssg_ndo_start_xmit(struct sk_buff *skb, struct net_device *ndev) 660 { 661 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 662 struct prueth_emac *emac = netdev_priv(ndev); 663 struct netdev_queue *netif_txq; 664 struct prueth_tx_chn *tx_chn; 665 dma_addr_t desc_dma, buf_dma; 666 int i, ret = 0, q_idx; 667 bool in_tx_ts = 0; 668 int tx_ts_cookie; 669 void **swdata; 670 u32 pkt_len; 671 u32 *epib; 672 673 pkt_len = skb_headlen(skb); 674 q_idx = skb_get_queue_mapping(skb); 675 676 tx_chn = &emac->tx_chns[q_idx]; 677 netif_txq = netdev_get_tx_queue(ndev, q_idx); 678 679 /* Map the linear buffer */ 680 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, DMA_TO_DEVICE); 681 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 682 netdev_err(ndev, "tx: failed to map skb buffer\n"); 683 ret = NETDEV_TX_OK; 684 goto drop_free_skb; 685 } 686 687 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 688 if (!first_desc) { 689 netdev_dbg(ndev, "tx: failed to allocate descriptor\n"); 690 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, DMA_TO_DEVICE); 691 goto drop_stop_q_busy; 692 } 693 694 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 695 PRUETH_NAV_PS_DATA_SIZE); 696 cppi5_hdesc_set_pkttype(first_desc, 0); 697 epib = first_desc->epib; 698 epib[0] = 0; 699 epib[1] = 0; 700 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 701 emac->tx_ts_enabled) { 702 tx_ts_cookie = prueth_tx_ts_cookie_get(emac); 703 if (tx_ts_cookie >= 0) { 704 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 705 /* Request TX timestamp */ 706 epib[0] = (u32)tx_ts_cookie; 707 epib[1] = 0x80000000; /* TX TS request */ 708 emac->tx_ts_skb[tx_ts_cookie] = skb_get(skb); 709 in_tx_ts = 1; 710 } 711 } 712 713 /* set dst tag to indicate internal qid at the firmware which is at 714 * bit8..bit15. bit0..bit7 indicates port num for directed 715 * packets in case of switch mode operation 716 */ 717 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, (emac->port_id | (q_idx << 8))); 718 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 719 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 720 swdata = cppi5_hdesc_get_swdata(first_desc); 721 *swdata = skb; 722 723 /* Handle the case where skb is fragmented in pages */ 724 cur_desc = first_desc; 725 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 726 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 727 u32 frag_size = skb_frag_size(frag); 728 729 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 730 if (!next_desc) { 731 netdev_err(ndev, 732 "tx: failed to allocate frag. descriptor\n"); 733 goto free_desc_stop_q_busy_cleanup_tx_ts; 734 } 735 736 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 737 DMA_TO_DEVICE); 738 if (dma_mapping_error(tx_chn->dma_dev, buf_dma)) { 739 netdev_err(ndev, "tx: Failed to map skb page\n"); 740 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 741 ret = NETDEV_TX_OK; 742 goto cleanup_tx_ts; 743 } 744 745 cppi5_hdesc_reset_hbdesc(next_desc); 746 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 747 cppi5_hdesc_attach_buf(next_desc, 748 buf_dma, frag_size, buf_dma, frag_size); 749 750 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 751 next_desc); 752 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 753 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 754 755 pkt_len += frag_size; 756 cur_desc = next_desc; 757 } 758 WARN_ON_ONCE(pkt_len != skb->len); 759 760 /* report bql before sending packet */ 761 netdev_tx_sent_queue(netif_txq, pkt_len); 762 763 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 764 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 765 /* cppi5_desc_dump(first_desc, 64); */ 766 767 skb_tx_timestamp(skb); /* SW timestamp if SKBTX_IN_PROGRESS not set */ 768 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 769 if (ret) { 770 netdev_err(ndev, "tx: push failed: %d\n", ret); 771 goto drop_free_descs; 772 } 773 774 if (in_tx_ts) 775 atomic_inc(&emac->tx_ts_pending); 776 777 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 778 netif_tx_stop_queue(netif_txq); 779 /* Barrier, so that stop_queue visible to other cpus */ 780 smp_mb__after_atomic(); 781 782 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 783 MAX_SKB_FRAGS) 784 netif_tx_wake_queue(netif_txq); 785 } 786 787 return NETDEV_TX_OK; 788 789 cleanup_tx_ts: 790 if (in_tx_ts) { 791 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 792 emac->tx_ts_skb[tx_ts_cookie] = NULL; 793 } 794 795 drop_free_descs: 796 prueth_xmit_free(tx_chn, first_desc); 797 798 drop_free_skb: 799 dev_kfree_skb_any(skb); 800 801 /* error */ 802 ndev->stats.tx_dropped++; 803 netdev_err(ndev, "tx: error: %d\n", ret); 804 805 return ret; 806 807 free_desc_stop_q_busy_cleanup_tx_ts: 808 if (in_tx_ts) { 809 dev_kfree_skb_any(emac->tx_ts_skb[tx_ts_cookie]); 810 emac->tx_ts_skb[tx_ts_cookie] = NULL; 811 } 812 prueth_xmit_free(tx_chn, first_desc); 813 814 drop_stop_q_busy: 815 netif_tx_stop_queue(netif_txq); 816 return NETDEV_TX_BUSY; 817 } 818 EXPORT_SYMBOL_GPL(icssg_ndo_start_xmit); 819 820 static void prueth_tx_cleanup(void *data, dma_addr_t desc_dma) 821 { 822 struct prueth_tx_chn *tx_chn = data; 823 struct cppi5_host_desc_t *desc_tx; 824 struct sk_buff *skb; 825 void **swdata; 826 827 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 828 swdata = cppi5_hdesc_get_swdata(desc_tx); 829 skb = *(swdata); 830 prueth_xmit_free(tx_chn, desc_tx); 831 832 dev_kfree_skb_any(skb); 833 } 834 835 irqreturn_t prueth_rx_irq(int irq, void *dev_id) 836 { 837 struct prueth_emac *emac = dev_id; 838 839 disable_irq_nosync(irq); 840 napi_schedule(&emac->napi_rx); 841 842 return IRQ_HANDLED; 843 } 844 EXPORT_SYMBOL_GPL(prueth_rx_irq); 845 846 void prueth_emac_stop(struct prueth_emac *emac) 847 { 848 struct prueth *prueth = emac->prueth; 849 int slice; 850 851 switch (emac->port_id) { 852 case PRUETH_PORT_MII0: 853 slice = ICSS_SLICE0; 854 break; 855 case PRUETH_PORT_MII1: 856 slice = ICSS_SLICE1; 857 break; 858 default: 859 netdev_err(emac->ndev, "invalid port\n"); 860 return; 861 } 862 863 emac->fw_running = 0; 864 if (!emac->is_sr1) 865 rproc_shutdown(prueth->txpru[slice]); 866 rproc_shutdown(prueth->rtu[slice]); 867 rproc_shutdown(prueth->pru[slice]); 868 } 869 EXPORT_SYMBOL_GPL(prueth_emac_stop); 870 871 void prueth_cleanup_tx_ts(struct prueth_emac *emac) 872 { 873 int i; 874 875 for (i = 0; i < PRUETH_MAX_TX_TS_REQUESTS; i++) { 876 if (emac->tx_ts_skb[i]) { 877 dev_kfree_skb_any(emac->tx_ts_skb[i]); 878 emac->tx_ts_skb[i] = NULL; 879 } 880 } 881 } 882 EXPORT_SYMBOL_GPL(prueth_cleanup_tx_ts); 883 884 int icssg_napi_rx_poll(struct napi_struct *napi_rx, int budget) 885 { 886 struct prueth_emac *emac = prueth_napi_to_emac(napi_rx); 887 int rx_flow = emac->is_sr1 ? 888 PRUETH_RX_FLOW_DATA_SR1 : PRUETH_RX_FLOW_DATA; 889 int flow = emac->is_sr1 ? 890 PRUETH_MAX_RX_FLOWS_SR1 : PRUETH_MAX_RX_FLOWS; 891 int num_rx = 0; 892 int cur_budget; 893 int ret; 894 895 while (flow--) { 896 cur_budget = budget - num_rx; 897 898 while (cur_budget--) { 899 ret = emac_rx_packet(emac, flow); 900 if (ret) 901 break; 902 num_rx++; 903 } 904 905 if (num_rx >= budget) 906 break; 907 } 908 909 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 910 if (unlikely(emac->rx_pace_timeout_ns)) { 911 hrtimer_start(&emac->rx_hrtimer, 912 ns_to_ktime(emac->rx_pace_timeout_ns), 913 HRTIMER_MODE_REL_PINNED); 914 } else { 915 enable_irq(emac->rx_chns.irq[rx_flow]); 916 } 917 } 918 919 return num_rx; 920 } 921 EXPORT_SYMBOL_GPL(icssg_napi_rx_poll); 922 923 int prueth_prepare_rx_chan(struct prueth_emac *emac, 924 struct prueth_rx_chn *chn, 925 int buf_size) 926 { 927 struct sk_buff *skb; 928 int i, ret; 929 930 for (i = 0; i < chn->descs_num; i++) { 931 skb = __netdev_alloc_skb_ip_align(NULL, buf_size, GFP_KERNEL); 932 if (!skb) 933 return -ENOMEM; 934 935 ret = prueth_dma_rx_push(emac, skb, chn); 936 if (ret < 0) { 937 netdev_err(emac->ndev, 938 "cannot submit skb for rx chan %s ret %d\n", 939 chn->name, ret); 940 kfree_skb(skb); 941 return ret; 942 } 943 } 944 945 return 0; 946 } 947 EXPORT_SYMBOL_GPL(prueth_prepare_rx_chan); 948 949 void prueth_reset_tx_chan(struct prueth_emac *emac, int ch_num, 950 bool free_skb) 951 { 952 int i; 953 954 for (i = 0; i < ch_num; i++) { 955 if (free_skb) 956 k3_udma_glue_reset_tx_chn(emac->tx_chns[i].tx_chn, 957 &emac->tx_chns[i], 958 prueth_tx_cleanup); 959 k3_udma_glue_disable_tx_chn(emac->tx_chns[i].tx_chn); 960 } 961 } 962 EXPORT_SYMBOL_GPL(prueth_reset_tx_chan); 963 964 void prueth_reset_rx_chan(struct prueth_rx_chn *chn, 965 int num_flows, bool disable) 966 { 967 int i; 968 969 for (i = 0; i < num_flows; i++) 970 k3_udma_glue_reset_rx_chn(chn->rx_chn, i, chn, 971 prueth_rx_cleanup, !!i); 972 if (disable) 973 k3_udma_glue_disable_rx_chn(chn->rx_chn); 974 } 975 EXPORT_SYMBOL_GPL(prueth_reset_rx_chan); 976 977 void icssg_ndo_tx_timeout(struct net_device *ndev, unsigned int txqueue) 978 { 979 ndev->stats.tx_errors++; 980 } 981 EXPORT_SYMBOL_GPL(icssg_ndo_tx_timeout); 982 983 static int emac_set_ts_config(struct net_device *ndev, struct ifreq *ifr) 984 { 985 struct prueth_emac *emac = netdev_priv(ndev); 986 struct hwtstamp_config config; 987 988 if (copy_from_user(&config, ifr->ifr_data, sizeof(config))) 989 return -EFAULT; 990 991 switch (config.tx_type) { 992 case HWTSTAMP_TX_OFF: 993 emac->tx_ts_enabled = 0; 994 break; 995 case HWTSTAMP_TX_ON: 996 emac->tx_ts_enabled = 1; 997 break; 998 default: 999 return -ERANGE; 1000 } 1001 1002 switch (config.rx_filter) { 1003 case HWTSTAMP_FILTER_NONE: 1004 emac->rx_ts_enabled = 0; 1005 break; 1006 case HWTSTAMP_FILTER_ALL: 1007 case HWTSTAMP_FILTER_SOME: 1008 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1009 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1010 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1011 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1012 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1013 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1014 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1015 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1016 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1017 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1018 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1019 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1020 case HWTSTAMP_FILTER_NTP_ALL: 1021 emac->rx_ts_enabled = 1; 1022 config.rx_filter = HWTSTAMP_FILTER_ALL; 1023 break; 1024 default: 1025 return -ERANGE; 1026 } 1027 1028 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1029 -EFAULT : 0; 1030 } 1031 1032 static int emac_get_ts_config(struct net_device *ndev, struct ifreq *ifr) 1033 { 1034 struct prueth_emac *emac = netdev_priv(ndev); 1035 struct hwtstamp_config config; 1036 1037 config.flags = 0; 1038 config.tx_type = emac->tx_ts_enabled ? HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1039 config.rx_filter = emac->rx_ts_enabled ? HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1040 1041 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? 1042 -EFAULT : 0; 1043 } 1044 1045 int icssg_ndo_ioctl(struct net_device *ndev, struct ifreq *ifr, int cmd) 1046 { 1047 switch (cmd) { 1048 case SIOCGHWTSTAMP: 1049 return emac_get_ts_config(ndev, ifr); 1050 case SIOCSHWTSTAMP: 1051 return emac_set_ts_config(ndev, ifr); 1052 default: 1053 break; 1054 } 1055 1056 return phy_do_ioctl(ndev, ifr, cmd); 1057 } 1058 EXPORT_SYMBOL_GPL(icssg_ndo_ioctl); 1059 1060 void icssg_ndo_get_stats64(struct net_device *ndev, 1061 struct rtnl_link_stats64 *stats) 1062 { 1063 struct prueth_emac *emac = netdev_priv(ndev); 1064 1065 emac_update_hardware_stats(emac); 1066 1067 stats->rx_packets = emac_get_stat_by_name(emac, "rx_packets"); 1068 stats->rx_bytes = emac_get_stat_by_name(emac, "rx_bytes"); 1069 stats->tx_packets = emac_get_stat_by_name(emac, "tx_packets"); 1070 stats->tx_bytes = emac_get_stat_by_name(emac, "tx_bytes"); 1071 stats->rx_crc_errors = emac_get_stat_by_name(emac, "rx_crc_errors"); 1072 stats->rx_over_errors = emac_get_stat_by_name(emac, "rx_over_errors"); 1073 stats->multicast = emac_get_stat_by_name(emac, "rx_multicast_frames"); 1074 1075 stats->rx_errors = ndev->stats.rx_errors; 1076 stats->rx_dropped = ndev->stats.rx_dropped; 1077 stats->tx_errors = ndev->stats.tx_errors; 1078 stats->tx_dropped = ndev->stats.tx_dropped; 1079 } 1080 EXPORT_SYMBOL_GPL(icssg_ndo_get_stats64); 1081 1082 int icssg_ndo_get_phys_port_name(struct net_device *ndev, char *name, 1083 size_t len) 1084 { 1085 struct prueth_emac *emac = netdev_priv(ndev); 1086 int ret; 1087 1088 ret = snprintf(name, len, "p%d", emac->port_id); 1089 if (ret >= len) 1090 return -EINVAL; 1091 1092 return 0; 1093 } 1094 EXPORT_SYMBOL_GPL(icssg_ndo_get_phys_port_name); 1095 1096 /* get emac_port corresponding to eth_node name */ 1097 int prueth_node_port(struct device_node *eth_node) 1098 { 1099 u32 port_id; 1100 int ret; 1101 1102 ret = of_property_read_u32(eth_node, "reg", &port_id); 1103 if (ret) 1104 return ret; 1105 1106 if (port_id == 0) 1107 return PRUETH_PORT_MII0; 1108 else if (port_id == 1) 1109 return PRUETH_PORT_MII1; 1110 else 1111 return PRUETH_PORT_INVALID; 1112 } 1113 EXPORT_SYMBOL_GPL(prueth_node_port); 1114 1115 /* get MAC instance corresponding to eth_node name */ 1116 int prueth_node_mac(struct device_node *eth_node) 1117 { 1118 u32 port_id; 1119 int ret; 1120 1121 ret = of_property_read_u32(eth_node, "reg", &port_id); 1122 if (ret) 1123 return ret; 1124 1125 if (port_id == 0) 1126 return PRUETH_MAC0; 1127 else if (port_id == 1) 1128 return PRUETH_MAC1; 1129 else 1130 return PRUETH_MAC_INVALID; 1131 } 1132 EXPORT_SYMBOL_GPL(prueth_node_mac); 1133 1134 void prueth_netdev_exit(struct prueth *prueth, 1135 struct device_node *eth_node) 1136 { 1137 struct prueth_emac *emac; 1138 enum prueth_mac mac; 1139 1140 mac = prueth_node_mac(eth_node); 1141 if (mac == PRUETH_MAC_INVALID) 1142 return; 1143 1144 emac = prueth->emac[mac]; 1145 if (!emac) 1146 return; 1147 1148 if (of_phy_is_fixed_link(emac->phy_node)) 1149 of_phy_deregister_fixed_link(emac->phy_node); 1150 1151 netif_napi_del(&emac->napi_rx); 1152 1153 pruss_release_mem_region(prueth->pruss, &emac->dram); 1154 destroy_workqueue(emac->cmd_wq); 1155 free_netdev(emac->ndev); 1156 prueth->emac[mac] = NULL; 1157 } 1158 EXPORT_SYMBOL_GPL(prueth_netdev_exit); 1159 1160 int prueth_get_cores(struct prueth *prueth, int slice, bool is_sr1) 1161 { 1162 struct device *dev = prueth->dev; 1163 enum pruss_pru_id pruss_id; 1164 struct device_node *np; 1165 int idx = -1, ret; 1166 1167 np = dev->of_node; 1168 1169 switch (slice) { 1170 case ICSS_SLICE0: 1171 idx = 0; 1172 break; 1173 case ICSS_SLICE1: 1174 idx = is_sr1 ? 2 : 3; 1175 break; 1176 default: 1177 return -EINVAL; 1178 } 1179 1180 prueth->pru[slice] = pru_rproc_get(np, idx, &pruss_id); 1181 if (IS_ERR(prueth->pru[slice])) { 1182 ret = PTR_ERR(prueth->pru[slice]); 1183 prueth->pru[slice] = NULL; 1184 return dev_err_probe(dev, ret, "unable to get PRU%d\n", slice); 1185 } 1186 prueth->pru_id[slice] = pruss_id; 1187 1188 idx++; 1189 prueth->rtu[slice] = pru_rproc_get(np, idx, NULL); 1190 if (IS_ERR(prueth->rtu[slice])) { 1191 ret = PTR_ERR(prueth->rtu[slice]); 1192 prueth->rtu[slice] = NULL; 1193 return dev_err_probe(dev, ret, "unable to get RTU%d\n", slice); 1194 } 1195 1196 if (is_sr1) 1197 return 0; 1198 1199 idx++; 1200 prueth->txpru[slice] = pru_rproc_get(np, idx, NULL); 1201 if (IS_ERR(prueth->txpru[slice])) { 1202 ret = PTR_ERR(prueth->txpru[slice]); 1203 prueth->txpru[slice] = NULL; 1204 return dev_err_probe(dev, ret, "unable to get TX_PRU%d\n", slice); 1205 } 1206 1207 return 0; 1208 } 1209 EXPORT_SYMBOL_GPL(prueth_get_cores); 1210 1211 void prueth_put_cores(struct prueth *prueth, int slice) 1212 { 1213 if (prueth->txpru[slice]) 1214 pru_rproc_put(prueth->txpru[slice]); 1215 1216 if (prueth->rtu[slice]) 1217 pru_rproc_put(prueth->rtu[slice]); 1218 1219 if (prueth->pru[slice]) 1220 pru_rproc_put(prueth->pru[slice]); 1221 } 1222 EXPORT_SYMBOL_GPL(prueth_put_cores); 1223 1224 #ifdef CONFIG_PM_SLEEP 1225 static int prueth_suspend(struct device *dev) 1226 { 1227 struct prueth *prueth = dev_get_drvdata(dev); 1228 struct net_device *ndev; 1229 int i, ret; 1230 1231 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1232 ndev = prueth->registered_netdevs[i]; 1233 1234 if (!ndev) 1235 continue; 1236 1237 if (netif_running(ndev)) { 1238 netif_device_detach(ndev); 1239 ret = ndev->netdev_ops->ndo_stop(ndev); 1240 if (ret < 0) { 1241 netdev_err(ndev, "failed to stop: %d", ret); 1242 return ret; 1243 } 1244 } 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int prueth_resume(struct device *dev) 1251 { 1252 struct prueth *prueth = dev_get_drvdata(dev); 1253 struct net_device *ndev; 1254 int i, ret; 1255 1256 for (i = 0; i < PRUETH_NUM_MACS; i++) { 1257 ndev = prueth->registered_netdevs[i]; 1258 1259 if (!ndev) 1260 continue; 1261 1262 if (netif_running(ndev)) { 1263 ret = ndev->netdev_ops->ndo_open(ndev); 1264 if (ret < 0) { 1265 netdev_err(ndev, "failed to start: %d", ret); 1266 return ret; 1267 } 1268 netif_device_attach(ndev); 1269 } 1270 } 1271 1272 return 0; 1273 } 1274 #endif /* CONFIG_PM_SLEEP */ 1275 1276 const struct dev_pm_ops prueth_dev_pm_ops = { 1277 SET_SYSTEM_SLEEP_PM_OPS(prueth_suspend, prueth_resume) 1278 }; 1279 EXPORT_SYMBOL_GPL(prueth_dev_pm_ops); 1280 1281 MODULE_AUTHOR("Roger Quadros <rogerq@ti.com>"); 1282 MODULE_AUTHOR("Md Danish Anwar <danishanwar@ti.com>"); 1283 MODULE_DESCRIPTION("PRUSS ICSSG Ethernet Driver Common Module"); 1284 MODULE_LICENSE("GPL"); 1285