1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * DaVinci MDIO Module driver 4 * 5 * Copyright (C) 2010 Texas Instruments. 6 * 7 * Shamelessly ripped out of davinci_emac.c, original copyrights follow: 8 * 9 * Copyright (C) 2009 Texas Instruments. 10 * 11 */ 12 #include <linux/module.h> 13 #include <linux/kernel.h> 14 #include <linux/platform_device.h> 15 #include <linux/delay.h> 16 #include <linux/sched.h> 17 #include <linux/slab.h> 18 #include <linux/phy.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/davinci_emac.h> 25 #include <linux/of.h> 26 #include <linux/of_mdio.h> 27 #include <linux/pinctrl/consumer.h> 28 #include <linux/mdio-bitbang.h> 29 #include <linux/sys_soc.h> 30 31 /* 32 * This timeout definition is a worst-case ultra defensive measure against 33 * unexpected controller lock ups. Ideally, we should never ever hit this 34 * scenario in practice. 35 */ 36 #define MDIO_TIMEOUT 100 /* msecs */ 37 38 #define PHY_REG_MASK 0x1f 39 #define PHY_ID_MASK 0x1f 40 41 #define DEF_OUT_FREQ 2200000 /* 2.2 MHz */ 42 43 struct davinci_mdio_of_param { 44 int autosuspend_delay_ms; 45 bool manual_mode; 46 }; 47 48 struct davinci_mdio_regs { 49 u32 version; 50 u32 control; 51 #define CONTROL_IDLE BIT(31) 52 #define CONTROL_ENABLE BIT(30) 53 #define CONTROL_MAX_DIV (0xffff) 54 #define CONTROL_CLKDIV GENMASK(15, 0) 55 56 #define MDIO_MAN_MDCLK_O BIT(2) 57 #define MDIO_MAN_OE BIT(1) 58 #define MDIO_MAN_PIN BIT(0) 59 #define MDIO_MANUALMODE BIT(31) 60 61 #define MDIO_PIN 0 62 63 64 u32 alive; 65 u32 link; 66 u32 linkintraw; 67 u32 linkintmasked; 68 u32 __reserved_0[2]; 69 u32 userintraw; 70 u32 userintmasked; 71 u32 userintmaskset; 72 u32 userintmaskclr; 73 u32 manualif; 74 u32 poll; 75 u32 __reserved_1[18]; 76 77 struct { 78 u32 access; 79 #define USERACCESS_GO BIT(31) 80 #define USERACCESS_WRITE BIT(30) 81 #define USERACCESS_ACK BIT(29) 82 #define USERACCESS_READ (0) 83 #define USERACCESS_DATA (0xffff) 84 85 u32 physel; 86 } user[]; 87 }; 88 89 static const struct mdio_platform_data default_pdata = { 90 .bus_freq = DEF_OUT_FREQ, 91 }; 92 93 struct davinci_mdio_data { 94 struct mdio_platform_data pdata; 95 struct mdiobb_ctrl bb_ctrl; 96 struct davinci_mdio_regs __iomem *regs; 97 struct clk *clk; 98 struct device *dev; 99 struct mii_bus *bus; 100 bool active_in_suspend; 101 unsigned long access_time; /* jiffies */ 102 /* Indicates that driver shouldn't modify phy_mask in case 103 * if MDIO bus is registered from DT. 104 */ 105 bool skip_scan; 106 u32 clk_div; 107 bool manual_mode; 108 }; 109 110 static void davinci_mdio_init_clk(struct davinci_mdio_data *data) 111 { 112 u32 mdio_in, div, mdio_out_khz, access_time; 113 114 mdio_in = clk_get_rate(data->clk); 115 div = (mdio_in / data->pdata.bus_freq) - 1; 116 if (div > CONTROL_MAX_DIV) 117 div = CONTROL_MAX_DIV; 118 119 data->clk_div = div; 120 /* 121 * One mdio transaction consists of: 122 * 32 bits of preamble 123 * 32 bits of transferred data 124 * 24 bits of bus yield (not needed unless shared?) 125 */ 126 mdio_out_khz = mdio_in / (1000 * (div + 1)); 127 access_time = (88 * 1000) / mdio_out_khz; 128 129 /* 130 * In the worst case, we could be kicking off a user-access immediately 131 * after the mdio bus scan state-machine triggered its own read. If 132 * so, our request could get deferred by one access cycle. We 133 * defensively allow for 4 access cycles. 134 */ 135 data->access_time = usecs_to_jiffies(access_time * 4); 136 if (!data->access_time) 137 data->access_time = 1; 138 } 139 140 static void davinci_mdio_enable(struct davinci_mdio_data *data) 141 { 142 /* set enable and clock divider */ 143 writel(data->clk_div | CONTROL_ENABLE, &data->regs->control); 144 } 145 146 static void davinci_mdio_disable(struct davinci_mdio_data *data) 147 { 148 u32 reg; 149 150 /* Disable MDIO state machine */ 151 reg = readl(&data->regs->control); 152 153 reg &= ~CONTROL_CLKDIV; 154 reg |= data->clk_div; 155 156 reg &= ~CONTROL_ENABLE; 157 writel(reg, &data->regs->control); 158 } 159 160 static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data) 161 { 162 u32 reg; 163 /* set manual mode */ 164 reg = readl(&data->regs->poll); 165 reg |= MDIO_MANUALMODE; 166 writel(reg, &data->regs->poll); 167 } 168 169 static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level) 170 { 171 struct davinci_mdio_data *data; 172 u32 reg; 173 174 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); 175 reg = readl(&data->regs->manualif); 176 177 if (level) 178 reg |= MDIO_MAN_MDCLK_O; 179 else 180 reg &= ~MDIO_MAN_MDCLK_O; 181 182 writel(reg, &data->regs->manualif); 183 } 184 185 static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output) 186 { 187 struct davinci_mdio_data *data; 188 u32 reg; 189 190 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); 191 reg = readl(&data->regs->manualif); 192 193 if (output) 194 reg |= MDIO_MAN_OE; 195 else 196 reg &= ~MDIO_MAN_OE; 197 198 writel(reg, &data->regs->manualif); 199 } 200 201 static void davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value) 202 { 203 struct davinci_mdio_data *data; 204 u32 reg; 205 206 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); 207 reg = readl(&data->regs->manualif); 208 209 if (value) 210 reg |= MDIO_MAN_PIN; 211 else 212 reg &= ~MDIO_MAN_PIN; 213 214 writel(reg, &data->regs->manualif); 215 } 216 217 static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl) 218 { 219 struct davinci_mdio_data *data; 220 unsigned long reg; 221 222 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); 223 reg = readl(&data->regs->manualif); 224 return test_bit(MDIO_PIN, ®); 225 } 226 227 static int davinci_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg) 228 { 229 int ret; 230 231 ret = pm_runtime_resume_and_get(bus->parent); 232 if (ret < 0) 233 return ret; 234 235 ret = mdiobb_read_c22(bus, phy, reg); 236 237 pm_runtime_put_autosuspend(bus->parent); 238 239 return ret; 240 } 241 242 static int davinci_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg, 243 u16 val) 244 { 245 int ret; 246 247 ret = pm_runtime_resume_and_get(bus->parent); 248 if (ret < 0) 249 return ret; 250 251 ret = mdiobb_write_c22(bus, phy, reg, val); 252 253 pm_runtime_put_autosuspend(bus->parent); 254 255 return ret; 256 } 257 258 static int davinci_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad, 259 int reg) 260 { 261 int ret; 262 263 ret = pm_runtime_resume_and_get(bus->parent); 264 if (ret < 0) 265 return ret; 266 267 ret = mdiobb_read_c45(bus, phy, devad, reg); 268 269 pm_runtime_put_autosuspend(bus->parent); 270 271 return ret; 272 } 273 274 static int davinci_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad, 275 int reg, u16 val) 276 { 277 int ret; 278 279 ret = pm_runtime_resume_and_get(bus->parent); 280 if (ret < 0) 281 return ret; 282 283 ret = mdiobb_write_c45(bus, phy, devad, reg, val); 284 285 pm_runtime_put_autosuspend(bus->parent); 286 287 return ret; 288 } 289 290 static int davinci_mdio_common_reset(struct davinci_mdio_data *data) 291 { 292 u32 phy_mask, ver; 293 int ret; 294 295 ret = pm_runtime_resume_and_get(data->dev); 296 if (ret < 0) 297 return ret; 298 299 if (data->manual_mode) { 300 davinci_mdio_disable(data); 301 davinci_mdio_enable_manual_mode(data); 302 } 303 304 /* wait for scan logic to settle */ 305 msleep(PHY_MAX_ADDR * data->access_time); 306 307 /* dump hardware version info */ 308 ver = readl(&data->regs->version); 309 dev_info(data->dev, 310 "davinci mdio revision %d.%d, bus freq %ld\n", 311 (ver >> 8) & 0xff, ver & 0xff, 312 data->pdata.bus_freq); 313 314 if (data->skip_scan) 315 goto done; 316 317 /* get phy mask from the alive register */ 318 phy_mask = readl(&data->regs->alive); 319 if (phy_mask) { 320 /* restrict mdio bus to live phys only */ 321 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask); 322 phy_mask = ~phy_mask; 323 } else { 324 /* desperately scan all phys */ 325 dev_warn(data->dev, "no live phy, scanning all\n"); 326 phy_mask = 0; 327 } 328 data->bus->phy_mask = phy_mask; 329 330 done: 331 pm_runtime_put_autosuspend(data->dev); 332 333 return 0; 334 } 335 336 static int davinci_mdio_reset(struct mii_bus *bus) 337 { 338 struct davinci_mdio_data *data = bus->priv; 339 340 return davinci_mdio_common_reset(data); 341 } 342 343 static int davinci_mdiobb_reset(struct mii_bus *bus) 344 { 345 struct mdiobb_ctrl *ctrl = bus->priv; 346 struct davinci_mdio_data *data; 347 348 data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl); 349 350 return davinci_mdio_common_reset(data); 351 } 352 353 /* wait until hardware is ready for another user access */ 354 static inline int wait_for_user_access(struct davinci_mdio_data *data) 355 { 356 struct davinci_mdio_regs __iomem *regs = data->regs; 357 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT); 358 u32 reg; 359 360 while (time_after(timeout, jiffies)) { 361 reg = readl(®s->user[0].access); 362 if ((reg & USERACCESS_GO) == 0) 363 return 0; 364 365 reg = readl(®s->control); 366 if ((reg & CONTROL_IDLE) == 0) { 367 usleep_range(100, 200); 368 continue; 369 } 370 371 /* 372 * An emac soft_reset may have clobbered the mdio controller's 373 * state machine. We need to reset and retry the current 374 * operation 375 */ 376 dev_warn(data->dev, "resetting idled controller\n"); 377 davinci_mdio_enable(data); 378 return -EAGAIN; 379 } 380 381 reg = readl(®s->user[0].access); 382 if ((reg & USERACCESS_GO) == 0) 383 return 0; 384 385 dev_err(data->dev, "timed out waiting for user access\n"); 386 return -ETIMEDOUT; 387 } 388 389 /* wait until hardware state machine is idle */ 390 static inline int wait_for_idle(struct davinci_mdio_data *data) 391 { 392 struct davinci_mdio_regs __iomem *regs = data->regs; 393 u32 val, ret; 394 395 ret = readl_poll_timeout(®s->control, val, val & CONTROL_IDLE, 396 0, MDIO_TIMEOUT * 1000); 397 if (ret) 398 dev_err(data->dev, "timed out waiting for idle\n"); 399 400 return ret; 401 } 402 403 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg) 404 { 405 struct davinci_mdio_data *data = bus->priv; 406 u32 reg; 407 int ret; 408 409 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 410 return -EINVAL; 411 412 ret = pm_runtime_resume_and_get(data->dev); 413 if (ret < 0) 414 return ret; 415 416 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) | 417 (phy_id << 16)); 418 419 while (1) { 420 ret = wait_for_user_access(data); 421 if (ret == -EAGAIN) 422 continue; 423 if (ret < 0) 424 break; 425 426 writel(reg, &data->regs->user[0].access); 427 428 ret = wait_for_user_access(data); 429 if (ret == -EAGAIN) 430 continue; 431 if (ret < 0) 432 break; 433 434 reg = readl(&data->regs->user[0].access); 435 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO; 436 break; 437 } 438 439 pm_runtime_put_autosuspend(data->dev); 440 return ret; 441 } 442 443 static int davinci_mdio_write(struct mii_bus *bus, int phy_id, 444 int phy_reg, u16 phy_data) 445 { 446 struct davinci_mdio_data *data = bus->priv; 447 u32 reg; 448 int ret; 449 450 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK) 451 return -EINVAL; 452 453 ret = pm_runtime_resume_and_get(data->dev); 454 if (ret < 0) 455 return ret; 456 457 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) | 458 (phy_id << 16) | (phy_data & USERACCESS_DATA)); 459 460 while (1) { 461 ret = wait_for_user_access(data); 462 if (ret == -EAGAIN) 463 continue; 464 if (ret < 0) 465 break; 466 467 writel(reg, &data->regs->user[0].access); 468 469 ret = wait_for_user_access(data); 470 if (ret == -EAGAIN) 471 continue; 472 break; 473 } 474 475 pm_runtime_put_autosuspend(data->dev); 476 477 return ret; 478 } 479 480 static int davinci_mdio_probe_dt(struct mdio_platform_data *data, 481 struct platform_device *pdev) 482 { 483 struct device_node *node = pdev->dev.of_node; 484 u32 prop; 485 486 if (!node) 487 return -EINVAL; 488 489 if (of_property_read_u32(node, "bus_freq", &prop)) { 490 dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n"); 491 return -EINVAL; 492 } 493 data->bus_freq = prop; 494 495 return 0; 496 } 497 498 struct k3_mdio_soc_data { 499 bool manual_mode; 500 }; 501 502 static const struct k3_mdio_soc_data am65_mdio_soc_data = { 503 .manual_mode = true, 504 }; 505 506 static const struct soc_device_attribute k3_mdio_socinfo[] = { 507 { .family = "AM62X", .data = &am65_mdio_soc_data }, 508 { .family = "AM64X", .data = &am65_mdio_soc_data }, 509 { .family = "AM65X", .data = &am65_mdio_soc_data }, 510 { .family = "J7200", .data = &am65_mdio_soc_data }, 511 { .family = "J721E", .data = &am65_mdio_soc_data }, 512 { .family = "J721S2", .data = &am65_mdio_soc_data }, 513 { /* sentinel */ }, 514 }; 515 516 #if IS_ENABLED(CONFIG_OF) 517 static const struct davinci_mdio_of_param of_cpsw_mdio_data = { 518 .autosuspend_delay_ms = 100, 519 }; 520 521 static const struct of_device_id davinci_mdio_of_mtable[] = { 522 { .compatible = "ti,davinci_mdio", }, 523 { .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data}, 524 { /* sentinel */ }, 525 }; 526 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable); 527 #endif 528 529 static const struct mdiobb_ops davinci_mdiobb_ops = { 530 .owner = THIS_MODULE, 531 .set_mdc = davinci_set_mdc, 532 .set_mdio_dir = davinci_set_mdio_dir, 533 .set_mdio_data = davinci_set_mdio_data, 534 .get_mdio_data = davinci_get_mdio_data, 535 }; 536 537 static int davinci_mdio_probe(struct platform_device *pdev) 538 { 539 struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev); 540 struct device *dev = &pdev->dev; 541 struct davinci_mdio_data *data; 542 struct resource *res; 543 struct phy_device *phy; 544 int autosuspend_delay_ms = -1; 545 int ret; 546 547 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); 548 if (!data) 549 return -ENOMEM; 550 551 data->manual_mode = false; 552 data->bb_ctrl.ops = &davinci_mdiobb_ops; 553 554 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 555 const struct soc_device_attribute *soc_match_data; 556 557 soc_match_data = soc_device_match(k3_mdio_socinfo); 558 if (soc_match_data && soc_match_data->data) { 559 const struct k3_mdio_soc_data *socdata = 560 soc_match_data->data; 561 562 data->manual_mode = socdata->manual_mode; 563 } 564 } 565 566 if (data->manual_mode) 567 data->bus = alloc_mdio_bitbang(&data->bb_ctrl); 568 else 569 data->bus = devm_mdiobus_alloc(dev); 570 571 if (!data->bus) { 572 dev_err(dev, "failed to alloc mii bus\n"); 573 return -ENOMEM; 574 } 575 576 if (IS_ENABLED(CONFIG_OF) && dev->of_node) { 577 const struct davinci_mdio_of_param *of_mdio_data; 578 579 ret = davinci_mdio_probe_dt(&data->pdata, pdev); 580 if (ret) 581 return ret; 582 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name); 583 584 of_mdio_data = of_device_get_match_data(&pdev->dev); 585 if (of_mdio_data) { 586 autosuspend_delay_ms = 587 of_mdio_data->autosuspend_delay_ms; 588 } 589 } else { 590 data->pdata = pdata ? (*pdata) : default_pdata; 591 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x", 592 pdev->name, pdev->id); 593 } 594 595 data->bus->name = dev_name(dev); 596 597 if (data->manual_mode) { 598 data->bus->read = davinci_mdiobb_read_c22; 599 data->bus->write = davinci_mdiobb_write_c22; 600 data->bus->read_c45 = davinci_mdiobb_read_c45; 601 data->bus->write_c45 = davinci_mdiobb_write_c45; 602 data->bus->reset = davinci_mdiobb_reset; 603 604 dev_info(dev, "Configuring MDIO in manual mode\n"); 605 } else { 606 data->bus->read = davinci_mdio_read; 607 data->bus->write = davinci_mdio_write; 608 data->bus->reset = davinci_mdio_reset; 609 data->bus->priv = data; 610 } 611 data->bus->parent = dev; 612 613 data->clk = devm_clk_get(dev, "fck"); 614 if (IS_ERR(data->clk)) { 615 dev_err(dev, "failed to get device clock\n"); 616 return PTR_ERR(data->clk); 617 } 618 619 dev_set_drvdata(dev, data); 620 data->dev = dev; 621 622 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 623 if (!res) 624 return -EINVAL; 625 data->regs = devm_ioremap(dev, res->start, resource_size(res)); 626 if (!data->regs) 627 return -ENOMEM; 628 629 davinci_mdio_init_clk(data); 630 631 pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms); 632 pm_runtime_use_autosuspend(&pdev->dev); 633 pm_runtime_enable(&pdev->dev); 634 635 /* register the mii bus 636 * Create PHYs from DT only in case if PHY child nodes are explicitly 637 * defined to support backward compatibility with DTs which assume that 638 * Davinci MDIO will always scan the bus for PHYs detection. 639 */ 640 if (dev->of_node && of_get_child_count(dev->of_node)) 641 data->skip_scan = true; 642 643 ret = of_mdiobus_register(data->bus, dev->of_node); 644 if (ret) 645 goto bail_out; 646 647 /* scan and dump the bus */ 648 mdiobus_for_each_phy(data->bus, phy) 649 dev_info(dev, "phy[%d]: device %s, driver %s\n", 650 phy->mdio.addr, phydev_name(phy), 651 phy->drv ? phy->drv->name : "unknown"); 652 653 return 0; 654 655 bail_out: 656 pm_runtime_dont_use_autosuspend(&pdev->dev); 657 pm_runtime_disable(&pdev->dev); 658 return ret; 659 } 660 661 static void davinci_mdio_remove(struct platform_device *pdev) 662 { 663 struct davinci_mdio_data *data = platform_get_drvdata(pdev); 664 665 if (data->bus) { 666 mdiobus_unregister(data->bus); 667 668 if (data->manual_mode) 669 free_mdio_bitbang(data->bus); 670 } 671 672 pm_runtime_dont_use_autosuspend(&pdev->dev); 673 pm_runtime_disable(&pdev->dev); 674 } 675 676 #ifdef CONFIG_PM 677 static int davinci_mdio_runtime_suspend(struct device *dev) 678 { 679 struct davinci_mdio_data *data = dev_get_drvdata(dev); 680 u32 ctrl; 681 682 /* shutdown the scan state machine */ 683 ctrl = readl(&data->regs->control); 684 ctrl &= ~CONTROL_ENABLE; 685 writel(ctrl, &data->regs->control); 686 687 if (!data->manual_mode) 688 wait_for_idle(data); 689 690 return 0; 691 } 692 693 static int davinci_mdio_runtime_resume(struct device *dev) 694 { 695 struct davinci_mdio_data *data = dev_get_drvdata(dev); 696 697 if (data->manual_mode) { 698 davinci_mdio_disable(data); 699 davinci_mdio_enable_manual_mode(data); 700 } else { 701 davinci_mdio_enable(data); 702 } 703 return 0; 704 } 705 #endif 706 707 #ifdef CONFIG_PM_SLEEP 708 static int davinci_mdio_suspend(struct device *dev) 709 { 710 struct davinci_mdio_data *data = dev_get_drvdata(dev); 711 int ret = 0; 712 713 data->active_in_suspend = !pm_runtime_status_suspended(dev); 714 if (data->active_in_suspend) 715 ret = pm_runtime_force_suspend(dev); 716 if (ret < 0) 717 return ret; 718 719 /* Select sleep pin state */ 720 pinctrl_pm_select_sleep_state(dev); 721 722 return 0; 723 } 724 725 static int davinci_mdio_resume(struct device *dev) 726 { 727 struct davinci_mdio_data *data = dev_get_drvdata(dev); 728 729 /* Select default pin state */ 730 pinctrl_pm_select_default_state(dev); 731 732 if (data->active_in_suspend) 733 pm_runtime_force_resume(dev); 734 735 return 0; 736 } 737 #endif 738 739 static const struct dev_pm_ops davinci_mdio_pm_ops = { 740 SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend, 741 davinci_mdio_runtime_resume, NULL) 742 SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume) 743 }; 744 745 static struct platform_driver davinci_mdio_driver = { 746 .driver = { 747 .name = "davinci_mdio", 748 .pm = &davinci_mdio_pm_ops, 749 .of_match_table = of_match_ptr(davinci_mdio_of_mtable), 750 }, 751 .probe = davinci_mdio_probe, 752 .remove = davinci_mdio_remove, 753 }; 754 755 static int __init davinci_mdio_init(void) 756 { 757 return platform_driver_register(&davinci_mdio_driver); 758 } 759 device_initcall(davinci_mdio_init); 760 761 static void __exit davinci_mdio_exit(void) 762 { 763 platform_driver_unregister(&davinci_mdio_driver); 764 } 765 module_exit(davinci_mdio_exit); 766 767 MODULE_LICENSE("GPL"); 768 MODULE_DESCRIPTION("DaVinci MDIO driver"); 769