xref: /linux/drivers/net/ethernet/ti/davinci_mdio.c (revision 0526b56cbc3c489642bd6a5fe4b718dea7ef0ee8)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * DaVinci MDIO Module driver
4  *
5  * Copyright (C) 2010 Texas Instruments.
6  *
7  * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
8  *
9  * Copyright (C) 2009 Texas Instruments.
10  *
11  */
12 #include <linux/module.h>
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/delay.h>
16 #include <linux/sched.h>
17 #include <linux/slab.h>
18 #include <linux/phy.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22 #include <linux/iopoll.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/davinci_emac.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/pinctrl/consumer.h>
29 #include <linux/mdio-bitbang.h>
30 #include <linux/sys_soc.h>
31 
32 /*
33  * This timeout definition is a worst-case ultra defensive measure against
34  * unexpected controller lock ups.  Ideally, we should never ever hit this
35  * scenario in practice.
36  */
37 #define MDIO_TIMEOUT		100 /* msecs */
38 
39 #define PHY_REG_MASK		0x1f
40 #define PHY_ID_MASK		0x1f
41 
42 #define DEF_OUT_FREQ		2200000		/* 2.2 MHz */
43 
44 struct davinci_mdio_of_param {
45 	int autosuspend_delay_ms;
46 	bool manual_mode;
47 };
48 
49 struct davinci_mdio_regs {
50 	u32	version;
51 	u32	control;
52 #define CONTROL_IDLE		BIT(31)
53 #define CONTROL_ENABLE		BIT(30)
54 #define CONTROL_MAX_DIV		(0xffff)
55 #define CONTROL_CLKDIV		GENMASK(15, 0)
56 
57 #define MDIO_MAN_MDCLK_O	BIT(2)
58 #define MDIO_MAN_OE		BIT(1)
59 #define MDIO_MAN_PIN		BIT(0)
60 #define MDIO_MANUALMODE		BIT(31)
61 
62 #define MDIO_PIN               0
63 
64 
65 	u32	alive;
66 	u32	link;
67 	u32	linkintraw;
68 	u32	linkintmasked;
69 	u32	__reserved_0[2];
70 	u32	userintraw;
71 	u32	userintmasked;
72 	u32	userintmaskset;
73 	u32	userintmaskclr;
74 	u32	manualif;
75 	u32	poll;
76 	u32	__reserved_1[18];
77 
78 	struct {
79 		u32	access;
80 #define USERACCESS_GO		BIT(31)
81 #define USERACCESS_WRITE	BIT(30)
82 #define USERACCESS_ACK		BIT(29)
83 #define USERACCESS_READ		(0)
84 #define USERACCESS_DATA		(0xffff)
85 
86 		u32	physel;
87 	}	user[];
88 };
89 
90 static const struct mdio_platform_data default_pdata = {
91 	.bus_freq = DEF_OUT_FREQ,
92 };
93 
94 struct davinci_mdio_data {
95 	struct mdio_platform_data pdata;
96 	struct mdiobb_ctrl bb_ctrl;
97 	struct davinci_mdio_regs __iomem *regs;
98 	struct clk	*clk;
99 	struct device	*dev;
100 	struct mii_bus	*bus;
101 	bool            active_in_suspend;
102 	unsigned long	access_time; /* jiffies */
103 	/* Indicates that driver shouldn't modify phy_mask in case
104 	 * if MDIO bus is registered from DT.
105 	 */
106 	bool		skip_scan;
107 	u32		clk_div;
108 	bool		manual_mode;
109 };
110 
111 static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
112 {
113 	u32 mdio_in, div, mdio_out_khz, access_time;
114 
115 	mdio_in = clk_get_rate(data->clk);
116 	div = (mdio_in / data->pdata.bus_freq) - 1;
117 	if (div > CONTROL_MAX_DIV)
118 		div = CONTROL_MAX_DIV;
119 
120 	data->clk_div = div;
121 	/*
122 	 * One mdio transaction consists of:
123 	 *	32 bits of preamble
124 	 *	32 bits of transferred data
125 	 *	24 bits of bus yield (not needed unless shared?)
126 	 */
127 	mdio_out_khz = mdio_in / (1000 * (div + 1));
128 	access_time  = (88 * 1000) / mdio_out_khz;
129 
130 	/*
131 	 * In the worst case, we could be kicking off a user-access immediately
132 	 * after the mdio bus scan state-machine triggered its own read.  If
133 	 * so, our request could get deferred by one access cycle.  We
134 	 * defensively allow for 4 access cycles.
135 	 */
136 	data->access_time = usecs_to_jiffies(access_time * 4);
137 	if (!data->access_time)
138 		data->access_time = 1;
139 }
140 
141 static void davinci_mdio_enable(struct davinci_mdio_data *data)
142 {
143 	/* set enable and clock divider */
144 	writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
145 }
146 
147 static void davinci_mdio_disable(struct davinci_mdio_data *data)
148 {
149 	u32 reg;
150 
151 	/* Disable MDIO state machine */
152 	reg = readl(&data->regs->control);
153 
154 	reg &= ~CONTROL_CLKDIV;
155 	reg |= data->clk_div;
156 
157 	reg &= ~CONTROL_ENABLE;
158 	writel(reg, &data->regs->control);
159 }
160 
161 static void davinci_mdio_enable_manual_mode(struct davinci_mdio_data *data)
162 {
163 	u32 reg;
164 	/* set manual mode */
165 	reg = readl(&data->regs->poll);
166 	reg |= MDIO_MANUALMODE;
167 	writel(reg, &data->regs->poll);
168 }
169 
170 static void davinci_set_mdc(struct mdiobb_ctrl *ctrl, int level)
171 {
172 	struct davinci_mdio_data *data;
173 	u32 reg;
174 
175 	data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
176 	reg = readl(&data->regs->manualif);
177 
178 	if (level)
179 		reg |= MDIO_MAN_MDCLK_O;
180 	else
181 		reg &= ~MDIO_MAN_MDCLK_O;
182 
183 	writel(reg, &data->regs->manualif);
184 }
185 
186 static void davinci_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
187 {
188 	struct davinci_mdio_data *data;
189 	u32 reg;
190 
191 	data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
192 	reg = readl(&data->regs->manualif);
193 
194 	if (output)
195 		reg |= MDIO_MAN_OE;
196 	else
197 		reg &= ~MDIO_MAN_OE;
198 
199 	writel(reg, &data->regs->manualif);
200 }
201 
202 static void  davinci_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
203 {
204 	struct davinci_mdio_data *data;
205 	u32 reg;
206 
207 	data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
208 	reg = readl(&data->regs->manualif);
209 
210 	if (value)
211 		reg |= MDIO_MAN_PIN;
212 	else
213 		reg &= ~MDIO_MAN_PIN;
214 
215 	writel(reg, &data->regs->manualif);
216 }
217 
218 static int davinci_get_mdio_data(struct mdiobb_ctrl *ctrl)
219 {
220 	struct davinci_mdio_data *data;
221 	unsigned long reg;
222 
223 	data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
224 	reg = readl(&data->regs->manualif);
225 	return test_bit(MDIO_PIN, &reg);
226 }
227 
228 static int davinci_mdiobb_read_c22(struct mii_bus *bus, int phy, int reg)
229 {
230 	int ret;
231 
232 	ret = pm_runtime_resume_and_get(bus->parent);
233 	if (ret < 0)
234 		return ret;
235 
236 	ret = mdiobb_read_c22(bus, phy, reg);
237 
238 	pm_runtime_mark_last_busy(bus->parent);
239 	pm_runtime_put_autosuspend(bus->parent);
240 
241 	return ret;
242 }
243 
244 static int davinci_mdiobb_write_c22(struct mii_bus *bus, int phy, int reg,
245 				    u16 val)
246 {
247 	int ret;
248 
249 	ret = pm_runtime_resume_and_get(bus->parent);
250 	if (ret < 0)
251 		return ret;
252 
253 	ret = mdiobb_write_c22(bus, phy, reg, val);
254 
255 	pm_runtime_mark_last_busy(bus->parent);
256 	pm_runtime_put_autosuspend(bus->parent);
257 
258 	return ret;
259 }
260 
261 static int davinci_mdiobb_read_c45(struct mii_bus *bus, int phy, int devad,
262 				   int reg)
263 {
264 	int ret;
265 
266 	ret = pm_runtime_resume_and_get(bus->parent);
267 	if (ret < 0)
268 		return ret;
269 
270 	ret = mdiobb_read_c45(bus, phy, devad, reg);
271 
272 	pm_runtime_mark_last_busy(bus->parent);
273 	pm_runtime_put_autosuspend(bus->parent);
274 
275 	return ret;
276 }
277 
278 static int davinci_mdiobb_write_c45(struct mii_bus *bus, int phy, int devad,
279 				    int reg, u16 val)
280 {
281 	int ret;
282 
283 	ret = pm_runtime_resume_and_get(bus->parent);
284 	if (ret < 0)
285 		return ret;
286 
287 	ret = mdiobb_write_c45(bus, phy, devad, reg, val);
288 
289 	pm_runtime_mark_last_busy(bus->parent);
290 	pm_runtime_put_autosuspend(bus->parent);
291 
292 	return ret;
293 }
294 
295 static int davinci_mdio_common_reset(struct davinci_mdio_data *data)
296 {
297 	u32 phy_mask, ver;
298 	int ret;
299 
300 	ret = pm_runtime_resume_and_get(data->dev);
301 	if (ret < 0)
302 		return ret;
303 
304 	if (data->manual_mode) {
305 		davinci_mdio_disable(data);
306 		davinci_mdio_enable_manual_mode(data);
307 	}
308 
309 	/* wait for scan logic to settle */
310 	msleep(PHY_MAX_ADDR * data->access_time);
311 
312 	/* dump hardware version info */
313 	ver = readl(&data->regs->version);
314 	dev_info(data->dev,
315 		 "davinci mdio revision %d.%d, bus freq %ld\n",
316 		 (ver >> 8) & 0xff, ver & 0xff,
317 		 data->pdata.bus_freq);
318 
319 	if (data->skip_scan)
320 		goto done;
321 
322 	/* get phy mask from the alive register */
323 	phy_mask = readl(&data->regs->alive);
324 	if (phy_mask) {
325 		/* restrict mdio bus to live phys only */
326 		dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
327 		phy_mask = ~phy_mask;
328 	} else {
329 		/* desperately scan all phys */
330 		dev_warn(data->dev, "no live phy, scanning all\n");
331 		phy_mask = 0;
332 	}
333 	data->bus->phy_mask = phy_mask;
334 
335 done:
336 	pm_runtime_mark_last_busy(data->dev);
337 	pm_runtime_put_autosuspend(data->dev);
338 
339 	return 0;
340 }
341 
342 static int davinci_mdio_reset(struct mii_bus *bus)
343 {
344 	struct davinci_mdio_data *data = bus->priv;
345 
346 	return davinci_mdio_common_reset(data);
347 }
348 
349 static int davinci_mdiobb_reset(struct mii_bus *bus)
350 {
351 	struct mdiobb_ctrl *ctrl = bus->priv;
352 	struct davinci_mdio_data *data;
353 
354 	data = container_of(ctrl, struct davinci_mdio_data, bb_ctrl);
355 
356 	return davinci_mdio_common_reset(data);
357 }
358 
359 /* wait until hardware is ready for another user access */
360 static inline int wait_for_user_access(struct davinci_mdio_data *data)
361 {
362 	struct davinci_mdio_regs __iomem *regs = data->regs;
363 	unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
364 	u32 reg;
365 
366 	while (time_after(timeout, jiffies)) {
367 		reg = readl(&regs->user[0].access);
368 		if ((reg & USERACCESS_GO) == 0)
369 			return 0;
370 
371 		reg = readl(&regs->control);
372 		if ((reg & CONTROL_IDLE) == 0) {
373 			usleep_range(100, 200);
374 			continue;
375 		}
376 
377 		/*
378 		 * An emac soft_reset may have clobbered the mdio controller's
379 		 * state machine.  We need to reset and retry the current
380 		 * operation
381 		 */
382 		dev_warn(data->dev, "resetting idled controller\n");
383 		davinci_mdio_enable(data);
384 		return -EAGAIN;
385 	}
386 
387 	reg = readl(&regs->user[0].access);
388 	if ((reg & USERACCESS_GO) == 0)
389 		return 0;
390 
391 	dev_err(data->dev, "timed out waiting for user access\n");
392 	return -ETIMEDOUT;
393 }
394 
395 /* wait until hardware state machine is idle */
396 static inline int wait_for_idle(struct davinci_mdio_data *data)
397 {
398 	struct davinci_mdio_regs __iomem *regs = data->regs;
399 	u32 val, ret;
400 
401 	ret = readl_poll_timeout(&regs->control, val, val & CONTROL_IDLE,
402 				 0, MDIO_TIMEOUT * 1000);
403 	if (ret)
404 		dev_err(data->dev, "timed out waiting for idle\n");
405 
406 	return ret;
407 }
408 
409 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
410 {
411 	struct davinci_mdio_data *data = bus->priv;
412 	u32 reg;
413 	int ret;
414 
415 	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
416 		return -EINVAL;
417 
418 	ret = pm_runtime_resume_and_get(data->dev);
419 	if (ret < 0)
420 		return ret;
421 
422 	reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
423 	       (phy_id << 16));
424 
425 	while (1) {
426 		ret = wait_for_user_access(data);
427 		if (ret == -EAGAIN)
428 			continue;
429 		if (ret < 0)
430 			break;
431 
432 		writel(reg, &data->regs->user[0].access);
433 
434 		ret = wait_for_user_access(data);
435 		if (ret == -EAGAIN)
436 			continue;
437 		if (ret < 0)
438 			break;
439 
440 		reg = readl(&data->regs->user[0].access);
441 		ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
442 		break;
443 	}
444 
445 	pm_runtime_mark_last_busy(data->dev);
446 	pm_runtime_put_autosuspend(data->dev);
447 	return ret;
448 }
449 
450 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
451 			      int phy_reg, u16 phy_data)
452 {
453 	struct davinci_mdio_data *data = bus->priv;
454 	u32 reg;
455 	int ret;
456 
457 	if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
458 		return -EINVAL;
459 
460 	ret = pm_runtime_resume_and_get(data->dev);
461 	if (ret < 0)
462 		return ret;
463 
464 	reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
465 		   (phy_id << 16) | (phy_data & USERACCESS_DATA));
466 
467 	while (1) {
468 		ret = wait_for_user_access(data);
469 		if (ret == -EAGAIN)
470 			continue;
471 		if (ret < 0)
472 			break;
473 
474 		writel(reg, &data->regs->user[0].access);
475 
476 		ret = wait_for_user_access(data);
477 		if (ret == -EAGAIN)
478 			continue;
479 		break;
480 	}
481 
482 	pm_runtime_mark_last_busy(data->dev);
483 	pm_runtime_put_autosuspend(data->dev);
484 
485 	return ret;
486 }
487 
488 static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
489 			 struct platform_device *pdev)
490 {
491 	struct device_node *node = pdev->dev.of_node;
492 	u32 prop;
493 
494 	if (!node)
495 		return -EINVAL;
496 
497 	if (of_property_read_u32(node, "bus_freq", &prop)) {
498 		dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
499 		return -EINVAL;
500 	}
501 	data->bus_freq = prop;
502 
503 	return 0;
504 }
505 
506 struct k3_mdio_soc_data {
507 	bool manual_mode;
508 };
509 
510 static const struct k3_mdio_soc_data am65_mdio_soc_data = {
511 	.manual_mode = true,
512 };
513 
514 static const struct soc_device_attribute k3_mdio_socinfo[] = {
515 	{ .family = "AM62X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
516 	{ .family = "AM64X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
517 	{ .family = "AM64X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
518 	{ .family = "AM65X", .revision = "SR1.0", .data = &am65_mdio_soc_data },
519 	{ .family = "AM65X", .revision = "SR2.0", .data = &am65_mdio_soc_data },
520 	{ .family = "J7200", .revision = "SR1.0", .data = &am65_mdio_soc_data },
521 	{ .family = "J7200", .revision = "SR2.0", .data = &am65_mdio_soc_data },
522 	{ .family = "J721E", .revision = "SR1.0", .data = &am65_mdio_soc_data },
523 	{ .family = "J721E", .revision = "SR2.0", .data = &am65_mdio_soc_data },
524 	{ .family = "J721S2", .revision = "SR1.0", .data = &am65_mdio_soc_data},
525 	{ /* sentinel */ },
526 };
527 
528 #if IS_ENABLED(CONFIG_OF)
529 static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
530 	.autosuspend_delay_ms = 100,
531 };
532 
533 static const struct of_device_id davinci_mdio_of_mtable[] = {
534 	{ .compatible = "ti,davinci_mdio", },
535 	{ .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
536 	{ /* sentinel */ },
537 };
538 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
539 #endif
540 
541 static const struct mdiobb_ops davinci_mdiobb_ops = {
542 	.owner = THIS_MODULE,
543 	.set_mdc = davinci_set_mdc,
544 	.set_mdio_dir = davinci_set_mdio_dir,
545 	.set_mdio_data = davinci_set_mdio_data,
546 	.get_mdio_data = davinci_get_mdio_data,
547 };
548 
549 static int davinci_mdio_probe(struct platform_device *pdev)
550 {
551 	struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
552 	struct device *dev = &pdev->dev;
553 	struct davinci_mdio_data *data;
554 	struct resource *res;
555 	struct phy_device *phy;
556 	int ret, addr;
557 	int autosuspend_delay_ms = -1;
558 
559 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
560 	if (!data)
561 		return -ENOMEM;
562 
563 	data->manual_mode = false;
564 	data->bb_ctrl.ops = &davinci_mdiobb_ops;
565 
566 	if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
567 		const struct soc_device_attribute *soc_match_data;
568 
569 		soc_match_data = soc_device_match(k3_mdio_socinfo);
570 		if (soc_match_data && soc_match_data->data) {
571 			const struct k3_mdio_soc_data *socdata =
572 						soc_match_data->data;
573 
574 			data->manual_mode = socdata->manual_mode;
575 		}
576 	}
577 
578 	if (data->manual_mode)
579 		data->bus = alloc_mdio_bitbang(&data->bb_ctrl);
580 	else
581 		data->bus = devm_mdiobus_alloc(dev);
582 
583 	if (!data->bus) {
584 		dev_err(dev, "failed to alloc mii bus\n");
585 		return -ENOMEM;
586 	}
587 
588 	if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
589 		const struct davinci_mdio_of_param *of_mdio_data;
590 
591 		ret = davinci_mdio_probe_dt(&data->pdata, pdev);
592 		if (ret)
593 			return ret;
594 		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
595 
596 		of_mdio_data = of_device_get_match_data(&pdev->dev);
597 		if (of_mdio_data) {
598 			autosuspend_delay_ms =
599 					of_mdio_data->autosuspend_delay_ms;
600 		}
601 	} else {
602 		data->pdata = pdata ? (*pdata) : default_pdata;
603 		snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
604 			 pdev->name, pdev->id);
605 	}
606 
607 	data->bus->name		= dev_name(dev);
608 
609 	if (data->manual_mode) {
610 		data->bus->read		= davinci_mdiobb_read_c22;
611 		data->bus->write	= davinci_mdiobb_write_c22;
612 		data->bus->read_c45	= davinci_mdiobb_read_c45;
613 		data->bus->write_c45	= davinci_mdiobb_write_c45;
614 		data->bus->reset	= davinci_mdiobb_reset;
615 
616 		dev_info(dev, "Configuring MDIO in manual mode\n");
617 	} else {
618 		data->bus->read		= davinci_mdio_read;
619 		data->bus->write	= davinci_mdio_write;
620 		data->bus->reset	= davinci_mdio_reset;
621 		data->bus->priv		= data;
622 	}
623 	data->bus->parent	= dev;
624 
625 	data->clk = devm_clk_get(dev, "fck");
626 	if (IS_ERR(data->clk)) {
627 		dev_err(dev, "failed to get device clock\n");
628 		return PTR_ERR(data->clk);
629 	}
630 
631 	dev_set_drvdata(dev, data);
632 	data->dev = dev;
633 
634 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
635 	if (!res)
636 		return -EINVAL;
637 	data->regs = devm_ioremap(dev, res->start, resource_size(res));
638 	if (!data->regs)
639 		return -ENOMEM;
640 
641 	davinci_mdio_init_clk(data);
642 
643 	pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
644 	pm_runtime_use_autosuspend(&pdev->dev);
645 	pm_runtime_enable(&pdev->dev);
646 
647 	/* register the mii bus
648 	 * Create PHYs from DT only in case if PHY child nodes are explicitly
649 	 * defined to support backward compatibility with DTs which assume that
650 	 * Davinci MDIO will always scan the bus for PHYs detection.
651 	 */
652 	if (dev->of_node && of_get_child_count(dev->of_node))
653 		data->skip_scan = true;
654 
655 	ret = of_mdiobus_register(data->bus, dev->of_node);
656 	if (ret)
657 		goto bail_out;
658 
659 	/* scan and dump the bus */
660 	for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
661 		phy = mdiobus_get_phy(data->bus, addr);
662 		if (phy) {
663 			dev_info(dev, "phy[%d]: device %s, driver %s\n",
664 				 phy->mdio.addr, phydev_name(phy),
665 				 phy->drv ? phy->drv->name : "unknown");
666 		}
667 	}
668 
669 	return 0;
670 
671 bail_out:
672 	pm_runtime_dont_use_autosuspend(&pdev->dev);
673 	pm_runtime_disable(&pdev->dev);
674 	return ret;
675 }
676 
677 static int davinci_mdio_remove(struct platform_device *pdev)
678 {
679 	struct davinci_mdio_data *data = platform_get_drvdata(pdev);
680 
681 	if (data->bus) {
682 		mdiobus_unregister(data->bus);
683 
684 		if (data->manual_mode)
685 			free_mdio_bitbang(data->bus);
686 	}
687 
688 	pm_runtime_dont_use_autosuspend(&pdev->dev);
689 	pm_runtime_disable(&pdev->dev);
690 
691 	return 0;
692 }
693 
694 #ifdef CONFIG_PM
695 static int davinci_mdio_runtime_suspend(struct device *dev)
696 {
697 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
698 	u32 ctrl;
699 
700 	/* shutdown the scan state machine */
701 	ctrl = readl(&data->regs->control);
702 	ctrl &= ~CONTROL_ENABLE;
703 	writel(ctrl, &data->regs->control);
704 
705 	if (!data->manual_mode)
706 		wait_for_idle(data);
707 
708 	return 0;
709 }
710 
711 static int davinci_mdio_runtime_resume(struct device *dev)
712 {
713 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
714 
715 	if (data->manual_mode) {
716 		davinci_mdio_disable(data);
717 		davinci_mdio_enable_manual_mode(data);
718 	} else {
719 		davinci_mdio_enable(data);
720 	}
721 	return 0;
722 }
723 #endif
724 
725 #ifdef CONFIG_PM_SLEEP
726 static int davinci_mdio_suspend(struct device *dev)
727 {
728 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
729 	int ret = 0;
730 
731 	data->active_in_suspend = !pm_runtime_status_suspended(dev);
732 	if (data->active_in_suspend)
733 		ret = pm_runtime_force_suspend(dev);
734 	if (ret < 0)
735 		return ret;
736 
737 	/* Select sleep pin state */
738 	pinctrl_pm_select_sleep_state(dev);
739 
740 	return 0;
741 }
742 
743 static int davinci_mdio_resume(struct device *dev)
744 {
745 	struct davinci_mdio_data *data = dev_get_drvdata(dev);
746 
747 	/* Select default pin state */
748 	pinctrl_pm_select_default_state(dev);
749 
750 	if (data->active_in_suspend)
751 		pm_runtime_force_resume(dev);
752 
753 	return 0;
754 }
755 #endif
756 
757 static const struct dev_pm_ops davinci_mdio_pm_ops = {
758 	SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
759 			   davinci_mdio_runtime_resume, NULL)
760 	SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
761 };
762 
763 static struct platform_driver davinci_mdio_driver = {
764 	.driver = {
765 		.name	 = "davinci_mdio",
766 		.pm	 = &davinci_mdio_pm_ops,
767 		.of_match_table = of_match_ptr(davinci_mdio_of_mtable),
768 	},
769 	.probe = davinci_mdio_probe,
770 	.remove = davinci_mdio_remove,
771 };
772 
773 static int __init davinci_mdio_init(void)
774 {
775 	return platform_driver_register(&davinci_mdio_driver);
776 }
777 device_initcall(davinci_mdio_init);
778 
779 static void __exit davinci_mdio_exit(void)
780 {
781 	platform_driver_unregister(&davinci_mdio_driver);
782 }
783 module_exit(davinci_mdio_exit);
784 
785 MODULE_LICENSE("GPL");
786 MODULE_DESCRIPTION("DaVinci MDIO driver");
787