1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * DaVinci Ethernet Medium Access Controller 4 * 5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine 6 * 7 * Copyright (C) 2009 Texas Instruments. 8 * 9 * --------------------------------------------------------------------------- 10 * History: 11 * 0-5 A number of folks worked on this driver in bits and pieces but the major 12 * contribution came from Suraj Iyer and Anant Gole 13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions 14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features, 15 * PHY layer usage 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/sched.h> 21 #include <linux/string.h> 22 #include <linux/timer.h> 23 #include <linux/errno.h> 24 #include <linux/in.h> 25 #include <linux/ioport.h> 26 #include <linux/slab.h> 27 #include <linux/mm.h> 28 #include <linux/interrupt.h> 29 #include <linux/init.h> 30 #include <linux/netdevice.h> 31 #include <linux/etherdevice.h> 32 #include <linux/skbuff.h> 33 #include <linux/ethtool.h> 34 #include <linux/highmem.h> 35 #include <linux/proc_fs.h> 36 #include <linux/ctype.h> 37 #include <linux/spinlock.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/clk.h> 40 #include <linux/platform_device.h> 41 #include <linux/regmap.h> 42 #include <linux/semaphore.h> 43 #include <linux/phy.h> 44 #include <linux/bitops.h> 45 #include <linux/io.h> 46 #include <linux/uaccess.h> 47 #include <linux/pm_runtime.h> 48 #include <linux/davinci_emac.h> 49 #include <linux/of.h> 50 #include <linux/of_address.h> 51 #include <linux/of_device.h> 52 #include <linux/of_mdio.h> 53 #include <linux/of_irq.h> 54 #include <linux/of_net.h> 55 #include <linux/mfd/syscon.h> 56 57 #include <asm/irq.h> 58 #include <asm/page.h> 59 60 #include "cpsw.h" 61 #include "davinci_cpdma.h" 62 63 static int debug_level; 64 module_param(debug_level, int, 0); 65 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 66 67 /* Netif debug messages possible */ 68 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ 69 NETIF_MSG_PROBE | \ 70 NETIF_MSG_LINK | \ 71 NETIF_MSG_TIMER | \ 72 NETIF_MSG_IFDOWN | \ 73 NETIF_MSG_IFUP | \ 74 NETIF_MSG_RX_ERR | \ 75 NETIF_MSG_TX_ERR | \ 76 NETIF_MSG_TX_QUEUED | \ 77 NETIF_MSG_INTR | \ 78 NETIF_MSG_TX_DONE | \ 79 NETIF_MSG_RX_STATUS | \ 80 NETIF_MSG_PKTDATA | \ 81 NETIF_MSG_HW | \ 82 NETIF_MSG_WOL) 83 84 /* version info */ 85 #define EMAC_MAJOR_VERSION 6 86 #define EMAC_MINOR_VERSION 1 87 #define EMAC_MODULE_VERSION "6.1" 88 MODULE_VERSION(EMAC_MODULE_VERSION); 89 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 90 91 /* Configuration items */ 92 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ 93 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 94 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 95 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 96 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 97 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 98 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ 99 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ 100 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 101 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 102 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 103 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ 104 105 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ 106 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ 107 108 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ 109 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ 110 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 111 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 112 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 113 #define EMAC_DEF_RX_NUM_DESC (128) 114 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 115 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 116 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 117 118 /* Buffer descriptor parameters */ 119 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ 120 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ 121 122 /* EMAC register related defines */ 123 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 124 #define EMAC_NUM_MULTICAST_BITS (64) 125 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 126 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 127 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 128 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) 129 #define EMAC_INT_MASK_CLEAR (0xFF) 130 131 /* RX MBP register bit positions */ 132 #define EMAC_RXMBP_PASSCRC_MASK BIT(30) 133 #define EMAC_RXMBP_QOSEN_MASK BIT(29) 134 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) 135 #define EMAC_RXMBP_CMFEN_MASK BIT(24) 136 #define EMAC_RXMBP_CSFEN_MASK BIT(23) 137 #define EMAC_RXMBP_CEFEN_MASK BIT(22) 138 #define EMAC_RXMBP_CAFEN_MASK BIT(21) 139 #define EMAC_RXMBP_PROMCH_SHIFT (16) 140 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) 141 #define EMAC_RXMBP_BROADEN_MASK BIT(13) 142 #define EMAC_RXMBP_BROADCH_SHIFT (8) 143 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) 144 #define EMAC_RXMBP_MULTIEN_MASK BIT(5) 145 #define EMAC_RXMBP_MULTICH_SHIFT (0) 146 #define EMAC_RXMBP_MULTICH_MASK (0x7) 147 #define EMAC_RXMBP_CHMASK (0x7) 148 149 /* EMAC register definitions/bit maps used */ 150 # define EMAC_MBP_RXPROMISC (0x00200000) 151 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) 152 # define EMAC_MBP_RXBCAST (0x00002000) 153 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) 154 # define EMAC_MBP_RXMCAST (0x00000020) 155 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) 156 157 /* EMAC mac_control register */ 158 #define EMAC_MACCONTROL_TXPTYPE BIT(9) 159 #define EMAC_MACCONTROL_TXPACEEN BIT(6) 160 #define EMAC_MACCONTROL_GMIIEN BIT(5) 161 #define EMAC_MACCONTROL_GIGABITEN BIT(7) 162 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) 163 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) 164 165 /* GIGABIT MODE related bits */ 166 #define EMAC_DM646X_MACCONTORL_GIG BIT(7) 167 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) 168 169 /* EMAC mac_status register */ 170 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) 171 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) 172 #define EMAC_MACSTATUS_TXERRCH_MASK (0x70000) 173 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) 174 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) 175 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) 176 #define EMAC_MACSTATUS_RXERRCH_MASK (0x700) 177 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) 178 179 /* EMAC RX register masks */ 180 #define EMAC_RX_MAX_LEN_MASK (0xFFFF) 181 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) 182 183 /* MAC_IN_VECTOR (0x180) register bit fields */ 184 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) 185 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) 186 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) 187 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) 188 189 /** NOTE:: For DM646x the IN_VECTOR has changed */ 190 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) 191 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) 192 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) 193 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) 194 195 /* CPPI bit positions */ 196 #define EMAC_CPPI_SOP_BIT BIT(31) 197 #define EMAC_CPPI_EOP_BIT BIT(30) 198 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) 199 #define EMAC_CPPI_EOQ_BIT BIT(28) 200 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) 201 #define EMAC_CPPI_PASS_CRC_BIT BIT(26) 202 #define EMAC_RX_BD_BUF_SIZE (0xFFFF) 203 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ 204 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) 205 206 /* Max hardware defines */ 207 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ 208 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 209 210 /* EMAC Peripheral Device Register Memory Layout structure */ 211 #define EMAC_MACINVECTOR 0x90 212 213 #define EMAC_DM646X_MACEOIVECTOR 0x94 214 215 #define EMAC_MACINTSTATRAW 0xB0 216 #define EMAC_MACINTSTATMASKED 0xB4 217 #define EMAC_MACINTMASKSET 0xB8 218 #define EMAC_MACINTMASKCLEAR 0xBC 219 220 #define EMAC_RXMBPENABLE 0x100 221 #define EMAC_RXUNICASTSET 0x104 222 #define EMAC_RXUNICASTCLEAR 0x108 223 #define EMAC_RXMAXLEN 0x10C 224 #define EMAC_RXBUFFEROFFSET 0x110 225 #define EMAC_RXFILTERLOWTHRESH 0x114 226 227 #define EMAC_MACCONTROL 0x160 228 #define EMAC_MACSTATUS 0x164 229 #define EMAC_EMCONTROL 0x168 230 #define EMAC_FIFOCONTROL 0x16C 231 #define EMAC_MACCONFIG 0x170 232 #define EMAC_SOFTRESET 0x174 233 #define EMAC_MACSRCADDRLO 0x1D0 234 #define EMAC_MACSRCADDRHI 0x1D4 235 #define EMAC_MACHASH1 0x1D8 236 #define EMAC_MACHASH2 0x1DC 237 #define EMAC_MACADDRLO 0x500 238 #define EMAC_MACADDRHI 0x504 239 #define EMAC_MACINDEX 0x508 240 241 /* EMAC statistics registers */ 242 #define EMAC_RXGOODFRAMES 0x200 243 #define EMAC_RXBCASTFRAMES 0x204 244 #define EMAC_RXMCASTFRAMES 0x208 245 #define EMAC_RXPAUSEFRAMES 0x20C 246 #define EMAC_RXCRCERRORS 0x210 247 #define EMAC_RXALIGNCODEERRORS 0x214 248 #define EMAC_RXOVERSIZED 0x218 249 #define EMAC_RXJABBER 0x21C 250 #define EMAC_RXUNDERSIZED 0x220 251 #define EMAC_RXFRAGMENTS 0x224 252 #define EMAC_RXFILTERED 0x228 253 #define EMAC_RXQOSFILTERED 0x22C 254 #define EMAC_RXOCTETS 0x230 255 #define EMAC_TXGOODFRAMES 0x234 256 #define EMAC_TXBCASTFRAMES 0x238 257 #define EMAC_TXMCASTFRAMES 0x23C 258 #define EMAC_TXPAUSEFRAMES 0x240 259 #define EMAC_TXDEFERRED 0x244 260 #define EMAC_TXCOLLISION 0x248 261 #define EMAC_TXSINGLECOLL 0x24C 262 #define EMAC_TXMULTICOLL 0x250 263 #define EMAC_TXEXCESSIVECOLL 0x254 264 #define EMAC_TXLATECOLL 0x258 265 #define EMAC_TXUNDERRUN 0x25C 266 #define EMAC_TXCARRIERSENSE 0x260 267 #define EMAC_TXOCTETS 0x264 268 #define EMAC_NETOCTETS 0x280 269 #define EMAC_RXSOFOVERRUNS 0x284 270 #define EMAC_RXMOFOVERRUNS 0x288 271 #define EMAC_RXDMAOVERRUNS 0x28C 272 273 /* EMAC DM644x control registers */ 274 #define EMAC_CTRL_EWCTL (0x4) 275 #define EMAC_CTRL_EWINTTCNT (0x8) 276 277 /* EMAC DM644x control module masks */ 278 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF 279 #define EMAC_DM644X_INTMIN_INTVL 0x1 280 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 281 282 /* EMAC DM646X control module registers */ 283 #define EMAC_DM646X_CMINTCTRL 0x0C 284 #define EMAC_DM646X_CMRXINTEN 0x14 285 #define EMAC_DM646X_CMTXINTEN 0x18 286 #define EMAC_DM646X_CMRXINTMAX 0x70 287 #define EMAC_DM646X_CMTXINTMAX 0x74 288 289 /* EMAC DM646X control module masks */ 290 #define EMAC_DM646X_INTPACEEN (0x3 << 16) 291 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) 292 #define EMAC_DM646X_CMINTMAX_CNT 63 293 #define EMAC_DM646X_CMINTMIN_CNT 2 294 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) 295 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) 296 297 298 /* EMAC EOI codes for C0 */ 299 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 300 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 301 302 /* EMAC Stats Clear Mask */ 303 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 304 305 /* emac_priv: EMAC private data structure 306 * 307 * EMAC adapter private data structure 308 */ 309 struct emac_priv { 310 u32 msg_enable; 311 struct net_device *ndev; 312 struct platform_device *pdev; 313 struct napi_struct napi; 314 char mac_addr[6]; 315 void __iomem *remap_addr; 316 u32 emac_base_phys; 317 void __iomem *emac_base; 318 void __iomem *ctrl_base; 319 struct cpdma_ctlr *dma; 320 struct cpdma_chan *txchan; 321 struct cpdma_chan *rxchan; 322 u32 link; /* 1=link on, 0=link off */ 323 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 324 u32 duplex; /* Link duplex: 0=Half, 1=Full */ 325 u32 rx_buf_size; 326 u32 isr_count; 327 u32 coal_intvl; 328 u32 bus_freq_mhz; 329 u8 rmii_en; 330 u8 version; 331 u32 mac_hash1; 332 u32 mac_hash2; 333 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 334 u32 rx_addr_type; 335 const char *phy_id; 336 struct device_node *phy_node; 337 spinlock_t lock; 338 /*platform specific members*/ 339 void (*int_enable) (void); 340 void (*int_disable) (void); 341 }; 342 343 /* EMAC TX Host Error description strings */ 344 static char *emac_txhost_errcodes[16] = { 345 "No error", "SOP error", "Ownership bit not set in SOP buffer", 346 "Zero Next Buffer Descriptor Pointer Without EOP", 347 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", 348 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 349 "Reserved", "Reserved", "Reserved", "Reserved" 350 }; 351 352 /* EMAC RX Host Error description strings */ 353 static char *emac_rxhost_errcodes[16] = { 354 "No error", "Reserved", "Ownership bit not set in input buffer", 355 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", 356 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 357 "Reserved", "Reserved", "Reserved", "Reserved" 358 }; 359 360 /* Helper macros */ 361 #define emac_read(reg) ioread32(priv->emac_base + (reg)) 362 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) 363 364 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 365 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 366 367 /** 368 * emac_get_drvinfo - Get EMAC driver information 369 * @ndev: The DaVinci EMAC network adapter 370 * @info: ethtool info structure containing name and version 371 * 372 * Returns EMAC driver information (name and version) 373 * 374 */ 375 static void emac_get_drvinfo(struct net_device *ndev, 376 struct ethtool_drvinfo *info) 377 { 378 strlcpy(info->driver, emac_version_string, sizeof(info->driver)); 379 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version)); 380 } 381 382 /** 383 * emac_get_coalesce - Get interrupt coalesce settings for this device 384 * @ndev : The DaVinci EMAC network adapter 385 * @coal : ethtool coalesce settings structure 386 * @kernel_coal: ethtool CQE mode setting structure 387 * @extack: extack for reporting error messages 388 * 389 * Fetch the current interrupt coalesce settings 390 * 391 */ 392 static int emac_get_coalesce(struct net_device *ndev, 393 struct ethtool_coalesce *coal, 394 struct kernel_ethtool_coalesce *kernel_coal, 395 struct netlink_ext_ack *extack) 396 { 397 struct emac_priv *priv = netdev_priv(ndev); 398 399 coal->rx_coalesce_usecs = priv->coal_intvl; 400 return 0; 401 402 } 403 404 /** 405 * emac_set_coalesce - Set interrupt coalesce settings for this device 406 * @ndev : The DaVinci EMAC network adapter 407 * @coal : ethtool coalesce settings structure 408 * @kernel_coal: ethtool CQE mode setting structure 409 * @extack: extack for reporting error messages 410 * 411 * Set interrupt coalesce parameters 412 * 413 */ 414 static int emac_set_coalesce(struct net_device *ndev, 415 struct ethtool_coalesce *coal, 416 struct kernel_ethtool_coalesce *kernel_coal, 417 struct netlink_ext_ack *extack) 418 { 419 struct emac_priv *priv = netdev_priv(ndev); 420 u32 int_ctrl, num_interrupts = 0; 421 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; 422 423 if (!coal->rx_coalesce_usecs) 424 return -EINVAL; 425 426 coal_intvl = coal->rx_coalesce_usecs; 427 428 switch (priv->version) { 429 case EMAC_VERSION_2: 430 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); 431 prescale = priv->bus_freq_mhz * 4; 432 433 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) 434 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; 435 436 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { 437 /* 438 * Interrupt pacer works with 4us Pulse, we can 439 * throttle further by dilating the 4us pulse. 440 */ 441 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; 442 443 if (addnl_dvdr > 1) { 444 prescale *= addnl_dvdr; 445 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL 446 * addnl_dvdr)) 447 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL 448 * addnl_dvdr); 449 } else { 450 addnl_dvdr = 1; 451 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; 452 } 453 } 454 455 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 456 457 int_ctrl |= EMAC_DM646X_INTPACEEN; 458 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); 459 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); 460 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); 461 462 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); 463 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); 464 465 break; 466 default: 467 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); 468 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); 469 prescale = coal_intvl * priv->bus_freq_mhz; 470 if (prescale > EMAC_DM644X_EWINTCNT_MASK) { 471 prescale = EMAC_DM644X_EWINTCNT_MASK; 472 coal_intvl = prescale / priv->bus_freq_mhz; 473 } 474 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); 475 476 break; 477 } 478 479 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); 480 priv->coal_intvl = coal_intvl; 481 482 return 0; 483 484 } 485 486 487 /* ethtool_ops: DaVinci EMAC Ethtool structure 488 * 489 * Ethtool support for EMAC adapter 490 */ 491 static const struct ethtool_ops ethtool_ops = { 492 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, 493 .get_drvinfo = emac_get_drvinfo, 494 .get_link = ethtool_op_get_link, 495 .get_coalesce = emac_get_coalesce, 496 .set_coalesce = emac_set_coalesce, 497 .get_ts_info = ethtool_op_get_ts_info, 498 .get_link_ksettings = phy_ethtool_get_link_ksettings, 499 .set_link_ksettings = phy_ethtool_set_link_ksettings, 500 }; 501 502 /** 503 * emac_update_phystatus - Update Phy status 504 * @priv: The DaVinci EMAC private adapter structure 505 * 506 * Updates phy status and takes action for network queue if required 507 * based upon link status 508 * 509 */ 510 static void emac_update_phystatus(struct emac_priv *priv) 511 { 512 u32 mac_control; 513 u32 new_duplex; 514 u32 cur_duplex; 515 struct net_device *ndev = priv->ndev; 516 517 mac_control = emac_read(EMAC_MACCONTROL); 518 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? 519 DUPLEX_FULL : DUPLEX_HALF; 520 if (ndev->phydev) 521 new_duplex = ndev->phydev->duplex; 522 else 523 new_duplex = DUPLEX_FULL; 524 525 /* We get called only if link has changed (speed/duplex/status) */ 526 if ((priv->link) && (new_duplex != cur_duplex)) { 527 priv->duplex = new_duplex; 528 if (DUPLEX_FULL == priv->duplex) 529 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); 530 else 531 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); 532 } 533 534 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { 535 mac_control = emac_read(EMAC_MACCONTROL); 536 mac_control |= (EMAC_DM646X_MACCONTORL_GIG | 537 EMAC_DM646X_MACCONTORL_GIGFORCE); 538 } else { 539 /* Clear the GIG bit and GIGFORCE bit */ 540 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | 541 EMAC_DM646X_MACCONTORL_GIG); 542 543 if (priv->rmii_en && (priv->speed == SPEED_100)) 544 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; 545 else 546 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; 547 } 548 549 /* Update mac_control if changed */ 550 emac_write(EMAC_MACCONTROL, mac_control); 551 552 if (priv->link) { 553 /* link ON */ 554 if (!netif_carrier_ok(ndev)) 555 netif_carrier_on(ndev); 556 /* reactivate the transmit queue if it is stopped */ 557 if (netif_running(ndev) && netif_queue_stopped(ndev)) 558 netif_wake_queue(ndev); 559 } else { 560 /* link OFF */ 561 if (netif_carrier_ok(ndev)) 562 netif_carrier_off(ndev); 563 if (!netif_queue_stopped(ndev)) 564 netif_stop_queue(ndev); 565 } 566 } 567 568 /** 569 * hash_get - Calculate hash value from mac address 570 * @addr: mac address to delete from hash table 571 * 572 * Calculates hash value from mac address 573 * 574 */ 575 static u32 hash_get(u8 *addr) 576 { 577 u32 hash; 578 u8 tmpval; 579 int cnt; 580 hash = 0; 581 582 for (cnt = 0; cnt < 2; cnt++) { 583 tmpval = *addr++; 584 hash ^= (tmpval >> 2) ^ (tmpval << 4); 585 tmpval = *addr++; 586 hash ^= (tmpval >> 4) ^ (tmpval << 2); 587 tmpval = *addr++; 588 hash ^= (tmpval >> 6) ^ (tmpval); 589 } 590 591 return hash & 0x3F; 592 } 593 594 /** 595 * emac_hash_add - Hash function to add mac addr from hash table 596 * @priv: The DaVinci EMAC private adapter structure 597 * @mac_addr: mac address to delete from hash table 598 * 599 * Adds mac address to the internal hash table 600 * 601 */ 602 static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr) 603 { 604 struct device *emac_dev = &priv->ndev->dev; 605 u32 rc = 0; 606 u32 hash_bit; 607 u32 hash_value = hash_get(mac_addr); 608 609 if (hash_value >= EMAC_NUM_MULTICAST_BITS) { 610 if (netif_msg_drv(priv)) { 611 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\ 612 "Hash %08x, should not be greater than %08x", 613 hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); 614 } 615 return -1; 616 } 617 618 /* set the hash bit only if not previously set */ 619 if (priv->multicast_hash_cnt[hash_value] == 0) { 620 rc = 1; /* hash value changed */ 621 if (hash_value < 32) { 622 hash_bit = BIT(hash_value); 623 priv->mac_hash1 |= hash_bit; 624 } else { 625 hash_bit = BIT((hash_value - 32)); 626 priv->mac_hash2 |= hash_bit; 627 } 628 } 629 630 /* incr counter for num of mcast addr's mapped to "this" hash bit */ 631 ++priv->multicast_hash_cnt[hash_value]; 632 633 return rc; 634 } 635 636 /** 637 * emac_hash_del - Hash function to delete mac addr from hash table 638 * @priv: The DaVinci EMAC private adapter structure 639 * @mac_addr: mac address to delete from hash table 640 * 641 * Removes mac address from the internal hash table 642 * 643 */ 644 static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr) 645 { 646 u32 hash_value; 647 u32 hash_bit; 648 649 hash_value = hash_get(mac_addr); 650 if (priv->multicast_hash_cnt[hash_value] > 0) { 651 /* dec cntr for num of mcast addr's mapped to this hash bit */ 652 --priv->multicast_hash_cnt[hash_value]; 653 } 654 655 /* if counter still > 0, at least one multicast address refers 656 * to this hash bit. so return 0 */ 657 if (priv->multicast_hash_cnt[hash_value] > 0) 658 return 0; 659 660 if (hash_value < 32) { 661 hash_bit = BIT(hash_value); 662 priv->mac_hash1 &= ~hash_bit; 663 } else { 664 hash_bit = BIT((hash_value - 32)); 665 priv->mac_hash2 &= ~hash_bit; 666 } 667 668 /* return 1 to indicate change in mac_hash registers reqd */ 669 return 1; 670 } 671 672 /* EMAC multicast operation */ 673 #define EMAC_MULTICAST_ADD 0 674 #define EMAC_MULTICAST_DEL 1 675 #define EMAC_ALL_MULTI_SET 2 676 #define EMAC_ALL_MULTI_CLR 3 677 678 /** 679 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal) 680 * @priv: The DaVinci EMAC private adapter structure 681 * @action: multicast operation to perform 682 * @mac_addr: mac address to set 683 * 684 * Set multicast addresses in EMAC adapter - internal function 685 * 686 */ 687 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) 688 { 689 struct device *emac_dev = &priv->ndev->dev; 690 int update = -1; 691 692 switch (action) { 693 case EMAC_MULTICAST_ADD: 694 update = emac_hash_add(priv, mac_addr); 695 break; 696 case EMAC_MULTICAST_DEL: 697 update = emac_hash_del(priv, mac_addr); 698 break; 699 case EMAC_ALL_MULTI_SET: 700 update = 1; 701 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; 702 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; 703 break; 704 case EMAC_ALL_MULTI_CLR: 705 update = 1; 706 priv->mac_hash1 = 0; 707 priv->mac_hash2 = 0; 708 memset(&(priv->multicast_hash_cnt[0]), 0, 709 sizeof(priv->multicast_hash_cnt[0]) * 710 EMAC_NUM_MULTICAST_BITS); 711 break; 712 default: 713 if (netif_msg_drv(priv)) 714 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ 715 ": bad operation %d", action); 716 break; 717 } 718 719 /* write to the hardware only if the register status chances */ 720 if (update > 0) { 721 emac_write(EMAC_MACHASH1, priv->mac_hash1); 722 emac_write(EMAC_MACHASH2, priv->mac_hash2); 723 } 724 } 725 726 /** 727 * emac_dev_mcast_set - Set multicast address in the EMAC adapter 728 * @ndev: The DaVinci EMAC network adapter 729 * 730 * Set multicast addresses in EMAC adapter 731 * 732 */ 733 static void emac_dev_mcast_set(struct net_device *ndev) 734 { 735 u32 mbp_enable; 736 struct emac_priv *priv = netdev_priv(ndev); 737 738 mbp_enable = emac_read(EMAC_RXMBPENABLE); 739 if (ndev->flags & IFF_PROMISC) { 740 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); 741 mbp_enable |= (EMAC_MBP_RXPROMISC); 742 } else { 743 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); 744 if ((ndev->flags & IFF_ALLMULTI) || 745 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { 746 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 747 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); 748 } else if (!netdev_mc_empty(ndev)) { 749 struct netdev_hw_addr *ha; 750 751 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 752 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 753 /* program multicast address list into EMAC hardware */ 754 netdev_for_each_mc_addr(ha, ndev) { 755 emac_add_mcast(priv, EMAC_MULTICAST_ADD, 756 (u8 *) ha->addr); 757 } 758 } else { 759 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); 760 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 761 } 762 } 763 /* Set mbp config register */ 764 emac_write(EMAC_RXMBPENABLE, mbp_enable); 765 } 766 767 /************************************************************************* 768 * EMAC Hardware manipulation 769 *************************************************************************/ 770 771 /** 772 * emac_int_disable - Disable EMAC module interrupt (from adapter) 773 * @priv: The DaVinci EMAC private adapter structure 774 * 775 * Disable EMAC interrupt on the adapter 776 * 777 */ 778 static void emac_int_disable(struct emac_priv *priv) 779 { 780 if (priv->version == EMAC_VERSION_2) { 781 unsigned long flags; 782 783 local_irq_save(flags); 784 785 /* Program C0_Int_En to zero to turn off 786 * interrupts to the CPU */ 787 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); 788 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); 789 /* NOTE: Rx Threshold and Misc interrupts are not disabled */ 790 if (priv->int_disable) 791 priv->int_disable(); 792 793 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 794 795 /* ack rxen only then a new pulse will be generated */ 796 emac_write(EMAC_DM646X_MACEOIVECTOR, 797 EMAC_DM646X_MAC_EOI_C0_RXEN); 798 799 /* ack txen- only then a new pulse will be generated */ 800 emac_write(EMAC_DM646X_MACEOIVECTOR, 801 EMAC_DM646X_MAC_EOI_C0_TXEN); 802 803 local_irq_restore(flags); 804 805 } else { 806 /* Set DM644x control registers for interrupt control */ 807 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); 808 } 809 } 810 811 /** 812 * emac_int_enable - Enable EMAC module interrupt (from adapter) 813 * @priv: The DaVinci EMAC private adapter structure 814 * 815 * Enable EMAC interrupt on the adapter 816 * 817 */ 818 static void emac_int_enable(struct emac_priv *priv) 819 { 820 if (priv->version == EMAC_VERSION_2) { 821 if (priv->int_enable) 822 priv->int_enable(); 823 824 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); 825 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); 826 827 /* In addition to turning on interrupt Enable, we need 828 * ack by writing appropriate values to the EOI 829 * register */ 830 831 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 832 } else { 833 /* Set DM644x control registers for interrupt control */ 834 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); 835 } 836 } 837 838 /** 839 * emac_irq - EMAC interrupt handler 840 * @irq: interrupt number 841 * @dev_id: EMAC network adapter data structure ptr 842 * 843 * EMAC Interrupt handler - we only schedule NAPI and not process any packets 844 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function 845 * 846 * Returns interrupt handled condition 847 */ 848 static irqreturn_t emac_irq(int irq, void *dev_id) 849 { 850 struct net_device *ndev = (struct net_device *)dev_id; 851 struct emac_priv *priv = netdev_priv(ndev); 852 853 ++priv->isr_count; 854 if (likely(netif_running(priv->ndev))) { 855 emac_int_disable(priv); 856 napi_schedule(&priv->napi); 857 } else { 858 /* we are closing down, so dont process anything */ 859 } 860 return IRQ_HANDLED; 861 } 862 863 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv) 864 { 865 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size); 866 if (WARN_ON(!skb)) 867 return NULL; 868 skb_reserve(skb, NET_IP_ALIGN); 869 return skb; 870 } 871 872 static void emac_rx_handler(void *token, int len, int status) 873 { 874 struct sk_buff *skb = token; 875 struct net_device *ndev = skb->dev; 876 struct emac_priv *priv = netdev_priv(ndev); 877 struct device *emac_dev = &ndev->dev; 878 int ret; 879 880 /* free and bail if we are shutting down */ 881 if (unlikely(!netif_running(ndev))) { 882 dev_kfree_skb_any(skb); 883 return; 884 } 885 886 /* recycle on receive error */ 887 if (status < 0) { 888 ndev->stats.rx_errors++; 889 goto recycle; 890 } 891 892 /* feed received packet up the stack */ 893 skb_put(skb, len); 894 skb->protocol = eth_type_trans(skb, ndev); 895 netif_receive_skb(skb); 896 ndev->stats.rx_bytes += len; 897 ndev->stats.rx_packets++; 898 899 /* alloc a new packet for receive */ 900 skb = emac_rx_alloc(priv); 901 if (!skb) { 902 if (netif_msg_rx_err(priv) && net_ratelimit()) 903 dev_err(emac_dev, "failed rx buffer alloc\n"); 904 return; 905 } 906 907 recycle: 908 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 909 skb_tailroom(skb), 0); 910 911 WARN_ON(ret == -ENOMEM); 912 if (unlikely(ret < 0)) 913 dev_kfree_skb_any(skb); 914 } 915 916 static void emac_tx_handler(void *token, int len, int status) 917 { 918 struct sk_buff *skb = token; 919 struct net_device *ndev = skb->dev; 920 921 /* Check whether the queue is stopped due to stalled tx dma, if the 922 * queue is stopped then start the queue as we have free desc for tx 923 */ 924 if (unlikely(netif_queue_stopped(ndev))) 925 netif_wake_queue(ndev); 926 ndev->stats.tx_packets++; 927 ndev->stats.tx_bytes += len; 928 dev_kfree_skb_any(skb); 929 } 930 931 /** 932 * emac_dev_xmit - EMAC Transmit function 933 * @skb: SKB pointer 934 * @ndev: The DaVinci EMAC network adapter 935 * 936 * Called by the system to transmit a packet - we queue the packet in 937 * EMAC hardware transmit queue 938 * 939 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) 940 */ 941 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) 942 { 943 struct device *emac_dev = &ndev->dev; 944 int ret_code; 945 struct emac_priv *priv = netdev_priv(ndev); 946 947 /* If no link, return */ 948 if (unlikely(!priv->link)) { 949 if (netif_msg_tx_err(priv) && net_ratelimit()) 950 dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); 951 goto fail_tx; 952 } 953 954 ret_code = skb_put_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE); 955 if (unlikely(ret_code < 0)) { 956 if (netif_msg_tx_err(priv) && net_ratelimit()) 957 dev_err(emac_dev, "DaVinci EMAC: packet pad failed"); 958 goto fail_tx; 959 } 960 961 skb_tx_timestamp(skb); 962 963 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len, 964 0); 965 if (unlikely(ret_code != 0)) { 966 if (netif_msg_tx_err(priv) && net_ratelimit()) 967 dev_err(emac_dev, "DaVinci EMAC: desc submit failed"); 968 goto fail_tx; 969 } 970 971 /* If there is no more tx desc left free then we need to 972 * tell the kernel to stop sending us tx frames. 973 */ 974 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan))) 975 netif_stop_queue(ndev); 976 977 return NETDEV_TX_OK; 978 979 fail_tx: 980 ndev->stats.tx_dropped++; 981 netif_stop_queue(ndev); 982 return NETDEV_TX_BUSY; 983 } 984 985 /** 986 * emac_dev_tx_timeout - EMAC Transmit timeout function 987 * @ndev: The DaVinci EMAC network adapter 988 * @txqueue: the index of the hung transmit queue 989 * 990 * Called when system detects that a skb timeout period has expired 991 * potentially due to a fault in the adapter in not being able to send 992 * it out on the wire. We teardown the TX channel assuming a hardware 993 * error and re-initialize the TX channel for hardware operation 994 * 995 */ 996 static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue) 997 { 998 struct emac_priv *priv = netdev_priv(ndev); 999 struct device *emac_dev = &ndev->dev; 1000 1001 if (netif_msg_tx_err(priv)) 1002 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); 1003 1004 ndev->stats.tx_errors++; 1005 emac_int_disable(priv); 1006 cpdma_chan_stop(priv->txchan); 1007 cpdma_chan_start(priv->txchan); 1008 emac_int_enable(priv); 1009 } 1010 1011 /** 1012 * emac_set_type0addr - Set EMAC Type0 mac address 1013 * @priv: The DaVinci EMAC private adapter structure 1014 * @ch: RX channel number 1015 * @mac_addr: MAC address to set in device 1016 * 1017 * Called internally to set Type0 mac address of the adapter (Device) 1018 * 1019 * Returns success (0) or appropriate error code (none as of now) 1020 */ 1021 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1022 { 1023 u32 val; 1024 val = ((mac_addr[5] << 8) | (mac_addr[4])); 1025 emac_write(EMAC_MACSRCADDRLO, val); 1026 1027 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1028 (mac_addr[1] << 8) | (mac_addr[0])); 1029 emac_write(EMAC_MACSRCADDRHI, val); 1030 val = emac_read(EMAC_RXUNICASTSET); 1031 val |= BIT(ch); 1032 emac_write(EMAC_RXUNICASTSET, val); 1033 val = emac_read(EMAC_RXUNICASTCLEAR); 1034 val &= ~BIT(ch); 1035 emac_write(EMAC_RXUNICASTCLEAR, val); 1036 } 1037 1038 /** 1039 * emac_set_type1addr - Set EMAC Type1 mac address 1040 * @priv: The DaVinci EMAC private adapter structure 1041 * @ch: RX channel number 1042 * @mac_addr: MAC address to set in device 1043 * 1044 * Called internally to set Type1 mac address of the adapter (Device) 1045 * 1046 * Returns success (0) or appropriate error code (none as of now) 1047 */ 1048 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1049 { 1050 u32 val; 1051 emac_write(EMAC_MACINDEX, ch); 1052 val = ((mac_addr[5] << 8) | mac_addr[4]); 1053 emac_write(EMAC_MACADDRLO, val); 1054 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1055 (mac_addr[1] << 8) | (mac_addr[0])); 1056 emac_write(EMAC_MACADDRHI, val); 1057 emac_set_type0addr(priv, ch, mac_addr); 1058 } 1059 1060 /** 1061 * emac_set_type2addr - Set EMAC Type2 mac address 1062 * @priv: The DaVinci EMAC private adapter structure 1063 * @ch: RX channel number 1064 * @mac_addr: MAC address to set in device 1065 * @index: index into RX address entries 1066 * @match: match parameter for RX address matching logic 1067 * 1068 * Called internally to set Type2 mac address of the adapter (Device) 1069 * 1070 * Returns success (0) or appropriate error code (none as of now) 1071 */ 1072 static void emac_set_type2addr(struct emac_priv *priv, u32 ch, 1073 char *mac_addr, int index, int match) 1074 { 1075 u32 val; 1076 emac_write(EMAC_MACINDEX, index); 1077 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1078 (mac_addr[1] << 8) | (mac_addr[0])); 1079 emac_write(EMAC_MACADDRHI, val); 1080 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ 1081 (match << 19) | BIT(20)); 1082 emac_write(EMAC_MACADDRLO, val); 1083 emac_set_type0addr(priv, ch, mac_addr); 1084 } 1085 1086 /** 1087 * emac_setmac - Set mac address in the adapter (internal function) 1088 * @priv: The DaVinci EMAC private adapter structure 1089 * @ch: RX channel number 1090 * @mac_addr: MAC address to set in device 1091 * 1092 * Called internally to set the mac address of the adapter (Device) 1093 * 1094 * Returns success (0) or appropriate error code (none as of now) 1095 */ 1096 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) 1097 { 1098 struct device *emac_dev = &priv->ndev->dev; 1099 1100 if (priv->rx_addr_type == 0) { 1101 emac_set_type0addr(priv, ch, mac_addr); 1102 } else if (priv->rx_addr_type == 1) { 1103 u32 cnt; 1104 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) 1105 emac_set_type1addr(priv, ch, mac_addr); 1106 } else if (priv->rx_addr_type == 2) { 1107 emac_set_type2addr(priv, ch, mac_addr, ch, 1); 1108 emac_set_type0addr(priv, ch, mac_addr); 1109 } else { 1110 if (netif_msg_drv(priv)) 1111 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); 1112 } 1113 } 1114 1115 /** 1116 * emac_dev_setmac_addr - Set mac address in the adapter 1117 * @ndev: The DaVinci EMAC network adapter 1118 * @addr: MAC address to set in device 1119 * 1120 * Called by the system to set the mac address of the adapter (Device) 1121 * 1122 * Returns success (0) or appropriate error code (none as of now) 1123 */ 1124 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) 1125 { 1126 struct emac_priv *priv = netdev_priv(ndev); 1127 struct device *emac_dev = &priv->ndev->dev; 1128 struct sockaddr *sa = addr; 1129 1130 if (!is_valid_ether_addr(sa->sa_data)) 1131 return -EADDRNOTAVAIL; 1132 1133 /* Store mac addr in priv and rx channel and set it in EMAC hw */ 1134 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1135 eth_hw_addr_set(ndev, sa->sa_data); 1136 1137 /* MAC address is configured only after the interface is enabled. */ 1138 if (netif_running(ndev)) { 1139 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1140 } 1141 1142 if (netif_msg_drv(priv)) 1143 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", 1144 priv->mac_addr); 1145 1146 return 0; 1147 } 1148 1149 /** 1150 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception 1151 * @priv: The DaVinci EMAC private adapter structure 1152 * 1153 * Enables EMAC hardware for packet processing - enables PHY, enables RX 1154 * for packet reception and enables device interrupts and then NAPI 1155 * 1156 * Returns success (0) or appropriate error code (none right now) 1157 */ 1158 static int emac_hw_enable(struct emac_priv *priv) 1159 { 1160 u32 val, mbp_enable, mac_control; 1161 1162 /* Soft reset */ 1163 emac_write(EMAC_SOFTRESET, 1); 1164 while (emac_read(EMAC_SOFTRESET)) 1165 cpu_relax(); 1166 1167 /* Disable interrupt & Set pacing for more interrupts initially */ 1168 emac_int_disable(priv); 1169 1170 /* Full duplex enable bit set when auto negotiation happens */ 1171 mac_control = 1172 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | 1173 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | 1174 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | 1175 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); 1176 emac_write(EMAC_MACCONTROL, mac_control); 1177 1178 mbp_enable = 1179 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | 1180 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | 1181 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | 1182 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | 1183 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | 1184 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | 1185 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | 1186 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ 1187 EMAC_RXMBP_PROMCH_SHIFT) | 1188 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | 1189 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ 1190 EMAC_RXMBP_BROADCH_SHIFT) | 1191 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | 1192 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ 1193 EMAC_RXMBP_MULTICH_SHIFT)); 1194 emac_write(EMAC_RXMBPENABLE, mbp_enable); 1195 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & 1196 EMAC_RX_MAX_LEN_MASK)); 1197 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & 1198 EMAC_RX_BUFFER_OFFSET_MASK)); 1199 emac_write(EMAC_RXFILTERLOWTHRESH, 0); 1200 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); 1201 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; 1202 1203 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); 1204 1205 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1206 1207 /* Enable MII */ 1208 val = emac_read(EMAC_MACCONTROL); 1209 val |= (EMAC_MACCONTROL_GMIIEN); 1210 emac_write(EMAC_MACCONTROL, val); 1211 1212 /* Enable NAPI and interrupts */ 1213 napi_enable(&priv->napi); 1214 emac_int_enable(priv); 1215 return 0; 1216 1217 } 1218 1219 /** 1220 * emac_poll - EMAC NAPI Poll function 1221 * @napi: pointer to the napi_struct containing The DaVinci EMAC network adapter 1222 * @budget: Number of receive packets to process (as told by NAPI layer) 1223 * 1224 * NAPI Poll function implemented to process packets as per budget. We check 1225 * the type of interrupt on the device and accordingly call the TX or RX 1226 * packet processing functions. We follow the budget for RX processing and 1227 * also put a cap on number of TX pkts processed through config param. The 1228 * NAPI schedule function is called if more packets pending. 1229 * 1230 * Returns number of packets received (in most cases; else TX pkts - rarely) 1231 */ 1232 static int emac_poll(struct napi_struct *napi, int budget) 1233 { 1234 unsigned int mask; 1235 struct emac_priv *priv = container_of(napi, struct emac_priv, napi); 1236 struct net_device *ndev = priv->ndev; 1237 struct device *emac_dev = &ndev->dev; 1238 u32 status = 0; 1239 u32 num_rx_pkts = 0; 1240 1241 /* Check interrupt vectors and call packet processing */ 1242 status = emac_read(EMAC_MACINVECTOR); 1243 1244 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; 1245 1246 if (priv->version == EMAC_VERSION_2) 1247 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; 1248 1249 if (status & mask) { 1250 cpdma_chan_process(priv->txchan, EMAC_DEF_TX_MAX_SERVICE); 1251 } /* TX processing */ 1252 1253 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; 1254 1255 if (priv->version == EMAC_VERSION_2) 1256 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; 1257 1258 if (status & mask) { 1259 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget); 1260 } /* RX processing */ 1261 1262 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; 1263 if (priv->version == EMAC_VERSION_2) 1264 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; 1265 1266 if (unlikely(status & mask)) { 1267 u32 ch, cause; 1268 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); 1269 netif_stop_queue(ndev); 1270 napi_disable(&priv->napi); 1271 1272 status = emac_read(EMAC_MACSTATUS); 1273 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> 1274 EMAC_MACSTATUS_TXERRCODE_SHIFT); 1275 if (cause) { 1276 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> 1277 EMAC_MACSTATUS_TXERRCH_SHIFT); 1278 if (net_ratelimit()) { 1279 dev_err(emac_dev, "TX Host error %s on ch=%d\n", 1280 &emac_txhost_errcodes[cause][0], ch); 1281 } 1282 } 1283 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> 1284 EMAC_MACSTATUS_RXERRCODE_SHIFT); 1285 if (cause) { 1286 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> 1287 EMAC_MACSTATUS_RXERRCH_SHIFT); 1288 if (netif_msg_hw(priv) && net_ratelimit()) 1289 dev_err(emac_dev, "RX Host error %s on ch=%d\n", 1290 &emac_rxhost_errcodes[cause][0], ch); 1291 } 1292 } else if (num_rx_pkts < budget) { 1293 napi_complete_done(napi, num_rx_pkts); 1294 emac_int_enable(priv); 1295 } 1296 1297 return num_rx_pkts; 1298 } 1299 1300 #ifdef CONFIG_NET_POLL_CONTROLLER 1301 /** 1302 * emac_poll_controller - EMAC Poll controller function 1303 * @ndev: The DaVinci EMAC network adapter 1304 * 1305 * Polled functionality used by netconsole and others in non interrupt mode 1306 * 1307 */ 1308 static void emac_poll_controller(struct net_device *ndev) 1309 { 1310 struct emac_priv *priv = netdev_priv(ndev); 1311 1312 emac_int_disable(priv); 1313 emac_irq(ndev->irq, ndev); 1314 emac_int_enable(priv); 1315 } 1316 #endif 1317 1318 static void emac_adjust_link(struct net_device *ndev) 1319 { 1320 struct emac_priv *priv = netdev_priv(ndev); 1321 struct phy_device *phydev = ndev->phydev; 1322 unsigned long flags; 1323 int new_state = 0; 1324 1325 spin_lock_irqsave(&priv->lock, flags); 1326 1327 if (phydev->link) { 1328 /* check the mode of operation - full/half duplex */ 1329 if (phydev->duplex != priv->duplex) { 1330 new_state = 1; 1331 priv->duplex = phydev->duplex; 1332 } 1333 if (phydev->speed != priv->speed) { 1334 new_state = 1; 1335 priv->speed = phydev->speed; 1336 } 1337 if (!priv->link) { 1338 new_state = 1; 1339 priv->link = 1; 1340 } 1341 1342 } else if (priv->link) { 1343 new_state = 1; 1344 priv->link = 0; 1345 priv->speed = 0; 1346 priv->duplex = ~0; 1347 } 1348 if (new_state) { 1349 emac_update_phystatus(priv); 1350 phy_print_status(ndev->phydev); 1351 } 1352 1353 spin_unlock_irqrestore(&priv->lock, flags); 1354 } 1355 1356 /************************************************************************* 1357 * Linux Driver Model 1358 *************************************************************************/ 1359 1360 /** 1361 * emac_devioctl - EMAC adapter ioctl 1362 * @ndev: The DaVinci EMAC network adapter 1363 * @ifrq: request parameter 1364 * @cmd: command parameter 1365 * 1366 * EMAC driver ioctl function 1367 * 1368 * Returns success(0) or appropriate error code 1369 */ 1370 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) 1371 { 1372 if (!(netif_running(ndev))) 1373 return -EINVAL; 1374 1375 /* TODO: Add phy read and write and private statistics get feature */ 1376 1377 if (ndev->phydev) 1378 return phy_mii_ioctl(ndev->phydev, ifrq, cmd); 1379 else 1380 return -EOPNOTSUPP; 1381 } 1382 1383 static int match_first_device(struct device *dev, const void *data) 1384 { 1385 if (dev->parent && dev->parent->of_node) 1386 return of_device_is_compatible(dev->parent->of_node, 1387 "ti,davinci_mdio"); 1388 1389 return !strncmp(dev_name(dev), "davinci_mdio", 12); 1390 } 1391 1392 /** 1393 * emac_dev_open - EMAC device open 1394 * @ndev: The DaVinci EMAC network adapter 1395 * 1396 * Called when system wants to start the interface. We init TX/RX channels 1397 * and enable the hardware for packet reception/transmission and start the 1398 * network queue. 1399 * 1400 * Returns 0 for a successful open, or appropriate error code 1401 */ 1402 static int emac_dev_open(struct net_device *ndev) 1403 { 1404 struct device *emac_dev = &ndev->dev; 1405 struct resource *res; 1406 int q, m, ret; 1407 int res_num = 0, irq_num = 0; 1408 int i = 0; 1409 struct emac_priv *priv = netdev_priv(ndev); 1410 struct phy_device *phydev = NULL; 1411 struct device *phy = NULL; 1412 1413 ret = pm_runtime_get_sync(&priv->pdev->dev); 1414 if (ret < 0) { 1415 pm_runtime_put_noidle(&priv->pdev->dev); 1416 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1417 __func__, ret); 1418 return ret; 1419 } 1420 1421 netif_carrier_off(ndev); 1422 eth_hw_addr_set(ndev, priv->mac_addr); 1423 1424 /* Configuration items */ 1425 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; 1426 1427 priv->mac_hash1 = 0; 1428 priv->mac_hash2 = 0; 1429 emac_write(EMAC_MACHASH1, 0); 1430 emac_write(EMAC_MACHASH2, 0); 1431 1432 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) { 1433 struct sk_buff *skb = emac_rx_alloc(priv); 1434 1435 if (!skb) 1436 break; 1437 1438 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data, 1439 skb_tailroom(skb), 0); 1440 if (WARN_ON(ret < 0)) 1441 break; 1442 } 1443 1444 /* Request IRQ */ 1445 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, 1446 res_num))) { 1447 for (irq_num = res->start; irq_num <= res->end; irq_num++) { 1448 if (request_irq(irq_num, emac_irq, 0, ndev->name, 1449 ndev)) { 1450 dev_err(emac_dev, 1451 "DaVinci EMAC: request_irq() failed\n"); 1452 ret = -EBUSY; 1453 1454 goto rollback; 1455 } 1456 } 1457 res_num++; 1458 } 1459 /* prepare counters for rollback in case of an error */ 1460 res_num--; 1461 irq_num--; 1462 1463 /* Start/Enable EMAC hardware */ 1464 emac_hw_enable(priv); 1465 1466 /* Enable Interrupt pacing if configured */ 1467 if (priv->coal_intvl != 0) { 1468 struct ethtool_coalesce coal; 1469 1470 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1471 emac_set_coalesce(ndev, &coal, NULL, NULL); 1472 } 1473 1474 cpdma_ctlr_start(priv->dma); 1475 1476 if (priv->phy_node) { 1477 phydev = of_phy_connect(ndev, priv->phy_node, 1478 &emac_adjust_link, 0, 0); 1479 if (!phydev) { 1480 dev_err(emac_dev, "could not connect to phy %pOF\n", 1481 priv->phy_node); 1482 ret = -ENODEV; 1483 goto err; 1484 } 1485 } 1486 1487 /* use the first phy on the bus if pdata did not give us a phy id */ 1488 if (!phydev && !priv->phy_id) { 1489 /* NOTE: we can't use bus_find_device_by_name() here because 1490 * the device name is not guaranteed to be 'davinci_mdio'. On 1491 * some systems it can be 'davinci_mdio.0' so we need to use 1492 * strncmp() against the first part of the string to correctly 1493 * match it. 1494 */ 1495 phy = bus_find_device(&mdio_bus_type, NULL, NULL, 1496 match_first_device); 1497 if (phy) { 1498 priv->phy_id = dev_name(phy); 1499 if (!priv->phy_id || !*priv->phy_id) 1500 put_device(phy); 1501 } 1502 } 1503 1504 if (!phydev && priv->phy_id && *priv->phy_id) { 1505 phydev = phy_connect(ndev, priv->phy_id, 1506 &emac_adjust_link, 1507 PHY_INTERFACE_MODE_MII); 1508 put_device(phy); /* reference taken by bus_find_device */ 1509 if (IS_ERR(phydev)) { 1510 dev_err(emac_dev, "could not connect to phy %s\n", 1511 priv->phy_id); 1512 ret = PTR_ERR(phydev); 1513 goto err; 1514 } 1515 1516 priv->link = 0; 1517 priv->speed = 0; 1518 priv->duplex = ~0; 1519 1520 phy_attached_info(phydev); 1521 } 1522 1523 if (!phydev) { 1524 /* No PHY , fix the link, speed and duplex settings */ 1525 dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); 1526 priv->link = 1; 1527 priv->speed = SPEED_100; 1528 priv->duplex = DUPLEX_FULL; 1529 emac_update_phystatus(priv); 1530 } 1531 1532 if (netif_msg_drv(priv)) 1533 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); 1534 1535 if (phydev) 1536 phy_start(phydev); 1537 1538 return 0; 1539 1540 err: 1541 emac_int_disable(priv); 1542 napi_disable(&priv->napi); 1543 1544 rollback: 1545 for (q = res_num; q >= 0; q--) { 1546 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q); 1547 /* at the first iteration, irq_num is already set to the 1548 * right value 1549 */ 1550 if (q != res_num) 1551 irq_num = res->end; 1552 1553 for (m = irq_num; m >= res->start; m--) 1554 free_irq(m, ndev); 1555 } 1556 cpdma_ctlr_stop(priv->dma); 1557 pm_runtime_put(&priv->pdev->dev); 1558 return ret; 1559 } 1560 1561 /** 1562 * emac_dev_stop - EMAC device stop 1563 * @ndev: The DaVinci EMAC network adapter 1564 * 1565 * Called when system wants to stop or down the interface. We stop the network 1566 * queue, disable interrupts and cleanup TX/RX channels. 1567 * 1568 * We return the statistics in net_device_stats structure pulled from emac 1569 */ 1570 static int emac_dev_stop(struct net_device *ndev) 1571 { 1572 struct resource *res; 1573 int i = 0; 1574 int irq_num; 1575 struct emac_priv *priv = netdev_priv(ndev); 1576 struct device *emac_dev = &ndev->dev; 1577 1578 /* inform the upper layers. */ 1579 netif_stop_queue(ndev); 1580 napi_disable(&priv->napi); 1581 1582 netif_carrier_off(ndev); 1583 emac_int_disable(priv); 1584 cpdma_ctlr_stop(priv->dma); 1585 emac_write(EMAC_SOFTRESET, 1); 1586 1587 if (ndev->phydev) 1588 phy_disconnect(ndev->phydev); 1589 1590 /* Free IRQ */ 1591 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { 1592 for (irq_num = res->start; irq_num <= res->end; irq_num++) 1593 free_irq(irq_num, priv->ndev); 1594 i++; 1595 } 1596 1597 if (netif_msg_drv(priv)) 1598 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); 1599 1600 pm_runtime_put(&priv->pdev->dev); 1601 return 0; 1602 } 1603 1604 /** 1605 * emac_dev_getnetstats - EMAC get statistics function 1606 * @ndev: The DaVinci EMAC network adapter 1607 * 1608 * Called when system wants to get statistics from the device. 1609 * 1610 * We return the statistics in net_device_stats structure pulled from emac 1611 */ 1612 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) 1613 { 1614 struct emac_priv *priv = netdev_priv(ndev); 1615 u32 mac_control; 1616 u32 stats_clear_mask; 1617 int err; 1618 1619 err = pm_runtime_get_sync(&priv->pdev->dev); 1620 if (err < 0) { 1621 pm_runtime_put_noidle(&priv->pdev->dev); 1622 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1623 __func__, err); 1624 return &ndev->stats; 1625 } 1626 1627 /* update emac hardware stats and reset the registers*/ 1628 1629 mac_control = emac_read(EMAC_MACCONTROL); 1630 1631 if (mac_control & EMAC_MACCONTROL_GMIIEN) 1632 stats_clear_mask = EMAC_STATS_CLR_MASK; 1633 else 1634 stats_clear_mask = 0; 1635 1636 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); 1637 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); 1638 1639 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + 1640 emac_read(EMAC_TXSINGLECOLL) + 1641 emac_read(EMAC_TXMULTICOLL)); 1642 emac_write(EMAC_TXCOLLISION, stats_clear_mask); 1643 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); 1644 emac_write(EMAC_TXMULTICOLL, stats_clear_mask); 1645 1646 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + 1647 emac_read(EMAC_RXJABBER) + 1648 emac_read(EMAC_RXUNDERSIZED)); 1649 emac_write(EMAC_RXOVERSIZED, stats_clear_mask); 1650 emac_write(EMAC_RXJABBER, stats_clear_mask); 1651 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); 1652 1653 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + 1654 emac_read(EMAC_RXMOFOVERRUNS)); 1655 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); 1656 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); 1657 1658 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); 1659 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); 1660 1661 ndev->stats.tx_carrier_errors += 1662 emac_read(EMAC_TXCARRIERSENSE); 1663 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); 1664 1665 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); 1666 emac_write(EMAC_TXUNDERRUN, stats_clear_mask); 1667 1668 pm_runtime_put(&priv->pdev->dev); 1669 1670 return &ndev->stats; 1671 } 1672 1673 static const struct net_device_ops emac_netdev_ops = { 1674 .ndo_open = emac_dev_open, 1675 .ndo_stop = emac_dev_stop, 1676 .ndo_start_xmit = emac_dev_xmit, 1677 .ndo_set_rx_mode = emac_dev_mcast_set, 1678 .ndo_set_mac_address = emac_dev_setmac_addr, 1679 .ndo_eth_ioctl = emac_devioctl, 1680 .ndo_tx_timeout = emac_dev_tx_timeout, 1681 .ndo_get_stats = emac_dev_getnetstats, 1682 #ifdef CONFIG_NET_POLL_CONTROLLER 1683 .ndo_poll_controller = emac_poll_controller, 1684 #endif 1685 }; 1686 1687 static const struct of_device_id davinci_emac_of_match[]; 1688 1689 static struct emac_platform_data * 1690 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv) 1691 { 1692 struct device_node *np; 1693 const struct of_device_id *match; 1694 const struct emac_platform_data *auxdata; 1695 struct emac_platform_data *pdata = NULL; 1696 1697 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) 1698 return dev_get_platdata(&pdev->dev); 1699 1700 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1701 if (!pdata) 1702 return NULL; 1703 1704 np = pdev->dev.of_node; 1705 pdata->version = EMAC_VERSION_2; 1706 1707 if (!is_valid_ether_addr(pdata->mac_addr)) 1708 of_get_mac_address(np, pdata->mac_addr); 1709 1710 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", 1711 &pdata->ctrl_reg_offset); 1712 1713 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset", 1714 &pdata->ctrl_mod_reg_offset); 1715 1716 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", 1717 &pdata->ctrl_ram_offset); 1718 1719 of_property_read_u32(np, "ti,davinci-ctrl-ram-size", 1720 &pdata->ctrl_ram_size); 1721 1722 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en); 1723 1724 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram"); 1725 1726 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 1727 if (!priv->phy_node) { 1728 if (!of_phy_is_fixed_link(np)) 1729 pdata->phy_id = NULL; 1730 else if (of_phy_register_fixed_link(np) >= 0) 1731 priv->phy_node = of_node_get(np); 1732 } 1733 1734 auxdata = pdev->dev.platform_data; 1735 if (auxdata) { 1736 pdata->interrupt_enable = auxdata->interrupt_enable; 1737 pdata->interrupt_disable = auxdata->interrupt_disable; 1738 } 1739 1740 match = of_match_device(davinci_emac_of_match, &pdev->dev); 1741 if (match && match->data) { 1742 auxdata = match->data; 1743 pdata->version = auxdata->version; 1744 pdata->hw_ram_addr = auxdata->hw_ram_addr; 1745 } 1746 1747 return pdata; 1748 } 1749 1750 static int davinci_emac_try_get_mac(struct platform_device *pdev, 1751 int instance, u8 *mac_addr) 1752 { 1753 if (!pdev->dev.of_node) 1754 return -EINVAL; 1755 1756 return ti_cm_get_macid(&pdev->dev, instance, mac_addr); 1757 } 1758 1759 /** 1760 * davinci_emac_probe - EMAC device probe 1761 * @pdev: The DaVinci EMAC device that we are removing 1762 * 1763 * Called when probing for emac devicesr. We get details of instances and 1764 * resource information from platform init and register a network device 1765 * and allocate resources necessary for driver to perform 1766 */ 1767 static int davinci_emac_probe(struct platform_device *pdev) 1768 { 1769 struct device_node *np = pdev->dev.of_node; 1770 int rc = 0; 1771 struct resource *res, *res_ctrl; 1772 struct net_device *ndev; 1773 struct emac_priv *priv; 1774 unsigned long hw_ram_addr; 1775 struct emac_platform_data *pdata; 1776 struct cpdma_params dma_params; 1777 struct clk *emac_clk; 1778 unsigned long emac_bus_frequency; 1779 1780 1781 /* obtain emac clock from kernel */ 1782 emac_clk = devm_clk_get(&pdev->dev, NULL); 1783 if (IS_ERR(emac_clk)) { 1784 dev_err(&pdev->dev, "failed to get EMAC clock\n"); 1785 return -EBUSY; 1786 } 1787 emac_bus_frequency = clk_get_rate(emac_clk); 1788 devm_clk_put(&pdev->dev, emac_clk); 1789 1790 /* TODO: Probe PHY here if possible */ 1791 1792 ndev = alloc_etherdev(sizeof(struct emac_priv)); 1793 if (!ndev) 1794 return -ENOMEM; 1795 1796 platform_set_drvdata(pdev, ndev); 1797 priv = netdev_priv(ndev); 1798 priv->pdev = pdev; 1799 priv->ndev = ndev; 1800 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); 1801 1802 spin_lock_init(&priv->lock); 1803 1804 pdata = davinci_emac_of_get_pdata(pdev, priv); 1805 if (!pdata) { 1806 dev_err(&pdev->dev, "no platform data\n"); 1807 rc = -ENODEV; 1808 goto err_free_netdev; 1809 } 1810 1811 /* MAC addr and PHY mask , RMII enable info from platform_data */ 1812 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN); 1813 priv->phy_id = pdata->phy_id; 1814 priv->rmii_en = pdata->rmii_en; 1815 priv->version = pdata->version; 1816 priv->int_enable = pdata->interrupt_enable; 1817 priv->int_disable = pdata->interrupt_disable; 1818 1819 priv->coal_intvl = 0; 1820 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); 1821 1822 /* Get EMAC platform data */ 1823 priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1824 if (IS_ERR(priv->remap_addr)) { 1825 rc = PTR_ERR(priv->remap_addr); 1826 goto no_pdata; 1827 } 1828 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 1829 1830 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1831 if (res_ctrl) { 1832 priv->ctrl_base = 1833 devm_ioremap_resource(&pdev->dev, res_ctrl); 1834 if (IS_ERR(priv->ctrl_base)) { 1835 rc = PTR_ERR(priv->ctrl_base); 1836 goto no_pdata; 1837 } 1838 } else { 1839 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; 1840 } 1841 1842 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; 1843 ndev->base_addr = (unsigned long)priv->remap_addr; 1844 1845 hw_ram_addr = pdata->hw_ram_addr; 1846 if (!hw_ram_addr) 1847 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; 1848 1849 memset(&dma_params, 0, sizeof(dma_params)); 1850 dma_params.dev = &pdev->dev; 1851 dma_params.dmaregs = priv->emac_base; 1852 dma_params.rxthresh = priv->emac_base + 0x120; 1853 dma_params.rxfree = priv->emac_base + 0x140; 1854 dma_params.txhdp = priv->emac_base + 0x600; 1855 dma_params.rxhdp = priv->emac_base + 0x620; 1856 dma_params.txcp = priv->emac_base + 0x640; 1857 dma_params.rxcp = priv->emac_base + 0x660; 1858 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS; 1859 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE; 1860 dma_params.desc_hw_addr = hw_ram_addr; 1861 dma_params.desc_mem_size = pdata->ctrl_ram_size; 1862 dma_params.desc_align = 16; 1863 1864 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 : 1865 (u32 __force)res->start + pdata->ctrl_ram_offset; 1866 1867 priv->dma = cpdma_ctlr_create(&dma_params); 1868 if (!priv->dma) { 1869 dev_err(&pdev->dev, "error initializing DMA\n"); 1870 rc = -ENOMEM; 1871 goto no_pdata; 1872 } 1873 1874 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH, 1875 emac_tx_handler, 0); 1876 if (IS_ERR(priv->txchan)) { 1877 dev_err(&pdev->dev, "error initializing tx dma channel\n"); 1878 rc = PTR_ERR(priv->txchan); 1879 goto err_free_dma; 1880 } 1881 1882 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH, 1883 emac_rx_handler, 1); 1884 if (IS_ERR(priv->rxchan)) { 1885 dev_err(&pdev->dev, "error initializing rx dma channel\n"); 1886 rc = PTR_ERR(priv->rxchan); 1887 goto err_free_txchan; 1888 } 1889 1890 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1891 if (!res) { 1892 dev_err(&pdev->dev, "error getting irq res\n"); 1893 rc = -ENOENT; 1894 goto err_free_rxchan; 1895 } 1896 ndev->irq = res->start; 1897 1898 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr); 1899 if (!rc) 1900 eth_hw_addr_set(ndev, priv->mac_addr); 1901 1902 if (!is_valid_ether_addr(priv->mac_addr)) { 1903 /* Use random MAC if still none obtained. */ 1904 eth_hw_addr_random(ndev); 1905 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len); 1906 dev_warn(&pdev->dev, "using random MAC addr: %pM\n", 1907 priv->mac_addr); 1908 } 1909 1910 ndev->netdev_ops = &emac_netdev_ops; 1911 ndev->ethtool_ops = ðtool_ops; 1912 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); 1913 1914 pm_runtime_enable(&pdev->dev); 1915 rc = pm_runtime_get_sync(&pdev->dev); 1916 if (rc < 0) { 1917 pm_runtime_put_noidle(&pdev->dev); 1918 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n", 1919 __func__, rc); 1920 goto err_napi_del; 1921 } 1922 1923 /* register the network device */ 1924 SET_NETDEV_DEV(ndev, &pdev->dev); 1925 rc = register_netdev(ndev); 1926 if (rc) { 1927 dev_err(&pdev->dev, "error in register_netdev\n"); 1928 rc = -ENODEV; 1929 pm_runtime_put(&pdev->dev); 1930 goto err_napi_del; 1931 } 1932 1933 1934 if (netif_msg_probe(priv)) { 1935 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device " 1936 "(regs: %pa, irq: %d)\n", 1937 &priv->emac_base_phys, ndev->irq); 1938 } 1939 pm_runtime_put(&pdev->dev); 1940 1941 return 0; 1942 1943 err_napi_del: 1944 netif_napi_del(&priv->napi); 1945 err_free_rxchan: 1946 cpdma_chan_destroy(priv->rxchan); 1947 err_free_txchan: 1948 cpdma_chan_destroy(priv->txchan); 1949 err_free_dma: 1950 cpdma_ctlr_destroy(priv->dma); 1951 no_pdata: 1952 if (of_phy_is_fixed_link(np)) 1953 of_phy_deregister_fixed_link(np); 1954 of_node_put(priv->phy_node); 1955 err_free_netdev: 1956 free_netdev(ndev); 1957 return rc; 1958 } 1959 1960 /** 1961 * davinci_emac_remove - EMAC device remove 1962 * @pdev: The DaVinci EMAC device that we are removing 1963 * 1964 * Called when removing the device driver. We disable clock usage and release 1965 * the resources taken up by the driver and unregister network device 1966 */ 1967 static int davinci_emac_remove(struct platform_device *pdev) 1968 { 1969 struct net_device *ndev = platform_get_drvdata(pdev); 1970 struct emac_priv *priv = netdev_priv(ndev); 1971 struct device_node *np = pdev->dev.of_node; 1972 1973 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); 1974 1975 if (priv->txchan) 1976 cpdma_chan_destroy(priv->txchan); 1977 if (priv->rxchan) 1978 cpdma_chan_destroy(priv->rxchan); 1979 cpdma_ctlr_destroy(priv->dma); 1980 1981 unregister_netdev(ndev); 1982 of_node_put(priv->phy_node); 1983 pm_runtime_disable(&pdev->dev); 1984 if (of_phy_is_fixed_link(np)) 1985 of_phy_deregister_fixed_link(np); 1986 free_netdev(ndev); 1987 1988 return 0; 1989 } 1990 1991 static int davinci_emac_suspend(struct device *dev) 1992 { 1993 struct net_device *ndev = dev_get_drvdata(dev); 1994 1995 if (netif_running(ndev)) 1996 emac_dev_stop(ndev); 1997 1998 return 0; 1999 } 2000 2001 static int davinci_emac_resume(struct device *dev) 2002 { 2003 struct net_device *ndev = dev_get_drvdata(dev); 2004 2005 if (netif_running(ndev)) 2006 emac_dev_open(ndev); 2007 2008 return 0; 2009 } 2010 2011 static const struct dev_pm_ops davinci_emac_pm_ops = { 2012 .suspend = davinci_emac_suspend, 2013 .resume = davinci_emac_resume, 2014 }; 2015 2016 static const struct emac_platform_data am3517_emac_data = { 2017 .version = EMAC_VERSION_2, 2018 .hw_ram_addr = 0x01e20000, 2019 }; 2020 2021 static const struct emac_platform_data dm816_emac_data = { 2022 .version = EMAC_VERSION_2, 2023 }; 2024 2025 static const struct of_device_id davinci_emac_of_match[] = { 2026 {.compatible = "ti,davinci-dm6467-emac", }, 2027 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, }, 2028 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, }, 2029 {}, 2030 }; 2031 MODULE_DEVICE_TABLE(of, davinci_emac_of_match); 2032 2033 /* davinci_emac_driver: EMAC platform driver structure */ 2034 static struct platform_driver davinci_emac_driver = { 2035 .driver = { 2036 .name = "davinci_emac", 2037 .pm = &davinci_emac_pm_ops, 2038 .of_match_table = davinci_emac_of_match, 2039 }, 2040 .probe = davinci_emac_probe, 2041 .remove = davinci_emac_remove, 2042 }; 2043 2044 /** 2045 * davinci_emac_init - EMAC driver module init 2046 * 2047 * Called when initializing the driver. We register the driver with 2048 * the platform. 2049 */ 2050 static int __init davinci_emac_init(void) 2051 { 2052 return platform_driver_register(&davinci_emac_driver); 2053 } 2054 late_initcall(davinci_emac_init); 2055 2056 /** 2057 * davinci_emac_exit - EMAC driver module exit 2058 * 2059 * Called when exiting the driver completely. We unregister the driver with 2060 * the platform and exit 2061 */ 2062 static void __exit davinci_emac_exit(void) 2063 { 2064 platform_driver_unregister(&davinci_emac_driver); 2065 } 2066 module_exit(davinci_emac_exit); 2067 2068 MODULE_LICENSE("GPL"); 2069 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); 2070 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); 2071 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); 2072