1 /* 2 * DaVinci Ethernet Medium Access Controller 3 * 4 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine 5 * 6 * Copyright (C) 2009 Texas Instruments. 7 * 8 * --------------------------------------------------------------------------- 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 23 * --------------------------------------------------------------------------- 24 * History: 25 * 0-5 A number of folks worked on this driver in bits and pieces but the major 26 * contribution came from Suraj Iyer and Anant Gole 27 * 6.0 Anant Gole - rewrote the driver as per Linux conventions 28 * 6.1 Chaithrika U S - added support for Gigabit and RMII features, 29 * PHY layer usage 30 */ 31 32 #include <linux/module.h> 33 #include <linux/kernel.h> 34 #include <linux/sched.h> 35 #include <linux/string.h> 36 #include <linux/timer.h> 37 #include <linux/errno.h> 38 #include <linux/in.h> 39 #include <linux/ioport.h> 40 #include <linux/slab.h> 41 #include <linux/mm.h> 42 #include <linux/interrupt.h> 43 #include <linux/init.h> 44 #include <linux/netdevice.h> 45 #include <linux/etherdevice.h> 46 #include <linux/skbuff.h> 47 #include <linux/ethtool.h> 48 #include <linux/highmem.h> 49 #include <linux/proc_fs.h> 50 #include <linux/ctype.h> 51 #include <linux/spinlock.h> 52 #include <linux/dma-mapping.h> 53 #include <linux/clk.h> 54 #include <linux/platform_device.h> 55 #include <linux/semaphore.h> 56 #include <linux/phy.h> 57 #include <linux/bitops.h> 58 #include <linux/io.h> 59 #include <linux/uaccess.h> 60 #include <linux/pm_runtime.h> 61 #include <linux/davinci_emac.h> 62 #include <linux/of.h> 63 #include <linux/of_address.h> 64 #include <linux/of_irq.h> 65 #include <linux/of_net.h> 66 67 #include <asm/irq.h> 68 #include <asm/page.h> 69 70 #include "davinci_cpdma.h" 71 72 static int debug_level; 73 module_param(debug_level, int, 0); 74 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 75 76 /* Netif debug messages possible */ 77 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ 78 NETIF_MSG_PROBE | \ 79 NETIF_MSG_LINK | \ 80 NETIF_MSG_TIMER | \ 81 NETIF_MSG_IFDOWN | \ 82 NETIF_MSG_IFUP | \ 83 NETIF_MSG_RX_ERR | \ 84 NETIF_MSG_TX_ERR | \ 85 NETIF_MSG_TX_QUEUED | \ 86 NETIF_MSG_INTR | \ 87 NETIF_MSG_TX_DONE | \ 88 NETIF_MSG_RX_STATUS | \ 89 NETIF_MSG_PKTDATA | \ 90 NETIF_MSG_HW | \ 91 NETIF_MSG_WOL) 92 93 /* version info */ 94 #define EMAC_MAJOR_VERSION 6 95 #define EMAC_MINOR_VERSION 1 96 #define EMAC_MODULE_VERSION "6.1" 97 MODULE_VERSION(EMAC_MODULE_VERSION); 98 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 99 100 /* Configuration items */ 101 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ 102 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 103 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 104 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 105 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 106 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 107 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ 108 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ 109 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 110 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 111 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 112 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ 113 114 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ 115 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ 116 117 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ 118 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ 119 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 120 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 121 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 122 #define EMAC_DEF_RX_NUM_DESC (128) 123 #define EMAC_DEF_TX_NUM_DESC (128) 124 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 125 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 126 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 127 128 /* Buffer descriptor parameters */ 129 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ 130 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ 131 132 /* EMAC register related defines */ 133 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 134 #define EMAC_NUM_MULTICAST_BITS (64) 135 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 136 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 137 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 138 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) 139 #define EMAC_INT_MASK_CLEAR (0xFF) 140 141 /* RX MBP register bit positions */ 142 #define EMAC_RXMBP_PASSCRC_MASK BIT(30) 143 #define EMAC_RXMBP_QOSEN_MASK BIT(29) 144 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) 145 #define EMAC_RXMBP_CMFEN_MASK BIT(24) 146 #define EMAC_RXMBP_CSFEN_MASK BIT(23) 147 #define EMAC_RXMBP_CEFEN_MASK BIT(22) 148 #define EMAC_RXMBP_CAFEN_MASK BIT(21) 149 #define EMAC_RXMBP_PROMCH_SHIFT (16) 150 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) 151 #define EMAC_RXMBP_BROADEN_MASK BIT(13) 152 #define EMAC_RXMBP_BROADCH_SHIFT (8) 153 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) 154 #define EMAC_RXMBP_MULTIEN_MASK BIT(5) 155 #define EMAC_RXMBP_MULTICH_SHIFT (0) 156 #define EMAC_RXMBP_MULTICH_MASK (0x7) 157 #define EMAC_RXMBP_CHMASK (0x7) 158 159 /* EMAC register definitions/bit maps used */ 160 # define EMAC_MBP_RXPROMISC (0x00200000) 161 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) 162 # define EMAC_MBP_RXBCAST (0x00002000) 163 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) 164 # define EMAC_MBP_RXMCAST (0x00000020) 165 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) 166 167 /* EMAC mac_control register */ 168 #define EMAC_MACCONTROL_TXPTYPE BIT(9) 169 #define EMAC_MACCONTROL_TXPACEEN BIT(6) 170 #define EMAC_MACCONTROL_GMIIEN BIT(5) 171 #define EMAC_MACCONTROL_GIGABITEN BIT(7) 172 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) 173 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) 174 175 /* GIGABIT MODE related bits */ 176 #define EMAC_DM646X_MACCONTORL_GIG BIT(7) 177 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) 178 179 /* EMAC mac_status register */ 180 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) 181 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) 182 #define EMAC_MACSTATUS_TXERRCH_MASK (0x7) 183 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) 184 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) 185 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) 186 #define EMAC_MACSTATUS_RXERRCH_MASK (0x7) 187 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) 188 189 /* EMAC RX register masks */ 190 #define EMAC_RX_MAX_LEN_MASK (0xFFFF) 191 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) 192 193 /* MAC_IN_VECTOR (0x180) register bit fields */ 194 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) 195 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) 196 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) 197 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) 198 199 /** NOTE:: For DM646x the IN_VECTOR has changed */ 200 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) 201 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) 202 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) 203 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) 204 205 /* CPPI bit positions */ 206 #define EMAC_CPPI_SOP_BIT BIT(31) 207 #define EMAC_CPPI_EOP_BIT BIT(30) 208 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) 209 #define EMAC_CPPI_EOQ_BIT BIT(28) 210 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) 211 #define EMAC_CPPI_PASS_CRC_BIT BIT(26) 212 #define EMAC_RX_BD_BUF_SIZE (0xFFFF) 213 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ 214 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) 215 216 /* Max hardware defines */ 217 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ 218 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 219 220 /* EMAC Peripheral Device Register Memory Layout structure */ 221 #define EMAC_MACINVECTOR 0x90 222 223 #define EMAC_DM646X_MACEOIVECTOR 0x94 224 225 #define EMAC_MACINTSTATRAW 0xB0 226 #define EMAC_MACINTSTATMASKED 0xB4 227 #define EMAC_MACINTMASKSET 0xB8 228 #define EMAC_MACINTMASKCLEAR 0xBC 229 230 #define EMAC_RXMBPENABLE 0x100 231 #define EMAC_RXUNICASTSET 0x104 232 #define EMAC_RXUNICASTCLEAR 0x108 233 #define EMAC_RXMAXLEN 0x10C 234 #define EMAC_RXBUFFEROFFSET 0x110 235 #define EMAC_RXFILTERLOWTHRESH 0x114 236 237 #define EMAC_MACCONTROL 0x160 238 #define EMAC_MACSTATUS 0x164 239 #define EMAC_EMCONTROL 0x168 240 #define EMAC_FIFOCONTROL 0x16C 241 #define EMAC_MACCONFIG 0x170 242 #define EMAC_SOFTRESET 0x174 243 #define EMAC_MACSRCADDRLO 0x1D0 244 #define EMAC_MACSRCADDRHI 0x1D4 245 #define EMAC_MACHASH1 0x1D8 246 #define EMAC_MACHASH2 0x1DC 247 #define EMAC_MACADDRLO 0x500 248 #define EMAC_MACADDRHI 0x504 249 #define EMAC_MACINDEX 0x508 250 251 /* EMAC statistics registers */ 252 #define EMAC_RXGOODFRAMES 0x200 253 #define EMAC_RXBCASTFRAMES 0x204 254 #define EMAC_RXMCASTFRAMES 0x208 255 #define EMAC_RXPAUSEFRAMES 0x20C 256 #define EMAC_RXCRCERRORS 0x210 257 #define EMAC_RXALIGNCODEERRORS 0x214 258 #define EMAC_RXOVERSIZED 0x218 259 #define EMAC_RXJABBER 0x21C 260 #define EMAC_RXUNDERSIZED 0x220 261 #define EMAC_RXFRAGMENTS 0x224 262 #define EMAC_RXFILTERED 0x228 263 #define EMAC_RXQOSFILTERED 0x22C 264 #define EMAC_RXOCTETS 0x230 265 #define EMAC_TXGOODFRAMES 0x234 266 #define EMAC_TXBCASTFRAMES 0x238 267 #define EMAC_TXMCASTFRAMES 0x23C 268 #define EMAC_TXPAUSEFRAMES 0x240 269 #define EMAC_TXDEFERRED 0x244 270 #define EMAC_TXCOLLISION 0x248 271 #define EMAC_TXSINGLECOLL 0x24C 272 #define EMAC_TXMULTICOLL 0x250 273 #define EMAC_TXEXCESSIVECOLL 0x254 274 #define EMAC_TXLATECOLL 0x258 275 #define EMAC_TXUNDERRUN 0x25C 276 #define EMAC_TXCARRIERSENSE 0x260 277 #define EMAC_TXOCTETS 0x264 278 #define EMAC_NETOCTETS 0x280 279 #define EMAC_RXSOFOVERRUNS 0x284 280 #define EMAC_RXMOFOVERRUNS 0x288 281 #define EMAC_RXDMAOVERRUNS 0x28C 282 283 /* EMAC DM644x control registers */ 284 #define EMAC_CTRL_EWCTL (0x4) 285 #define EMAC_CTRL_EWINTTCNT (0x8) 286 287 /* EMAC DM644x control module masks */ 288 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF 289 #define EMAC_DM644X_INTMIN_INTVL 0x1 290 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 291 292 /* EMAC DM646X control module registers */ 293 #define EMAC_DM646X_CMINTCTRL 0x0C 294 #define EMAC_DM646X_CMRXINTEN 0x14 295 #define EMAC_DM646X_CMTXINTEN 0x18 296 #define EMAC_DM646X_CMRXINTMAX 0x70 297 #define EMAC_DM646X_CMTXINTMAX 0x74 298 299 /* EMAC DM646X control module masks */ 300 #define EMAC_DM646X_INTPACEEN (0x3 << 16) 301 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) 302 #define EMAC_DM646X_CMINTMAX_CNT 63 303 #define EMAC_DM646X_CMINTMIN_CNT 2 304 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) 305 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) 306 307 308 /* EMAC EOI codes for C0 */ 309 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 310 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 311 312 /* EMAC Stats Clear Mask */ 313 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 314 315 /* emac_priv: EMAC private data structure 316 * 317 * EMAC adapter private data structure 318 */ 319 struct emac_priv { 320 u32 msg_enable; 321 struct net_device *ndev; 322 struct platform_device *pdev; 323 struct napi_struct napi; 324 char mac_addr[6]; 325 void __iomem *remap_addr; 326 u32 emac_base_phys; 327 void __iomem *emac_base; 328 void __iomem *ctrl_base; 329 struct cpdma_ctlr *dma; 330 struct cpdma_chan *txchan; 331 struct cpdma_chan *rxchan; 332 u32 link; /* 1=link on, 0=link off */ 333 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 334 u32 duplex; /* Link duplex: 0=Half, 1=Full */ 335 u32 rx_buf_size; 336 u32 isr_count; 337 u32 coal_intvl; 338 u32 bus_freq_mhz; 339 u8 rmii_en; 340 u8 version; 341 u32 mac_hash1; 342 u32 mac_hash2; 343 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 344 u32 rx_addr_type; 345 atomic_t cur_tx; 346 const char *phy_id; 347 #ifdef CONFIG_OF 348 struct device_node *phy_node; 349 #endif 350 struct phy_device *phydev; 351 spinlock_t lock; 352 /*platform specific members*/ 353 void (*int_enable) (void); 354 void (*int_disable) (void); 355 }; 356 357 /* EMAC TX Host Error description strings */ 358 static char *emac_txhost_errcodes[16] = { 359 "No error", "SOP error", "Ownership bit not set in SOP buffer", 360 "Zero Next Buffer Descriptor Pointer Without EOP", 361 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", 362 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 363 "Reserved", "Reserved", "Reserved", "Reserved" 364 }; 365 366 /* EMAC RX Host Error description strings */ 367 static char *emac_rxhost_errcodes[16] = { 368 "No error", "Reserved", "Ownership bit not set in input buffer", 369 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", 370 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 371 "Reserved", "Reserved", "Reserved", "Reserved" 372 }; 373 374 /* Helper macros */ 375 #define emac_read(reg) ioread32(priv->emac_base + (reg)) 376 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) 377 378 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 379 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 380 381 /** 382 * emac_dump_regs - Dump important EMAC registers to debug terminal 383 * @priv: The DaVinci EMAC private adapter structure 384 * 385 * Executes ethtool set cmd & sets phy mode 386 * 387 */ 388 static void emac_dump_regs(struct emac_priv *priv) 389 { 390 struct device *emac_dev = &priv->ndev->dev; 391 392 /* Print important registers in EMAC */ 393 dev_info(emac_dev, "EMAC Basic registers\n"); 394 if (priv->version == EMAC_VERSION_1) { 395 dev_info(emac_dev, "EMAC: EWCTL: %08X, EWINTTCNT: %08X\n", 396 emac_ctrl_read(EMAC_CTRL_EWCTL), 397 emac_ctrl_read(EMAC_CTRL_EWINTTCNT)); 398 } 399 dev_info(emac_dev, "EMAC: EmuControl:%08X, FifoControl: %08X\n", 400 emac_read(EMAC_EMCONTROL), emac_read(EMAC_FIFOCONTROL)); 401 dev_info(emac_dev, "EMAC: MBPEnable:%08X, RXUnicastSet: %08X, "\ 402 "RXMaxLen=%08X\n", emac_read(EMAC_RXMBPENABLE), 403 emac_read(EMAC_RXUNICASTSET), emac_read(EMAC_RXMAXLEN)); 404 dev_info(emac_dev, "EMAC: MacControl:%08X, MacStatus: %08X, "\ 405 "MacConfig=%08X\n", emac_read(EMAC_MACCONTROL), 406 emac_read(EMAC_MACSTATUS), emac_read(EMAC_MACCONFIG)); 407 dev_info(emac_dev, "EMAC Statistics\n"); 408 dev_info(emac_dev, "EMAC: rx_good_frames:%d\n", 409 emac_read(EMAC_RXGOODFRAMES)); 410 dev_info(emac_dev, "EMAC: rx_broadcast_frames:%d\n", 411 emac_read(EMAC_RXBCASTFRAMES)); 412 dev_info(emac_dev, "EMAC: rx_multicast_frames:%d\n", 413 emac_read(EMAC_RXMCASTFRAMES)); 414 dev_info(emac_dev, "EMAC: rx_pause_frames:%d\n", 415 emac_read(EMAC_RXPAUSEFRAMES)); 416 dev_info(emac_dev, "EMAC: rx_crcerrors:%d\n", 417 emac_read(EMAC_RXCRCERRORS)); 418 dev_info(emac_dev, "EMAC: rx_align_code_errors:%d\n", 419 emac_read(EMAC_RXALIGNCODEERRORS)); 420 dev_info(emac_dev, "EMAC: rx_oversized_frames:%d\n", 421 emac_read(EMAC_RXOVERSIZED)); 422 dev_info(emac_dev, "EMAC: rx_jabber_frames:%d\n", 423 emac_read(EMAC_RXJABBER)); 424 dev_info(emac_dev, "EMAC: rx_undersized_frames:%d\n", 425 emac_read(EMAC_RXUNDERSIZED)); 426 dev_info(emac_dev, "EMAC: rx_fragments:%d\n", 427 emac_read(EMAC_RXFRAGMENTS)); 428 dev_info(emac_dev, "EMAC: rx_filtered_frames:%d\n", 429 emac_read(EMAC_RXFILTERED)); 430 dev_info(emac_dev, "EMAC: rx_qos_filtered_frames:%d\n", 431 emac_read(EMAC_RXQOSFILTERED)); 432 dev_info(emac_dev, "EMAC: rx_octets:%d\n", 433 emac_read(EMAC_RXOCTETS)); 434 dev_info(emac_dev, "EMAC: tx_goodframes:%d\n", 435 emac_read(EMAC_TXGOODFRAMES)); 436 dev_info(emac_dev, "EMAC: tx_bcastframes:%d\n", 437 emac_read(EMAC_TXBCASTFRAMES)); 438 dev_info(emac_dev, "EMAC: tx_mcastframes:%d\n", 439 emac_read(EMAC_TXMCASTFRAMES)); 440 dev_info(emac_dev, "EMAC: tx_pause_frames:%d\n", 441 emac_read(EMAC_TXPAUSEFRAMES)); 442 dev_info(emac_dev, "EMAC: tx_deferred_frames:%d\n", 443 emac_read(EMAC_TXDEFERRED)); 444 dev_info(emac_dev, "EMAC: tx_collision_frames:%d\n", 445 emac_read(EMAC_TXCOLLISION)); 446 dev_info(emac_dev, "EMAC: tx_single_coll_frames:%d\n", 447 emac_read(EMAC_TXSINGLECOLL)); 448 dev_info(emac_dev, "EMAC: tx_mult_coll_frames:%d\n", 449 emac_read(EMAC_TXMULTICOLL)); 450 dev_info(emac_dev, "EMAC: tx_excessive_collisions:%d\n", 451 emac_read(EMAC_TXEXCESSIVECOLL)); 452 dev_info(emac_dev, "EMAC: tx_late_collisions:%d\n", 453 emac_read(EMAC_TXLATECOLL)); 454 dev_info(emac_dev, "EMAC: tx_underrun:%d\n", 455 emac_read(EMAC_TXUNDERRUN)); 456 dev_info(emac_dev, "EMAC: tx_carrier_sense_errors:%d\n", 457 emac_read(EMAC_TXCARRIERSENSE)); 458 dev_info(emac_dev, "EMAC: tx_octets:%d\n", 459 emac_read(EMAC_TXOCTETS)); 460 dev_info(emac_dev, "EMAC: net_octets:%d\n", 461 emac_read(EMAC_NETOCTETS)); 462 dev_info(emac_dev, "EMAC: rx_sof_overruns:%d\n", 463 emac_read(EMAC_RXSOFOVERRUNS)); 464 dev_info(emac_dev, "EMAC: rx_mof_overruns:%d\n", 465 emac_read(EMAC_RXMOFOVERRUNS)); 466 dev_info(emac_dev, "EMAC: rx_dma_overruns:%d\n", 467 emac_read(EMAC_RXDMAOVERRUNS)); 468 469 cpdma_ctlr_dump(priv->dma); 470 } 471 472 /** 473 * emac_get_drvinfo - Get EMAC driver information 474 * @ndev: The DaVinci EMAC network adapter 475 * @info: ethtool info structure containing name and version 476 * 477 * Returns EMAC driver information (name and version) 478 * 479 */ 480 static void emac_get_drvinfo(struct net_device *ndev, 481 struct ethtool_drvinfo *info) 482 { 483 strcpy(info->driver, emac_version_string); 484 strcpy(info->version, EMAC_MODULE_VERSION); 485 } 486 487 /** 488 * emac_get_settings - Get EMAC settings 489 * @ndev: The DaVinci EMAC network adapter 490 * @ecmd: ethtool command 491 * 492 * Executes ethool get command 493 * 494 */ 495 static int emac_get_settings(struct net_device *ndev, 496 struct ethtool_cmd *ecmd) 497 { 498 struct emac_priv *priv = netdev_priv(ndev); 499 if (priv->phydev) 500 return phy_ethtool_gset(priv->phydev, ecmd); 501 else 502 return -EOPNOTSUPP; 503 504 } 505 506 /** 507 * emac_set_settings - Set EMAC settings 508 * @ndev: The DaVinci EMAC network adapter 509 * @ecmd: ethtool command 510 * 511 * Executes ethool set command 512 * 513 */ 514 static int emac_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 515 { 516 struct emac_priv *priv = netdev_priv(ndev); 517 if (priv->phydev) 518 return phy_ethtool_sset(priv->phydev, ecmd); 519 else 520 return -EOPNOTSUPP; 521 522 } 523 524 /** 525 * emac_get_coalesce - Get interrupt coalesce settings for this device 526 * @ndev : The DaVinci EMAC network adapter 527 * @coal : ethtool coalesce settings structure 528 * 529 * Fetch the current interrupt coalesce settings 530 * 531 */ 532 static int emac_get_coalesce(struct net_device *ndev, 533 struct ethtool_coalesce *coal) 534 { 535 struct emac_priv *priv = netdev_priv(ndev); 536 537 coal->rx_coalesce_usecs = priv->coal_intvl; 538 return 0; 539 540 } 541 542 /** 543 * emac_set_coalesce - Set interrupt coalesce settings for this device 544 * @ndev : The DaVinci EMAC network adapter 545 * @coal : ethtool coalesce settings structure 546 * 547 * Set interrupt coalesce parameters 548 * 549 */ 550 static int emac_set_coalesce(struct net_device *ndev, 551 struct ethtool_coalesce *coal) 552 { 553 struct emac_priv *priv = netdev_priv(ndev); 554 u32 int_ctrl, num_interrupts = 0; 555 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; 556 557 if (!coal->rx_coalesce_usecs) 558 return -EINVAL; 559 560 coal_intvl = coal->rx_coalesce_usecs; 561 562 switch (priv->version) { 563 case EMAC_VERSION_2: 564 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); 565 prescale = priv->bus_freq_mhz * 4; 566 567 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) 568 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; 569 570 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { 571 /* 572 * Interrupt pacer works with 4us Pulse, we can 573 * throttle further by dilating the 4us pulse. 574 */ 575 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; 576 577 if (addnl_dvdr > 1) { 578 prescale *= addnl_dvdr; 579 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL 580 * addnl_dvdr)) 581 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL 582 * addnl_dvdr); 583 } else { 584 addnl_dvdr = 1; 585 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; 586 } 587 } 588 589 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 590 591 int_ctrl |= EMAC_DM646X_INTPACEEN; 592 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); 593 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); 594 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); 595 596 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); 597 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); 598 599 break; 600 default: 601 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); 602 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); 603 prescale = coal_intvl * priv->bus_freq_mhz; 604 if (prescale > EMAC_DM644X_EWINTCNT_MASK) { 605 prescale = EMAC_DM644X_EWINTCNT_MASK; 606 coal_intvl = prescale / priv->bus_freq_mhz; 607 } 608 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); 609 610 break; 611 } 612 613 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); 614 priv->coal_intvl = coal_intvl; 615 616 return 0; 617 618 } 619 620 621 /* ethtool_ops: DaVinci EMAC Ethtool structure 622 * 623 * Ethtool support for EMAC adapter 624 */ 625 static const struct ethtool_ops ethtool_ops = { 626 .get_drvinfo = emac_get_drvinfo, 627 .get_settings = emac_get_settings, 628 .set_settings = emac_set_settings, 629 .get_link = ethtool_op_get_link, 630 .get_coalesce = emac_get_coalesce, 631 .set_coalesce = emac_set_coalesce, 632 .get_ts_info = ethtool_op_get_ts_info, 633 }; 634 635 /** 636 * emac_update_phystatus - Update Phy status 637 * @priv: The DaVinci EMAC private adapter structure 638 * 639 * Updates phy status and takes action for network queue if required 640 * based upon link status 641 * 642 */ 643 static void emac_update_phystatus(struct emac_priv *priv) 644 { 645 u32 mac_control; 646 u32 new_duplex; 647 u32 cur_duplex; 648 struct net_device *ndev = priv->ndev; 649 650 mac_control = emac_read(EMAC_MACCONTROL); 651 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? 652 DUPLEX_FULL : DUPLEX_HALF; 653 if (priv->phydev) 654 new_duplex = priv->phydev->duplex; 655 else 656 new_duplex = DUPLEX_FULL; 657 658 /* We get called only if link has changed (speed/duplex/status) */ 659 if ((priv->link) && (new_duplex != cur_duplex)) { 660 priv->duplex = new_duplex; 661 if (DUPLEX_FULL == priv->duplex) 662 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); 663 else 664 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); 665 } 666 667 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { 668 mac_control = emac_read(EMAC_MACCONTROL); 669 mac_control |= (EMAC_DM646X_MACCONTORL_GIG | 670 EMAC_DM646X_MACCONTORL_GIGFORCE); 671 } else { 672 /* Clear the GIG bit and GIGFORCE bit */ 673 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | 674 EMAC_DM646X_MACCONTORL_GIG); 675 676 if (priv->rmii_en && (priv->speed == SPEED_100)) 677 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; 678 else 679 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; 680 } 681 682 /* Update mac_control if changed */ 683 emac_write(EMAC_MACCONTROL, mac_control); 684 685 if (priv->link) { 686 /* link ON */ 687 if (!netif_carrier_ok(ndev)) 688 netif_carrier_on(ndev); 689 /* reactivate the transmit queue if it is stopped */ 690 if (netif_running(ndev) && netif_queue_stopped(ndev)) 691 netif_wake_queue(ndev); 692 } else { 693 /* link OFF */ 694 if (netif_carrier_ok(ndev)) 695 netif_carrier_off(ndev); 696 if (!netif_queue_stopped(ndev)) 697 netif_stop_queue(ndev); 698 } 699 } 700 701 /** 702 * hash_get - Calculate hash value from mac address 703 * @addr: mac address to delete from hash table 704 * 705 * Calculates hash value from mac address 706 * 707 */ 708 static u32 hash_get(u8 *addr) 709 { 710 u32 hash; 711 u8 tmpval; 712 int cnt; 713 hash = 0; 714 715 for (cnt = 0; cnt < 2; cnt++) { 716 tmpval = *addr++; 717 hash ^= (tmpval >> 2) ^ (tmpval << 4); 718 tmpval = *addr++; 719 hash ^= (tmpval >> 4) ^ (tmpval << 2); 720 tmpval = *addr++; 721 hash ^= (tmpval >> 6) ^ (tmpval); 722 } 723 724 return hash & 0x3F; 725 } 726 727 /** 728 * hash_add - Hash function to add mac addr from hash table 729 * @priv: The DaVinci EMAC private adapter structure 730 * @mac_addr: mac address to delete from hash table 731 * 732 * Adds mac address to the internal hash table 733 * 734 */ 735 static int hash_add(struct emac_priv *priv, u8 *mac_addr) 736 { 737 struct device *emac_dev = &priv->ndev->dev; 738 u32 rc = 0; 739 u32 hash_bit; 740 u32 hash_value = hash_get(mac_addr); 741 742 if (hash_value >= EMAC_NUM_MULTICAST_BITS) { 743 if (netif_msg_drv(priv)) { 744 dev_err(emac_dev, "DaVinci EMAC: hash_add(): Invalid "\ 745 "Hash %08x, should not be greater than %08x", 746 hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); 747 } 748 return -1; 749 } 750 751 /* set the hash bit only if not previously set */ 752 if (priv->multicast_hash_cnt[hash_value] == 0) { 753 rc = 1; /* hash value changed */ 754 if (hash_value < 32) { 755 hash_bit = BIT(hash_value); 756 priv->mac_hash1 |= hash_bit; 757 } else { 758 hash_bit = BIT((hash_value - 32)); 759 priv->mac_hash2 |= hash_bit; 760 } 761 } 762 763 /* incr counter for num of mcast addr's mapped to "this" hash bit */ 764 ++priv->multicast_hash_cnt[hash_value]; 765 766 return rc; 767 } 768 769 /** 770 * hash_del - Hash function to delete mac addr from hash table 771 * @priv: The DaVinci EMAC private adapter structure 772 * @mac_addr: mac address to delete from hash table 773 * 774 * Removes mac address from the internal hash table 775 * 776 */ 777 static int hash_del(struct emac_priv *priv, u8 *mac_addr) 778 { 779 u32 hash_value; 780 u32 hash_bit; 781 782 hash_value = hash_get(mac_addr); 783 if (priv->multicast_hash_cnt[hash_value] > 0) { 784 /* dec cntr for num of mcast addr's mapped to this hash bit */ 785 --priv->multicast_hash_cnt[hash_value]; 786 } 787 788 /* if counter still > 0, at least one multicast address refers 789 * to this hash bit. so return 0 */ 790 if (priv->multicast_hash_cnt[hash_value] > 0) 791 return 0; 792 793 if (hash_value < 32) { 794 hash_bit = BIT(hash_value); 795 priv->mac_hash1 &= ~hash_bit; 796 } else { 797 hash_bit = BIT((hash_value - 32)); 798 priv->mac_hash2 &= ~hash_bit; 799 } 800 801 /* return 1 to indicate change in mac_hash registers reqd */ 802 return 1; 803 } 804 805 /* EMAC multicast operation */ 806 #define EMAC_MULTICAST_ADD 0 807 #define EMAC_MULTICAST_DEL 1 808 #define EMAC_ALL_MULTI_SET 2 809 #define EMAC_ALL_MULTI_CLR 3 810 811 /** 812 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal) 813 * @priv: The DaVinci EMAC private adapter structure 814 * @action: multicast operation to perform 815 * mac_addr: mac address to set 816 * 817 * Set multicast addresses in EMAC adapter - internal function 818 * 819 */ 820 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) 821 { 822 struct device *emac_dev = &priv->ndev->dev; 823 int update = -1; 824 825 switch (action) { 826 case EMAC_MULTICAST_ADD: 827 update = hash_add(priv, mac_addr); 828 break; 829 case EMAC_MULTICAST_DEL: 830 update = hash_del(priv, mac_addr); 831 break; 832 case EMAC_ALL_MULTI_SET: 833 update = 1; 834 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; 835 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; 836 break; 837 case EMAC_ALL_MULTI_CLR: 838 update = 1; 839 priv->mac_hash1 = 0; 840 priv->mac_hash2 = 0; 841 memset(&(priv->multicast_hash_cnt[0]), 0, 842 sizeof(priv->multicast_hash_cnt[0]) * 843 EMAC_NUM_MULTICAST_BITS); 844 break; 845 default: 846 if (netif_msg_drv(priv)) 847 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ 848 ": bad operation %d", action); 849 break; 850 } 851 852 /* write to the hardware only if the register status chances */ 853 if (update > 0) { 854 emac_write(EMAC_MACHASH1, priv->mac_hash1); 855 emac_write(EMAC_MACHASH2, priv->mac_hash2); 856 } 857 } 858 859 /** 860 * emac_dev_mcast_set - Set multicast address in the EMAC adapter 861 * @ndev: The DaVinci EMAC network adapter 862 * 863 * Set multicast addresses in EMAC adapter 864 * 865 */ 866 static void emac_dev_mcast_set(struct net_device *ndev) 867 { 868 u32 mbp_enable; 869 struct emac_priv *priv = netdev_priv(ndev); 870 871 mbp_enable = emac_read(EMAC_RXMBPENABLE); 872 if (ndev->flags & IFF_PROMISC) { 873 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); 874 mbp_enable |= (EMAC_MBP_RXPROMISC); 875 } else { 876 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); 877 if ((ndev->flags & IFF_ALLMULTI) || 878 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { 879 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 880 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); 881 } 882 if (!netdev_mc_empty(ndev)) { 883 struct netdev_hw_addr *ha; 884 885 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 886 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 887 /* program multicast address list into EMAC hardware */ 888 netdev_for_each_mc_addr(ha, ndev) { 889 emac_add_mcast(priv, EMAC_MULTICAST_ADD, 890 (u8 *) ha->addr); 891 } 892 } else { 893 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); 894 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 895 } 896 } 897 /* Set mbp config register */ 898 emac_write(EMAC_RXMBPENABLE, mbp_enable); 899 } 900 901 /************************************************************************* 902 * EMAC Hardware manipulation 903 *************************************************************************/ 904 905 /** 906 * emac_int_disable - Disable EMAC module interrupt (from adapter) 907 * @priv: The DaVinci EMAC private adapter structure 908 * 909 * Disable EMAC interrupt on the adapter 910 * 911 */ 912 static void emac_int_disable(struct emac_priv *priv) 913 { 914 if (priv->version == EMAC_VERSION_2) { 915 unsigned long flags; 916 917 local_irq_save(flags); 918 919 /* Program C0_Int_En to zero to turn off 920 * interrupts to the CPU */ 921 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); 922 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); 923 /* NOTE: Rx Threshold and Misc interrupts are not disabled */ 924 if (priv->int_disable) 925 priv->int_disable(); 926 927 local_irq_restore(flags); 928 929 } else { 930 /* Set DM644x control registers for interrupt control */ 931 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); 932 } 933 } 934 935 /** 936 * emac_int_enable - Enable EMAC module interrupt (from adapter) 937 * @priv: The DaVinci EMAC private adapter structure 938 * 939 * Enable EMAC interrupt on the adapter 940 * 941 */ 942 static void emac_int_enable(struct emac_priv *priv) 943 { 944 if (priv->version == EMAC_VERSION_2) { 945 if (priv->int_enable) 946 priv->int_enable(); 947 948 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); 949 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); 950 951 /* In addition to turning on interrupt Enable, we need 952 * ack by writing appropriate values to the EOI 953 * register */ 954 955 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 956 957 /* ack rxen only then a new pulse will be generated */ 958 emac_write(EMAC_DM646X_MACEOIVECTOR, 959 EMAC_DM646X_MAC_EOI_C0_RXEN); 960 961 /* ack txen- only then a new pulse will be generated */ 962 emac_write(EMAC_DM646X_MACEOIVECTOR, 963 EMAC_DM646X_MAC_EOI_C0_TXEN); 964 965 } else { 966 /* Set DM644x control registers for interrupt control */ 967 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); 968 } 969 } 970 971 /** 972 * emac_irq - EMAC interrupt handler 973 * @irq: interrupt number 974 * @dev_id: EMAC network adapter data structure ptr 975 * 976 * EMAC Interrupt handler - we only schedule NAPI and not process any packets 977 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function 978 * 979 * Returns interrupt handled condition 980 */ 981 static irqreturn_t emac_irq(int irq, void *dev_id) 982 { 983 struct net_device *ndev = (struct net_device *)dev_id; 984 struct emac_priv *priv = netdev_priv(ndev); 985 986 ++priv->isr_count; 987 if (likely(netif_running(priv->ndev))) { 988 emac_int_disable(priv); 989 napi_schedule(&priv->napi); 990 } else { 991 /* we are closing down, so dont process anything */ 992 } 993 return IRQ_HANDLED; 994 } 995 996 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv) 997 { 998 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size); 999 if (WARN_ON(!skb)) 1000 return NULL; 1001 skb_reserve(skb, NET_IP_ALIGN); 1002 return skb; 1003 } 1004 1005 static void emac_rx_handler(void *token, int len, int status) 1006 { 1007 struct sk_buff *skb = token; 1008 struct net_device *ndev = skb->dev; 1009 struct emac_priv *priv = netdev_priv(ndev); 1010 struct device *emac_dev = &ndev->dev; 1011 int ret; 1012 1013 /* free and bail if we are shutting down */ 1014 if (unlikely(!netif_running(ndev))) { 1015 dev_kfree_skb_any(skb); 1016 return; 1017 } 1018 1019 /* recycle on receive error */ 1020 if (status < 0) { 1021 ndev->stats.rx_errors++; 1022 goto recycle; 1023 } 1024 1025 /* feed received packet up the stack */ 1026 skb_put(skb, len); 1027 skb->protocol = eth_type_trans(skb, ndev); 1028 netif_receive_skb(skb); 1029 ndev->stats.rx_bytes += len; 1030 ndev->stats.rx_packets++; 1031 1032 /* alloc a new packet for receive */ 1033 skb = emac_rx_alloc(priv); 1034 if (!skb) { 1035 if (netif_msg_rx_err(priv) && net_ratelimit()) 1036 dev_err(emac_dev, "failed rx buffer alloc\n"); 1037 return; 1038 } 1039 1040 recycle: 1041 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 1042 skb_tailroom(skb), GFP_KERNEL); 1043 1044 WARN_ON(ret == -ENOMEM); 1045 if (unlikely(ret < 0)) 1046 dev_kfree_skb_any(skb); 1047 } 1048 1049 static void emac_tx_handler(void *token, int len, int status) 1050 { 1051 struct sk_buff *skb = token; 1052 struct net_device *ndev = skb->dev; 1053 struct emac_priv *priv = netdev_priv(ndev); 1054 1055 atomic_dec(&priv->cur_tx); 1056 1057 if (unlikely(netif_queue_stopped(ndev))) 1058 netif_start_queue(ndev); 1059 ndev->stats.tx_packets++; 1060 ndev->stats.tx_bytes += len; 1061 dev_kfree_skb_any(skb); 1062 } 1063 1064 /** 1065 * emac_dev_xmit - EMAC Transmit function 1066 * @skb: SKB pointer 1067 * @ndev: The DaVinci EMAC network adapter 1068 * 1069 * Called by the system to transmit a packet - we queue the packet in 1070 * EMAC hardware transmit queue 1071 * 1072 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) 1073 */ 1074 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) 1075 { 1076 struct device *emac_dev = &ndev->dev; 1077 int ret_code; 1078 struct emac_priv *priv = netdev_priv(ndev); 1079 1080 /* If no link, return */ 1081 if (unlikely(!priv->link)) { 1082 if (netif_msg_tx_err(priv) && net_ratelimit()) 1083 dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); 1084 goto fail_tx; 1085 } 1086 1087 ret_code = skb_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE); 1088 if (unlikely(ret_code < 0)) { 1089 if (netif_msg_tx_err(priv) && net_ratelimit()) 1090 dev_err(emac_dev, "DaVinci EMAC: packet pad failed"); 1091 goto fail_tx; 1092 } 1093 1094 skb_tx_timestamp(skb); 1095 1096 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len, 1097 GFP_KERNEL); 1098 if (unlikely(ret_code != 0)) { 1099 if (netif_msg_tx_err(priv) && net_ratelimit()) 1100 dev_err(emac_dev, "DaVinci EMAC: desc submit failed"); 1101 goto fail_tx; 1102 } 1103 1104 if (atomic_inc_return(&priv->cur_tx) >= EMAC_DEF_TX_NUM_DESC) 1105 netif_stop_queue(ndev); 1106 1107 return NETDEV_TX_OK; 1108 1109 fail_tx: 1110 ndev->stats.tx_dropped++; 1111 netif_stop_queue(ndev); 1112 return NETDEV_TX_BUSY; 1113 } 1114 1115 /** 1116 * emac_dev_tx_timeout - EMAC Transmit timeout function 1117 * @ndev: The DaVinci EMAC network adapter 1118 * 1119 * Called when system detects that a skb timeout period has expired 1120 * potentially due to a fault in the adapter in not being able to send 1121 * it out on the wire. We teardown the TX channel assuming a hardware 1122 * error and re-initialize the TX channel for hardware operation 1123 * 1124 */ 1125 static void emac_dev_tx_timeout(struct net_device *ndev) 1126 { 1127 struct emac_priv *priv = netdev_priv(ndev); 1128 struct device *emac_dev = &ndev->dev; 1129 1130 if (netif_msg_tx_err(priv)) 1131 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); 1132 1133 emac_dump_regs(priv); 1134 1135 ndev->stats.tx_errors++; 1136 emac_int_disable(priv); 1137 cpdma_chan_stop(priv->txchan); 1138 cpdma_chan_start(priv->txchan); 1139 emac_int_enable(priv); 1140 } 1141 1142 /** 1143 * emac_set_type0addr - Set EMAC Type0 mac address 1144 * @priv: The DaVinci EMAC private adapter structure 1145 * @ch: RX channel number 1146 * @mac_addr: MAC address to set in device 1147 * 1148 * Called internally to set Type0 mac address of the adapter (Device) 1149 * 1150 * Returns success (0) or appropriate error code (none as of now) 1151 */ 1152 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1153 { 1154 u32 val; 1155 val = ((mac_addr[5] << 8) | (mac_addr[4])); 1156 emac_write(EMAC_MACSRCADDRLO, val); 1157 1158 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1159 (mac_addr[1] << 8) | (mac_addr[0])); 1160 emac_write(EMAC_MACSRCADDRHI, val); 1161 val = emac_read(EMAC_RXUNICASTSET); 1162 val |= BIT(ch); 1163 emac_write(EMAC_RXUNICASTSET, val); 1164 val = emac_read(EMAC_RXUNICASTCLEAR); 1165 val &= ~BIT(ch); 1166 emac_write(EMAC_RXUNICASTCLEAR, val); 1167 } 1168 1169 /** 1170 * emac_set_type1addr - Set EMAC Type1 mac address 1171 * @priv: The DaVinci EMAC private adapter structure 1172 * @ch: RX channel number 1173 * @mac_addr: MAC address to set in device 1174 * 1175 * Called internally to set Type1 mac address of the adapter (Device) 1176 * 1177 * Returns success (0) or appropriate error code (none as of now) 1178 */ 1179 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1180 { 1181 u32 val; 1182 emac_write(EMAC_MACINDEX, ch); 1183 val = ((mac_addr[5] << 8) | mac_addr[4]); 1184 emac_write(EMAC_MACADDRLO, val); 1185 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1186 (mac_addr[1] << 8) | (mac_addr[0])); 1187 emac_write(EMAC_MACADDRHI, val); 1188 emac_set_type0addr(priv, ch, mac_addr); 1189 } 1190 1191 /** 1192 * emac_set_type2addr - Set EMAC Type2 mac address 1193 * @priv: The DaVinci EMAC private adapter structure 1194 * @ch: RX channel number 1195 * @mac_addr: MAC address to set in device 1196 * @index: index into RX address entries 1197 * @match: match parameter for RX address matching logic 1198 * 1199 * Called internally to set Type2 mac address of the adapter (Device) 1200 * 1201 * Returns success (0) or appropriate error code (none as of now) 1202 */ 1203 static void emac_set_type2addr(struct emac_priv *priv, u32 ch, 1204 char *mac_addr, int index, int match) 1205 { 1206 u32 val; 1207 emac_write(EMAC_MACINDEX, index); 1208 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1209 (mac_addr[1] << 8) | (mac_addr[0])); 1210 emac_write(EMAC_MACADDRHI, val); 1211 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ 1212 (match << 19) | BIT(20)); 1213 emac_write(EMAC_MACADDRLO, val); 1214 emac_set_type0addr(priv, ch, mac_addr); 1215 } 1216 1217 /** 1218 * emac_setmac - Set mac address in the adapter (internal function) 1219 * @priv: The DaVinci EMAC private adapter structure 1220 * @ch: RX channel number 1221 * @mac_addr: MAC address to set in device 1222 * 1223 * Called internally to set the mac address of the adapter (Device) 1224 * 1225 * Returns success (0) or appropriate error code (none as of now) 1226 */ 1227 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) 1228 { 1229 struct device *emac_dev = &priv->ndev->dev; 1230 1231 if (priv->rx_addr_type == 0) { 1232 emac_set_type0addr(priv, ch, mac_addr); 1233 } else if (priv->rx_addr_type == 1) { 1234 u32 cnt; 1235 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) 1236 emac_set_type1addr(priv, ch, mac_addr); 1237 } else if (priv->rx_addr_type == 2) { 1238 emac_set_type2addr(priv, ch, mac_addr, ch, 1); 1239 emac_set_type0addr(priv, ch, mac_addr); 1240 } else { 1241 if (netif_msg_drv(priv)) 1242 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); 1243 } 1244 } 1245 1246 /** 1247 * emac_dev_setmac_addr - Set mac address in the adapter 1248 * @ndev: The DaVinci EMAC network adapter 1249 * @addr: MAC address to set in device 1250 * 1251 * Called by the system to set the mac address of the adapter (Device) 1252 * 1253 * Returns success (0) or appropriate error code (none as of now) 1254 */ 1255 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) 1256 { 1257 struct emac_priv *priv = netdev_priv(ndev); 1258 struct device *emac_dev = &priv->ndev->dev; 1259 struct sockaddr *sa = addr; 1260 1261 if (!is_valid_ether_addr(sa->sa_data)) 1262 return -EADDRNOTAVAIL; 1263 1264 /* Store mac addr in priv and rx channel and set it in EMAC hw */ 1265 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1266 memcpy(ndev->dev_addr, sa->sa_data, ndev->addr_len); 1267 ndev->addr_assign_type &= ~NET_ADDR_RANDOM; 1268 1269 /* MAC address is configured only after the interface is enabled. */ 1270 if (netif_running(ndev)) { 1271 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1272 } 1273 1274 if (netif_msg_drv(priv)) 1275 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", 1276 priv->mac_addr); 1277 1278 return 0; 1279 } 1280 1281 /** 1282 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception 1283 * @priv: The DaVinci EMAC private adapter structure 1284 * 1285 * Enables EMAC hardware for packet processing - enables PHY, enables RX 1286 * for packet reception and enables device interrupts and then NAPI 1287 * 1288 * Returns success (0) or appropriate error code (none right now) 1289 */ 1290 static int emac_hw_enable(struct emac_priv *priv) 1291 { 1292 u32 val, mbp_enable, mac_control; 1293 1294 /* Soft reset */ 1295 emac_write(EMAC_SOFTRESET, 1); 1296 while (emac_read(EMAC_SOFTRESET)) 1297 cpu_relax(); 1298 1299 /* Disable interrupt & Set pacing for more interrupts initially */ 1300 emac_int_disable(priv); 1301 1302 /* Full duplex enable bit set when auto negotiation happens */ 1303 mac_control = 1304 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | 1305 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | 1306 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | 1307 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); 1308 emac_write(EMAC_MACCONTROL, mac_control); 1309 1310 mbp_enable = 1311 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | 1312 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | 1313 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | 1314 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | 1315 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | 1316 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | 1317 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | 1318 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ 1319 EMAC_RXMBP_PROMCH_SHIFT) | 1320 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | 1321 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ 1322 EMAC_RXMBP_BROADCH_SHIFT) | 1323 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | 1324 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ 1325 EMAC_RXMBP_MULTICH_SHIFT)); 1326 emac_write(EMAC_RXMBPENABLE, mbp_enable); 1327 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & 1328 EMAC_RX_MAX_LEN_MASK)); 1329 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & 1330 EMAC_RX_BUFFER_OFFSET_MASK)); 1331 emac_write(EMAC_RXFILTERLOWTHRESH, 0); 1332 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); 1333 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; 1334 1335 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); 1336 1337 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1338 1339 /* Enable MII */ 1340 val = emac_read(EMAC_MACCONTROL); 1341 val |= (EMAC_MACCONTROL_GMIIEN); 1342 emac_write(EMAC_MACCONTROL, val); 1343 1344 /* Enable NAPI and interrupts */ 1345 napi_enable(&priv->napi); 1346 emac_int_enable(priv); 1347 return 0; 1348 1349 } 1350 1351 /** 1352 * emac_poll - EMAC NAPI Poll function 1353 * @ndev: The DaVinci EMAC network adapter 1354 * @budget: Number of receive packets to process (as told by NAPI layer) 1355 * 1356 * NAPI Poll function implemented to process packets as per budget. We check 1357 * the type of interrupt on the device and accordingly call the TX or RX 1358 * packet processing functions. We follow the budget for RX processing and 1359 * also put a cap on number of TX pkts processed through config param. The 1360 * NAPI schedule function is called if more packets pending. 1361 * 1362 * Returns number of packets received (in most cases; else TX pkts - rarely) 1363 */ 1364 static int emac_poll(struct napi_struct *napi, int budget) 1365 { 1366 unsigned int mask; 1367 struct emac_priv *priv = container_of(napi, struct emac_priv, napi); 1368 struct net_device *ndev = priv->ndev; 1369 struct device *emac_dev = &ndev->dev; 1370 u32 status = 0; 1371 u32 num_tx_pkts = 0, num_rx_pkts = 0; 1372 1373 /* Check interrupt vectors and call packet processing */ 1374 status = emac_read(EMAC_MACINVECTOR); 1375 1376 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; 1377 1378 if (priv->version == EMAC_VERSION_2) 1379 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; 1380 1381 if (status & mask) { 1382 num_tx_pkts = cpdma_chan_process(priv->txchan, 1383 EMAC_DEF_TX_MAX_SERVICE); 1384 } /* TX processing */ 1385 1386 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; 1387 1388 if (priv->version == EMAC_VERSION_2) 1389 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; 1390 1391 if (status & mask) { 1392 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget); 1393 } /* RX processing */ 1394 1395 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; 1396 if (priv->version == EMAC_VERSION_2) 1397 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; 1398 1399 if (unlikely(status & mask)) { 1400 u32 ch, cause; 1401 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); 1402 netif_stop_queue(ndev); 1403 napi_disable(&priv->napi); 1404 1405 status = emac_read(EMAC_MACSTATUS); 1406 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> 1407 EMAC_MACSTATUS_TXERRCODE_SHIFT); 1408 if (cause) { 1409 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> 1410 EMAC_MACSTATUS_TXERRCH_SHIFT); 1411 if (net_ratelimit()) { 1412 dev_err(emac_dev, "TX Host error %s on ch=%d\n", 1413 &emac_txhost_errcodes[cause][0], ch); 1414 } 1415 } 1416 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> 1417 EMAC_MACSTATUS_RXERRCODE_SHIFT); 1418 if (cause) { 1419 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> 1420 EMAC_MACSTATUS_RXERRCH_SHIFT); 1421 if (netif_msg_hw(priv) && net_ratelimit()) 1422 dev_err(emac_dev, "RX Host error %s on ch=%d\n", 1423 &emac_rxhost_errcodes[cause][0], ch); 1424 } 1425 } else if (num_rx_pkts < budget) { 1426 napi_complete(napi); 1427 emac_int_enable(priv); 1428 } 1429 1430 return num_rx_pkts; 1431 } 1432 1433 #ifdef CONFIG_NET_POLL_CONTROLLER 1434 /** 1435 * emac_poll_controller - EMAC Poll controller function 1436 * @ndev: The DaVinci EMAC network adapter 1437 * 1438 * Polled functionality used by netconsole and others in non interrupt mode 1439 * 1440 */ 1441 void emac_poll_controller(struct net_device *ndev) 1442 { 1443 struct emac_priv *priv = netdev_priv(ndev); 1444 1445 emac_int_disable(priv); 1446 emac_irq(ndev->irq, ndev); 1447 emac_int_enable(priv); 1448 } 1449 #endif 1450 1451 static void emac_adjust_link(struct net_device *ndev) 1452 { 1453 struct emac_priv *priv = netdev_priv(ndev); 1454 struct phy_device *phydev = priv->phydev; 1455 unsigned long flags; 1456 int new_state = 0; 1457 1458 spin_lock_irqsave(&priv->lock, flags); 1459 1460 if (phydev->link) { 1461 /* check the mode of operation - full/half duplex */ 1462 if (phydev->duplex != priv->duplex) { 1463 new_state = 1; 1464 priv->duplex = phydev->duplex; 1465 } 1466 if (phydev->speed != priv->speed) { 1467 new_state = 1; 1468 priv->speed = phydev->speed; 1469 } 1470 if (!priv->link) { 1471 new_state = 1; 1472 priv->link = 1; 1473 } 1474 1475 } else if (priv->link) { 1476 new_state = 1; 1477 priv->link = 0; 1478 priv->speed = 0; 1479 priv->duplex = ~0; 1480 } 1481 if (new_state) { 1482 emac_update_phystatus(priv); 1483 phy_print_status(priv->phydev); 1484 } 1485 1486 spin_unlock_irqrestore(&priv->lock, flags); 1487 } 1488 1489 /************************************************************************* 1490 * Linux Driver Model 1491 *************************************************************************/ 1492 1493 /** 1494 * emac_devioctl - EMAC adapter ioctl 1495 * @ndev: The DaVinci EMAC network adapter 1496 * @ifrq: request parameter 1497 * @cmd: command parameter 1498 * 1499 * EMAC driver ioctl function 1500 * 1501 * Returns success(0) or appropriate error code 1502 */ 1503 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) 1504 { 1505 struct emac_priv *priv = netdev_priv(ndev); 1506 1507 if (!(netif_running(ndev))) 1508 return -EINVAL; 1509 1510 /* TODO: Add phy read and write and private statistics get feature */ 1511 1512 return phy_mii_ioctl(priv->phydev, ifrq, cmd); 1513 } 1514 1515 static int match_first_device(struct device *dev, void *data) 1516 { 1517 return !strncmp(dev_name(dev), "davinci_mdio", 12); 1518 } 1519 1520 /** 1521 * emac_dev_open - EMAC device open 1522 * @ndev: The DaVinci EMAC network adapter 1523 * 1524 * Called when system wants to start the interface. We init TX/RX channels 1525 * and enable the hardware for packet reception/transmission and start the 1526 * network queue. 1527 * 1528 * Returns 0 for a successful open, or appropriate error code 1529 */ 1530 static int emac_dev_open(struct net_device *ndev) 1531 { 1532 struct device *emac_dev = &ndev->dev; 1533 u32 cnt; 1534 struct resource *res; 1535 int q, m, ret; 1536 int i = 0; 1537 int k = 0; 1538 struct emac_priv *priv = netdev_priv(ndev); 1539 1540 pm_runtime_get(&priv->pdev->dev); 1541 1542 netif_carrier_off(ndev); 1543 for (cnt = 0; cnt < ETH_ALEN; cnt++) 1544 ndev->dev_addr[cnt] = priv->mac_addr[cnt]; 1545 1546 /* Configuration items */ 1547 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; 1548 1549 priv->mac_hash1 = 0; 1550 priv->mac_hash2 = 0; 1551 emac_write(EMAC_MACHASH1, 0); 1552 emac_write(EMAC_MACHASH2, 0); 1553 1554 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) { 1555 struct sk_buff *skb = emac_rx_alloc(priv); 1556 1557 if (!skb) 1558 break; 1559 1560 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 1561 skb_tailroom(skb), GFP_KERNEL); 1562 if (WARN_ON(ret < 0)) 1563 break; 1564 } 1565 1566 /* Request IRQ */ 1567 1568 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 1569 for (i = res->start; i <= res->end; i++) { 1570 if (request_irq(i, emac_irq, IRQF_DISABLED, 1571 ndev->name, ndev)) 1572 goto rollback; 1573 } 1574 k++; 1575 } 1576 1577 /* Start/Enable EMAC hardware */ 1578 emac_hw_enable(priv); 1579 1580 /* Enable Interrupt pacing if configured */ 1581 if (priv->coal_intvl != 0) { 1582 struct ethtool_coalesce coal; 1583 1584 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1585 emac_set_coalesce(ndev, &coal); 1586 } 1587 1588 cpdma_ctlr_start(priv->dma); 1589 1590 priv->phydev = NULL; 1591 /* use the first phy on the bus if pdata did not give us a phy id */ 1592 if (!priv->phy_id) { 1593 struct device *phy; 1594 1595 phy = bus_find_device(&mdio_bus_type, NULL, NULL, 1596 match_first_device); 1597 if (phy) 1598 priv->phy_id = dev_name(phy); 1599 } 1600 1601 if (priv->phy_id && *priv->phy_id) { 1602 priv->phydev = phy_connect(ndev, priv->phy_id, 1603 &emac_adjust_link, 0, 1604 PHY_INTERFACE_MODE_MII); 1605 1606 if (IS_ERR(priv->phydev)) { 1607 dev_err(emac_dev, "could not connect to phy %s\n", 1608 priv->phy_id); 1609 ret = PTR_ERR(priv->phydev); 1610 priv->phydev = NULL; 1611 goto err; 1612 } 1613 1614 priv->link = 0; 1615 priv->speed = 0; 1616 priv->duplex = ~0; 1617 1618 dev_info(emac_dev, "attached PHY driver [%s] " 1619 "(mii_bus:phy_addr=%s, id=%x)\n", 1620 priv->phydev->drv->name, dev_name(&priv->phydev->dev), 1621 priv->phydev->phy_id); 1622 } else { 1623 /* No PHY , fix the link, speed and duplex settings */ 1624 dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); 1625 priv->link = 1; 1626 priv->speed = SPEED_100; 1627 priv->duplex = DUPLEX_FULL; 1628 emac_update_phystatus(priv); 1629 } 1630 1631 if (!netif_running(ndev)) /* debug only - to avoid compiler warning */ 1632 emac_dump_regs(priv); 1633 1634 if (netif_msg_drv(priv)) 1635 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); 1636 1637 if (priv->phydev) 1638 phy_start(priv->phydev); 1639 1640 return 0; 1641 1642 rollback: 1643 1644 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed"); 1645 1646 for (q = k; k >= 0; k--) { 1647 for (m = i; m >= res->start; m--) 1648 free_irq(m, ndev); 1649 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k-1); 1650 m = res->end; 1651 } 1652 1653 ret = -EBUSY; 1654 err: 1655 pm_runtime_put(&priv->pdev->dev); 1656 return ret; 1657 } 1658 1659 /** 1660 * emac_dev_stop - EMAC device stop 1661 * @ndev: The DaVinci EMAC network adapter 1662 * 1663 * Called when system wants to stop or down the interface. We stop the network 1664 * queue, disable interrupts and cleanup TX/RX channels. 1665 * 1666 * We return the statistics in net_device_stats structure pulled from emac 1667 */ 1668 static int emac_dev_stop(struct net_device *ndev) 1669 { 1670 struct resource *res; 1671 int i = 0; 1672 int irq_num; 1673 struct emac_priv *priv = netdev_priv(ndev); 1674 struct device *emac_dev = &ndev->dev; 1675 1676 /* inform the upper layers. */ 1677 netif_stop_queue(ndev); 1678 napi_disable(&priv->napi); 1679 1680 netif_carrier_off(ndev); 1681 emac_int_disable(priv); 1682 cpdma_ctlr_stop(priv->dma); 1683 emac_write(EMAC_SOFTRESET, 1); 1684 1685 if (priv->phydev) 1686 phy_disconnect(priv->phydev); 1687 1688 /* Free IRQ */ 1689 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { 1690 for (irq_num = res->start; irq_num <= res->end; irq_num++) 1691 free_irq(irq_num, priv->ndev); 1692 i++; 1693 } 1694 1695 if (netif_msg_drv(priv)) 1696 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); 1697 1698 pm_runtime_put(&priv->pdev->dev); 1699 return 0; 1700 } 1701 1702 /** 1703 * emac_dev_getnetstats - EMAC get statistics function 1704 * @ndev: The DaVinci EMAC network adapter 1705 * 1706 * Called when system wants to get statistics from the device. 1707 * 1708 * We return the statistics in net_device_stats structure pulled from emac 1709 */ 1710 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) 1711 { 1712 struct emac_priv *priv = netdev_priv(ndev); 1713 u32 mac_control; 1714 u32 stats_clear_mask; 1715 1716 /* update emac hardware stats and reset the registers*/ 1717 1718 mac_control = emac_read(EMAC_MACCONTROL); 1719 1720 if (mac_control & EMAC_MACCONTROL_GMIIEN) 1721 stats_clear_mask = EMAC_STATS_CLR_MASK; 1722 else 1723 stats_clear_mask = 0; 1724 1725 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); 1726 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); 1727 1728 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + 1729 emac_read(EMAC_TXSINGLECOLL) + 1730 emac_read(EMAC_TXMULTICOLL)); 1731 emac_write(EMAC_TXCOLLISION, stats_clear_mask); 1732 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); 1733 emac_write(EMAC_TXMULTICOLL, stats_clear_mask); 1734 1735 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + 1736 emac_read(EMAC_RXJABBER) + 1737 emac_read(EMAC_RXUNDERSIZED)); 1738 emac_write(EMAC_RXOVERSIZED, stats_clear_mask); 1739 emac_write(EMAC_RXJABBER, stats_clear_mask); 1740 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); 1741 1742 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + 1743 emac_read(EMAC_RXMOFOVERRUNS)); 1744 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); 1745 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); 1746 1747 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); 1748 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); 1749 1750 ndev->stats.tx_carrier_errors += 1751 emac_read(EMAC_TXCARRIERSENSE); 1752 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); 1753 1754 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); 1755 emac_write(EMAC_TXUNDERRUN, stats_clear_mask); 1756 1757 return &ndev->stats; 1758 } 1759 1760 static const struct net_device_ops emac_netdev_ops = { 1761 .ndo_open = emac_dev_open, 1762 .ndo_stop = emac_dev_stop, 1763 .ndo_start_xmit = emac_dev_xmit, 1764 .ndo_set_rx_mode = emac_dev_mcast_set, 1765 .ndo_set_mac_address = emac_dev_setmac_addr, 1766 .ndo_do_ioctl = emac_devioctl, 1767 .ndo_tx_timeout = emac_dev_tx_timeout, 1768 .ndo_get_stats = emac_dev_getnetstats, 1769 #ifdef CONFIG_NET_POLL_CONTROLLER 1770 .ndo_poll_controller = emac_poll_controller, 1771 #endif 1772 }; 1773 1774 #ifdef CONFIG_OF 1775 static struct emac_platform_data 1776 *davinci_emac_of_get_pdata(struct platform_device *pdev, 1777 struct emac_priv *priv) 1778 { 1779 struct device_node *np; 1780 struct emac_platform_data *pdata = NULL; 1781 const u8 *mac_addr; 1782 u32 data; 1783 int ret; 1784 1785 pdata = pdev->dev.platform_data; 1786 if (!pdata) { 1787 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1788 if (!pdata) 1789 goto nodata; 1790 } 1791 1792 np = pdev->dev.of_node; 1793 if (!np) 1794 goto nodata; 1795 else 1796 pdata->version = EMAC_VERSION_2; 1797 1798 if (!is_valid_ether_addr(pdata->mac_addr)) { 1799 mac_addr = of_get_mac_address(np); 1800 if (mac_addr) 1801 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN); 1802 } 1803 1804 ret = of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", &data); 1805 if (!ret) 1806 pdata->ctrl_reg_offset = data; 1807 1808 ret = of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset", 1809 &data); 1810 if (!ret) 1811 pdata->ctrl_mod_reg_offset = data; 1812 1813 ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", &data); 1814 if (!ret) 1815 pdata->ctrl_ram_offset = data; 1816 1817 ret = of_property_read_u32(np, "ti,davinci-ctrl-ram-size", &data); 1818 if (!ret) 1819 pdata->ctrl_ram_size = data; 1820 1821 ret = of_property_read_u32(np, "ti,davinci-rmii-en", &data); 1822 if (!ret) 1823 pdata->rmii_en = data; 1824 1825 ret = of_property_read_u32(np, "ti,davinci-no-bd-ram", &data); 1826 if (!ret) 1827 pdata->no_bd_ram = data; 1828 1829 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 1830 if (!priv->phy_node) 1831 pdata->phy_id = ""; 1832 1833 pdev->dev.platform_data = pdata; 1834 nodata: 1835 return pdata; 1836 } 1837 #else 1838 static struct emac_platform_data 1839 *davinci_emac_of_get_pdata(struct platform_device *pdev, 1840 struct emac_priv *priv) 1841 { 1842 return pdev->dev.platform_data; 1843 } 1844 #endif 1845 /** 1846 * davinci_emac_probe - EMAC device probe 1847 * @pdev: The DaVinci EMAC device that we are removing 1848 * 1849 * Called when probing for emac devicesr. We get details of instances and 1850 * resource information from platform init and register a network device 1851 * and allocate resources necessary for driver to perform 1852 */ 1853 static int __devinit davinci_emac_probe(struct platform_device *pdev) 1854 { 1855 int rc = 0; 1856 struct resource *res; 1857 struct net_device *ndev; 1858 struct emac_priv *priv; 1859 unsigned long size, hw_ram_addr; 1860 struct emac_platform_data *pdata; 1861 struct device *emac_dev; 1862 struct cpdma_params dma_params; 1863 struct clk *emac_clk; 1864 unsigned long emac_bus_frequency; 1865 1866 1867 /* obtain emac clock from kernel */ 1868 emac_clk = clk_get(&pdev->dev, NULL); 1869 if (IS_ERR(emac_clk)) { 1870 dev_err(&pdev->dev, "failed to get EMAC clock\n"); 1871 return -EBUSY; 1872 } 1873 emac_bus_frequency = clk_get_rate(emac_clk); 1874 clk_put(emac_clk); 1875 1876 /* TODO: Probe PHY here if possible */ 1877 1878 ndev = alloc_etherdev(sizeof(struct emac_priv)); 1879 if (!ndev) { 1880 rc = -ENOMEM; 1881 goto no_ndev; 1882 } 1883 1884 platform_set_drvdata(pdev, ndev); 1885 priv = netdev_priv(ndev); 1886 priv->pdev = pdev; 1887 priv->ndev = ndev; 1888 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); 1889 1890 spin_lock_init(&priv->lock); 1891 1892 pdata = davinci_emac_of_get_pdata(pdev, priv); 1893 if (!pdata) { 1894 dev_err(&pdev->dev, "no platform data\n"); 1895 rc = -ENODEV; 1896 goto probe_quit; 1897 } 1898 1899 /* MAC addr and PHY mask , RMII enable info from platform_data */ 1900 memcpy(priv->mac_addr, pdata->mac_addr, 6); 1901 priv->phy_id = pdata->phy_id; 1902 priv->rmii_en = pdata->rmii_en; 1903 priv->version = pdata->version; 1904 priv->int_enable = pdata->interrupt_enable; 1905 priv->int_disable = pdata->interrupt_disable; 1906 1907 priv->coal_intvl = 0; 1908 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); 1909 1910 emac_dev = &ndev->dev; 1911 /* Get EMAC platform data */ 1912 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1913 if (!res) { 1914 dev_err(&pdev->dev,"error getting res\n"); 1915 rc = -ENOENT; 1916 goto probe_quit; 1917 } 1918 1919 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 1920 size = resource_size(res); 1921 if (!request_mem_region(res->start, size, ndev->name)) { 1922 dev_err(&pdev->dev, "failed request_mem_region() for regs\n"); 1923 rc = -ENXIO; 1924 goto probe_quit; 1925 } 1926 1927 priv->remap_addr = ioremap(res->start, size); 1928 if (!priv->remap_addr) { 1929 dev_err(&pdev->dev, "unable to map IO\n"); 1930 rc = -ENOMEM; 1931 release_mem_region(res->start, size); 1932 goto probe_quit; 1933 } 1934 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; 1935 ndev->base_addr = (unsigned long)priv->remap_addr; 1936 1937 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; 1938 1939 hw_ram_addr = pdata->hw_ram_addr; 1940 if (!hw_ram_addr) 1941 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; 1942 1943 memset(&dma_params, 0, sizeof(dma_params)); 1944 dma_params.dev = emac_dev; 1945 dma_params.dmaregs = priv->emac_base; 1946 dma_params.rxthresh = priv->emac_base + 0x120; 1947 dma_params.rxfree = priv->emac_base + 0x140; 1948 dma_params.txhdp = priv->emac_base + 0x600; 1949 dma_params.rxhdp = priv->emac_base + 0x620; 1950 dma_params.txcp = priv->emac_base + 0x640; 1951 dma_params.rxcp = priv->emac_base + 0x660; 1952 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS; 1953 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE; 1954 dma_params.desc_hw_addr = hw_ram_addr; 1955 dma_params.desc_mem_size = pdata->ctrl_ram_size; 1956 dma_params.desc_align = 16; 1957 1958 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 : 1959 (u32 __force)res->start + pdata->ctrl_ram_offset; 1960 1961 priv->dma = cpdma_ctlr_create(&dma_params); 1962 if (!priv->dma) { 1963 dev_err(&pdev->dev, "error initializing DMA\n"); 1964 rc = -ENOMEM; 1965 goto no_dma; 1966 } 1967 1968 priv->txchan = cpdma_chan_create(priv->dma, tx_chan_num(EMAC_DEF_TX_CH), 1969 emac_tx_handler); 1970 priv->rxchan = cpdma_chan_create(priv->dma, rx_chan_num(EMAC_DEF_RX_CH), 1971 emac_rx_handler); 1972 if (WARN_ON(!priv->txchan || !priv->rxchan)) { 1973 rc = -ENOMEM; 1974 goto no_irq_res; 1975 } 1976 1977 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1978 if (!res) { 1979 dev_err(&pdev->dev, "error getting irq res\n"); 1980 rc = -ENOENT; 1981 goto no_irq_res; 1982 } 1983 ndev->irq = res->start; 1984 1985 if (!is_valid_ether_addr(priv->mac_addr)) { 1986 /* Use random MAC if none passed */ 1987 eth_hw_addr_random(ndev); 1988 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len); 1989 dev_warn(&pdev->dev, "using random MAC addr: %pM\n", 1990 priv->mac_addr); 1991 } 1992 1993 ndev->netdev_ops = &emac_netdev_ops; 1994 SET_ETHTOOL_OPS(ndev, ðtool_ops); 1995 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); 1996 1997 /* register the network device */ 1998 SET_NETDEV_DEV(ndev, &pdev->dev); 1999 rc = register_netdev(ndev); 2000 if (rc) { 2001 dev_err(&pdev->dev, "error in register_netdev\n"); 2002 rc = -ENODEV; 2003 goto no_irq_res; 2004 } 2005 2006 2007 if (netif_msg_probe(priv)) { 2008 dev_notice(emac_dev, "DaVinci EMAC Probe found device "\ 2009 "(regs: %p, irq: %d)\n", 2010 (void *)priv->emac_base_phys, ndev->irq); 2011 } 2012 2013 pm_runtime_enable(&pdev->dev); 2014 pm_runtime_resume(&pdev->dev); 2015 2016 return 0; 2017 2018 no_irq_res: 2019 if (priv->txchan) 2020 cpdma_chan_destroy(priv->txchan); 2021 if (priv->rxchan) 2022 cpdma_chan_destroy(priv->rxchan); 2023 cpdma_ctlr_destroy(priv->dma); 2024 no_dma: 2025 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2026 release_mem_region(res->start, resource_size(res)); 2027 iounmap(priv->remap_addr); 2028 2029 probe_quit: 2030 free_netdev(ndev); 2031 no_ndev: 2032 return rc; 2033 } 2034 2035 /** 2036 * davinci_emac_remove - EMAC device remove 2037 * @pdev: The DaVinci EMAC device that we are removing 2038 * 2039 * Called when removing the device driver. We disable clock usage and release 2040 * the resources taken up by the driver and unregister network device 2041 */ 2042 static int __devexit davinci_emac_remove(struct platform_device *pdev) 2043 { 2044 struct resource *res; 2045 struct net_device *ndev = platform_get_drvdata(pdev); 2046 struct emac_priv *priv = netdev_priv(ndev); 2047 2048 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); 2049 2050 platform_set_drvdata(pdev, NULL); 2051 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2052 2053 if (priv->txchan) 2054 cpdma_chan_destroy(priv->txchan); 2055 if (priv->rxchan) 2056 cpdma_chan_destroy(priv->rxchan); 2057 cpdma_ctlr_destroy(priv->dma); 2058 2059 release_mem_region(res->start, resource_size(res)); 2060 2061 unregister_netdev(ndev); 2062 iounmap(priv->remap_addr); 2063 free_netdev(ndev); 2064 2065 return 0; 2066 } 2067 2068 static int davinci_emac_suspend(struct device *dev) 2069 { 2070 struct platform_device *pdev = to_platform_device(dev); 2071 struct net_device *ndev = platform_get_drvdata(pdev); 2072 2073 if (netif_running(ndev)) 2074 emac_dev_stop(ndev); 2075 2076 return 0; 2077 } 2078 2079 static int davinci_emac_resume(struct device *dev) 2080 { 2081 struct platform_device *pdev = to_platform_device(dev); 2082 struct net_device *ndev = platform_get_drvdata(pdev); 2083 2084 if (netif_running(ndev)) 2085 emac_dev_open(ndev); 2086 2087 return 0; 2088 } 2089 2090 static const struct dev_pm_ops davinci_emac_pm_ops = { 2091 .suspend = davinci_emac_suspend, 2092 .resume = davinci_emac_resume, 2093 }; 2094 2095 static const struct of_device_id davinci_emac_of_match[] = { 2096 {.compatible = "ti,davinci-dm6467-emac", }, 2097 {}, 2098 }; 2099 MODULE_DEVICE_TABLE(of, davinci_emac_of_match); 2100 2101 /* davinci_emac_driver: EMAC platform driver structure */ 2102 static struct platform_driver davinci_emac_driver = { 2103 .driver = { 2104 .name = "davinci_emac", 2105 .owner = THIS_MODULE, 2106 .pm = &davinci_emac_pm_ops, 2107 .of_match_table = of_match_ptr(davinci_emac_of_match), 2108 }, 2109 .probe = davinci_emac_probe, 2110 .remove = __devexit_p(davinci_emac_remove), 2111 }; 2112 2113 /** 2114 * davinci_emac_init - EMAC driver module init 2115 * 2116 * Called when initializing the driver. We register the driver with 2117 * the platform. 2118 */ 2119 static int __init davinci_emac_init(void) 2120 { 2121 return platform_driver_register(&davinci_emac_driver); 2122 } 2123 late_initcall(davinci_emac_init); 2124 2125 /** 2126 * davinci_emac_exit - EMAC driver module exit 2127 * 2128 * Called when exiting the driver completely. We unregister the driver with 2129 * the platform and exit 2130 */ 2131 static void __exit davinci_emac_exit(void) 2132 { 2133 platform_driver_unregister(&davinci_emac_driver); 2134 } 2135 module_exit(davinci_emac_exit); 2136 2137 MODULE_LICENSE("GPL"); 2138 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); 2139 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); 2140 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); 2141