1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * DaVinci Ethernet Medium Access Controller 4 * 5 * DaVinci EMAC is based upon CPPI 3.0 TI DMA engine 6 * 7 * Copyright (C) 2009 Texas Instruments. 8 * 9 * --------------------------------------------------------------------------- 10 * History: 11 * 0-5 A number of folks worked on this driver in bits and pieces but the major 12 * contribution came from Suraj Iyer and Anant Gole 13 * 6.0 Anant Gole - rewrote the driver as per Linux conventions 14 * 6.1 Chaithrika U S - added support for Gigabit and RMII features, 15 * PHY layer usage 16 */ 17 18 #include <linux/module.h> 19 #include <linux/kernel.h> 20 #include <linux/sched.h> 21 #include <linux/string.h> 22 #include <linux/timer.h> 23 #include <linux/errno.h> 24 #include <linux/in.h> 25 #include <linux/ioport.h> 26 #include <linux/slab.h> 27 #include <linux/mm.h> 28 #include <linux/interrupt.h> 29 #include <linux/init.h> 30 #include <linux/netdevice.h> 31 #include <linux/etherdevice.h> 32 #include <linux/skbuff.h> 33 #include <linux/ethtool.h> 34 #include <linux/highmem.h> 35 #include <linux/proc_fs.h> 36 #include <linux/ctype.h> 37 #include <linux/spinlock.h> 38 #include <linux/dma-mapping.h> 39 #include <linux/clk.h> 40 #include <linux/platform_device.h> 41 #include <linux/regmap.h> 42 #include <linux/semaphore.h> 43 #include <linux/phy.h> 44 #include <linux/bitops.h> 45 #include <linux/io.h> 46 #include <linux/uaccess.h> 47 #include <linux/pm_runtime.h> 48 #include <linux/davinci_emac.h> 49 #include <linux/of.h> 50 #include <linux/of_address.h> 51 #include <linux/of_device.h> 52 #include <linux/of_mdio.h> 53 #include <linux/of_irq.h> 54 #include <linux/of_net.h> 55 #include <linux/mfd/syscon.h> 56 57 #include <asm/irq.h> 58 #include <asm/page.h> 59 60 #include "cpsw.h" 61 #include "davinci_cpdma.h" 62 63 static int debug_level; 64 module_param(debug_level, int, 0); 65 MODULE_PARM_DESC(debug_level, "DaVinci EMAC debug level (NETIF_MSG bits)"); 66 67 /* Netif debug messages possible */ 68 #define DAVINCI_EMAC_DEBUG (NETIF_MSG_DRV | \ 69 NETIF_MSG_PROBE | \ 70 NETIF_MSG_LINK | \ 71 NETIF_MSG_TIMER | \ 72 NETIF_MSG_IFDOWN | \ 73 NETIF_MSG_IFUP | \ 74 NETIF_MSG_RX_ERR | \ 75 NETIF_MSG_TX_ERR | \ 76 NETIF_MSG_TX_QUEUED | \ 77 NETIF_MSG_INTR | \ 78 NETIF_MSG_TX_DONE | \ 79 NETIF_MSG_RX_STATUS | \ 80 NETIF_MSG_PKTDATA | \ 81 NETIF_MSG_HW | \ 82 NETIF_MSG_WOL) 83 84 /* version info */ 85 #define EMAC_MAJOR_VERSION 6 86 #define EMAC_MINOR_VERSION 1 87 #define EMAC_MODULE_VERSION "6.1" 88 MODULE_VERSION(EMAC_MODULE_VERSION); 89 static const char emac_version_string[] = "TI DaVinci EMAC Linux v6.1"; 90 91 /* Configuration items */ 92 #define EMAC_DEF_PASS_CRC (0) /* Do not pass CRC up to frames */ 93 #define EMAC_DEF_QOS_EN (0) /* EMAC proprietary QoS disabled */ 94 #define EMAC_DEF_NO_BUFF_CHAIN (0) /* No buffer chain */ 95 #define EMAC_DEF_MACCTRL_FRAME_EN (0) /* Discard Maccontrol frames */ 96 #define EMAC_DEF_SHORT_FRAME_EN (0) /* Discard short frames */ 97 #define EMAC_DEF_ERROR_FRAME_EN (0) /* Discard error frames */ 98 #define EMAC_DEF_PROM_EN (0) /* Promiscuous disabled */ 99 #define EMAC_DEF_PROM_CH (0) /* Promiscuous channel is 0 */ 100 #define EMAC_DEF_BCAST_EN (1) /* Broadcast enabled */ 101 #define EMAC_DEF_BCAST_CH (0) /* Broadcast channel is 0 */ 102 #define EMAC_DEF_MCAST_EN (1) /* Multicast enabled */ 103 #define EMAC_DEF_MCAST_CH (0) /* Multicast channel is 0 */ 104 105 #define EMAC_DEF_TXPRIO_FIXED (1) /* TX Priority is fixed */ 106 #define EMAC_DEF_TXPACING_EN (0) /* TX pacing NOT supported*/ 107 108 #define EMAC_DEF_BUFFER_OFFSET (0) /* Buffer offset to DMA (future) */ 109 #define EMAC_DEF_MIN_ETHPKTSIZE (60) /* Minimum ethernet pkt size */ 110 #define EMAC_DEF_MAX_FRAME_SIZE (1500 + 14 + 4 + 4) 111 #define EMAC_DEF_TX_CH (0) /* Default 0th channel */ 112 #define EMAC_DEF_RX_CH (0) /* Default 0th channel */ 113 #define EMAC_DEF_RX_NUM_DESC (128) 114 #define EMAC_DEF_MAX_TX_CH (1) /* Max TX channels configured */ 115 #define EMAC_DEF_MAX_RX_CH (1) /* Max RX channels configured */ 116 #define EMAC_POLL_WEIGHT (64) /* Default NAPI poll weight */ 117 118 /* Buffer descriptor parameters */ 119 #define EMAC_DEF_TX_MAX_SERVICE (32) /* TX max service BD's */ 120 #define EMAC_DEF_RX_MAX_SERVICE (64) /* should = netdev->weight */ 121 122 /* EMAC register related defines */ 123 #define EMAC_ALL_MULTI_REG_VALUE (0xFFFFFFFF) 124 #define EMAC_NUM_MULTICAST_BITS (64) 125 #define EMAC_TX_CONTROL_TX_ENABLE_VAL (0x1) 126 #define EMAC_RX_CONTROL_RX_ENABLE_VAL (0x1) 127 #define EMAC_MAC_HOST_ERR_INTMASK_VAL (0x2) 128 #define EMAC_RX_UNICAST_CLEAR_ALL (0xFF) 129 #define EMAC_INT_MASK_CLEAR (0xFF) 130 131 /* RX MBP register bit positions */ 132 #define EMAC_RXMBP_PASSCRC_MASK BIT(30) 133 #define EMAC_RXMBP_QOSEN_MASK BIT(29) 134 #define EMAC_RXMBP_NOCHAIN_MASK BIT(28) 135 #define EMAC_RXMBP_CMFEN_MASK BIT(24) 136 #define EMAC_RXMBP_CSFEN_MASK BIT(23) 137 #define EMAC_RXMBP_CEFEN_MASK BIT(22) 138 #define EMAC_RXMBP_CAFEN_MASK BIT(21) 139 #define EMAC_RXMBP_PROMCH_SHIFT (16) 140 #define EMAC_RXMBP_PROMCH_MASK (0x7 << 16) 141 #define EMAC_RXMBP_BROADEN_MASK BIT(13) 142 #define EMAC_RXMBP_BROADCH_SHIFT (8) 143 #define EMAC_RXMBP_BROADCH_MASK (0x7 << 8) 144 #define EMAC_RXMBP_MULTIEN_MASK BIT(5) 145 #define EMAC_RXMBP_MULTICH_SHIFT (0) 146 #define EMAC_RXMBP_MULTICH_MASK (0x7) 147 #define EMAC_RXMBP_CHMASK (0x7) 148 149 /* EMAC register definitions/bit maps used */ 150 # define EMAC_MBP_RXPROMISC (0x00200000) 151 # define EMAC_MBP_PROMISCCH(ch) (((ch) & 0x7) << 16) 152 # define EMAC_MBP_RXBCAST (0x00002000) 153 # define EMAC_MBP_BCASTCHAN(ch) (((ch) & 0x7) << 8) 154 # define EMAC_MBP_RXMCAST (0x00000020) 155 # define EMAC_MBP_MCASTCHAN(ch) ((ch) & 0x7) 156 157 /* EMAC mac_control register */ 158 #define EMAC_MACCONTROL_TXPTYPE BIT(9) 159 #define EMAC_MACCONTROL_TXPACEEN BIT(6) 160 #define EMAC_MACCONTROL_GMIIEN BIT(5) 161 #define EMAC_MACCONTROL_GIGABITEN BIT(7) 162 #define EMAC_MACCONTROL_FULLDUPLEXEN BIT(0) 163 #define EMAC_MACCONTROL_RMIISPEED_MASK BIT(15) 164 165 /* GIGABIT MODE related bits */ 166 #define EMAC_DM646X_MACCONTORL_GIG BIT(7) 167 #define EMAC_DM646X_MACCONTORL_GIGFORCE BIT(17) 168 169 /* EMAC mac_status register */ 170 #define EMAC_MACSTATUS_TXERRCODE_MASK (0xF00000) 171 #define EMAC_MACSTATUS_TXERRCODE_SHIFT (20) 172 #define EMAC_MACSTATUS_TXERRCH_MASK (0x70000) 173 #define EMAC_MACSTATUS_TXERRCH_SHIFT (16) 174 #define EMAC_MACSTATUS_RXERRCODE_MASK (0xF000) 175 #define EMAC_MACSTATUS_RXERRCODE_SHIFT (12) 176 #define EMAC_MACSTATUS_RXERRCH_MASK (0x700) 177 #define EMAC_MACSTATUS_RXERRCH_SHIFT (8) 178 179 /* EMAC RX register masks */ 180 #define EMAC_RX_MAX_LEN_MASK (0xFFFF) 181 #define EMAC_RX_BUFFER_OFFSET_MASK (0xFFFF) 182 183 /* MAC_IN_VECTOR (0x180) register bit fields */ 184 #define EMAC_DM644X_MAC_IN_VECTOR_HOST_INT BIT(17) 185 #define EMAC_DM644X_MAC_IN_VECTOR_STATPEND_INT BIT(16) 186 #define EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC BIT(8) 187 #define EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC BIT(0) 188 189 /** NOTE:: For DM646x the IN_VECTOR has changed */ 190 #define EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC BIT(EMAC_DEF_RX_CH) 191 #define EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC BIT(16 + EMAC_DEF_TX_CH) 192 #define EMAC_DM646X_MAC_IN_VECTOR_HOST_INT BIT(26) 193 #define EMAC_DM646X_MAC_IN_VECTOR_STATPEND_INT BIT(27) 194 195 /* CPPI bit positions */ 196 #define EMAC_CPPI_SOP_BIT BIT(31) 197 #define EMAC_CPPI_EOP_BIT BIT(30) 198 #define EMAC_CPPI_OWNERSHIP_BIT BIT(29) 199 #define EMAC_CPPI_EOQ_BIT BIT(28) 200 #define EMAC_CPPI_TEARDOWN_COMPLETE_BIT BIT(27) 201 #define EMAC_CPPI_PASS_CRC_BIT BIT(26) 202 #define EMAC_RX_BD_BUF_SIZE (0xFFFF) 203 #define EMAC_BD_LENGTH_FOR_CACHE (16) /* only CPPI bytes */ 204 #define EMAC_RX_BD_PKT_LENGTH_MASK (0xFFFF) 205 206 /* Max hardware defines */ 207 #define EMAC_MAX_TXRX_CHANNELS (8) /* Max hardware channels */ 208 #define EMAC_DEF_MAX_MULTICAST_ADDRESSES (64) /* Max mcast addr's */ 209 210 /* EMAC Peripheral Device Register Memory Layout structure */ 211 #define EMAC_MACINVECTOR 0x90 212 213 #define EMAC_DM646X_MACEOIVECTOR 0x94 214 215 #define EMAC_MACINTSTATRAW 0xB0 216 #define EMAC_MACINTSTATMASKED 0xB4 217 #define EMAC_MACINTMASKSET 0xB8 218 #define EMAC_MACINTMASKCLEAR 0xBC 219 220 #define EMAC_RXMBPENABLE 0x100 221 #define EMAC_RXUNICASTSET 0x104 222 #define EMAC_RXUNICASTCLEAR 0x108 223 #define EMAC_RXMAXLEN 0x10C 224 #define EMAC_RXBUFFEROFFSET 0x110 225 #define EMAC_RXFILTERLOWTHRESH 0x114 226 227 #define EMAC_MACCONTROL 0x160 228 #define EMAC_MACSTATUS 0x164 229 #define EMAC_EMCONTROL 0x168 230 #define EMAC_FIFOCONTROL 0x16C 231 #define EMAC_MACCONFIG 0x170 232 #define EMAC_SOFTRESET 0x174 233 #define EMAC_MACSRCADDRLO 0x1D0 234 #define EMAC_MACSRCADDRHI 0x1D4 235 #define EMAC_MACHASH1 0x1D8 236 #define EMAC_MACHASH2 0x1DC 237 #define EMAC_MACADDRLO 0x500 238 #define EMAC_MACADDRHI 0x504 239 #define EMAC_MACINDEX 0x508 240 241 /* EMAC statistics registers */ 242 #define EMAC_RXGOODFRAMES 0x200 243 #define EMAC_RXBCASTFRAMES 0x204 244 #define EMAC_RXMCASTFRAMES 0x208 245 #define EMAC_RXPAUSEFRAMES 0x20C 246 #define EMAC_RXCRCERRORS 0x210 247 #define EMAC_RXALIGNCODEERRORS 0x214 248 #define EMAC_RXOVERSIZED 0x218 249 #define EMAC_RXJABBER 0x21C 250 #define EMAC_RXUNDERSIZED 0x220 251 #define EMAC_RXFRAGMENTS 0x224 252 #define EMAC_RXFILTERED 0x228 253 #define EMAC_RXQOSFILTERED 0x22C 254 #define EMAC_RXOCTETS 0x230 255 #define EMAC_TXGOODFRAMES 0x234 256 #define EMAC_TXBCASTFRAMES 0x238 257 #define EMAC_TXMCASTFRAMES 0x23C 258 #define EMAC_TXPAUSEFRAMES 0x240 259 #define EMAC_TXDEFERRED 0x244 260 #define EMAC_TXCOLLISION 0x248 261 #define EMAC_TXSINGLECOLL 0x24C 262 #define EMAC_TXMULTICOLL 0x250 263 #define EMAC_TXEXCESSIVECOLL 0x254 264 #define EMAC_TXLATECOLL 0x258 265 #define EMAC_TXUNDERRUN 0x25C 266 #define EMAC_TXCARRIERSENSE 0x260 267 #define EMAC_TXOCTETS 0x264 268 #define EMAC_NETOCTETS 0x280 269 #define EMAC_RXSOFOVERRUNS 0x284 270 #define EMAC_RXMOFOVERRUNS 0x288 271 #define EMAC_RXDMAOVERRUNS 0x28C 272 273 /* EMAC DM644x control registers */ 274 #define EMAC_CTRL_EWCTL (0x4) 275 #define EMAC_CTRL_EWINTTCNT (0x8) 276 277 /* EMAC DM644x control module masks */ 278 #define EMAC_DM644X_EWINTCNT_MASK 0x1FFFF 279 #define EMAC_DM644X_INTMIN_INTVL 0x1 280 #define EMAC_DM644X_INTMAX_INTVL (EMAC_DM644X_EWINTCNT_MASK) 281 282 /* EMAC DM646X control module registers */ 283 #define EMAC_DM646X_CMINTCTRL 0x0C 284 #define EMAC_DM646X_CMRXINTEN 0x14 285 #define EMAC_DM646X_CMTXINTEN 0x18 286 #define EMAC_DM646X_CMRXINTMAX 0x70 287 #define EMAC_DM646X_CMTXINTMAX 0x74 288 289 /* EMAC DM646X control module masks */ 290 #define EMAC_DM646X_INTPACEEN (0x3 << 16) 291 #define EMAC_DM646X_INTPRESCALE_MASK (0x7FF << 0) 292 #define EMAC_DM646X_CMINTMAX_CNT 63 293 #define EMAC_DM646X_CMINTMIN_CNT 2 294 #define EMAC_DM646X_CMINTMAX_INTVL (1000 / EMAC_DM646X_CMINTMIN_CNT) 295 #define EMAC_DM646X_CMINTMIN_INTVL ((1000 / EMAC_DM646X_CMINTMAX_CNT) + 1) 296 297 298 /* EMAC EOI codes for C0 */ 299 #define EMAC_DM646X_MAC_EOI_C0_RXEN (0x01) 300 #define EMAC_DM646X_MAC_EOI_C0_TXEN (0x02) 301 302 /* EMAC Stats Clear Mask */ 303 #define EMAC_STATS_CLR_MASK (0xFFFFFFFF) 304 305 /* emac_priv: EMAC private data structure 306 * 307 * EMAC adapter private data structure 308 */ 309 struct emac_priv { 310 u32 msg_enable; 311 struct net_device *ndev; 312 struct platform_device *pdev; 313 struct napi_struct napi; 314 char mac_addr[6]; 315 void __iomem *remap_addr; 316 u32 emac_base_phys; 317 void __iomem *emac_base; 318 void __iomem *ctrl_base; 319 struct cpdma_ctlr *dma; 320 struct cpdma_chan *txchan; 321 struct cpdma_chan *rxchan; 322 u32 link; /* 1=link on, 0=link off */ 323 u32 speed; /* 0=Auto Neg, 1=No PHY, 10,100, 1000 - mbps */ 324 u32 duplex; /* Link duplex: 0=Half, 1=Full */ 325 u32 rx_buf_size; 326 u32 isr_count; 327 u32 coal_intvl; 328 u32 bus_freq_mhz; 329 u8 rmii_en; 330 u8 version; 331 u32 mac_hash1; 332 u32 mac_hash2; 333 u32 multicast_hash_cnt[EMAC_NUM_MULTICAST_BITS]; 334 u32 rx_addr_type; 335 const char *phy_id; 336 struct device_node *phy_node; 337 spinlock_t lock; 338 /*platform specific members*/ 339 void (*int_enable) (void); 340 void (*int_disable) (void); 341 }; 342 343 /* EMAC TX Host Error description strings */ 344 static char *emac_txhost_errcodes[16] = { 345 "No error", "SOP error", "Ownership bit not set in SOP buffer", 346 "Zero Next Buffer Descriptor Pointer Without EOP", 347 "Zero Buffer Pointer", "Zero Buffer Length", "Packet Length Error", 348 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 349 "Reserved", "Reserved", "Reserved", "Reserved" 350 }; 351 352 /* EMAC RX Host Error description strings */ 353 static char *emac_rxhost_errcodes[16] = { 354 "No error", "Reserved", "Ownership bit not set in input buffer", 355 "Reserved", "Zero Buffer Pointer", "Reserved", "Reserved", 356 "Reserved", "Reserved", "Reserved", "Reserved", "Reserved", 357 "Reserved", "Reserved", "Reserved", "Reserved" 358 }; 359 360 /* Helper macros */ 361 #define emac_read(reg) ioread32(priv->emac_base + (reg)) 362 #define emac_write(reg, val) iowrite32(val, priv->emac_base + (reg)) 363 364 #define emac_ctrl_read(reg) ioread32((priv->ctrl_base + (reg))) 365 #define emac_ctrl_write(reg, val) iowrite32(val, (priv->ctrl_base + (reg))) 366 367 /** 368 * emac_get_drvinfo - Get EMAC driver information 369 * @ndev: The DaVinci EMAC network adapter 370 * @info: ethtool info structure containing name and version 371 * 372 * Returns EMAC driver information (name and version) 373 * 374 */ 375 static void emac_get_drvinfo(struct net_device *ndev, 376 struct ethtool_drvinfo *info) 377 { 378 strlcpy(info->driver, emac_version_string, sizeof(info->driver)); 379 strlcpy(info->version, EMAC_MODULE_VERSION, sizeof(info->version)); 380 } 381 382 /** 383 * emac_get_coalesce - Get interrupt coalesce settings for this device 384 * @ndev : The DaVinci EMAC network adapter 385 * @coal : ethtool coalesce settings structure 386 * @kernel_coal: ethtool CQE mode setting structure 387 * @extack: extack for reporting error messages 388 * 389 * Fetch the current interrupt coalesce settings 390 * 391 */ 392 static int emac_get_coalesce(struct net_device *ndev, 393 struct ethtool_coalesce *coal, 394 struct kernel_ethtool_coalesce *kernel_coal, 395 struct netlink_ext_ack *extack) 396 { 397 struct emac_priv *priv = netdev_priv(ndev); 398 399 coal->rx_coalesce_usecs = priv->coal_intvl; 400 return 0; 401 402 } 403 404 /** 405 * emac_set_coalesce - Set interrupt coalesce settings for this device 406 * @ndev : The DaVinci EMAC network adapter 407 * @coal : ethtool coalesce settings structure 408 * @kernel_coal: ethtool CQE mode setting structure 409 * @extack: extack for reporting error messages 410 * 411 * Set interrupt coalesce parameters 412 * 413 */ 414 static int emac_set_coalesce(struct net_device *ndev, 415 struct ethtool_coalesce *coal, 416 struct kernel_ethtool_coalesce *kernel_coal, 417 struct netlink_ext_ack *extack) 418 { 419 struct emac_priv *priv = netdev_priv(ndev); 420 u32 int_ctrl, num_interrupts = 0; 421 u32 prescale = 0, addnl_dvdr = 1, coal_intvl = 0; 422 423 if (!coal->rx_coalesce_usecs) { 424 priv->coal_intvl = 0; 425 426 switch (priv->version) { 427 case EMAC_VERSION_2: 428 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, 0); 429 break; 430 default: 431 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, 0); 432 break; 433 } 434 435 return 0; 436 } 437 438 coal_intvl = coal->rx_coalesce_usecs; 439 440 switch (priv->version) { 441 case EMAC_VERSION_2: 442 int_ctrl = emac_ctrl_read(EMAC_DM646X_CMINTCTRL); 443 prescale = priv->bus_freq_mhz * 4; 444 445 if (coal_intvl < EMAC_DM646X_CMINTMIN_INTVL) 446 coal_intvl = EMAC_DM646X_CMINTMIN_INTVL; 447 448 if (coal_intvl > EMAC_DM646X_CMINTMAX_INTVL) { 449 /* 450 * Interrupt pacer works with 4us Pulse, we can 451 * throttle further by dilating the 4us pulse. 452 */ 453 addnl_dvdr = EMAC_DM646X_INTPRESCALE_MASK / prescale; 454 455 if (addnl_dvdr > 1) { 456 prescale *= addnl_dvdr; 457 if (coal_intvl > (EMAC_DM646X_CMINTMAX_INTVL 458 * addnl_dvdr)) 459 coal_intvl = (EMAC_DM646X_CMINTMAX_INTVL 460 * addnl_dvdr); 461 } else { 462 addnl_dvdr = 1; 463 coal_intvl = EMAC_DM646X_CMINTMAX_INTVL; 464 } 465 } 466 467 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 468 469 int_ctrl |= EMAC_DM646X_INTPACEEN; 470 int_ctrl &= (~EMAC_DM646X_INTPRESCALE_MASK); 471 int_ctrl |= (prescale & EMAC_DM646X_INTPRESCALE_MASK); 472 emac_ctrl_write(EMAC_DM646X_CMINTCTRL, int_ctrl); 473 474 emac_ctrl_write(EMAC_DM646X_CMRXINTMAX, num_interrupts); 475 emac_ctrl_write(EMAC_DM646X_CMTXINTMAX, num_interrupts); 476 477 break; 478 default: 479 int_ctrl = emac_ctrl_read(EMAC_CTRL_EWINTTCNT); 480 int_ctrl &= (~EMAC_DM644X_EWINTCNT_MASK); 481 prescale = coal_intvl * priv->bus_freq_mhz; 482 if (prescale > EMAC_DM644X_EWINTCNT_MASK) { 483 prescale = EMAC_DM644X_EWINTCNT_MASK; 484 coal_intvl = prescale / priv->bus_freq_mhz; 485 } 486 emac_ctrl_write(EMAC_CTRL_EWINTTCNT, (int_ctrl | prescale)); 487 488 break; 489 } 490 491 printk(KERN_INFO"Set coalesce to %d usecs.\n", coal_intvl); 492 priv->coal_intvl = coal_intvl; 493 494 return 0; 495 496 } 497 498 499 /* ethtool_ops: DaVinci EMAC Ethtool structure 500 * 501 * Ethtool support for EMAC adapter 502 */ 503 static const struct ethtool_ops ethtool_ops = { 504 .supported_coalesce_params = ETHTOOL_COALESCE_RX_USECS, 505 .get_drvinfo = emac_get_drvinfo, 506 .get_link = ethtool_op_get_link, 507 .get_coalesce = emac_get_coalesce, 508 .set_coalesce = emac_set_coalesce, 509 .get_ts_info = ethtool_op_get_ts_info, 510 .get_link_ksettings = phy_ethtool_get_link_ksettings, 511 .set_link_ksettings = phy_ethtool_set_link_ksettings, 512 }; 513 514 /** 515 * emac_update_phystatus - Update Phy status 516 * @priv: The DaVinci EMAC private adapter structure 517 * 518 * Updates phy status and takes action for network queue if required 519 * based upon link status 520 * 521 */ 522 static void emac_update_phystatus(struct emac_priv *priv) 523 { 524 u32 mac_control; 525 u32 new_duplex; 526 u32 cur_duplex; 527 struct net_device *ndev = priv->ndev; 528 529 mac_control = emac_read(EMAC_MACCONTROL); 530 cur_duplex = (mac_control & EMAC_MACCONTROL_FULLDUPLEXEN) ? 531 DUPLEX_FULL : DUPLEX_HALF; 532 if (ndev->phydev) 533 new_duplex = ndev->phydev->duplex; 534 else 535 new_duplex = DUPLEX_FULL; 536 537 /* We get called only if link has changed (speed/duplex/status) */ 538 if ((priv->link) && (new_duplex != cur_duplex)) { 539 priv->duplex = new_duplex; 540 if (DUPLEX_FULL == priv->duplex) 541 mac_control |= (EMAC_MACCONTROL_FULLDUPLEXEN); 542 else 543 mac_control &= ~(EMAC_MACCONTROL_FULLDUPLEXEN); 544 } 545 546 if (priv->speed == SPEED_1000 && (priv->version == EMAC_VERSION_2)) { 547 mac_control = emac_read(EMAC_MACCONTROL); 548 mac_control |= (EMAC_DM646X_MACCONTORL_GIG | 549 EMAC_DM646X_MACCONTORL_GIGFORCE); 550 } else { 551 /* Clear the GIG bit and GIGFORCE bit */ 552 mac_control &= ~(EMAC_DM646X_MACCONTORL_GIGFORCE | 553 EMAC_DM646X_MACCONTORL_GIG); 554 555 if (priv->rmii_en && (priv->speed == SPEED_100)) 556 mac_control |= EMAC_MACCONTROL_RMIISPEED_MASK; 557 else 558 mac_control &= ~EMAC_MACCONTROL_RMIISPEED_MASK; 559 } 560 561 /* Update mac_control if changed */ 562 emac_write(EMAC_MACCONTROL, mac_control); 563 564 if (priv->link) { 565 /* link ON */ 566 if (!netif_carrier_ok(ndev)) 567 netif_carrier_on(ndev); 568 /* reactivate the transmit queue if it is stopped */ 569 if (netif_running(ndev) && netif_queue_stopped(ndev)) 570 netif_wake_queue(ndev); 571 } else { 572 /* link OFF */ 573 if (netif_carrier_ok(ndev)) 574 netif_carrier_off(ndev); 575 if (!netif_queue_stopped(ndev)) 576 netif_stop_queue(ndev); 577 } 578 } 579 580 /** 581 * hash_get - Calculate hash value from mac address 582 * @addr: mac address to delete from hash table 583 * 584 * Calculates hash value from mac address 585 * 586 */ 587 static u32 hash_get(u8 *addr) 588 { 589 u32 hash; 590 u8 tmpval; 591 int cnt; 592 hash = 0; 593 594 for (cnt = 0; cnt < 2; cnt++) { 595 tmpval = *addr++; 596 hash ^= (tmpval >> 2) ^ (tmpval << 4); 597 tmpval = *addr++; 598 hash ^= (tmpval >> 4) ^ (tmpval << 2); 599 tmpval = *addr++; 600 hash ^= (tmpval >> 6) ^ (tmpval); 601 } 602 603 return hash & 0x3F; 604 } 605 606 /** 607 * emac_hash_add - Hash function to add mac addr from hash table 608 * @priv: The DaVinci EMAC private adapter structure 609 * @mac_addr: mac address to delete from hash table 610 * 611 * Adds mac address to the internal hash table 612 * 613 */ 614 static int emac_hash_add(struct emac_priv *priv, u8 *mac_addr) 615 { 616 struct device *emac_dev = &priv->ndev->dev; 617 u32 rc = 0; 618 u32 hash_bit; 619 u32 hash_value = hash_get(mac_addr); 620 621 if (hash_value >= EMAC_NUM_MULTICAST_BITS) { 622 if (netif_msg_drv(priv)) { 623 dev_err(emac_dev, "DaVinci EMAC: emac_hash_add(): Invalid "\ 624 "Hash %08x, should not be greater than %08x", 625 hash_value, (EMAC_NUM_MULTICAST_BITS - 1)); 626 } 627 return -1; 628 } 629 630 /* set the hash bit only if not previously set */ 631 if (priv->multicast_hash_cnt[hash_value] == 0) { 632 rc = 1; /* hash value changed */ 633 if (hash_value < 32) { 634 hash_bit = BIT(hash_value); 635 priv->mac_hash1 |= hash_bit; 636 } else { 637 hash_bit = BIT((hash_value - 32)); 638 priv->mac_hash2 |= hash_bit; 639 } 640 } 641 642 /* incr counter for num of mcast addr's mapped to "this" hash bit */ 643 ++priv->multicast_hash_cnt[hash_value]; 644 645 return rc; 646 } 647 648 /** 649 * emac_hash_del - Hash function to delete mac addr from hash table 650 * @priv: The DaVinci EMAC private adapter structure 651 * @mac_addr: mac address to delete from hash table 652 * 653 * Removes mac address from the internal hash table 654 * 655 */ 656 static int emac_hash_del(struct emac_priv *priv, u8 *mac_addr) 657 { 658 u32 hash_value; 659 u32 hash_bit; 660 661 hash_value = hash_get(mac_addr); 662 if (priv->multicast_hash_cnt[hash_value] > 0) { 663 /* dec cntr for num of mcast addr's mapped to this hash bit */ 664 --priv->multicast_hash_cnt[hash_value]; 665 } 666 667 /* if counter still > 0, at least one multicast address refers 668 * to this hash bit. so return 0 */ 669 if (priv->multicast_hash_cnt[hash_value] > 0) 670 return 0; 671 672 if (hash_value < 32) { 673 hash_bit = BIT(hash_value); 674 priv->mac_hash1 &= ~hash_bit; 675 } else { 676 hash_bit = BIT((hash_value - 32)); 677 priv->mac_hash2 &= ~hash_bit; 678 } 679 680 /* return 1 to indicate change in mac_hash registers reqd */ 681 return 1; 682 } 683 684 /* EMAC multicast operation */ 685 #define EMAC_MULTICAST_ADD 0 686 #define EMAC_MULTICAST_DEL 1 687 #define EMAC_ALL_MULTI_SET 2 688 #define EMAC_ALL_MULTI_CLR 3 689 690 /** 691 * emac_add_mcast - Set multicast address in the EMAC adapter (Internal) 692 * @priv: The DaVinci EMAC private adapter structure 693 * @action: multicast operation to perform 694 * @mac_addr: mac address to set 695 * 696 * Set multicast addresses in EMAC adapter - internal function 697 * 698 */ 699 static void emac_add_mcast(struct emac_priv *priv, u32 action, u8 *mac_addr) 700 { 701 struct device *emac_dev = &priv->ndev->dev; 702 int update = -1; 703 704 switch (action) { 705 case EMAC_MULTICAST_ADD: 706 update = emac_hash_add(priv, mac_addr); 707 break; 708 case EMAC_MULTICAST_DEL: 709 update = emac_hash_del(priv, mac_addr); 710 break; 711 case EMAC_ALL_MULTI_SET: 712 update = 1; 713 priv->mac_hash1 = EMAC_ALL_MULTI_REG_VALUE; 714 priv->mac_hash2 = EMAC_ALL_MULTI_REG_VALUE; 715 break; 716 case EMAC_ALL_MULTI_CLR: 717 update = 1; 718 priv->mac_hash1 = 0; 719 priv->mac_hash2 = 0; 720 memset(&(priv->multicast_hash_cnt[0]), 0, 721 sizeof(priv->multicast_hash_cnt[0]) * 722 EMAC_NUM_MULTICAST_BITS); 723 break; 724 default: 725 if (netif_msg_drv(priv)) 726 dev_err(emac_dev, "DaVinci EMAC: add_mcast"\ 727 ": bad operation %d", action); 728 break; 729 } 730 731 /* write to the hardware only if the register status chances */ 732 if (update > 0) { 733 emac_write(EMAC_MACHASH1, priv->mac_hash1); 734 emac_write(EMAC_MACHASH2, priv->mac_hash2); 735 } 736 } 737 738 /** 739 * emac_dev_mcast_set - Set multicast address in the EMAC adapter 740 * @ndev: The DaVinci EMAC network adapter 741 * 742 * Set multicast addresses in EMAC adapter 743 * 744 */ 745 static void emac_dev_mcast_set(struct net_device *ndev) 746 { 747 u32 mbp_enable; 748 struct emac_priv *priv = netdev_priv(ndev); 749 750 mbp_enable = emac_read(EMAC_RXMBPENABLE); 751 if (ndev->flags & IFF_PROMISC) { 752 mbp_enable &= (~EMAC_MBP_PROMISCCH(EMAC_DEF_PROM_CH)); 753 mbp_enable |= (EMAC_MBP_RXPROMISC); 754 } else { 755 mbp_enable = (mbp_enable & ~EMAC_MBP_RXPROMISC); 756 if ((ndev->flags & IFF_ALLMULTI) || 757 netdev_mc_count(ndev) > EMAC_DEF_MAX_MULTICAST_ADDRESSES) { 758 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 759 emac_add_mcast(priv, EMAC_ALL_MULTI_SET, NULL); 760 } else if (!netdev_mc_empty(ndev)) { 761 struct netdev_hw_addr *ha; 762 763 mbp_enable = (mbp_enable | EMAC_MBP_RXMCAST); 764 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 765 /* program multicast address list into EMAC hardware */ 766 netdev_for_each_mc_addr(ha, ndev) { 767 emac_add_mcast(priv, EMAC_MULTICAST_ADD, 768 (u8 *) ha->addr); 769 } 770 } else { 771 mbp_enable = (mbp_enable & ~EMAC_MBP_RXMCAST); 772 emac_add_mcast(priv, EMAC_ALL_MULTI_CLR, NULL); 773 } 774 } 775 /* Set mbp config register */ 776 emac_write(EMAC_RXMBPENABLE, mbp_enable); 777 } 778 779 /************************************************************************* 780 * EMAC Hardware manipulation 781 *************************************************************************/ 782 783 /** 784 * emac_int_disable - Disable EMAC module interrupt (from adapter) 785 * @priv: The DaVinci EMAC private adapter structure 786 * 787 * Disable EMAC interrupt on the adapter 788 * 789 */ 790 static void emac_int_disable(struct emac_priv *priv) 791 { 792 if (priv->version == EMAC_VERSION_2) { 793 unsigned long flags; 794 795 local_irq_save(flags); 796 797 /* Program C0_Int_En to zero to turn off 798 * interrupts to the CPU */ 799 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0x0); 800 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0x0); 801 /* NOTE: Rx Threshold and Misc interrupts are not disabled */ 802 if (priv->int_disable) 803 priv->int_disable(); 804 805 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 806 807 /* ack rxen only then a new pulse will be generated */ 808 emac_write(EMAC_DM646X_MACEOIVECTOR, 809 EMAC_DM646X_MAC_EOI_C0_RXEN); 810 811 /* ack txen- only then a new pulse will be generated */ 812 emac_write(EMAC_DM646X_MACEOIVECTOR, 813 EMAC_DM646X_MAC_EOI_C0_TXEN); 814 815 local_irq_restore(flags); 816 817 } else { 818 /* Set DM644x control registers for interrupt control */ 819 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x0); 820 } 821 } 822 823 /** 824 * emac_int_enable - Enable EMAC module interrupt (from adapter) 825 * @priv: The DaVinci EMAC private adapter structure 826 * 827 * Enable EMAC interrupt on the adapter 828 * 829 */ 830 static void emac_int_enable(struct emac_priv *priv) 831 { 832 if (priv->version == EMAC_VERSION_2) { 833 if (priv->int_enable) 834 priv->int_enable(); 835 836 emac_ctrl_write(EMAC_DM646X_CMRXINTEN, 0xff); 837 emac_ctrl_write(EMAC_DM646X_CMTXINTEN, 0xff); 838 839 /* In addition to turning on interrupt Enable, we need 840 * ack by writing appropriate values to the EOI 841 * register */ 842 843 /* NOTE: Rx Threshold and Misc interrupts are not enabled */ 844 } else { 845 /* Set DM644x control registers for interrupt control */ 846 emac_ctrl_write(EMAC_CTRL_EWCTL, 0x1); 847 } 848 } 849 850 /** 851 * emac_irq - EMAC interrupt handler 852 * @irq: interrupt number 853 * @dev_id: EMAC network adapter data structure ptr 854 * 855 * EMAC Interrupt handler - we only schedule NAPI and not process any packets 856 * here. EVen the interrupt status is checked (TX/RX/Err) in NAPI poll function 857 * 858 * Returns interrupt handled condition 859 */ 860 static irqreturn_t emac_irq(int irq, void *dev_id) 861 { 862 struct net_device *ndev = (struct net_device *)dev_id; 863 struct emac_priv *priv = netdev_priv(ndev); 864 865 ++priv->isr_count; 866 if (likely(netif_running(priv->ndev))) { 867 emac_int_disable(priv); 868 napi_schedule(&priv->napi); 869 } else { 870 /* we are closing down, so dont process anything */ 871 } 872 return IRQ_HANDLED; 873 } 874 875 static struct sk_buff *emac_rx_alloc(struct emac_priv *priv) 876 { 877 struct sk_buff *skb = netdev_alloc_skb(priv->ndev, priv->rx_buf_size); 878 if (WARN_ON(!skb)) 879 return NULL; 880 skb_reserve(skb, NET_IP_ALIGN); 881 return skb; 882 } 883 884 static void emac_rx_handler(void *token, int len, int status) 885 { 886 struct sk_buff *skb = token; 887 struct net_device *ndev = skb->dev; 888 struct emac_priv *priv = netdev_priv(ndev); 889 struct device *emac_dev = &ndev->dev; 890 int ret; 891 892 /* free and bail if we are shutting down */ 893 if (unlikely(!netif_running(ndev))) { 894 dev_kfree_skb_any(skb); 895 return; 896 } 897 898 /* recycle on receive error */ 899 if (status < 0) { 900 ndev->stats.rx_errors++; 901 goto recycle; 902 } 903 904 /* feed received packet up the stack */ 905 skb_put(skb, len); 906 skb->protocol = eth_type_trans(skb, ndev); 907 netif_receive_skb(skb); 908 ndev->stats.rx_bytes += len; 909 ndev->stats.rx_packets++; 910 911 /* alloc a new packet for receive */ 912 skb = emac_rx_alloc(priv); 913 if (!skb) { 914 if (netif_msg_rx_err(priv) && net_ratelimit()) 915 dev_err(emac_dev, "failed rx buffer alloc\n"); 916 return; 917 } 918 919 recycle: 920 ret = cpdma_chan_submit(priv->rxchan, skb, skb->data, 921 skb_tailroom(skb), 0); 922 923 WARN_ON(ret == -ENOMEM); 924 if (unlikely(ret < 0)) 925 dev_kfree_skb_any(skb); 926 } 927 928 static void emac_tx_handler(void *token, int len, int status) 929 { 930 struct sk_buff *skb = token; 931 struct net_device *ndev = skb->dev; 932 933 /* Check whether the queue is stopped due to stalled tx dma, if the 934 * queue is stopped then start the queue as we have free desc for tx 935 */ 936 if (unlikely(netif_queue_stopped(ndev))) 937 netif_wake_queue(ndev); 938 ndev->stats.tx_packets++; 939 ndev->stats.tx_bytes += len; 940 dev_kfree_skb_any(skb); 941 } 942 943 /** 944 * emac_dev_xmit - EMAC Transmit function 945 * @skb: SKB pointer 946 * @ndev: The DaVinci EMAC network adapter 947 * 948 * Called by the system to transmit a packet - we queue the packet in 949 * EMAC hardware transmit queue 950 * 951 * Returns success(NETDEV_TX_OK) or error code (typically out of desc's) 952 */ 953 static int emac_dev_xmit(struct sk_buff *skb, struct net_device *ndev) 954 { 955 struct device *emac_dev = &ndev->dev; 956 int ret_code; 957 struct emac_priv *priv = netdev_priv(ndev); 958 959 /* If no link, return */ 960 if (unlikely(!priv->link)) { 961 if (netif_msg_tx_err(priv) && net_ratelimit()) 962 dev_err(emac_dev, "DaVinci EMAC: No link to transmit"); 963 goto fail_tx; 964 } 965 966 ret_code = skb_put_padto(skb, EMAC_DEF_MIN_ETHPKTSIZE); 967 if (unlikely(ret_code < 0)) { 968 if (netif_msg_tx_err(priv) && net_ratelimit()) 969 dev_err(emac_dev, "DaVinci EMAC: packet pad failed"); 970 goto fail_tx; 971 } 972 973 skb_tx_timestamp(skb); 974 975 ret_code = cpdma_chan_submit(priv->txchan, skb, skb->data, skb->len, 976 0); 977 if (unlikely(ret_code != 0)) { 978 if (netif_msg_tx_err(priv) && net_ratelimit()) 979 dev_err(emac_dev, "DaVinci EMAC: desc submit failed"); 980 goto fail_tx; 981 } 982 983 /* If there is no more tx desc left free then we need to 984 * tell the kernel to stop sending us tx frames. 985 */ 986 if (unlikely(!cpdma_check_free_tx_desc(priv->txchan))) 987 netif_stop_queue(ndev); 988 989 return NETDEV_TX_OK; 990 991 fail_tx: 992 ndev->stats.tx_dropped++; 993 netif_stop_queue(ndev); 994 return NETDEV_TX_BUSY; 995 } 996 997 /** 998 * emac_dev_tx_timeout - EMAC Transmit timeout function 999 * @ndev: The DaVinci EMAC network adapter 1000 * @txqueue: the index of the hung transmit queue 1001 * 1002 * Called when system detects that a skb timeout period has expired 1003 * potentially due to a fault in the adapter in not being able to send 1004 * it out on the wire. We teardown the TX channel assuming a hardware 1005 * error and re-initialize the TX channel for hardware operation 1006 * 1007 */ 1008 static void emac_dev_tx_timeout(struct net_device *ndev, unsigned int txqueue) 1009 { 1010 struct emac_priv *priv = netdev_priv(ndev); 1011 struct device *emac_dev = &ndev->dev; 1012 1013 if (netif_msg_tx_err(priv)) 1014 dev_err(emac_dev, "DaVinci EMAC: xmit timeout, restarting TX"); 1015 1016 ndev->stats.tx_errors++; 1017 emac_int_disable(priv); 1018 cpdma_chan_stop(priv->txchan); 1019 cpdma_chan_start(priv->txchan); 1020 emac_int_enable(priv); 1021 } 1022 1023 /** 1024 * emac_set_type0addr - Set EMAC Type0 mac address 1025 * @priv: The DaVinci EMAC private adapter structure 1026 * @ch: RX channel number 1027 * @mac_addr: MAC address to set in device 1028 * 1029 * Called internally to set Type0 mac address of the adapter (Device) 1030 * 1031 * Returns success (0) or appropriate error code (none as of now) 1032 */ 1033 static void emac_set_type0addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1034 { 1035 u32 val; 1036 val = ((mac_addr[5] << 8) | (mac_addr[4])); 1037 emac_write(EMAC_MACSRCADDRLO, val); 1038 1039 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1040 (mac_addr[1] << 8) | (mac_addr[0])); 1041 emac_write(EMAC_MACSRCADDRHI, val); 1042 val = emac_read(EMAC_RXUNICASTSET); 1043 val |= BIT(ch); 1044 emac_write(EMAC_RXUNICASTSET, val); 1045 val = emac_read(EMAC_RXUNICASTCLEAR); 1046 val &= ~BIT(ch); 1047 emac_write(EMAC_RXUNICASTCLEAR, val); 1048 } 1049 1050 /** 1051 * emac_set_type1addr - Set EMAC Type1 mac address 1052 * @priv: The DaVinci EMAC private adapter structure 1053 * @ch: RX channel number 1054 * @mac_addr: MAC address to set in device 1055 * 1056 * Called internally to set Type1 mac address of the adapter (Device) 1057 * 1058 * Returns success (0) or appropriate error code (none as of now) 1059 */ 1060 static void emac_set_type1addr(struct emac_priv *priv, u32 ch, char *mac_addr) 1061 { 1062 u32 val; 1063 emac_write(EMAC_MACINDEX, ch); 1064 val = ((mac_addr[5] << 8) | mac_addr[4]); 1065 emac_write(EMAC_MACADDRLO, val); 1066 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1067 (mac_addr[1] << 8) | (mac_addr[0])); 1068 emac_write(EMAC_MACADDRHI, val); 1069 emac_set_type0addr(priv, ch, mac_addr); 1070 } 1071 1072 /** 1073 * emac_set_type2addr - Set EMAC Type2 mac address 1074 * @priv: The DaVinci EMAC private adapter structure 1075 * @ch: RX channel number 1076 * @mac_addr: MAC address to set in device 1077 * @index: index into RX address entries 1078 * @match: match parameter for RX address matching logic 1079 * 1080 * Called internally to set Type2 mac address of the adapter (Device) 1081 * 1082 * Returns success (0) or appropriate error code (none as of now) 1083 */ 1084 static void emac_set_type2addr(struct emac_priv *priv, u32 ch, 1085 char *mac_addr, int index, int match) 1086 { 1087 u32 val; 1088 emac_write(EMAC_MACINDEX, index); 1089 val = ((mac_addr[3] << 24) | (mac_addr[2] << 16) | \ 1090 (mac_addr[1] << 8) | (mac_addr[0])); 1091 emac_write(EMAC_MACADDRHI, val); 1092 val = ((mac_addr[5] << 8) | mac_addr[4] | ((ch & 0x7) << 16) | \ 1093 (match << 19) | BIT(20)); 1094 emac_write(EMAC_MACADDRLO, val); 1095 emac_set_type0addr(priv, ch, mac_addr); 1096 } 1097 1098 /** 1099 * emac_setmac - Set mac address in the adapter (internal function) 1100 * @priv: The DaVinci EMAC private adapter structure 1101 * @ch: RX channel number 1102 * @mac_addr: MAC address to set in device 1103 * 1104 * Called internally to set the mac address of the adapter (Device) 1105 * 1106 * Returns success (0) or appropriate error code (none as of now) 1107 */ 1108 static void emac_setmac(struct emac_priv *priv, u32 ch, char *mac_addr) 1109 { 1110 struct device *emac_dev = &priv->ndev->dev; 1111 1112 if (priv->rx_addr_type == 0) { 1113 emac_set_type0addr(priv, ch, mac_addr); 1114 } else if (priv->rx_addr_type == 1) { 1115 u32 cnt; 1116 for (cnt = 0; cnt < EMAC_MAX_TXRX_CHANNELS; cnt++) 1117 emac_set_type1addr(priv, ch, mac_addr); 1118 } else if (priv->rx_addr_type == 2) { 1119 emac_set_type2addr(priv, ch, mac_addr, ch, 1); 1120 emac_set_type0addr(priv, ch, mac_addr); 1121 } else { 1122 if (netif_msg_drv(priv)) 1123 dev_err(emac_dev, "DaVinci EMAC: Wrong addressing\n"); 1124 } 1125 } 1126 1127 /** 1128 * emac_dev_setmac_addr - Set mac address in the adapter 1129 * @ndev: The DaVinci EMAC network adapter 1130 * @addr: MAC address to set in device 1131 * 1132 * Called by the system to set the mac address of the adapter (Device) 1133 * 1134 * Returns success (0) or appropriate error code (none as of now) 1135 */ 1136 static int emac_dev_setmac_addr(struct net_device *ndev, void *addr) 1137 { 1138 struct emac_priv *priv = netdev_priv(ndev); 1139 struct device *emac_dev = &priv->ndev->dev; 1140 struct sockaddr *sa = addr; 1141 1142 if (!is_valid_ether_addr(sa->sa_data)) 1143 return -EADDRNOTAVAIL; 1144 1145 /* Store mac addr in priv and rx channel and set it in EMAC hw */ 1146 memcpy(priv->mac_addr, sa->sa_data, ndev->addr_len); 1147 eth_hw_addr_set(ndev, sa->sa_data); 1148 1149 /* MAC address is configured only after the interface is enabled. */ 1150 if (netif_running(ndev)) { 1151 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1152 } 1153 1154 if (netif_msg_drv(priv)) 1155 dev_notice(emac_dev, "DaVinci EMAC: emac_dev_setmac_addr %pM\n", 1156 priv->mac_addr); 1157 1158 return 0; 1159 } 1160 1161 /** 1162 * emac_hw_enable - Enable EMAC hardware for packet transmission/reception 1163 * @priv: The DaVinci EMAC private adapter structure 1164 * 1165 * Enables EMAC hardware for packet processing - enables PHY, enables RX 1166 * for packet reception and enables device interrupts and then NAPI 1167 * 1168 * Returns success (0) or appropriate error code (none right now) 1169 */ 1170 static int emac_hw_enable(struct emac_priv *priv) 1171 { 1172 u32 val, mbp_enable, mac_control; 1173 1174 /* Soft reset */ 1175 emac_write(EMAC_SOFTRESET, 1); 1176 while (emac_read(EMAC_SOFTRESET)) 1177 cpu_relax(); 1178 1179 /* Disable interrupt & Set pacing for more interrupts initially */ 1180 emac_int_disable(priv); 1181 1182 /* Full duplex enable bit set when auto negotiation happens */ 1183 mac_control = 1184 (((EMAC_DEF_TXPRIO_FIXED) ? (EMAC_MACCONTROL_TXPTYPE) : 0x0) | 1185 ((priv->speed == 1000) ? EMAC_MACCONTROL_GIGABITEN : 0x0) | 1186 ((EMAC_DEF_TXPACING_EN) ? (EMAC_MACCONTROL_TXPACEEN) : 0x0) | 1187 ((priv->duplex == DUPLEX_FULL) ? 0x1 : 0)); 1188 emac_write(EMAC_MACCONTROL, mac_control); 1189 1190 mbp_enable = 1191 (((EMAC_DEF_PASS_CRC) ? (EMAC_RXMBP_PASSCRC_MASK) : 0x0) | 1192 ((EMAC_DEF_QOS_EN) ? (EMAC_RXMBP_QOSEN_MASK) : 0x0) | 1193 ((EMAC_DEF_NO_BUFF_CHAIN) ? (EMAC_RXMBP_NOCHAIN_MASK) : 0x0) | 1194 ((EMAC_DEF_MACCTRL_FRAME_EN) ? (EMAC_RXMBP_CMFEN_MASK) : 0x0) | 1195 ((EMAC_DEF_SHORT_FRAME_EN) ? (EMAC_RXMBP_CSFEN_MASK) : 0x0) | 1196 ((EMAC_DEF_ERROR_FRAME_EN) ? (EMAC_RXMBP_CEFEN_MASK) : 0x0) | 1197 ((EMAC_DEF_PROM_EN) ? (EMAC_RXMBP_CAFEN_MASK) : 0x0) | 1198 ((EMAC_DEF_PROM_CH & EMAC_RXMBP_CHMASK) << \ 1199 EMAC_RXMBP_PROMCH_SHIFT) | 1200 ((EMAC_DEF_BCAST_EN) ? (EMAC_RXMBP_BROADEN_MASK) : 0x0) | 1201 ((EMAC_DEF_BCAST_CH & EMAC_RXMBP_CHMASK) << \ 1202 EMAC_RXMBP_BROADCH_SHIFT) | 1203 ((EMAC_DEF_MCAST_EN) ? (EMAC_RXMBP_MULTIEN_MASK) : 0x0) | 1204 ((EMAC_DEF_MCAST_CH & EMAC_RXMBP_CHMASK) << \ 1205 EMAC_RXMBP_MULTICH_SHIFT)); 1206 emac_write(EMAC_RXMBPENABLE, mbp_enable); 1207 emac_write(EMAC_RXMAXLEN, (EMAC_DEF_MAX_FRAME_SIZE & 1208 EMAC_RX_MAX_LEN_MASK)); 1209 emac_write(EMAC_RXBUFFEROFFSET, (EMAC_DEF_BUFFER_OFFSET & 1210 EMAC_RX_BUFFER_OFFSET_MASK)); 1211 emac_write(EMAC_RXFILTERLOWTHRESH, 0); 1212 emac_write(EMAC_RXUNICASTCLEAR, EMAC_RX_UNICAST_CLEAR_ALL); 1213 priv->rx_addr_type = (emac_read(EMAC_MACCONFIG) >> 8) & 0xFF; 1214 1215 emac_write(EMAC_MACINTMASKSET, EMAC_MAC_HOST_ERR_INTMASK_VAL); 1216 1217 emac_setmac(priv, EMAC_DEF_RX_CH, priv->mac_addr); 1218 1219 /* Enable MII */ 1220 val = emac_read(EMAC_MACCONTROL); 1221 val |= (EMAC_MACCONTROL_GMIIEN); 1222 emac_write(EMAC_MACCONTROL, val); 1223 1224 /* Enable NAPI and interrupts */ 1225 napi_enable(&priv->napi); 1226 emac_int_enable(priv); 1227 return 0; 1228 1229 } 1230 1231 /** 1232 * emac_poll - EMAC NAPI Poll function 1233 * @napi: pointer to the napi_struct containing The DaVinci EMAC network adapter 1234 * @budget: Number of receive packets to process (as told by NAPI layer) 1235 * 1236 * NAPI Poll function implemented to process packets as per budget. We check 1237 * the type of interrupt on the device and accordingly call the TX or RX 1238 * packet processing functions. We follow the budget for RX processing and 1239 * also put a cap on number of TX pkts processed through config param. The 1240 * NAPI schedule function is called if more packets pending. 1241 * 1242 * Returns number of packets received (in most cases; else TX pkts - rarely) 1243 */ 1244 static int emac_poll(struct napi_struct *napi, int budget) 1245 { 1246 unsigned int mask; 1247 struct emac_priv *priv = container_of(napi, struct emac_priv, napi); 1248 struct net_device *ndev = priv->ndev; 1249 struct device *emac_dev = &ndev->dev; 1250 u32 status = 0; 1251 u32 num_rx_pkts = 0; 1252 1253 /* Check interrupt vectors and call packet processing */ 1254 status = emac_read(EMAC_MACINVECTOR); 1255 1256 mask = EMAC_DM644X_MAC_IN_VECTOR_TX_INT_VEC; 1257 1258 if (priv->version == EMAC_VERSION_2) 1259 mask = EMAC_DM646X_MAC_IN_VECTOR_TX_INT_VEC; 1260 1261 if (status & mask) { 1262 cpdma_chan_process(priv->txchan, EMAC_DEF_TX_MAX_SERVICE); 1263 } /* TX processing */ 1264 1265 mask = EMAC_DM644X_MAC_IN_VECTOR_RX_INT_VEC; 1266 1267 if (priv->version == EMAC_VERSION_2) 1268 mask = EMAC_DM646X_MAC_IN_VECTOR_RX_INT_VEC; 1269 1270 if (status & mask) { 1271 num_rx_pkts = cpdma_chan_process(priv->rxchan, budget); 1272 } /* RX processing */ 1273 1274 mask = EMAC_DM644X_MAC_IN_VECTOR_HOST_INT; 1275 if (priv->version == EMAC_VERSION_2) 1276 mask = EMAC_DM646X_MAC_IN_VECTOR_HOST_INT; 1277 1278 if (unlikely(status & mask)) { 1279 u32 ch, cause; 1280 dev_err(emac_dev, "DaVinci EMAC: Fatal Hardware Error\n"); 1281 netif_stop_queue(ndev); 1282 napi_disable(&priv->napi); 1283 1284 status = emac_read(EMAC_MACSTATUS); 1285 cause = ((status & EMAC_MACSTATUS_TXERRCODE_MASK) >> 1286 EMAC_MACSTATUS_TXERRCODE_SHIFT); 1287 if (cause) { 1288 ch = ((status & EMAC_MACSTATUS_TXERRCH_MASK) >> 1289 EMAC_MACSTATUS_TXERRCH_SHIFT); 1290 if (net_ratelimit()) { 1291 dev_err(emac_dev, "TX Host error %s on ch=%d\n", 1292 &emac_txhost_errcodes[cause][0], ch); 1293 } 1294 } 1295 cause = ((status & EMAC_MACSTATUS_RXERRCODE_MASK) >> 1296 EMAC_MACSTATUS_RXERRCODE_SHIFT); 1297 if (cause) { 1298 ch = ((status & EMAC_MACSTATUS_RXERRCH_MASK) >> 1299 EMAC_MACSTATUS_RXERRCH_SHIFT); 1300 if (netif_msg_hw(priv) && net_ratelimit()) 1301 dev_err(emac_dev, "RX Host error %s on ch=%d\n", 1302 &emac_rxhost_errcodes[cause][0], ch); 1303 } 1304 } else if (num_rx_pkts < budget) { 1305 napi_complete_done(napi, num_rx_pkts); 1306 emac_int_enable(priv); 1307 } 1308 1309 return num_rx_pkts; 1310 } 1311 1312 #ifdef CONFIG_NET_POLL_CONTROLLER 1313 /** 1314 * emac_poll_controller - EMAC Poll controller function 1315 * @ndev: The DaVinci EMAC network adapter 1316 * 1317 * Polled functionality used by netconsole and others in non interrupt mode 1318 * 1319 */ 1320 static void emac_poll_controller(struct net_device *ndev) 1321 { 1322 struct emac_priv *priv = netdev_priv(ndev); 1323 1324 emac_int_disable(priv); 1325 emac_irq(ndev->irq, ndev); 1326 emac_int_enable(priv); 1327 } 1328 #endif 1329 1330 static void emac_adjust_link(struct net_device *ndev) 1331 { 1332 struct emac_priv *priv = netdev_priv(ndev); 1333 struct phy_device *phydev = ndev->phydev; 1334 unsigned long flags; 1335 int new_state = 0; 1336 1337 spin_lock_irqsave(&priv->lock, flags); 1338 1339 if (phydev->link) { 1340 /* check the mode of operation - full/half duplex */ 1341 if (phydev->duplex != priv->duplex) { 1342 new_state = 1; 1343 priv->duplex = phydev->duplex; 1344 } 1345 if (phydev->speed != priv->speed) { 1346 new_state = 1; 1347 priv->speed = phydev->speed; 1348 } 1349 if (!priv->link) { 1350 new_state = 1; 1351 priv->link = 1; 1352 } 1353 1354 } else if (priv->link) { 1355 new_state = 1; 1356 priv->link = 0; 1357 priv->speed = 0; 1358 priv->duplex = ~0; 1359 } 1360 if (new_state) { 1361 emac_update_phystatus(priv); 1362 phy_print_status(ndev->phydev); 1363 } 1364 1365 spin_unlock_irqrestore(&priv->lock, flags); 1366 } 1367 1368 /************************************************************************* 1369 * Linux Driver Model 1370 *************************************************************************/ 1371 1372 /** 1373 * emac_devioctl - EMAC adapter ioctl 1374 * @ndev: The DaVinci EMAC network adapter 1375 * @ifrq: request parameter 1376 * @cmd: command parameter 1377 * 1378 * EMAC driver ioctl function 1379 * 1380 * Returns success(0) or appropriate error code 1381 */ 1382 static int emac_devioctl(struct net_device *ndev, struct ifreq *ifrq, int cmd) 1383 { 1384 if (!(netif_running(ndev))) 1385 return -EINVAL; 1386 1387 /* TODO: Add phy read and write and private statistics get feature */ 1388 1389 if (ndev->phydev) 1390 return phy_mii_ioctl(ndev->phydev, ifrq, cmd); 1391 else 1392 return -EOPNOTSUPP; 1393 } 1394 1395 static int match_first_device(struct device *dev, const void *data) 1396 { 1397 if (dev->parent && dev->parent->of_node) 1398 return of_device_is_compatible(dev->parent->of_node, 1399 "ti,davinci_mdio"); 1400 1401 return !strncmp(dev_name(dev), "davinci_mdio", 12); 1402 } 1403 1404 /** 1405 * emac_dev_open - EMAC device open 1406 * @ndev: The DaVinci EMAC network adapter 1407 * 1408 * Called when system wants to start the interface. We init TX/RX channels 1409 * and enable the hardware for packet reception/transmission and start the 1410 * network queue. 1411 * 1412 * Returns 0 for a successful open, or appropriate error code 1413 */ 1414 static int emac_dev_open(struct net_device *ndev) 1415 { 1416 struct device *emac_dev = &ndev->dev; 1417 struct resource *res; 1418 int q, m, ret; 1419 int res_num = 0, irq_num = 0; 1420 int i = 0; 1421 struct emac_priv *priv = netdev_priv(ndev); 1422 struct phy_device *phydev = NULL; 1423 struct device *phy = NULL; 1424 1425 ret = pm_runtime_resume_and_get(&priv->pdev->dev); 1426 if (ret < 0) { 1427 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1428 __func__, ret); 1429 return ret; 1430 } 1431 1432 netif_carrier_off(ndev); 1433 eth_hw_addr_set(ndev, priv->mac_addr); 1434 1435 /* Configuration items */ 1436 priv->rx_buf_size = EMAC_DEF_MAX_FRAME_SIZE + NET_IP_ALIGN; 1437 1438 priv->mac_hash1 = 0; 1439 priv->mac_hash2 = 0; 1440 emac_write(EMAC_MACHASH1, 0); 1441 emac_write(EMAC_MACHASH2, 0); 1442 1443 for (i = 0; i < EMAC_DEF_RX_NUM_DESC; i++) { 1444 struct sk_buff *skb = emac_rx_alloc(priv); 1445 1446 if (!skb) 1447 break; 1448 1449 ret = cpdma_chan_idle_submit(priv->rxchan, skb, skb->data, 1450 skb_tailroom(skb), 0); 1451 if (WARN_ON(ret < 0)) 1452 break; 1453 } 1454 1455 /* Request IRQ */ 1456 if (dev_of_node(&priv->pdev->dev)) { 1457 while ((ret = platform_get_irq_optional(priv->pdev, res_num)) != -ENXIO) { 1458 if (ret < 0) 1459 goto rollback; 1460 1461 ret = request_irq(ret, emac_irq, 0, ndev->name, ndev); 1462 if (ret) { 1463 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed\n"); 1464 goto rollback; 1465 } 1466 res_num++; 1467 } 1468 } else { 1469 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, res_num))) { 1470 for (irq_num = res->start; irq_num <= res->end; irq_num++) { 1471 ret = request_irq(irq_num, emac_irq, 0, ndev->name, ndev); 1472 if (ret) { 1473 dev_err(emac_dev, "DaVinci EMAC: request_irq() failed\n"); 1474 goto rollback; 1475 } 1476 } 1477 res_num++; 1478 } 1479 /* prepare counters for rollback in case of an error */ 1480 res_num--; 1481 irq_num--; 1482 } 1483 1484 /* Start/Enable EMAC hardware */ 1485 emac_hw_enable(priv); 1486 1487 /* Enable Interrupt pacing if configured */ 1488 if (priv->coal_intvl != 0) { 1489 struct ethtool_coalesce coal; 1490 1491 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1492 emac_set_coalesce(ndev, &coal, NULL, NULL); 1493 } 1494 1495 cpdma_ctlr_start(priv->dma); 1496 1497 if (priv->phy_node) { 1498 phydev = of_phy_connect(ndev, priv->phy_node, 1499 &emac_adjust_link, 0, 0); 1500 if (!phydev) { 1501 dev_err(emac_dev, "could not connect to phy %pOF\n", 1502 priv->phy_node); 1503 ret = -ENODEV; 1504 goto err; 1505 } 1506 } 1507 1508 /* use the first phy on the bus if pdata did not give us a phy id */ 1509 if (!phydev && !priv->phy_id) { 1510 /* NOTE: we can't use bus_find_device_by_name() here because 1511 * the device name is not guaranteed to be 'davinci_mdio'. On 1512 * some systems it can be 'davinci_mdio.0' so we need to use 1513 * strncmp() against the first part of the string to correctly 1514 * match it. 1515 */ 1516 phy = bus_find_device(&mdio_bus_type, NULL, NULL, 1517 match_first_device); 1518 if (phy) { 1519 priv->phy_id = dev_name(phy); 1520 if (!priv->phy_id || !*priv->phy_id) 1521 put_device(phy); 1522 } 1523 } 1524 1525 if (!phydev && priv->phy_id && *priv->phy_id) { 1526 phydev = phy_connect(ndev, priv->phy_id, 1527 &emac_adjust_link, 1528 PHY_INTERFACE_MODE_MII); 1529 put_device(phy); /* reference taken by bus_find_device */ 1530 if (IS_ERR(phydev)) { 1531 dev_err(emac_dev, "could not connect to phy %s\n", 1532 priv->phy_id); 1533 ret = PTR_ERR(phydev); 1534 goto err; 1535 } 1536 1537 priv->link = 0; 1538 priv->speed = 0; 1539 priv->duplex = ~0; 1540 1541 phy_attached_info(phydev); 1542 } 1543 1544 if (!phydev) { 1545 /* No PHY , fix the link, speed and duplex settings */ 1546 dev_notice(emac_dev, "no phy, defaulting to 100/full\n"); 1547 priv->link = 1; 1548 priv->speed = SPEED_100; 1549 priv->duplex = DUPLEX_FULL; 1550 emac_update_phystatus(priv); 1551 } 1552 1553 if (netif_msg_drv(priv)) 1554 dev_notice(emac_dev, "DaVinci EMAC: Opened %s\n", ndev->name); 1555 1556 if (phydev) 1557 phy_start(phydev); 1558 1559 return 0; 1560 1561 err: 1562 emac_int_disable(priv); 1563 napi_disable(&priv->napi); 1564 1565 rollback: 1566 if (dev_of_node(&priv->pdev->dev)) { 1567 for (q = res_num - 1; q >= 0; q--) { 1568 irq_num = platform_get_irq(priv->pdev, q); 1569 if (irq_num > 0) 1570 free_irq(irq_num, ndev); 1571 } 1572 } else { 1573 for (q = res_num; q >= 0; q--) { 1574 res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, q); 1575 /* at the first iteration, irq_num is already set to the 1576 * right value 1577 */ 1578 if (q != res_num) 1579 irq_num = res->end; 1580 1581 for (m = irq_num; m >= res->start; m--) 1582 free_irq(m, ndev); 1583 } 1584 } 1585 cpdma_ctlr_stop(priv->dma); 1586 pm_runtime_put(&priv->pdev->dev); 1587 return ret; 1588 } 1589 1590 /** 1591 * emac_dev_stop - EMAC device stop 1592 * @ndev: The DaVinci EMAC network adapter 1593 * 1594 * Called when system wants to stop or down the interface. We stop the network 1595 * queue, disable interrupts and cleanup TX/RX channels. 1596 * 1597 * We return the statistics in net_device_stats structure pulled from emac 1598 */ 1599 static int emac_dev_stop(struct net_device *ndev) 1600 { 1601 struct resource *res; 1602 int i = 0; 1603 int irq_num; 1604 struct emac_priv *priv = netdev_priv(ndev); 1605 struct device *emac_dev = &ndev->dev; 1606 int ret = 0; 1607 1608 /* inform the upper layers. */ 1609 netif_stop_queue(ndev); 1610 napi_disable(&priv->napi); 1611 1612 netif_carrier_off(ndev); 1613 emac_int_disable(priv); 1614 cpdma_ctlr_stop(priv->dma); 1615 emac_write(EMAC_SOFTRESET, 1); 1616 1617 if (ndev->phydev) 1618 phy_disconnect(ndev->phydev); 1619 1620 /* Free IRQ */ 1621 if (dev_of_node(&priv->pdev->dev)) { 1622 do { 1623 ret = platform_get_irq_optional(priv->pdev, i); 1624 if (ret < 0 && ret != -ENXIO) 1625 break; 1626 if (ret > 0) { 1627 free_irq(ret, priv->ndev); 1628 } else { 1629 ret = 0; 1630 break; 1631 } 1632 } while (++i); 1633 } else { 1634 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, i))) { 1635 for (irq_num = res->start; irq_num <= res->end; irq_num++) 1636 free_irq(irq_num, priv->ndev); 1637 i++; 1638 } 1639 } 1640 1641 if (netif_msg_drv(priv)) 1642 dev_notice(emac_dev, "DaVinci EMAC: %s stopped\n", ndev->name); 1643 1644 pm_runtime_put(&priv->pdev->dev); 1645 return ret; 1646 } 1647 1648 /** 1649 * emac_dev_getnetstats - EMAC get statistics function 1650 * @ndev: The DaVinci EMAC network adapter 1651 * 1652 * Called when system wants to get statistics from the device. 1653 * 1654 * We return the statistics in net_device_stats structure pulled from emac 1655 */ 1656 static struct net_device_stats *emac_dev_getnetstats(struct net_device *ndev) 1657 { 1658 struct emac_priv *priv = netdev_priv(ndev); 1659 u32 mac_control; 1660 u32 stats_clear_mask; 1661 int err; 1662 1663 err = pm_runtime_resume_and_get(&priv->pdev->dev); 1664 if (err < 0) { 1665 dev_err(&priv->pdev->dev, "%s: failed to get_sync(%d)\n", 1666 __func__, err); 1667 return &ndev->stats; 1668 } 1669 1670 /* update emac hardware stats and reset the registers*/ 1671 1672 mac_control = emac_read(EMAC_MACCONTROL); 1673 1674 if (mac_control & EMAC_MACCONTROL_GMIIEN) 1675 stats_clear_mask = EMAC_STATS_CLR_MASK; 1676 else 1677 stats_clear_mask = 0; 1678 1679 ndev->stats.multicast += emac_read(EMAC_RXMCASTFRAMES); 1680 emac_write(EMAC_RXMCASTFRAMES, stats_clear_mask); 1681 1682 ndev->stats.collisions += (emac_read(EMAC_TXCOLLISION) + 1683 emac_read(EMAC_TXSINGLECOLL) + 1684 emac_read(EMAC_TXMULTICOLL)); 1685 emac_write(EMAC_TXCOLLISION, stats_clear_mask); 1686 emac_write(EMAC_TXSINGLECOLL, stats_clear_mask); 1687 emac_write(EMAC_TXMULTICOLL, stats_clear_mask); 1688 1689 ndev->stats.rx_length_errors += (emac_read(EMAC_RXOVERSIZED) + 1690 emac_read(EMAC_RXJABBER) + 1691 emac_read(EMAC_RXUNDERSIZED)); 1692 emac_write(EMAC_RXOVERSIZED, stats_clear_mask); 1693 emac_write(EMAC_RXJABBER, stats_clear_mask); 1694 emac_write(EMAC_RXUNDERSIZED, stats_clear_mask); 1695 1696 ndev->stats.rx_over_errors += (emac_read(EMAC_RXSOFOVERRUNS) + 1697 emac_read(EMAC_RXMOFOVERRUNS)); 1698 emac_write(EMAC_RXSOFOVERRUNS, stats_clear_mask); 1699 emac_write(EMAC_RXMOFOVERRUNS, stats_clear_mask); 1700 1701 ndev->stats.rx_fifo_errors += emac_read(EMAC_RXDMAOVERRUNS); 1702 emac_write(EMAC_RXDMAOVERRUNS, stats_clear_mask); 1703 1704 ndev->stats.tx_carrier_errors += 1705 emac_read(EMAC_TXCARRIERSENSE); 1706 emac_write(EMAC_TXCARRIERSENSE, stats_clear_mask); 1707 1708 ndev->stats.tx_fifo_errors += emac_read(EMAC_TXUNDERRUN); 1709 emac_write(EMAC_TXUNDERRUN, stats_clear_mask); 1710 1711 pm_runtime_put(&priv->pdev->dev); 1712 1713 return &ndev->stats; 1714 } 1715 1716 static const struct net_device_ops emac_netdev_ops = { 1717 .ndo_open = emac_dev_open, 1718 .ndo_stop = emac_dev_stop, 1719 .ndo_start_xmit = emac_dev_xmit, 1720 .ndo_set_rx_mode = emac_dev_mcast_set, 1721 .ndo_set_mac_address = emac_dev_setmac_addr, 1722 .ndo_eth_ioctl = emac_devioctl, 1723 .ndo_tx_timeout = emac_dev_tx_timeout, 1724 .ndo_get_stats = emac_dev_getnetstats, 1725 #ifdef CONFIG_NET_POLL_CONTROLLER 1726 .ndo_poll_controller = emac_poll_controller, 1727 #endif 1728 }; 1729 1730 static const struct of_device_id davinci_emac_of_match[]; 1731 1732 static struct emac_platform_data * 1733 davinci_emac_of_get_pdata(struct platform_device *pdev, struct emac_priv *priv) 1734 { 1735 struct device_node *np; 1736 const struct of_device_id *match; 1737 const struct emac_platform_data *auxdata; 1738 struct emac_platform_data *pdata = NULL; 1739 1740 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node) 1741 return dev_get_platdata(&pdev->dev); 1742 1743 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1744 if (!pdata) 1745 return NULL; 1746 1747 np = pdev->dev.of_node; 1748 pdata->version = EMAC_VERSION_2; 1749 1750 if (!is_valid_ether_addr(pdata->mac_addr)) 1751 of_get_mac_address(np, pdata->mac_addr); 1752 1753 of_property_read_u32(np, "ti,davinci-ctrl-reg-offset", 1754 &pdata->ctrl_reg_offset); 1755 1756 of_property_read_u32(np, "ti,davinci-ctrl-mod-reg-offset", 1757 &pdata->ctrl_mod_reg_offset); 1758 1759 of_property_read_u32(np, "ti,davinci-ctrl-ram-offset", 1760 &pdata->ctrl_ram_offset); 1761 1762 of_property_read_u32(np, "ti,davinci-ctrl-ram-size", 1763 &pdata->ctrl_ram_size); 1764 1765 of_property_read_u8(np, "ti,davinci-rmii-en", &pdata->rmii_en); 1766 1767 pdata->no_bd_ram = of_property_read_bool(np, "ti,davinci-no-bd-ram"); 1768 1769 priv->phy_node = of_parse_phandle(np, "phy-handle", 0); 1770 if (!priv->phy_node) { 1771 if (!of_phy_is_fixed_link(np)) 1772 pdata->phy_id = NULL; 1773 else if (of_phy_register_fixed_link(np) >= 0) 1774 priv->phy_node = of_node_get(np); 1775 } 1776 1777 auxdata = pdev->dev.platform_data; 1778 if (auxdata) { 1779 pdata->interrupt_enable = auxdata->interrupt_enable; 1780 pdata->interrupt_disable = auxdata->interrupt_disable; 1781 } 1782 1783 match = of_match_device(davinci_emac_of_match, &pdev->dev); 1784 if (match && match->data) { 1785 auxdata = match->data; 1786 pdata->version = auxdata->version; 1787 pdata->hw_ram_addr = auxdata->hw_ram_addr; 1788 } 1789 1790 return pdata; 1791 } 1792 1793 static int davinci_emac_try_get_mac(struct platform_device *pdev, 1794 int instance, u8 *mac_addr) 1795 { 1796 if (!pdev->dev.of_node) 1797 return -EINVAL; 1798 1799 return ti_cm_get_macid(&pdev->dev, instance, mac_addr); 1800 } 1801 1802 /** 1803 * davinci_emac_probe - EMAC device probe 1804 * @pdev: The DaVinci EMAC device that we are removing 1805 * 1806 * Called when probing for emac devicesr. We get details of instances and 1807 * resource information from platform init and register a network device 1808 * and allocate resources necessary for driver to perform 1809 */ 1810 static int davinci_emac_probe(struct platform_device *pdev) 1811 { 1812 struct device_node *np = pdev->dev.of_node; 1813 int rc = 0; 1814 struct resource *res, *res_ctrl; 1815 struct net_device *ndev; 1816 struct emac_priv *priv; 1817 unsigned long hw_ram_addr; 1818 struct emac_platform_data *pdata; 1819 struct cpdma_params dma_params; 1820 struct clk *emac_clk; 1821 unsigned long emac_bus_frequency; 1822 1823 1824 /* obtain emac clock from kernel */ 1825 emac_clk = devm_clk_get(&pdev->dev, NULL); 1826 if (IS_ERR(emac_clk)) { 1827 dev_err(&pdev->dev, "failed to get EMAC clock\n"); 1828 return -EBUSY; 1829 } 1830 emac_bus_frequency = clk_get_rate(emac_clk); 1831 devm_clk_put(&pdev->dev, emac_clk); 1832 1833 /* TODO: Probe PHY here if possible */ 1834 1835 ndev = alloc_etherdev(sizeof(struct emac_priv)); 1836 if (!ndev) 1837 return -ENOMEM; 1838 1839 platform_set_drvdata(pdev, ndev); 1840 priv = netdev_priv(ndev); 1841 priv->pdev = pdev; 1842 priv->ndev = ndev; 1843 priv->msg_enable = netif_msg_init(debug_level, DAVINCI_EMAC_DEBUG); 1844 1845 spin_lock_init(&priv->lock); 1846 1847 pdata = davinci_emac_of_get_pdata(pdev, priv); 1848 if (!pdata) { 1849 dev_err(&pdev->dev, "no platform data\n"); 1850 rc = -ENODEV; 1851 goto err_free_netdev; 1852 } 1853 1854 /* MAC addr and PHY mask , RMII enable info from platform_data */ 1855 memcpy(priv->mac_addr, pdata->mac_addr, ETH_ALEN); 1856 priv->phy_id = pdata->phy_id; 1857 priv->rmii_en = pdata->rmii_en; 1858 priv->version = pdata->version; 1859 priv->int_enable = pdata->interrupt_enable; 1860 priv->int_disable = pdata->interrupt_disable; 1861 1862 priv->coal_intvl = 0; 1863 priv->bus_freq_mhz = (u32)(emac_bus_frequency / 1000000); 1864 1865 /* Get EMAC platform data */ 1866 priv->remap_addr = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1867 if (IS_ERR(priv->remap_addr)) { 1868 rc = PTR_ERR(priv->remap_addr); 1869 goto no_pdata; 1870 } 1871 priv->emac_base_phys = res->start + pdata->ctrl_reg_offset; 1872 1873 res_ctrl = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1874 if (res_ctrl) { 1875 priv->ctrl_base = 1876 devm_ioremap_resource(&pdev->dev, res_ctrl); 1877 if (IS_ERR(priv->ctrl_base)) { 1878 rc = PTR_ERR(priv->ctrl_base); 1879 goto no_pdata; 1880 } 1881 } else { 1882 priv->ctrl_base = priv->remap_addr + pdata->ctrl_mod_reg_offset; 1883 } 1884 1885 priv->emac_base = priv->remap_addr + pdata->ctrl_reg_offset; 1886 ndev->base_addr = (unsigned long)priv->remap_addr; 1887 1888 hw_ram_addr = pdata->hw_ram_addr; 1889 if (!hw_ram_addr) 1890 hw_ram_addr = (u32 __force)res->start + pdata->ctrl_ram_offset; 1891 1892 memset(&dma_params, 0, sizeof(dma_params)); 1893 dma_params.dev = &pdev->dev; 1894 dma_params.dmaregs = priv->emac_base; 1895 dma_params.rxthresh = priv->emac_base + 0x120; 1896 dma_params.rxfree = priv->emac_base + 0x140; 1897 dma_params.txhdp = priv->emac_base + 0x600; 1898 dma_params.rxhdp = priv->emac_base + 0x620; 1899 dma_params.txcp = priv->emac_base + 0x640; 1900 dma_params.rxcp = priv->emac_base + 0x660; 1901 dma_params.num_chan = EMAC_MAX_TXRX_CHANNELS; 1902 dma_params.min_packet_size = EMAC_DEF_MIN_ETHPKTSIZE; 1903 dma_params.desc_hw_addr = hw_ram_addr; 1904 dma_params.desc_mem_size = pdata->ctrl_ram_size; 1905 dma_params.desc_align = 16; 1906 1907 dma_params.desc_mem_phys = pdata->no_bd_ram ? 0 : 1908 (u32 __force)res->start + pdata->ctrl_ram_offset; 1909 1910 priv->dma = cpdma_ctlr_create(&dma_params); 1911 if (!priv->dma) { 1912 dev_err(&pdev->dev, "error initializing DMA\n"); 1913 rc = -ENOMEM; 1914 goto no_pdata; 1915 } 1916 1917 priv->txchan = cpdma_chan_create(priv->dma, EMAC_DEF_TX_CH, 1918 emac_tx_handler, 0); 1919 if (IS_ERR(priv->txchan)) { 1920 dev_err(&pdev->dev, "error initializing tx dma channel\n"); 1921 rc = PTR_ERR(priv->txchan); 1922 goto err_free_dma; 1923 } 1924 1925 priv->rxchan = cpdma_chan_create(priv->dma, EMAC_DEF_RX_CH, 1926 emac_rx_handler, 1); 1927 if (IS_ERR(priv->rxchan)) { 1928 dev_err(&pdev->dev, "error initializing rx dma channel\n"); 1929 rc = PTR_ERR(priv->rxchan); 1930 goto err_free_txchan; 1931 } 1932 1933 rc = platform_get_irq(pdev, 0); 1934 if (rc < 0) 1935 goto err_free_rxchan; 1936 ndev->irq = rc; 1937 1938 rc = davinci_emac_try_get_mac(pdev, res_ctrl ? 0 : 1, priv->mac_addr); 1939 if (!rc) 1940 eth_hw_addr_set(ndev, priv->mac_addr); 1941 1942 if (!is_valid_ether_addr(priv->mac_addr)) { 1943 /* Use random MAC if still none obtained. */ 1944 eth_hw_addr_random(ndev); 1945 memcpy(priv->mac_addr, ndev->dev_addr, ndev->addr_len); 1946 dev_warn(&pdev->dev, "using random MAC addr: %pM\n", 1947 priv->mac_addr); 1948 } 1949 1950 ndev->netdev_ops = &emac_netdev_ops; 1951 ndev->ethtool_ops = ðtool_ops; 1952 netif_napi_add(ndev, &priv->napi, emac_poll, EMAC_POLL_WEIGHT); 1953 1954 pm_runtime_enable(&pdev->dev); 1955 rc = pm_runtime_resume_and_get(&pdev->dev); 1956 if (rc < 0) { 1957 dev_err(&pdev->dev, "%s: failed to get_sync(%d)\n", 1958 __func__, rc); 1959 goto err_napi_del; 1960 } 1961 1962 /* register the network device */ 1963 SET_NETDEV_DEV(ndev, &pdev->dev); 1964 rc = register_netdev(ndev); 1965 if (rc) { 1966 dev_err(&pdev->dev, "error in register_netdev\n"); 1967 rc = -ENODEV; 1968 pm_runtime_put(&pdev->dev); 1969 goto err_napi_del; 1970 } 1971 1972 1973 if (netif_msg_probe(priv)) { 1974 dev_notice(&pdev->dev, "DaVinci EMAC Probe found device " 1975 "(regs: %pa, irq: %d)\n", 1976 &priv->emac_base_phys, ndev->irq); 1977 } 1978 pm_runtime_put(&pdev->dev); 1979 1980 return 0; 1981 1982 err_napi_del: 1983 netif_napi_del(&priv->napi); 1984 err_free_rxchan: 1985 cpdma_chan_destroy(priv->rxchan); 1986 err_free_txchan: 1987 cpdma_chan_destroy(priv->txchan); 1988 err_free_dma: 1989 cpdma_ctlr_destroy(priv->dma); 1990 no_pdata: 1991 if (of_phy_is_fixed_link(np)) 1992 of_phy_deregister_fixed_link(np); 1993 of_node_put(priv->phy_node); 1994 err_free_netdev: 1995 free_netdev(ndev); 1996 return rc; 1997 } 1998 1999 /** 2000 * davinci_emac_remove - EMAC device remove 2001 * @pdev: The DaVinci EMAC device that we are removing 2002 * 2003 * Called when removing the device driver. We disable clock usage and release 2004 * the resources taken up by the driver and unregister network device 2005 */ 2006 static int davinci_emac_remove(struct platform_device *pdev) 2007 { 2008 struct net_device *ndev = platform_get_drvdata(pdev); 2009 struct emac_priv *priv = netdev_priv(ndev); 2010 struct device_node *np = pdev->dev.of_node; 2011 2012 dev_notice(&ndev->dev, "DaVinci EMAC: davinci_emac_remove()\n"); 2013 2014 if (priv->txchan) 2015 cpdma_chan_destroy(priv->txchan); 2016 if (priv->rxchan) 2017 cpdma_chan_destroy(priv->rxchan); 2018 cpdma_ctlr_destroy(priv->dma); 2019 2020 unregister_netdev(ndev); 2021 of_node_put(priv->phy_node); 2022 pm_runtime_disable(&pdev->dev); 2023 if (of_phy_is_fixed_link(np)) 2024 of_phy_deregister_fixed_link(np); 2025 free_netdev(ndev); 2026 2027 return 0; 2028 } 2029 2030 static int davinci_emac_suspend(struct device *dev) 2031 { 2032 struct net_device *ndev = dev_get_drvdata(dev); 2033 2034 if (netif_running(ndev)) 2035 emac_dev_stop(ndev); 2036 2037 return 0; 2038 } 2039 2040 static int davinci_emac_resume(struct device *dev) 2041 { 2042 struct net_device *ndev = dev_get_drvdata(dev); 2043 2044 if (netif_running(ndev)) 2045 emac_dev_open(ndev); 2046 2047 return 0; 2048 } 2049 2050 static const struct dev_pm_ops davinci_emac_pm_ops = { 2051 .suspend = davinci_emac_suspend, 2052 .resume = davinci_emac_resume, 2053 }; 2054 2055 static const struct emac_platform_data am3517_emac_data = { 2056 .version = EMAC_VERSION_2, 2057 .hw_ram_addr = 0x01e20000, 2058 }; 2059 2060 static const struct emac_platform_data dm816_emac_data = { 2061 .version = EMAC_VERSION_2, 2062 }; 2063 2064 static const struct of_device_id davinci_emac_of_match[] = { 2065 {.compatible = "ti,davinci-dm6467-emac", }, 2066 {.compatible = "ti,am3517-emac", .data = &am3517_emac_data, }, 2067 {.compatible = "ti,dm816-emac", .data = &dm816_emac_data, }, 2068 {}, 2069 }; 2070 MODULE_DEVICE_TABLE(of, davinci_emac_of_match); 2071 2072 /* davinci_emac_driver: EMAC platform driver structure */ 2073 static struct platform_driver davinci_emac_driver = { 2074 .driver = { 2075 .name = "davinci_emac", 2076 .pm = &davinci_emac_pm_ops, 2077 .of_match_table = davinci_emac_of_match, 2078 }, 2079 .probe = davinci_emac_probe, 2080 .remove = davinci_emac_remove, 2081 }; 2082 2083 /** 2084 * davinci_emac_init - EMAC driver module init 2085 * 2086 * Called when initializing the driver. We register the driver with 2087 * the platform. 2088 */ 2089 static int __init davinci_emac_init(void) 2090 { 2091 return platform_driver_register(&davinci_emac_driver); 2092 } 2093 late_initcall(davinci_emac_init); 2094 2095 /** 2096 * davinci_emac_exit - EMAC driver module exit 2097 * 2098 * Called when exiting the driver completely. We unregister the driver with 2099 * the platform and exit 2100 */ 2101 static void __exit davinci_emac_exit(void) 2102 { 2103 platform_driver_unregister(&davinci_emac_driver); 2104 } 2105 module_exit(davinci_emac_exit); 2106 2107 MODULE_LICENSE("GPL"); 2108 MODULE_AUTHOR("DaVinci EMAC Maintainer: Anant Gole <anantgole@ti.com>"); 2109 MODULE_AUTHOR("DaVinci EMAC Maintainer: Chaithrika U S <chaithrika@ti.com>"); 2110 MODULE_DESCRIPTION("DaVinci EMAC Ethernet driver"); 2111