1 /* 2 * Texas Instruments CPDMA Driver 3 * 4 * Copyright (C) 2010 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 #include <linux/kernel.h> 16 #include <linux/spinlock.h> 17 #include <linux/device.h> 18 #include <linux/slab.h> 19 #include <linux/err.h> 20 #include <linux/dma-mapping.h> 21 #include <linux/io.h> 22 23 #include "davinci_cpdma.h" 24 25 /* DMA Registers */ 26 #define CPDMA_TXIDVER 0x00 27 #define CPDMA_TXCONTROL 0x04 28 #define CPDMA_TXTEARDOWN 0x08 29 #define CPDMA_RXIDVER 0x10 30 #define CPDMA_RXCONTROL 0x14 31 #define CPDMA_SOFTRESET 0x1c 32 #define CPDMA_RXTEARDOWN 0x18 33 #define CPDMA_TXINTSTATRAW 0x80 34 #define CPDMA_TXINTSTATMASKED 0x84 35 #define CPDMA_TXINTMASKSET 0x88 36 #define CPDMA_TXINTMASKCLEAR 0x8c 37 #define CPDMA_MACINVECTOR 0x90 38 #define CPDMA_MACEOIVECTOR 0x94 39 #define CPDMA_RXINTSTATRAW 0xa0 40 #define CPDMA_RXINTSTATMASKED 0xa4 41 #define CPDMA_RXINTMASKSET 0xa8 42 #define CPDMA_RXINTMASKCLEAR 0xac 43 #define CPDMA_DMAINTSTATRAW 0xb0 44 #define CPDMA_DMAINTSTATMASKED 0xb4 45 #define CPDMA_DMAINTMASKSET 0xb8 46 #define CPDMA_DMAINTMASKCLEAR 0xbc 47 #define CPDMA_DMAINT_HOSTERR BIT(1) 48 49 /* the following exist only if has_ext_regs is set */ 50 #define CPDMA_DMACONTROL 0x20 51 #define CPDMA_DMASTATUS 0x24 52 #define CPDMA_RXBUFFOFS 0x28 53 #define CPDMA_EM_CONTROL 0x2c 54 55 /* Descriptor mode bits */ 56 #define CPDMA_DESC_SOP BIT(31) 57 #define CPDMA_DESC_EOP BIT(30) 58 #define CPDMA_DESC_OWNER BIT(29) 59 #define CPDMA_DESC_EOQ BIT(28) 60 #define CPDMA_DESC_TD_COMPLETE BIT(27) 61 #define CPDMA_DESC_PASS_CRC BIT(26) 62 63 #define CPDMA_TEARDOWN_VALUE 0xfffffffc 64 65 struct cpdma_desc { 66 /* hardware fields */ 67 u32 hw_next; 68 u32 hw_buffer; 69 u32 hw_len; 70 u32 hw_mode; 71 /* software fields */ 72 void *sw_token; 73 u32 sw_buffer; 74 u32 sw_len; 75 }; 76 77 struct cpdma_desc_pool { 78 u32 phys; 79 u32 hw_addr; 80 void __iomem *iomap; /* ioremap map */ 81 void *cpumap; /* dma_alloc map */ 82 int desc_size, mem_size; 83 int num_desc, used_desc; 84 unsigned long *bitmap; 85 struct device *dev; 86 spinlock_t lock; 87 }; 88 89 enum cpdma_state { 90 CPDMA_STATE_IDLE, 91 CPDMA_STATE_ACTIVE, 92 CPDMA_STATE_TEARDOWN, 93 }; 94 95 static const char *cpdma_state_str[] = { "idle", "active", "teardown" }; 96 97 struct cpdma_ctlr { 98 enum cpdma_state state; 99 struct cpdma_params params; 100 struct device *dev; 101 struct cpdma_desc_pool *pool; 102 spinlock_t lock; 103 struct cpdma_chan *channels[2 * CPDMA_MAX_CHANNELS]; 104 }; 105 106 struct cpdma_chan { 107 enum cpdma_state state; 108 struct cpdma_ctlr *ctlr; 109 int chan_num; 110 spinlock_t lock; 111 struct cpdma_desc __iomem *head, *tail; 112 int count; 113 void __iomem *hdp, *cp, *rxfree; 114 u32 mask; 115 cpdma_handler_fn handler; 116 enum dma_data_direction dir; 117 struct cpdma_chan_stats stats; 118 /* offsets into dmaregs */ 119 int int_set, int_clear, td; 120 }; 121 122 /* The following make access to common cpdma_ctlr params more readable */ 123 #define dmaregs params.dmaregs 124 #define num_chan params.num_chan 125 126 /* various accessors */ 127 #define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs)) 128 #define chan_read(chan, fld) __raw_readl((chan)->fld) 129 #define desc_read(desc, fld) __raw_readl(&(desc)->fld) 130 #define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs)) 131 #define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld) 132 #define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld) 133 134 /* 135 * Utility constructs for a cpdma descriptor pool. Some devices (e.g. davinci 136 * emac) have dedicated on-chip memory for these descriptors. Some other 137 * devices (e.g. cpsw switches) use plain old memory. Descriptor pools 138 * abstract out these details 139 */ 140 static struct cpdma_desc_pool * 141 cpdma_desc_pool_create(struct device *dev, u32 phys, u32 hw_addr, 142 int size, int align) 143 { 144 int bitmap_size; 145 struct cpdma_desc_pool *pool; 146 147 pool = kzalloc(sizeof(*pool), GFP_KERNEL); 148 if (!pool) 149 return NULL; 150 151 spin_lock_init(&pool->lock); 152 153 pool->dev = dev; 154 pool->mem_size = size; 155 pool->desc_size = ALIGN(sizeof(struct cpdma_desc), align); 156 pool->num_desc = size / pool->desc_size; 157 158 bitmap_size = (pool->num_desc / BITS_PER_LONG) * sizeof(long); 159 pool->bitmap = kzalloc(bitmap_size, GFP_KERNEL); 160 if (!pool->bitmap) 161 goto fail; 162 163 if (phys) { 164 pool->phys = phys; 165 pool->iomap = ioremap(phys, size); 166 pool->hw_addr = hw_addr; 167 } else { 168 pool->cpumap = dma_alloc_coherent(dev, size, &pool->phys, 169 GFP_KERNEL); 170 pool->iomap = pool->cpumap; 171 pool->hw_addr = pool->phys; 172 } 173 174 if (pool->iomap) 175 return pool; 176 177 fail: 178 kfree(pool->bitmap); 179 kfree(pool); 180 return NULL; 181 } 182 183 static void cpdma_desc_pool_destroy(struct cpdma_desc_pool *pool) 184 { 185 unsigned long flags; 186 187 if (!pool) 188 return; 189 190 spin_lock_irqsave(&pool->lock, flags); 191 WARN_ON(pool->used_desc); 192 kfree(pool->bitmap); 193 if (pool->cpumap) { 194 dma_free_coherent(pool->dev, pool->mem_size, pool->cpumap, 195 pool->phys); 196 } else { 197 iounmap(pool->iomap); 198 } 199 spin_unlock_irqrestore(&pool->lock, flags); 200 kfree(pool); 201 } 202 203 static inline dma_addr_t desc_phys(struct cpdma_desc_pool *pool, 204 struct cpdma_desc __iomem *desc) 205 { 206 if (!desc) 207 return 0; 208 return pool->hw_addr + (__force dma_addr_t)desc - 209 (__force dma_addr_t)pool->iomap; 210 } 211 212 static inline struct cpdma_desc __iomem * 213 desc_from_phys(struct cpdma_desc_pool *pool, dma_addr_t dma) 214 { 215 return dma ? pool->iomap + dma - pool->hw_addr : NULL; 216 } 217 218 static struct cpdma_desc __iomem * 219 cpdma_desc_alloc(struct cpdma_desc_pool *pool, int num_desc) 220 { 221 unsigned long flags; 222 int index; 223 struct cpdma_desc __iomem *desc = NULL; 224 225 spin_lock_irqsave(&pool->lock, flags); 226 227 index = bitmap_find_next_zero_area(pool->bitmap, pool->num_desc, 0, 228 num_desc, 0); 229 if (index < pool->num_desc) { 230 bitmap_set(pool->bitmap, index, num_desc); 231 desc = pool->iomap + pool->desc_size * index; 232 pool->used_desc++; 233 } 234 235 spin_unlock_irqrestore(&pool->lock, flags); 236 return desc; 237 } 238 239 static void cpdma_desc_free(struct cpdma_desc_pool *pool, 240 struct cpdma_desc __iomem *desc, int num_desc) 241 { 242 unsigned long flags, index; 243 244 index = ((unsigned long)desc - (unsigned long)pool->iomap) / 245 pool->desc_size; 246 spin_lock_irqsave(&pool->lock, flags); 247 bitmap_clear(pool->bitmap, index, num_desc); 248 pool->used_desc--; 249 spin_unlock_irqrestore(&pool->lock, flags); 250 } 251 252 struct cpdma_ctlr *cpdma_ctlr_create(struct cpdma_params *params) 253 { 254 struct cpdma_ctlr *ctlr; 255 256 ctlr = kzalloc(sizeof(*ctlr), GFP_KERNEL); 257 if (!ctlr) 258 return NULL; 259 260 ctlr->state = CPDMA_STATE_IDLE; 261 ctlr->params = *params; 262 ctlr->dev = params->dev; 263 spin_lock_init(&ctlr->lock); 264 265 ctlr->pool = cpdma_desc_pool_create(ctlr->dev, 266 ctlr->params.desc_mem_phys, 267 ctlr->params.desc_hw_addr, 268 ctlr->params.desc_mem_size, 269 ctlr->params.desc_align); 270 if (!ctlr->pool) { 271 kfree(ctlr); 272 return NULL; 273 } 274 275 if (WARN_ON(ctlr->num_chan > CPDMA_MAX_CHANNELS)) 276 ctlr->num_chan = CPDMA_MAX_CHANNELS; 277 return ctlr; 278 } 279 EXPORT_SYMBOL_GPL(cpdma_ctlr_create); 280 281 int cpdma_ctlr_start(struct cpdma_ctlr *ctlr) 282 { 283 unsigned long flags; 284 int i; 285 286 spin_lock_irqsave(&ctlr->lock, flags); 287 if (ctlr->state != CPDMA_STATE_IDLE) { 288 spin_unlock_irqrestore(&ctlr->lock, flags); 289 return -EBUSY; 290 } 291 292 if (ctlr->params.has_soft_reset) { 293 unsigned long timeout = jiffies + HZ/10; 294 295 dma_reg_write(ctlr, CPDMA_SOFTRESET, 1); 296 while (time_before(jiffies, timeout)) { 297 if (dma_reg_read(ctlr, CPDMA_SOFTRESET) == 0) 298 break; 299 } 300 WARN_ON(!time_before(jiffies, timeout)); 301 } 302 303 for (i = 0; i < ctlr->num_chan; i++) { 304 __raw_writel(0, ctlr->params.txhdp + 4 * i); 305 __raw_writel(0, ctlr->params.rxhdp + 4 * i); 306 __raw_writel(0, ctlr->params.txcp + 4 * i); 307 __raw_writel(0, ctlr->params.rxcp + 4 * i); 308 } 309 310 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); 311 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); 312 313 dma_reg_write(ctlr, CPDMA_TXCONTROL, 1); 314 dma_reg_write(ctlr, CPDMA_RXCONTROL, 1); 315 316 ctlr->state = CPDMA_STATE_ACTIVE; 317 318 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { 319 if (ctlr->channels[i]) 320 cpdma_chan_start(ctlr->channels[i]); 321 } 322 spin_unlock_irqrestore(&ctlr->lock, flags); 323 return 0; 324 } 325 EXPORT_SYMBOL_GPL(cpdma_ctlr_start); 326 327 int cpdma_ctlr_stop(struct cpdma_ctlr *ctlr) 328 { 329 unsigned long flags; 330 int i; 331 332 spin_lock_irqsave(&ctlr->lock, flags); 333 if (ctlr->state != CPDMA_STATE_ACTIVE) { 334 spin_unlock_irqrestore(&ctlr->lock, flags); 335 return -EINVAL; 336 } 337 338 ctlr->state = CPDMA_STATE_TEARDOWN; 339 340 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { 341 if (ctlr->channels[i]) 342 cpdma_chan_stop(ctlr->channels[i]); 343 } 344 345 dma_reg_write(ctlr, CPDMA_RXINTMASKCLEAR, 0xffffffff); 346 dma_reg_write(ctlr, CPDMA_TXINTMASKCLEAR, 0xffffffff); 347 348 dma_reg_write(ctlr, CPDMA_TXCONTROL, 0); 349 dma_reg_write(ctlr, CPDMA_RXCONTROL, 0); 350 351 ctlr->state = CPDMA_STATE_IDLE; 352 353 spin_unlock_irqrestore(&ctlr->lock, flags); 354 return 0; 355 } 356 EXPORT_SYMBOL_GPL(cpdma_ctlr_stop); 357 358 int cpdma_ctlr_dump(struct cpdma_ctlr *ctlr) 359 { 360 struct device *dev = ctlr->dev; 361 unsigned long flags; 362 int i; 363 364 spin_lock_irqsave(&ctlr->lock, flags); 365 366 dev_info(dev, "CPDMA: state: %s", cpdma_state_str[ctlr->state]); 367 368 dev_info(dev, "CPDMA: txidver: %x", 369 dma_reg_read(ctlr, CPDMA_TXIDVER)); 370 dev_info(dev, "CPDMA: txcontrol: %x", 371 dma_reg_read(ctlr, CPDMA_TXCONTROL)); 372 dev_info(dev, "CPDMA: txteardown: %x", 373 dma_reg_read(ctlr, CPDMA_TXTEARDOWN)); 374 dev_info(dev, "CPDMA: rxidver: %x", 375 dma_reg_read(ctlr, CPDMA_RXIDVER)); 376 dev_info(dev, "CPDMA: rxcontrol: %x", 377 dma_reg_read(ctlr, CPDMA_RXCONTROL)); 378 dev_info(dev, "CPDMA: softreset: %x", 379 dma_reg_read(ctlr, CPDMA_SOFTRESET)); 380 dev_info(dev, "CPDMA: rxteardown: %x", 381 dma_reg_read(ctlr, CPDMA_RXTEARDOWN)); 382 dev_info(dev, "CPDMA: txintstatraw: %x", 383 dma_reg_read(ctlr, CPDMA_TXINTSTATRAW)); 384 dev_info(dev, "CPDMA: txintstatmasked: %x", 385 dma_reg_read(ctlr, CPDMA_TXINTSTATMASKED)); 386 dev_info(dev, "CPDMA: txintmaskset: %x", 387 dma_reg_read(ctlr, CPDMA_TXINTMASKSET)); 388 dev_info(dev, "CPDMA: txintmaskclear: %x", 389 dma_reg_read(ctlr, CPDMA_TXINTMASKCLEAR)); 390 dev_info(dev, "CPDMA: macinvector: %x", 391 dma_reg_read(ctlr, CPDMA_MACINVECTOR)); 392 dev_info(dev, "CPDMA: maceoivector: %x", 393 dma_reg_read(ctlr, CPDMA_MACEOIVECTOR)); 394 dev_info(dev, "CPDMA: rxintstatraw: %x", 395 dma_reg_read(ctlr, CPDMA_RXINTSTATRAW)); 396 dev_info(dev, "CPDMA: rxintstatmasked: %x", 397 dma_reg_read(ctlr, CPDMA_RXINTSTATMASKED)); 398 dev_info(dev, "CPDMA: rxintmaskset: %x", 399 dma_reg_read(ctlr, CPDMA_RXINTMASKSET)); 400 dev_info(dev, "CPDMA: rxintmaskclear: %x", 401 dma_reg_read(ctlr, CPDMA_RXINTMASKCLEAR)); 402 dev_info(dev, "CPDMA: dmaintstatraw: %x", 403 dma_reg_read(ctlr, CPDMA_DMAINTSTATRAW)); 404 dev_info(dev, "CPDMA: dmaintstatmasked: %x", 405 dma_reg_read(ctlr, CPDMA_DMAINTSTATMASKED)); 406 dev_info(dev, "CPDMA: dmaintmaskset: %x", 407 dma_reg_read(ctlr, CPDMA_DMAINTMASKSET)); 408 dev_info(dev, "CPDMA: dmaintmaskclear: %x", 409 dma_reg_read(ctlr, CPDMA_DMAINTMASKCLEAR)); 410 411 if (!ctlr->params.has_ext_regs) { 412 dev_info(dev, "CPDMA: dmacontrol: %x", 413 dma_reg_read(ctlr, CPDMA_DMACONTROL)); 414 dev_info(dev, "CPDMA: dmastatus: %x", 415 dma_reg_read(ctlr, CPDMA_DMASTATUS)); 416 dev_info(dev, "CPDMA: rxbuffofs: %x", 417 dma_reg_read(ctlr, CPDMA_RXBUFFOFS)); 418 } 419 420 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) 421 if (ctlr->channels[i]) 422 cpdma_chan_dump(ctlr->channels[i]); 423 424 spin_unlock_irqrestore(&ctlr->lock, flags); 425 return 0; 426 } 427 EXPORT_SYMBOL_GPL(cpdma_ctlr_dump); 428 429 int cpdma_ctlr_destroy(struct cpdma_ctlr *ctlr) 430 { 431 unsigned long flags; 432 int ret = 0, i; 433 434 if (!ctlr) 435 return -EINVAL; 436 437 spin_lock_irqsave(&ctlr->lock, flags); 438 if (ctlr->state != CPDMA_STATE_IDLE) 439 cpdma_ctlr_stop(ctlr); 440 441 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { 442 if (ctlr->channels[i]) 443 cpdma_chan_destroy(ctlr->channels[i]); 444 } 445 446 cpdma_desc_pool_destroy(ctlr->pool); 447 spin_unlock_irqrestore(&ctlr->lock, flags); 448 kfree(ctlr); 449 return ret; 450 } 451 EXPORT_SYMBOL_GPL(cpdma_ctlr_destroy); 452 453 int cpdma_ctlr_int_ctrl(struct cpdma_ctlr *ctlr, bool enable) 454 { 455 unsigned long flags; 456 int i, reg; 457 458 spin_lock_irqsave(&ctlr->lock, flags); 459 if (ctlr->state != CPDMA_STATE_ACTIVE) { 460 spin_unlock_irqrestore(&ctlr->lock, flags); 461 return -EINVAL; 462 } 463 464 reg = enable ? CPDMA_DMAINTMASKSET : CPDMA_DMAINTMASKCLEAR; 465 dma_reg_write(ctlr, reg, CPDMA_DMAINT_HOSTERR); 466 467 for (i = 0; i < ARRAY_SIZE(ctlr->channels); i++) { 468 if (ctlr->channels[i]) 469 cpdma_chan_int_ctrl(ctlr->channels[i], enable); 470 } 471 472 spin_unlock_irqrestore(&ctlr->lock, flags); 473 return 0; 474 } 475 476 void cpdma_ctlr_eoi(struct cpdma_ctlr *ctlr) 477 { 478 dma_reg_write(ctlr, CPDMA_MACEOIVECTOR, 0); 479 } 480 481 struct cpdma_chan *cpdma_chan_create(struct cpdma_ctlr *ctlr, int chan_num, 482 cpdma_handler_fn handler) 483 { 484 struct cpdma_chan *chan; 485 int ret, offset = (chan_num % CPDMA_MAX_CHANNELS) * 4; 486 unsigned long flags; 487 488 if (__chan_linear(chan_num) >= ctlr->num_chan) 489 return NULL; 490 491 ret = -ENOMEM; 492 chan = kzalloc(sizeof(*chan), GFP_KERNEL); 493 if (!chan) 494 goto err_chan_alloc; 495 496 spin_lock_irqsave(&ctlr->lock, flags); 497 ret = -EBUSY; 498 if (ctlr->channels[chan_num]) 499 goto err_chan_busy; 500 501 chan->ctlr = ctlr; 502 chan->state = CPDMA_STATE_IDLE; 503 chan->chan_num = chan_num; 504 chan->handler = handler; 505 506 if (is_rx_chan(chan)) { 507 chan->hdp = ctlr->params.rxhdp + offset; 508 chan->cp = ctlr->params.rxcp + offset; 509 chan->rxfree = ctlr->params.rxfree + offset; 510 chan->int_set = CPDMA_RXINTMASKSET; 511 chan->int_clear = CPDMA_RXINTMASKCLEAR; 512 chan->td = CPDMA_RXTEARDOWN; 513 chan->dir = DMA_FROM_DEVICE; 514 } else { 515 chan->hdp = ctlr->params.txhdp + offset; 516 chan->cp = ctlr->params.txcp + offset; 517 chan->int_set = CPDMA_TXINTMASKSET; 518 chan->int_clear = CPDMA_TXINTMASKCLEAR; 519 chan->td = CPDMA_TXTEARDOWN; 520 chan->dir = DMA_TO_DEVICE; 521 } 522 chan->mask = BIT(chan_linear(chan)); 523 524 spin_lock_init(&chan->lock); 525 526 ctlr->channels[chan_num] = chan; 527 spin_unlock_irqrestore(&ctlr->lock, flags); 528 return chan; 529 530 err_chan_busy: 531 spin_unlock_irqrestore(&ctlr->lock, flags); 532 kfree(chan); 533 err_chan_alloc: 534 return ERR_PTR(ret); 535 } 536 EXPORT_SYMBOL_GPL(cpdma_chan_create); 537 538 int cpdma_chan_destroy(struct cpdma_chan *chan) 539 { 540 struct cpdma_ctlr *ctlr = chan->ctlr; 541 unsigned long flags; 542 543 if (!chan) 544 return -EINVAL; 545 546 spin_lock_irqsave(&ctlr->lock, flags); 547 if (chan->state != CPDMA_STATE_IDLE) 548 cpdma_chan_stop(chan); 549 ctlr->channels[chan->chan_num] = NULL; 550 spin_unlock_irqrestore(&ctlr->lock, flags); 551 kfree(chan); 552 return 0; 553 } 554 EXPORT_SYMBOL_GPL(cpdma_chan_destroy); 555 556 int cpdma_chan_get_stats(struct cpdma_chan *chan, 557 struct cpdma_chan_stats *stats) 558 { 559 unsigned long flags; 560 if (!chan) 561 return -EINVAL; 562 spin_lock_irqsave(&chan->lock, flags); 563 memcpy(stats, &chan->stats, sizeof(*stats)); 564 spin_unlock_irqrestore(&chan->lock, flags); 565 return 0; 566 } 567 568 int cpdma_chan_dump(struct cpdma_chan *chan) 569 { 570 unsigned long flags; 571 struct device *dev = chan->ctlr->dev; 572 573 spin_lock_irqsave(&chan->lock, flags); 574 575 dev_info(dev, "channel %d (%s %d) state %s", 576 chan->chan_num, is_rx_chan(chan) ? "rx" : "tx", 577 chan_linear(chan), cpdma_state_str[chan->state]); 578 dev_info(dev, "\thdp: %x\n", chan_read(chan, hdp)); 579 dev_info(dev, "\tcp: %x\n", chan_read(chan, cp)); 580 if (chan->rxfree) { 581 dev_info(dev, "\trxfree: %x\n", 582 chan_read(chan, rxfree)); 583 } 584 585 dev_info(dev, "\tstats head_enqueue: %d\n", 586 chan->stats.head_enqueue); 587 dev_info(dev, "\tstats tail_enqueue: %d\n", 588 chan->stats.tail_enqueue); 589 dev_info(dev, "\tstats pad_enqueue: %d\n", 590 chan->stats.pad_enqueue); 591 dev_info(dev, "\tstats misqueued: %d\n", 592 chan->stats.misqueued); 593 dev_info(dev, "\tstats desc_alloc_fail: %d\n", 594 chan->stats.desc_alloc_fail); 595 dev_info(dev, "\tstats pad_alloc_fail: %d\n", 596 chan->stats.pad_alloc_fail); 597 dev_info(dev, "\tstats runt_receive_buff: %d\n", 598 chan->stats.runt_receive_buff); 599 dev_info(dev, "\tstats runt_transmit_buff: %d\n", 600 chan->stats.runt_transmit_buff); 601 dev_info(dev, "\tstats empty_dequeue: %d\n", 602 chan->stats.empty_dequeue); 603 dev_info(dev, "\tstats busy_dequeue: %d\n", 604 chan->stats.busy_dequeue); 605 dev_info(dev, "\tstats good_dequeue: %d\n", 606 chan->stats.good_dequeue); 607 dev_info(dev, "\tstats requeue: %d\n", 608 chan->stats.requeue); 609 dev_info(dev, "\tstats teardown_dequeue: %d\n", 610 chan->stats.teardown_dequeue); 611 612 spin_unlock_irqrestore(&chan->lock, flags); 613 return 0; 614 } 615 616 static void __cpdma_chan_submit(struct cpdma_chan *chan, 617 struct cpdma_desc __iomem *desc) 618 { 619 struct cpdma_ctlr *ctlr = chan->ctlr; 620 struct cpdma_desc __iomem *prev = chan->tail; 621 struct cpdma_desc_pool *pool = ctlr->pool; 622 dma_addr_t desc_dma; 623 u32 mode; 624 625 desc_dma = desc_phys(pool, desc); 626 627 /* simple case - idle channel */ 628 if (!chan->head) { 629 chan->stats.head_enqueue++; 630 chan->head = desc; 631 chan->tail = desc; 632 if (chan->state == CPDMA_STATE_ACTIVE) 633 chan_write(chan, hdp, desc_dma); 634 return; 635 } 636 637 /* first chain the descriptor at the tail of the list */ 638 desc_write(prev, hw_next, desc_dma); 639 chan->tail = desc; 640 chan->stats.tail_enqueue++; 641 642 /* next check if EOQ has been triggered already */ 643 mode = desc_read(prev, hw_mode); 644 if (((mode & (CPDMA_DESC_EOQ | CPDMA_DESC_OWNER)) == CPDMA_DESC_EOQ) && 645 (chan->state == CPDMA_STATE_ACTIVE)) { 646 desc_write(prev, hw_mode, mode & ~CPDMA_DESC_EOQ); 647 chan_write(chan, hdp, desc_dma); 648 chan->stats.misqueued++; 649 } 650 } 651 652 int cpdma_chan_submit(struct cpdma_chan *chan, void *token, void *data, 653 int len, gfp_t gfp_mask) 654 { 655 struct cpdma_ctlr *ctlr = chan->ctlr; 656 struct cpdma_desc __iomem *desc; 657 dma_addr_t buffer; 658 unsigned long flags; 659 u32 mode; 660 int ret = 0; 661 662 spin_lock_irqsave(&chan->lock, flags); 663 664 if (chan->state == CPDMA_STATE_TEARDOWN) { 665 ret = -EINVAL; 666 goto unlock_ret; 667 } 668 669 desc = cpdma_desc_alloc(ctlr->pool, 1); 670 if (!desc) { 671 chan->stats.desc_alloc_fail++; 672 ret = -ENOMEM; 673 goto unlock_ret; 674 } 675 676 if (len < ctlr->params.min_packet_size) { 677 len = ctlr->params.min_packet_size; 678 chan->stats.runt_transmit_buff++; 679 } 680 681 buffer = dma_map_single(ctlr->dev, data, len, chan->dir); 682 mode = CPDMA_DESC_OWNER | CPDMA_DESC_SOP | CPDMA_DESC_EOP; 683 684 desc_write(desc, hw_next, 0); 685 desc_write(desc, hw_buffer, buffer); 686 desc_write(desc, hw_len, len); 687 desc_write(desc, hw_mode, mode | len); 688 desc_write(desc, sw_token, token); 689 desc_write(desc, sw_buffer, buffer); 690 desc_write(desc, sw_len, len); 691 692 __cpdma_chan_submit(chan, desc); 693 694 if (chan->state == CPDMA_STATE_ACTIVE && chan->rxfree) 695 chan_write(chan, rxfree, 1); 696 697 chan->count++; 698 699 unlock_ret: 700 spin_unlock_irqrestore(&chan->lock, flags); 701 return ret; 702 } 703 EXPORT_SYMBOL_GPL(cpdma_chan_submit); 704 705 static void __cpdma_chan_free(struct cpdma_chan *chan, 706 struct cpdma_desc __iomem *desc, 707 int outlen, int status) 708 { 709 struct cpdma_ctlr *ctlr = chan->ctlr; 710 struct cpdma_desc_pool *pool = ctlr->pool; 711 dma_addr_t buff_dma; 712 int origlen; 713 void *token; 714 715 token = (void *)desc_read(desc, sw_token); 716 buff_dma = desc_read(desc, sw_buffer); 717 origlen = desc_read(desc, sw_len); 718 719 dma_unmap_single(ctlr->dev, buff_dma, origlen, chan->dir); 720 cpdma_desc_free(pool, desc, 1); 721 (*chan->handler)(token, outlen, status); 722 } 723 724 static int __cpdma_chan_process(struct cpdma_chan *chan) 725 { 726 struct cpdma_ctlr *ctlr = chan->ctlr; 727 struct cpdma_desc __iomem *desc; 728 int status, outlen; 729 struct cpdma_desc_pool *pool = ctlr->pool; 730 dma_addr_t desc_dma; 731 unsigned long flags; 732 733 spin_lock_irqsave(&chan->lock, flags); 734 735 desc = chan->head; 736 if (!desc) { 737 chan->stats.empty_dequeue++; 738 status = -ENOENT; 739 goto unlock_ret; 740 } 741 desc_dma = desc_phys(pool, desc); 742 743 status = __raw_readl(&desc->hw_mode); 744 outlen = status & 0x7ff; 745 if (status & CPDMA_DESC_OWNER) { 746 chan->stats.busy_dequeue++; 747 status = -EBUSY; 748 goto unlock_ret; 749 } 750 status = status & (CPDMA_DESC_EOQ | CPDMA_DESC_TD_COMPLETE); 751 752 chan->head = desc_from_phys(pool, desc_read(desc, hw_next)); 753 chan_write(chan, cp, desc_dma); 754 chan->count--; 755 chan->stats.good_dequeue++; 756 757 if (status & CPDMA_DESC_EOQ) { 758 chan->stats.requeue++; 759 chan_write(chan, hdp, desc_phys(pool, chan->head)); 760 } 761 762 spin_unlock_irqrestore(&chan->lock, flags); 763 764 __cpdma_chan_free(chan, desc, outlen, status); 765 return status; 766 767 unlock_ret: 768 spin_unlock_irqrestore(&chan->lock, flags); 769 return status; 770 } 771 772 int cpdma_chan_process(struct cpdma_chan *chan, int quota) 773 { 774 int used = 0, ret = 0; 775 776 if (chan->state != CPDMA_STATE_ACTIVE) 777 return -EINVAL; 778 779 while (used < quota) { 780 ret = __cpdma_chan_process(chan); 781 if (ret < 0) 782 break; 783 used++; 784 } 785 return used; 786 } 787 EXPORT_SYMBOL_GPL(cpdma_chan_process); 788 789 int cpdma_chan_start(struct cpdma_chan *chan) 790 { 791 struct cpdma_ctlr *ctlr = chan->ctlr; 792 struct cpdma_desc_pool *pool = ctlr->pool; 793 unsigned long flags; 794 795 spin_lock_irqsave(&chan->lock, flags); 796 if (chan->state != CPDMA_STATE_IDLE) { 797 spin_unlock_irqrestore(&chan->lock, flags); 798 return -EBUSY; 799 } 800 if (ctlr->state != CPDMA_STATE_ACTIVE) { 801 spin_unlock_irqrestore(&chan->lock, flags); 802 return -EINVAL; 803 } 804 dma_reg_write(ctlr, chan->int_set, chan->mask); 805 chan->state = CPDMA_STATE_ACTIVE; 806 if (chan->head) { 807 chan_write(chan, hdp, desc_phys(pool, chan->head)); 808 if (chan->rxfree) 809 chan_write(chan, rxfree, chan->count); 810 } 811 812 spin_unlock_irqrestore(&chan->lock, flags); 813 return 0; 814 } 815 EXPORT_SYMBOL_GPL(cpdma_chan_start); 816 817 int cpdma_chan_stop(struct cpdma_chan *chan) 818 { 819 struct cpdma_ctlr *ctlr = chan->ctlr; 820 struct cpdma_desc_pool *pool = ctlr->pool; 821 unsigned long flags; 822 int ret; 823 unsigned long timeout; 824 825 spin_lock_irqsave(&chan->lock, flags); 826 if (chan->state != CPDMA_STATE_ACTIVE) { 827 spin_unlock_irqrestore(&chan->lock, flags); 828 return -EINVAL; 829 } 830 831 chan->state = CPDMA_STATE_TEARDOWN; 832 dma_reg_write(ctlr, chan->int_clear, chan->mask); 833 834 /* trigger teardown */ 835 dma_reg_write(ctlr, chan->td, chan_linear(chan)); 836 837 /* wait for teardown complete */ 838 timeout = jiffies + HZ/10; /* 100 msec */ 839 while (time_before(jiffies, timeout)) { 840 u32 cp = chan_read(chan, cp); 841 if ((cp & CPDMA_TEARDOWN_VALUE) == CPDMA_TEARDOWN_VALUE) 842 break; 843 cpu_relax(); 844 } 845 WARN_ON(!time_before(jiffies, timeout)); 846 chan_write(chan, cp, CPDMA_TEARDOWN_VALUE); 847 848 /* handle completed packets */ 849 spin_unlock_irqrestore(&chan->lock, flags); 850 do { 851 ret = __cpdma_chan_process(chan); 852 if (ret < 0) 853 break; 854 } while ((ret & CPDMA_DESC_TD_COMPLETE) == 0); 855 spin_lock_irqsave(&chan->lock, flags); 856 857 /* remaining packets haven't been tx/rx'ed, clean them up */ 858 while (chan->head) { 859 struct cpdma_desc __iomem *desc = chan->head; 860 dma_addr_t next_dma; 861 862 next_dma = desc_read(desc, hw_next); 863 chan->head = desc_from_phys(pool, next_dma); 864 chan->stats.teardown_dequeue++; 865 866 /* issue callback without locks held */ 867 spin_unlock_irqrestore(&chan->lock, flags); 868 __cpdma_chan_free(chan, desc, 0, -ENOSYS); 869 spin_lock_irqsave(&chan->lock, flags); 870 } 871 872 chan->state = CPDMA_STATE_IDLE; 873 spin_unlock_irqrestore(&chan->lock, flags); 874 return 0; 875 } 876 EXPORT_SYMBOL_GPL(cpdma_chan_stop); 877 878 int cpdma_chan_int_ctrl(struct cpdma_chan *chan, bool enable) 879 { 880 unsigned long flags; 881 882 spin_lock_irqsave(&chan->lock, flags); 883 if (chan->state != CPDMA_STATE_ACTIVE) { 884 spin_unlock_irqrestore(&chan->lock, flags); 885 return -EINVAL; 886 } 887 888 dma_reg_write(chan->ctlr, enable ? chan->int_set : chan->int_clear, 889 chan->mask); 890 spin_unlock_irqrestore(&chan->lock, flags); 891 892 return 0; 893 } 894 895 struct cpdma_control_info { 896 u32 reg; 897 u32 shift, mask; 898 int access; 899 #define ACCESS_RO BIT(0) 900 #define ACCESS_WO BIT(1) 901 #define ACCESS_RW (ACCESS_RO | ACCESS_WO) 902 }; 903 904 struct cpdma_control_info controls[] = { 905 [CPDMA_CMD_IDLE] = {CPDMA_DMACONTROL, 3, 1, ACCESS_WO}, 906 [CPDMA_COPY_ERROR_FRAMES] = {CPDMA_DMACONTROL, 4, 1, ACCESS_RW}, 907 [CPDMA_RX_OFF_LEN_UPDATE] = {CPDMA_DMACONTROL, 2, 1, ACCESS_RW}, 908 [CPDMA_RX_OWNERSHIP_FLIP] = {CPDMA_DMACONTROL, 1, 1, ACCESS_RW}, 909 [CPDMA_TX_PRIO_FIXED] = {CPDMA_DMACONTROL, 0, 1, ACCESS_RW}, 910 [CPDMA_STAT_IDLE] = {CPDMA_DMASTATUS, 31, 1, ACCESS_RO}, 911 [CPDMA_STAT_TX_ERR_CODE] = {CPDMA_DMASTATUS, 20, 0xf, ACCESS_RW}, 912 [CPDMA_STAT_TX_ERR_CHAN] = {CPDMA_DMASTATUS, 16, 0x7, ACCESS_RW}, 913 [CPDMA_STAT_RX_ERR_CODE] = {CPDMA_DMASTATUS, 12, 0xf, ACCESS_RW}, 914 [CPDMA_STAT_RX_ERR_CHAN] = {CPDMA_DMASTATUS, 8, 0x7, ACCESS_RW}, 915 [CPDMA_RX_BUFFER_OFFSET] = {CPDMA_RXBUFFOFS, 0, 0xffff, ACCESS_RW}, 916 }; 917 918 int cpdma_control_get(struct cpdma_ctlr *ctlr, int control) 919 { 920 unsigned long flags; 921 struct cpdma_control_info *info = &controls[control]; 922 int ret; 923 924 spin_lock_irqsave(&ctlr->lock, flags); 925 926 ret = -ENOTSUPP; 927 if (!ctlr->params.has_ext_regs) 928 goto unlock_ret; 929 930 ret = -EINVAL; 931 if (ctlr->state != CPDMA_STATE_ACTIVE) 932 goto unlock_ret; 933 934 ret = -ENOENT; 935 if (control < 0 || control >= ARRAY_SIZE(controls)) 936 goto unlock_ret; 937 938 ret = -EPERM; 939 if ((info->access & ACCESS_RO) != ACCESS_RO) 940 goto unlock_ret; 941 942 ret = (dma_reg_read(ctlr, info->reg) >> info->shift) & info->mask; 943 944 unlock_ret: 945 spin_unlock_irqrestore(&ctlr->lock, flags); 946 return ret; 947 } 948 949 int cpdma_control_set(struct cpdma_ctlr *ctlr, int control, int value) 950 { 951 unsigned long flags; 952 struct cpdma_control_info *info = &controls[control]; 953 int ret; 954 u32 val; 955 956 spin_lock_irqsave(&ctlr->lock, flags); 957 958 ret = -ENOTSUPP; 959 if (!ctlr->params.has_ext_regs) 960 goto unlock_ret; 961 962 ret = -EINVAL; 963 if (ctlr->state != CPDMA_STATE_ACTIVE) 964 goto unlock_ret; 965 966 ret = -ENOENT; 967 if (control < 0 || control >= ARRAY_SIZE(controls)) 968 goto unlock_ret; 969 970 ret = -EPERM; 971 if ((info->access & ACCESS_WO) != ACCESS_WO) 972 goto unlock_ret; 973 974 val = dma_reg_read(ctlr, info->reg); 975 val &= ~(info->mask << info->shift); 976 val |= (value & info->mask) << info->shift; 977 dma_reg_write(ctlr, info->reg, val); 978 ret = 0; 979 980 unlock_ret: 981 spin_unlock_irqrestore(&ctlr->lock, flags); 982 return ret; 983 } 984