1 /* 2 * Texas Instruments Ethernet Switch Driver 3 * 4 * Copyright (C) 2012 Texas Instruments 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/io.h> 18 #include <linux/clk.h> 19 #include <linux/timer.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/irqreturn.h> 23 #include <linux/interrupt.h> 24 #include <linux/if_ether.h> 25 #include <linux/etherdevice.h> 26 #include <linux/netdevice.h> 27 #include <linux/net_tstamp.h> 28 #include <linux/phy.h> 29 #include <linux/workqueue.h> 30 #include <linux/delay.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/of.h> 33 #include <linux/of_net.h> 34 #include <linux/of_device.h> 35 #include <linux/if_vlan.h> 36 37 #include <linux/pinctrl/consumer.h> 38 39 #include "cpsw.h" 40 #include "cpsw_ale.h" 41 #include "cpts.h" 42 #include "davinci_cpdma.h" 43 44 #define CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_WOL | \ 45 NETIF_MSG_DRV | NETIF_MSG_LINK | \ 46 NETIF_MSG_IFUP | NETIF_MSG_INTR | \ 47 NETIF_MSG_PROBE | NETIF_MSG_TIMER | \ 48 NETIF_MSG_IFDOWN | NETIF_MSG_RX_ERR | \ 49 NETIF_MSG_TX_ERR | NETIF_MSG_TX_DONE | \ 50 NETIF_MSG_PKTDATA | NETIF_MSG_TX_QUEUED | \ 51 NETIF_MSG_RX_STATUS) 52 53 #define cpsw_info(priv, type, format, ...) \ 54 do { \ 55 if (netif_msg_##type(priv) && net_ratelimit()) \ 56 dev_info(priv->dev, format, ## __VA_ARGS__); \ 57 } while (0) 58 59 #define cpsw_err(priv, type, format, ...) \ 60 do { \ 61 if (netif_msg_##type(priv) && net_ratelimit()) \ 62 dev_err(priv->dev, format, ## __VA_ARGS__); \ 63 } while (0) 64 65 #define cpsw_dbg(priv, type, format, ...) \ 66 do { \ 67 if (netif_msg_##type(priv) && net_ratelimit()) \ 68 dev_dbg(priv->dev, format, ## __VA_ARGS__); \ 69 } while (0) 70 71 #define cpsw_notice(priv, type, format, ...) \ 72 do { \ 73 if (netif_msg_##type(priv) && net_ratelimit()) \ 74 dev_notice(priv->dev, format, ## __VA_ARGS__); \ 75 } while (0) 76 77 #define ALE_ALL_PORTS 0x7 78 79 #define CPSW_MAJOR_VERSION(reg) (reg >> 8 & 0x7) 80 #define CPSW_MINOR_VERSION(reg) (reg & 0xff) 81 #define CPSW_RTL_VERSION(reg) ((reg >> 11) & 0x1f) 82 83 #define CPSW_VERSION_1 0x19010a 84 #define CPSW_VERSION_2 0x19010c 85 #define CPSW_VERSION_3 0x19010f 86 #define CPSW_VERSION_4 0x190112 87 88 #define HOST_PORT_NUM 0 89 #define SLIVER_SIZE 0x40 90 91 #define CPSW1_HOST_PORT_OFFSET 0x028 92 #define CPSW1_SLAVE_OFFSET 0x050 93 #define CPSW1_SLAVE_SIZE 0x040 94 #define CPSW1_CPDMA_OFFSET 0x100 95 #define CPSW1_STATERAM_OFFSET 0x200 96 #define CPSW1_HW_STATS 0x400 97 #define CPSW1_CPTS_OFFSET 0x500 98 #define CPSW1_ALE_OFFSET 0x600 99 #define CPSW1_SLIVER_OFFSET 0x700 100 101 #define CPSW2_HOST_PORT_OFFSET 0x108 102 #define CPSW2_SLAVE_OFFSET 0x200 103 #define CPSW2_SLAVE_SIZE 0x100 104 #define CPSW2_CPDMA_OFFSET 0x800 105 #define CPSW2_HW_STATS 0x900 106 #define CPSW2_STATERAM_OFFSET 0xa00 107 #define CPSW2_CPTS_OFFSET 0xc00 108 #define CPSW2_ALE_OFFSET 0xd00 109 #define CPSW2_SLIVER_OFFSET 0xd80 110 #define CPSW2_BD_OFFSET 0x2000 111 112 #define CPDMA_RXTHRESH 0x0c0 113 #define CPDMA_RXFREE 0x0e0 114 #define CPDMA_TXHDP 0x00 115 #define CPDMA_RXHDP 0x20 116 #define CPDMA_TXCP 0x40 117 #define CPDMA_RXCP 0x60 118 119 #define CPSW_POLL_WEIGHT 64 120 #define CPSW_MIN_PACKET_SIZE 60 121 #define CPSW_MAX_PACKET_SIZE (1500 + 14 + 4 + 4) 122 123 #define RX_PRIORITY_MAPPING 0x76543210 124 #define TX_PRIORITY_MAPPING 0x33221100 125 #define CPDMA_TX_PRIORITY_MAP 0x76543210 126 127 #define CPSW_VLAN_AWARE BIT(1) 128 #define CPSW_ALE_VLAN_AWARE 1 129 130 #define CPSW_FIFO_NORMAL_MODE (0 << 15) 131 #define CPSW_FIFO_DUAL_MAC_MODE (1 << 15) 132 #define CPSW_FIFO_RATE_LIMIT_MODE (2 << 15) 133 134 #define CPSW_INTPACEEN (0x3f << 16) 135 #define CPSW_INTPRESCALE_MASK (0x7FF << 0) 136 #define CPSW_CMINTMAX_CNT 63 137 #define CPSW_CMINTMIN_CNT 2 138 #define CPSW_CMINTMAX_INTVL (1000 / CPSW_CMINTMIN_CNT) 139 #define CPSW_CMINTMIN_INTVL ((1000 / CPSW_CMINTMAX_CNT) + 1) 140 141 #define cpsw_enable_irq(priv) \ 142 do { \ 143 u32 i; \ 144 for (i = 0; i < priv->num_irqs; i++) \ 145 enable_irq(priv->irqs_table[i]); \ 146 } while (0); 147 #define cpsw_disable_irq(priv) \ 148 do { \ 149 u32 i; \ 150 for (i = 0; i < priv->num_irqs; i++) \ 151 disable_irq_nosync(priv->irqs_table[i]); \ 152 } while (0); 153 154 #define cpsw_slave_index(priv) \ 155 ((priv->data.dual_emac) ? priv->emac_port : \ 156 priv->data.active_slave) 157 158 static int debug_level; 159 module_param(debug_level, int, 0); 160 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)"); 161 162 static int ale_ageout = 10; 163 module_param(ale_ageout, int, 0); 164 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)"); 165 166 static int rx_packet_max = CPSW_MAX_PACKET_SIZE; 167 module_param(rx_packet_max, int, 0); 168 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)"); 169 170 struct cpsw_wr_regs { 171 u32 id_ver; 172 u32 soft_reset; 173 u32 control; 174 u32 int_control; 175 u32 rx_thresh_en; 176 u32 rx_en; 177 u32 tx_en; 178 u32 misc_en; 179 u32 mem_allign1[8]; 180 u32 rx_thresh_stat; 181 u32 rx_stat; 182 u32 tx_stat; 183 u32 misc_stat; 184 u32 mem_allign2[8]; 185 u32 rx_imax; 186 u32 tx_imax; 187 188 }; 189 190 struct cpsw_ss_regs { 191 u32 id_ver; 192 u32 control; 193 u32 soft_reset; 194 u32 stat_port_en; 195 u32 ptype; 196 u32 soft_idle; 197 u32 thru_rate; 198 u32 gap_thresh; 199 u32 tx_start_wds; 200 u32 flow_control; 201 u32 vlan_ltype; 202 u32 ts_ltype; 203 u32 dlr_ltype; 204 }; 205 206 /* CPSW_PORT_V1 */ 207 #define CPSW1_MAX_BLKS 0x00 /* Maximum FIFO Blocks */ 208 #define CPSW1_BLK_CNT 0x04 /* FIFO Block Usage Count (Read Only) */ 209 #define CPSW1_TX_IN_CTL 0x08 /* Transmit FIFO Control */ 210 #define CPSW1_PORT_VLAN 0x0c /* VLAN Register */ 211 #define CPSW1_TX_PRI_MAP 0x10 /* Tx Header Priority to Switch Pri Mapping */ 212 #define CPSW1_TS_CTL 0x14 /* Time Sync Control */ 213 #define CPSW1_TS_SEQ_LTYPE 0x18 /* Time Sync Sequence ID Offset and Msg Type */ 214 #define CPSW1_TS_VLAN 0x1c /* Time Sync VLAN1 and VLAN2 */ 215 216 /* CPSW_PORT_V2 */ 217 #define CPSW2_CONTROL 0x00 /* Control Register */ 218 #define CPSW2_MAX_BLKS 0x08 /* Maximum FIFO Blocks */ 219 #define CPSW2_BLK_CNT 0x0c /* FIFO Block Usage Count (Read Only) */ 220 #define CPSW2_TX_IN_CTL 0x10 /* Transmit FIFO Control */ 221 #define CPSW2_PORT_VLAN 0x14 /* VLAN Register */ 222 #define CPSW2_TX_PRI_MAP 0x18 /* Tx Header Priority to Switch Pri Mapping */ 223 #define CPSW2_TS_SEQ_MTYPE 0x1c /* Time Sync Sequence ID Offset and Msg Type */ 224 225 /* CPSW_PORT_V1 and V2 */ 226 #define SA_LO 0x20 /* CPGMAC_SL Source Address Low */ 227 #define SA_HI 0x24 /* CPGMAC_SL Source Address High */ 228 #define SEND_PERCENT 0x28 /* Transmit Queue Send Percentages */ 229 230 /* CPSW_PORT_V2 only */ 231 #define RX_DSCP_PRI_MAP0 0x30 /* Rx DSCP Priority to Rx Packet Mapping */ 232 #define RX_DSCP_PRI_MAP1 0x34 /* Rx DSCP Priority to Rx Packet Mapping */ 233 #define RX_DSCP_PRI_MAP2 0x38 /* Rx DSCP Priority to Rx Packet Mapping */ 234 #define RX_DSCP_PRI_MAP3 0x3c /* Rx DSCP Priority to Rx Packet Mapping */ 235 #define RX_DSCP_PRI_MAP4 0x40 /* Rx DSCP Priority to Rx Packet Mapping */ 236 #define RX_DSCP_PRI_MAP5 0x44 /* Rx DSCP Priority to Rx Packet Mapping */ 237 #define RX_DSCP_PRI_MAP6 0x48 /* Rx DSCP Priority to Rx Packet Mapping */ 238 #define RX_DSCP_PRI_MAP7 0x4c /* Rx DSCP Priority to Rx Packet Mapping */ 239 240 /* Bit definitions for the CPSW2_CONTROL register */ 241 #define PASS_PRI_TAGGED (1<<24) /* Pass Priority Tagged */ 242 #define VLAN_LTYPE2_EN (1<<21) /* VLAN LTYPE 2 enable */ 243 #define VLAN_LTYPE1_EN (1<<20) /* VLAN LTYPE 1 enable */ 244 #define DSCP_PRI_EN (1<<16) /* DSCP Priority Enable */ 245 #define TS_320 (1<<14) /* Time Sync Dest Port 320 enable */ 246 #define TS_319 (1<<13) /* Time Sync Dest Port 319 enable */ 247 #define TS_132 (1<<12) /* Time Sync Dest IP Addr 132 enable */ 248 #define TS_131 (1<<11) /* Time Sync Dest IP Addr 131 enable */ 249 #define TS_130 (1<<10) /* Time Sync Dest IP Addr 130 enable */ 250 #define TS_129 (1<<9) /* Time Sync Dest IP Addr 129 enable */ 251 #define TS_BIT8 (1<<8) /* ts_ttl_nonzero? */ 252 #define TS_ANNEX_D_EN (1<<4) /* Time Sync Annex D enable */ 253 #define TS_LTYPE2_EN (1<<3) /* Time Sync LTYPE 2 enable */ 254 #define TS_LTYPE1_EN (1<<2) /* Time Sync LTYPE 1 enable */ 255 #define TS_TX_EN (1<<1) /* Time Sync Transmit Enable */ 256 #define TS_RX_EN (1<<0) /* Time Sync Receive Enable */ 257 258 #define CTRL_TS_BITS \ 259 (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 | TS_BIT8 | \ 260 TS_ANNEX_D_EN | TS_LTYPE1_EN) 261 262 #define CTRL_ALL_TS_MASK (CTRL_TS_BITS | TS_TX_EN | TS_RX_EN) 263 #define CTRL_TX_TS_BITS (CTRL_TS_BITS | TS_TX_EN) 264 #define CTRL_RX_TS_BITS (CTRL_TS_BITS | TS_RX_EN) 265 266 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */ 267 #define TS_SEQ_ID_OFFSET_SHIFT (16) /* Time Sync Sequence ID Offset */ 268 #define TS_SEQ_ID_OFFSET_MASK (0x3f) 269 #define TS_MSG_TYPE_EN_SHIFT (0) /* Time Sync Message Type Enable */ 270 #define TS_MSG_TYPE_EN_MASK (0xffff) 271 272 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 273 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3)) 274 275 /* Bit definitions for the CPSW1_TS_CTL register */ 276 #define CPSW_V1_TS_RX_EN BIT(0) 277 #define CPSW_V1_TS_TX_EN BIT(4) 278 #define CPSW_V1_MSG_TYPE_OFS 16 279 280 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */ 281 #define CPSW_V1_SEQ_ID_OFS_SHIFT 16 282 283 struct cpsw_host_regs { 284 u32 max_blks; 285 u32 blk_cnt; 286 u32 tx_in_ctl; 287 u32 port_vlan; 288 u32 tx_pri_map; 289 u32 cpdma_tx_pri_map; 290 u32 cpdma_rx_chan_map; 291 }; 292 293 struct cpsw_sliver_regs { 294 u32 id_ver; 295 u32 mac_control; 296 u32 mac_status; 297 u32 soft_reset; 298 u32 rx_maxlen; 299 u32 __reserved_0; 300 u32 rx_pause; 301 u32 tx_pause; 302 u32 __reserved_1; 303 u32 rx_pri_map; 304 }; 305 306 struct cpsw_hw_stats { 307 u32 rxgoodframes; 308 u32 rxbroadcastframes; 309 u32 rxmulticastframes; 310 u32 rxpauseframes; 311 u32 rxcrcerrors; 312 u32 rxaligncodeerrors; 313 u32 rxoversizedframes; 314 u32 rxjabberframes; 315 u32 rxundersizedframes; 316 u32 rxfragments; 317 u32 __pad_0[2]; 318 u32 rxoctets; 319 u32 txgoodframes; 320 u32 txbroadcastframes; 321 u32 txmulticastframes; 322 u32 txpauseframes; 323 u32 txdeferredframes; 324 u32 txcollisionframes; 325 u32 txsinglecollframes; 326 u32 txmultcollframes; 327 u32 txexcessivecollisions; 328 u32 txlatecollisions; 329 u32 txunderrun; 330 u32 txcarriersenseerrors; 331 u32 txoctets; 332 u32 octetframes64; 333 u32 octetframes65t127; 334 u32 octetframes128t255; 335 u32 octetframes256t511; 336 u32 octetframes512t1023; 337 u32 octetframes1024tup; 338 u32 netoctets; 339 u32 rxsofoverruns; 340 u32 rxmofoverruns; 341 u32 rxdmaoverruns; 342 }; 343 344 struct cpsw_slave { 345 void __iomem *regs; 346 struct cpsw_sliver_regs __iomem *sliver; 347 int slave_num; 348 u32 mac_control; 349 struct cpsw_slave_data *data; 350 struct phy_device *phy; 351 struct net_device *ndev; 352 u32 port_vlan; 353 u32 open_stat; 354 }; 355 356 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset) 357 { 358 return __raw_readl(slave->regs + offset); 359 } 360 361 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset) 362 { 363 __raw_writel(val, slave->regs + offset); 364 } 365 366 struct cpsw_priv { 367 spinlock_t lock; 368 struct platform_device *pdev; 369 struct net_device *ndev; 370 struct napi_struct napi; 371 struct device *dev; 372 struct cpsw_platform_data data; 373 struct cpsw_ss_regs __iomem *regs; 374 struct cpsw_wr_regs __iomem *wr_regs; 375 u8 __iomem *hw_stats; 376 struct cpsw_host_regs __iomem *host_port_regs; 377 u32 msg_enable; 378 u32 version; 379 u32 coal_intvl; 380 u32 bus_freq_mhz; 381 struct net_device_stats stats; 382 int rx_packet_max; 383 int host_port; 384 struct clk *clk; 385 u8 mac_addr[ETH_ALEN]; 386 struct cpsw_slave *slaves; 387 struct cpdma_ctlr *dma; 388 struct cpdma_chan *txch, *rxch; 389 struct cpsw_ale *ale; 390 /* snapshot of IRQ numbers */ 391 u32 irqs_table[4]; 392 u32 num_irqs; 393 bool irq_enabled; 394 struct cpts *cpts; 395 u32 emac_port; 396 }; 397 398 struct cpsw_stats { 399 char stat_string[ETH_GSTRING_LEN]; 400 int type; 401 int sizeof_stat; 402 int stat_offset; 403 }; 404 405 enum { 406 CPSW_STATS, 407 CPDMA_RX_STATS, 408 CPDMA_TX_STATS, 409 }; 410 411 #define CPSW_STAT(m) CPSW_STATS, \ 412 sizeof(((struct cpsw_hw_stats *)0)->m), \ 413 offsetof(struct cpsw_hw_stats, m) 414 #define CPDMA_RX_STAT(m) CPDMA_RX_STATS, \ 415 sizeof(((struct cpdma_chan_stats *)0)->m), \ 416 offsetof(struct cpdma_chan_stats, m) 417 #define CPDMA_TX_STAT(m) CPDMA_TX_STATS, \ 418 sizeof(((struct cpdma_chan_stats *)0)->m), \ 419 offsetof(struct cpdma_chan_stats, m) 420 421 static const struct cpsw_stats cpsw_gstrings_stats[] = { 422 { "Good Rx Frames", CPSW_STAT(rxgoodframes) }, 423 { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) }, 424 { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) }, 425 { "Pause Rx Frames", CPSW_STAT(rxpauseframes) }, 426 { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) }, 427 { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) }, 428 { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) }, 429 { "Rx Jabbers", CPSW_STAT(rxjabberframes) }, 430 { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) }, 431 { "Rx Fragments", CPSW_STAT(rxfragments) }, 432 { "Rx Octets", CPSW_STAT(rxoctets) }, 433 { "Good Tx Frames", CPSW_STAT(txgoodframes) }, 434 { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) }, 435 { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) }, 436 { "Pause Tx Frames", CPSW_STAT(txpauseframes) }, 437 { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) }, 438 { "Collisions", CPSW_STAT(txcollisionframes) }, 439 { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) }, 440 { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) }, 441 { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) }, 442 { "Late Collisions", CPSW_STAT(txlatecollisions) }, 443 { "Tx Underrun", CPSW_STAT(txunderrun) }, 444 { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) }, 445 { "Tx Octets", CPSW_STAT(txoctets) }, 446 { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) }, 447 { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) }, 448 { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) }, 449 { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) }, 450 { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) }, 451 { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) }, 452 { "Net Octets", CPSW_STAT(netoctets) }, 453 { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) }, 454 { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) }, 455 { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) }, 456 { "Rx DMA chan: head_enqueue", CPDMA_RX_STAT(head_enqueue) }, 457 { "Rx DMA chan: tail_enqueue", CPDMA_RX_STAT(tail_enqueue) }, 458 { "Rx DMA chan: pad_enqueue", CPDMA_RX_STAT(pad_enqueue) }, 459 { "Rx DMA chan: misqueued", CPDMA_RX_STAT(misqueued) }, 460 { "Rx DMA chan: desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) }, 461 { "Rx DMA chan: pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) }, 462 { "Rx DMA chan: runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) }, 463 { "Rx DMA chan: runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) }, 464 { "Rx DMA chan: empty_dequeue", CPDMA_RX_STAT(empty_dequeue) }, 465 { "Rx DMA chan: busy_dequeue", CPDMA_RX_STAT(busy_dequeue) }, 466 { "Rx DMA chan: good_dequeue", CPDMA_RX_STAT(good_dequeue) }, 467 { "Rx DMA chan: requeue", CPDMA_RX_STAT(requeue) }, 468 { "Rx DMA chan: teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) }, 469 { "Tx DMA chan: head_enqueue", CPDMA_TX_STAT(head_enqueue) }, 470 { "Tx DMA chan: tail_enqueue", CPDMA_TX_STAT(tail_enqueue) }, 471 { "Tx DMA chan: pad_enqueue", CPDMA_TX_STAT(pad_enqueue) }, 472 { "Tx DMA chan: misqueued", CPDMA_TX_STAT(misqueued) }, 473 { "Tx DMA chan: desc_alloc_fail", CPDMA_TX_STAT(desc_alloc_fail) }, 474 { "Tx DMA chan: pad_alloc_fail", CPDMA_TX_STAT(pad_alloc_fail) }, 475 { "Tx DMA chan: runt_receive_buf", CPDMA_TX_STAT(runt_receive_buff) }, 476 { "Tx DMA chan: runt_transmit_buf", CPDMA_TX_STAT(runt_transmit_buff) }, 477 { "Tx DMA chan: empty_dequeue", CPDMA_TX_STAT(empty_dequeue) }, 478 { "Tx DMA chan: busy_dequeue", CPDMA_TX_STAT(busy_dequeue) }, 479 { "Tx DMA chan: good_dequeue", CPDMA_TX_STAT(good_dequeue) }, 480 { "Tx DMA chan: requeue", CPDMA_TX_STAT(requeue) }, 481 { "Tx DMA chan: teardown_dequeue", CPDMA_TX_STAT(teardown_dequeue) }, 482 }; 483 484 #define CPSW_STATS_LEN ARRAY_SIZE(cpsw_gstrings_stats) 485 486 #define napi_to_priv(napi) container_of(napi, struct cpsw_priv, napi) 487 #define for_each_slave(priv, func, arg...) \ 488 do { \ 489 struct cpsw_slave *slave; \ 490 int n; \ 491 if (priv->data.dual_emac) \ 492 (func)((priv)->slaves + priv->emac_port, ##arg);\ 493 else \ 494 for (n = (priv)->data.slaves, \ 495 slave = (priv)->slaves; \ 496 n; n--) \ 497 (func)(slave++, ##arg); \ 498 } while (0) 499 #define cpsw_get_slave_ndev(priv, __slave_no__) \ 500 (priv->slaves[__slave_no__].ndev) 501 #define cpsw_get_slave_priv(priv, __slave_no__) \ 502 ((priv->slaves[__slave_no__].ndev) ? \ 503 netdev_priv(priv->slaves[__slave_no__].ndev) : NULL) \ 504 505 #define cpsw_dual_emac_src_port_detect(status, priv, ndev, skb) \ 506 do { \ 507 if (!priv->data.dual_emac) \ 508 break; \ 509 if (CPDMA_RX_SOURCE_PORT(status) == 1) { \ 510 ndev = cpsw_get_slave_ndev(priv, 0); \ 511 priv = netdev_priv(ndev); \ 512 skb->dev = ndev; \ 513 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) { \ 514 ndev = cpsw_get_slave_ndev(priv, 1); \ 515 priv = netdev_priv(ndev); \ 516 skb->dev = ndev; \ 517 } \ 518 } while (0) 519 #define cpsw_add_mcast(priv, addr) \ 520 do { \ 521 if (priv->data.dual_emac) { \ 522 struct cpsw_slave *slave = priv->slaves + \ 523 priv->emac_port; \ 524 int slave_port = cpsw_get_slave_port(priv, \ 525 slave->slave_num); \ 526 cpsw_ale_add_mcast(priv->ale, addr, \ 527 1 << slave_port | 1 << priv->host_port, \ 528 ALE_VLAN, slave->port_vlan, 0); \ 529 } else { \ 530 cpsw_ale_add_mcast(priv->ale, addr, \ 531 ALE_ALL_PORTS << priv->host_port, \ 532 0, 0, 0); \ 533 } \ 534 } while (0) 535 536 static inline int cpsw_get_slave_port(struct cpsw_priv *priv, u32 slave_num) 537 { 538 if (priv->host_port == 0) 539 return slave_num + 1; 540 else 541 return slave_num; 542 } 543 544 static void cpsw_ndo_set_rx_mode(struct net_device *ndev) 545 { 546 struct cpsw_priv *priv = netdev_priv(ndev); 547 548 if (ndev->flags & IFF_PROMISC) { 549 /* Enable promiscuous mode */ 550 dev_err(priv->dev, "Ignoring Promiscuous mode\n"); 551 return; 552 } 553 554 /* Clear all mcast from ALE */ 555 cpsw_ale_flush_multicast(priv->ale, ALE_ALL_PORTS << priv->host_port); 556 557 if (!netdev_mc_empty(ndev)) { 558 struct netdev_hw_addr *ha; 559 560 /* program multicast address list into ALE register */ 561 netdev_for_each_mc_addr(ha, ndev) { 562 cpsw_add_mcast(priv, (u8 *)ha->addr); 563 } 564 } 565 } 566 567 static void cpsw_intr_enable(struct cpsw_priv *priv) 568 { 569 __raw_writel(0xFF, &priv->wr_regs->tx_en); 570 __raw_writel(0xFF, &priv->wr_regs->rx_en); 571 572 cpdma_ctlr_int_ctrl(priv->dma, true); 573 return; 574 } 575 576 static void cpsw_intr_disable(struct cpsw_priv *priv) 577 { 578 __raw_writel(0, &priv->wr_regs->tx_en); 579 __raw_writel(0, &priv->wr_regs->rx_en); 580 581 cpdma_ctlr_int_ctrl(priv->dma, false); 582 return; 583 } 584 585 void cpsw_tx_handler(void *token, int len, int status) 586 { 587 struct sk_buff *skb = token; 588 struct net_device *ndev = skb->dev; 589 struct cpsw_priv *priv = netdev_priv(ndev); 590 591 /* Check whether the queue is stopped due to stalled tx dma, if the 592 * queue is stopped then start the queue as we have free desc for tx 593 */ 594 if (unlikely(netif_queue_stopped(ndev))) 595 netif_wake_queue(ndev); 596 cpts_tx_timestamp(priv->cpts, skb); 597 priv->stats.tx_packets++; 598 priv->stats.tx_bytes += len; 599 dev_kfree_skb_any(skb); 600 } 601 602 void cpsw_rx_handler(void *token, int len, int status) 603 { 604 struct sk_buff *skb = token; 605 struct sk_buff *new_skb; 606 struct net_device *ndev = skb->dev; 607 struct cpsw_priv *priv = netdev_priv(ndev); 608 int ret = 0; 609 610 cpsw_dual_emac_src_port_detect(status, priv, ndev, skb); 611 612 if (unlikely(status < 0)) { 613 /* the interface is going down, skbs are purged */ 614 dev_kfree_skb_any(skb); 615 return; 616 } 617 618 new_skb = netdev_alloc_skb_ip_align(ndev, priv->rx_packet_max); 619 if (new_skb) { 620 skb_put(skb, len); 621 cpts_rx_timestamp(priv->cpts, skb); 622 skb->protocol = eth_type_trans(skb, ndev); 623 netif_receive_skb(skb); 624 priv->stats.rx_bytes += len; 625 priv->stats.rx_packets++; 626 } else { 627 priv->stats.rx_dropped++; 628 new_skb = skb; 629 } 630 631 ret = cpdma_chan_submit(priv->rxch, new_skb, new_skb->data, 632 skb_tailroom(new_skb), 0); 633 if (WARN_ON(ret < 0)) 634 dev_kfree_skb_any(new_skb); 635 } 636 637 static irqreturn_t cpsw_interrupt(int irq, void *dev_id) 638 { 639 struct cpsw_priv *priv = dev_id; 640 641 cpsw_intr_disable(priv); 642 if (priv->irq_enabled == true) { 643 cpsw_disable_irq(priv); 644 priv->irq_enabled = false; 645 } 646 647 if (netif_running(priv->ndev)) { 648 napi_schedule(&priv->napi); 649 return IRQ_HANDLED; 650 } 651 652 priv = cpsw_get_slave_priv(priv, 1); 653 if (!priv) 654 return IRQ_NONE; 655 656 if (netif_running(priv->ndev)) { 657 napi_schedule(&priv->napi); 658 return IRQ_HANDLED; 659 } 660 return IRQ_NONE; 661 } 662 663 static int cpsw_poll(struct napi_struct *napi, int budget) 664 { 665 struct cpsw_priv *priv = napi_to_priv(napi); 666 int num_tx, num_rx; 667 668 num_tx = cpdma_chan_process(priv->txch, 128); 669 if (num_tx) 670 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 671 672 num_rx = cpdma_chan_process(priv->rxch, budget); 673 if (num_rx < budget) { 674 struct cpsw_priv *prim_cpsw; 675 676 napi_complete(napi); 677 cpsw_intr_enable(priv); 678 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 679 prim_cpsw = cpsw_get_slave_priv(priv, 0); 680 if (prim_cpsw->irq_enabled == false) { 681 prim_cpsw->irq_enabled = true; 682 cpsw_enable_irq(priv); 683 } 684 } 685 686 if (num_rx || num_tx) 687 cpsw_dbg(priv, intr, "poll %d rx, %d tx pkts\n", 688 num_rx, num_tx); 689 690 return num_rx; 691 } 692 693 static inline void soft_reset(const char *module, void __iomem *reg) 694 { 695 unsigned long timeout = jiffies + HZ; 696 697 __raw_writel(1, reg); 698 do { 699 cpu_relax(); 700 } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies)); 701 702 WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module); 703 } 704 705 #define mac_hi(mac) (((mac)[0] << 0) | ((mac)[1] << 8) | \ 706 ((mac)[2] << 16) | ((mac)[3] << 24)) 707 #define mac_lo(mac) (((mac)[4] << 0) | ((mac)[5] << 8)) 708 709 static void cpsw_set_slave_mac(struct cpsw_slave *slave, 710 struct cpsw_priv *priv) 711 { 712 slave_write(slave, mac_hi(priv->mac_addr), SA_HI); 713 slave_write(slave, mac_lo(priv->mac_addr), SA_LO); 714 } 715 716 static void _cpsw_adjust_link(struct cpsw_slave *slave, 717 struct cpsw_priv *priv, bool *link) 718 { 719 struct phy_device *phy = slave->phy; 720 u32 mac_control = 0; 721 u32 slave_port; 722 723 if (!phy) 724 return; 725 726 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 727 728 if (phy->link) { 729 mac_control = priv->data.mac_control; 730 731 /* enable forwarding */ 732 cpsw_ale_control_set(priv->ale, slave_port, 733 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 734 735 if (phy->speed == 1000) 736 mac_control |= BIT(7); /* GIGABITEN */ 737 if (phy->duplex) 738 mac_control |= BIT(0); /* FULLDUPLEXEN */ 739 740 /* set speed_in input in case RMII mode is used in 100Mbps */ 741 if (phy->speed == 100) 742 mac_control |= BIT(15); 743 744 *link = true; 745 } else { 746 mac_control = 0; 747 /* disable forwarding */ 748 cpsw_ale_control_set(priv->ale, slave_port, 749 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 750 } 751 752 if (mac_control != slave->mac_control) { 753 phy_print_status(phy); 754 __raw_writel(mac_control, &slave->sliver->mac_control); 755 } 756 757 slave->mac_control = mac_control; 758 } 759 760 static void cpsw_adjust_link(struct net_device *ndev) 761 { 762 struct cpsw_priv *priv = netdev_priv(ndev); 763 bool link = false; 764 765 for_each_slave(priv, _cpsw_adjust_link, priv, &link); 766 767 if (link) { 768 netif_carrier_on(ndev); 769 if (netif_running(ndev)) 770 netif_wake_queue(ndev); 771 } else { 772 netif_carrier_off(ndev); 773 netif_stop_queue(ndev); 774 } 775 } 776 777 static int cpsw_get_coalesce(struct net_device *ndev, 778 struct ethtool_coalesce *coal) 779 { 780 struct cpsw_priv *priv = netdev_priv(ndev); 781 782 coal->rx_coalesce_usecs = priv->coal_intvl; 783 return 0; 784 } 785 786 static int cpsw_set_coalesce(struct net_device *ndev, 787 struct ethtool_coalesce *coal) 788 { 789 struct cpsw_priv *priv = netdev_priv(ndev); 790 u32 int_ctrl; 791 u32 num_interrupts = 0; 792 u32 prescale = 0; 793 u32 addnl_dvdr = 1; 794 u32 coal_intvl = 0; 795 796 if (!coal->rx_coalesce_usecs) 797 return -EINVAL; 798 799 coal_intvl = coal->rx_coalesce_usecs; 800 801 int_ctrl = readl(&priv->wr_regs->int_control); 802 prescale = priv->bus_freq_mhz * 4; 803 804 if (coal_intvl < CPSW_CMINTMIN_INTVL) 805 coal_intvl = CPSW_CMINTMIN_INTVL; 806 807 if (coal_intvl > CPSW_CMINTMAX_INTVL) { 808 /* Interrupt pacer works with 4us Pulse, we can 809 * throttle further by dilating the 4us pulse. 810 */ 811 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale; 812 813 if (addnl_dvdr > 1) { 814 prescale *= addnl_dvdr; 815 if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr)) 816 coal_intvl = (CPSW_CMINTMAX_INTVL 817 * addnl_dvdr); 818 } else { 819 addnl_dvdr = 1; 820 coal_intvl = CPSW_CMINTMAX_INTVL; 821 } 822 } 823 824 num_interrupts = (1000 * addnl_dvdr) / coal_intvl; 825 writel(num_interrupts, &priv->wr_regs->rx_imax); 826 writel(num_interrupts, &priv->wr_regs->tx_imax); 827 828 int_ctrl |= CPSW_INTPACEEN; 829 int_ctrl &= (~CPSW_INTPRESCALE_MASK); 830 int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK); 831 writel(int_ctrl, &priv->wr_regs->int_control); 832 833 cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl); 834 if (priv->data.dual_emac) { 835 int i; 836 837 for (i = 0; i < priv->data.slaves; i++) { 838 priv = netdev_priv(priv->slaves[i].ndev); 839 priv->coal_intvl = coal_intvl; 840 } 841 } else { 842 priv->coal_intvl = coal_intvl; 843 } 844 845 return 0; 846 } 847 848 static int cpsw_get_sset_count(struct net_device *ndev, int sset) 849 { 850 switch (sset) { 851 case ETH_SS_STATS: 852 return CPSW_STATS_LEN; 853 default: 854 return -EOPNOTSUPP; 855 } 856 } 857 858 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data) 859 { 860 u8 *p = data; 861 int i; 862 863 switch (stringset) { 864 case ETH_SS_STATS: 865 for (i = 0; i < CPSW_STATS_LEN; i++) { 866 memcpy(p, cpsw_gstrings_stats[i].stat_string, 867 ETH_GSTRING_LEN); 868 p += ETH_GSTRING_LEN; 869 } 870 break; 871 } 872 } 873 874 static void cpsw_get_ethtool_stats(struct net_device *ndev, 875 struct ethtool_stats *stats, u64 *data) 876 { 877 struct cpsw_priv *priv = netdev_priv(ndev); 878 struct cpdma_chan_stats rx_stats; 879 struct cpdma_chan_stats tx_stats; 880 u32 val; 881 u8 *p; 882 int i; 883 884 /* Collect Davinci CPDMA stats for Rx and Tx Channel */ 885 cpdma_chan_get_stats(priv->rxch, &rx_stats); 886 cpdma_chan_get_stats(priv->txch, &tx_stats); 887 888 for (i = 0; i < CPSW_STATS_LEN; i++) { 889 switch (cpsw_gstrings_stats[i].type) { 890 case CPSW_STATS: 891 val = readl(priv->hw_stats + 892 cpsw_gstrings_stats[i].stat_offset); 893 data[i] = val; 894 break; 895 896 case CPDMA_RX_STATS: 897 p = (u8 *)&rx_stats + 898 cpsw_gstrings_stats[i].stat_offset; 899 data[i] = *(u32 *)p; 900 break; 901 902 case CPDMA_TX_STATS: 903 p = (u8 *)&tx_stats + 904 cpsw_gstrings_stats[i].stat_offset; 905 data[i] = *(u32 *)p; 906 break; 907 } 908 } 909 } 910 911 static inline int __show_stat(char *buf, int maxlen, const char *name, u32 val) 912 { 913 static char *leader = "........................................"; 914 915 if (!val) 916 return 0; 917 else 918 return snprintf(buf, maxlen, "%s %s %10d\n", name, 919 leader + strlen(name), val); 920 } 921 922 static int cpsw_common_res_usage_state(struct cpsw_priv *priv) 923 { 924 u32 i; 925 u32 usage_count = 0; 926 927 if (!priv->data.dual_emac) 928 return 0; 929 930 for (i = 0; i < priv->data.slaves; i++) 931 if (priv->slaves[i].open_stat) 932 usage_count++; 933 934 return usage_count; 935 } 936 937 static inline int cpsw_tx_packet_submit(struct net_device *ndev, 938 struct cpsw_priv *priv, struct sk_buff *skb) 939 { 940 if (!priv->data.dual_emac) 941 return cpdma_chan_submit(priv->txch, skb, skb->data, 942 skb->len, 0); 943 944 if (ndev == cpsw_get_slave_ndev(priv, 0)) 945 return cpdma_chan_submit(priv->txch, skb, skb->data, 946 skb->len, 1); 947 else 948 return cpdma_chan_submit(priv->txch, skb, skb->data, 949 skb->len, 2); 950 } 951 952 static inline void cpsw_add_dual_emac_def_ale_entries( 953 struct cpsw_priv *priv, struct cpsw_slave *slave, 954 u32 slave_port) 955 { 956 u32 port_mask = 1 << slave_port | 1 << priv->host_port; 957 958 if (priv->version == CPSW_VERSION_1) 959 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN); 960 else 961 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN); 962 cpsw_ale_add_vlan(priv->ale, slave->port_vlan, port_mask, 963 port_mask, port_mask, 0); 964 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 965 port_mask, ALE_VLAN, slave->port_vlan, 0); 966 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 967 priv->host_port, ALE_VLAN, slave->port_vlan); 968 } 969 970 static void soft_reset_slave(struct cpsw_slave *slave) 971 { 972 char name[32]; 973 974 snprintf(name, sizeof(name), "slave-%d", slave->slave_num); 975 soft_reset(name, &slave->sliver->soft_reset); 976 } 977 978 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv) 979 { 980 u32 slave_port; 981 982 soft_reset_slave(slave); 983 984 /* setup priority mapping */ 985 __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map); 986 987 switch (priv->version) { 988 case CPSW_VERSION_1: 989 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP); 990 break; 991 case CPSW_VERSION_2: 992 case CPSW_VERSION_3: 993 case CPSW_VERSION_4: 994 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP); 995 break; 996 } 997 998 /* setup max packet size, and mac address */ 999 __raw_writel(priv->rx_packet_max, &slave->sliver->rx_maxlen); 1000 cpsw_set_slave_mac(slave, priv); 1001 1002 slave->mac_control = 0; /* no link yet */ 1003 1004 slave_port = cpsw_get_slave_port(priv, slave->slave_num); 1005 1006 if (priv->data.dual_emac) 1007 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port); 1008 else 1009 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1010 1 << slave_port, 0, 0, ALE_MCAST_FWD_2); 1011 1012 slave->phy = phy_connect(priv->ndev, slave->data->phy_id, 1013 &cpsw_adjust_link, slave->data->phy_if); 1014 if (IS_ERR(slave->phy)) { 1015 dev_err(priv->dev, "phy %s not found on slave %d\n", 1016 slave->data->phy_id, slave->slave_num); 1017 slave->phy = NULL; 1018 } else { 1019 dev_info(priv->dev, "phy found : id is : 0x%x\n", 1020 slave->phy->phy_id); 1021 phy_start(slave->phy); 1022 1023 /* Configure GMII_SEL register */ 1024 cpsw_phy_sel(&priv->pdev->dev, slave->phy->interface, 1025 slave->slave_num); 1026 } 1027 } 1028 1029 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv) 1030 { 1031 const int vlan = priv->data.default_vlan; 1032 const int port = priv->host_port; 1033 u32 reg; 1034 int i; 1035 1036 reg = (priv->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN : 1037 CPSW2_PORT_VLAN; 1038 1039 writel(vlan, &priv->host_port_regs->port_vlan); 1040 1041 for (i = 0; i < priv->data.slaves; i++) 1042 slave_write(priv->slaves + i, vlan, reg); 1043 1044 cpsw_ale_add_vlan(priv->ale, vlan, ALE_ALL_PORTS << port, 1045 ALE_ALL_PORTS << port, ALE_ALL_PORTS << port, 1046 (ALE_PORT_1 | ALE_PORT_2) << port); 1047 } 1048 1049 static void cpsw_init_host_port(struct cpsw_priv *priv) 1050 { 1051 u32 control_reg; 1052 u32 fifo_mode; 1053 1054 /* soft reset the controller and initialize ale */ 1055 soft_reset("cpsw", &priv->regs->soft_reset); 1056 cpsw_ale_start(priv->ale); 1057 1058 /* switch to vlan unaware mode */ 1059 cpsw_ale_control_set(priv->ale, priv->host_port, ALE_VLAN_AWARE, 1060 CPSW_ALE_VLAN_AWARE); 1061 control_reg = readl(&priv->regs->control); 1062 control_reg |= CPSW_VLAN_AWARE; 1063 writel(control_reg, &priv->regs->control); 1064 fifo_mode = (priv->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE : 1065 CPSW_FIFO_NORMAL_MODE; 1066 writel(fifo_mode, &priv->host_port_regs->tx_in_ctl); 1067 1068 /* setup host port priority mapping */ 1069 __raw_writel(CPDMA_TX_PRIORITY_MAP, 1070 &priv->host_port_regs->cpdma_tx_pri_map); 1071 __raw_writel(0, &priv->host_port_regs->cpdma_rx_chan_map); 1072 1073 cpsw_ale_control_set(priv->ale, priv->host_port, 1074 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1075 1076 if (!priv->data.dual_emac) { 1077 cpsw_ale_add_ucast(priv->ale, priv->mac_addr, priv->host_port, 1078 0, 0); 1079 cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1080 1 << priv->host_port, 0, 0, ALE_MCAST_FWD_2); 1081 } 1082 } 1083 1084 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_priv *priv) 1085 { 1086 if (!slave->phy) 1087 return; 1088 phy_stop(slave->phy); 1089 phy_disconnect(slave->phy); 1090 slave->phy = NULL; 1091 } 1092 1093 static int cpsw_ndo_open(struct net_device *ndev) 1094 { 1095 struct cpsw_priv *priv = netdev_priv(ndev); 1096 struct cpsw_priv *prim_cpsw; 1097 int i, ret; 1098 u32 reg; 1099 1100 if (!cpsw_common_res_usage_state(priv)) 1101 cpsw_intr_disable(priv); 1102 netif_carrier_off(ndev); 1103 1104 pm_runtime_get_sync(&priv->pdev->dev); 1105 1106 reg = priv->version; 1107 1108 dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n", 1109 CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg), 1110 CPSW_RTL_VERSION(reg)); 1111 1112 /* initialize host and slave ports */ 1113 if (!cpsw_common_res_usage_state(priv)) 1114 cpsw_init_host_port(priv); 1115 for_each_slave(priv, cpsw_slave_open, priv); 1116 1117 /* Add default VLAN */ 1118 if (!priv->data.dual_emac) 1119 cpsw_add_default_vlan(priv); 1120 1121 if (!cpsw_common_res_usage_state(priv)) { 1122 /* setup tx dma to fixed prio and zero offset */ 1123 cpdma_control_set(priv->dma, CPDMA_TX_PRIO_FIXED, 1); 1124 cpdma_control_set(priv->dma, CPDMA_RX_BUFFER_OFFSET, 0); 1125 1126 /* disable priority elevation */ 1127 __raw_writel(0, &priv->regs->ptype); 1128 1129 /* enable statistics collection only on all ports */ 1130 __raw_writel(0x7, &priv->regs->stat_port_en); 1131 1132 if (WARN_ON(!priv->data.rx_descs)) 1133 priv->data.rx_descs = 128; 1134 1135 for (i = 0; i < priv->data.rx_descs; i++) { 1136 struct sk_buff *skb; 1137 1138 ret = -ENOMEM; 1139 skb = __netdev_alloc_skb_ip_align(priv->ndev, 1140 priv->rx_packet_max, GFP_KERNEL); 1141 if (!skb) 1142 goto err_cleanup; 1143 ret = cpdma_chan_submit(priv->rxch, skb, skb->data, 1144 skb_tailroom(skb), 0); 1145 if (ret < 0) { 1146 kfree_skb(skb); 1147 goto err_cleanup; 1148 } 1149 } 1150 /* continue even if we didn't manage to submit all 1151 * receive descs 1152 */ 1153 cpsw_info(priv, ifup, "submitted %d rx descriptors\n", i); 1154 1155 if (cpts_register(&priv->pdev->dev, priv->cpts, 1156 priv->data.cpts_clock_mult, 1157 priv->data.cpts_clock_shift)) 1158 dev_err(priv->dev, "error registering cpts device\n"); 1159 1160 } 1161 1162 /* Enable Interrupt pacing if configured */ 1163 if (priv->coal_intvl != 0) { 1164 struct ethtool_coalesce coal; 1165 1166 coal.rx_coalesce_usecs = (priv->coal_intvl << 4); 1167 cpsw_set_coalesce(ndev, &coal); 1168 } 1169 1170 prim_cpsw = cpsw_get_slave_priv(priv, 0); 1171 if (prim_cpsw->irq_enabled == false) { 1172 if ((priv == prim_cpsw) || !netif_running(prim_cpsw->ndev)) { 1173 prim_cpsw->irq_enabled = true; 1174 cpsw_enable_irq(prim_cpsw); 1175 } 1176 } 1177 1178 napi_enable(&priv->napi); 1179 cpdma_ctlr_start(priv->dma); 1180 cpsw_intr_enable(priv); 1181 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1182 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1183 1184 if (priv->data.dual_emac) 1185 priv->slaves[priv->emac_port].open_stat = true; 1186 return 0; 1187 1188 err_cleanup: 1189 cpdma_ctlr_stop(priv->dma); 1190 for_each_slave(priv, cpsw_slave_stop, priv); 1191 pm_runtime_put_sync(&priv->pdev->dev); 1192 netif_carrier_off(priv->ndev); 1193 return ret; 1194 } 1195 1196 static int cpsw_ndo_stop(struct net_device *ndev) 1197 { 1198 struct cpsw_priv *priv = netdev_priv(ndev); 1199 1200 cpsw_info(priv, ifdown, "shutting down cpsw device\n"); 1201 netif_stop_queue(priv->ndev); 1202 napi_disable(&priv->napi); 1203 netif_carrier_off(priv->ndev); 1204 1205 if (cpsw_common_res_usage_state(priv) <= 1) { 1206 cpts_unregister(priv->cpts); 1207 cpsw_intr_disable(priv); 1208 cpdma_ctlr_int_ctrl(priv->dma, false); 1209 cpdma_ctlr_stop(priv->dma); 1210 cpsw_ale_stop(priv->ale); 1211 } 1212 for_each_slave(priv, cpsw_slave_stop, priv); 1213 pm_runtime_put_sync(&priv->pdev->dev); 1214 if (priv->data.dual_emac) 1215 priv->slaves[priv->emac_port].open_stat = false; 1216 return 0; 1217 } 1218 1219 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb, 1220 struct net_device *ndev) 1221 { 1222 struct cpsw_priv *priv = netdev_priv(ndev); 1223 int ret; 1224 1225 ndev->trans_start = jiffies; 1226 1227 if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) { 1228 cpsw_err(priv, tx_err, "packet pad failed\n"); 1229 priv->stats.tx_dropped++; 1230 return NETDEV_TX_OK; 1231 } 1232 1233 if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP && 1234 priv->cpts->tx_enable) 1235 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 1236 1237 skb_tx_timestamp(skb); 1238 1239 ret = cpsw_tx_packet_submit(ndev, priv, skb); 1240 if (unlikely(ret != 0)) { 1241 cpsw_err(priv, tx_err, "desc submit failed\n"); 1242 goto fail; 1243 } 1244 1245 /* If there is no more tx desc left free then we need to 1246 * tell the kernel to stop sending us tx frames. 1247 */ 1248 if (unlikely(!cpdma_check_free_tx_desc(priv->txch))) 1249 netif_stop_queue(ndev); 1250 1251 return NETDEV_TX_OK; 1252 fail: 1253 priv->stats.tx_dropped++; 1254 netif_stop_queue(ndev); 1255 return NETDEV_TX_BUSY; 1256 } 1257 1258 static void cpsw_ndo_change_rx_flags(struct net_device *ndev, int flags) 1259 { 1260 /* 1261 * The switch cannot operate in promiscuous mode without substantial 1262 * headache. For promiscuous mode to work, we would need to put the 1263 * ALE in bypass mode and route all traffic to the host port. 1264 * Subsequently, the host will need to operate as a "bridge", learn, 1265 * and flood as needed. For now, we simply complain here and 1266 * do nothing about it :-) 1267 */ 1268 if ((flags & IFF_PROMISC) && (ndev->flags & IFF_PROMISC)) 1269 dev_err(&ndev->dev, "promiscuity ignored!\n"); 1270 1271 /* 1272 * The switch cannot filter multicast traffic unless it is configured 1273 * in "VLAN Aware" mode. Unfortunately, VLAN awareness requires a 1274 * whole bunch of additional logic that this driver does not implement 1275 * at present. 1276 */ 1277 if ((flags & IFF_ALLMULTI) && !(ndev->flags & IFF_ALLMULTI)) 1278 dev_err(&ndev->dev, "multicast traffic cannot be filtered!\n"); 1279 } 1280 1281 #ifdef CONFIG_TI_CPTS 1282 1283 static void cpsw_hwtstamp_v1(struct cpsw_priv *priv) 1284 { 1285 struct cpsw_slave *slave = &priv->slaves[priv->data.active_slave]; 1286 u32 ts_en, seq_id; 1287 1288 if (!priv->cpts->tx_enable && !priv->cpts->rx_enable) { 1289 slave_write(slave, 0, CPSW1_TS_CTL); 1290 return; 1291 } 1292 1293 seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588; 1294 ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS; 1295 1296 if (priv->cpts->tx_enable) 1297 ts_en |= CPSW_V1_TS_TX_EN; 1298 1299 if (priv->cpts->rx_enable) 1300 ts_en |= CPSW_V1_TS_RX_EN; 1301 1302 slave_write(slave, ts_en, CPSW1_TS_CTL); 1303 slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE); 1304 } 1305 1306 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv) 1307 { 1308 struct cpsw_slave *slave; 1309 u32 ctrl, mtype; 1310 1311 if (priv->data.dual_emac) 1312 slave = &priv->slaves[priv->emac_port]; 1313 else 1314 slave = &priv->slaves[priv->data.active_slave]; 1315 1316 ctrl = slave_read(slave, CPSW2_CONTROL); 1317 ctrl &= ~CTRL_ALL_TS_MASK; 1318 1319 if (priv->cpts->tx_enable) 1320 ctrl |= CTRL_TX_TS_BITS; 1321 1322 if (priv->cpts->rx_enable) 1323 ctrl |= CTRL_RX_TS_BITS; 1324 1325 mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS; 1326 1327 slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE); 1328 slave_write(slave, ctrl, CPSW2_CONTROL); 1329 __raw_writel(ETH_P_1588, &priv->regs->ts_ltype); 1330 } 1331 1332 static int cpsw_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 1333 { 1334 struct cpsw_priv *priv = netdev_priv(dev); 1335 struct cpts *cpts = priv->cpts; 1336 struct hwtstamp_config cfg; 1337 1338 if (priv->version != CPSW_VERSION_1 && 1339 priv->version != CPSW_VERSION_2) 1340 return -EOPNOTSUPP; 1341 1342 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1343 return -EFAULT; 1344 1345 /* reserved for future extensions */ 1346 if (cfg.flags) 1347 return -EINVAL; 1348 1349 if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON) 1350 return -ERANGE; 1351 1352 switch (cfg.rx_filter) { 1353 case HWTSTAMP_FILTER_NONE: 1354 cpts->rx_enable = 0; 1355 break; 1356 case HWTSTAMP_FILTER_ALL: 1357 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1358 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1359 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1360 return -ERANGE; 1361 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1362 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1363 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1364 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1365 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1366 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1367 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1368 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1369 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1370 cpts->rx_enable = 1; 1371 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1372 break; 1373 default: 1374 return -ERANGE; 1375 } 1376 1377 cpts->tx_enable = cfg.tx_type == HWTSTAMP_TX_ON; 1378 1379 switch (priv->version) { 1380 case CPSW_VERSION_1: 1381 cpsw_hwtstamp_v1(priv); 1382 break; 1383 case CPSW_VERSION_2: 1384 cpsw_hwtstamp_v2(priv); 1385 break; 1386 default: 1387 WARN_ON(1); 1388 } 1389 1390 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1391 } 1392 1393 #endif /*CONFIG_TI_CPTS*/ 1394 1395 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd) 1396 { 1397 struct cpsw_priv *priv = netdev_priv(dev); 1398 struct mii_ioctl_data *data = if_mii(req); 1399 int slave_no = cpsw_slave_index(priv); 1400 1401 if (!netif_running(dev)) 1402 return -EINVAL; 1403 1404 switch (cmd) { 1405 #ifdef CONFIG_TI_CPTS 1406 case SIOCSHWTSTAMP: 1407 return cpsw_hwtstamp_ioctl(dev, req); 1408 #endif 1409 case SIOCGMIIPHY: 1410 data->phy_id = priv->slaves[slave_no].phy->addr; 1411 break; 1412 default: 1413 return -ENOTSUPP; 1414 } 1415 1416 return 0; 1417 } 1418 1419 static void cpsw_ndo_tx_timeout(struct net_device *ndev) 1420 { 1421 struct cpsw_priv *priv = netdev_priv(ndev); 1422 1423 cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n"); 1424 priv->stats.tx_errors++; 1425 cpsw_intr_disable(priv); 1426 cpdma_ctlr_int_ctrl(priv->dma, false); 1427 cpdma_chan_stop(priv->txch); 1428 cpdma_chan_start(priv->txch); 1429 cpdma_ctlr_int_ctrl(priv->dma, true); 1430 cpsw_intr_enable(priv); 1431 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1432 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1433 1434 } 1435 1436 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p) 1437 { 1438 struct cpsw_priv *priv = netdev_priv(ndev); 1439 struct sockaddr *addr = (struct sockaddr *)p; 1440 int flags = 0; 1441 u16 vid = 0; 1442 1443 if (!is_valid_ether_addr(addr->sa_data)) 1444 return -EADDRNOTAVAIL; 1445 1446 if (priv->data.dual_emac) { 1447 vid = priv->slaves[priv->emac_port].port_vlan; 1448 flags = ALE_VLAN; 1449 } 1450 1451 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, priv->host_port, 1452 flags, vid); 1453 cpsw_ale_add_ucast(priv->ale, addr->sa_data, priv->host_port, 1454 flags, vid); 1455 1456 memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN); 1457 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1458 for_each_slave(priv, cpsw_set_slave_mac, priv); 1459 1460 return 0; 1461 } 1462 1463 static struct net_device_stats *cpsw_ndo_get_stats(struct net_device *ndev) 1464 { 1465 struct cpsw_priv *priv = netdev_priv(ndev); 1466 return &priv->stats; 1467 } 1468 1469 #ifdef CONFIG_NET_POLL_CONTROLLER 1470 static void cpsw_ndo_poll_controller(struct net_device *ndev) 1471 { 1472 struct cpsw_priv *priv = netdev_priv(ndev); 1473 1474 cpsw_intr_disable(priv); 1475 cpdma_ctlr_int_ctrl(priv->dma, false); 1476 cpsw_interrupt(ndev->irq, priv); 1477 cpdma_ctlr_int_ctrl(priv->dma, true); 1478 cpsw_intr_enable(priv); 1479 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_RX); 1480 cpdma_ctlr_eoi(priv->dma, CPDMA_EOI_TX); 1481 1482 } 1483 #endif 1484 1485 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv, 1486 unsigned short vid) 1487 { 1488 int ret; 1489 1490 ret = cpsw_ale_add_vlan(priv->ale, vid, 1491 ALE_ALL_PORTS << priv->host_port, 1492 0, ALE_ALL_PORTS << priv->host_port, 1493 (ALE_PORT_1 | ALE_PORT_2) << priv->host_port); 1494 if (ret != 0) 1495 return ret; 1496 1497 ret = cpsw_ale_add_ucast(priv->ale, priv->mac_addr, 1498 priv->host_port, ALE_VLAN, vid); 1499 if (ret != 0) 1500 goto clean_vid; 1501 1502 ret = cpsw_ale_add_mcast(priv->ale, priv->ndev->broadcast, 1503 ALE_ALL_PORTS << priv->host_port, 1504 ALE_VLAN, vid, 0); 1505 if (ret != 0) 1506 goto clean_vlan_ucast; 1507 return 0; 1508 1509 clean_vlan_ucast: 1510 cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1511 priv->host_port, ALE_VLAN, vid); 1512 clean_vid: 1513 cpsw_ale_del_vlan(priv->ale, vid, 0); 1514 return ret; 1515 } 1516 1517 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev, 1518 __be16 proto, u16 vid) 1519 { 1520 struct cpsw_priv *priv = netdev_priv(ndev); 1521 1522 if (vid == priv->data.default_vlan) 1523 return 0; 1524 1525 dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid); 1526 return cpsw_add_vlan_ale_entry(priv, vid); 1527 } 1528 1529 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev, 1530 __be16 proto, u16 vid) 1531 { 1532 struct cpsw_priv *priv = netdev_priv(ndev); 1533 int ret; 1534 1535 if (vid == priv->data.default_vlan) 1536 return 0; 1537 1538 dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid); 1539 ret = cpsw_ale_del_vlan(priv->ale, vid, 0); 1540 if (ret != 0) 1541 return ret; 1542 1543 ret = cpsw_ale_del_ucast(priv->ale, priv->mac_addr, 1544 priv->host_port, ALE_VLAN, vid); 1545 if (ret != 0) 1546 return ret; 1547 1548 return cpsw_ale_del_mcast(priv->ale, priv->ndev->broadcast, 1549 0, ALE_VLAN, vid); 1550 } 1551 1552 static const struct net_device_ops cpsw_netdev_ops = { 1553 .ndo_open = cpsw_ndo_open, 1554 .ndo_stop = cpsw_ndo_stop, 1555 .ndo_start_xmit = cpsw_ndo_start_xmit, 1556 .ndo_change_rx_flags = cpsw_ndo_change_rx_flags, 1557 .ndo_set_mac_address = cpsw_ndo_set_mac_address, 1558 .ndo_do_ioctl = cpsw_ndo_ioctl, 1559 .ndo_validate_addr = eth_validate_addr, 1560 .ndo_change_mtu = eth_change_mtu, 1561 .ndo_tx_timeout = cpsw_ndo_tx_timeout, 1562 .ndo_get_stats = cpsw_ndo_get_stats, 1563 .ndo_set_rx_mode = cpsw_ndo_set_rx_mode, 1564 #ifdef CONFIG_NET_POLL_CONTROLLER 1565 .ndo_poll_controller = cpsw_ndo_poll_controller, 1566 #endif 1567 .ndo_vlan_rx_add_vid = cpsw_ndo_vlan_rx_add_vid, 1568 .ndo_vlan_rx_kill_vid = cpsw_ndo_vlan_rx_kill_vid, 1569 }; 1570 1571 static void cpsw_get_drvinfo(struct net_device *ndev, 1572 struct ethtool_drvinfo *info) 1573 { 1574 struct cpsw_priv *priv = netdev_priv(ndev); 1575 1576 strlcpy(info->driver, "TI CPSW Driver v1.0", sizeof(info->driver)); 1577 strlcpy(info->version, "1.0", sizeof(info->version)); 1578 strlcpy(info->bus_info, priv->pdev->name, sizeof(info->bus_info)); 1579 } 1580 1581 static u32 cpsw_get_msglevel(struct net_device *ndev) 1582 { 1583 struct cpsw_priv *priv = netdev_priv(ndev); 1584 return priv->msg_enable; 1585 } 1586 1587 static void cpsw_set_msglevel(struct net_device *ndev, u32 value) 1588 { 1589 struct cpsw_priv *priv = netdev_priv(ndev); 1590 priv->msg_enable = value; 1591 } 1592 1593 static int cpsw_get_ts_info(struct net_device *ndev, 1594 struct ethtool_ts_info *info) 1595 { 1596 #ifdef CONFIG_TI_CPTS 1597 struct cpsw_priv *priv = netdev_priv(ndev); 1598 1599 info->so_timestamping = 1600 SOF_TIMESTAMPING_TX_HARDWARE | 1601 SOF_TIMESTAMPING_TX_SOFTWARE | 1602 SOF_TIMESTAMPING_RX_HARDWARE | 1603 SOF_TIMESTAMPING_RX_SOFTWARE | 1604 SOF_TIMESTAMPING_SOFTWARE | 1605 SOF_TIMESTAMPING_RAW_HARDWARE; 1606 info->phc_index = priv->cpts->phc_index; 1607 info->tx_types = 1608 (1 << HWTSTAMP_TX_OFF) | 1609 (1 << HWTSTAMP_TX_ON); 1610 info->rx_filters = 1611 (1 << HWTSTAMP_FILTER_NONE) | 1612 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT); 1613 #else 1614 info->so_timestamping = 1615 SOF_TIMESTAMPING_TX_SOFTWARE | 1616 SOF_TIMESTAMPING_RX_SOFTWARE | 1617 SOF_TIMESTAMPING_SOFTWARE; 1618 info->phc_index = -1; 1619 info->tx_types = 0; 1620 info->rx_filters = 0; 1621 #endif 1622 return 0; 1623 } 1624 1625 static int cpsw_get_settings(struct net_device *ndev, 1626 struct ethtool_cmd *ecmd) 1627 { 1628 struct cpsw_priv *priv = netdev_priv(ndev); 1629 int slave_no = cpsw_slave_index(priv); 1630 1631 if (priv->slaves[slave_no].phy) 1632 return phy_ethtool_gset(priv->slaves[slave_no].phy, ecmd); 1633 else 1634 return -EOPNOTSUPP; 1635 } 1636 1637 static int cpsw_set_settings(struct net_device *ndev, struct ethtool_cmd *ecmd) 1638 { 1639 struct cpsw_priv *priv = netdev_priv(ndev); 1640 int slave_no = cpsw_slave_index(priv); 1641 1642 if (priv->slaves[slave_no].phy) 1643 return phy_ethtool_sset(priv->slaves[slave_no].phy, ecmd); 1644 else 1645 return -EOPNOTSUPP; 1646 } 1647 1648 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1649 { 1650 struct cpsw_priv *priv = netdev_priv(ndev); 1651 int slave_no = cpsw_slave_index(priv); 1652 1653 wol->supported = 0; 1654 wol->wolopts = 0; 1655 1656 if (priv->slaves[slave_no].phy) 1657 phy_ethtool_get_wol(priv->slaves[slave_no].phy, wol); 1658 } 1659 1660 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol) 1661 { 1662 struct cpsw_priv *priv = netdev_priv(ndev); 1663 int slave_no = cpsw_slave_index(priv); 1664 1665 if (priv->slaves[slave_no].phy) 1666 return phy_ethtool_set_wol(priv->slaves[slave_no].phy, wol); 1667 else 1668 return -EOPNOTSUPP; 1669 } 1670 1671 static const struct ethtool_ops cpsw_ethtool_ops = { 1672 .get_drvinfo = cpsw_get_drvinfo, 1673 .get_msglevel = cpsw_get_msglevel, 1674 .set_msglevel = cpsw_set_msglevel, 1675 .get_link = ethtool_op_get_link, 1676 .get_ts_info = cpsw_get_ts_info, 1677 .get_settings = cpsw_get_settings, 1678 .set_settings = cpsw_set_settings, 1679 .get_coalesce = cpsw_get_coalesce, 1680 .set_coalesce = cpsw_set_coalesce, 1681 .get_sset_count = cpsw_get_sset_count, 1682 .get_strings = cpsw_get_strings, 1683 .get_ethtool_stats = cpsw_get_ethtool_stats, 1684 .get_wol = cpsw_get_wol, 1685 .set_wol = cpsw_set_wol, 1686 }; 1687 1688 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_priv *priv, 1689 u32 slave_reg_ofs, u32 sliver_reg_ofs) 1690 { 1691 void __iomem *regs = priv->regs; 1692 int slave_num = slave->slave_num; 1693 struct cpsw_slave_data *data = priv->data.slave_data + slave_num; 1694 1695 slave->data = data; 1696 slave->regs = regs + slave_reg_ofs; 1697 slave->sliver = regs + sliver_reg_ofs; 1698 slave->port_vlan = data->dual_emac_res_vlan; 1699 } 1700 1701 static int cpsw_probe_dt(struct cpsw_platform_data *data, 1702 struct platform_device *pdev) 1703 { 1704 struct device_node *node = pdev->dev.of_node; 1705 struct device_node *slave_node; 1706 int i = 0, ret; 1707 u32 prop; 1708 1709 if (!node) 1710 return -EINVAL; 1711 1712 if (of_property_read_u32(node, "slaves", &prop)) { 1713 pr_err("Missing slaves property in the DT.\n"); 1714 return -EINVAL; 1715 } 1716 data->slaves = prop; 1717 1718 if (of_property_read_u32(node, "active_slave", &prop)) { 1719 pr_err("Missing active_slave property in the DT.\n"); 1720 return -EINVAL; 1721 } 1722 data->active_slave = prop; 1723 1724 if (of_property_read_u32(node, "cpts_clock_mult", &prop)) { 1725 pr_err("Missing cpts_clock_mult property in the DT.\n"); 1726 return -EINVAL; 1727 } 1728 data->cpts_clock_mult = prop; 1729 1730 if (of_property_read_u32(node, "cpts_clock_shift", &prop)) { 1731 pr_err("Missing cpts_clock_shift property in the DT.\n"); 1732 return -EINVAL; 1733 } 1734 data->cpts_clock_shift = prop; 1735 1736 data->slave_data = devm_kzalloc(&pdev->dev, data->slaves 1737 * sizeof(struct cpsw_slave_data), 1738 GFP_KERNEL); 1739 if (!data->slave_data) 1740 return -ENOMEM; 1741 1742 if (of_property_read_u32(node, "cpdma_channels", &prop)) { 1743 pr_err("Missing cpdma_channels property in the DT.\n"); 1744 return -EINVAL; 1745 } 1746 data->channels = prop; 1747 1748 if (of_property_read_u32(node, "ale_entries", &prop)) { 1749 pr_err("Missing ale_entries property in the DT.\n"); 1750 return -EINVAL; 1751 } 1752 data->ale_entries = prop; 1753 1754 if (of_property_read_u32(node, "bd_ram_size", &prop)) { 1755 pr_err("Missing bd_ram_size property in the DT.\n"); 1756 return -EINVAL; 1757 } 1758 data->bd_ram_size = prop; 1759 1760 if (of_property_read_u32(node, "rx_descs", &prop)) { 1761 pr_err("Missing rx_descs property in the DT.\n"); 1762 return -EINVAL; 1763 } 1764 data->rx_descs = prop; 1765 1766 if (of_property_read_u32(node, "mac_control", &prop)) { 1767 pr_err("Missing mac_control property in the DT.\n"); 1768 return -EINVAL; 1769 } 1770 data->mac_control = prop; 1771 1772 if (of_property_read_bool(node, "dual_emac")) 1773 data->dual_emac = 1; 1774 1775 /* 1776 * Populate all the child nodes here... 1777 */ 1778 ret = of_platform_populate(node, NULL, NULL, &pdev->dev); 1779 /* We do not want to force this, as in some cases may not have child */ 1780 if (ret) 1781 pr_warn("Doesn't have any child node\n"); 1782 1783 for_each_child_of_node(node, slave_node) { 1784 struct cpsw_slave_data *slave_data = data->slave_data + i; 1785 const void *mac_addr = NULL; 1786 u32 phyid; 1787 int lenp; 1788 const __be32 *parp; 1789 struct device_node *mdio_node; 1790 struct platform_device *mdio; 1791 1792 /* This is no slave child node, continue */ 1793 if (strcmp(slave_node->name, "slave")) 1794 continue; 1795 1796 parp = of_get_property(slave_node, "phy_id", &lenp); 1797 if ((parp == NULL) || (lenp != (sizeof(void *) * 2))) { 1798 pr_err("Missing slave[%d] phy_id property\n", i); 1799 return -EINVAL; 1800 } 1801 mdio_node = of_find_node_by_phandle(be32_to_cpup(parp)); 1802 phyid = be32_to_cpup(parp+1); 1803 mdio = of_find_device_by_node(mdio_node); 1804 snprintf(slave_data->phy_id, sizeof(slave_data->phy_id), 1805 PHY_ID_FMT, mdio->name, phyid); 1806 1807 mac_addr = of_get_mac_address(slave_node); 1808 if (mac_addr) 1809 memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN); 1810 1811 slave_data->phy_if = of_get_phy_mode(slave_node); 1812 1813 if (data->dual_emac) { 1814 if (of_property_read_u32(slave_node, "dual_emac_res_vlan", 1815 &prop)) { 1816 pr_err("Missing dual_emac_res_vlan in DT.\n"); 1817 slave_data->dual_emac_res_vlan = i+1; 1818 pr_err("Using %d as Reserved VLAN for %d slave\n", 1819 slave_data->dual_emac_res_vlan, i); 1820 } else { 1821 slave_data->dual_emac_res_vlan = prop; 1822 } 1823 } 1824 1825 i++; 1826 if (i == data->slaves) 1827 break; 1828 } 1829 1830 return 0; 1831 } 1832 1833 static int cpsw_probe_dual_emac(struct platform_device *pdev, 1834 struct cpsw_priv *priv) 1835 { 1836 struct cpsw_platform_data *data = &priv->data; 1837 struct net_device *ndev; 1838 struct cpsw_priv *priv_sl2; 1839 int ret = 0, i; 1840 1841 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1842 if (!ndev) { 1843 pr_err("cpsw: error allocating net_device\n"); 1844 return -ENOMEM; 1845 } 1846 1847 priv_sl2 = netdev_priv(ndev); 1848 spin_lock_init(&priv_sl2->lock); 1849 priv_sl2->data = *data; 1850 priv_sl2->pdev = pdev; 1851 priv_sl2->ndev = ndev; 1852 priv_sl2->dev = &ndev->dev; 1853 priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1854 priv_sl2->rx_packet_max = max(rx_packet_max, 128); 1855 1856 if (is_valid_ether_addr(data->slave_data[1].mac_addr)) { 1857 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr, 1858 ETH_ALEN); 1859 pr_info("cpsw: Detected MACID = %pM\n", priv_sl2->mac_addr); 1860 } else { 1861 random_ether_addr(priv_sl2->mac_addr); 1862 pr_info("cpsw: Random MACID = %pM\n", priv_sl2->mac_addr); 1863 } 1864 memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN); 1865 1866 priv_sl2->slaves = priv->slaves; 1867 priv_sl2->clk = priv->clk; 1868 1869 priv_sl2->coal_intvl = 0; 1870 priv_sl2->bus_freq_mhz = priv->bus_freq_mhz; 1871 1872 priv_sl2->regs = priv->regs; 1873 priv_sl2->host_port = priv->host_port; 1874 priv_sl2->host_port_regs = priv->host_port_regs; 1875 priv_sl2->wr_regs = priv->wr_regs; 1876 priv_sl2->hw_stats = priv->hw_stats; 1877 priv_sl2->dma = priv->dma; 1878 priv_sl2->txch = priv->txch; 1879 priv_sl2->rxch = priv->rxch; 1880 priv_sl2->ale = priv->ale; 1881 priv_sl2->emac_port = 1; 1882 priv->slaves[1].ndev = ndev; 1883 priv_sl2->cpts = priv->cpts; 1884 priv_sl2->version = priv->version; 1885 1886 for (i = 0; i < priv->num_irqs; i++) { 1887 priv_sl2->irqs_table[i] = priv->irqs_table[i]; 1888 priv_sl2->num_irqs = priv->num_irqs; 1889 } 1890 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 1891 1892 ndev->netdev_ops = &cpsw_netdev_ops; 1893 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 1894 netif_napi_add(ndev, &priv_sl2->napi, cpsw_poll, CPSW_POLL_WEIGHT); 1895 1896 /* register the network device */ 1897 SET_NETDEV_DEV(ndev, &pdev->dev); 1898 ret = register_netdev(ndev); 1899 if (ret) { 1900 pr_err("cpsw: error registering net device\n"); 1901 free_netdev(ndev); 1902 ret = -ENODEV; 1903 } 1904 1905 return ret; 1906 } 1907 1908 static int cpsw_probe(struct platform_device *pdev) 1909 { 1910 struct cpsw_platform_data *data; 1911 struct net_device *ndev; 1912 struct cpsw_priv *priv; 1913 struct cpdma_params dma_params; 1914 struct cpsw_ale_params ale_params; 1915 void __iomem *ss_regs; 1916 struct resource *res, *ss_res; 1917 u32 slave_offset, sliver_offset, slave_size; 1918 int ret = 0, i, k = 0; 1919 1920 ndev = alloc_etherdev(sizeof(struct cpsw_priv)); 1921 if (!ndev) { 1922 pr_err("error allocating net_device\n"); 1923 return -ENOMEM; 1924 } 1925 1926 platform_set_drvdata(pdev, ndev); 1927 priv = netdev_priv(ndev); 1928 spin_lock_init(&priv->lock); 1929 priv->pdev = pdev; 1930 priv->ndev = ndev; 1931 priv->dev = &ndev->dev; 1932 priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG); 1933 priv->rx_packet_max = max(rx_packet_max, 128); 1934 priv->cpts = devm_kzalloc(&pdev->dev, sizeof(struct cpts), GFP_KERNEL); 1935 priv->irq_enabled = true; 1936 if (!priv->cpts) { 1937 pr_err("error allocating cpts\n"); 1938 goto clean_ndev_ret; 1939 } 1940 1941 /* 1942 * This may be required here for child devices. 1943 */ 1944 pm_runtime_enable(&pdev->dev); 1945 1946 /* Select default pin state */ 1947 pinctrl_pm_select_default_state(&pdev->dev); 1948 1949 if (cpsw_probe_dt(&priv->data, pdev)) { 1950 pr_err("cpsw: platform data missing\n"); 1951 ret = -ENODEV; 1952 goto clean_runtime_disable_ret; 1953 } 1954 data = &priv->data; 1955 1956 if (is_valid_ether_addr(data->slave_data[0].mac_addr)) { 1957 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN); 1958 pr_info("Detected MACID = %pM\n", priv->mac_addr); 1959 } else { 1960 eth_random_addr(priv->mac_addr); 1961 pr_info("Random MACID = %pM\n", priv->mac_addr); 1962 } 1963 1964 memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN); 1965 1966 priv->slaves = devm_kzalloc(&pdev->dev, 1967 sizeof(struct cpsw_slave) * data->slaves, 1968 GFP_KERNEL); 1969 if (!priv->slaves) { 1970 ret = -ENOMEM; 1971 goto clean_runtime_disable_ret; 1972 } 1973 for (i = 0; i < data->slaves; i++) 1974 priv->slaves[i].slave_num = i; 1975 1976 priv->slaves[0].ndev = ndev; 1977 priv->emac_port = 0; 1978 1979 priv->clk = devm_clk_get(&pdev->dev, "fck"); 1980 if (IS_ERR(priv->clk)) { 1981 dev_err(priv->dev, "fck is not found\n"); 1982 ret = -ENODEV; 1983 goto clean_runtime_disable_ret; 1984 } 1985 priv->coal_intvl = 0; 1986 priv->bus_freq_mhz = clk_get_rate(priv->clk) / 1000000; 1987 1988 ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1989 ss_regs = devm_ioremap_resource(&pdev->dev, ss_res); 1990 if (IS_ERR(ss_regs)) { 1991 ret = PTR_ERR(ss_regs); 1992 goto clean_runtime_disable_ret; 1993 } 1994 priv->regs = ss_regs; 1995 priv->host_port = HOST_PORT_NUM; 1996 1997 /* Need to enable clocks with runtime PM api to access module 1998 * registers 1999 */ 2000 pm_runtime_get_sync(&pdev->dev); 2001 priv->version = readl(&priv->regs->id_ver); 2002 pm_runtime_put_sync(&pdev->dev); 2003 2004 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2005 priv->wr_regs = devm_ioremap_resource(&pdev->dev, res); 2006 if (IS_ERR(priv->wr_regs)) { 2007 ret = PTR_ERR(priv->wr_regs); 2008 goto clean_runtime_disable_ret; 2009 } 2010 2011 memset(&dma_params, 0, sizeof(dma_params)); 2012 memset(&ale_params, 0, sizeof(ale_params)); 2013 2014 switch (priv->version) { 2015 case CPSW_VERSION_1: 2016 priv->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET; 2017 priv->cpts->reg = ss_regs + CPSW1_CPTS_OFFSET; 2018 priv->hw_stats = ss_regs + CPSW1_HW_STATS; 2019 dma_params.dmaregs = ss_regs + CPSW1_CPDMA_OFFSET; 2020 dma_params.txhdp = ss_regs + CPSW1_STATERAM_OFFSET; 2021 ale_params.ale_regs = ss_regs + CPSW1_ALE_OFFSET; 2022 slave_offset = CPSW1_SLAVE_OFFSET; 2023 slave_size = CPSW1_SLAVE_SIZE; 2024 sliver_offset = CPSW1_SLIVER_OFFSET; 2025 dma_params.desc_mem_phys = 0; 2026 break; 2027 case CPSW_VERSION_2: 2028 case CPSW_VERSION_3: 2029 case CPSW_VERSION_4: 2030 priv->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET; 2031 priv->cpts->reg = ss_regs + CPSW2_CPTS_OFFSET; 2032 priv->hw_stats = ss_regs + CPSW2_HW_STATS; 2033 dma_params.dmaregs = ss_regs + CPSW2_CPDMA_OFFSET; 2034 dma_params.txhdp = ss_regs + CPSW2_STATERAM_OFFSET; 2035 ale_params.ale_regs = ss_regs + CPSW2_ALE_OFFSET; 2036 slave_offset = CPSW2_SLAVE_OFFSET; 2037 slave_size = CPSW2_SLAVE_SIZE; 2038 sliver_offset = CPSW2_SLIVER_OFFSET; 2039 dma_params.desc_mem_phys = 2040 (u32 __force) ss_res->start + CPSW2_BD_OFFSET; 2041 break; 2042 default: 2043 dev_err(priv->dev, "unknown version 0x%08x\n", priv->version); 2044 ret = -ENODEV; 2045 goto clean_runtime_disable_ret; 2046 } 2047 for (i = 0; i < priv->data.slaves; i++) { 2048 struct cpsw_slave *slave = &priv->slaves[i]; 2049 cpsw_slave_init(slave, priv, slave_offset, sliver_offset); 2050 slave_offset += slave_size; 2051 sliver_offset += SLIVER_SIZE; 2052 } 2053 2054 dma_params.dev = &pdev->dev; 2055 dma_params.rxthresh = dma_params.dmaregs + CPDMA_RXTHRESH; 2056 dma_params.rxfree = dma_params.dmaregs + CPDMA_RXFREE; 2057 dma_params.rxhdp = dma_params.txhdp + CPDMA_RXHDP; 2058 dma_params.txcp = dma_params.txhdp + CPDMA_TXCP; 2059 dma_params.rxcp = dma_params.txhdp + CPDMA_RXCP; 2060 2061 dma_params.num_chan = data->channels; 2062 dma_params.has_soft_reset = true; 2063 dma_params.min_packet_size = CPSW_MIN_PACKET_SIZE; 2064 dma_params.desc_mem_size = data->bd_ram_size; 2065 dma_params.desc_align = 16; 2066 dma_params.has_ext_regs = true; 2067 dma_params.desc_hw_addr = dma_params.desc_mem_phys; 2068 2069 priv->dma = cpdma_ctlr_create(&dma_params); 2070 if (!priv->dma) { 2071 dev_err(priv->dev, "error initializing dma\n"); 2072 ret = -ENOMEM; 2073 goto clean_runtime_disable_ret; 2074 } 2075 2076 priv->txch = cpdma_chan_create(priv->dma, tx_chan_num(0), 2077 cpsw_tx_handler); 2078 priv->rxch = cpdma_chan_create(priv->dma, rx_chan_num(0), 2079 cpsw_rx_handler); 2080 2081 if (WARN_ON(!priv->txch || !priv->rxch)) { 2082 dev_err(priv->dev, "error initializing dma channels\n"); 2083 ret = -ENOMEM; 2084 goto clean_dma_ret; 2085 } 2086 2087 ale_params.dev = &ndev->dev; 2088 ale_params.ale_ageout = ale_ageout; 2089 ale_params.ale_entries = data->ale_entries; 2090 ale_params.ale_ports = data->slaves; 2091 2092 priv->ale = cpsw_ale_create(&ale_params); 2093 if (!priv->ale) { 2094 dev_err(priv->dev, "error initializing ale engine\n"); 2095 ret = -ENODEV; 2096 goto clean_dma_ret; 2097 } 2098 2099 ndev->irq = platform_get_irq(pdev, 0); 2100 if (ndev->irq < 0) { 2101 dev_err(priv->dev, "error getting irq resource\n"); 2102 ret = -ENOENT; 2103 goto clean_ale_ret; 2104 } 2105 2106 while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) { 2107 for (i = res->start; i <= res->end; i++) { 2108 if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0, 2109 dev_name(priv->dev), priv)) { 2110 dev_err(priv->dev, "error attaching irq\n"); 2111 goto clean_ale_ret; 2112 } 2113 priv->irqs_table[k] = i; 2114 priv->num_irqs = k + 1; 2115 } 2116 k++; 2117 } 2118 2119 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 2120 2121 ndev->netdev_ops = &cpsw_netdev_ops; 2122 SET_ETHTOOL_OPS(ndev, &cpsw_ethtool_ops); 2123 netif_napi_add(ndev, &priv->napi, cpsw_poll, CPSW_POLL_WEIGHT); 2124 2125 /* register the network device */ 2126 SET_NETDEV_DEV(ndev, &pdev->dev); 2127 ret = register_netdev(ndev); 2128 if (ret) { 2129 dev_err(priv->dev, "error registering net device\n"); 2130 ret = -ENODEV; 2131 goto clean_ale_ret; 2132 } 2133 2134 if (cpts_register(&pdev->dev, priv->cpts, 2135 data->cpts_clock_mult, data->cpts_clock_shift)) 2136 dev_err(priv->dev, "error registering cpts device\n"); 2137 2138 cpsw_notice(priv, probe, "initialized device (regs %x, irq %d)\n", 2139 ss_res->start, ndev->irq); 2140 2141 if (priv->data.dual_emac) { 2142 ret = cpsw_probe_dual_emac(pdev, priv); 2143 if (ret) { 2144 cpsw_err(priv, probe, "error probe slave 2 emac interface\n"); 2145 goto clean_ale_ret; 2146 } 2147 } 2148 2149 return 0; 2150 2151 clean_ale_ret: 2152 cpsw_ale_destroy(priv->ale); 2153 clean_dma_ret: 2154 cpdma_chan_destroy(priv->txch); 2155 cpdma_chan_destroy(priv->rxch); 2156 cpdma_ctlr_destroy(priv->dma); 2157 clean_runtime_disable_ret: 2158 pm_runtime_disable(&pdev->dev); 2159 clean_ndev_ret: 2160 free_netdev(priv->ndev); 2161 return ret; 2162 } 2163 2164 static int cpsw_remove(struct platform_device *pdev) 2165 { 2166 struct net_device *ndev = platform_get_drvdata(pdev); 2167 struct cpsw_priv *priv = netdev_priv(ndev); 2168 2169 if (priv->data.dual_emac) 2170 unregister_netdev(cpsw_get_slave_ndev(priv, 1)); 2171 unregister_netdev(ndev); 2172 2173 cpsw_ale_destroy(priv->ale); 2174 cpdma_chan_destroy(priv->txch); 2175 cpdma_chan_destroy(priv->rxch); 2176 cpdma_ctlr_destroy(priv->dma); 2177 pm_runtime_disable(&pdev->dev); 2178 if (priv->data.dual_emac) 2179 free_netdev(cpsw_get_slave_ndev(priv, 1)); 2180 free_netdev(ndev); 2181 return 0; 2182 } 2183 2184 static int cpsw_suspend(struct device *dev) 2185 { 2186 struct platform_device *pdev = to_platform_device(dev); 2187 struct net_device *ndev = platform_get_drvdata(pdev); 2188 struct cpsw_priv *priv = netdev_priv(ndev); 2189 2190 if (netif_running(ndev)) 2191 cpsw_ndo_stop(ndev); 2192 2193 for_each_slave(priv, soft_reset_slave); 2194 2195 pm_runtime_put_sync(&pdev->dev); 2196 2197 /* Select sleep pin state */ 2198 pinctrl_pm_select_sleep_state(&pdev->dev); 2199 2200 return 0; 2201 } 2202 2203 static int cpsw_resume(struct device *dev) 2204 { 2205 struct platform_device *pdev = to_platform_device(dev); 2206 struct net_device *ndev = platform_get_drvdata(pdev); 2207 2208 pm_runtime_get_sync(&pdev->dev); 2209 2210 /* Select default pin state */ 2211 pinctrl_pm_select_default_state(&pdev->dev); 2212 2213 if (netif_running(ndev)) 2214 cpsw_ndo_open(ndev); 2215 return 0; 2216 } 2217 2218 static const struct dev_pm_ops cpsw_pm_ops = { 2219 .suspend = cpsw_suspend, 2220 .resume = cpsw_resume, 2221 }; 2222 2223 static const struct of_device_id cpsw_of_mtable[] = { 2224 { .compatible = "ti,cpsw", }, 2225 { /* sentinel */ }, 2226 }; 2227 MODULE_DEVICE_TABLE(of, cpsw_of_mtable); 2228 2229 static struct platform_driver cpsw_driver = { 2230 .driver = { 2231 .name = "cpsw", 2232 .owner = THIS_MODULE, 2233 .pm = &cpsw_pm_ops, 2234 .of_match_table = cpsw_of_mtable, 2235 }, 2236 .probe = cpsw_probe, 2237 .remove = cpsw_remove, 2238 }; 2239 2240 static int __init cpsw_init(void) 2241 { 2242 return platform_driver_register(&cpsw_driver); 2243 } 2244 late_initcall(cpsw_init); 2245 2246 static void __exit cpsw_exit(void) 2247 { 2248 platform_driver_unregister(&cpsw_driver); 2249 } 2250 module_exit(cpsw_exit); 2251 2252 MODULE_LICENSE("GPL"); 2253 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>"); 2254 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>"); 2255 MODULE_DESCRIPTION("TI CPSW Ethernet driver"); 2256