1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 */ 5 6 #ifndef AM65_CPSW_NUSS_H_ 7 #define AM65_CPSW_NUSS_H_ 8 9 #include <linux/if_ether.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/phylink.h> 14 #include <linux/platform_device.h> 15 #include <linux/soc/ti/k3-ringacc.h> 16 #include <net/devlink.h> 17 #include <net/xdp.h> 18 #include "am65-cpsw-qos.h" 19 20 struct am65_cpts; 21 22 #define HOST_PORT_NUM 0 23 24 #define AM65_CPSW_MAX_TX_QUEUES 8 25 #define AM65_CPSW_MAX_RX_QUEUES 1 26 #define AM65_CPSW_MAX_RX_FLOWS 1 27 28 #define AM65_CPSW_PORT_VLAN_REG_OFFSET 0x014 29 30 struct am65_cpsw_slave_data { 31 bool mac_only; 32 struct cpsw_sl *mac_sl; 33 struct device_node *port_np; 34 phy_interface_t phy_if; 35 struct phy *ifphy; 36 struct phy *serdes_phy; 37 bool rx_pause; 38 bool tx_pause; 39 u8 mac_addr[ETH_ALEN]; 40 int port_vlan; 41 struct phylink *phylink; 42 struct phylink_config phylink_config; 43 }; 44 45 struct am65_cpsw_port { 46 struct am65_cpsw_common *common; 47 struct net_device *ndev; 48 const char *name; 49 u32 port_id; 50 void __iomem *port_base; 51 void __iomem *sgmii_base; 52 void __iomem *stat_base; 53 void __iomem *fetch_ram_base; 54 bool disabled; 55 struct am65_cpsw_slave_data slave; 56 bool tx_ts_enabled; 57 bool rx_ts_enabled; 58 struct am65_cpsw_qos qos; 59 struct devlink_port devlink_port; 60 struct bpf_prog *xdp_prog; 61 struct xdp_rxq_info xdp_rxq; 62 /* Only for suspend resume context */ 63 u32 vid_context; 64 }; 65 66 enum am65_cpsw_tx_buf_type { 67 AM65_CPSW_TX_BUF_TYPE_SKB, 68 AM65_CPSW_TX_BUF_TYPE_XDP_TX, 69 AM65_CPSW_TX_BUF_TYPE_XDP_NDO, 70 }; 71 72 struct am65_cpsw_host { 73 struct am65_cpsw_common *common; 74 void __iomem *port_base; 75 void __iomem *stat_base; 76 /* Only for suspend resume context */ 77 u32 vid_context; 78 }; 79 80 struct am65_cpsw_tx_chn { 81 struct device *dma_dev; 82 struct napi_struct napi_tx; 83 struct am65_cpsw_common *common; 84 struct k3_cppi_desc_pool *desc_pool; 85 struct k3_udma_glue_tx_channel *tx_chn; 86 spinlock_t lock; /* protect TX rings in multi-port mode */ 87 struct hrtimer tx_hrtimer; 88 unsigned long tx_pace_timeout; 89 int irq; 90 u32 id; 91 u32 descs_num; 92 unsigned char dsize_log2; 93 char tx_chn_name[128]; 94 u32 rate_mbps; 95 }; 96 97 struct am65_cpsw_rx_chn { 98 struct device *dev; 99 struct device *dma_dev; 100 struct k3_cppi_desc_pool *desc_pool; 101 struct k3_udma_glue_rx_channel *rx_chn; 102 struct page_pool *page_pool; 103 struct page **pages; 104 u32 descs_num; 105 unsigned char dsize_log2; 106 int irq; 107 }; 108 109 #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0) 110 #define AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ BIT(1) 111 112 struct am65_cpsw_pdata { 113 u32 quirks; 114 u64 extra_modes; 115 enum k3_ring_mode fdqring_mode; 116 const char *ale_dev_id; 117 }; 118 119 enum cpsw_devlink_param_id { 120 AM65_CPSW_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 121 AM65_CPSW_DL_PARAM_SWITCH_MODE, 122 }; 123 124 struct am65_cpsw_devlink { 125 struct am65_cpsw_common *common; 126 }; 127 128 struct am65_cpsw_common { 129 struct device *dev; 130 struct device *mdio_dev; 131 struct am65_cpsw_pdata pdata; 132 133 void __iomem *ss_base; 134 void __iomem *cpsw_base; 135 136 u32 port_num; 137 struct am65_cpsw_host host; 138 struct am65_cpsw_port *ports; 139 u32 disabled_ports_mask; 140 struct net_device *dma_ndev; 141 142 int usage_count; /* number of opened ports */ 143 struct cpsw_ale *ale; 144 int tx_ch_num; 145 u32 tx_ch_rate_msk; 146 u32 rx_flow_id_base; 147 148 struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_TX_QUEUES]; 149 struct completion tdown_complete; 150 atomic_t tdown_cnt; 151 152 struct am65_cpsw_rx_chn rx_chns; 153 struct napi_struct napi_rx; 154 155 bool rx_irq_disabled; 156 struct hrtimer rx_hrtimer; 157 unsigned long rx_pace_timeout; 158 159 u32 nuss_ver; 160 u32 cpsw_ver; 161 unsigned long bus_freq; 162 bool pf_p0_rx_ptype_rrobin; 163 struct am65_cpts *cpts; 164 int est_enabled; 165 bool iet_enabled; 166 167 bool is_emac_mode; 168 u16 br_members; 169 int default_vlan; 170 struct devlink *devlink; 171 struct net_device *hw_bridge_dev; 172 struct notifier_block am65_cpsw_netdevice_nb; 173 unsigned char switch_id[MAX_PHYS_ITEM_ID_LEN]; 174 /* only for suspend/resume context restore */ 175 u32 *ale_context; 176 }; 177 178 struct am65_cpsw_ndev_stats { 179 u64 tx_packets; 180 u64 tx_bytes; 181 u64 rx_packets; 182 u64 rx_bytes; 183 struct u64_stats_sync syncp; 184 }; 185 186 struct am65_cpsw_ndev_priv { 187 u32 msg_enable; 188 struct am65_cpsw_port *port; 189 struct am65_cpsw_ndev_stats __percpu *stats; 190 bool offload_fwd_mark; 191 /* Serialize access to MAC Merge state between ethtool requests 192 * and link state updates 193 */ 194 struct mutex mm_lock; 195 }; 196 197 #define am65_ndev_to_priv(ndev) \ 198 ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev)) 199 #define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port) 200 #define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common) 201 #define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave) 202 203 #define am65_common_get_host(common) (&(common)->host) 204 #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1]) 205 206 #define am65_cpsw_napi_to_common(pnapi) \ 207 container_of(pnapi, struct am65_cpsw_common, napi_rx) 208 #define am65_cpsw_napi_to_tx_chn(pnapi) \ 209 container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx) 210 211 #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss" 212 213 #define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1) 214 215 extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave; 216 217 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common); 218 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common); 219 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx); 220 221 bool am65_cpsw_port_dev_check(const struct net_device *dev); 222 223 #endif /* AM65_CPSW_NUSS_H_ */ 224