1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 */ 5 6 #ifndef AM65_CPSW_NUSS_H_ 7 #define AM65_CPSW_NUSS_H_ 8 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/netdevice.h> 12 #include <linux/platform_device.h> 13 14 struct am65_cpts; 15 16 #define HOST_PORT_NUM 0 17 18 #define AM65_CPSW_MAX_TX_QUEUES 8 19 #define AM65_CPSW_MAX_RX_QUEUES 1 20 #define AM65_CPSW_MAX_RX_FLOWS 1 21 22 struct am65_cpsw_slave_data { 23 bool mac_only; 24 struct cpsw_sl *mac_sl; 25 struct device_node *phy_node; 26 struct phy_device *phy; 27 phy_interface_t phy_if; 28 struct phy *ifphy; 29 bool rx_pause; 30 bool tx_pause; 31 u8 mac_addr[ETH_ALEN]; 32 }; 33 34 struct am65_cpsw_port { 35 struct am65_cpsw_common *common; 36 struct net_device *ndev; 37 const char *name; 38 u32 port_id; 39 void __iomem *port_base; 40 void __iomem *stat_base; 41 bool disabled; 42 struct am65_cpsw_slave_data slave; 43 bool tx_ts_enabled; 44 bool rx_ts_enabled; 45 }; 46 47 struct am65_cpsw_host { 48 struct am65_cpsw_common *common; 49 void __iomem *port_base; 50 void __iomem *stat_base; 51 }; 52 53 struct am65_cpsw_tx_chn { 54 struct napi_struct napi_tx; 55 struct am65_cpsw_common *common; 56 struct k3_cppi_desc_pool *desc_pool; 57 struct k3_udma_glue_tx_channel *tx_chn; 58 int irq; 59 u32 id; 60 u32 descs_num; 61 char tx_chn_name[128]; 62 }; 63 64 struct am65_cpsw_rx_chn { 65 struct device *dev; 66 struct k3_cppi_desc_pool *desc_pool; 67 struct k3_udma_glue_rx_channel *rx_chn; 68 u32 descs_num; 69 int irq; 70 }; 71 72 #define AM65_CPSW_QUIRK_I2027_NO_TX_CSUM BIT(0) 73 74 struct am65_cpsw_pdata { 75 u32 quirks; 76 }; 77 78 struct am65_cpsw_common { 79 struct device *dev; 80 struct device *mdio_dev; 81 const struct am65_cpsw_pdata *pdata; 82 83 void __iomem *ss_base; 84 void __iomem *cpsw_base; 85 86 u32 port_num; 87 struct am65_cpsw_host host; 88 struct am65_cpsw_port *ports; 89 u32 disabled_ports_mask; 90 91 int usage_count; /* number of opened ports */ 92 struct cpsw_ale *ale; 93 int tx_ch_num; 94 u32 rx_flow_id_base; 95 96 struct am65_cpsw_tx_chn tx_chns[AM65_CPSW_MAX_TX_QUEUES]; 97 struct completion tdown_complete; 98 atomic_t tdown_cnt; 99 100 struct am65_cpsw_rx_chn rx_chns; 101 struct napi_struct napi_rx; 102 103 u32 nuss_ver; 104 u32 cpsw_ver; 105 bool pf_p0_rx_ptype_rrobin; 106 struct am65_cpts *cpts; 107 }; 108 109 struct am65_cpsw_ndev_stats { 110 u64 tx_packets; 111 u64 tx_bytes; 112 u64 rx_packets; 113 u64 rx_bytes; 114 struct u64_stats_sync syncp; 115 }; 116 117 struct am65_cpsw_ndev_priv { 118 u32 msg_enable; 119 struct am65_cpsw_port *port; 120 struct am65_cpsw_ndev_stats __percpu *stats; 121 }; 122 123 #define am65_ndev_to_priv(ndev) \ 124 ((struct am65_cpsw_ndev_priv *)netdev_priv(ndev)) 125 #define am65_ndev_to_port(ndev) (am65_ndev_to_priv(ndev)->port) 126 #define am65_ndev_to_common(ndev) (am65_ndev_to_port(ndev)->common) 127 #define am65_ndev_to_slave(ndev) (&am65_ndev_to_port(ndev)->slave) 128 129 #define am65_common_get_host(common) (&(common)->host) 130 #define am65_common_get_port(common, id) (&(common)->ports[(id) - 1]) 131 132 #define am65_cpsw_napi_to_common(pnapi) \ 133 container_of(pnapi, struct am65_cpsw_common, napi_rx) 134 #define am65_cpsw_napi_to_tx_chn(pnapi) \ 135 container_of(pnapi, struct am65_cpsw_tx_chn, napi_tx) 136 137 #define AM65_CPSW_DRV_NAME "am65-cpsw-nuss" 138 139 #define AM65_CPSW_IS_CPSW2G(common) ((common)->port_num == 1) 140 141 extern const struct ethtool_ops am65_cpsw_ethtool_ops_slave; 142 143 void am65_cpsw_nuss_adjust_link(struct net_device *ndev); 144 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common); 145 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common); 146 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx); 147 148 #endif /* AM65_CPSW_NUSS_H_ */ 149