1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/bpf_trace.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/kmemleak.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/phylink.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/rtnetlink.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/sys_soc.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 #include <net/page_pool/helpers.h> 35 #include <net/switchdev.h> 36 37 #include "cpsw_ale.h" 38 #include "cpsw_sl.h" 39 #include "am65-cpsw-nuss.h" 40 #include "am65-cpsw-switchdev.h" 41 #include "k3-cppi-desc-pool.h" 42 #include "am65-cpts.h" 43 44 #define AM65_CPSW_SS_BASE 0x0 45 #define AM65_CPSW_SGMII_BASE 0x100 46 #define AM65_CPSW_XGMII_BASE 0x2100 47 #define AM65_CPSW_CPSW_NU_BASE 0x20000 48 #define AM65_CPSW_NU_PORTS_BASE 0x1000 49 #define AM65_CPSW_NU_FRAM_BASE 0x12000 50 #define AM65_CPSW_NU_STATS_BASE 0x1a000 51 #define AM65_CPSW_NU_ALE_BASE 0x1e000 52 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 53 54 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 55 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 56 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 57 58 #define AM65_CPSW_MAX_PORTS 8 59 60 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 61 #define AM65_CPSW_MAX_PACKET_SIZE 2024 62 63 #define AM65_CPSW_REG_CTL 0x004 64 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 65 #define AM65_CPSW_REG_PTYPE 0x018 66 67 #define AM65_CPSW_P0_REG_CTL 0x004 68 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 69 70 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 71 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 72 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 73 74 #define AM65_CPSW_PORTN_REG_SA_L 0x308 75 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 76 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 77 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 78 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 79 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 80 81 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 82 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 83 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 84 85 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 86 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 87 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 88 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 89 90 /* AM65_CPSW_P0_REG_CTL */ 91 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 92 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 93 94 /* AM65_CPSW_PORT_REG_PRI_CTL */ 95 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 96 97 /* AM65_CPSW_PN_TS_CTL register fields */ 98 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 99 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 100 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 101 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 102 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 103 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 104 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 105 106 #define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0) 107 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1) 108 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2) 109 #define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3) 110 #define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9) 111 112 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 113 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 114 115 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 116 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 117 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 118 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 119 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 120 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 121 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 122 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 123 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 124 125 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 126 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 127 128 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 129 130 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 131 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 132 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 133 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 134 135 #define AM65_CPSW_TS_RX_ANX_ALL_EN \ 136 (AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \ 137 AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \ 138 AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) 139 140 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 141 /* Number of TX/RX descriptors */ 142 #define AM65_CPSW_MAX_TX_DESC 500 143 #define AM65_CPSW_MAX_RX_DESC 500 144 145 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 146 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 147 148 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 149 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 150 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 151 152 #define AM65_CPSW_DEFAULT_TX_CHNS 8 153 154 /* CPPI streaming packet interface */ 155 #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF 156 #define AM65_CPSW_CPPI_TX_PKT_TYPE 0x7 157 158 /* XDP */ 159 #define AM65_CPSW_XDP_CONSUMED BIT(1) 160 #define AM65_CPSW_XDP_REDIRECT BIT(0) 161 #define AM65_CPSW_XDP_PASS 0 162 163 /* Include headroom compatible with both skb and xdpf */ 164 #define AM65_CPSW_HEADROOM_NA (max(NET_SKB_PAD, XDP_PACKET_HEADROOM) + NET_IP_ALIGN) 165 #define AM65_CPSW_HEADROOM ALIGN(AM65_CPSW_HEADROOM_NA, sizeof(long)) 166 167 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 168 const u8 *dev_addr) 169 { 170 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 171 (dev_addr[2] << 16) | (dev_addr[3] << 24); 172 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 173 174 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 175 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 176 } 177 178 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 179 { 180 cpsw_sl_reset(port->slave.mac_sl, 100); 181 /* Max length register has to be restored after MAC SL reset */ 182 writel(AM65_CPSW_MAX_PACKET_SIZE, 183 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 184 } 185 186 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 187 { 188 common->nuss_ver = readl(common->ss_base); 189 common->cpsw_ver = readl(common->cpsw_base); 190 dev_info(common->dev, 191 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 192 common->nuss_ver, 193 common->cpsw_ver, 194 common->port_num + 1, 195 common->pdata.quirks); 196 } 197 198 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 199 __be16 proto, u16 vid) 200 { 201 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 202 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 203 u32 port_mask, unreg_mcast = 0; 204 int ret; 205 206 if (!common->is_emac_mode) 207 return 0; 208 209 if (!netif_running(ndev) || !vid) 210 return 0; 211 212 ret = pm_runtime_resume_and_get(common->dev); 213 if (ret < 0) 214 return ret; 215 216 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 217 if (!vid) 218 unreg_mcast = port_mask; 219 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 220 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 221 unreg_mcast, port_mask, 0); 222 223 pm_runtime_put(common->dev); 224 return ret; 225 } 226 227 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 228 __be16 proto, u16 vid) 229 { 230 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 231 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 232 int ret; 233 234 if (!common->is_emac_mode) 235 return 0; 236 237 if (!netif_running(ndev) || !vid) 238 return 0; 239 240 ret = pm_runtime_resume_and_get(common->dev); 241 if (ret < 0) 242 return ret; 243 244 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 245 ret = cpsw_ale_del_vlan(common->ale, vid, 246 BIT(port->port_id) | ALE_PORT_HOST); 247 248 pm_runtime_put(common->dev); 249 return ret; 250 } 251 252 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 253 bool promisc) 254 { 255 struct am65_cpsw_common *common = port->common; 256 257 if (promisc && !common->is_emac_mode) { 258 dev_dbg(common->dev, "promisc mode requested in switch mode"); 259 return; 260 } 261 262 if (promisc) { 263 /* Enable promiscuous mode */ 264 cpsw_ale_control_set(common->ale, port->port_id, 265 ALE_PORT_MACONLY_CAF, 1); 266 dev_dbg(common->dev, "promisc enabled\n"); 267 } else { 268 /* Disable promiscuous mode */ 269 cpsw_ale_control_set(common->ale, port->port_id, 270 ALE_PORT_MACONLY_CAF, 0); 271 dev_dbg(common->dev, "promisc disabled\n"); 272 } 273 } 274 275 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 276 { 277 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 278 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 279 u32 port_mask; 280 bool promisc; 281 282 promisc = !!(ndev->flags & IFF_PROMISC); 283 am65_cpsw_slave_set_promisc(port, promisc); 284 285 if (promisc) 286 return; 287 288 /* Restore allmulti on vlans if necessary */ 289 cpsw_ale_set_allmulti(common->ale, 290 ndev->flags & IFF_ALLMULTI, port->port_id); 291 292 port_mask = ALE_PORT_HOST; 293 /* Clear all mcast from ALE */ 294 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 295 296 if (!netdev_mc_empty(ndev)) { 297 struct netdev_hw_addr *ha; 298 299 /* program multicast address list into ALE register */ 300 netdev_for_each_mc_addr(ha, ndev) { 301 cpsw_ale_add_mcast(common->ale, ha->addr, 302 port_mask, 0, 0, 0); 303 } 304 } 305 } 306 307 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 308 unsigned int txqueue) 309 { 310 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 311 struct am65_cpsw_tx_chn *tx_chn; 312 struct netdev_queue *netif_txq; 313 unsigned long trans_start; 314 315 netif_txq = netdev_get_tx_queue(ndev, txqueue); 316 tx_chn = &common->tx_chns[txqueue]; 317 trans_start = READ_ONCE(netif_txq->trans_start); 318 319 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 320 txqueue, 321 netif_tx_queue_stopped(netif_txq), 322 jiffies_to_msecs(jiffies - trans_start), 323 netdev_queue_dql_avail(netif_txq), 324 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 325 326 if (netif_tx_queue_stopped(netif_txq)) { 327 /* try recover if stopped by us */ 328 txq_trans_update(netif_txq); 329 netif_tx_wake_queue(netif_txq); 330 } 331 } 332 333 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 334 struct page *page) 335 { 336 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 337 struct cppi5_host_desc_t *desc_rx; 338 struct device *dev = common->dev; 339 dma_addr_t desc_dma; 340 dma_addr_t buf_dma; 341 void *swdata; 342 343 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 344 if (!desc_rx) { 345 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 346 return -ENOMEM; 347 } 348 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 349 350 buf_dma = dma_map_single(rx_chn->dma_dev, 351 page_address(page) + AM65_CPSW_HEADROOM, 352 AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); 353 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 354 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 355 dev_err(dev, "Failed to map rx buffer\n"); 356 return -EINVAL; 357 } 358 359 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 360 AM65_CPSW_NAV_PS_DATA_SIZE); 361 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 362 cppi5_hdesc_attach_buf(desc_rx, buf_dma, AM65_CPSW_MAX_PACKET_SIZE, 363 buf_dma, AM65_CPSW_MAX_PACKET_SIZE); 364 swdata = cppi5_hdesc_get_swdata(desc_rx); 365 *((void **)swdata) = page_address(page); 366 367 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 368 } 369 370 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 371 { 372 struct am65_cpsw_host *host_p = am65_common_get_host(common); 373 u32 val, pri_map; 374 375 /* P0 set Receive Priority Type */ 376 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 377 378 if (common->pf_p0_rx_ptype_rrobin) { 379 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 380 /* Enet Ports fifos works in fixed priority mode only, so 381 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 382 */ 383 pri_map = 0x0; 384 } else { 385 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 386 /* restore P0_Rx_Pri_Map */ 387 pri_map = 0x76543210; 388 } 389 390 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 391 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 392 } 393 394 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 395 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 396 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 397 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 398 399 static void am65_cpsw_destroy_xdp_rxqs(struct am65_cpsw_common *common) 400 { 401 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 402 struct xdp_rxq_info *rxq; 403 int i; 404 405 for (i = 0; i < common->port_num; i++) { 406 if (!common->ports[i].ndev) 407 continue; 408 409 rxq = &common->ports[i].xdp_rxq; 410 411 if (xdp_rxq_info_is_reg(rxq)) 412 xdp_rxq_info_unreg(rxq); 413 } 414 415 if (rx_chn->page_pool) { 416 page_pool_destroy(rx_chn->page_pool); 417 rx_chn->page_pool = NULL; 418 } 419 } 420 421 static int am65_cpsw_create_xdp_rxqs(struct am65_cpsw_common *common) 422 { 423 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 424 struct page_pool_params pp_params = { 425 .flags = PP_FLAG_DMA_MAP, 426 .order = 0, 427 .pool_size = AM65_CPSW_MAX_RX_DESC, 428 .nid = dev_to_node(common->dev), 429 .dev = common->dev, 430 .dma_dir = DMA_BIDIRECTIONAL, 431 .napi = &common->napi_rx, 432 }; 433 struct xdp_rxq_info *rxq; 434 struct page_pool *pool; 435 int i, ret; 436 437 pool = page_pool_create(&pp_params); 438 if (IS_ERR(pool)) 439 return PTR_ERR(pool); 440 441 rx_chn->page_pool = pool; 442 443 for (i = 0; i < common->port_num; i++) { 444 if (!common->ports[i].ndev) 445 continue; 446 447 rxq = &common->ports[i].xdp_rxq; 448 449 ret = xdp_rxq_info_reg(rxq, common->ports[i].ndev, i, 0); 450 if (ret) 451 goto err; 452 453 ret = xdp_rxq_info_reg_mem_model(rxq, MEM_TYPE_PAGE_POOL, pool); 454 if (ret) 455 goto err; 456 } 457 458 return 0; 459 460 err: 461 am65_cpsw_destroy_xdp_rxqs(common); 462 return ret; 463 } 464 465 static int am65_cpsw_nuss_desc_idx(struct k3_cppi_desc_pool *desc_pool, 466 void *desc, 467 unsigned char dsize_log2) 468 { 469 void *pool_addr = k3_cppi_desc_pool_cpuaddr(desc_pool); 470 471 return (desc - pool_addr) >> dsize_log2; 472 } 473 474 static void am65_cpsw_nuss_set_buf_type(struct am65_cpsw_tx_chn *tx_chn, 475 struct cppi5_host_desc_t *desc, 476 enum am65_cpsw_tx_buf_type buf_type) 477 { 478 int desc_idx; 479 480 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc, 481 tx_chn->dsize_log2); 482 k3_cppi_desc_pool_desc_info_set(tx_chn->desc_pool, desc_idx, 483 (void *)buf_type); 484 } 485 486 static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_chn *tx_chn, 487 dma_addr_t desc_dma) 488 { 489 struct cppi5_host_desc_t *desc_tx; 490 int desc_idx; 491 492 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 493 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc_tx, 494 tx_chn->dsize_log2); 495 496 return (enum am65_cpsw_tx_buf_type)k3_cppi_desc_pool_desc_info(tx_chn->desc_pool, 497 desc_idx); 498 } 499 500 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_chn *rx_chn, 501 struct page *page, 502 bool allow_direct, 503 int desc_idx) 504 { 505 page_pool_put_full_page(rx_chn->page_pool, page, allow_direct); 506 rx_chn->pages[desc_idx] = NULL; 507 } 508 509 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 510 { 511 struct am65_cpsw_rx_chn *rx_chn = data; 512 struct cppi5_host_desc_t *desc_rx; 513 dma_addr_t buf_dma; 514 u32 buf_dma_len; 515 void *page_addr; 516 void **swdata; 517 int desc_idx; 518 519 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 520 swdata = cppi5_hdesc_get_swdata(desc_rx); 521 page_addr = *swdata; 522 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 523 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 524 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 525 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 526 527 desc_idx = am65_cpsw_nuss_desc_idx(rx_chn->desc_pool, desc_rx, 528 rx_chn->dsize_log2); 529 am65_cpsw_put_page(rx_chn, virt_to_page(page_addr), false, desc_idx); 530 } 531 532 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 533 struct cppi5_host_desc_t *desc) 534 { 535 struct cppi5_host_desc_t *first_desc, *next_desc; 536 dma_addr_t buf_dma, next_desc_dma; 537 u32 buf_dma_len; 538 539 first_desc = desc; 540 next_desc = first_desc; 541 542 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 543 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 544 545 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 546 547 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 548 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 549 while (next_desc_dma) { 550 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 551 next_desc_dma); 552 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 553 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 554 555 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 556 DMA_TO_DEVICE); 557 558 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 559 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 560 561 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 562 } 563 564 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 565 } 566 567 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 568 { 569 struct am65_cpsw_tx_chn *tx_chn = data; 570 struct cppi5_host_desc_t *desc_tx; 571 struct sk_buff *skb; 572 void **swdata; 573 574 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 575 swdata = cppi5_hdesc_get_swdata(desc_tx); 576 skb = *(swdata); 577 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 578 579 dev_kfree_skb_any(skb); 580 } 581 582 static struct sk_buff *am65_cpsw_build_skb(void *page_addr, 583 struct net_device *ndev, 584 unsigned int len) 585 { 586 struct sk_buff *skb; 587 588 len += AM65_CPSW_HEADROOM; 589 590 skb = build_skb(page_addr, len); 591 if (unlikely(!skb)) 592 return NULL; 593 594 skb_reserve(skb, AM65_CPSW_HEADROOM); 595 skb->dev = ndev; 596 597 return skb; 598 } 599 600 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 601 { 602 struct am65_cpsw_host *host_p = am65_common_get_host(common); 603 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 604 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 605 int port_idx, i, ret, tx; 606 u32 val, port_mask; 607 struct page *page; 608 609 if (common->usage_count) 610 return 0; 611 612 /* Control register */ 613 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 614 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 615 common->cpsw_base + AM65_CPSW_REG_CTL); 616 /* Max length register */ 617 writel(AM65_CPSW_MAX_PACKET_SIZE, 618 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 619 /* set base flow_id */ 620 writel(common->rx_flow_id_base, 621 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 622 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 623 host_p->port_base + AM65_CPSW_P0_REG_CTL); 624 625 am65_cpsw_nuss_set_p0_ptype(common); 626 627 /* enable statistic */ 628 val = BIT(HOST_PORT_NUM); 629 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 630 struct am65_cpsw_port *port = &common->ports[port_idx]; 631 632 if (!port->disabled) 633 val |= BIT(port->port_id); 634 } 635 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 636 637 /* disable priority elevation */ 638 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 639 640 cpsw_ale_start(common->ale); 641 642 /* limit to one RX flow only */ 643 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 644 ALE_DEFAULT_THREAD_ID, 0); 645 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 646 ALE_DEFAULT_THREAD_ENABLE, 1); 647 /* switch to vlan unaware mode */ 648 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 649 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 650 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 651 652 /* default vlan cfg: create mask based on enabled ports */ 653 port_mask = GENMASK(common->port_num, 0) & 654 ~common->disabled_ports_mask; 655 656 cpsw_ale_add_vlan(common->ale, 0, port_mask, 657 port_mask, port_mask, 658 port_mask & ~ALE_PORT_HOST); 659 660 if (common->is_emac_mode) 661 am65_cpsw_init_host_port_emac(common); 662 else 663 am65_cpsw_init_host_port_switch(common); 664 665 am65_cpsw_qos_tx_p0_rate_init(common); 666 667 ret = am65_cpsw_create_xdp_rxqs(common); 668 if (ret) { 669 dev_err(common->dev, "Failed to create XDP rx queues\n"); 670 return ret; 671 } 672 673 for (i = 0; i < rx_chn->descs_num; i++) { 674 page = page_pool_dev_alloc_pages(rx_chn->page_pool); 675 if (!page) { 676 ret = -ENOMEM; 677 if (i) 678 goto fail_rx; 679 680 return ret; 681 } 682 rx_chn->pages[i] = page; 683 684 ret = am65_cpsw_nuss_rx_push(common, page); 685 if (ret < 0) { 686 dev_err(common->dev, 687 "cannot submit page to channel rx: %d\n", 688 ret); 689 am65_cpsw_put_page(rx_chn, page, false, i); 690 if (i) 691 goto fail_rx; 692 693 return ret; 694 } 695 } 696 697 ret = k3_udma_glue_enable_rx_chn(rx_chn->rx_chn); 698 if (ret) { 699 dev_err(common->dev, "couldn't enable rx chn: %d\n", ret); 700 goto fail_rx; 701 } 702 703 for (tx = 0; tx < common->tx_ch_num; tx++) { 704 ret = k3_udma_glue_enable_tx_chn(tx_chn[tx].tx_chn); 705 if (ret) { 706 dev_err(common->dev, "couldn't enable tx chn %d: %d\n", 707 tx, ret); 708 tx--; 709 goto fail_tx; 710 } 711 napi_enable(&tx_chn[tx].napi_tx); 712 } 713 714 napi_enable(&common->napi_rx); 715 if (common->rx_irq_disabled) { 716 common->rx_irq_disabled = false; 717 enable_irq(rx_chn->irq); 718 } 719 720 dev_dbg(common->dev, "cpsw_nuss started\n"); 721 return 0; 722 723 fail_tx: 724 while (tx >= 0) { 725 napi_disable(&tx_chn[tx].napi_tx); 726 k3_udma_glue_disable_tx_chn(tx_chn[tx].tx_chn); 727 tx--; 728 } 729 730 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 731 732 fail_rx: 733 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, 0, rx_chn, 734 am65_cpsw_nuss_rx_cleanup, 0); 735 return ret; 736 } 737 738 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 739 { 740 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 741 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 742 int i; 743 744 if (common->usage_count != 1) 745 return 0; 746 747 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 748 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 749 750 /* shutdown tx channels */ 751 atomic_set(&common->tdown_cnt, common->tx_ch_num); 752 /* ensure new tdown_cnt value is visible */ 753 smp_mb__after_atomic(); 754 reinit_completion(&common->tdown_complete); 755 756 for (i = 0; i < common->tx_ch_num; i++) 757 k3_udma_glue_tdown_tx_chn(tx_chn[i].tx_chn, false); 758 759 i = wait_for_completion_timeout(&common->tdown_complete, 760 msecs_to_jiffies(1000)); 761 if (!i) 762 dev_err(common->dev, "tx timeout\n"); 763 for (i = 0; i < common->tx_ch_num; i++) { 764 napi_disable(&tx_chn[i].napi_tx); 765 hrtimer_cancel(&tx_chn[i].tx_hrtimer); 766 } 767 768 for (i = 0; i < common->tx_ch_num; i++) { 769 k3_udma_glue_reset_tx_chn(tx_chn[i].tx_chn, &tx_chn[i], 770 am65_cpsw_nuss_tx_cleanup); 771 k3_udma_glue_disable_tx_chn(tx_chn[i].tx_chn); 772 } 773 774 reinit_completion(&common->tdown_complete); 775 k3_udma_glue_tdown_rx_chn(rx_chn->rx_chn, true); 776 777 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 778 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 779 if (!i) 780 dev_err(common->dev, "rx teardown timeout\n"); 781 } 782 783 napi_disable(&common->napi_rx); 784 hrtimer_cancel(&common->rx_hrtimer); 785 786 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 787 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, rx_chn, 788 am65_cpsw_nuss_rx_cleanup, !!i); 789 790 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 791 792 cpsw_ale_stop(common->ale); 793 794 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 795 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 796 797 for (i = 0; i < rx_chn->descs_num; i++) { 798 if (rx_chn->pages[i]) 799 am65_cpsw_put_page(rx_chn, rx_chn->pages[i], false, i); 800 } 801 am65_cpsw_destroy_xdp_rxqs(common); 802 803 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 804 return 0; 805 } 806 807 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 808 { 809 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 810 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 811 int ret; 812 813 phylink_stop(port->slave.phylink); 814 815 netif_tx_stop_all_queues(ndev); 816 817 phylink_disconnect_phy(port->slave.phylink); 818 819 ret = am65_cpsw_nuss_common_stop(common); 820 if (ret) 821 return ret; 822 823 common->usage_count--; 824 pm_runtime_put(common->dev); 825 return 0; 826 } 827 828 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 829 { 830 struct am65_cpsw_port *port = arg; 831 832 if (!vdev) 833 return 0; 834 835 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 836 } 837 838 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 839 { 840 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 841 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 842 int ret, i; 843 u32 reg; 844 845 ret = pm_runtime_resume_and_get(common->dev); 846 if (ret < 0) 847 return ret; 848 849 /* Idle MAC port */ 850 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 851 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 852 cpsw_sl_ctl_reset(port->slave.mac_sl); 853 854 /* soft reset MAC */ 855 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 856 mdelay(1); 857 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 858 if (reg) { 859 dev_err(common->dev, "soft RESET didn't complete\n"); 860 ret = -ETIMEDOUT; 861 goto runtime_put; 862 } 863 864 /* Notify the stack of the actual queue counts. */ 865 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 866 if (ret) { 867 dev_err(common->dev, "cannot set real number of tx queues\n"); 868 goto runtime_put; 869 } 870 871 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 872 if (ret) { 873 dev_err(common->dev, "cannot set real number of rx queues\n"); 874 goto runtime_put; 875 } 876 877 for (i = 0; i < common->tx_ch_num; i++) { 878 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 879 880 netdev_tx_reset_queue(txq); 881 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 882 } 883 884 ret = am65_cpsw_nuss_common_open(common); 885 if (ret) 886 goto runtime_put; 887 888 common->usage_count++; 889 890 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 891 892 if (common->is_emac_mode) 893 am65_cpsw_init_port_emac_ale(port); 894 else 895 am65_cpsw_init_port_switch_ale(port); 896 897 /* mac_sl should be configured via phy-link interface */ 898 am65_cpsw_sl_ctl_reset(port); 899 900 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.port_np, 0); 901 if (ret) 902 goto error_cleanup; 903 904 /* restore vlan configurations */ 905 vlan_for_each(ndev, cpsw_restore_vlans, port); 906 907 phylink_start(port->slave.phylink); 908 909 return 0; 910 911 error_cleanup: 912 am65_cpsw_nuss_ndo_slave_stop(ndev); 913 return ret; 914 915 runtime_put: 916 pm_runtime_put(common->dev); 917 return ret; 918 } 919 920 static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, 921 struct am65_cpsw_tx_chn *tx_chn, 922 struct xdp_frame *xdpf, 923 enum am65_cpsw_tx_buf_type buf_type) 924 { 925 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 926 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 927 struct cppi5_host_desc_t *host_desc; 928 struct netdev_queue *netif_txq; 929 dma_addr_t dma_desc, dma_buf; 930 u32 pkt_len = xdpf->len; 931 void **swdata; 932 int ret; 933 934 host_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 935 if (unlikely(!host_desc)) { 936 ndev->stats.tx_dropped++; 937 return AM65_CPSW_XDP_CONSUMED; /* drop */ 938 } 939 940 am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, buf_type); 941 942 dma_buf = dma_map_single(tx_chn->dma_dev, xdpf->data, 943 pkt_len, DMA_TO_DEVICE); 944 if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { 945 ndev->stats.tx_dropped++; 946 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 947 goto pool_free; 948 } 949 950 cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 951 AM65_CPSW_NAV_PS_DATA_SIZE); 952 cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 953 cppi5_hdesc_set_pktlen(host_desc, pkt_len); 954 cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 955 cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); 956 957 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); 958 cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); 959 960 swdata = cppi5_hdesc_get_swdata(host_desc); 961 *(swdata) = xdpf; 962 963 /* Report BQL before sending the packet */ 964 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 965 netdev_tx_sent_queue(netif_txq, pkt_len); 966 967 dma_desc = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); 968 if (AM65_CPSW_IS_CPSW2G(common)) { 969 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 970 dma_desc); 971 } else { 972 spin_lock_bh(&tx_chn->lock); 973 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 974 dma_desc); 975 spin_unlock_bh(&tx_chn->lock); 976 } 977 if (ret) { 978 /* Inform BQL */ 979 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 980 ndev->stats.tx_errors++; 981 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 982 goto dma_unmap; 983 } 984 985 return 0; 986 987 dma_unmap: 988 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); 989 dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); 990 pool_free: 991 k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); 992 return ret; 993 } 994 995 static int am65_cpsw_run_xdp(struct am65_cpsw_common *common, 996 struct am65_cpsw_port *port, 997 struct xdp_buff *xdp, 998 int desc_idx, int cpu, int *len) 999 { 1000 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1001 struct am65_cpsw_ndev_priv *ndev_priv; 1002 struct net_device *ndev = port->ndev; 1003 struct am65_cpsw_ndev_stats *stats; 1004 int ret = AM65_CPSW_XDP_CONSUMED; 1005 struct am65_cpsw_tx_chn *tx_chn; 1006 struct netdev_queue *netif_txq; 1007 struct xdp_frame *xdpf; 1008 struct bpf_prog *prog; 1009 struct page *page; 1010 u32 act; 1011 int err; 1012 1013 prog = READ_ONCE(port->xdp_prog); 1014 if (!prog) 1015 return AM65_CPSW_XDP_PASS; 1016 1017 act = bpf_prog_run_xdp(prog, xdp); 1018 /* XDP prog might have changed packet data and boundaries */ 1019 *len = xdp->data_end - xdp->data; 1020 1021 ndev_priv = netdev_priv(ndev); 1022 stats = this_cpu_ptr(ndev_priv->stats); 1023 1024 switch (act) { 1025 case XDP_PASS: 1026 ret = AM65_CPSW_XDP_PASS; 1027 goto out; 1028 case XDP_TX: 1029 tx_chn = &common->tx_chns[cpu % AM65_CPSW_MAX_TX_QUEUES]; 1030 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1031 1032 xdpf = xdp_convert_buff_to_frame(xdp); 1033 if (unlikely(!xdpf)) 1034 goto drop; 1035 1036 __netif_tx_lock(netif_txq, cpu); 1037 err = am65_cpsw_xdp_tx_frame(ndev, tx_chn, xdpf, 1038 AM65_CPSW_TX_BUF_TYPE_XDP_TX); 1039 __netif_tx_unlock(netif_txq); 1040 if (err) 1041 goto drop; 1042 1043 u64_stats_update_begin(&stats->syncp); 1044 stats->rx_bytes += *len; 1045 stats->rx_packets++; 1046 u64_stats_update_end(&stats->syncp); 1047 ret = AM65_CPSW_XDP_CONSUMED; 1048 goto out; 1049 case XDP_REDIRECT: 1050 if (unlikely(xdp_do_redirect(ndev, xdp, prog))) 1051 goto drop; 1052 1053 u64_stats_update_begin(&stats->syncp); 1054 stats->rx_bytes += *len; 1055 stats->rx_packets++; 1056 u64_stats_update_end(&stats->syncp); 1057 ret = AM65_CPSW_XDP_REDIRECT; 1058 goto out; 1059 default: 1060 bpf_warn_invalid_xdp_action(ndev, prog, act); 1061 fallthrough; 1062 case XDP_ABORTED: 1063 drop: 1064 trace_xdp_exception(ndev, prog, act); 1065 fallthrough; 1066 case XDP_DROP: 1067 ndev->stats.rx_dropped++; 1068 } 1069 1070 page = virt_to_head_page(xdp->data); 1071 am65_cpsw_put_page(rx_chn, page, true, desc_idx); 1072 out: 1073 return ret; 1074 } 1075 1076 /* RX psdata[2] word format - checksum information */ 1077 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 1078 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 1079 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 1080 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 1081 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 1082 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 1083 1084 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 1085 { 1086 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 1087 * csum information provides in psdata[2] word: 1088 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 1089 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 1090 * bits - indicates IPv4/IPv6 packet 1091 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 1092 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 1093 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 1094 */ 1095 skb_checksum_none_assert(skb); 1096 1097 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 1098 return; 1099 1100 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 1101 AM65_CPSW_RX_PSD_IPV4_VALID)) && 1102 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 1103 /* csum for fragmented packets is unsupported */ 1104 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 1105 skb->ip_summed = CHECKSUM_UNNECESSARY; 1106 } 1107 } 1108 1109 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 1110 u32 flow_idx, int cpu, int *xdp_state) 1111 { 1112 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1113 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 1114 struct am65_cpsw_ndev_priv *ndev_priv; 1115 struct am65_cpsw_ndev_stats *stats; 1116 struct cppi5_host_desc_t *desc_rx; 1117 struct device *dev = common->dev; 1118 struct page *page, *new_page; 1119 dma_addr_t desc_dma, buf_dma; 1120 struct am65_cpsw_port *port; 1121 int headroom, desc_idx, ret; 1122 struct net_device *ndev; 1123 struct sk_buff *skb; 1124 struct xdp_buff xdp; 1125 void *page_addr; 1126 void **swdata; 1127 u32 *psdata; 1128 1129 *xdp_state = AM65_CPSW_XDP_PASS; 1130 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 1131 if (ret) { 1132 if (ret != -ENODATA) 1133 dev_err(dev, "RX: pop chn fail %d\n", ret); 1134 return ret; 1135 } 1136 1137 if (cppi5_desc_is_tdcm(desc_dma)) { 1138 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 1139 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 1140 complete(&common->tdown_complete); 1141 return 0; 1142 } 1143 1144 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 1145 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 1146 __func__, flow_idx, &desc_dma); 1147 1148 swdata = cppi5_hdesc_get_swdata(desc_rx); 1149 page_addr = *swdata; 1150 page = virt_to_page(page_addr); 1151 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 1152 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 1153 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 1154 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 1155 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 1156 port = am65_common_get_port(common, port_id); 1157 ndev = port->ndev; 1158 psdata = cppi5_hdesc_get_psdata(desc_rx); 1159 csum_info = psdata[2]; 1160 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 1161 1162 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 1163 1164 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 1165 1166 desc_idx = am65_cpsw_nuss_desc_idx(rx_chn->desc_pool, desc_rx, 1167 rx_chn->dsize_log2); 1168 1169 skb = am65_cpsw_build_skb(page_addr, ndev, 1170 AM65_CPSW_MAX_PACKET_SIZE); 1171 if (unlikely(!skb)) { 1172 new_page = page; 1173 goto requeue; 1174 } 1175 1176 if (port->xdp_prog) { 1177 xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq); 1178 xdp_prepare_buff(&xdp, page_addr, AM65_CPSW_HEADROOM, 1179 pkt_len, false); 1180 *xdp_state = am65_cpsw_run_xdp(common, port, &xdp, desc_idx, 1181 cpu, &pkt_len); 1182 if (*xdp_state != AM65_CPSW_XDP_PASS) 1183 goto allocate; 1184 1185 /* Compute additional headroom to be reserved */ 1186 headroom = (xdp.data - xdp.data_hard_start) - skb_headroom(skb); 1187 skb_reserve(skb, headroom); 1188 } 1189 1190 ndev_priv = netdev_priv(ndev); 1191 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 1192 skb_put(skb, pkt_len); 1193 if (port->rx_ts_enabled) 1194 am65_cpts_rx_timestamp(common->cpts, skb); 1195 skb_mark_for_recycle(skb); 1196 skb->protocol = eth_type_trans(skb, ndev); 1197 am65_cpsw_nuss_rx_csum(skb, csum_info); 1198 napi_gro_receive(&common->napi_rx, skb); 1199 1200 stats = this_cpu_ptr(ndev_priv->stats); 1201 1202 u64_stats_update_begin(&stats->syncp); 1203 stats->rx_packets++; 1204 stats->rx_bytes += pkt_len; 1205 u64_stats_update_end(&stats->syncp); 1206 1207 allocate: 1208 new_page = page_pool_dev_alloc_pages(rx_chn->page_pool); 1209 if (unlikely(!new_page)) { 1210 dev_err(dev, "page alloc failed\n"); 1211 return -ENOMEM; 1212 } 1213 1214 rx_chn->pages[desc_idx] = new_page; 1215 1216 if (netif_dormant(ndev)) { 1217 am65_cpsw_put_page(rx_chn, new_page, true, desc_idx); 1218 ndev->stats.rx_dropped++; 1219 return 0; 1220 } 1221 1222 requeue: 1223 ret = am65_cpsw_nuss_rx_push(common, new_page); 1224 if (WARN_ON(ret < 0)) { 1225 am65_cpsw_put_page(rx_chn, new_page, true, desc_idx); 1226 ndev->stats.rx_errors++; 1227 ndev->stats.rx_dropped++; 1228 } 1229 1230 return ret; 1231 } 1232 1233 static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) 1234 { 1235 struct am65_cpsw_common *common = 1236 container_of(timer, struct am65_cpsw_common, rx_hrtimer); 1237 1238 enable_irq(common->rx_chns.irq); 1239 return HRTIMER_NORESTART; 1240 } 1241 1242 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 1243 { 1244 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 1245 int flow = AM65_CPSW_MAX_RX_FLOWS; 1246 int cpu = smp_processor_id(); 1247 int xdp_state_or = 0; 1248 int cur_budget, ret; 1249 int xdp_state; 1250 int num_rx = 0; 1251 1252 /* process every flow */ 1253 while (flow--) { 1254 cur_budget = budget - num_rx; 1255 1256 while (cur_budget--) { 1257 ret = am65_cpsw_nuss_rx_packets(common, flow, cpu, 1258 &xdp_state); 1259 xdp_state_or |= xdp_state; 1260 if (ret) 1261 break; 1262 num_rx++; 1263 } 1264 1265 if (num_rx >= budget) 1266 break; 1267 } 1268 1269 if (xdp_state_or & AM65_CPSW_XDP_REDIRECT) 1270 xdp_do_flush(); 1271 1272 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 1273 1274 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1275 if (common->rx_irq_disabled) { 1276 common->rx_irq_disabled = false; 1277 if (unlikely(common->rx_pace_timeout)) { 1278 hrtimer_start(&common->rx_hrtimer, 1279 ns_to_ktime(common->rx_pace_timeout), 1280 HRTIMER_MODE_REL_PINNED); 1281 } else { 1282 enable_irq(common->rx_chns.irq); 1283 } 1284 } 1285 } 1286 1287 return num_rx; 1288 } 1289 1290 static struct sk_buff * 1291 am65_cpsw_nuss_tx_compl_packet_skb(struct am65_cpsw_tx_chn *tx_chn, 1292 dma_addr_t desc_dma) 1293 { 1294 struct am65_cpsw_ndev_priv *ndev_priv; 1295 struct am65_cpsw_ndev_stats *stats; 1296 struct cppi5_host_desc_t *desc_tx; 1297 struct net_device *ndev; 1298 struct sk_buff *skb; 1299 void **swdata; 1300 1301 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 1302 desc_dma); 1303 swdata = cppi5_hdesc_get_swdata(desc_tx); 1304 skb = *(swdata); 1305 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1306 1307 ndev = skb->dev; 1308 1309 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 1310 1311 ndev_priv = netdev_priv(ndev); 1312 stats = this_cpu_ptr(ndev_priv->stats); 1313 u64_stats_update_begin(&stats->syncp); 1314 stats->tx_packets++; 1315 stats->tx_bytes += skb->len; 1316 u64_stats_update_end(&stats->syncp); 1317 1318 return skb; 1319 } 1320 1321 static struct xdp_frame * 1322 am65_cpsw_nuss_tx_compl_packet_xdp(struct am65_cpsw_common *common, 1323 struct am65_cpsw_tx_chn *tx_chn, 1324 dma_addr_t desc_dma, 1325 struct net_device **ndev) 1326 { 1327 struct am65_cpsw_ndev_priv *ndev_priv; 1328 struct am65_cpsw_ndev_stats *stats; 1329 struct cppi5_host_desc_t *desc_tx; 1330 struct am65_cpsw_port *port; 1331 struct xdp_frame *xdpf; 1332 u32 port_id = 0; 1333 void **swdata; 1334 1335 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 1336 cppi5_desc_get_tags_ids(&desc_tx->hdr, NULL, &port_id); 1337 swdata = cppi5_hdesc_get_swdata(desc_tx); 1338 xdpf = *(swdata); 1339 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1340 1341 port = am65_common_get_port(common, port_id); 1342 *ndev = port->ndev; 1343 1344 ndev_priv = netdev_priv(*ndev); 1345 stats = this_cpu_ptr(ndev_priv->stats); 1346 u64_stats_update_begin(&stats->syncp); 1347 stats->tx_packets++; 1348 stats->tx_bytes += xdpf->len; 1349 u64_stats_update_end(&stats->syncp); 1350 1351 return xdpf; 1352 } 1353 1354 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 1355 struct netdev_queue *netif_txq) 1356 { 1357 if (netif_tx_queue_stopped(netif_txq)) { 1358 /* Check whether the queue is stopped due to stalled 1359 * tx dma, if the queue is stopped then wake the queue 1360 * as we have free desc for tx 1361 */ 1362 __netif_tx_lock(netif_txq, smp_processor_id()); 1363 if (netif_running(ndev) && 1364 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 1365 netif_tx_wake_queue(netif_txq); 1366 1367 __netif_tx_unlock(netif_txq); 1368 } 1369 } 1370 1371 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 1372 int chn, unsigned int budget, bool *tdown) 1373 { 1374 enum am65_cpsw_tx_buf_type buf_type; 1375 struct device *dev = common->dev; 1376 struct am65_cpsw_tx_chn *tx_chn; 1377 struct netdev_queue *netif_txq; 1378 unsigned int total_bytes = 0; 1379 struct net_device *ndev; 1380 struct xdp_frame *xdpf; 1381 struct sk_buff *skb; 1382 dma_addr_t desc_dma; 1383 int res, num_tx = 0; 1384 1385 tx_chn = &common->tx_chns[chn]; 1386 1387 while (true) { 1388 spin_lock(&tx_chn->lock); 1389 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1390 spin_unlock(&tx_chn->lock); 1391 if (res == -ENODATA) 1392 break; 1393 1394 if (cppi5_desc_is_tdcm(desc_dma)) { 1395 if (atomic_dec_and_test(&common->tdown_cnt)) 1396 complete(&common->tdown_complete); 1397 *tdown = true; 1398 break; 1399 } 1400 1401 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1402 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1403 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1404 ndev = skb->dev; 1405 total_bytes = skb->len; 1406 napi_consume_skb(skb, budget); 1407 } else { 1408 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1409 desc_dma, &ndev); 1410 total_bytes = xdpf->len; 1411 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1412 xdp_return_frame_rx_napi(xdpf); 1413 else 1414 xdp_return_frame(xdpf); 1415 } 1416 num_tx++; 1417 1418 netif_txq = netdev_get_tx_queue(ndev, chn); 1419 1420 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1421 1422 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1423 } 1424 1425 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1426 1427 return num_tx; 1428 } 1429 1430 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 1431 int chn, unsigned int budget, bool *tdown) 1432 { 1433 enum am65_cpsw_tx_buf_type buf_type; 1434 struct device *dev = common->dev; 1435 struct am65_cpsw_tx_chn *tx_chn; 1436 struct netdev_queue *netif_txq; 1437 unsigned int total_bytes = 0; 1438 struct net_device *ndev; 1439 struct xdp_frame *xdpf; 1440 struct sk_buff *skb; 1441 dma_addr_t desc_dma; 1442 int res, num_tx = 0; 1443 1444 tx_chn = &common->tx_chns[chn]; 1445 1446 while (true) { 1447 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1448 if (res == -ENODATA) 1449 break; 1450 1451 if (cppi5_desc_is_tdcm(desc_dma)) { 1452 if (atomic_dec_and_test(&common->tdown_cnt)) 1453 complete(&common->tdown_complete); 1454 *tdown = true; 1455 break; 1456 } 1457 1458 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1459 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1460 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1461 ndev = skb->dev; 1462 total_bytes += skb->len; 1463 napi_consume_skb(skb, budget); 1464 } else { 1465 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1466 desc_dma, &ndev); 1467 total_bytes += xdpf->len; 1468 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1469 xdp_return_frame_rx_napi(xdpf); 1470 else 1471 xdp_return_frame(xdpf); 1472 } 1473 num_tx++; 1474 } 1475 1476 if (!num_tx) 1477 return 0; 1478 1479 netif_txq = netdev_get_tx_queue(ndev, chn); 1480 1481 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1482 1483 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1484 1485 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1486 1487 return num_tx; 1488 } 1489 1490 static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer) 1491 { 1492 struct am65_cpsw_tx_chn *tx_chns = 1493 container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer); 1494 1495 enable_irq(tx_chns->irq); 1496 return HRTIMER_NORESTART; 1497 } 1498 1499 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1500 { 1501 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1502 bool tdown = false; 1503 int num_tx; 1504 1505 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1506 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, 1507 budget, &tdown); 1508 else 1509 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, 1510 tx_chn->id, budget, &tdown); 1511 1512 if (num_tx >= budget) 1513 return budget; 1514 1515 if (napi_complete_done(napi_tx, num_tx)) { 1516 if (unlikely(tx_chn->tx_pace_timeout && !tdown)) { 1517 hrtimer_start(&tx_chn->tx_hrtimer, 1518 ns_to_ktime(tx_chn->tx_pace_timeout), 1519 HRTIMER_MODE_REL_PINNED); 1520 } else { 1521 enable_irq(tx_chn->irq); 1522 } 1523 } 1524 1525 return 0; 1526 } 1527 1528 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1529 { 1530 struct am65_cpsw_common *common = dev_id; 1531 1532 common->rx_irq_disabled = true; 1533 disable_irq_nosync(irq); 1534 napi_schedule(&common->napi_rx); 1535 1536 return IRQ_HANDLED; 1537 } 1538 1539 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1540 { 1541 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1542 1543 disable_irq_nosync(irq); 1544 napi_schedule(&tx_chn->napi_tx); 1545 1546 return IRQ_HANDLED; 1547 } 1548 1549 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1550 struct net_device *ndev) 1551 { 1552 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1553 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1554 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1555 struct device *dev = common->dev; 1556 struct am65_cpsw_tx_chn *tx_chn; 1557 struct netdev_queue *netif_txq; 1558 dma_addr_t desc_dma, buf_dma; 1559 int ret, q_idx, i; 1560 void **swdata; 1561 u32 *psdata; 1562 u32 pkt_len; 1563 1564 /* padding enabled in hw */ 1565 pkt_len = skb_headlen(skb); 1566 1567 /* SKB TX timestamp */ 1568 if (port->tx_ts_enabled) 1569 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1570 1571 q_idx = skb_get_queue_mapping(skb); 1572 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1573 1574 tx_chn = &common->tx_chns[q_idx]; 1575 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1576 1577 /* Map the linear buffer */ 1578 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1579 DMA_TO_DEVICE); 1580 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1581 dev_err(dev, "Failed to map tx skb buffer\n"); 1582 ndev->stats.tx_errors++; 1583 goto err_free_skb; 1584 } 1585 1586 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1587 if (!first_desc) { 1588 dev_dbg(dev, "Failed to allocate descriptor\n"); 1589 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1590 DMA_TO_DEVICE); 1591 goto busy_stop_q; 1592 } 1593 1594 am65_cpsw_nuss_set_buf_type(tx_chn, first_desc, 1595 AM65_CPSW_TX_BUF_TYPE_SKB); 1596 1597 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1598 AM65_CPSW_NAV_PS_DATA_SIZE); 1599 cppi5_desc_set_pktids(&first_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1600 cppi5_hdesc_set_pkttype(first_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1601 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1602 1603 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1604 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1605 swdata = cppi5_hdesc_get_swdata(first_desc); 1606 *(swdata) = skb; 1607 psdata = cppi5_hdesc_get_psdata(first_desc); 1608 1609 /* HW csum offload if enabled */ 1610 psdata[2] = 0; 1611 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1612 unsigned int cs_start, cs_offset; 1613 1614 cs_start = skb_transport_offset(skb); 1615 cs_offset = cs_start + skb->csum_offset; 1616 /* HW numerates bytes starting from 1 */ 1617 psdata[2] = ((cs_offset + 1) << 24) | 1618 ((cs_start + 1) << 16) | (skb->len - cs_start); 1619 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1620 } 1621 1622 if (!skb_is_nonlinear(skb)) 1623 goto done_tx; 1624 1625 dev_dbg(dev, "fragmented SKB\n"); 1626 1627 /* Handle the case where skb is fragmented in pages */ 1628 cur_desc = first_desc; 1629 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1630 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1631 u32 frag_size = skb_frag_size(frag); 1632 1633 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1634 if (!next_desc) { 1635 dev_err(dev, "Failed to allocate descriptor\n"); 1636 goto busy_free_descs; 1637 } 1638 1639 am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, 1640 AM65_CPSW_TX_BUF_TYPE_SKB); 1641 1642 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1643 DMA_TO_DEVICE); 1644 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1645 dev_err(dev, "Failed to map tx skb page\n"); 1646 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1647 ndev->stats.tx_errors++; 1648 goto err_free_descs; 1649 } 1650 1651 cppi5_hdesc_reset_hbdesc(next_desc); 1652 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1653 cppi5_hdesc_attach_buf(next_desc, 1654 buf_dma, frag_size, buf_dma, frag_size); 1655 1656 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1657 next_desc); 1658 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1659 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1660 1661 pkt_len += frag_size; 1662 cur_desc = next_desc; 1663 } 1664 WARN_ON(pkt_len != skb->len); 1665 1666 done_tx: 1667 skb_tx_timestamp(skb); 1668 1669 /* report bql before sending packet */ 1670 netdev_tx_sent_queue(netif_txq, pkt_len); 1671 1672 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1673 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1674 if (AM65_CPSW_IS_CPSW2G(common)) { 1675 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1676 } else { 1677 spin_lock_bh(&tx_chn->lock); 1678 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1679 spin_unlock_bh(&tx_chn->lock); 1680 } 1681 if (ret) { 1682 dev_err(dev, "can't push desc %d\n", ret); 1683 /* inform bql */ 1684 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1685 ndev->stats.tx_errors++; 1686 goto err_free_descs; 1687 } 1688 1689 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1690 netif_tx_stop_queue(netif_txq); 1691 /* Barrier, so that stop_queue visible to other cpus */ 1692 smp_mb__after_atomic(); 1693 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1694 1695 /* re-check for smp */ 1696 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1697 MAX_SKB_FRAGS) { 1698 netif_tx_wake_queue(netif_txq); 1699 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1700 } 1701 } 1702 1703 return NETDEV_TX_OK; 1704 1705 err_free_descs: 1706 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1707 err_free_skb: 1708 ndev->stats.tx_dropped++; 1709 dev_kfree_skb_any(skb); 1710 return NETDEV_TX_OK; 1711 1712 busy_free_descs: 1713 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1714 busy_stop_q: 1715 netif_tx_stop_queue(netif_txq); 1716 return NETDEV_TX_BUSY; 1717 } 1718 1719 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1720 void *addr) 1721 { 1722 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1723 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1724 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1725 int ret; 1726 1727 ret = eth_prepare_mac_addr_change(ndev, addr); 1728 if (ret < 0) 1729 return ret; 1730 1731 ret = pm_runtime_resume_and_get(common->dev); 1732 if (ret < 0) 1733 return ret; 1734 1735 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1736 HOST_PORT_NUM, 0, 0); 1737 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1738 HOST_PORT_NUM, ALE_SECURE, 0); 1739 1740 am65_cpsw_port_set_sl_mac(port, addr); 1741 eth_commit_mac_addr_change(ndev, sockaddr); 1742 1743 pm_runtime_put(common->dev); 1744 1745 return 0; 1746 } 1747 1748 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1749 struct ifreq *ifr) 1750 { 1751 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1752 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1753 struct hwtstamp_config cfg; 1754 1755 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1756 return -EOPNOTSUPP; 1757 1758 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1759 return -EFAULT; 1760 1761 /* TX HW timestamp */ 1762 switch (cfg.tx_type) { 1763 case HWTSTAMP_TX_OFF: 1764 case HWTSTAMP_TX_ON: 1765 break; 1766 default: 1767 return -ERANGE; 1768 } 1769 1770 switch (cfg.rx_filter) { 1771 case HWTSTAMP_FILTER_NONE: 1772 port->rx_ts_enabled = false; 1773 break; 1774 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1775 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1776 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1777 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1778 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1779 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1780 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1781 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1782 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1783 port->rx_ts_enabled = true; 1784 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1785 break; 1786 case HWTSTAMP_FILTER_ALL: 1787 case HWTSTAMP_FILTER_SOME: 1788 case HWTSTAMP_FILTER_NTP_ALL: 1789 return -EOPNOTSUPP; 1790 default: 1791 return -ERANGE; 1792 } 1793 1794 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1795 1796 /* cfg TX timestamp */ 1797 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1798 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1799 1800 ts_vlan_ltype = ETH_P_8021Q; 1801 1802 ts_ctrl_ltype2 = ETH_P_1588 | 1803 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1804 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1805 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1806 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1807 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1808 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1809 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1810 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1811 1812 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1813 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1814 1815 if (port->tx_ts_enabled) 1816 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1817 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1818 1819 if (port->rx_ts_enabled) 1820 ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN | 1821 AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN; 1822 1823 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1824 writel(ts_vlan_ltype, port->port_base + 1825 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1826 writel(ts_ctrl_ltype2, port->port_base + 1827 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1828 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1829 1830 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1831 } 1832 1833 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1834 struct ifreq *ifr) 1835 { 1836 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1837 struct hwtstamp_config cfg; 1838 1839 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1840 return -EOPNOTSUPP; 1841 1842 cfg.flags = 0; 1843 cfg.tx_type = port->tx_ts_enabled ? 1844 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1845 cfg.rx_filter = port->rx_ts_enabled ? 1846 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE; 1847 1848 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1849 } 1850 1851 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1852 struct ifreq *req, int cmd) 1853 { 1854 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1855 1856 if (!netif_running(ndev)) 1857 return -EINVAL; 1858 1859 switch (cmd) { 1860 case SIOCSHWTSTAMP: 1861 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1862 case SIOCGHWTSTAMP: 1863 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1864 } 1865 1866 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1867 } 1868 1869 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1870 struct rtnl_link_stats64 *stats) 1871 { 1872 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1873 unsigned int start; 1874 int cpu; 1875 1876 for_each_possible_cpu(cpu) { 1877 struct am65_cpsw_ndev_stats *cpu_stats; 1878 u64 rx_packets; 1879 u64 rx_bytes; 1880 u64 tx_packets; 1881 u64 tx_bytes; 1882 1883 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1884 do { 1885 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1886 rx_packets = cpu_stats->rx_packets; 1887 rx_bytes = cpu_stats->rx_bytes; 1888 tx_packets = cpu_stats->tx_packets; 1889 tx_bytes = cpu_stats->tx_bytes; 1890 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1891 1892 stats->rx_packets += rx_packets; 1893 stats->rx_bytes += rx_bytes; 1894 stats->tx_packets += tx_packets; 1895 stats->tx_bytes += tx_bytes; 1896 } 1897 1898 stats->rx_errors = dev->stats.rx_errors; 1899 stats->rx_dropped = dev->stats.rx_dropped; 1900 stats->tx_dropped = dev->stats.tx_dropped; 1901 } 1902 1903 static int am65_cpsw_xdp_prog_setup(struct net_device *ndev, 1904 struct bpf_prog *prog) 1905 { 1906 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1907 bool running = netif_running(ndev); 1908 struct bpf_prog *old_prog; 1909 1910 if (running) 1911 am65_cpsw_nuss_ndo_slave_stop(ndev); 1912 1913 old_prog = xchg(&port->xdp_prog, prog); 1914 if (old_prog) 1915 bpf_prog_put(old_prog); 1916 1917 if (running) 1918 return am65_cpsw_nuss_ndo_slave_open(ndev); 1919 1920 return 0; 1921 } 1922 1923 static int am65_cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 1924 { 1925 switch (bpf->command) { 1926 case XDP_SETUP_PROG: 1927 return am65_cpsw_xdp_prog_setup(ndev, bpf->prog); 1928 default: 1929 return -EINVAL; 1930 } 1931 } 1932 1933 static int am65_cpsw_ndo_xdp_xmit(struct net_device *ndev, int n, 1934 struct xdp_frame **frames, u32 flags) 1935 { 1936 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1937 struct am65_cpsw_tx_chn *tx_chn; 1938 struct netdev_queue *netif_txq; 1939 int cpu = smp_processor_id(); 1940 int i, nxmit = 0; 1941 1942 tx_chn = &common->tx_chns[cpu % common->tx_ch_num]; 1943 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1944 1945 __netif_tx_lock(netif_txq, cpu); 1946 for (i = 0; i < n; i++) { 1947 if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], 1948 AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) 1949 break; 1950 nxmit++; 1951 } 1952 __netif_tx_unlock(netif_txq); 1953 1954 return nxmit; 1955 } 1956 1957 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1958 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1959 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1960 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1961 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1962 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1963 .ndo_validate_addr = eth_validate_addr, 1964 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1965 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1966 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1967 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1968 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1969 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1970 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 1971 .ndo_bpf = am65_cpsw_ndo_bpf, 1972 .ndo_xdp_xmit = am65_cpsw_ndo_xdp_xmit, 1973 }; 1974 1975 static void am65_cpsw_disable_phy(struct phy *phy) 1976 { 1977 phy_power_off(phy); 1978 phy_exit(phy); 1979 } 1980 1981 static int am65_cpsw_enable_phy(struct phy *phy) 1982 { 1983 int ret; 1984 1985 ret = phy_init(phy); 1986 if (ret < 0) 1987 return ret; 1988 1989 ret = phy_power_on(phy); 1990 if (ret < 0) { 1991 phy_exit(phy); 1992 return ret; 1993 } 1994 1995 return 0; 1996 } 1997 1998 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 1999 { 2000 struct am65_cpsw_port *port; 2001 struct phy *phy; 2002 int i; 2003 2004 for (i = 0; i < common->port_num; i++) { 2005 port = &common->ports[i]; 2006 phy = port->slave.serdes_phy; 2007 if (phy) 2008 am65_cpsw_disable_phy(phy); 2009 } 2010 } 2011 2012 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 2013 struct am65_cpsw_port *port) 2014 { 2015 const char *name = "serdes"; 2016 struct phy *phy; 2017 int ret; 2018 2019 phy = devm_of_phy_optional_get(dev, port_np, name); 2020 if (IS_ERR_OR_NULL(phy)) 2021 return PTR_ERR_OR_ZERO(phy); 2022 2023 /* Serdes PHY exists. Store it. */ 2024 port->slave.serdes_phy = phy; 2025 2026 ret = am65_cpsw_enable_phy(phy); 2027 if (ret < 0) 2028 goto err_phy; 2029 2030 return 0; 2031 2032 err_phy: 2033 devm_phy_put(dev, phy); 2034 return ret; 2035 } 2036 2037 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 2038 const struct phylink_link_state *state) 2039 { 2040 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2041 phylink_config); 2042 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2043 struct am65_cpsw_common *common = port->common; 2044 2045 if (common->pdata.extra_modes & BIT(state->interface)) { 2046 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 2047 writel(ADVERTISE_SGMII, 2048 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 2049 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2050 } else { 2051 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2052 } 2053 2054 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 2055 cpsw_sl_ctl_set(port->slave.mac_sl, 2056 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2057 } else { 2058 cpsw_sl_ctl_clr(port->slave.mac_sl, 2059 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2060 } 2061 2062 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 2063 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 2064 } 2065 } 2066 2067 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 2068 phy_interface_t interface) 2069 { 2070 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2071 phylink_config); 2072 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2073 struct am65_cpsw_common *common = port->common; 2074 struct net_device *ndev = port->ndev; 2075 u32 mac_control; 2076 int tmo; 2077 2078 /* disable forwarding */ 2079 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2080 2081 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2082 2083 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 2084 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 2085 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 2086 2087 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 2088 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 2089 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 2090 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 2091 if (phy_interface_mode_is_rgmii(interface)) 2092 mac_control |= CPSW_SL_CTL_EXT_EN; 2093 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 2094 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 2095 2096 am65_cpsw_qos_link_down(ndev); 2097 netif_tx_stop_all_queues(ndev); 2098 } 2099 2100 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 2101 unsigned int mode, phy_interface_t interface, int speed, 2102 int duplex, bool tx_pause, bool rx_pause) 2103 { 2104 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2105 phylink_config); 2106 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2107 struct am65_cpsw_common *common = port->common; 2108 u32 mac_control = CPSW_SL_CTL_GMII_EN; 2109 struct net_device *ndev = port->ndev; 2110 2111 /* Bring the port out of idle state */ 2112 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2113 2114 if (speed == SPEED_1000) 2115 mac_control |= CPSW_SL_CTL_GIG; 2116 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 2117 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 2118 /* Can be used with in band mode only */ 2119 mac_control |= CPSW_SL_CTL_EXT_EN; 2120 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 2121 mac_control |= CPSW_SL_CTL_IFCTL_A; 2122 if (duplex) 2123 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 2124 2125 /* rx_pause/tx_pause */ 2126 if (rx_pause) 2127 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 2128 2129 if (tx_pause) 2130 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 2131 2132 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 2133 2134 /* enable forwarding */ 2135 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2136 2137 am65_cpsw_qos_link_up(ndev, speed); 2138 netif_tx_wake_all_queues(ndev); 2139 } 2140 2141 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 2142 .mac_config = am65_cpsw_nuss_mac_config, 2143 .mac_link_down = am65_cpsw_nuss_mac_link_down, 2144 .mac_link_up = am65_cpsw_nuss_mac_link_up, 2145 }; 2146 2147 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 2148 { 2149 struct am65_cpsw_common *common = port->common; 2150 2151 if (!port->disabled) 2152 return; 2153 2154 cpsw_ale_control_set(common->ale, port->port_id, 2155 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2156 2157 cpsw_sl_reset(port->slave.mac_sl, 100); 2158 cpsw_sl_ctl_reset(port->slave.mac_sl); 2159 } 2160 2161 static void am65_cpsw_nuss_free_tx_chns(void *data) 2162 { 2163 struct am65_cpsw_common *common = data; 2164 int i; 2165 2166 for (i = 0; i < common->tx_ch_num; i++) { 2167 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2168 2169 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2170 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2171 2172 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2173 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2174 2175 memset(tx_chn, 0, sizeof(*tx_chn)); 2176 } 2177 } 2178 2179 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 2180 { 2181 struct device *dev = common->dev; 2182 int i; 2183 2184 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2185 2186 common->tx_ch_rate_msk = 0; 2187 for (i = 0; i < common->tx_ch_num; i++) { 2188 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2189 2190 if (tx_chn->irq) 2191 devm_free_irq(dev, tx_chn->irq, tx_chn); 2192 2193 netif_napi_del(&tx_chn->napi_tx); 2194 2195 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2196 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2197 2198 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2199 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2200 2201 memset(tx_chn, 0, sizeof(*tx_chn)); 2202 } 2203 } 2204 2205 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2206 { 2207 struct device *dev = common->dev; 2208 int i, ret = 0; 2209 2210 for (i = 0; i < common->tx_ch_num; i++) { 2211 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2212 2213 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2214 am65_cpsw_nuss_tx_poll); 2215 hrtimer_init(&tx_chn->tx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2216 tx_chn->tx_hrtimer.function = &am65_cpsw_nuss_tx_timer_callback; 2217 2218 ret = devm_request_irq(dev, tx_chn->irq, 2219 am65_cpsw_nuss_tx_irq, 2220 IRQF_TRIGGER_HIGH, 2221 tx_chn->tx_chn_name, tx_chn); 2222 if (ret) { 2223 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2224 tx_chn->id, tx_chn->irq, ret); 2225 goto err; 2226 } 2227 } 2228 2229 err: 2230 return ret; 2231 } 2232 2233 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 2234 { 2235 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 2236 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 2237 struct device *dev = common->dev; 2238 struct k3_ring_cfg ring_cfg = { 2239 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2240 .mode = K3_RINGACC_RING_MODE_RING, 2241 .flags = 0 2242 }; 2243 u32 hdesc_size, hdesc_size_out; 2244 int i, ret = 0; 2245 2246 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2247 AM65_CPSW_NAV_SW_DATA_SIZE); 2248 2249 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2250 tx_cfg.tx_cfg = ring_cfg; 2251 tx_cfg.txcq_cfg = ring_cfg; 2252 tx_cfg.tx_cfg.size = max_desc_num; 2253 tx_cfg.txcq_cfg.size = max_desc_num; 2254 2255 for (i = 0; i < common->tx_ch_num; i++) { 2256 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2257 2258 snprintf(tx_chn->tx_chn_name, 2259 sizeof(tx_chn->tx_chn_name), "tx%d", i); 2260 2261 spin_lock_init(&tx_chn->lock); 2262 tx_chn->common = common; 2263 tx_chn->id = i; 2264 tx_chn->descs_num = max_desc_num; 2265 2266 tx_chn->tx_chn = 2267 k3_udma_glue_request_tx_chn(dev, 2268 tx_chn->tx_chn_name, 2269 &tx_cfg); 2270 if (IS_ERR(tx_chn->tx_chn)) { 2271 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 2272 "Failed to request tx dma channel\n"); 2273 goto err; 2274 } 2275 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 2276 2277 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 2278 tx_chn->descs_num, 2279 hdesc_size, 2280 tx_chn->tx_chn_name); 2281 if (IS_ERR(tx_chn->desc_pool)) { 2282 ret = PTR_ERR(tx_chn->desc_pool); 2283 dev_err(dev, "Failed to create poll %d\n", ret); 2284 goto err; 2285 } 2286 2287 hdesc_size_out = k3_cppi_desc_pool_desc_size(tx_chn->desc_pool); 2288 tx_chn->dsize_log2 = __fls(hdesc_size_out); 2289 WARN_ON(hdesc_size_out != (1 << tx_chn->dsize_log2)); 2290 2291 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 2292 if (tx_chn->irq < 0) { 2293 dev_err(dev, "Failed to get tx dma irq %d\n", 2294 tx_chn->irq); 2295 ret = tx_chn->irq; 2296 goto err; 2297 } 2298 2299 snprintf(tx_chn->tx_chn_name, 2300 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 2301 dev_name(dev), tx_chn->id); 2302 } 2303 2304 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2305 if (ret) { 2306 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 2307 goto err; 2308 } 2309 2310 err: 2311 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2312 if (i) { 2313 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 2314 return i; 2315 } 2316 2317 return ret; 2318 } 2319 2320 static void am65_cpsw_nuss_free_rx_chns(void *data) 2321 { 2322 struct am65_cpsw_common *common = data; 2323 struct am65_cpsw_rx_chn *rx_chn; 2324 2325 rx_chn = &common->rx_chns; 2326 2327 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 2328 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 2329 2330 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 2331 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 2332 } 2333 2334 static void am65_cpsw_nuss_remove_rx_chns(void *data) 2335 { 2336 struct am65_cpsw_common *common = data; 2337 struct device *dev = common->dev; 2338 struct am65_cpsw_rx_chn *rx_chn; 2339 2340 rx_chn = &common->rx_chns; 2341 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2342 2343 if (!(rx_chn->irq < 0)) 2344 devm_free_irq(dev, rx_chn->irq, common); 2345 2346 netif_napi_del(&common->napi_rx); 2347 2348 am65_cpsw_nuss_free_rx_chns(common); 2349 2350 common->rx_flow_id_base = -1; 2351 } 2352 2353 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 2354 { 2355 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 2356 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 2357 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 2358 struct device *dev = common->dev; 2359 u32 hdesc_size, hdesc_size_out; 2360 u32 fdqring_id; 2361 int i, ret = 0; 2362 2363 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2364 AM65_CPSW_NAV_SW_DATA_SIZE); 2365 2366 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2367 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 2368 rx_cfg.flow_id_base = common->rx_flow_id_base; 2369 2370 /* init all flows */ 2371 rx_chn->dev = dev; 2372 rx_chn->descs_num = max_desc_num; 2373 2374 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 2375 if (IS_ERR(rx_chn->rx_chn)) { 2376 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 2377 "Failed to request rx dma channel\n"); 2378 goto err; 2379 } 2380 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 2381 2382 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 2383 rx_chn->descs_num, 2384 hdesc_size, "rx"); 2385 if (IS_ERR(rx_chn->desc_pool)) { 2386 ret = PTR_ERR(rx_chn->desc_pool); 2387 dev_err(dev, "Failed to create rx poll %d\n", ret); 2388 goto err; 2389 } 2390 2391 hdesc_size_out = k3_cppi_desc_pool_desc_size(rx_chn->desc_pool); 2392 rx_chn->dsize_log2 = __fls(hdesc_size_out); 2393 WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); 2394 2395 rx_chn->page_pool = NULL; 2396 2397 rx_chn->pages = devm_kcalloc(dev, rx_chn->descs_num, 2398 sizeof(*rx_chn->pages), GFP_KERNEL); 2399 if (!rx_chn->pages) 2400 return -ENOMEM; 2401 2402 common->rx_flow_id_base = 2403 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 2404 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 2405 2406 fdqring_id = K3_RINGACC_RING_ID_ANY; 2407 for (i = 0; i < rx_cfg.flow_id_num; i++) { 2408 struct k3_ring_cfg rxring_cfg = { 2409 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2410 .mode = K3_RINGACC_RING_MODE_RING, 2411 .flags = 0, 2412 }; 2413 struct k3_ring_cfg fdqring_cfg = { 2414 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2415 .flags = K3_RINGACC_RING_SHARED, 2416 }; 2417 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 2418 .rx_cfg = rxring_cfg, 2419 .rxfdq_cfg = fdqring_cfg, 2420 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 2421 .src_tag_lo_sel = 2422 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 2423 }; 2424 2425 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 2426 rx_flow_cfg.rx_cfg.size = max_desc_num; 2427 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 2428 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 2429 2430 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 2431 i, &rx_flow_cfg); 2432 if (ret) { 2433 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 2434 goto err; 2435 } 2436 if (!i) 2437 fdqring_id = 2438 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 2439 i); 2440 2441 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 2442 2443 if (rx_chn->irq < 0) { 2444 dev_err(dev, "Failed to get rx dma irq %d\n", 2445 rx_chn->irq); 2446 ret = rx_chn->irq; 2447 goto err; 2448 } 2449 } 2450 2451 netif_napi_add(common->dma_ndev, &common->napi_rx, 2452 am65_cpsw_nuss_rx_poll); 2453 hrtimer_init(&common->rx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2454 common->rx_hrtimer.function = &am65_cpsw_nuss_rx_timer_callback; 2455 2456 ret = devm_request_irq(dev, rx_chn->irq, 2457 am65_cpsw_nuss_rx_irq, 2458 IRQF_TRIGGER_HIGH, dev_name(dev), common); 2459 if (ret) { 2460 dev_err(dev, "failure requesting rx irq %u, %d\n", 2461 rx_chn->irq, ret); 2462 goto err; 2463 } 2464 2465 err: 2466 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2467 if (i) { 2468 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 2469 return i; 2470 } 2471 2472 return ret; 2473 } 2474 2475 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 2476 { 2477 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2478 2479 host_p->common = common; 2480 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 2481 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 2482 2483 return 0; 2484 } 2485 2486 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 2487 int slave, u8 *mac_addr) 2488 { 2489 u32 mac_lo, mac_hi, offset; 2490 struct regmap *syscon; 2491 int ret; 2492 2493 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 2494 if (IS_ERR(syscon)) { 2495 if (PTR_ERR(syscon) == -ENODEV) 2496 return 0; 2497 return PTR_ERR(syscon); 2498 } 2499 2500 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 2501 &offset); 2502 if (ret) 2503 return ret; 2504 2505 regmap_read(syscon, offset, &mac_lo); 2506 regmap_read(syscon, offset + 4, &mac_hi); 2507 2508 mac_addr[0] = (mac_hi >> 8) & 0xff; 2509 mac_addr[1] = mac_hi & 0xff; 2510 mac_addr[2] = (mac_lo >> 24) & 0xff; 2511 mac_addr[3] = (mac_lo >> 16) & 0xff; 2512 mac_addr[4] = (mac_lo >> 8) & 0xff; 2513 mac_addr[5] = mac_lo & 0xff; 2514 2515 return 0; 2516 } 2517 2518 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 2519 { 2520 struct device *dev = common->dev; 2521 struct device_node *node; 2522 struct am65_cpts *cpts; 2523 void __iomem *reg_base; 2524 2525 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 2526 return 0; 2527 2528 node = of_get_child_by_name(dev->of_node, "cpts"); 2529 if (!node) { 2530 dev_err(dev, "%s cpts not found\n", __func__); 2531 return -ENOENT; 2532 } 2533 2534 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 2535 cpts = am65_cpts_create(dev, reg_base, node); 2536 if (IS_ERR(cpts)) { 2537 int ret = PTR_ERR(cpts); 2538 2539 of_node_put(node); 2540 dev_err(dev, "cpts create err %d\n", ret); 2541 return ret; 2542 } 2543 common->cpts = cpts; 2544 /* Forbid PM runtime if CPTS is running. 2545 * K3 CPSWxG modules may completely lose context during ON->OFF 2546 * transitions depending on integration. 2547 * AM65x/J721E MCU CPSW2G: false 2548 * J721E MAIN_CPSW9G: true 2549 */ 2550 pm_runtime_forbid(dev); 2551 2552 return 0; 2553 } 2554 2555 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2556 { 2557 struct device_node *node, *port_np; 2558 struct device *dev = common->dev; 2559 int ret; 2560 2561 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2562 if (!node) 2563 return -ENOENT; 2564 2565 for_each_child_of_node(node, port_np) { 2566 struct am65_cpsw_port *port; 2567 u32 port_id; 2568 2569 /* it is not a slave port node, continue */ 2570 if (strcmp(port_np->name, "port")) 2571 continue; 2572 2573 ret = of_property_read_u32(port_np, "reg", &port_id); 2574 if (ret < 0) { 2575 dev_err(dev, "%pOF error reading port_id %d\n", 2576 port_np, ret); 2577 goto of_node_put; 2578 } 2579 2580 if (!port_id || port_id > common->port_num) { 2581 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2582 port_np, port_id, port_np->name); 2583 ret = -EINVAL; 2584 goto of_node_put; 2585 } 2586 2587 port = am65_common_get_port(common, port_id); 2588 port->port_id = port_id; 2589 port->common = common; 2590 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2591 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2592 if (common->pdata.extra_modes) 2593 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2594 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2595 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2596 port->name = of_get_property(port_np, "label", NULL); 2597 port->fetch_ram_base = 2598 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2599 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2600 2601 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2602 if (IS_ERR(port->slave.mac_sl)) { 2603 ret = PTR_ERR(port->slave.mac_sl); 2604 goto of_node_put; 2605 } 2606 2607 port->disabled = !of_device_is_available(port_np); 2608 if (port->disabled) { 2609 common->disabled_ports_mask |= BIT(port->port_id); 2610 continue; 2611 } 2612 2613 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2614 if (IS_ERR(port->slave.ifphy)) { 2615 ret = PTR_ERR(port->slave.ifphy); 2616 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2617 port_np, ret); 2618 goto of_node_put; 2619 } 2620 2621 /* Initialize the Serdes PHY for the port */ 2622 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2623 if (ret) 2624 goto of_node_put; 2625 2626 port->slave.mac_only = 2627 of_property_read_bool(port_np, "ti,mac-only"); 2628 2629 /* get phy/link info */ 2630 port->slave.port_np = port_np; 2631 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2632 if (ret) { 2633 dev_err(dev, "%pOF read phy-mode err %d\n", 2634 port_np, ret); 2635 goto of_node_put; 2636 } 2637 2638 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2639 if (ret) 2640 goto of_node_put; 2641 2642 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2643 if (ret) { 2644 am65_cpsw_am654_get_efuse_macid(port_np, 2645 port->port_id, 2646 port->slave.mac_addr); 2647 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2648 eth_random_addr(port->slave.mac_addr); 2649 dev_err(dev, "Use random MAC address\n"); 2650 } 2651 } 2652 2653 /* Reset all Queue priorities to 0 */ 2654 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); 2655 } 2656 of_node_put(node); 2657 2658 /* is there at least one ext.port */ 2659 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2660 dev_err(dev, "No Ext. port are available\n"); 2661 return -ENODEV; 2662 } 2663 2664 return 0; 2665 2666 of_node_put: 2667 of_node_put(port_np); 2668 of_node_put(node); 2669 return ret; 2670 } 2671 2672 static void am65_cpsw_pcpu_stats_free(void *data) 2673 { 2674 struct am65_cpsw_ndev_stats __percpu *stats = data; 2675 2676 free_percpu(stats); 2677 } 2678 2679 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2680 { 2681 struct am65_cpsw_port *port; 2682 int i; 2683 2684 for (i = 0; i < common->port_num; i++) { 2685 port = &common->ports[i]; 2686 if (port->slave.phylink) 2687 phylink_destroy(port->slave.phylink); 2688 } 2689 } 2690 2691 static int 2692 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2693 { 2694 struct am65_cpsw_ndev_priv *ndev_priv; 2695 struct device *dev = common->dev; 2696 struct am65_cpsw_port *port; 2697 struct phylink *phylink; 2698 int ret; 2699 2700 port = &common->ports[port_idx]; 2701 2702 if (port->disabled) 2703 return 0; 2704 2705 /* alloc netdev */ 2706 port->ndev = devm_alloc_etherdev_mqs(common->dev, 2707 sizeof(struct am65_cpsw_ndev_priv), 2708 AM65_CPSW_MAX_TX_QUEUES, 2709 AM65_CPSW_MAX_RX_QUEUES); 2710 if (!port->ndev) { 2711 dev_err(dev, "error allocating slave net_device %u\n", 2712 port->port_id); 2713 return -ENOMEM; 2714 } 2715 2716 ndev_priv = netdev_priv(port->ndev); 2717 ndev_priv->port = port; 2718 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2719 mutex_init(&ndev_priv->mm_lock); 2720 port->qos.link_speed = SPEED_UNKNOWN; 2721 SET_NETDEV_DEV(port->ndev, dev); 2722 port->ndev->dev.of_node = port->slave.port_np; 2723 2724 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2725 2726 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2727 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE - 2728 (VLAN_ETH_HLEN + ETH_FCS_LEN); 2729 port->ndev->hw_features = NETIF_F_SG | 2730 NETIF_F_RXCSUM | 2731 NETIF_F_HW_CSUM | 2732 NETIF_F_HW_TC; 2733 port->ndev->features = port->ndev->hw_features | 2734 NETIF_F_HW_VLAN_CTAG_FILTER; 2735 port->ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 2736 NETDEV_XDP_ACT_REDIRECT | 2737 NETDEV_XDP_ACT_NDO_XMIT; 2738 port->ndev->vlan_features |= NETIF_F_SG; 2739 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2740 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2741 2742 /* Configuring Phylink */ 2743 port->slave.phylink_config.dev = &port->ndev->dev; 2744 port->slave.phylink_config.type = PHYLINK_NETDEV; 2745 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2746 MAC_1000FD | MAC_5000FD; 2747 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2748 2749 switch (port->slave.phy_if) { 2750 case PHY_INTERFACE_MODE_RGMII: 2751 case PHY_INTERFACE_MODE_RGMII_ID: 2752 case PHY_INTERFACE_MODE_RGMII_RXID: 2753 case PHY_INTERFACE_MODE_RGMII_TXID: 2754 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2755 break; 2756 2757 case PHY_INTERFACE_MODE_RMII: 2758 __set_bit(PHY_INTERFACE_MODE_RMII, 2759 port->slave.phylink_config.supported_interfaces); 2760 break; 2761 2762 case PHY_INTERFACE_MODE_QSGMII: 2763 case PHY_INTERFACE_MODE_SGMII: 2764 case PHY_INTERFACE_MODE_USXGMII: 2765 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2766 __set_bit(port->slave.phy_if, 2767 port->slave.phylink_config.supported_interfaces); 2768 } else { 2769 dev_err(dev, "selected phy-mode is not supported\n"); 2770 return -EOPNOTSUPP; 2771 } 2772 break; 2773 2774 default: 2775 dev_err(dev, "selected phy-mode is not supported\n"); 2776 return -EOPNOTSUPP; 2777 } 2778 2779 phylink = phylink_create(&port->slave.phylink_config, 2780 of_node_to_fwnode(port->slave.port_np), 2781 port->slave.phy_if, 2782 &am65_cpsw_phylink_mac_ops); 2783 if (IS_ERR(phylink)) 2784 return PTR_ERR(phylink); 2785 2786 port->slave.phylink = phylink; 2787 2788 /* Disable TX checksum offload by default due to HW bug */ 2789 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2790 port->ndev->features &= ~NETIF_F_HW_CSUM; 2791 2792 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2793 if (!ndev_priv->stats) 2794 return -ENOMEM; 2795 2796 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2797 ndev_priv->stats); 2798 if (ret) 2799 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2800 2801 port->xdp_prog = NULL; 2802 2803 if (!common->dma_ndev) 2804 common->dma_ndev = port->ndev; 2805 2806 return ret; 2807 } 2808 2809 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2810 { 2811 int ret; 2812 int i; 2813 2814 for (i = 0; i < common->port_num; i++) { 2815 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2816 if (ret) 2817 return ret; 2818 } 2819 2820 return ret; 2821 } 2822 2823 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2824 { 2825 struct am65_cpsw_port *port; 2826 int i; 2827 2828 for (i = 0; i < common->port_num; i++) { 2829 port = &common->ports[i]; 2830 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED) 2831 unregister_netdev(port->ndev); 2832 } 2833 } 2834 2835 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2836 { 2837 int set_val = 0; 2838 int i; 2839 2840 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2841 set_val = 1; 2842 2843 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2844 2845 for (i = 1; i <= common->port_num; i++) { 2846 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2847 struct am65_cpsw_ndev_priv *priv; 2848 2849 if (!port->ndev) 2850 continue; 2851 2852 priv = am65_ndev_to_priv(port->ndev); 2853 priv->offload_fwd_mark = set_val; 2854 } 2855 } 2856 2857 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2858 { 2859 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2860 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2861 2862 return !common->is_emac_mode; 2863 } 2864 2865 return false; 2866 } 2867 2868 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2869 struct net_device *br_ndev, 2870 struct netlink_ext_ack *extack) 2871 { 2872 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2873 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2874 int err; 2875 2876 if (!common->br_members) { 2877 common->hw_bridge_dev = br_ndev; 2878 } else { 2879 /* This is adding the port to a second bridge, this is 2880 * unsupported 2881 */ 2882 if (common->hw_bridge_dev != br_ndev) 2883 return -EOPNOTSUPP; 2884 } 2885 2886 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2887 false, extack); 2888 if (err) 2889 return err; 2890 2891 common->br_members |= BIT(priv->port->port_id); 2892 2893 am65_cpsw_port_offload_fwd_mark_update(common); 2894 2895 return NOTIFY_DONE; 2896 } 2897 2898 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2899 { 2900 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2901 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2902 2903 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2904 2905 common->br_members &= ~BIT(priv->port->port_id); 2906 2907 am65_cpsw_port_offload_fwd_mark_update(common); 2908 2909 if (!common->br_members) 2910 common->hw_bridge_dev = NULL; 2911 } 2912 2913 /* netdev notifier */ 2914 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2915 unsigned long event, void *ptr) 2916 { 2917 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2918 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2919 struct netdev_notifier_changeupper_info *info; 2920 int ret = NOTIFY_DONE; 2921 2922 if (!am65_cpsw_port_dev_check(ndev)) 2923 return NOTIFY_DONE; 2924 2925 switch (event) { 2926 case NETDEV_CHANGEUPPER: 2927 info = ptr; 2928 2929 if (netif_is_bridge_master(info->upper_dev)) { 2930 if (info->linking) 2931 ret = am65_cpsw_netdevice_port_link(ndev, 2932 info->upper_dev, 2933 extack); 2934 else 2935 am65_cpsw_netdevice_port_unlink(ndev); 2936 } 2937 break; 2938 default: 2939 return NOTIFY_DONE; 2940 } 2941 2942 return notifier_from_errno(ret); 2943 } 2944 2945 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2946 { 2947 int ret = 0; 2948 2949 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2950 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2951 return 0; 2952 2953 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2954 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2955 if (ret) { 2956 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2957 return ret; 2958 } 2959 2960 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2961 if (ret) 2962 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2963 2964 return ret; 2965 } 2966 2967 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2968 { 2969 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2970 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2971 return; 2972 2973 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2974 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2975 } 2976 2977 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2978 2979 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2980 { 2981 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2982 ALE_MCAST_BLOCK_LEARN_FWD); 2983 } 2984 2985 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2986 { 2987 struct am65_cpsw_host *host = am65_common_get_host(common); 2988 2989 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2990 2991 am65_cpsw_init_stp_ale_entry(common); 2992 2993 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2994 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2995 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2996 } 2997 2998 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2999 { 3000 struct am65_cpsw_host *host = am65_common_get_host(common); 3001 3002 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3003 3004 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 3005 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 3006 3007 /* learning make no sense in multi-mac mode */ 3008 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 3009 } 3010 3011 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 3012 struct devlink_param_gset_ctx *ctx) 3013 { 3014 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3015 struct am65_cpsw_common *common = dl_priv->common; 3016 3017 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 3018 3019 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3020 return -EOPNOTSUPP; 3021 3022 ctx->val.vbool = !common->is_emac_mode; 3023 3024 return 0; 3025 } 3026 3027 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 3028 { 3029 struct am65_cpsw_slave_data *slave = &port->slave; 3030 struct am65_cpsw_common *common = port->common; 3031 u32 port_mask; 3032 3033 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3034 3035 if (slave->mac_only) 3036 /* enable mac-only mode on port */ 3037 cpsw_ale_control_set(common->ale, port->port_id, 3038 ALE_PORT_MACONLY, 1); 3039 3040 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 3041 3042 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3043 3044 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 3045 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 3046 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 3047 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 3048 } 3049 3050 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 3051 { 3052 struct am65_cpsw_slave_data *slave = &port->slave; 3053 struct am65_cpsw_common *cpsw = port->common; 3054 u32 port_mask; 3055 3056 cpsw_ale_control_set(cpsw->ale, port->port_id, 3057 ALE_PORT_NOLEARN, 0); 3058 3059 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 3060 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 3061 slave->port_vlan); 3062 3063 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3064 3065 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 3066 port_mask, ALE_VLAN, slave->port_vlan, 3067 ALE_MCAST_FWD_2); 3068 3069 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3070 3071 cpsw_ale_control_set(cpsw->ale, port->port_id, 3072 ALE_PORT_MACONLY, 0); 3073 } 3074 3075 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 3076 struct devlink_param_gset_ctx *ctx, 3077 struct netlink_ext_ack *extack) 3078 { 3079 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3080 struct am65_cpsw_common *cpsw = dl_priv->common; 3081 bool switch_en = ctx->val.vbool; 3082 bool if_running = false; 3083 int i; 3084 3085 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 3086 3087 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3088 return -EOPNOTSUPP; 3089 3090 if (switch_en == !cpsw->is_emac_mode) 3091 return 0; 3092 3093 if (!switch_en && cpsw->br_members) { 3094 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 3095 return -EINVAL; 3096 } 3097 3098 rtnl_lock(); 3099 3100 cpsw->is_emac_mode = !switch_en; 3101 3102 for (i = 0; i < cpsw->port_num; i++) { 3103 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3104 3105 if (!sl_ndev || !netif_running(sl_ndev)) 3106 continue; 3107 3108 if_running = true; 3109 } 3110 3111 if (!if_running) { 3112 /* all ndevs are down */ 3113 for (i = 0; i < cpsw->port_num; i++) { 3114 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3115 struct am65_cpsw_slave_data *slave; 3116 3117 if (!sl_ndev) 3118 continue; 3119 3120 slave = am65_ndev_to_slave(sl_ndev); 3121 if (switch_en) 3122 slave->port_vlan = cpsw->default_vlan; 3123 else 3124 slave->port_vlan = 0; 3125 } 3126 3127 goto exit; 3128 } 3129 3130 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 3131 /* clean up ALE table */ 3132 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 3133 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 3134 3135 if (switch_en) { 3136 dev_info(cpsw->dev, "Enable switch mode\n"); 3137 3138 am65_cpsw_init_host_port_switch(cpsw); 3139 3140 for (i = 0; i < cpsw->port_num; i++) { 3141 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3142 struct am65_cpsw_slave_data *slave; 3143 struct am65_cpsw_port *port; 3144 3145 if (!sl_ndev) 3146 continue; 3147 3148 port = am65_ndev_to_port(sl_ndev); 3149 slave = am65_ndev_to_slave(sl_ndev); 3150 slave->port_vlan = cpsw->default_vlan; 3151 3152 if (netif_running(sl_ndev)) 3153 am65_cpsw_init_port_switch_ale(port); 3154 } 3155 3156 } else { 3157 dev_info(cpsw->dev, "Disable switch mode\n"); 3158 3159 am65_cpsw_init_host_port_emac(cpsw); 3160 3161 for (i = 0; i < cpsw->port_num; i++) { 3162 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3163 struct am65_cpsw_port *port; 3164 3165 if (!sl_ndev) 3166 continue; 3167 3168 port = am65_ndev_to_port(sl_ndev); 3169 port->slave.port_vlan = 0; 3170 if (netif_running(sl_ndev)) 3171 am65_cpsw_init_port_emac_ale(port); 3172 } 3173 } 3174 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 3175 exit: 3176 rtnl_unlock(); 3177 3178 return 0; 3179 } 3180 3181 static const struct devlink_param am65_cpsw_devlink_params[] = { 3182 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 3183 DEVLINK_PARAM_TYPE_BOOL, 3184 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3185 am65_cpsw_dl_switch_mode_get, 3186 am65_cpsw_dl_switch_mode_set, NULL), 3187 }; 3188 3189 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 3190 { 3191 struct devlink_port_attrs attrs = {}; 3192 struct am65_cpsw_devlink *dl_priv; 3193 struct device *dev = common->dev; 3194 struct devlink_port *dl_port; 3195 struct am65_cpsw_port *port; 3196 int ret = 0; 3197 int i; 3198 3199 common->devlink = 3200 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 3201 if (!common->devlink) 3202 return -ENOMEM; 3203 3204 dl_priv = devlink_priv(common->devlink); 3205 dl_priv->common = common; 3206 3207 /* Provide devlink hook to switch mode when multiple external ports 3208 * are present NUSS switchdev driver is enabled. 3209 */ 3210 if (!AM65_CPSW_IS_CPSW2G(common) && 3211 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 3212 ret = devlink_params_register(common->devlink, 3213 am65_cpsw_devlink_params, 3214 ARRAY_SIZE(am65_cpsw_devlink_params)); 3215 if (ret) { 3216 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 3217 goto dl_unreg; 3218 } 3219 } 3220 3221 for (i = 1; i <= common->port_num; i++) { 3222 port = am65_common_get_port(common, i); 3223 dl_port = &port->devlink_port; 3224 3225 if (port->ndev) 3226 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 3227 else 3228 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 3229 attrs.phys.port_number = port->port_id; 3230 attrs.switch_id.id_len = sizeof(resource_size_t); 3231 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 3232 devlink_port_attrs_set(dl_port, &attrs); 3233 3234 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 3235 if (ret) { 3236 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 3237 port->port_id, ret); 3238 goto dl_port_unreg; 3239 } 3240 } 3241 devlink_register(common->devlink); 3242 return ret; 3243 3244 dl_port_unreg: 3245 for (i = i - 1; i >= 1; i--) { 3246 port = am65_common_get_port(common, i); 3247 dl_port = &port->devlink_port; 3248 3249 devlink_port_unregister(dl_port); 3250 } 3251 dl_unreg: 3252 devlink_free(common->devlink); 3253 return ret; 3254 } 3255 3256 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 3257 { 3258 struct devlink_port *dl_port; 3259 struct am65_cpsw_port *port; 3260 int i; 3261 3262 devlink_unregister(common->devlink); 3263 3264 for (i = 1; i <= common->port_num; i++) { 3265 port = am65_common_get_port(common, i); 3266 dl_port = &port->devlink_port; 3267 3268 devlink_port_unregister(dl_port); 3269 } 3270 3271 if (!AM65_CPSW_IS_CPSW2G(common) && 3272 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3273 devlink_params_unregister(common->devlink, 3274 am65_cpsw_devlink_params, 3275 ARRAY_SIZE(am65_cpsw_devlink_params)); 3276 3277 devlink_free(common->devlink); 3278 } 3279 3280 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 3281 { 3282 struct am65_cpsw_rx_chn *rx_chan = &common->rx_chns; 3283 struct am65_cpsw_tx_chn *tx_chan = common->tx_chns; 3284 struct device *dev = common->dev; 3285 struct am65_cpsw_port *port; 3286 int ret = 0, i; 3287 3288 /* init tx channels */ 3289 ret = am65_cpsw_nuss_init_tx_chns(common); 3290 if (ret) 3291 return ret; 3292 ret = am65_cpsw_nuss_init_rx_chns(common); 3293 if (ret) 3294 return ret; 3295 3296 /* The DMA Channels are not guaranteed to be in a clean state. 3297 * Reset and disable them to ensure that they are back to the 3298 * clean state and ready to be used. 3299 */ 3300 for (i = 0; i < common->tx_ch_num; i++) { 3301 k3_udma_glue_reset_tx_chn(tx_chan[i].tx_chn, &tx_chan[i], 3302 am65_cpsw_nuss_tx_cleanup); 3303 k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); 3304 } 3305 3306 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 3307 k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, rx_chan, 3308 am65_cpsw_nuss_rx_cleanup, !!i); 3309 3310 k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); 3311 3312 ret = am65_cpsw_nuss_register_devlink(common); 3313 if (ret) 3314 return ret; 3315 3316 for (i = 0; i < common->port_num; i++) { 3317 port = &common->ports[i]; 3318 3319 if (!port->ndev) 3320 continue; 3321 3322 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 3323 3324 ret = register_netdev(port->ndev); 3325 if (ret) { 3326 dev_err(dev, "error registering slave net device%i %d\n", 3327 i, ret); 3328 goto err_cleanup_ndev; 3329 } 3330 } 3331 3332 ret = am65_cpsw_register_notifiers(common); 3333 if (ret) 3334 goto err_cleanup_ndev; 3335 3336 /* can't auto unregister ndev using devm_add_action() due to 3337 * devres release sequence in DD core for DMA 3338 */ 3339 3340 return 0; 3341 3342 err_cleanup_ndev: 3343 am65_cpsw_nuss_cleanup_ndev(common); 3344 am65_cpsw_unregister_devlink(common); 3345 3346 return ret; 3347 } 3348 3349 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 3350 { 3351 int ret; 3352 3353 common->tx_ch_num = num_tx; 3354 ret = am65_cpsw_nuss_init_tx_chns(common); 3355 3356 return ret; 3357 } 3358 3359 struct am65_cpsw_soc_pdata { 3360 u32 quirks_dis; 3361 }; 3362 3363 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 3364 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3365 }; 3366 3367 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 3368 { .family = "AM65X", 3369 .revision = "SR2.0", 3370 .data = &am65x_soc_sr2_0 3371 }, 3372 {/* sentinel */} 3373 }; 3374 3375 static const struct am65_cpsw_pdata am65x_sr1_0 = { 3376 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3377 .ale_dev_id = "am65x-cpsw2g", 3378 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3379 }; 3380 3381 static const struct am65_cpsw_pdata j721e_pdata = { 3382 .quirks = 0, 3383 .ale_dev_id = "am65x-cpsw2g", 3384 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3385 }; 3386 3387 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 3388 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 3389 .ale_dev_id = "am64-cpswxg", 3390 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3391 }; 3392 3393 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 3394 .quirks = 0, 3395 .ale_dev_id = "am64-cpswxg", 3396 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3397 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3398 }; 3399 3400 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 3401 .quirks = 0, 3402 .ale_dev_id = "am64-cpswxg", 3403 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3404 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3405 }; 3406 3407 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 3408 .quirks = 0, 3409 .ale_dev_id = "am64-cpswxg", 3410 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3411 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3412 BIT(PHY_INTERFACE_MODE_USXGMII), 3413 }; 3414 3415 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 3416 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 3417 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 3418 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 3419 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 3420 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 3421 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 3422 { /* sentinel */ }, 3423 }; 3424 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 3425 3426 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 3427 { 3428 const struct soc_device_attribute *soc; 3429 3430 soc = soc_device_match(am65_cpsw_socinfo); 3431 if (soc && soc->data) { 3432 const struct am65_cpsw_soc_pdata *socdata = soc->data; 3433 3434 /* disable quirks */ 3435 common->pdata.quirks &= ~socdata->quirks_dis; 3436 } 3437 } 3438 3439 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 3440 { 3441 struct cpsw_ale_params ale_params = { 0 }; 3442 const struct of_device_id *of_id; 3443 struct device *dev = &pdev->dev; 3444 struct am65_cpsw_common *common; 3445 struct device_node *node; 3446 struct resource *res; 3447 struct clk *clk; 3448 int ale_entries; 3449 u64 id_temp; 3450 int ret, i; 3451 3452 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 3453 if (!common) 3454 return -ENOMEM; 3455 common->dev = dev; 3456 3457 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 3458 if (!of_id) 3459 return -EINVAL; 3460 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 3461 3462 am65_cpsw_nuss_apply_socinfo(common); 3463 3464 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 3465 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 3466 if (IS_ERR(common->ss_base)) 3467 return PTR_ERR(common->ss_base); 3468 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 3469 /* Use device's physical base address as switch id */ 3470 id_temp = cpu_to_be64(res->start); 3471 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 3472 3473 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 3474 if (!node) 3475 return -ENOENT; 3476 common->port_num = of_get_child_count(node); 3477 of_node_put(node); 3478 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 3479 return -ENOENT; 3480 3481 common->rx_flow_id_base = -1; 3482 init_completion(&common->tdown_complete); 3483 common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; 3484 common->pf_p0_rx_ptype_rrobin = false; 3485 common->default_vlan = 1; 3486 3487 common->ports = devm_kcalloc(dev, common->port_num, 3488 sizeof(*common->ports), 3489 GFP_KERNEL); 3490 if (!common->ports) 3491 return -ENOMEM; 3492 3493 clk = devm_clk_get(dev, "fck"); 3494 if (IS_ERR(clk)) 3495 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 3496 common->bus_freq = clk_get_rate(clk); 3497 3498 pm_runtime_enable(dev); 3499 ret = pm_runtime_resume_and_get(dev); 3500 if (ret < 0) { 3501 pm_runtime_disable(dev); 3502 return ret; 3503 } 3504 3505 node = of_get_child_by_name(dev->of_node, "mdio"); 3506 if (!node) { 3507 dev_warn(dev, "MDIO node not found\n"); 3508 } else if (of_device_is_available(node)) { 3509 struct platform_device *mdio_pdev; 3510 3511 mdio_pdev = of_platform_device_create(node, NULL, dev); 3512 if (!mdio_pdev) { 3513 ret = -ENODEV; 3514 goto err_pm_clear; 3515 } 3516 3517 common->mdio_dev = &mdio_pdev->dev; 3518 } 3519 of_node_put(node); 3520 3521 am65_cpsw_nuss_get_ver(common); 3522 3523 ret = am65_cpsw_nuss_init_host_p(common); 3524 if (ret) 3525 goto err_of_clear; 3526 3527 ret = am65_cpsw_nuss_init_slave_ports(common); 3528 if (ret) 3529 goto err_of_clear; 3530 3531 /* init common data */ 3532 ale_params.dev = dev; 3533 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 3534 ale_params.ale_ports = common->port_num + 1; 3535 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 3536 ale_params.dev_id = common->pdata.ale_dev_id; 3537 ale_params.bus_freq = common->bus_freq; 3538 3539 common->ale = cpsw_ale_create(&ale_params); 3540 if (IS_ERR(common->ale)) { 3541 dev_err(dev, "error initializing ale engine\n"); 3542 ret = PTR_ERR(common->ale); 3543 goto err_of_clear; 3544 } 3545 3546 ale_entries = common->ale->params.ale_entries; 3547 common->ale_context = devm_kzalloc(dev, 3548 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 3549 GFP_KERNEL); 3550 ret = am65_cpsw_init_cpts(common); 3551 if (ret) 3552 goto err_of_clear; 3553 3554 /* init ports */ 3555 for (i = 0; i < common->port_num; i++) 3556 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 3557 3558 dev_set_drvdata(dev, common); 3559 3560 common->is_emac_mode = true; 3561 3562 ret = am65_cpsw_nuss_init_ndevs(common); 3563 if (ret) 3564 goto err_free_phylink; 3565 3566 ret = am65_cpsw_nuss_register_ndevs(common); 3567 if (ret) 3568 goto err_free_phylink; 3569 3570 pm_runtime_put(dev); 3571 return 0; 3572 3573 err_free_phylink: 3574 am65_cpsw_nuss_phylink_cleanup(common); 3575 am65_cpts_release(common->cpts); 3576 err_of_clear: 3577 if (common->mdio_dev) 3578 of_platform_device_destroy(common->mdio_dev, NULL); 3579 err_pm_clear: 3580 pm_runtime_put_sync(dev); 3581 pm_runtime_disable(dev); 3582 return ret; 3583 } 3584 3585 static void am65_cpsw_nuss_remove(struct platform_device *pdev) 3586 { 3587 struct device *dev = &pdev->dev; 3588 struct am65_cpsw_common *common; 3589 int ret; 3590 3591 common = dev_get_drvdata(dev); 3592 3593 ret = pm_runtime_resume_and_get(&pdev->dev); 3594 if (ret < 0) { 3595 /* Note, if this error path is taken, we're leaking some 3596 * resources. 3597 */ 3598 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", 3599 ERR_PTR(ret)); 3600 return; 3601 } 3602 3603 am65_cpsw_unregister_devlink(common); 3604 am65_cpsw_unregister_notifiers(common); 3605 3606 /* must unregister ndevs here because DD release_driver routine calls 3607 * dma_deconfigure(dev) before devres_release_all(dev) 3608 */ 3609 am65_cpsw_nuss_cleanup_ndev(common); 3610 am65_cpsw_nuss_phylink_cleanup(common); 3611 am65_cpts_release(common->cpts); 3612 am65_cpsw_disable_serdes_phy(common); 3613 3614 if (common->mdio_dev) 3615 of_platform_device_destroy(common->mdio_dev, NULL); 3616 3617 pm_runtime_put_sync(&pdev->dev); 3618 pm_runtime_disable(&pdev->dev); 3619 } 3620 3621 static int am65_cpsw_nuss_suspend(struct device *dev) 3622 { 3623 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3624 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3625 struct am65_cpsw_port *port; 3626 struct net_device *ndev; 3627 int i, ret; 3628 3629 cpsw_ale_dump(common->ale, common->ale_context); 3630 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3631 for (i = 0; i < common->port_num; i++) { 3632 port = &common->ports[i]; 3633 ndev = port->ndev; 3634 3635 if (!ndev) 3636 continue; 3637 3638 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3639 netif_device_detach(ndev); 3640 if (netif_running(ndev)) { 3641 rtnl_lock(); 3642 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3643 rtnl_unlock(); 3644 if (ret < 0) { 3645 netdev_err(ndev, "failed to stop: %d", ret); 3646 return ret; 3647 } 3648 } 3649 } 3650 3651 am65_cpts_suspend(common->cpts); 3652 3653 am65_cpsw_nuss_remove_rx_chns(common); 3654 am65_cpsw_nuss_remove_tx_chns(common); 3655 3656 return 0; 3657 } 3658 3659 static int am65_cpsw_nuss_resume(struct device *dev) 3660 { 3661 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3662 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3663 struct am65_cpsw_port *port; 3664 struct net_device *ndev; 3665 int i, ret; 3666 3667 ret = am65_cpsw_nuss_init_tx_chns(common); 3668 if (ret) 3669 return ret; 3670 ret = am65_cpsw_nuss_init_rx_chns(common); 3671 if (ret) 3672 return ret; 3673 3674 /* If RX IRQ was disabled before suspend, keep it disabled */ 3675 if (common->rx_irq_disabled) 3676 disable_irq(common->rx_chns.irq); 3677 3678 am65_cpts_resume(common->cpts); 3679 3680 for (i = 0; i < common->port_num; i++) { 3681 port = &common->ports[i]; 3682 ndev = port->ndev; 3683 3684 if (!ndev) 3685 continue; 3686 3687 if (netif_running(ndev)) { 3688 rtnl_lock(); 3689 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3690 rtnl_unlock(); 3691 if (ret < 0) { 3692 netdev_err(ndev, "failed to start: %d", ret); 3693 return ret; 3694 } 3695 } 3696 3697 netif_device_attach(ndev); 3698 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3699 } 3700 3701 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3702 cpsw_ale_restore(common->ale, common->ale_context); 3703 3704 return 0; 3705 } 3706 3707 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3708 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3709 }; 3710 3711 static struct platform_driver am65_cpsw_nuss_driver = { 3712 .driver = { 3713 .name = AM65_CPSW_DRV_NAME, 3714 .of_match_table = am65_cpsw_nuss_of_mtable, 3715 .pm = &am65_cpsw_nuss_dev_pm_ops, 3716 }, 3717 .probe = am65_cpsw_nuss_probe, 3718 .remove_new = am65_cpsw_nuss_remove, 3719 }; 3720 3721 module_platform_driver(am65_cpsw_nuss_driver); 3722 3723 MODULE_LICENSE("GPL v2"); 3724 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3725 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3726