1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/bpf_trace.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/kmemleak.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/phylink.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/rtnetlink.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/sys_soc.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 #include <net/page_pool/helpers.h> 35 #include <net/switchdev.h> 36 37 #include "cpsw_ale.h" 38 #include "cpsw_sl.h" 39 #include "am65-cpsw-nuss.h" 40 #include "am65-cpsw-switchdev.h" 41 #include "k3-cppi-desc-pool.h" 42 #include "am65-cpts.h" 43 44 #define AM65_CPSW_SS_BASE 0x0 45 #define AM65_CPSW_SGMII_BASE 0x100 46 #define AM65_CPSW_XGMII_BASE 0x2100 47 #define AM65_CPSW_CPSW_NU_BASE 0x20000 48 #define AM65_CPSW_NU_PORTS_BASE 0x1000 49 #define AM65_CPSW_NU_FRAM_BASE 0x12000 50 #define AM65_CPSW_NU_STATS_BASE 0x1a000 51 #define AM65_CPSW_NU_ALE_BASE 0x1e000 52 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 53 54 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 55 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 56 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 57 58 #define AM65_CPSW_MAX_PORTS 8 59 60 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 61 #define AM65_CPSW_MAX_PACKET_SIZE 2024 62 63 #define AM65_CPSW_REG_CTL 0x004 64 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 65 #define AM65_CPSW_REG_PTYPE 0x018 66 67 #define AM65_CPSW_P0_REG_CTL 0x004 68 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 69 70 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 71 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 72 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 73 74 #define AM65_CPSW_PORTN_REG_SA_L 0x308 75 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 76 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 77 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 78 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 79 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 80 81 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 82 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 83 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 84 85 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 86 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 87 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 88 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 89 90 /* AM65_CPSW_P0_REG_CTL */ 91 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 92 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 93 94 /* AM65_CPSW_PORT_REG_PRI_CTL */ 95 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 96 97 /* AM65_CPSW_PN_TS_CTL register fields */ 98 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 99 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 100 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 101 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 102 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 103 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 104 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 105 106 #define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0) 107 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1) 108 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2) 109 #define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3) 110 #define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9) 111 112 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 113 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 114 115 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 116 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 117 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 118 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 119 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 120 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 121 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 122 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 123 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 124 125 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 126 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 127 128 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 129 130 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 131 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 132 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 133 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 134 135 #define AM65_CPSW_TS_RX_ANX_ALL_EN \ 136 (AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \ 137 AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \ 138 AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) 139 140 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 141 /* Number of TX/RX descriptors per channel/flow */ 142 #define AM65_CPSW_MAX_TX_DESC 500 143 #define AM65_CPSW_MAX_RX_DESC 500 144 145 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 146 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 147 148 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 149 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 150 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 151 152 #define AM65_CPSW_DEFAULT_TX_CHNS 8 153 #define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 154 155 /* CPPI streaming packet interface */ 156 #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF 157 #define AM65_CPSW_CPPI_TX_PKT_TYPE 0x7 158 159 /* XDP */ 160 #define AM65_CPSW_XDP_CONSUMED BIT(1) 161 #define AM65_CPSW_XDP_REDIRECT BIT(0) 162 #define AM65_CPSW_XDP_PASS 0 163 164 /* Include headroom compatible with both skb and xdpf */ 165 #define AM65_CPSW_HEADROOM_NA (max(NET_SKB_PAD, XDP_PACKET_HEADROOM) + NET_IP_ALIGN) 166 #define AM65_CPSW_HEADROOM ALIGN(AM65_CPSW_HEADROOM_NA, sizeof(long)) 167 168 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 169 const u8 *dev_addr) 170 { 171 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 172 (dev_addr[2] << 16) | (dev_addr[3] << 24); 173 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 174 175 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 176 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 177 } 178 179 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 180 { 181 cpsw_sl_reset(port->slave.mac_sl, 100); 182 /* Max length register has to be restored after MAC SL reset */ 183 writel(AM65_CPSW_MAX_PACKET_SIZE, 184 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 185 } 186 187 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 188 { 189 common->nuss_ver = readl(common->ss_base); 190 common->cpsw_ver = readl(common->cpsw_base); 191 dev_info(common->dev, 192 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 193 common->nuss_ver, 194 common->cpsw_ver, 195 common->port_num + 1, 196 common->pdata.quirks); 197 } 198 199 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 200 __be16 proto, u16 vid) 201 { 202 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 203 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 204 u32 port_mask, unreg_mcast = 0; 205 int ret; 206 207 if (!common->is_emac_mode) 208 return 0; 209 210 if (!netif_running(ndev) || !vid) 211 return 0; 212 213 ret = pm_runtime_resume_and_get(common->dev); 214 if (ret < 0) 215 return ret; 216 217 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 218 if (!vid) 219 unreg_mcast = port_mask; 220 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 221 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 222 unreg_mcast, port_mask, 0); 223 224 pm_runtime_put(common->dev); 225 return ret; 226 } 227 228 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 229 __be16 proto, u16 vid) 230 { 231 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 232 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 233 int ret; 234 235 if (!common->is_emac_mode) 236 return 0; 237 238 if (!netif_running(ndev) || !vid) 239 return 0; 240 241 ret = pm_runtime_resume_and_get(common->dev); 242 if (ret < 0) 243 return ret; 244 245 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 246 ret = cpsw_ale_del_vlan(common->ale, vid, 247 BIT(port->port_id) | ALE_PORT_HOST); 248 249 pm_runtime_put(common->dev); 250 return ret; 251 } 252 253 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 254 bool promisc) 255 { 256 struct am65_cpsw_common *common = port->common; 257 258 if (promisc && !common->is_emac_mode) { 259 dev_dbg(common->dev, "promisc mode requested in switch mode"); 260 return; 261 } 262 263 if (promisc) { 264 /* Enable promiscuous mode */ 265 cpsw_ale_control_set(common->ale, port->port_id, 266 ALE_PORT_MACONLY_CAF, 1); 267 dev_dbg(common->dev, "promisc enabled\n"); 268 } else { 269 /* Disable promiscuous mode */ 270 cpsw_ale_control_set(common->ale, port->port_id, 271 ALE_PORT_MACONLY_CAF, 0); 272 dev_dbg(common->dev, "promisc disabled\n"); 273 } 274 } 275 276 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 277 { 278 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 279 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 280 u32 port_mask; 281 bool promisc; 282 283 promisc = !!(ndev->flags & IFF_PROMISC); 284 am65_cpsw_slave_set_promisc(port, promisc); 285 286 if (promisc) 287 return; 288 289 /* Restore allmulti on vlans if necessary */ 290 cpsw_ale_set_allmulti(common->ale, 291 ndev->flags & IFF_ALLMULTI, port->port_id); 292 293 port_mask = ALE_PORT_HOST; 294 /* Clear all mcast from ALE */ 295 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 296 297 if (!netdev_mc_empty(ndev)) { 298 struct netdev_hw_addr *ha; 299 300 /* program multicast address list into ALE register */ 301 netdev_for_each_mc_addr(ha, ndev) { 302 cpsw_ale_add_mcast(common->ale, ha->addr, 303 port_mask, 0, 0, 0); 304 } 305 } 306 } 307 308 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 309 unsigned int txqueue) 310 { 311 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 312 struct am65_cpsw_tx_chn *tx_chn; 313 struct netdev_queue *netif_txq; 314 unsigned long trans_start; 315 316 netif_txq = netdev_get_tx_queue(ndev, txqueue); 317 tx_chn = &common->tx_chns[txqueue]; 318 trans_start = READ_ONCE(netif_txq->trans_start); 319 320 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 321 txqueue, 322 netif_tx_queue_stopped(netif_txq), 323 jiffies_to_msecs(jiffies - trans_start), 324 netdev_queue_dql_avail(netif_txq), 325 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 326 327 if (netif_tx_queue_stopped(netif_txq)) { 328 /* try recover if stopped by us */ 329 txq_trans_update(netif_txq); 330 netif_tx_wake_queue(netif_txq); 331 } 332 } 333 334 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 335 struct page *page, u32 flow_idx) 336 { 337 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 338 struct cppi5_host_desc_t *desc_rx; 339 struct device *dev = common->dev; 340 dma_addr_t desc_dma; 341 dma_addr_t buf_dma; 342 void *swdata; 343 344 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 345 if (!desc_rx) { 346 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 347 return -ENOMEM; 348 } 349 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 350 351 buf_dma = dma_map_single(rx_chn->dma_dev, 352 page_address(page) + AM65_CPSW_HEADROOM, 353 AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); 354 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 355 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 356 dev_err(dev, "Failed to map rx buffer\n"); 357 return -EINVAL; 358 } 359 360 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 361 AM65_CPSW_NAV_PS_DATA_SIZE); 362 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 363 cppi5_hdesc_attach_buf(desc_rx, buf_dma, AM65_CPSW_MAX_PACKET_SIZE, 364 buf_dma, AM65_CPSW_MAX_PACKET_SIZE); 365 swdata = cppi5_hdesc_get_swdata(desc_rx); 366 *((void **)swdata) = page_address(page); 367 368 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, 369 desc_rx, desc_dma); 370 } 371 372 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 373 { 374 struct am65_cpsw_host *host_p = am65_common_get_host(common); 375 u32 val, pri_map; 376 377 /* P0 set Receive Priority Type */ 378 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 379 380 if (common->pf_p0_rx_ptype_rrobin) { 381 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 382 /* Enet Ports fifos works in fixed priority mode only, so 383 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 384 */ 385 pri_map = 0x0; 386 } else { 387 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 388 /* restore P0_Rx_Pri_Map */ 389 pri_map = 0x76543210; 390 } 391 392 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 393 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 394 } 395 396 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 397 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 398 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 399 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 400 401 static void am65_cpsw_destroy_xdp_rxqs(struct am65_cpsw_common *common) 402 { 403 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 404 struct am65_cpsw_rx_flow *flow; 405 struct xdp_rxq_info *rxq; 406 int id, port; 407 408 for (id = 0; id < common->rx_ch_num_flows; id++) { 409 flow = &rx_chn->flows[id]; 410 411 for (port = 0; port < common->port_num; port++) { 412 if (!common->ports[port].ndev) 413 continue; 414 415 rxq = &common->ports[port].xdp_rxq[id]; 416 417 if (xdp_rxq_info_is_reg(rxq)) 418 xdp_rxq_info_unreg(rxq); 419 } 420 421 if (flow->page_pool) { 422 page_pool_destroy(flow->page_pool); 423 flow->page_pool = NULL; 424 } 425 } 426 } 427 428 static int am65_cpsw_create_xdp_rxqs(struct am65_cpsw_common *common) 429 { 430 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 431 struct page_pool_params pp_params = { 432 .flags = PP_FLAG_DMA_MAP, 433 .order = 0, 434 .pool_size = AM65_CPSW_MAX_RX_DESC, 435 .nid = dev_to_node(common->dev), 436 .dev = common->dev, 437 .dma_dir = DMA_BIDIRECTIONAL, 438 /* .napi set dynamically */ 439 }; 440 struct am65_cpsw_rx_flow *flow; 441 struct xdp_rxq_info *rxq; 442 struct page_pool *pool; 443 int id, port, ret; 444 445 for (id = 0; id < common->rx_ch_num_flows; id++) { 446 flow = &rx_chn->flows[id]; 447 pp_params.napi = &flow->napi_rx; 448 pool = page_pool_create(&pp_params); 449 if (IS_ERR(pool)) { 450 ret = PTR_ERR(pool); 451 goto err; 452 } 453 454 flow->page_pool = pool; 455 456 /* using same page pool is allowed as no running rx handlers 457 * simultaneously for both ndevs 458 */ 459 for (port = 0; port < common->port_num; port++) { 460 if (!common->ports[port].ndev) 461 continue; 462 463 rxq = &common->ports[port].xdp_rxq[id]; 464 465 ret = xdp_rxq_info_reg(rxq, common->ports[port].ndev, 466 id, flow->napi_rx.napi_id); 467 if (ret) 468 goto err; 469 470 ret = xdp_rxq_info_reg_mem_model(rxq, 471 MEM_TYPE_PAGE_POOL, 472 pool); 473 if (ret) 474 goto err; 475 } 476 } 477 478 return 0; 479 480 err: 481 am65_cpsw_destroy_xdp_rxqs(common); 482 return ret; 483 } 484 485 static int am65_cpsw_nuss_desc_idx(struct k3_cppi_desc_pool *desc_pool, 486 void *desc, 487 unsigned char dsize_log2) 488 { 489 void *pool_addr = k3_cppi_desc_pool_cpuaddr(desc_pool); 490 491 return (desc - pool_addr) >> dsize_log2; 492 } 493 494 static void am65_cpsw_nuss_set_buf_type(struct am65_cpsw_tx_chn *tx_chn, 495 struct cppi5_host_desc_t *desc, 496 enum am65_cpsw_tx_buf_type buf_type) 497 { 498 int desc_idx; 499 500 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc, 501 tx_chn->dsize_log2); 502 k3_cppi_desc_pool_desc_info_set(tx_chn->desc_pool, desc_idx, 503 (void *)buf_type); 504 } 505 506 static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_chn *tx_chn, 507 dma_addr_t desc_dma) 508 { 509 struct cppi5_host_desc_t *desc_tx; 510 int desc_idx; 511 512 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 513 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc_tx, 514 tx_chn->dsize_log2); 515 516 return (enum am65_cpsw_tx_buf_type)k3_cppi_desc_pool_desc_info(tx_chn->desc_pool, 517 desc_idx); 518 } 519 520 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 521 struct page *page, 522 bool allow_direct, 523 int desc_idx) 524 { 525 page_pool_put_full_page(flow->page_pool, page, allow_direct); 526 flow->pages[desc_idx] = NULL; 527 } 528 529 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 530 { 531 struct am65_cpsw_rx_flow *flow = data; 532 struct cppi5_host_desc_t *desc_rx; 533 struct am65_cpsw_rx_chn *rx_chn; 534 dma_addr_t buf_dma; 535 u32 buf_dma_len; 536 void *page_addr; 537 void **swdata; 538 int desc_idx; 539 540 rx_chn = &flow->common->rx_chns; 541 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 542 swdata = cppi5_hdesc_get_swdata(desc_rx); 543 page_addr = *swdata; 544 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 545 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 546 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 547 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 548 549 desc_idx = am65_cpsw_nuss_desc_idx(rx_chn->desc_pool, desc_rx, 550 rx_chn->dsize_log2); 551 am65_cpsw_put_page(flow, virt_to_page(page_addr), false, desc_idx); 552 } 553 554 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 555 struct cppi5_host_desc_t *desc) 556 { 557 struct cppi5_host_desc_t *first_desc, *next_desc; 558 dma_addr_t buf_dma, next_desc_dma; 559 u32 buf_dma_len; 560 561 first_desc = desc; 562 next_desc = first_desc; 563 564 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 565 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 566 567 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 568 569 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 570 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 571 while (next_desc_dma) { 572 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 573 next_desc_dma); 574 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 575 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 576 577 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 578 DMA_TO_DEVICE); 579 580 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 581 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 582 583 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 584 } 585 586 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 587 } 588 589 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 590 { 591 struct am65_cpsw_tx_chn *tx_chn = data; 592 struct cppi5_host_desc_t *desc_tx; 593 struct sk_buff *skb; 594 void **swdata; 595 596 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 597 swdata = cppi5_hdesc_get_swdata(desc_tx); 598 skb = *(swdata); 599 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 600 601 dev_kfree_skb_any(skb); 602 } 603 604 static struct sk_buff *am65_cpsw_build_skb(void *page_addr, 605 struct net_device *ndev, 606 unsigned int len) 607 { 608 struct sk_buff *skb; 609 610 len += AM65_CPSW_HEADROOM; 611 612 skb = build_skb(page_addr, len); 613 if (unlikely(!skb)) 614 return NULL; 615 616 skb_reserve(skb, AM65_CPSW_HEADROOM); 617 skb->dev = ndev; 618 619 return skb; 620 } 621 622 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 623 { 624 struct am65_cpsw_host *host_p = am65_common_get_host(common); 625 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 626 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 627 int port_idx, i, ret, tx, flow_idx; 628 struct am65_cpsw_rx_flow *flow; 629 u32 val, port_mask; 630 struct page *page; 631 632 if (common->usage_count) 633 return 0; 634 635 /* Control register */ 636 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 637 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 638 common->cpsw_base + AM65_CPSW_REG_CTL); 639 /* Max length register */ 640 writel(AM65_CPSW_MAX_PACKET_SIZE, 641 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 642 /* set base flow_id */ 643 writel(common->rx_flow_id_base, 644 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 645 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 646 host_p->port_base + AM65_CPSW_P0_REG_CTL); 647 648 am65_cpsw_nuss_set_p0_ptype(common); 649 650 /* enable statistic */ 651 val = BIT(HOST_PORT_NUM); 652 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 653 struct am65_cpsw_port *port = &common->ports[port_idx]; 654 655 if (!port->disabled) 656 val |= BIT(port->port_id); 657 } 658 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 659 660 /* disable priority elevation */ 661 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 662 663 cpsw_ale_start(common->ale); 664 665 /* limit to one RX flow only */ 666 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 667 ALE_DEFAULT_THREAD_ID, 0); 668 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 669 ALE_DEFAULT_THREAD_ENABLE, 1); 670 /* switch to vlan unaware mode */ 671 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 672 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 673 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 674 675 /* default vlan cfg: create mask based on enabled ports */ 676 port_mask = GENMASK(common->port_num, 0) & 677 ~common->disabled_ports_mask; 678 679 cpsw_ale_add_vlan(common->ale, 0, port_mask, 680 port_mask, port_mask, 681 port_mask & ~ALE_PORT_HOST); 682 683 if (common->is_emac_mode) 684 am65_cpsw_init_host_port_emac(common); 685 else 686 am65_cpsw_init_host_port_switch(common); 687 688 am65_cpsw_qos_tx_p0_rate_init(common); 689 690 ret = am65_cpsw_create_xdp_rxqs(common); 691 if (ret) { 692 dev_err(common->dev, "Failed to create XDP rx queues\n"); 693 return ret; 694 } 695 696 for (flow_idx = 0; flow_idx < common->rx_ch_num_flows; flow_idx++) { 697 flow = &rx_chn->flows[flow_idx]; 698 for (i = 0; i < AM65_CPSW_MAX_RX_DESC; i++) { 699 page = page_pool_dev_alloc_pages(flow->page_pool); 700 if (!page) { 701 dev_err(common->dev, "cannot allocate page in flow %d\n", 702 flow_idx); 703 ret = -ENOMEM; 704 goto fail_rx; 705 } 706 flow->pages[i] = page; 707 708 ret = am65_cpsw_nuss_rx_push(common, page, flow_idx); 709 if (ret < 0) { 710 dev_err(common->dev, 711 "cannot submit page to rx channel flow %d, error %d\n", 712 flow_idx, ret); 713 am65_cpsw_put_page(flow, page, false, i); 714 goto fail_rx; 715 } 716 } 717 } 718 719 ret = k3_udma_glue_enable_rx_chn(rx_chn->rx_chn); 720 if (ret) { 721 dev_err(common->dev, "couldn't enable rx chn: %d\n", ret); 722 goto fail_rx; 723 } 724 725 for (i = 0; i < common->rx_ch_num_flows ; i++) { 726 napi_enable(&rx_chn->flows[i].napi_rx); 727 if (rx_chn->flows[i].irq_disabled) { 728 rx_chn->flows[i].irq_disabled = false; 729 enable_irq(rx_chn->flows[i].irq); 730 } 731 } 732 733 for (tx = 0; tx < common->tx_ch_num; tx++) { 734 ret = k3_udma_glue_enable_tx_chn(tx_chn[tx].tx_chn); 735 if (ret) { 736 dev_err(common->dev, "couldn't enable tx chn %d: %d\n", 737 tx, ret); 738 tx--; 739 goto fail_tx; 740 } 741 napi_enable(&tx_chn[tx].napi_tx); 742 } 743 744 dev_dbg(common->dev, "cpsw_nuss started\n"); 745 return 0; 746 747 fail_tx: 748 while (tx >= 0) { 749 napi_disable(&tx_chn[tx].napi_tx); 750 k3_udma_glue_disable_tx_chn(tx_chn[tx].tx_chn); 751 tx--; 752 } 753 754 for (flow_idx = 0; i < common->rx_ch_num_flows; flow_idx++) { 755 flow = &rx_chn->flows[flow_idx]; 756 if (!flow->irq_disabled) { 757 disable_irq(flow->irq); 758 flow->irq_disabled = true; 759 } 760 napi_disable(&flow->napi_rx); 761 } 762 763 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 764 765 fail_rx: 766 for (i = 0; i < common->rx_ch_num_flows; i++) 767 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, &rx_chn->flows[i], 768 am65_cpsw_nuss_rx_cleanup, 0); 769 770 am65_cpsw_destroy_xdp_rxqs(common); 771 772 return ret; 773 } 774 775 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 776 { 777 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 778 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 779 int i; 780 781 if (common->usage_count != 1) 782 return 0; 783 784 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 785 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 786 787 /* shutdown tx channels */ 788 atomic_set(&common->tdown_cnt, common->tx_ch_num); 789 /* ensure new tdown_cnt value is visible */ 790 smp_mb__after_atomic(); 791 reinit_completion(&common->tdown_complete); 792 793 for (i = 0; i < common->tx_ch_num; i++) 794 k3_udma_glue_tdown_tx_chn(tx_chn[i].tx_chn, false); 795 796 i = wait_for_completion_timeout(&common->tdown_complete, 797 msecs_to_jiffies(1000)); 798 if (!i) 799 dev_err(common->dev, "tx timeout\n"); 800 for (i = 0; i < common->tx_ch_num; i++) { 801 napi_disable(&tx_chn[i].napi_tx); 802 hrtimer_cancel(&tx_chn[i].tx_hrtimer); 803 } 804 805 for (i = 0; i < common->tx_ch_num; i++) { 806 k3_udma_glue_reset_tx_chn(tx_chn[i].tx_chn, &tx_chn[i], 807 am65_cpsw_nuss_tx_cleanup); 808 k3_udma_glue_disable_tx_chn(tx_chn[i].tx_chn); 809 } 810 811 reinit_completion(&common->tdown_complete); 812 k3_udma_glue_tdown_rx_chn(rx_chn->rx_chn, true); 813 814 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 815 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 816 if (!i) 817 dev_err(common->dev, "rx teardown timeout\n"); 818 } 819 820 for (i = 0; i < common->rx_ch_num_flows; i++) { 821 napi_disable(&rx_chn->flows[i].napi_rx); 822 hrtimer_cancel(&rx_chn->flows[i].rx_hrtimer); 823 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, &rx_chn->flows[i], 824 am65_cpsw_nuss_rx_cleanup, 0); 825 } 826 827 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 828 829 cpsw_ale_stop(common->ale); 830 831 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 832 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 833 834 am65_cpsw_destroy_xdp_rxqs(common); 835 836 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 837 return 0; 838 } 839 840 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 841 { 842 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 843 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 844 int ret; 845 846 phylink_stop(port->slave.phylink); 847 848 netif_tx_stop_all_queues(ndev); 849 850 phylink_disconnect_phy(port->slave.phylink); 851 852 ret = am65_cpsw_nuss_common_stop(common); 853 if (ret) 854 return ret; 855 856 common->usage_count--; 857 pm_runtime_put(common->dev); 858 return 0; 859 } 860 861 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 862 { 863 struct am65_cpsw_port *port = arg; 864 865 if (!vdev) 866 return 0; 867 868 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 869 } 870 871 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 872 { 873 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 874 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 875 int ret, i; 876 u32 reg; 877 878 ret = pm_runtime_resume_and_get(common->dev); 879 if (ret < 0) 880 return ret; 881 882 /* Idle MAC port */ 883 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 884 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 885 cpsw_sl_ctl_reset(port->slave.mac_sl); 886 887 /* soft reset MAC */ 888 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 889 mdelay(1); 890 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 891 if (reg) { 892 dev_err(common->dev, "soft RESET didn't complete\n"); 893 ret = -ETIMEDOUT; 894 goto runtime_put; 895 } 896 897 /* Notify the stack of the actual queue counts. */ 898 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 899 if (ret) { 900 dev_err(common->dev, "cannot set real number of tx queues\n"); 901 goto runtime_put; 902 } 903 904 ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); 905 if (ret) { 906 dev_err(common->dev, "cannot set real number of rx queues\n"); 907 goto runtime_put; 908 } 909 910 for (i = 0; i < common->tx_ch_num; i++) { 911 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 912 913 netdev_tx_reset_queue(txq); 914 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 915 } 916 917 ret = am65_cpsw_nuss_common_open(common); 918 if (ret) 919 goto runtime_put; 920 921 common->usage_count++; 922 923 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 924 925 if (common->is_emac_mode) 926 am65_cpsw_init_port_emac_ale(port); 927 else 928 am65_cpsw_init_port_switch_ale(port); 929 930 /* mac_sl should be configured via phy-link interface */ 931 am65_cpsw_sl_ctl_reset(port); 932 933 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.port_np, 0); 934 if (ret) 935 goto error_cleanup; 936 937 /* restore vlan configurations */ 938 vlan_for_each(ndev, cpsw_restore_vlans, port); 939 940 phylink_start(port->slave.phylink); 941 942 return 0; 943 944 error_cleanup: 945 am65_cpsw_nuss_ndo_slave_stop(ndev); 946 return ret; 947 948 runtime_put: 949 pm_runtime_put(common->dev); 950 return ret; 951 } 952 953 static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, 954 struct am65_cpsw_tx_chn *tx_chn, 955 struct xdp_frame *xdpf, 956 enum am65_cpsw_tx_buf_type buf_type) 957 { 958 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 959 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 960 struct cppi5_host_desc_t *host_desc; 961 struct netdev_queue *netif_txq; 962 dma_addr_t dma_desc, dma_buf; 963 u32 pkt_len = xdpf->len; 964 void **swdata; 965 int ret; 966 967 host_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 968 if (unlikely(!host_desc)) { 969 ndev->stats.tx_dropped++; 970 return AM65_CPSW_XDP_CONSUMED; /* drop */ 971 } 972 973 am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, buf_type); 974 975 dma_buf = dma_map_single(tx_chn->dma_dev, xdpf->data, 976 pkt_len, DMA_TO_DEVICE); 977 if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { 978 ndev->stats.tx_dropped++; 979 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 980 goto pool_free; 981 } 982 983 cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 984 AM65_CPSW_NAV_PS_DATA_SIZE); 985 cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 986 cppi5_hdesc_set_pktlen(host_desc, pkt_len); 987 cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 988 cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); 989 990 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); 991 cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); 992 993 swdata = cppi5_hdesc_get_swdata(host_desc); 994 *(swdata) = xdpf; 995 996 /* Report BQL before sending the packet */ 997 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 998 netdev_tx_sent_queue(netif_txq, pkt_len); 999 1000 dma_desc = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); 1001 if (AM65_CPSW_IS_CPSW2G(common)) { 1002 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1003 dma_desc); 1004 } else { 1005 spin_lock_bh(&tx_chn->lock); 1006 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1007 dma_desc); 1008 spin_unlock_bh(&tx_chn->lock); 1009 } 1010 if (ret) { 1011 /* Inform BQL */ 1012 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1013 ndev->stats.tx_errors++; 1014 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1015 goto dma_unmap; 1016 } 1017 1018 return 0; 1019 1020 dma_unmap: 1021 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); 1022 dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); 1023 pool_free: 1024 k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); 1025 return ret; 1026 } 1027 1028 static int am65_cpsw_run_xdp(struct am65_cpsw_rx_flow *flow, 1029 struct am65_cpsw_port *port, 1030 struct xdp_buff *xdp, 1031 int desc_idx, int cpu, int *len) 1032 { 1033 struct am65_cpsw_common *common = flow->common; 1034 struct net_device *ndev = port->ndev; 1035 int ret = AM65_CPSW_XDP_CONSUMED; 1036 struct am65_cpsw_tx_chn *tx_chn; 1037 struct netdev_queue *netif_txq; 1038 struct xdp_frame *xdpf; 1039 struct bpf_prog *prog; 1040 struct page *page; 1041 u32 act; 1042 int err; 1043 1044 prog = READ_ONCE(port->xdp_prog); 1045 if (!prog) 1046 return AM65_CPSW_XDP_PASS; 1047 1048 act = bpf_prog_run_xdp(prog, xdp); 1049 /* XDP prog might have changed packet data and boundaries */ 1050 *len = xdp->data_end - xdp->data; 1051 1052 switch (act) { 1053 case XDP_PASS: 1054 ret = AM65_CPSW_XDP_PASS; 1055 goto out; 1056 case XDP_TX: 1057 tx_chn = &common->tx_chns[cpu % AM65_CPSW_MAX_QUEUES]; 1058 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1059 1060 xdpf = xdp_convert_buff_to_frame(xdp); 1061 if (unlikely(!xdpf)) 1062 goto drop; 1063 1064 __netif_tx_lock(netif_txq, cpu); 1065 err = am65_cpsw_xdp_tx_frame(ndev, tx_chn, xdpf, 1066 AM65_CPSW_TX_BUF_TYPE_XDP_TX); 1067 __netif_tx_unlock(netif_txq); 1068 if (err) 1069 goto drop; 1070 1071 dev_sw_netstats_tx_add(ndev, 1, *len); 1072 ret = AM65_CPSW_XDP_CONSUMED; 1073 goto out; 1074 case XDP_REDIRECT: 1075 if (unlikely(xdp_do_redirect(ndev, xdp, prog))) 1076 goto drop; 1077 1078 dev_sw_netstats_rx_add(ndev, *len); 1079 ret = AM65_CPSW_XDP_REDIRECT; 1080 goto out; 1081 default: 1082 bpf_warn_invalid_xdp_action(ndev, prog, act); 1083 fallthrough; 1084 case XDP_ABORTED: 1085 drop: 1086 trace_xdp_exception(ndev, prog, act); 1087 fallthrough; 1088 case XDP_DROP: 1089 ndev->stats.rx_dropped++; 1090 } 1091 1092 page = virt_to_head_page(xdp->data); 1093 am65_cpsw_put_page(flow, page, true, desc_idx); 1094 1095 out: 1096 return ret; 1097 } 1098 1099 /* RX psdata[2] word format - checksum information */ 1100 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 1101 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 1102 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 1103 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 1104 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 1105 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 1106 1107 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 1108 { 1109 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 1110 * csum information provides in psdata[2] word: 1111 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 1112 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 1113 * bits - indicates IPv4/IPv6 packet 1114 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 1115 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 1116 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 1117 */ 1118 skb_checksum_none_assert(skb); 1119 1120 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 1121 return; 1122 1123 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 1124 AM65_CPSW_RX_PSD_IPV4_VALID)) && 1125 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 1126 /* csum for fragmented packets is unsupported */ 1127 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 1128 skb->ip_summed = CHECKSUM_UNNECESSARY; 1129 } 1130 } 1131 1132 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow, 1133 int cpu, int *xdp_state) 1134 { 1135 struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; 1136 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 1137 struct am65_cpsw_common *common = flow->common; 1138 struct am65_cpsw_ndev_priv *ndev_priv; 1139 struct cppi5_host_desc_t *desc_rx; 1140 struct device *dev = common->dev; 1141 struct page *page, *new_page; 1142 dma_addr_t desc_dma, buf_dma; 1143 struct am65_cpsw_port *port; 1144 int headroom, desc_idx, ret; 1145 struct net_device *ndev; 1146 u32 flow_idx = flow->id; 1147 struct sk_buff *skb; 1148 struct xdp_buff xdp; 1149 void *page_addr; 1150 void **swdata; 1151 u32 *psdata; 1152 1153 *xdp_state = AM65_CPSW_XDP_PASS; 1154 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 1155 if (ret) { 1156 if (ret != -ENODATA) 1157 dev_err(dev, "RX: pop chn fail %d\n", ret); 1158 return ret; 1159 } 1160 1161 if (cppi5_desc_is_tdcm(desc_dma)) { 1162 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 1163 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 1164 complete(&common->tdown_complete); 1165 return 0; 1166 } 1167 1168 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 1169 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 1170 __func__, flow_idx, &desc_dma); 1171 1172 swdata = cppi5_hdesc_get_swdata(desc_rx); 1173 page_addr = *swdata; 1174 page = virt_to_page(page_addr); 1175 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 1176 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 1177 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 1178 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 1179 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 1180 port = am65_common_get_port(common, port_id); 1181 ndev = port->ndev; 1182 psdata = cppi5_hdesc_get_psdata(desc_rx); 1183 csum_info = psdata[2]; 1184 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 1185 1186 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 1187 1188 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 1189 1190 desc_idx = am65_cpsw_nuss_desc_idx(rx_chn->desc_pool, desc_rx, 1191 rx_chn->dsize_log2); 1192 1193 skb = am65_cpsw_build_skb(page_addr, ndev, 1194 AM65_CPSW_MAX_PACKET_SIZE); 1195 if (unlikely(!skb)) { 1196 new_page = page; 1197 goto requeue; 1198 } 1199 1200 if (port->xdp_prog) { 1201 xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq[flow->id]); 1202 xdp_prepare_buff(&xdp, page_addr, AM65_CPSW_HEADROOM, 1203 pkt_len, false); 1204 *xdp_state = am65_cpsw_run_xdp(flow, port, &xdp, desc_idx, 1205 cpu, &pkt_len); 1206 if (*xdp_state != AM65_CPSW_XDP_PASS) 1207 goto allocate; 1208 1209 /* Compute additional headroom to be reserved */ 1210 headroom = (xdp.data - xdp.data_hard_start) - skb_headroom(skb); 1211 skb_reserve(skb, headroom); 1212 } 1213 1214 ndev_priv = netdev_priv(ndev); 1215 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 1216 skb_put(skb, pkt_len); 1217 if (port->rx_ts_enabled) 1218 am65_cpts_rx_timestamp(common->cpts, skb); 1219 skb_mark_for_recycle(skb); 1220 skb->protocol = eth_type_trans(skb, ndev); 1221 am65_cpsw_nuss_rx_csum(skb, csum_info); 1222 napi_gro_receive(&flow->napi_rx, skb); 1223 1224 dev_sw_netstats_rx_add(ndev, pkt_len); 1225 1226 allocate: 1227 new_page = page_pool_dev_alloc_pages(flow->page_pool); 1228 if (unlikely(!new_page)) { 1229 dev_err(dev, "page alloc failed\n"); 1230 return -ENOMEM; 1231 } 1232 1233 flow->pages[desc_idx] = new_page; 1234 1235 if (netif_dormant(ndev)) { 1236 am65_cpsw_put_page(flow, new_page, true, desc_idx); 1237 ndev->stats.rx_dropped++; 1238 return 0; 1239 } 1240 1241 requeue: 1242 ret = am65_cpsw_nuss_rx_push(common, new_page, flow_idx); 1243 if (WARN_ON(ret < 0)) { 1244 am65_cpsw_put_page(flow, new_page, true, desc_idx); 1245 ndev->stats.rx_errors++; 1246 ndev->stats.rx_dropped++; 1247 } 1248 1249 return ret; 1250 } 1251 1252 static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) 1253 { 1254 struct am65_cpsw_rx_flow *flow = container_of(timer, 1255 struct am65_cpsw_rx_flow, 1256 rx_hrtimer); 1257 1258 enable_irq(flow->irq); 1259 return HRTIMER_NORESTART; 1260 } 1261 1262 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 1263 { 1264 struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); 1265 struct am65_cpsw_common *common = flow->common; 1266 int cpu = smp_processor_id(); 1267 int xdp_state_or = 0; 1268 int cur_budget, ret; 1269 int xdp_state; 1270 int num_rx = 0; 1271 1272 /* process only this flow */ 1273 cur_budget = budget; 1274 while (cur_budget--) { 1275 ret = am65_cpsw_nuss_rx_packets(flow, cpu, &xdp_state); 1276 xdp_state_or |= xdp_state; 1277 if (ret) 1278 break; 1279 num_rx++; 1280 } 1281 1282 if (xdp_state_or & AM65_CPSW_XDP_REDIRECT) 1283 xdp_do_flush(); 1284 1285 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 1286 1287 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1288 if (flow->irq_disabled) { 1289 flow->irq_disabled = false; 1290 if (unlikely(flow->rx_pace_timeout)) { 1291 hrtimer_start(&flow->rx_hrtimer, 1292 ns_to_ktime(flow->rx_pace_timeout), 1293 HRTIMER_MODE_REL_PINNED); 1294 } else { 1295 enable_irq(flow->irq); 1296 } 1297 } 1298 } 1299 1300 return num_rx; 1301 } 1302 1303 static struct sk_buff * 1304 am65_cpsw_nuss_tx_compl_packet_skb(struct am65_cpsw_tx_chn *tx_chn, 1305 dma_addr_t desc_dma) 1306 { 1307 struct cppi5_host_desc_t *desc_tx; 1308 struct sk_buff *skb; 1309 void **swdata; 1310 1311 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 1312 desc_dma); 1313 swdata = cppi5_hdesc_get_swdata(desc_tx); 1314 skb = *(swdata); 1315 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1316 1317 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 1318 1319 dev_sw_netstats_tx_add(skb->dev, 1, skb->len); 1320 1321 return skb; 1322 } 1323 1324 static struct xdp_frame * 1325 am65_cpsw_nuss_tx_compl_packet_xdp(struct am65_cpsw_common *common, 1326 struct am65_cpsw_tx_chn *tx_chn, 1327 dma_addr_t desc_dma, 1328 struct net_device **ndev) 1329 { 1330 struct cppi5_host_desc_t *desc_tx; 1331 struct am65_cpsw_port *port; 1332 struct xdp_frame *xdpf; 1333 u32 port_id = 0; 1334 void **swdata; 1335 1336 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 1337 cppi5_desc_get_tags_ids(&desc_tx->hdr, NULL, &port_id); 1338 swdata = cppi5_hdesc_get_swdata(desc_tx); 1339 xdpf = *(swdata); 1340 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1341 1342 port = am65_common_get_port(common, port_id); 1343 dev_sw_netstats_tx_add(port->ndev, 1, xdpf->len); 1344 *ndev = port->ndev; 1345 1346 return xdpf; 1347 } 1348 1349 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 1350 struct netdev_queue *netif_txq) 1351 { 1352 if (netif_tx_queue_stopped(netif_txq)) { 1353 /* Check whether the queue is stopped due to stalled 1354 * tx dma, if the queue is stopped then wake the queue 1355 * as we have free desc for tx 1356 */ 1357 __netif_tx_lock(netif_txq, smp_processor_id()); 1358 if (netif_running(ndev) && 1359 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 1360 netif_tx_wake_queue(netif_txq); 1361 1362 __netif_tx_unlock(netif_txq); 1363 } 1364 } 1365 1366 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 1367 int chn, unsigned int budget, bool *tdown) 1368 { 1369 enum am65_cpsw_tx_buf_type buf_type; 1370 struct device *dev = common->dev; 1371 struct am65_cpsw_tx_chn *tx_chn; 1372 struct netdev_queue *netif_txq; 1373 unsigned int total_bytes = 0; 1374 struct net_device *ndev; 1375 struct xdp_frame *xdpf; 1376 struct sk_buff *skb; 1377 dma_addr_t desc_dma; 1378 int res, num_tx = 0; 1379 1380 tx_chn = &common->tx_chns[chn]; 1381 1382 while (true) { 1383 spin_lock(&tx_chn->lock); 1384 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1385 spin_unlock(&tx_chn->lock); 1386 if (res == -ENODATA) 1387 break; 1388 1389 if (cppi5_desc_is_tdcm(desc_dma)) { 1390 if (atomic_dec_and_test(&common->tdown_cnt)) 1391 complete(&common->tdown_complete); 1392 *tdown = true; 1393 break; 1394 } 1395 1396 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1397 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1398 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1399 ndev = skb->dev; 1400 total_bytes = skb->len; 1401 napi_consume_skb(skb, budget); 1402 } else { 1403 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1404 desc_dma, &ndev); 1405 total_bytes = xdpf->len; 1406 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1407 xdp_return_frame_rx_napi(xdpf); 1408 else 1409 xdp_return_frame(xdpf); 1410 } 1411 num_tx++; 1412 1413 netif_txq = netdev_get_tx_queue(ndev, chn); 1414 1415 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1416 1417 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1418 } 1419 1420 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1421 1422 return num_tx; 1423 } 1424 1425 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 1426 int chn, unsigned int budget, bool *tdown) 1427 { 1428 enum am65_cpsw_tx_buf_type buf_type; 1429 struct device *dev = common->dev; 1430 struct am65_cpsw_tx_chn *tx_chn; 1431 struct netdev_queue *netif_txq; 1432 unsigned int total_bytes = 0; 1433 struct net_device *ndev; 1434 struct xdp_frame *xdpf; 1435 struct sk_buff *skb; 1436 dma_addr_t desc_dma; 1437 int res, num_tx = 0; 1438 1439 tx_chn = &common->tx_chns[chn]; 1440 1441 while (true) { 1442 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1443 if (res == -ENODATA) 1444 break; 1445 1446 if (cppi5_desc_is_tdcm(desc_dma)) { 1447 if (atomic_dec_and_test(&common->tdown_cnt)) 1448 complete(&common->tdown_complete); 1449 *tdown = true; 1450 break; 1451 } 1452 1453 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1454 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1455 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1456 ndev = skb->dev; 1457 total_bytes += skb->len; 1458 napi_consume_skb(skb, budget); 1459 } else { 1460 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1461 desc_dma, &ndev); 1462 total_bytes += xdpf->len; 1463 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1464 xdp_return_frame_rx_napi(xdpf); 1465 else 1466 xdp_return_frame(xdpf); 1467 } 1468 num_tx++; 1469 } 1470 1471 if (!num_tx) 1472 return 0; 1473 1474 netif_txq = netdev_get_tx_queue(ndev, chn); 1475 1476 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1477 1478 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1479 1480 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1481 1482 return num_tx; 1483 } 1484 1485 static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer) 1486 { 1487 struct am65_cpsw_tx_chn *tx_chns = 1488 container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer); 1489 1490 enable_irq(tx_chns->irq); 1491 return HRTIMER_NORESTART; 1492 } 1493 1494 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1495 { 1496 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1497 bool tdown = false; 1498 int num_tx; 1499 1500 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1501 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, 1502 budget, &tdown); 1503 else 1504 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, 1505 tx_chn->id, budget, &tdown); 1506 1507 if (num_tx >= budget) 1508 return budget; 1509 1510 if (napi_complete_done(napi_tx, num_tx)) { 1511 if (unlikely(tx_chn->tx_pace_timeout && !tdown)) { 1512 hrtimer_start(&tx_chn->tx_hrtimer, 1513 ns_to_ktime(tx_chn->tx_pace_timeout), 1514 HRTIMER_MODE_REL_PINNED); 1515 } else { 1516 enable_irq(tx_chn->irq); 1517 } 1518 } 1519 1520 return 0; 1521 } 1522 1523 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1524 { 1525 struct am65_cpsw_rx_flow *flow = dev_id; 1526 1527 flow->irq_disabled = true; 1528 disable_irq_nosync(irq); 1529 napi_schedule(&flow->napi_rx); 1530 1531 return IRQ_HANDLED; 1532 } 1533 1534 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1535 { 1536 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1537 1538 disable_irq_nosync(irq); 1539 napi_schedule(&tx_chn->napi_tx); 1540 1541 return IRQ_HANDLED; 1542 } 1543 1544 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1545 struct net_device *ndev) 1546 { 1547 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1548 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1549 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1550 struct device *dev = common->dev; 1551 struct am65_cpsw_tx_chn *tx_chn; 1552 struct netdev_queue *netif_txq; 1553 dma_addr_t desc_dma, buf_dma; 1554 int ret, q_idx, i; 1555 void **swdata; 1556 u32 *psdata; 1557 u32 pkt_len; 1558 1559 /* padding enabled in hw */ 1560 pkt_len = skb_headlen(skb); 1561 1562 /* SKB TX timestamp */ 1563 if (port->tx_ts_enabled) 1564 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1565 1566 q_idx = skb_get_queue_mapping(skb); 1567 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1568 1569 tx_chn = &common->tx_chns[q_idx]; 1570 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1571 1572 /* Map the linear buffer */ 1573 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1574 DMA_TO_DEVICE); 1575 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1576 dev_err(dev, "Failed to map tx skb buffer\n"); 1577 ndev->stats.tx_errors++; 1578 goto err_free_skb; 1579 } 1580 1581 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1582 if (!first_desc) { 1583 dev_dbg(dev, "Failed to allocate descriptor\n"); 1584 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1585 DMA_TO_DEVICE); 1586 goto busy_stop_q; 1587 } 1588 1589 am65_cpsw_nuss_set_buf_type(tx_chn, first_desc, 1590 AM65_CPSW_TX_BUF_TYPE_SKB); 1591 1592 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1593 AM65_CPSW_NAV_PS_DATA_SIZE); 1594 cppi5_desc_set_pktids(&first_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1595 cppi5_hdesc_set_pkttype(first_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1596 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1597 1598 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1599 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1600 swdata = cppi5_hdesc_get_swdata(first_desc); 1601 *(swdata) = skb; 1602 psdata = cppi5_hdesc_get_psdata(first_desc); 1603 1604 /* HW csum offload if enabled */ 1605 psdata[2] = 0; 1606 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1607 unsigned int cs_start, cs_offset; 1608 1609 cs_start = skb_transport_offset(skb); 1610 cs_offset = cs_start + skb->csum_offset; 1611 /* HW numerates bytes starting from 1 */ 1612 psdata[2] = ((cs_offset + 1) << 24) | 1613 ((cs_start + 1) << 16) | (skb->len - cs_start); 1614 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1615 } 1616 1617 if (!skb_is_nonlinear(skb)) 1618 goto done_tx; 1619 1620 dev_dbg(dev, "fragmented SKB\n"); 1621 1622 /* Handle the case where skb is fragmented in pages */ 1623 cur_desc = first_desc; 1624 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1625 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1626 u32 frag_size = skb_frag_size(frag); 1627 1628 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1629 if (!next_desc) { 1630 dev_err(dev, "Failed to allocate descriptor\n"); 1631 goto busy_free_descs; 1632 } 1633 1634 am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, 1635 AM65_CPSW_TX_BUF_TYPE_SKB); 1636 1637 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1638 DMA_TO_DEVICE); 1639 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1640 dev_err(dev, "Failed to map tx skb page\n"); 1641 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1642 ndev->stats.tx_errors++; 1643 goto err_free_descs; 1644 } 1645 1646 cppi5_hdesc_reset_hbdesc(next_desc); 1647 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1648 cppi5_hdesc_attach_buf(next_desc, 1649 buf_dma, frag_size, buf_dma, frag_size); 1650 1651 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1652 next_desc); 1653 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1654 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1655 1656 pkt_len += frag_size; 1657 cur_desc = next_desc; 1658 } 1659 WARN_ON(pkt_len != skb->len); 1660 1661 done_tx: 1662 skb_tx_timestamp(skb); 1663 1664 /* report bql before sending packet */ 1665 netdev_tx_sent_queue(netif_txq, pkt_len); 1666 1667 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1668 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1669 if (AM65_CPSW_IS_CPSW2G(common)) { 1670 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1671 } else { 1672 spin_lock_bh(&tx_chn->lock); 1673 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1674 spin_unlock_bh(&tx_chn->lock); 1675 } 1676 if (ret) { 1677 dev_err(dev, "can't push desc %d\n", ret); 1678 /* inform bql */ 1679 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1680 ndev->stats.tx_errors++; 1681 goto err_free_descs; 1682 } 1683 1684 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1685 netif_tx_stop_queue(netif_txq); 1686 /* Barrier, so that stop_queue visible to other cpus */ 1687 smp_mb__after_atomic(); 1688 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1689 1690 /* re-check for smp */ 1691 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1692 MAX_SKB_FRAGS) { 1693 netif_tx_wake_queue(netif_txq); 1694 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1695 } 1696 } 1697 1698 return NETDEV_TX_OK; 1699 1700 err_free_descs: 1701 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1702 err_free_skb: 1703 ndev->stats.tx_dropped++; 1704 dev_kfree_skb_any(skb); 1705 return NETDEV_TX_OK; 1706 1707 busy_free_descs: 1708 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1709 busy_stop_q: 1710 netif_tx_stop_queue(netif_txq); 1711 return NETDEV_TX_BUSY; 1712 } 1713 1714 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1715 void *addr) 1716 { 1717 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1718 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1719 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1720 int ret; 1721 1722 ret = eth_prepare_mac_addr_change(ndev, addr); 1723 if (ret < 0) 1724 return ret; 1725 1726 ret = pm_runtime_resume_and_get(common->dev); 1727 if (ret < 0) 1728 return ret; 1729 1730 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1731 HOST_PORT_NUM, 0, 0); 1732 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1733 HOST_PORT_NUM, ALE_SECURE, 0); 1734 1735 am65_cpsw_port_set_sl_mac(port, addr); 1736 eth_commit_mac_addr_change(ndev, sockaddr); 1737 1738 pm_runtime_put(common->dev); 1739 1740 return 0; 1741 } 1742 1743 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1744 struct ifreq *ifr) 1745 { 1746 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1747 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1748 struct hwtstamp_config cfg; 1749 1750 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1751 return -EOPNOTSUPP; 1752 1753 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1754 return -EFAULT; 1755 1756 /* TX HW timestamp */ 1757 switch (cfg.tx_type) { 1758 case HWTSTAMP_TX_OFF: 1759 case HWTSTAMP_TX_ON: 1760 break; 1761 default: 1762 return -ERANGE; 1763 } 1764 1765 switch (cfg.rx_filter) { 1766 case HWTSTAMP_FILTER_NONE: 1767 port->rx_ts_enabled = false; 1768 break; 1769 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1770 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1771 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1772 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1773 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1774 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1775 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1776 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1777 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1778 port->rx_ts_enabled = true; 1779 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1780 break; 1781 case HWTSTAMP_FILTER_ALL: 1782 case HWTSTAMP_FILTER_SOME: 1783 case HWTSTAMP_FILTER_NTP_ALL: 1784 return -EOPNOTSUPP; 1785 default: 1786 return -ERANGE; 1787 } 1788 1789 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1790 1791 /* cfg TX timestamp */ 1792 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1793 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1794 1795 ts_vlan_ltype = ETH_P_8021Q; 1796 1797 ts_ctrl_ltype2 = ETH_P_1588 | 1798 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1799 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1800 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1801 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1802 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1803 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1804 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1805 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1806 1807 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1808 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1809 1810 if (port->tx_ts_enabled) 1811 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1812 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1813 1814 if (port->rx_ts_enabled) 1815 ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN | 1816 AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN; 1817 1818 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1819 writel(ts_vlan_ltype, port->port_base + 1820 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1821 writel(ts_ctrl_ltype2, port->port_base + 1822 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1823 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1824 1825 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1826 } 1827 1828 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1829 struct ifreq *ifr) 1830 { 1831 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1832 struct hwtstamp_config cfg; 1833 1834 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1835 return -EOPNOTSUPP; 1836 1837 cfg.flags = 0; 1838 cfg.tx_type = port->tx_ts_enabled ? 1839 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1840 cfg.rx_filter = port->rx_ts_enabled ? 1841 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE; 1842 1843 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1844 } 1845 1846 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1847 struct ifreq *req, int cmd) 1848 { 1849 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1850 1851 if (!netif_running(ndev)) 1852 return -EINVAL; 1853 1854 switch (cmd) { 1855 case SIOCSHWTSTAMP: 1856 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1857 case SIOCGHWTSTAMP: 1858 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1859 } 1860 1861 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1862 } 1863 1864 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1865 struct rtnl_link_stats64 *stats) 1866 { 1867 dev_fetch_sw_netstats(stats, dev->tstats); 1868 1869 stats->rx_errors = dev->stats.rx_errors; 1870 stats->rx_dropped = dev->stats.rx_dropped; 1871 stats->tx_dropped = dev->stats.tx_dropped; 1872 } 1873 1874 static int am65_cpsw_xdp_prog_setup(struct net_device *ndev, 1875 struct bpf_prog *prog) 1876 { 1877 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1878 bool running = netif_running(ndev); 1879 struct bpf_prog *old_prog; 1880 1881 if (running) 1882 am65_cpsw_nuss_ndo_slave_stop(ndev); 1883 1884 old_prog = xchg(&port->xdp_prog, prog); 1885 if (old_prog) 1886 bpf_prog_put(old_prog); 1887 1888 if (running) 1889 return am65_cpsw_nuss_ndo_slave_open(ndev); 1890 1891 return 0; 1892 } 1893 1894 static int am65_cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 1895 { 1896 switch (bpf->command) { 1897 case XDP_SETUP_PROG: 1898 return am65_cpsw_xdp_prog_setup(ndev, bpf->prog); 1899 default: 1900 return -EINVAL; 1901 } 1902 } 1903 1904 static int am65_cpsw_ndo_xdp_xmit(struct net_device *ndev, int n, 1905 struct xdp_frame **frames, u32 flags) 1906 { 1907 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1908 struct am65_cpsw_tx_chn *tx_chn; 1909 struct netdev_queue *netif_txq; 1910 int cpu = smp_processor_id(); 1911 int i, nxmit = 0; 1912 1913 tx_chn = &common->tx_chns[cpu % common->tx_ch_num]; 1914 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1915 1916 __netif_tx_lock(netif_txq, cpu); 1917 for (i = 0; i < n; i++) { 1918 if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], 1919 AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) 1920 break; 1921 nxmit++; 1922 } 1923 __netif_tx_unlock(netif_txq); 1924 1925 return nxmit; 1926 } 1927 1928 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1929 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1930 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1931 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1932 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1933 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1934 .ndo_validate_addr = eth_validate_addr, 1935 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1936 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1937 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1938 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1939 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1940 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1941 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 1942 .ndo_bpf = am65_cpsw_ndo_bpf, 1943 .ndo_xdp_xmit = am65_cpsw_ndo_xdp_xmit, 1944 }; 1945 1946 static void am65_cpsw_disable_phy(struct phy *phy) 1947 { 1948 phy_power_off(phy); 1949 phy_exit(phy); 1950 } 1951 1952 static int am65_cpsw_enable_phy(struct phy *phy) 1953 { 1954 int ret; 1955 1956 ret = phy_init(phy); 1957 if (ret < 0) 1958 return ret; 1959 1960 ret = phy_power_on(phy); 1961 if (ret < 0) { 1962 phy_exit(phy); 1963 return ret; 1964 } 1965 1966 return 0; 1967 } 1968 1969 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 1970 { 1971 struct am65_cpsw_port *port; 1972 struct phy *phy; 1973 int i; 1974 1975 for (i = 0; i < common->port_num; i++) { 1976 port = &common->ports[i]; 1977 phy = port->slave.serdes_phy; 1978 if (phy) 1979 am65_cpsw_disable_phy(phy); 1980 } 1981 } 1982 1983 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 1984 struct am65_cpsw_port *port) 1985 { 1986 const char *name = "serdes"; 1987 struct phy *phy; 1988 int ret; 1989 1990 phy = devm_of_phy_optional_get(dev, port_np, name); 1991 if (IS_ERR_OR_NULL(phy)) 1992 return PTR_ERR_OR_ZERO(phy); 1993 1994 /* Serdes PHY exists. Store it. */ 1995 port->slave.serdes_phy = phy; 1996 1997 ret = am65_cpsw_enable_phy(phy); 1998 if (ret < 0) 1999 goto err_phy; 2000 2001 return 0; 2002 2003 err_phy: 2004 devm_phy_put(dev, phy); 2005 return ret; 2006 } 2007 2008 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 2009 const struct phylink_link_state *state) 2010 { 2011 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2012 phylink_config); 2013 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2014 struct am65_cpsw_common *common = port->common; 2015 2016 if (common->pdata.extra_modes & BIT(state->interface)) { 2017 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 2018 writel(ADVERTISE_SGMII, 2019 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 2020 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2021 } else { 2022 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2023 } 2024 2025 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 2026 cpsw_sl_ctl_set(port->slave.mac_sl, 2027 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2028 } else { 2029 cpsw_sl_ctl_clr(port->slave.mac_sl, 2030 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2031 } 2032 2033 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 2034 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 2035 } 2036 } 2037 2038 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 2039 phy_interface_t interface) 2040 { 2041 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2042 phylink_config); 2043 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2044 struct am65_cpsw_common *common = port->common; 2045 struct net_device *ndev = port->ndev; 2046 u32 mac_control; 2047 int tmo; 2048 2049 /* disable forwarding */ 2050 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2051 2052 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2053 2054 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 2055 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 2056 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 2057 2058 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 2059 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 2060 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 2061 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 2062 if (phy_interface_mode_is_rgmii(interface)) 2063 mac_control |= CPSW_SL_CTL_EXT_EN; 2064 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 2065 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 2066 2067 am65_cpsw_qos_link_down(ndev); 2068 netif_tx_stop_all_queues(ndev); 2069 } 2070 2071 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 2072 unsigned int mode, phy_interface_t interface, int speed, 2073 int duplex, bool tx_pause, bool rx_pause) 2074 { 2075 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2076 phylink_config); 2077 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2078 struct am65_cpsw_common *common = port->common; 2079 u32 mac_control = CPSW_SL_CTL_GMII_EN; 2080 struct net_device *ndev = port->ndev; 2081 2082 /* Bring the port out of idle state */ 2083 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2084 2085 if (speed == SPEED_1000) 2086 mac_control |= CPSW_SL_CTL_GIG; 2087 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 2088 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 2089 /* Can be used with in band mode only */ 2090 mac_control |= CPSW_SL_CTL_EXT_EN; 2091 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 2092 mac_control |= CPSW_SL_CTL_IFCTL_A; 2093 if (duplex) 2094 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 2095 2096 /* rx_pause/tx_pause */ 2097 if (rx_pause) 2098 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 2099 2100 if (tx_pause) 2101 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 2102 2103 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 2104 2105 /* enable forwarding */ 2106 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2107 2108 am65_cpsw_qos_link_up(ndev, speed); 2109 netif_tx_wake_all_queues(ndev); 2110 } 2111 2112 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 2113 .mac_config = am65_cpsw_nuss_mac_config, 2114 .mac_link_down = am65_cpsw_nuss_mac_link_down, 2115 .mac_link_up = am65_cpsw_nuss_mac_link_up, 2116 }; 2117 2118 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 2119 { 2120 struct am65_cpsw_common *common = port->common; 2121 2122 if (!port->disabled) 2123 return; 2124 2125 cpsw_ale_control_set(common->ale, port->port_id, 2126 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2127 2128 cpsw_sl_reset(port->slave.mac_sl, 100); 2129 cpsw_sl_ctl_reset(port->slave.mac_sl); 2130 } 2131 2132 static void am65_cpsw_nuss_free_tx_chns(void *data) 2133 { 2134 struct am65_cpsw_common *common = data; 2135 int i; 2136 2137 for (i = 0; i < common->tx_ch_num; i++) { 2138 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2139 2140 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2141 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2142 2143 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2144 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2145 2146 memset(tx_chn, 0, sizeof(*tx_chn)); 2147 } 2148 } 2149 2150 static void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 2151 { 2152 struct device *dev = common->dev; 2153 int i; 2154 2155 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2156 2157 common->tx_ch_rate_msk = 0; 2158 for (i = 0; i < common->tx_ch_num; i++) { 2159 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2160 2161 if (tx_chn->irq) 2162 devm_free_irq(dev, tx_chn->irq, tx_chn); 2163 2164 netif_napi_del(&tx_chn->napi_tx); 2165 } 2166 2167 am65_cpsw_nuss_free_tx_chns(common); 2168 } 2169 2170 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2171 { 2172 struct device *dev = common->dev; 2173 int i, ret = 0; 2174 2175 for (i = 0; i < common->tx_ch_num; i++) { 2176 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2177 2178 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2179 am65_cpsw_nuss_tx_poll); 2180 hrtimer_init(&tx_chn->tx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2181 tx_chn->tx_hrtimer.function = &am65_cpsw_nuss_tx_timer_callback; 2182 2183 ret = devm_request_irq(dev, tx_chn->irq, 2184 am65_cpsw_nuss_tx_irq, 2185 IRQF_TRIGGER_HIGH, 2186 tx_chn->tx_chn_name, tx_chn); 2187 if (ret) { 2188 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2189 tx_chn->id, tx_chn->irq, ret); 2190 goto err; 2191 } 2192 } 2193 2194 err: 2195 return ret; 2196 } 2197 2198 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 2199 { 2200 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 2201 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 2202 struct device *dev = common->dev; 2203 struct k3_ring_cfg ring_cfg = { 2204 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2205 .mode = K3_RINGACC_RING_MODE_RING, 2206 .flags = 0 2207 }; 2208 u32 hdesc_size, hdesc_size_out; 2209 int i, ret = 0; 2210 2211 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2212 AM65_CPSW_NAV_SW_DATA_SIZE); 2213 2214 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2215 tx_cfg.tx_cfg = ring_cfg; 2216 tx_cfg.txcq_cfg = ring_cfg; 2217 tx_cfg.tx_cfg.size = max_desc_num; 2218 tx_cfg.txcq_cfg.size = max_desc_num; 2219 2220 for (i = 0; i < common->tx_ch_num; i++) { 2221 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2222 2223 snprintf(tx_chn->tx_chn_name, 2224 sizeof(tx_chn->tx_chn_name), "tx%d", i); 2225 2226 spin_lock_init(&tx_chn->lock); 2227 tx_chn->common = common; 2228 tx_chn->id = i; 2229 tx_chn->descs_num = max_desc_num; 2230 2231 tx_chn->tx_chn = 2232 k3_udma_glue_request_tx_chn(dev, 2233 tx_chn->tx_chn_name, 2234 &tx_cfg); 2235 if (IS_ERR(tx_chn->tx_chn)) { 2236 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 2237 "Failed to request tx dma channel\n"); 2238 goto err; 2239 } 2240 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 2241 2242 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 2243 tx_chn->descs_num, 2244 hdesc_size, 2245 tx_chn->tx_chn_name); 2246 if (IS_ERR(tx_chn->desc_pool)) { 2247 ret = PTR_ERR(tx_chn->desc_pool); 2248 dev_err(dev, "Failed to create poll %d\n", ret); 2249 goto err; 2250 } 2251 2252 hdesc_size_out = k3_cppi_desc_pool_desc_size(tx_chn->desc_pool); 2253 tx_chn->dsize_log2 = __fls(hdesc_size_out); 2254 WARN_ON(hdesc_size_out != (1 << tx_chn->dsize_log2)); 2255 2256 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 2257 if (tx_chn->irq < 0) { 2258 dev_err(dev, "Failed to get tx dma irq %d\n", 2259 tx_chn->irq); 2260 ret = tx_chn->irq; 2261 goto err; 2262 } 2263 2264 snprintf(tx_chn->tx_chn_name, 2265 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 2266 dev_name(dev), tx_chn->id); 2267 } 2268 2269 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2270 if (ret) { 2271 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 2272 goto err; 2273 } 2274 2275 err: 2276 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2277 if (i) { 2278 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 2279 return i; 2280 } 2281 2282 return ret; 2283 } 2284 2285 static void am65_cpsw_nuss_free_rx_chns(void *data) 2286 { 2287 struct am65_cpsw_common *common = data; 2288 struct am65_cpsw_rx_chn *rx_chn; 2289 2290 rx_chn = &common->rx_chns; 2291 2292 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 2293 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 2294 2295 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 2296 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 2297 } 2298 2299 static void am65_cpsw_nuss_remove_rx_chns(struct am65_cpsw_common *common) 2300 { 2301 struct device *dev = common->dev; 2302 struct am65_cpsw_rx_chn *rx_chn; 2303 struct am65_cpsw_rx_flow *flows; 2304 int i; 2305 2306 rx_chn = &common->rx_chns; 2307 flows = rx_chn->flows; 2308 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2309 2310 for (i = 0; i < common->rx_ch_num_flows; i++) { 2311 if (!(flows[i].irq < 0)) 2312 devm_free_irq(dev, flows[i].irq, &flows[i]); 2313 netif_napi_del(&flows[i].napi_rx); 2314 } 2315 2316 am65_cpsw_nuss_free_rx_chns(common); 2317 2318 common->rx_flow_id_base = -1; 2319 } 2320 2321 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 2322 { 2323 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 2324 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 2325 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 2326 struct device *dev = common->dev; 2327 struct am65_cpsw_rx_flow *flow; 2328 u32 hdesc_size, hdesc_size_out; 2329 u32 fdqring_id; 2330 int i, ret = 0; 2331 2332 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2333 AM65_CPSW_NAV_SW_DATA_SIZE); 2334 2335 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2336 rx_cfg.flow_id_num = common->rx_ch_num_flows; 2337 rx_cfg.flow_id_base = common->rx_flow_id_base; 2338 2339 /* init all flows */ 2340 rx_chn->dev = dev; 2341 rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; 2342 2343 for (i = 0; i < common->rx_ch_num_flows; i++) { 2344 flow = &rx_chn->flows[i]; 2345 flow->page_pool = NULL; 2346 flow->pages = devm_kcalloc(dev, AM65_CPSW_MAX_RX_DESC, 2347 sizeof(*flow->pages), GFP_KERNEL); 2348 if (!flow->pages) 2349 return -ENOMEM; 2350 } 2351 2352 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 2353 if (IS_ERR(rx_chn->rx_chn)) { 2354 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 2355 "Failed to request rx dma channel\n"); 2356 goto err; 2357 } 2358 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 2359 2360 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 2361 rx_chn->descs_num, 2362 hdesc_size, "rx"); 2363 if (IS_ERR(rx_chn->desc_pool)) { 2364 ret = PTR_ERR(rx_chn->desc_pool); 2365 dev_err(dev, "Failed to create rx poll %d\n", ret); 2366 goto err; 2367 } 2368 2369 hdesc_size_out = k3_cppi_desc_pool_desc_size(rx_chn->desc_pool); 2370 rx_chn->dsize_log2 = __fls(hdesc_size_out); 2371 WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); 2372 2373 common->rx_flow_id_base = 2374 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 2375 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 2376 2377 fdqring_id = K3_RINGACC_RING_ID_ANY; 2378 for (i = 0; i < rx_cfg.flow_id_num; i++) { 2379 struct k3_ring_cfg rxring_cfg = { 2380 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2381 .mode = K3_RINGACC_RING_MODE_RING, 2382 .flags = 0, 2383 }; 2384 struct k3_ring_cfg fdqring_cfg = { 2385 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2386 .flags = K3_RINGACC_RING_SHARED, 2387 }; 2388 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 2389 .rx_cfg = rxring_cfg, 2390 .rxfdq_cfg = fdqring_cfg, 2391 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 2392 .src_tag_lo_sel = 2393 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 2394 }; 2395 2396 flow = &rx_chn->flows[i]; 2397 flow->id = i; 2398 flow->common = common; 2399 2400 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 2401 rx_flow_cfg.rx_cfg.size = max_desc_num; 2402 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 2403 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 2404 2405 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 2406 i, &rx_flow_cfg); 2407 if (ret) { 2408 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 2409 goto err; 2410 } 2411 if (!i) 2412 fdqring_id = 2413 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 2414 i); 2415 2416 flow->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 2417 if (flow->irq <= 0) { 2418 dev_err(dev, "Failed to get rx dma irq %d\n", 2419 flow->irq); 2420 ret = flow->irq; 2421 goto err; 2422 } 2423 2424 snprintf(flow->name, 2425 sizeof(flow->name), "%s-rx%d", 2426 dev_name(dev), i); 2427 netif_napi_add(common->dma_ndev, &flow->napi_rx, 2428 am65_cpsw_nuss_rx_poll); 2429 hrtimer_init(&flow->rx_hrtimer, CLOCK_MONOTONIC, 2430 HRTIMER_MODE_REL_PINNED); 2431 flow->rx_hrtimer.function = &am65_cpsw_nuss_rx_timer_callback; 2432 2433 ret = devm_request_irq(dev, flow->irq, 2434 am65_cpsw_nuss_rx_irq, 2435 IRQF_TRIGGER_HIGH, 2436 flow->name, flow); 2437 if (ret) { 2438 dev_err(dev, "failure requesting rx %d irq %u, %d\n", 2439 i, flow->irq, ret); 2440 goto err; 2441 } 2442 } 2443 2444 /* setup classifier to route priorities to flows */ 2445 cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); 2446 2447 err: 2448 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2449 if (i) { 2450 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 2451 return i; 2452 } 2453 2454 return ret; 2455 } 2456 2457 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 2458 { 2459 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2460 2461 host_p->common = common; 2462 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 2463 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 2464 2465 return 0; 2466 } 2467 2468 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 2469 int slave, u8 *mac_addr) 2470 { 2471 u32 mac_lo, mac_hi, offset; 2472 struct regmap *syscon; 2473 int ret; 2474 2475 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 2476 if (IS_ERR(syscon)) { 2477 if (PTR_ERR(syscon) == -ENODEV) 2478 return 0; 2479 return PTR_ERR(syscon); 2480 } 2481 2482 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 2483 &offset); 2484 if (ret) 2485 return ret; 2486 2487 regmap_read(syscon, offset, &mac_lo); 2488 regmap_read(syscon, offset + 4, &mac_hi); 2489 2490 mac_addr[0] = (mac_hi >> 8) & 0xff; 2491 mac_addr[1] = mac_hi & 0xff; 2492 mac_addr[2] = (mac_lo >> 24) & 0xff; 2493 mac_addr[3] = (mac_lo >> 16) & 0xff; 2494 mac_addr[4] = (mac_lo >> 8) & 0xff; 2495 mac_addr[5] = mac_lo & 0xff; 2496 2497 return 0; 2498 } 2499 2500 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 2501 { 2502 struct device *dev = common->dev; 2503 struct device_node *node; 2504 struct am65_cpts *cpts; 2505 void __iomem *reg_base; 2506 2507 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 2508 return 0; 2509 2510 node = of_get_child_by_name(dev->of_node, "cpts"); 2511 if (!node) { 2512 dev_err(dev, "%s cpts not found\n", __func__); 2513 return -ENOENT; 2514 } 2515 2516 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 2517 cpts = am65_cpts_create(dev, reg_base, node); 2518 if (IS_ERR(cpts)) { 2519 int ret = PTR_ERR(cpts); 2520 2521 of_node_put(node); 2522 dev_err(dev, "cpts create err %d\n", ret); 2523 return ret; 2524 } 2525 common->cpts = cpts; 2526 /* Forbid PM runtime if CPTS is running. 2527 * K3 CPSWxG modules may completely lose context during ON->OFF 2528 * transitions depending on integration. 2529 * AM65x/J721E MCU CPSW2G: false 2530 * J721E MAIN_CPSW9G: true 2531 */ 2532 pm_runtime_forbid(dev); 2533 2534 return 0; 2535 } 2536 2537 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2538 { 2539 struct device_node *node, *port_np; 2540 struct device *dev = common->dev; 2541 int ret; 2542 2543 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2544 if (!node) 2545 return -ENOENT; 2546 2547 for_each_child_of_node(node, port_np) { 2548 struct am65_cpsw_port *port; 2549 u32 port_id; 2550 2551 /* it is not a slave port node, continue */ 2552 if (strcmp(port_np->name, "port")) 2553 continue; 2554 2555 ret = of_property_read_u32(port_np, "reg", &port_id); 2556 if (ret < 0) { 2557 dev_err(dev, "%pOF error reading port_id %d\n", 2558 port_np, ret); 2559 goto of_node_put; 2560 } 2561 2562 if (!port_id || port_id > common->port_num) { 2563 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2564 port_np, port_id, port_np->name); 2565 ret = -EINVAL; 2566 goto of_node_put; 2567 } 2568 2569 port = am65_common_get_port(common, port_id); 2570 port->port_id = port_id; 2571 port->common = common; 2572 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2573 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2574 if (common->pdata.extra_modes) 2575 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2576 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2577 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2578 port->name = of_get_property(port_np, "label", NULL); 2579 port->fetch_ram_base = 2580 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2581 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2582 2583 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2584 if (IS_ERR(port->slave.mac_sl)) { 2585 ret = PTR_ERR(port->slave.mac_sl); 2586 goto of_node_put; 2587 } 2588 2589 port->disabled = !of_device_is_available(port_np); 2590 if (port->disabled) { 2591 common->disabled_ports_mask |= BIT(port->port_id); 2592 continue; 2593 } 2594 2595 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2596 if (IS_ERR(port->slave.ifphy)) { 2597 ret = PTR_ERR(port->slave.ifphy); 2598 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2599 port_np, ret); 2600 goto of_node_put; 2601 } 2602 2603 /* Initialize the Serdes PHY for the port */ 2604 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2605 if (ret) 2606 goto of_node_put; 2607 2608 port->slave.mac_only = 2609 of_property_read_bool(port_np, "ti,mac-only"); 2610 2611 /* get phy/link info */ 2612 port->slave.port_np = port_np; 2613 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2614 if (ret) { 2615 dev_err(dev, "%pOF read phy-mode err %d\n", 2616 port_np, ret); 2617 goto of_node_put; 2618 } 2619 2620 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2621 if (ret) 2622 goto of_node_put; 2623 2624 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2625 if (ret) { 2626 am65_cpsw_am654_get_efuse_macid(port_np, 2627 port->port_id, 2628 port->slave.mac_addr); 2629 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2630 eth_random_addr(port->slave.mac_addr); 2631 dev_err(dev, "Use random MAC address\n"); 2632 } 2633 } 2634 2635 /* Reset all Queue priorities to 0 */ 2636 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); 2637 } 2638 of_node_put(node); 2639 2640 /* is there at least one ext.port */ 2641 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2642 dev_err(dev, "No Ext. port are available\n"); 2643 return -ENODEV; 2644 } 2645 2646 return 0; 2647 2648 of_node_put: 2649 of_node_put(port_np); 2650 of_node_put(node); 2651 return ret; 2652 } 2653 2654 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2655 { 2656 struct am65_cpsw_port *port; 2657 int i; 2658 2659 for (i = 0; i < common->port_num; i++) { 2660 port = &common->ports[i]; 2661 if (port->slave.phylink) 2662 phylink_destroy(port->slave.phylink); 2663 } 2664 } 2665 2666 static int 2667 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2668 { 2669 struct am65_cpsw_ndev_priv *ndev_priv; 2670 struct device *dev = common->dev; 2671 struct am65_cpsw_port *port; 2672 struct phylink *phylink; 2673 2674 port = &common->ports[port_idx]; 2675 2676 if (port->disabled) 2677 return 0; 2678 2679 /* alloc netdev */ 2680 port->ndev = alloc_etherdev_mqs(sizeof(struct am65_cpsw_ndev_priv), 2681 AM65_CPSW_MAX_QUEUES, 2682 AM65_CPSW_MAX_QUEUES); 2683 if (!port->ndev) { 2684 dev_err(dev, "error allocating slave net_device %u\n", 2685 port->port_id); 2686 return -ENOMEM; 2687 } 2688 2689 ndev_priv = netdev_priv(port->ndev); 2690 ndev_priv->port = port; 2691 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2692 mutex_init(&ndev_priv->mm_lock); 2693 port->qos.link_speed = SPEED_UNKNOWN; 2694 SET_NETDEV_DEV(port->ndev, dev); 2695 port->ndev->dev.of_node = port->slave.port_np; 2696 2697 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2698 2699 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2700 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE - 2701 (VLAN_ETH_HLEN + ETH_FCS_LEN); 2702 port->ndev->hw_features = NETIF_F_SG | 2703 NETIF_F_RXCSUM | 2704 NETIF_F_HW_CSUM | 2705 NETIF_F_HW_TC; 2706 port->ndev->features = port->ndev->hw_features | 2707 NETIF_F_HW_VLAN_CTAG_FILTER; 2708 port->ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 2709 NETDEV_XDP_ACT_REDIRECT | 2710 NETDEV_XDP_ACT_NDO_XMIT; 2711 port->ndev->vlan_features |= NETIF_F_SG; 2712 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2713 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2714 2715 /* Configuring Phylink */ 2716 port->slave.phylink_config.dev = &port->ndev->dev; 2717 port->slave.phylink_config.type = PHYLINK_NETDEV; 2718 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2719 MAC_1000FD | MAC_5000FD; 2720 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2721 2722 switch (port->slave.phy_if) { 2723 case PHY_INTERFACE_MODE_RGMII: 2724 case PHY_INTERFACE_MODE_RGMII_ID: 2725 case PHY_INTERFACE_MODE_RGMII_RXID: 2726 case PHY_INTERFACE_MODE_RGMII_TXID: 2727 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2728 break; 2729 2730 case PHY_INTERFACE_MODE_RMII: 2731 __set_bit(PHY_INTERFACE_MODE_RMII, 2732 port->slave.phylink_config.supported_interfaces); 2733 break; 2734 2735 case PHY_INTERFACE_MODE_QSGMII: 2736 case PHY_INTERFACE_MODE_SGMII: 2737 case PHY_INTERFACE_MODE_USXGMII: 2738 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2739 __set_bit(port->slave.phy_if, 2740 port->slave.phylink_config.supported_interfaces); 2741 } else { 2742 dev_err(dev, "selected phy-mode is not supported\n"); 2743 return -EOPNOTSUPP; 2744 } 2745 break; 2746 2747 default: 2748 dev_err(dev, "selected phy-mode is not supported\n"); 2749 return -EOPNOTSUPP; 2750 } 2751 2752 phylink = phylink_create(&port->slave.phylink_config, 2753 of_fwnode_handle(port->slave.port_np), 2754 port->slave.phy_if, 2755 &am65_cpsw_phylink_mac_ops); 2756 if (IS_ERR(phylink)) 2757 return PTR_ERR(phylink); 2758 2759 port->slave.phylink = phylink; 2760 2761 /* Disable TX checksum offload by default due to HW bug */ 2762 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2763 port->ndev->features &= ~NETIF_F_HW_CSUM; 2764 2765 port->ndev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 2766 port->xdp_prog = NULL; 2767 2768 if (!common->dma_ndev) 2769 common->dma_ndev = port->ndev; 2770 2771 return 0; 2772 } 2773 2774 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2775 { 2776 int ret; 2777 int i; 2778 2779 for (i = 0; i < common->port_num; i++) { 2780 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2781 if (ret) 2782 return ret; 2783 } 2784 2785 return ret; 2786 } 2787 2788 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2789 { 2790 struct am65_cpsw_port *port; 2791 int i; 2792 2793 for (i = 0; i < common->port_num; i++) { 2794 port = &common->ports[i]; 2795 if (!port->ndev) 2796 continue; 2797 if (port->ndev->reg_state == NETREG_REGISTERED) 2798 unregister_netdev(port->ndev); 2799 free_netdev(port->ndev); 2800 port->ndev = NULL; 2801 } 2802 } 2803 2804 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2805 { 2806 int set_val = 0; 2807 int i; 2808 2809 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2810 set_val = 1; 2811 2812 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2813 2814 for (i = 1; i <= common->port_num; i++) { 2815 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2816 struct am65_cpsw_ndev_priv *priv; 2817 2818 if (!port->ndev) 2819 continue; 2820 2821 priv = am65_ndev_to_priv(port->ndev); 2822 priv->offload_fwd_mark = set_val; 2823 } 2824 } 2825 2826 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2827 { 2828 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2829 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2830 2831 return !common->is_emac_mode; 2832 } 2833 2834 return false; 2835 } 2836 2837 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2838 struct net_device *br_ndev, 2839 struct netlink_ext_ack *extack) 2840 { 2841 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2842 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2843 int err; 2844 2845 if (!common->br_members) { 2846 common->hw_bridge_dev = br_ndev; 2847 } else { 2848 /* This is adding the port to a second bridge, this is 2849 * unsupported 2850 */ 2851 if (common->hw_bridge_dev != br_ndev) 2852 return -EOPNOTSUPP; 2853 } 2854 2855 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2856 false, extack); 2857 if (err) 2858 return err; 2859 2860 common->br_members |= BIT(priv->port->port_id); 2861 2862 am65_cpsw_port_offload_fwd_mark_update(common); 2863 2864 return NOTIFY_DONE; 2865 } 2866 2867 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2868 { 2869 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2870 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2871 2872 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2873 2874 common->br_members &= ~BIT(priv->port->port_id); 2875 2876 am65_cpsw_port_offload_fwd_mark_update(common); 2877 2878 if (!common->br_members) 2879 common->hw_bridge_dev = NULL; 2880 } 2881 2882 /* netdev notifier */ 2883 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2884 unsigned long event, void *ptr) 2885 { 2886 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2887 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2888 struct netdev_notifier_changeupper_info *info; 2889 int ret = NOTIFY_DONE; 2890 2891 if (!am65_cpsw_port_dev_check(ndev)) 2892 return NOTIFY_DONE; 2893 2894 switch (event) { 2895 case NETDEV_CHANGEUPPER: 2896 info = ptr; 2897 2898 if (netif_is_bridge_master(info->upper_dev)) { 2899 if (info->linking) 2900 ret = am65_cpsw_netdevice_port_link(ndev, 2901 info->upper_dev, 2902 extack); 2903 else 2904 am65_cpsw_netdevice_port_unlink(ndev); 2905 } 2906 break; 2907 default: 2908 return NOTIFY_DONE; 2909 } 2910 2911 return notifier_from_errno(ret); 2912 } 2913 2914 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2915 { 2916 int ret = 0; 2917 2918 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2919 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2920 return 0; 2921 2922 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2923 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2924 if (ret) { 2925 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2926 return ret; 2927 } 2928 2929 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2930 if (ret) 2931 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2932 2933 return ret; 2934 } 2935 2936 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2937 { 2938 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2939 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2940 return; 2941 2942 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2943 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2944 } 2945 2946 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2947 2948 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2949 { 2950 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2951 ALE_MCAST_BLOCK_LEARN_FWD); 2952 } 2953 2954 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2955 { 2956 struct am65_cpsw_host *host = am65_common_get_host(common); 2957 2958 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2959 2960 am65_cpsw_init_stp_ale_entry(common); 2961 2962 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2963 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2964 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2965 } 2966 2967 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2968 { 2969 struct am65_cpsw_host *host = am65_common_get_host(common); 2970 2971 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2972 2973 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2974 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2975 2976 /* learning make no sense in multi-mac mode */ 2977 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2978 } 2979 2980 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2981 struct devlink_param_gset_ctx *ctx) 2982 { 2983 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2984 struct am65_cpsw_common *common = dl_priv->common; 2985 2986 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2987 2988 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2989 return -EOPNOTSUPP; 2990 2991 ctx->val.vbool = !common->is_emac_mode; 2992 2993 return 0; 2994 } 2995 2996 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2997 { 2998 struct am65_cpsw_slave_data *slave = &port->slave; 2999 struct am65_cpsw_common *common = port->common; 3000 u32 port_mask; 3001 3002 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3003 3004 if (slave->mac_only) 3005 /* enable mac-only mode on port */ 3006 cpsw_ale_control_set(common->ale, port->port_id, 3007 ALE_PORT_MACONLY, 1); 3008 3009 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 3010 3011 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3012 3013 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 3014 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 3015 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 3016 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 3017 } 3018 3019 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 3020 { 3021 struct am65_cpsw_slave_data *slave = &port->slave; 3022 struct am65_cpsw_common *cpsw = port->common; 3023 u32 port_mask; 3024 3025 cpsw_ale_control_set(cpsw->ale, port->port_id, 3026 ALE_PORT_NOLEARN, 0); 3027 3028 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 3029 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 3030 slave->port_vlan); 3031 3032 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3033 3034 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 3035 port_mask, ALE_VLAN, slave->port_vlan, 3036 ALE_MCAST_FWD_2); 3037 3038 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3039 3040 cpsw_ale_control_set(cpsw->ale, port->port_id, 3041 ALE_PORT_MACONLY, 0); 3042 } 3043 3044 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 3045 struct devlink_param_gset_ctx *ctx, 3046 struct netlink_ext_ack *extack) 3047 { 3048 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3049 struct am65_cpsw_common *cpsw = dl_priv->common; 3050 bool switch_en = ctx->val.vbool; 3051 bool if_running = false; 3052 int i; 3053 3054 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 3055 3056 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3057 return -EOPNOTSUPP; 3058 3059 if (switch_en == !cpsw->is_emac_mode) 3060 return 0; 3061 3062 if (!switch_en && cpsw->br_members) { 3063 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 3064 return -EINVAL; 3065 } 3066 3067 rtnl_lock(); 3068 3069 cpsw->is_emac_mode = !switch_en; 3070 3071 for (i = 0; i < cpsw->port_num; i++) { 3072 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3073 3074 if (!sl_ndev || !netif_running(sl_ndev)) 3075 continue; 3076 3077 if_running = true; 3078 } 3079 3080 if (!if_running) { 3081 /* all ndevs are down */ 3082 for (i = 0; i < cpsw->port_num; i++) { 3083 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3084 struct am65_cpsw_slave_data *slave; 3085 3086 if (!sl_ndev) 3087 continue; 3088 3089 slave = am65_ndev_to_slave(sl_ndev); 3090 if (switch_en) 3091 slave->port_vlan = cpsw->default_vlan; 3092 else 3093 slave->port_vlan = 0; 3094 } 3095 3096 goto exit; 3097 } 3098 3099 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 3100 /* clean up ALE table */ 3101 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 3102 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 3103 3104 if (switch_en) { 3105 dev_info(cpsw->dev, "Enable switch mode\n"); 3106 3107 am65_cpsw_init_host_port_switch(cpsw); 3108 3109 for (i = 0; i < cpsw->port_num; i++) { 3110 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3111 struct am65_cpsw_slave_data *slave; 3112 struct am65_cpsw_port *port; 3113 3114 if (!sl_ndev) 3115 continue; 3116 3117 port = am65_ndev_to_port(sl_ndev); 3118 slave = am65_ndev_to_slave(sl_ndev); 3119 slave->port_vlan = cpsw->default_vlan; 3120 3121 if (netif_running(sl_ndev)) 3122 am65_cpsw_init_port_switch_ale(port); 3123 } 3124 3125 } else { 3126 dev_info(cpsw->dev, "Disable switch mode\n"); 3127 3128 am65_cpsw_init_host_port_emac(cpsw); 3129 3130 for (i = 0; i < cpsw->port_num; i++) { 3131 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3132 struct am65_cpsw_port *port; 3133 3134 if (!sl_ndev) 3135 continue; 3136 3137 port = am65_ndev_to_port(sl_ndev); 3138 port->slave.port_vlan = 0; 3139 if (netif_running(sl_ndev)) 3140 am65_cpsw_init_port_emac_ale(port); 3141 } 3142 } 3143 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 3144 exit: 3145 rtnl_unlock(); 3146 3147 return 0; 3148 } 3149 3150 static const struct devlink_param am65_cpsw_devlink_params[] = { 3151 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 3152 DEVLINK_PARAM_TYPE_BOOL, 3153 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3154 am65_cpsw_dl_switch_mode_get, 3155 am65_cpsw_dl_switch_mode_set, NULL), 3156 }; 3157 3158 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 3159 { 3160 struct devlink_port_attrs attrs = {}; 3161 struct am65_cpsw_devlink *dl_priv; 3162 struct device *dev = common->dev; 3163 struct devlink_port *dl_port; 3164 struct am65_cpsw_port *port; 3165 int ret = 0; 3166 int i; 3167 3168 common->devlink = 3169 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 3170 if (!common->devlink) 3171 return -ENOMEM; 3172 3173 dl_priv = devlink_priv(common->devlink); 3174 dl_priv->common = common; 3175 3176 /* Provide devlink hook to switch mode when multiple external ports 3177 * are present NUSS switchdev driver is enabled. 3178 */ 3179 if (!AM65_CPSW_IS_CPSW2G(common) && 3180 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 3181 ret = devlink_params_register(common->devlink, 3182 am65_cpsw_devlink_params, 3183 ARRAY_SIZE(am65_cpsw_devlink_params)); 3184 if (ret) { 3185 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 3186 goto dl_unreg; 3187 } 3188 } 3189 3190 for (i = 1; i <= common->port_num; i++) { 3191 port = am65_common_get_port(common, i); 3192 dl_port = &port->devlink_port; 3193 3194 if (port->ndev) 3195 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 3196 else 3197 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 3198 attrs.phys.port_number = port->port_id; 3199 attrs.switch_id.id_len = sizeof(resource_size_t); 3200 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 3201 devlink_port_attrs_set(dl_port, &attrs); 3202 3203 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 3204 if (ret) { 3205 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 3206 port->port_id, ret); 3207 goto dl_port_unreg; 3208 } 3209 } 3210 devlink_register(common->devlink); 3211 return ret; 3212 3213 dl_port_unreg: 3214 for (i = i - 1; i >= 1; i--) { 3215 port = am65_common_get_port(common, i); 3216 dl_port = &port->devlink_port; 3217 3218 devlink_port_unregister(dl_port); 3219 } 3220 dl_unreg: 3221 devlink_free(common->devlink); 3222 return ret; 3223 } 3224 3225 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 3226 { 3227 struct devlink_port *dl_port; 3228 struct am65_cpsw_port *port; 3229 int i; 3230 3231 devlink_unregister(common->devlink); 3232 3233 for (i = 1; i <= common->port_num; i++) { 3234 port = am65_common_get_port(common, i); 3235 dl_port = &port->devlink_port; 3236 3237 devlink_port_unregister(dl_port); 3238 } 3239 3240 if (!AM65_CPSW_IS_CPSW2G(common) && 3241 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3242 devlink_params_unregister(common->devlink, 3243 am65_cpsw_devlink_params, 3244 ARRAY_SIZE(am65_cpsw_devlink_params)); 3245 3246 devlink_free(common->devlink); 3247 } 3248 3249 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 3250 { 3251 struct am65_cpsw_rx_chn *rx_chan = &common->rx_chns; 3252 struct am65_cpsw_tx_chn *tx_chan = common->tx_chns; 3253 struct device *dev = common->dev; 3254 struct am65_cpsw_port *port; 3255 int ret = 0, i; 3256 3257 /* init tx channels */ 3258 ret = am65_cpsw_nuss_init_tx_chns(common); 3259 if (ret) 3260 return ret; 3261 ret = am65_cpsw_nuss_init_rx_chns(common); 3262 if (ret) 3263 return ret; 3264 3265 /* The DMA Channels are not guaranteed to be in a clean state. 3266 * Reset and disable them to ensure that they are back to the 3267 * clean state and ready to be used. 3268 */ 3269 for (i = 0; i < common->tx_ch_num; i++) { 3270 k3_udma_glue_reset_tx_chn(tx_chan[i].tx_chn, &tx_chan[i], 3271 am65_cpsw_nuss_tx_cleanup); 3272 k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); 3273 } 3274 3275 for (i = 0; i < common->rx_ch_num_flows; i++) 3276 k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, 3277 &rx_chan->flows[i], 3278 am65_cpsw_nuss_rx_cleanup, 0); 3279 3280 k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); 3281 3282 ret = am65_cpsw_nuss_register_devlink(common); 3283 if (ret) 3284 return ret; 3285 3286 for (i = 0; i < common->port_num; i++) { 3287 port = &common->ports[i]; 3288 3289 if (!port->ndev) 3290 continue; 3291 3292 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 3293 3294 ret = register_netdev(port->ndev); 3295 if (ret) { 3296 dev_err(dev, "error registering slave net device%i %d\n", 3297 i, ret); 3298 goto err_cleanup_ndev; 3299 } 3300 } 3301 3302 ret = am65_cpsw_register_notifiers(common); 3303 if (ret) 3304 goto err_cleanup_ndev; 3305 3306 /* can't auto unregister ndev using devm_add_action() due to 3307 * devres release sequence in DD core for DMA 3308 */ 3309 3310 return 0; 3311 3312 err_cleanup_ndev: 3313 am65_cpsw_nuss_cleanup_ndev(common); 3314 am65_cpsw_unregister_devlink(common); 3315 3316 return ret; 3317 } 3318 3319 int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, 3320 int num_tx, int num_rx) 3321 { 3322 int ret; 3323 3324 am65_cpsw_nuss_remove_tx_chns(common); 3325 am65_cpsw_nuss_remove_rx_chns(common); 3326 3327 common->tx_ch_num = num_tx; 3328 common->rx_ch_num_flows = num_rx; 3329 ret = am65_cpsw_nuss_init_tx_chns(common); 3330 if (ret) 3331 return ret; 3332 3333 ret = am65_cpsw_nuss_init_rx_chns(common); 3334 3335 return ret; 3336 } 3337 3338 struct am65_cpsw_soc_pdata { 3339 u32 quirks_dis; 3340 }; 3341 3342 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 3343 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3344 }; 3345 3346 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 3347 { .family = "AM65X", 3348 .revision = "SR2.0", 3349 .data = &am65x_soc_sr2_0 3350 }, 3351 {/* sentinel */} 3352 }; 3353 3354 static const struct am65_cpsw_pdata am65x_sr1_0 = { 3355 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3356 .ale_dev_id = "am65x-cpsw2g", 3357 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3358 }; 3359 3360 static const struct am65_cpsw_pdata j721e_pdata = { 3361 .quirks = 0, 3362 .ale_dev_id = "am65x-cpsw2g", 3363 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3364 }; 3365 3366 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 3367 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 3368 .ale_dev_id = "am64-cpswxg", 3369 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3370 }; 3371 3372 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 3373 .quirks = 0, 3374 .ale_dev_id = "am64-cpswxg", 3375 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3376 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3377 BIT(PHY_INTERFACE_MODE_USXGMII), 3378 }; 3379 3380 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 3381 .quirks = 0, 3382 .ale_dev_id = "am64-cpswxg", 3383 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3384 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3385 }; 3386 3387 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 3388 .quirks = 0, 3389 .ale_dev_id = "am64-cpswxg", 3390 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3391 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3392 BIT(PHY_INTERFACE_MODE_USXGMII), 3393 }; 3394 3395 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 3396 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 3397 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 3398 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 3399 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 3400 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 3401 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 3402 { /* sentinel */ }, 3403 }; 3404 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 3405 3406 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 3407 { 3408 const struct soc_device_attribute *soc; 3409 3410 soc = soc_device_match(am65_cpsw_socinfo); 3411 if (soc && soc->data) { 3412 const struct am65_cpsw_soc_pdata *socdata = soc->data; 3413 3414 /* disable quirks */ 3415 common->pdata.quirks &= ~socdata->quirks_dis; 3416 } 3417 } 3418 3419 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 3420 { 3421 struct cpsw_ale_params ale_params = { 0 }; 3422 const struct of_device_id *of_id; 3423 struct device *dev = &pdev->dev; 3424 struct am65_cpsw_common *common; 3425 struct device_node *node; 3426 struct resource *res; 3427 struct clk *clk; 3428 int ale_entries; 3429 __be64 id_temp; 3430 int ret, i; 3431 3432 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 3433 if (!common) 3434 return -ENOMEM; 3435 common->dev = dev; 3436 3437 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 3438 if (!of_id) 3439 return -EINVAL; 3440 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 3441 3442 am65_cpsw_nuss_apply_socinfo(common); 3443 3444 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 3445 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 3446 if (IS_ERR(common->ss_base)) 3447 return PTR_ERR(common->ss_base); 3448 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 3449 /* Use device's physical base address as switch id */ 3450 id_temp = cpu_to_be64(res->start); 3451 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 3452 3453 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 3454 if (!node) 3455 return -ENOENT; 3456 common->port_num = of_get_child_count(node); 3457 of_node_put(node); 3458 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 3459 return -ENOENT; 3460 3461 common->rx_flow_id_base = -1; 3462 init_completion(&common->tdown_complete); 3463 common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; 3464 common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; 3465 common->pf_p0_rx_ptype_rrobin = false; 3466 common->default_vlan = 1; 3467 3468 common->ports = devm_kcalloc(dev, common->port_num, 3469 sizeof(*common->ports), 3470 GFP_KERNEL); 3471 if (!common->ports) 3472 return -ENOMEM; 3473 3474 clk = devm_clk_get(dev, "fck"); 3475 if (IS_ERR(clk)) 3476 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 3477 common->bus_freq = clk_get_rate(clk); 3478 3479 pm_runtime_enable(dev); 3480 ret = pm_runtime_resume_and_get(dev); 3481 if (ret < 0) { 3482 pm_runtime_disable(dev); 3483 return ret; 3484 } 3485 3486 node = of_get_child_by_name(dev->of_node, "mdio"); 3487 if (!node) { 3488 dev_warn(dev, "MDIO node not found\n"); 3489 } else if (of_device_is_available(node)) { 3490 struct platform_device *mdio_pdev; 3491 3492 mdio_pdev = of_platform_device_create(node, NULL, dev); 3493 if (!mdio_pdev) { 3494 ret = -ENODEV; 3495 goto err_pm_clear; 3496 } 3497 3498 common->mdio_dev = &mdio_pdev->dev; 3499 } 3500 of_node_put(node); 3501 3502 am65_cpsw_nuss_get_ver(common); 3503 3504 ret = am65_cpsw_nuss_init_host_p(common); 3505 if (ret) 3506 goto err_of_clear; 3507 3508 ret = am65_cpsw_nuss_init_slave_ports(common); 3509 if (ret) 3510 goto err_of_clear; 3511 3512 /* init common data */ 3513 ale_params.dev = dev; 3514 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 3515 ale_params.ale_ports = common->port_num + 1; 3516 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 3517 ale_params.dev_id = common->pdata.ale_dev_id; 3518 ale_params.bus_freq = common->bus_freq; 3519 3520 common->ale = cpsw_ale_create(&ale_params); 3521 if (IS_ERR(common->ale)) { 3522 dev_err(dev, "error initializing ale engine\n"); 3523 ret = PTR_ERR(common->ale); 3524 goto err_of_clear; 3525 } 3526 3527 ale_entries = common->ale->params.ale_entries; 3528 common->ale_context = devm_kzalloc(dev, 3529 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 3530 GFP_KERNEL); 3531 ret = am65_cpsw_init_cpts(common); 3532 if (ret) 3533 goto err_of_clear; 3534 3535 /* init ports */ 3536 for (i = 0; i < common->port_num; i++) 3537 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 3538 3539 dev_set_drvdata(dev, common); 3540 3541 common->is_emac_mode = true; 3542 3543 ret = am65_cpsw_nuss_init_ndevs(common); 3544 if (ret) 3545 goto err_ndevs_clear; 3546 3547 ret = am65_cpsw_nuss_register_ndevs(common); 3548 if (ret) 3549 goto err_ndevs_clear; 3550 3551 pm_runtime_put(dev); 3552 return 0; 3553 3554 err_ndevs_clear: 3555 am65_cpsw_nuss_cleanup_ndev(common); 3556 am65_cpsw_nuss_phylink_cleanup(common); 3557 am65_cpts_release(common->cpts); 3558 err_of_clear: 3559 if (common->mdio_dev) 3560 of_platform_device_destroy(common->mdio_dev, NULL); 3561 err_pm_clear: 3562 pm_runtime_put_sync(dev); 3563 pm_runtime_disable(dev); 3564 return ret; 3565 } 3566 3567 static void am65_cpsw_nuss_remove(struct platform_device *pdev) 3568 { 3569 struct device *dev = &pdev->dev; 3570 struct am65_cpsw_common *common; 3571 int ret; 3572 3573 common = dev_get_drvdata(dev); 3574 3575 ret = pm_runtime_resume_and_get(&pdev->dev); 3576 if (ret < 0) { 3577 /* Note, if this error path is taken, we're leaking some 3578 * resources. 3579 */ 3580 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", 3581 ERR_PTR(ret)); 3582 return; 3583 } 3584 3585 am65_cpsw_unregister_notifiers(common); 3586 3587 /* must unregister ndevs here because DD release_driver routine calls 3588 * dma_deconfigure(dev) before devres_release_all(dev) 3589 */ 3590 am65_cpsw_nuss_cleanup_ndev(common); 3591 am65_cpsw_unregister_devlink(common); 3592 am65_cpsw_nuss_phylink_cleanup(common); 3593 am65_cpts_release(common->cpts); 3594 am65_cpsw_disable_serdes_phy(common); 3595 3596 if (common->mdio_dev) 3597 of_platform_device_destroy(common->mdio_dev, NULL); 3598 3599 pm_runtime_put_sync(&pdev->dev); 3600 pm_runtime_disable(&pdev->dev); 3601 } 3602 3603 static int am65_cpsw_nuss_suspend(struct device *dev) 3604 { 3605 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3606 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3607 struct am65_cpsw_port *port; 3608 struct net_device *ndev; 3609 int i, ret; 3610 3611 cpsw_ale_dump(common->ale, common->ale_context); 3612 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3613 for (i = 0; i < common->port_num; i++) { 3614 port = &common->ports[i]; 3615 ndev = port->ndev; 3616 3617 if (!ndev) 3618 continue; 3619 3620 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3621 netif_device_detach(ndev); 3622 if (netif_running(ndev)) { 3623 rtnl_lock(); 3624 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3625 rtnl_unlock(); 3626 if (ret < 0) { 3627 netdev_err(ndev, "failed to stop: %d", ret); 3628 return ret; 3629 } 3630 } 3631 } 3632 3633 am65_cpts_suspend(common->cpts); 3634 3635 am65_cpsw_nuss_remove_rx_chns(common); 3636 am65_cpsw_nuss_remove_tx_chns(common); 3637 3638 return 0; 3639 } 3640 3641 static int am65_cpsw_nuss_resume(struct device *dev) 3642 { 3643 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3644 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3645 struct am65_cpsw_port *port; 3646 struct net_device *ndev; 3647 int i, ret; 3648 3649 ret = am65_cpsw_nuss_init_tx_chns(common); 3650 if (ret) 3651 return ret; 3652 ret = am65_cpsw_nuss_init_rx_chns(common); 3653 if (ret) 3654 return ret; 3655 3656 /* If RX IRQ was disabled before suspend, keep it disabled */ 3657 for (i = 0; i < common->rx_ch_num_flows; i++) { 3658 if (common->rx_chns.flows[i].irq_disabled) 3659 disable_irq(common->rx_chns.flows[i].irq); 3660 } 3661 3662 am65_cpts_resume(common->cpts); 3663 3664 for (i = 0; i < common->port_num; i++) { 3665 port = &common->ports[i]; 3666 ndev = port->ndev; 3667 3668 if (!ndev) 3669 continue; 3670 3671 if (netif_running(ndev)) { 3672 rtnl_lock(); 3673 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3674 rtnl_unlock(); 3675 if (ret < 0) { 3676 netdev_err(ndev, "failed to start: %d", ret); 3677 return ret; 3678 } 3679 } 3680 3681 netif_device_attach(ndev); 3682 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3683 } 3684 3685 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3686 cpsw_ale_restore(common->ale, common->ale_context); 3687 3688 return 0; 3689 } 3690 3691 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3692 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3693 }; 3694 3695 static struct platform_driver am65_cpsw_nuss_driver = { 3696 .driver = { 3697 .name = AM65_CPSW_DRV_NAME, 3698 .of_match_table = am65_cpsw_nuss_of_mtable, 3699 .pm = &am65_cpsw_nuss_dev_pm_ops, 3700 }, 3701 .probe = am65_cpsw_nuss_probe, 3702 .remove = am65_cpsw_nuss_remove, 3703 }; 3704 3705 module_platform_driver(am65_cpsw_nuss_driver); 3706 3707 MODULE_LICENSE("GPL v2"); 3708 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3709 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3710