1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/bpf_trace.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/kmemleak.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/phylink.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/rtnetlink.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/sys_soc.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 #include <net/page_pool/helpers.h> 35 #include <net/dsa.h> 36 #include <net/switchdev.h> 37 38 #include "cpsw_ale.h" 39 #include "cpsw_sl.h" 40 #include "am65-cpsw-nuss.h" 41 #include "am65-cpsw-switchdev.h" 42 #include "k3-cppi-desc-pool.h" 43 #include "am65-cpts.h" 44 45 #define AM65_CPSW_SS_BASE 0x0 46 #define AM65_CPSW_SGMII_BASE 0x100 47 #define AM65_CPSW_XGMII_BASE 0x2100 48 #define AM65_CPSW_CPSW_NU_BASE 0x20000 49 #define AM65_CPSW_NU_PORTS_BASE 0x1000 50 #define AM65_CPSW_NU_FRAM_BASE 0x12000 51 #define AM65_CPSW_NU_STATS_BASE 0x1a000 52 #define AM65_CPSW_NU_ALE_BASE 0x1e000 53 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 54 55 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 56 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 57 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 58 59 #define AM65_CPSW_MAX_PORTS 8 60 61 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 62 #define AM65_CPSW_MAX_PACKET_SIZE 2024 63 64 #define AM65_CPSW_REG_CTL 0x004 65 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 66 #define AM65_CPSW_REG_PTYPE 0x018 67 68 #define AM65_CPSW_P0_REG_CTL 0x004 69 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 70 71 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 72 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 73 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 74 75 #define AM65_CPSW_PORTN_REG_CTL 0x004 76 #define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120 77 #define AM65_CPSW_PORTN_REG_SA_L 0x308 78 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 79 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 80 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 81 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 82 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 83 84 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 85 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 86 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 87 88 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 89 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 90 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 91 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 92 93 /* AM65_CPSW_P0_REG_CTL */ 94 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 95 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 96 97 /* AM65_CPSW_PORT_REG_PRI_CTL */ 98 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 99 100 /* AM65_CPSW_PN_REG_CTL */ 101 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1) 102 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2) 103 104 /* AM65_CPSW_PN_TS_CTL register fields */ 105 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 106 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 107 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 108 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 109 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 110 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 111 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 112 113 #define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0) 114 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1) 115 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2) 116 #define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3) 117 #define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9) 118 119 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 120 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 121 122 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 123 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 124 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 125 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 126 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 127 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 128 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 129 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 130 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 131 132 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 133 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 134 135 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 136 137 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 138 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 139 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 140 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 141 142 #define AM65_CPSW_TS_RX_ANX_ALL_EN \ 143 (AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \ 144 AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \ 145 AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) 146 147 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 148 /* Number of TX/RX descriptors per channel/flow */ 149 #define AM65_CPSW_MAX_TX_DESC 500 150 #define AM65_CPSW_MAX_RX_DESC 500 151 152 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 153 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 154 155 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 156 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 157 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 158 159 #define AM65_CPSW_DEFAULT_TX_CHNS 8 160 #define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 161 162 /* CPPI streaming packet interface */ 163 #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF 164 #define AM65_CPSW_CPPI_TX_PKT_TYPE 0x7 165 166 /* XDP */ 167 #define AM65_CPSW_XDP_CONSUMED BIT(1) 168 #define AM65_CPSW_XDP_REDIRECT BIT(0) 169 #define AM65_CPSW_XDP_PASS 0 170 171 /* Include headroom compatible with both skb and xdpf */ 172 #define AM65_CPSW_HEADROOM_NA (max(NET_SKB_PAD, XDP_PACKET_HEADROOM) + NET_IP_ALIGN) 173 #define AM65_CPSW_HEADROOM ALIGN(AM65_CPSW_HEADROOM_NA, sizeof(long)) 174 175 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 176 const u8 *dev_addr) 177 { 178 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 179 (dev_addr[2] << 16) | (dev_addr[3] << 24); 180 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 181 182 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 183 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 184 } 185 186 #define AM65_CPSW_DSCP_MAX GENMASK(5, 0) 187 #define AM65_CPSW_PRI_MAX GENMASK(2, 0) 188 #define AM65_CPSW_DSCP_PRI_PER_REG 8 189 #define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */ 190 static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri) 191 { 192 int reg_ofs; 193 int bit_ofs; 194 u32 val; 195 196 if (dscp > AM65_CPSW_DSCP_MAX) 197 return -EINVAL; 198 199 if (pri > AM65_CPSW_PRI_MAX) 200 return -EINVAL; 201 202 /* 32-bit register offset to this dscp */ 203 reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4; 204 /* bit field offset to this dscp */ 205 bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG); 206 207 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 208 val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */ 209 val |= pri << bit_ofs; /* set */ 210 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 211 212 return 0; 213 } 214 215 static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave) 216 { 217 int dscp, pri; 218 u32 val; 219 220 /* Default DSCP to User Priority mapping as per: 221 * https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 222 * and 223 * https://datatracker.ietf.org/doc/html/rfc8622#section-11 224 */ 225 for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) { 226 switch (dscp) { 227 case 56: /* CS7 */ 228 case 48: /* CS6 */ 229 pri = 7; 230 break; 231 case 46: /* EF */ 232 case 44: /* VA */ 233 pri = 6; 234 break; 235 case 40: /* CS5 */ 236 pri = 5; 237 break; 238 case 34: /* AF41 */ 239 case 36: /* AF42 */ 240 case 38: /* AF43 */ 241 case 32: /* CS4 */ 242 case 26: /* AF31 */ 243 case 28: /* AF32 */ 244 case 30: /* AF33 */ 245 case 24: /* CS3 */ 246 pri = 4; 247 break; 248 case 18: /* AF21 */ 249 case 20: /* AF22 */ 250 case 22: /* AF23 */ 251 pri = 3; 252 break; 253 case 16: /* CS2 */ 254 case 10: /* AF11 */ 255 case 12: /* AF12 */ 256 case 14: /* AF13 */ 257 case 0: /* DF */ 258 pri = 0; 259 break; 260 case 8: /* CS1 */ 261 case 1: /* LE */ 262 pri = 1; 263 break; 264 default: 265 pri = 0; 266 break; 267 } 268 269 am65_cpsw_port_set_dscp_map(slave, dscp, pri); 270 } 271 272 /* enable port IPV4 and IPV6 DSCP for this port */ 273 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL); 274 val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN | 275 AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN; 276 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL); 277 } 278 279 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 280 { 281 cpsw_sl_reset(port->slave.mac_sl, 100); 282 /* Max length register has to be restored after MAC SL reset */ 283 writel(AM65_CPSW_MAX_PACKET_SIZE, 284 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 285 } 286 287 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 288 { 289 common->nuss_ver = readl(common->ss_base); 290 common->cpsw_ver = readl(common->cpsw_base); 291 dev_info(common->dev, 292 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 293 common->nuss_ver, 294 common->cpsw_ver, 295 common->port_num + 1, 296 common->pdata.quirks); 297 } 298 299 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 300 __be16 proto, u16 vid) 301 { 302 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 303 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 304 u32 port_mask, unreg_mcast = 0; 305 int ret; 306 307 if (!common->is_emac_mode) 308 return 0; 309 310 if (!netif_running(ndev) || !vid) 311 return 0; 312 313 ret = pm_runtime_resume_and_get(common->dev); 314 if (ret < 0) 315 return ret; 316 317 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 318 if (!vid) 319 unreg_mcast = port_mask; 320 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 321 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 322 unreg_mcast, port_mask, 0); 323 324 pm_runtime_put(common->dev); 325 return ret; 326 } 327 328 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 329 __be16 proto, u16 vid) 330 { 331 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 332 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 333 int ret; 334 335 if (!common->is_emac_mode) 336 return 0; 337 338 if (!netif_running(ndev) || !vid) 339 return 0; 340 341 ret = pm_runtime_resume_and_get(common->dev); 342 if (ret < 0) 343 return ret; 344 345 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 346 ret = cpsw_ale_del_vlan(common->ale, vid, 347 BIT(port->port_id) | ALE_PORT_HOST); 348 349 pm_runtime_put(common->dev); 350 return ret; 351 } 352 353 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 354 bool promisc) 355 { 356 struct am65_cpsw_common *common = port->common; 357 358 if (promisc && !common->is_emac_mode) { 359 dev_dbg(common->dev, "promisc mode requested in switch mode"); 360 return; 361 } 362 363 if (promisc) { 364 /* Enable promiscuous mode */ 365 cpsw_ale_control_set(common->ale, port->port_id, 366 ALE_PORT_MACONLY_CAF, 1); 367 dev_dbg(common->dev, "promisc enabled\n"); 368 } else { 369 /* Disable promiscuous mode */ 370 cpsw_ale_control_set(common->ale, port->port_id, 371 ALE_PORT_MACONLY_CAF, 0); 372 dev_dbg(common->dev, "promisc disabled\n"); 373 } 374 } 375 376 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 377 { 378 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 379 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 380 u32 port_mask; 381 bool promisc; 382 383 promisc = !!(ndev->flags & IFF_PROMISC); 384 am65_cpsw_slave_set_promisc(port, promisc); 385 386 if (promisc) 387 return; 388 389 /* Restore allmulti on vlans if necessary */ 390 cpsw_ale_set_allmulti(common->ale, 391 ndev->flags & IFF_ALLMULTI, port->port_id); 392 393 port_mask = ALE_PORT_HOST; 394 /* Clear all mcast from ALE */ 395 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 396 397 if (!netdev_mc_empty(ndev)) { 398 struct netdev_hw_addr *ha; 399 400 /* program multicast address list into ALE register */ 401 netdev_for_each_mc_addr(ha, ndev) { 402 cpsw_ale_add_mcast(common->ale, ha->addr, 403 port_mask, 0, 0, 0); 404 } 405 } 406 } 407 408 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 409 unsigned int txqueue) 410 { 411 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 412 struct am65_cpsw_tx_chn *tx_chn; 413 struct netdev_queue *netif_txq; 414 unsigned long trans_start; 415 416 netif_txq = netdev_get_tx_queue(ndev, txqueue); 417 tx_chn = &common->tx_chns[txqueue]; 418 trans_start = READ_ONCE(netif_txq->trans_start); 419 420 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 421 txqueue, 422 netif_tx_queue_stopped(netif_txq), 423 jiffies_to_msecs(jiffies - trans_start), 424 netdev_queue_dql_avail(netif_txq), 425 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 426 427 if (netif_tx_queue_stopped(netif_txq)) { 428 /* try recover if stopped by us */ 429 txq_trans_update(netif_txq); 430 netif_tx_wake_queue(netif_txq); 431 } 432 } 433 434 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 435 struct page *page, u32 flow_idx) 436 { 437 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 438 struct cppi5_host_desc_t *desc_rx; 439 struct device *dev = common->dev; 440 struct am65_cpsw_swdata *swdata; 441 dma_addr_t desc_dma; 442 dma_addr_t buf_dma; 443 444 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 445 if (!desc_rx) { 446 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 447 return -ENOMEM; 448 } 449 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 450 451 buf_dma = dma_map_single(rx_chn->dma_dev, 452 page_address(page) + AM65_CPSW_HEADROOM, 453 AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); 454 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 455 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 456 dev_err(dev, "Failed to map rx buffer\n"); 457 return -EINVAL; 458 } 459 460 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 461 AM65_CPSW_NAV_PS_DATA_SIZE); 462 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 463 cppi5_hdesc_attach_buf(desc_rx, buf_dma, AM65_CPSW_MAX_PACKET_SIZE, 464 buf_dma, AM65_CPSW_MAX_PACKET_SIZE); 465 swdata = cppi5_hdesc_get_swdata(desc_rx); 466 swdata->page = page; 467 swdata->flow_id = flow_idx; 468 469 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, 470 desc_rx, desc_dma); 471 } 472 473 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 474 { 475 struct am65_cpsw_host *host_p = am65_common_get_host(common); 476 u32 val, pri_map; 477 478 /* P0 set Receive Priority Type */ 479 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 480 481 if (common->pf_p0_rx_ptype_rrobin) { 482 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 483 /* Enet Ports fifos works in fixed priority mode only, so 484 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 485 */ 486 pri_map = 0x0; 487 } else { 488 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 489 /* restore P0_Rx_Pri_Map */ 490 pri_map = 0x76543210; 491 } 492 493 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 494 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 495 } 496 497 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 498 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 499 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 500 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 501 502 static void am65_cpsw_destroy_xdp_rxqs(struct am65_cpsw_common *common) 503 { 504 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 505 struct am65_cpsw_rx_flow *flow; 506 struct xdp_rxq_info *rxq; 507 int id, port; 508 509 for (id = 0; id < common->rx_ch_num_flows; id++) { 510 flow = &rx_chn->flows[id]; 511 512 for (port = 0; port < common->port_num; port++) { 513 if (!common->ports[port].ndev) 514 continue; 515 516 rxq = &common->ports[port].xdp_rxq[id]; 517 518 if (xdp_rxq_info_is_reg(rxq)) 519 xdp_rxq_info_unreg(rxq); 520 } 521 522 if (flow->page_pool) { 523 page_pool_destroy(flow->page_pool); 524 flow->page_pool = NULL; 525 } 526 } 527 } 528 529 static int am65_cpsw_create_xdp_rxqs(struct am65_cpsw_common *common) 530 { 531 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 532 struct page_pool_params pp_params = { 533 .flags = PP_FLAG_DMA_MAP, 534 .order = 0, 535 .pool_size = AM65_CPSW_MAX_RX_DESC, 536 .nid = dev_to_node(common->dev), 537 .dev = common->dev, 538 .dma_dir = DMA_BIDIRECTIONAL, 539 /* .napi set dynamically */ 540 }; 541 struct am65_cpsw_rx_flow *flow; 542 struct xdp_rxq_info *rxq; 543 struct page_pool *pool; 544 int id, port, ret; 545 546 for (id = 0; id < common->rx_ch_num_flows; id++) { 547 flow = &rx_chn->flows[id]; 548 pp_params.napi = &flow->napi_rx; 549 pool = page_pool_create(&pp_params); 550 if (IS_ERR(pool)) { 551 ret = PTR_ERR(pool); 552 goto err; 553 } 554 555 flow->page_pool = pool; 556 557 /* using same page pool is allowed as no running rx handlers 558 * simultaneously for both ndevs 559 */ 560 for (port = 0; port < common->port_num; port++) { 561 if (!common->ports[port].ndev) 562 continue; 563 564 rxq = &common->ports[port].xdp_rxq[id]; 565 566 ret = xdp_rxq_info_reg(rxq, common->ports[port].ndev, 567 id, flow->napi_rx.napi_id); 568 if (ret) 569 goto err; 570 571 ret = xdp_rxq_info_reg_mem_model(rxq, 572 MEM_TYPE_PAGE_POOL, 573 pool); 574 if (ret) 575 goto err; 576 } 577 } 578 579 return 0; 580 581 err: 582 am65_cpsw_destroy_xdp_rxqs(common); 583 return ret; 584 } 585 586 static int am65_cpsw_nuss_desc_idx(struct k3_cppi_desc_pool *desc_pool, 587 void *desc, 588 unsigned char dsize_log2) 589 { 590 void *pool_addr = k3_cppi_desc_pool_cpuaddr(desc_pool); 591 592 return (desc - pool_addr) >> dsize_log2; 593 } 594 595 static void am65_cpsw_nuss_set_buf_type(struct am65_cpsw_tx_chn *tx_chn, 596 struct cppi5_host_desc_t *desc, 597 enum am65_cpsw_tx_buf_type buf_type) 598 { 599 int desc_idx; 600 601 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc, 602 tx_chn->dsize_log2); 603 k3_cppi_desc_pool_desc_info_set(tx_chn->desc_pool, desc_idx, 604 (void *)buf_type); 605 } 606 607 static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_chn *tx_chn, 608 dma_addr_t desc_dma) 609 { 610 struct cppi5_host_desc_t *desc_tx; 611 int desc_idx; 612 613 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 614 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc_tx, 615 tx_chn->dsize_log2); 616 617 return (enum am65_cpsw_tx_buf_type)k3_cppi_desc_pool_desc_info(tx_chn->desc_pool, 618 desc_idx); 619 } 620 621 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 622 struct page *page, 623 bool allow_direct) 624 { 625 page_pool_put_full_page(flow->page_pool, page, allow_direct); 626 } 627 628 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 629 { 630 struct am65_cpsw_rx_chn *rx_chn = data; 631 struct cppi5_host_desc_t *desc_rx; 632 struct am65_cpsw_swdata *swdata; 633 dma_addr_t buf_dma; 634 struct page *page; 635 u32 buf_dma_len; 636 u32 flow_id; 637 638 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 639 swdata = cppi5_hdesc_get_swdata(desc_rx); 640 page = swdata->page; 641 flow_id = swdata->flow_id; 642 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 643 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 644 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 645 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 646 647 am65_cpsw_put_page(&rx_chn->flows[flow_id], page, false); 648 } 649 650 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 651 struct cppi5_host_desc_t *desc) 652 { 653 struct cppi5_host_desc_t *first_desc, *next_desc; 654 dma_addr_t buf_dma, next_desc_dma; 655 u32 buf_dma_len; 656 657 first_desc = desc; 658 next_desc = first_desc; 659 660 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 661 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 662 663 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 664 665 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 666 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 667 while (next_desc_dma) { 668 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 669 next_desc_dma); 670 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 671 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 672 673 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 674 DMA_TO_DEVICE); 675 676 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 677 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 678 679 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 680 } 681 682 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 683 } 684 685 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 686 { 687 struct am65_cpsw_tx_chn *tx_chn = data; 688 struct cppi5_host_desc_t *desc_tx; 689 struct sk_buff *skb; 690 void **swdata; 691 692 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 693 swdata = cppi5_hdesc_get_swdata(desc_tx); 694 skb = *(swdata); 695 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 696 697 dev_kfree_skb_any(skb); 698 } 699 700 static struct sk_buff *am65_cpsw_build_skb(void *page_addr, 701 struct net_device *ndev, 702 unsigned int len) 703 { 704 struct sk_buff *skb; 705 706 len += AM65_CPSW_HEADROOM; 707 708 skb = build_skb(page_addr, len); 709 if (unlikely(!skb)) 710 return NULL; 711 712 skb_reserve(skb, AM65_CPSW_HEADROOM); 713 skb->dev = ndev; 714 715 return skb; 716 } 717 718 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 719 { 720 struct am65_cpsw_host *host_p = am65_common_get_host(common); 721 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 722 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 723 int port_idx, i, ret, tx, flow_idx; 724 struct am65_cpsw_rx_flow *flow; 725 u32 val, port_mask; 726 struct page *page; 727 728 if (common->usage_count) 729 return 0; 730 731 /* Control register */ 732 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 733 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 734 common->cpsw_base + AM65_CPSW_REG_CTL); 735 /* Max length register */ 736 writel(AM65_CPSW_MAX_PACKET_SIZE, 737 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 738 /* set base flow_id */ 739 writel(common->rx_flow_id_base, 740 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 741 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 742 host_p->port_base + AM65_CPSW_P0_REG_CTL); 743 744 am65_cpsw_nuss_set_p0_ptype(common); 745 746 /* enable statistic */ 747 val = BIT(HOST_PORT_NUM); 748 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 749 struct am65_cpsw_port *port = &common->ports[port_idx]; 750 751 if (!port->disabled) 752 val |= BIT(port->port_id); 753 } 754 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 755 756 /* disable priority elevation */ 757 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 758 759 cpsw_ale_start(common->ale); 760 761 /* limit to one RX flow only */ 762 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 763 ALE_DEFAULT_THREAD_ID, 0); 764 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 765 ALE_DEFAULT_THREAD_ENABLE, 1); 766 /* switch to vlan aware mode */ 767 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 768 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 769 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 770 771 /* default vlan cfg: create mask based on enabled ports */ 772 port_mask = GENMASK(common->port_num, 0) & 773 ~common->disabled_ports_mask; 774 775 cpsw_ale_add_vlan(common->ale, 0, port_mask, 776 port_mask, port_mask, 777 port_mask & ~ALE_PORT_HOST); 778 779 if (common->is_emac_mode) 780 am65_cpsw_init_host_port_emac(common); 781 else 782 am65_cpsw_init_host_port_switch(common); 783 784 am65_cpsw_qos_tx_p0_rate_init(common); 785 786 ret = am65_cpsw_create_xdp_rxqs(common); 787 if (ret) { 788 dev_err(common->dev, "Failed to create XDP rx queues\n"); 789 return ret; 790 } 791 792 for (flow_idx = 0; flow_idx < common->rx_ch_num_flows; flow_idx++) { 793 flow = &rx_chn->flows[flow_idx]; 794 for (i = 0; i < AM65_CPSW_MAX_RX_DESC; i++) { 795 page = page_pool_dev_alloc_pages(flow->page_pool); 796 if (!page) { 797 dev_err(common->dev, "cannot allocate page in flow %d\n", 798 flow_idx); 799 ret = -ENOMEM; 800 goto fail_rx; 801 } 802 803 ret = am65_cpsw_nuss_rx_push(common, page, flow_idx); 804 if (ret < 0) { 805 dev_err(common->dev, 806 "cannot submit page to rx channel flow %d, error %d\n", 807 flow_idx, ret); 808 am65_cpsw_put_page(flow, page, false); 809 goto fail_rx; 810 } 811 } 812 } 813 814 ret = k3_udma_glue_enable_rx_chn(rx_chn->rx_chn); 815 if (ret) { 816 dev_err(common->dev, "couldn't enable rx chn: %d\n", ret); 817 goto fail_rx; 818 } 819 820 for (i = 0; i < common->rx_ch_num_flows ; i++) { 821 napi_enable(&rx_chn->flows[i].napi_rx); 822 if (rx_chn->flows[i].irq_disabled) { 823 rx_chn->flows[i].irq_disabled = false; 824 enable_irq(rx_chn->flows[i].irq); 825 } 826 } 827 828 for (tx = 0; tx < common->tx_ch_num; tx++) { 829 ret = k3_udma_glue_enable_tx_chn(tx_chn[tx].tx_chn); 830 if (ret) { 831 dev_err(common->dev, "couldn't enable tx chn %d: %d\n", 832 tx, ret); 833 tx--; 834 goto fail_tx; 835 } 836 napi_enable(&tx_chn[tx].napi_tx); 837 } 838 839 dev_dbg(common->dev, "cpsw_nuss started\n"); 840 return 0; 841 842 fail_tx: 843 while (tx >= 0) { 844 napi_disable(&tx_chn[tx].napi_tx); 845 k3_udma_glue_disable_tx_chn(tx_chn[tx].tx_chn); 846 tx--; 847 } 848 849 for (flow_idx = 0; i < common->rx_ch_num_flows; flow_idx++) { 850 flow = &rx_chn->flows[flow_idx]; 851 if (!flow->irq_disabled) { 852 disable_irq(flow->irq); 853 flow->irq_disabled = true; 854 } 855 napi_disable(&flow->napi_rx); 856 } 857 858 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 859 860 fail_rx: 861 for (i = 0; i < common->rx_ch_num_flows; i++) 862 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, rx_chn, 863 am65_cpsw_nuss_rx_cleanup, !!i); 864 865 am65_cpsw_destroy_xdp_rxqs(common); 866 867 return ret; 868 } 869 870 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 871 { 872 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 873 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 874 int i; 875 876 if (common->usage_count != 1) 877 return 0; 878 879 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 880 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 881 882 /* shutdown tx channels */ 883 atomic_set(&common->tdown_cnt, common->tx_ch_num); 884 /* ensure new tdown_cnt value is visible */ 885 smp_mb__after_atomic(); 886 reinit_completion(&common->tdown_complete); 887 888 for (i = 0; i < common->tx_ch_num; i++) 889 k3_udma_glue_tdown_tx_chn(tx_chn[i].tx_chn, false); 890 891 i = wait_for_completion_timeout(&common->tdown_complete, 892 msecs_to_jiffies(1000)); 893 if (!i) 894 dev_err(common->dev, "tx timeout\n"); 895 for (i = 0; i < common->tx_ch_num; i++) { 896 napi_disable(&tx_chn[i].napi_tx); 897 hrtimer_cancel(&tx_chn[i].tx_hrtimer); 898 } 899 900 for (i = 0; i < common->tx_ch_num; i++) { 901 k3_udma_glue_reset_tx_chn(tx_chn[i].tx_chn, &tx_chn[i], 902 am65_cpsw_nuss_tx_cleanup); 903 k3_udma_glue_disable_tx_chn(tx_chn[i].tx_chn); 904 } 905 906 reinit_completion(&common->tdown_complete); 907 k3_udma_glue_tdown_rx_chn(rx_chn->rx_chn, true); 908 909 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 910 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 911 if (!i) 912 dev_err(common->dev, "rx teardown timeout\n"); 913 } 914 915 for (i = common->rx_ch_num_flows - 1; i >= 0; i--) { 916 napi_disable(&rx_chn->flows[i].napi_rx); 917 hrtimer_cancel(&rx_chn->flows[i].rx_hrtimer); 918 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, rx_chn, 919 am65_cpsw_nuss_rx_cleanup, !!i); 920 } 921 922 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 923 924 cpsw_ale_stop(common->ale); 925 926 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 927 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 928 929 am65_cpsw_destroy_xdp_rxqs(common); 930 931 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 932 return 0; 933 } 934 935 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 936 { 937 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 938 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 939 int ret; 940 941 phylink_stop(port->slave.phylink); 942 943 netif_tx_stop_all_queues(ndev); 944 945 phylink_disconnect_phy(port->slave.phylink); 946 947 ret = am65_cpsw_nuss_common_stop(common); 948 if (ret) 949 return ret; 950 951 common->usage_count--; 952 pm_runtime_put(common->dev); 953 return 0; 954 } 955 956 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 957 { 958 struct am65_cpsw_port *port = arg; 959 960 if (!vdev) 961 return 0; 962 963 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 964 } 965 966 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 967 { 968 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 969 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 970 int ret, i; 971 u32 reg; 972 973 ret = pm_runtime_resume_and_get(common->dev); 974 if (ret < 0) 975 return ret; 976 977 /* Idle MAC port */ 978 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 979 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 980 cpsw_sl_ctl_reset(port->slave.mac_sl); 981 982 /* soft reset MAC */ 983 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 984 mdelay(1); 985 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 986 if (reg) { 987 dev_err(common->dev, "soft RESET didn't complete\n"); 988 ret = -ETIMEDOUT; 989 goto runtime_put; 990 } 991 992 /* Notify the stack of the actual queue counts. */ 993 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 994 if (ret) { 995 dev_err(common->dev, "cannot set real number of tx queues\n"); 996 goto runtime_put; 997 } 998 999 ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); 1000 if (ret) { 1001 dev_err(common->dev, "cannot set real number of rx queues\n"); 1002 goto runtime_put; 1003 } 1004 1005 for (i = 0; i < common->tx_ch_num; i++) { 1006 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 1007 1008 netdev_tx_reset_queue(txq); 1009 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 1010 } 1011 1012 ret = am65_cpsw_nuss_common_open(common); 1013 if (ret) 1014 goto runtime_put; 1015 1016 common->usage_count++; 1017 1018 /* VLAN aware CPSW mode is incompatible with some DSA tagging schemes. 1019 * Therefore disable VLAN_AWARE mode if any of the ports is a DSA Port. 1020 */ 1021 if (netdev_uses_dsa(ndev)) { 1022 reg = readl(common->cpsw_base + AM65_CPSW_REG_CTL); 1023 reg &= ~AM65_CPSW_CTL_VLAN_AWARE; 1024 writel(reg, common->cpsw_base + AM65_CPSW_REG_CTL); 1025 } 1026 1027 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 1028 am65_cpsw_port_enable_dscp_map(port); 1029 1030 if (common->is_emac_mode) 1031 am65_cpsw_init_port_emac_ale(port); 1032 else 1033 am65_cpsw_init_port_switch_ale(port); 1034 1035 /* mac_sl should be configured via phy-link interface */ 1036 am65_cpsw_sl_ctl_reset(port); 1037 1038 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.port_np, 0); 1039 if (ret) 1040 goto error_cleanup; 1041 1042 /* restore vlan configurations */ 1043 vlan_for_each(ndev, cpsw_restore_vlans, port); 1044 1045 phylink_start(port->slave.phylink); 1046 1047 return 0; 1048 1049 error_cleanup: 1050 am65_cpsw_nuss_ndo_slave_stop(ndev); 1051 return ret; 1052 1053 runtime_put: 1054 pm_runtime_put(common->dev); 1055 return ret; 1056 } 1057 1058 static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, 1059 struct am65_cpsw_tx_chn *tx_chn, 1060 struct xdp_frame *xdpf, 1061 enum am65_cpsw_tx_buf_type buf_type) 1062 { 1063 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1064 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1065 struct cppi5_host_desc_t *host_desc; 1066 struct netdev_queue *netif_txq; 1067 dma_addr_t dma_desc, dma_buf; 1068 u32 pkt_len = xdpf->len; 1069 void **swdata; 1070 int ret; 1071 1072 host_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1073 if (unlikely(!host_desc)) { 1074 ndev->stats.tx_dropped++; 1075 return AM65_CPSW_XDP_CONSUMED; /* drop */ 1076 } 1077 1078 am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, buf_type); 1079 1080 dma_buf = dma_map_single(tx_chn->dma_dev, xdpf->data, 1081 pkt_len, DMA_TO_DEVICE); 1082 if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { 1083 ndev->stats.tx_dropped++; 1084 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1085 goto pool_free; 1086 } 1087 1088 cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1089 AM65_CPSW_NAV_PS_DATA_SIZE); 1090 cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1091 cppi5_hdesc_set_pktlen(host_desc, pkt_len); 1092 cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1093 cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); 1094 1095 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); 1096 cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); 1097 1098 swdata = cppi5_hdesc_get_swdata(host_desc); 1099 *(swdata) = xdpf; 1100 1101 /* Report BQL before sending the packet */ 1102 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1103 netdev_tx_sent_queue(netif_txq, pkt_len); 1104 1105 dma_desc = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); 1106 if (AM65_CPSW_IS_CPSW2G(common)) { 1107 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1108 dma_desc); 1109 } else { 1110 spin_lock_bh(&tx_chn->lock); 1111 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1112 dma_desc); 1113 spin_unlock_bh(&tx_chn->lock); 1114 } 1115 if (ret) { 1116 /* Inform BQL */ 1117 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1118 ndev->stats.tx_errors++; 1119 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1120 goto dma_unmap; 1121 } 1122 1123 return 0; 1124 1125 dma_unmap: 1126 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); 1127 dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); 1128 pool_free: 1129 k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); 1130 return ret; 1131 } 1132 1133 static int am65_cpsw_run_xdp(struct am65_cpsw_rx_flow *flow, 1134 struct am65_cpsw_port *port, 1135 struct xdp_buff *xdp, 1136 int cpu, int *len) 1137 { 1138 struct am65_cpsw_common *common = flow->common; 1139 struct net_device *ndev = port->ndev; 1140 int ret = AM65_CPSW_XDP_CONSUMED; 1141 struct am65_cpsw_tx_chn *tx_chn; 1142 struct netdev_queue *netif_txq; 1143 struct xdp_frame *xdpf; 1144 struct bpf_prog *prog; 1145 struct page *page; 1146 u32 act; 1147 int err; 1148 1149 prog = READ_ONCE(port->xdp_prog); 1150 if (!prog) 1151 return AM65_CPSW_XDP_PASS; 1152 1153 act = bpf_prog_run_xdp(prog, xdp); 1154 /* XDP prog might have changed packet data and boundaries */ 1155 *len = xdp->data_end - xdp->data; 1156 1157 switch (act) { 1158 case XDP_PASS: 1159 ret = AM65_CPSW_XDP_PASS; 1160 goto out; 1161 case XDP_TX: 1162 tx_chn = &common->tx_chns[cpu % AM65_CPSW_MAX_QUEUES]; 1163 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1164 1165 xdpf = xdp_convert_buff_to_frame(xdp); 1166 if (unlikely(!xdpf)) 1167 goto drop; 1168 1169 __netif_tx_lock(netif_txq, cpu); 1170 err = am65_cpsw_xdp_tx_frame(ndev, tx_chn, xdpf, 1171 AM65_CPSW_TX_BUF_TYPE_XDP_TX); 1172 __netif_tx_unlock(netif_txq); 1173 if (err) 1174 goto drop; 1175 1176 dev_sw_netstats_tx_add(ndev, 1, *len); 1177 ret = AM65_CPSW_XDP_CONSUMED; 1178 goto out; 1179 case XDP_REDIRECT: 1180 if (unlikely(xdp_do_redirect(ndev, xdp, prog))) 1181 goto drop; 1182 1183 dev_sw_netstats_rx_add(ndev, *len); 1184 ret = AM65_CPSW_XDP_REDIRECT; 1185 goto out; 1186 default: 1187 bpf_warn_invalid_xdp_action(ndev, prog, act); 1188 fallthrough; 1189 case XDP_ABORTED: 1190 drop: 1191 trace_xdp_exception(ndev, prog, act); 1192 fallthrough; 1193 case XDP_DROP: 1194 ndev->stats.rx_dropped++; 1195 } 1196 1197 page = virt_to_head_page(xdp->data); 1198 am65_cpsw_put_page(flow, page, true); 1199 1200 out: 1201 return ret; 1202 } 1203 1204 /* RX psdata[2] word format - checksum information */ 1205 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 1206 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 1207 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 1208 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 1209 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 1210 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 1211 1212 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 1213 { 1214 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 1215 * csum information provides in psdata[2] word: 1216 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 1217 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 1218 * bits - indicates IPv4/IPv6 packet 1219 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 1220 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 1221 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 1222 */ 1223 skb_checksum_none_assert(skb); 1224 1225 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 1226 return; 1227 1228 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 1229 AM65_CPSW_RX_PSD_IPV4_VALID)) && 1230 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 1231 /* csum for fragmented packets is unsupported */ 1232 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 1233 skb->ip_summed = CHECKSUM_UNNECESSARY; 1234 } 1235 } 1236 1237 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow, 1238 int cpu, int *xdp_state) 1239 { 1240 struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; 1241 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 1242 struct am65_cpsw_common *common = flow->common; 1243 struct am65_cpsw_ndev_priv *ndev_priv; 1244 struct cppi5_host_desc_t *desc_rx; 1245 struct device *dev = common->dev; 1246 struct am65_cpsw_swdata *swdata; 1247 struct page *page, *new_page; 1248 dma_addr_t desc_dma, buf_dma; 1249 struct am65_cpsw_port *port; 1250 struct net_device *ndev; 1251 u32 flow_idx = flow->id; 1252 struct sk_buff *skb; 1253 struct xdp_buff xdp; 1254 int headroom, ret; 1255 void *page_addr; 1256 u32 *psdata; 1257 1258 *xdp_state = AM65_CPSW_XDP_PASS; 1259 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 1260 if (ret) { 1261 if (ret != -ENODATA) 1262 dev_err(dev, "RX: pop chn fail %d\n", ret); 1263 return ret; 1264 } 1265 1266 if (cppi5_desc_is_tdcm(desc_dma)) { 1267 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 1268 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 1269 complete(&common->tdown_complete); 1270 return 0; 1271 } 1272 1273 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 1274 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 1275 __func__, flow_idx, &desc_dma); 1276 1277 swdata = cppi5_hdesc_get_swdata(desc_rx); 1278 page = swdata->page; 1279 page_addr = page_address(page); 1280 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 1281 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 1282 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 1283 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 1284 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 1285 port = am65_common_get_port(common, port_id); 1286 ndev = port->ndev; 1287 psdata = cppi5_hdesc_get_psdata(desc_rx); 1288 csum_info = psdata[2]; 1289 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 1290 1291 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 1292 1293 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 1294 1295 skb = am65_cpsw_build_skb(page_addr, ndev, 1296 AM65_CPSW_MAX_PACKET_SIZE); 1297 if (unlikely(!skb)) { 1298 new_page = page; 1299 goto requeue; 1300 } 1301 1302 if (port->xdp_prog) { 1303 xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq[flow->id]); 1304 xdp_prepare_buff(&xdp, page_addr, AM65_CPSW_HEADROOM, 1305 pkt_len, false); 1306 *xdp_state = am65_cpsw_run_xdp(flow, port, &xdp, 1307 cpu, &pkt_len); 1308 if (*xdp_state != AM65_CPSW_XDP_PASS) 1309 goto allocate; 1310 1311 /* Compute additional headroom to be reserved */ 1312 headroom = (xdp.data - xdp.data_hard_start) - skb_headroom(skb); 1313 skb_reserve(skb, headroom); 1314 } 1315 1316 ndev_priv = netdev_priv(ndev); 1317 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 1318 skb_put(skb, pkt_len); 1319 if (port->rx_ts_enabled) 1320 am65_cpts_rx_timestamp(common->cpts, skb); 1321 skb_mark_for_recycle(skb); 1322 skb->protocol = eth_type_trans(skb, ndev); 1323 am65_cpsw_nuss_rx_csum(skb, csum_info); 1324 napi_gro_receive(&flow->napi_rx, skb); 1325 1326 dev_sw_netstats_rx_add(ndev, pkt_len); 1327 1328 allocate: 1329 new_page = page_pool_dev_alloc_pages(flow->page_pool); 1330 if (unlikely(!new_page)) { 1331 dev_err(dev, "page alloc failed\n"); 1332 return -ENOMEM; 1333 } 1334 1335 if (netif_dormant(ndev)) { 1336 am65_cpsw_put_page(flow, new_page, true); 1337 ndev->stats.rx_dropped++; 1338 return 0; 1339 } 1340 1341 requeue: 1342 ret = am65_cpsw_nuss_rx_push(common, new_page, flow_idx); 1343 if (WARN_ON(ret < 0)) { 1344 am65_cpsw_put_page(flow, new_page, true); 1345 ndev->stats.rx_errors++; 1346 ndev->stats.rx_dropped++; 1347 } 1348 1349 return ret; 1350 } 1351 1352 static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) 1353 { 1354 struct am65_cpsw_rx_flow *flow = container_of(timer, 1355 struct am65_cpsw_rx_flow, 1356 rx_hrtimer); 1357 1358 enable_irq(flow->irq); 1359 return HRTIMER_NORESTART; 1360 } 1361 1362 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 1363 { 1364 struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); 1365 struct am65_cpsw_common *common = flow->common; 1366 int cpu = smp_processor_id(); 1367 int xdp_state_or = 0; 1368 int cur_budget, ret; 1369 int xdp_state; 1370 int num_rx = 0; 1371 1372 /* process only this flow */ 1373 cur_budget = budget; 1374 while (cur_budget--) { 1375 ret = am65_cpsw_nuss_rx_packets(flow, cpu, &xdp_state); 1376 xdp_state_or |= xdp_state; 1377 if (ret) 1378 break; 1379 num_rx++; 1380 } 1381 1382 if (xdp_state_or & AM65_CPSW_XDP_REDIRECT) 1383 xdp_do_flush(); 1384 1385 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 1386 1387 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1388 if (flow->irq_disabled) { 1389 flow->irq_disabled = false; 1390 if (unlikely(flow->rx_pace_timeout)) { 1391 hrtimer_start(&flow->rx_hrtimer, 1392 ns_to_ktime(flow->rx_pace_timeout), 1393 HRTIMER_MODE_REL_PINNED); 1394 } else { 1395 enable_irq(flow->irq); 1396 } 1397 } 1398 } 1399 1400 return num_rx; 1401 } 1402 1403 static struct sk_buff * 1404 am65_cpsw_nuss_tx_compl_packet_skb(struct am65_cpsw_tx_chn *tx_chn, 1405 dma_addr_t desc_dma) 1406 { 1407 struct cppi5_host_desc_t *desc_tx; 1408 struct sk_buff *skb; 1409 void **swdata; 1410 1411 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 1412 desc_dma); 1413 swdata = cppi5_hdesc_get_swdata(desc_tx); 1414 skb = *(swdata); 1415 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1416 1417 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 1418 1419 dev_sw_netstats_tx_add(skb->dev, 1, skb->len); 1420 1421 return skb; 1422 } 1423 1424 static struct xdp_frame * 1425 am65_cpsw_nuss_tx_compl_packet_xdp(struct am65_cpsw_common *common, 1426 struct am65_cpsw_tx_chn *tx_chn, 1427 dma_addr_t desc_dma, 1428 struct net_device **ndev) 1429 { 1430 struct cppi5_host_desc_t *desc_tx; 1431 struct am65_cpsw_port *port; 1432 struct xdp_frame *xdpf; 1433 u32 port_id = 0; 1434 void **swdata; 1435 1436 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 1437 cppi5_desc_get_tags_ids(&desc_tx->hdr, NULL, &port_id); 1438 swdata = cppi5_hdesc_get_swdata(desc_tx); 1439 xdpf = *(swdata); 1440 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1441 1442 port = am65_common_get_port(common, port_id); 1443 dev_sw_netstats_tx_add(port->ndev, 1, xdpf->len); 1444 *ndev = port->ndev; 1445 1446 return xdpf; 1447 } 1448 1449 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 1450 struct netdev_queue *netif_txq) 1451 { 1452 if (netif_tx_queue_stopped(netif_txq)) { 1453 /* Check whether the queue is stopped due to stalled 1454 * tx dma, if the queue is stopped then wake the queue 1455 * as we have free desc for tx 1456 */ 1457 __netif_tx_lock(netif_txq, smp_processor_id()); 1458 if (netif_running(ndev) && 1459 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 1460 netif_tx_wake_queue(netif_txq); 1461 1462 __netif_tx_unlock(netif_txq); 1463 } 1464 } 1465 1466 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 1467 int chn, unsigned int budget, bool *tdown) 1468 { 1469 enum am65_cpsw_tx_buf_type buf_type; 1470 struct device *dev = common->dev; 1471 struct am65_cpsw_tx_chn *tx_chn; 1472 struct netdev_queue *netif_txq; 1473 unsigned int total_bytes = 0; 1474 struct net_device *ndev; 1475 struct xdp_frame *xdpf; 1476 struct sk_buff *skb; 1477 dma_addr_t desc_dma; 1478 int res, num_tx = 0; 1479 1480 tx_chn = &common->tx_chns[chn]; 1481 1482 while (true) { 1483 spin_lock(&tx_chn->lock); 1484 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1485 spin_unlock(&tx_chn->lock); 1486 if (res == -ENODATA) 1487 break; 1488 1489 if (cppi5_desc_is_tdcm(desc_dma)) { 1490 if (atomic_dec_and_test(&common->tdown_cnt)) 1491 complete(&common->tdown_complete); 1492 *tdown = true; 1493 break; 1494 } 1495 1496 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1497 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1498 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1499 ndev = skb->dev; 1500 total_bytes = skb->len; 1501 napi_consume_skb(skb, budget); 1502 } else { 1503 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1504 desc_dma, &ndev); 1505 total_bytes = xdpf->len; 1506 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1507 xdp_return_frame_rx_napi(xdpf); 1508 else 1509 xdp_return_frame(xdpf); 1510 } 1511 num_tx++; 1512 1513 netif_txq = netdev_get_tx_queue(ndev, chn); 1514 1515 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1516 1517 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1518 } 1519 1520 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1521 1522 return num_tx; 1523 } 1524 1525 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 1526 int chn, unsigned int budget, bool *tdown) 1527 { 1528 enum am65_cpsw_tx_buf_type buf_type; 1529 struct device *dev = common->dev; 1530 struct am65_cpsw_tx_chn *tx_chn; 1531 struct netdev_queue *netif_txq; 1532 unsigned int total_bytes = 0; 1533 struct net_device *ndev; 1534 struct xdp_frame *xdpf; 1535 struct sk_buff *skb; 1536 dma_addr_t desc_dma; 1537 int res, num_tx = 0; 1538 1539 tx_chn = &common->tx_chns[chn]; 1540 1541 while (true) { 1542 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1543 if (res == -ENODATA) 1544 break; 1545 1546 if (cppi5_desc_is_tdcm(desc_dma)) { 1547 if (atomic_dec_and_test(&common->tdown_cnt)) 1548 complete(&common->tdown_complete); 1549 *tdown = true; 1550 break; 1551 } 1552 1553 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1554 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1555 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1556 ndev = skb->dev; 1557 total_bytes += skb->len; 1558 napi_consume_skb(skb, budget); 1559 } else { 1560 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1561 desc_dma, &ndev); 1562 total_bytes += xdpf->len; 1563 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1564 xdp_return_frame_rx_napi(xdpf); 1565 else 1566 xdp_return_frame(xdpf); 1567 } 1568 num_tx++; 1569 } 1570 1571 if (!num_tx) 1572 return 0; 1573 1574 netif_txq = netdev_get_tx_queue(ndev, chn); 1575 1576 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1577 1578 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1579 1580 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1581 1582 return num_tx; 1583 } 1584 1585 static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer) 1586 { 1587 struct am65_cpsw_tx_chn *tx_chns = 1588 container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer); 1589 1590 enable_irq(tx_chns->irq); 1591 return HRTIMER_NORESTART; 1592 } 1593 1594 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1595 { 1596 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1597 bool tdown = false; 1598 int num_tx; 1599 1600 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1601 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, 1602 budget, &tdown); 1603 else 1604 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, 1605 tx_chn->id, budget, &tdown); 1606 1607 if (num_tx >= budget) 1608 return budget; 1609 1610 if (napi_complete_done(napi_tx, num_tx)) { 1611 if (unlikely(tx_chn->tx_pace_timeout && !tdown)) { 1612 hrtimer_start(&tx_chn->tx_hrtimer, 1613 ns_to_ktime(tx_chn->tx_pace_timeout), 1614 HRTIMER_MODE_REL_PINNED); 1615 } else { 1616 enable_irq(tx_chn->irq); 1617 } 1618 } 1619 1620 return 0; 1621 } 1622 1623 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1624 { 1625 struct am65_cpsw_rx_flow *flow = dev_id; 1626 1627 flow->irq_disabled = true; 1628 disable_irq_nosync(irq); 1629 napi_schedule(&flow->napi_rx); 1630 1631 return IRQ_HANDLED; 1632 } 1633 1634 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1635 { 1636 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1637 1638 disable_irq_nosync(irq); 1639 napi_schedule(&tx_chn->napi_tx); 1640 1641 return IRQ_HANDLED; 1642 } 1643 1644 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1645 struct net_device *ndev) 1646 { 1647 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1648 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1649 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1650 struct device *dev = common->dev; 1651 struct am65_cpsw_tx_chn *tx_chn; 1652 struct netdev_queue *netif_txq; 1653 dma_addr_t desc_dma, buf_dma; 1654 int ret, q_idx, i; 1655 void **swdata; 1656 u32 *psdata; 1657 u32 pkt_len; 1658 1659 /* padding enabled in hw */ 1660 pkt_len = skb_headlen(skb); 1661 1662 /* SKB TX timestamp */ 1663 if (port->tx_ts_enabled) 1664 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1665 1666 q_idx = skb_get_queue_mapping(skb); 1667 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1668 1669 tx_chn = &common->tx_chns[q_idx]; 1670 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1671 1672 /* Map the linear buffer */ 1673 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1674 DMA_TO_DEVICE); 1675 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1676 dev_err(dev, "Failed to map tx skb buffer\n"); 1677 ndev->stats.tx_errors++; 1678 goto err_free_skb; 1679 } 1680 1681 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1682 if (!first_desc) { 1683 dev_dbg(dev, "Failed to allocate descriptor\n"); 1684 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1685 DMA_TO_DEVICE); 1686 goto busy_stop_q; 1687 } 1688 1689 am65_cpsw_nuss_set_buf_type(tx_chn, first_desc, 1690 AM65_CPSW_TX_BUF_TYPE_SKB); 1691 1692 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1693 AM65_CPSW_NAV_PS_DATA_SIZE); 1694 cppi5_desc_set_pktids(&first_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1695 cppi5_hdesc_set_pkttype(first_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1696 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1697 1698 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1699 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1700 swdata = cppi5_hdesc_get_swdata(first_desc); 1701 *(swdata) = skb; 1702 psdata = cppi5_hdesc_get_psdata(first_desc); 1703 1704 /* HW csum offload if enabled */ 1705 psdata[2] = 0; 1706 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1707 unsigned int cs_start, cs_offset; 1708 1709 cs_start = skb_transport_offset(skb); 1710 cs_offset = cs_start + skb->csum_offset; 1711 /* HW numerates bytes starting from 1 */ 1712 psdata[2] = ((cs_offset + 1) << 24) | 1713 ((cs_start + 1) << 16) | (skb->len - cs_start); 1714 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1715 } 1716 1717 if (!skb_is_nonlinear(skb)) 1718 goto done_tx; 1719 1720 dev_dbg(dev, "fragmented SKB\n"); 1721 1722 /* Handle the case where skb is fragmented in pages */ 1723 cur_desc = first_desc; 1724 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1725 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1726 u32 frag_size = skb_frag_size(frag); 1727 1728 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1729 if (!next_desc) { 1730 dev_err(dev, "Failed to allocate descriptor\n"); 1731 goto busy_free_descs; 1732 } 1733 1734 am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, 1735 AM65_CPSW_TX_BUF_TYPE_SKB); 1736 1737 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1738 DMA_TO_DEVICE); 1739 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1740 dev_err(dev, "Failed to map tx skb page\n"); 1741 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1742 ndev->stats.tx_errors++; 1743 goto err_free_descs; 1744 } 1745 1746 cppi5_hdesc_reset_hbdesc(next_desc); 1747 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1748 cppi5_hdesc_attach_buf(next_desc, 1749 buf_dma, frag_size, buf_dma, frag_size); 1750 1751 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1752 next_desc); 1753 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1754 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1755 1756 pkt_len += frag_size; 1757 cur_desc = next_desc; 1758 } 1759 WARN_ON(pkt_len != skb->len); 1760 1761 done_tx: 1762 skb_tx_timestamp(skb); 1763 1764 /* report bql before sending packet */ 1765 netdev_tx_sent_queue(netif_txq, pkt_len); 1766 1767 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1768 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1769 if (AM65_CPSW_IS_CPSW2G(common)) { 1770 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1771 } else { 1772 spin_lock_bh(&tx_chn->lock); 1773 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1774 spin_unlock_bh(&tx_chn->lock); 1775 } 1776 if (ret) { 1777 dev_err(dev, "can't push desc %d\n", ret); 1778 /* inform bql */ 1779 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1780 ndev->stats.tx_errors++; 1781 goto err_free_descs; 1782 } 1783 1784 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1785 netif_tx_stop_queue(netif_txq); 1786 /* Barrier, so that stop_queue visible to other cpus */ 1787 smp_mb__after_atomic(); 1788 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1789 1790 /* re-check for smp */ 1791 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1792 MAX_SKB_FRAGS) { 1793 netif_tx_wake_queue(netif_txq); 1794 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1795 } 1796 } 1797 1798 return NETDEV_TX_OK; 1799 1800 err_free_descs: 1801 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1802 err_free_skb: 1803 ndev->stats.tx_dropped++; 1804 dev_kfree_skb_any(skb); 1805 return NETDEV_TX_OK; 1806 1807 busy_free_descs: 1808 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1809 busy_stop_q: 1810 netif_tx_stop_queue(netif_txq); 1811 return NETDEV_TX_BUSY; 1812 } 1813 1814 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1815 void *addr) 1816 { 1817 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1818 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1819 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1820 int ret; 1821 1822 ret = eth_prepare_mac_addr_change(ndev, addr); 1823 if (ret < 0) 1824 return ret; 1825 1826 ret = pm_runtime_resume_and_get(common->dev); 1827 if (ret < 0) 1828 return ret; 1829 1830 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1831 HOST_PORT_NUM, 0, 0); 1832 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1833 HOST_PORT_NUM, ALE_SECURE, 0); 1834 1835 am65_cpsw_port_set_sl_mac(port, addr); 1836 eth_commit_mac_addr_change(ndev, sockaddr); 1837 1838 pm_runtime_put(common->dev); 1839 1840 return 0; 1841 } 1842 1843 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1844 struct ifreq *ifr) 1845 { 1846 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1847 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1848 struct hwtstamp_config cfg; 1849 1850 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1851 return -EOPNOTSUPP; 1852 1853 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1854 return -EFAULT; 1855 1856 /* TX HW timestamp */ 1857 switch (cfg.tx_type) { 1858 case HWTSTAMP_TX_OFF: 1859 case HWTSTAMP_TX_ON: 1860 break; 1861 default: 1862 return -ERANGE; 1863 } 1864 1865 switch (cfg.rx_filter) { 1866 case HWTSTAMP_FILTER_NONE: 1867 port->rx_ts_enabled = false; 1868 break; 1869 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1870 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1871 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1872 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1873 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1874 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1875 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1876 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1877 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1878 port->rx_ts_enabled = true; 1879 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1880 break; 1881 case HWTSTAMP_FILTER_ALL: 1882 case HWTSTAMP_FILTER_SOME: 1883 case HWTSTAMP_FILTER_NTP_ALL: 1884 return -EOPNOTSUPP; 1885 default: 1886 return -ERANGE; 1887 } 1888 1889 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1890 1891 /* cfg TX timestamp */ 1892 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1893 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1894 1895 ts_vlan_ltype = ETH_P_8021Q; 1896 1897 ts_ctrl_ltype2 = ETH_P_1588 | 1898 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1899 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1900 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1901 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1902 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1903 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1904 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1905 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1906 1907 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1908 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1909 1910 if (port->tx_ts_enabled) 1911 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1912 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1913 1914 if (port->rx_ts_enabled) 1915 ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN | 1916 AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN; 1917 1918 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1919 writel(ts_vlan_ltype, port->port_base + 1920 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1921 writel(ts_ctrl_ltype2, port->port_base + 1922 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1923 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1924 1925 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1926 } 1927 1928 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1929 struct ifreq *ifr) 1930 { 1931 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1932 struct hwtstamp_config cfg; 1933 1934 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1935 return -EOPNOTSUPP; 1936 1937 cfg.flags = 0; 1938 cfg.tx_type = port->tx_ts_enabled ? 1939 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1940 cfg.rx_filter = port->rx_ts_enabled ? 1941 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE; 1942 1943 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1944 } 1945 1946 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1947 struct ifreq *req, int cmd) 1948 { 1949 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1950 1951 if (!netif_running(ndev)) 1952 return -EINVAL; 1953 1954 switch (cmd) { 1955 case SIOCSHWTSTAMP: 1956 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1957 case SIOCGHWTSTAMP: 1958 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1959 } 1960 1961 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1962 } 1963 1964 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1965 struct rtnl_link_stats64 *stats) 1966 { 1967 dev_fetch_sw_netstats(stats, dev->tstats); 1968 1969 stats->rx_errors = dev->stats.rx_errors; 1970 stats->rx_dropped = dev->stats.rx_dropped; 1971 stats->tx_dropped = dev->stats.tx_dropped; 1972 } 1973 1974 static int am65_cpsw_xdp_prog_setup(struct net_device *ndev, 1975 struct bpf_prog *prog) 1976 { 1977 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1978 bool running = netif_running(ndev); 1979 struct bpf_prog *old_prog; 1980 1981 if (running) 1982 am65_cpsw_nuss_ndo_slave_stop(ndev); 1983 1984 old_prog = xchg(&port->xdp_prog, prog); 1985 if (old_prog) 1986 bpf_prog_put(old_prog); 1987 1988 if (running) 1989 return am65_cpsw_nuss_ndo_slave_open(ndev); 1990 1991 return 0; 1992 } 1993 1994 static int am65_cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 1995 { 1996 switch (bpf->command) { 1997 case XDP_SETUP_PROG: 1998 return am65_cpsw_xdp_prog_setup(ndev, bpf->prog); 1999 default: 2000 return -EINVAL; 2001 } 2002 } 2003 2004 static int am65_cpsw_ndo_xdp_xmit(struct net_device *ndev, int n, 2005 struct xdp_frame **frames, u32 flags) 2006 { 2007 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2008 struct am65_cpsw_tx_chn *tx_chn; 2009 struct netdev_queue *netif_txq; 2010 int cpu = smp_processor_id(); 2011 int i, nxmit = 0; 2012 2013 tx_chn = &common->tx_chns[cpu % common->tx_ch_num]; 2014 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 2015 2016 __netif_tx_lock(netif_txq, cpu); 2017 for (i = 0; i < n; i++) { 2018 if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], 2019 AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) 2020 break; 2021 nxmit++; 2022 } 2023 __netif_tx_unlock(netif_txq); 2024 2025 return nxmit; 2026 } 2027 2028 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 2029 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 2030 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 2031 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 2032 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 2033 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 2034 .ndo_validate_addr = eth_validate_addr, 2035 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 2036 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 2037 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 2038 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 2039 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 2040 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 2041 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 2042 .ndo_bpf = am65_cpsw_ndo_bpf, 2043 .ndo_xdp_xmit = am65_cpsw_ndo_xdp_xmit, 2044 }; 2045 2046 static void am65_cpsw_disable_phy(struct phy *phy) 2047 { 2048 phy_power_off(phy); 2049 phy_exit(phy); 2050 } 2051 2052 static int am65_cpsw_enable_phy(struct phy *phy) 2053 { 2054 int ret; 2055 2056 ret = phy_init(phy); 2057 if (ret < 0) 2058 return ret; 2059 2060 ret = phy_power_on(phy); 2061 if (ret < 0) { 2062 phy_exit(phy); 2063 return ret; 2064 } 2065 2066 return 0; 2067 } 2068 2069 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 2070 { 2071 struct am65_cpsw_port *port; 2072 struct phy *phy; 2073 int i; 2074 2075 for (i = 0; i < common->port_num; i++) { 2076 port = &common->ports[i]; 2077 phy = port->slave.serdes_phy; 2078 if (phy) 2079 am65_cpsw_disable_phy(phy); 2080 } 2081 } 2082 2083 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 2084 struct am65_cpsw_port *port) 2085 { 2086 const char *name = "serdes"; 2087 struct phy *phy; 2088 int ret; 2089 2090 phy = devm_of_phy_optional_get(dev, port_np, name); 2091 if (IS_ERR_OR_NULL(phy)) 2092 return PTR_ERR_OR_ZERO(phy); 2093 2094 /* Serdes PHY exists. Store it. */ 2095 port->slave.serdes_phy = phy; 2096 2097 ret = am65_cpsw_enable_phy(phy); 2098 if (ret < 0) 2099 goto err_phy; 2100 2101 return 0; 2102 2103 err_phy: 2104 devm_phy_put(dev, phy); 2105 return ret; 2106 } 2107 2108 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 2109 const struct phylink_link_state *state) 2110 { 2111 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2112 phylink_config); 2113 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2114 struct am65_cpsw_common *common = port->common; 2115 2116 if (common->pdata.extra_modes & BIT(state->interface)) { 2117 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 2118 writel(ADVERTISE_SGMII, 2119 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 2120 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2121 } else { 2122 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2123 } 2124 2125 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 2126 cpsw_sl_ctl_set(port->slave.mac_sl, 2127 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2128 } else { 2129 cpsw_sl_ctl_clr(port->slave.mac_sl, 2130 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2131 } 2132 2133 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 2134 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 2135 } 2136 } 2137 2138 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 2139 phy_interface_t interface) 2140 { 2141 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2142 phylink_config); 2143 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2144 struct am65_cpsw_common *common = port->common; 2145 struct net_device *ndev = port->ndev; 2146 u32 mac_control; 2147 int tmo; 2148 2149 /* disable forwarding */ 2150 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2151 2152 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2153 2154 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 2155 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 2156 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 2157 2158 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 2159 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 2160 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 2161 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 2162 if (phy_interface_mode_is_rgmii(interface)) 2163 mac_control |= CPSW_SL_CTL_EXT_EN; 2164 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 2165 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 2166 2167 am65_cpsw_qos_link_down(ndev); 2168 netif_tx_stop_all_queues(ndev); 2169 } 2170 2171 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 2172 unsigned int mode, phy_interface_t interface, int speed, 2173 int duplex, bool tx_pause, bool rx_pause) 2174 { 2175 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2176 phylink_config); 2177 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2178 struct am65_cpsw_common *common = port->common; 2179 u32 mac_control = CPSW_SL_CTL_GMII_EN; 2180 struct net_device *ndev = port->ndev; 2181 2182 /* Bring the port out of idle state */ 2183 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2184 2185 if (speed == SPEED_1000) 2186 mac_control |= CPSW_SL_CTL_GIG; 2187 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 2188 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 2189 /* Can be used with in band mode only */ 2190 mac_control |= CPSW_SL_CTL_EXT_EN; 2191 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 2192 mac_control |= CPSW_SL_CTL_IFCTL_A; 2193 if (duplex) 2194 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 2195 2196 /* rx_pause/tx_pause */ 2197 if (rx_pause) 2198 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 2199 2200 if (tx_pause) 2201 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 2202 2203 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 2204 2205 /* enable forwarding */ 2206 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2207 2208 am65_cpsw_qos_link_up(ndev, speed); 2209 netif_tx_wake_all_queues(ndev); 2210 } 2211 2212 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 2213 .mac_config = am65_cpsw_nuss_mac_config, 2214 .mac_link_down = am65_cpsw_nuss_mac_link_down, 2215 .mac_link_up = am65_cpsw_nuss_mac_link_up, 2216 }; 2217 2218 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 2219 { 2220 struct am65_cpsw_common *common = port->common; 2221 2222 if (!port->disabled) 2223 return; 2224 2225 cpsw_ale_control_set(common->ale, port->port_id, 2226 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2227 2228 cpsw_sl_reset(port->slave.mac_sl, 100); 2229 cpsw_sl_ctl_reset(port->slave.mac_sl); 2230 } 2231 2232 static void am65_cpsw_nuss_free_tx_chns(void *data) 2233 { 2234 struct am65_cpsw_common *common = data; 2235 int i; 2236 2237 for (i = 0; i < common->tx_ch_num; i++) { 2238 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2239 2240 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2241 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2242 2243 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2244 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2245 2246 memset(tx_chn, 0, sizeof(*tx_chn)); 2247 } 2248 } 2249 2250 static void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 2251 { 2252 struct device *dev = common->dev; 2253 int i; 2254 2255 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2256 2257 common->tx_ch_rate_msk = 0; 2258 for (i = 0; i < common->tx_ch_num; i++) { 2259 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2260 2261 if (tx_chn->irq) 2262 devm_free_irq(dev, tx_chn->irq, tx_chn); 2263 2264 netif_napi_del(&tx_chn->napi_tx); 2265 } 2266 2267 am65_cpsw_nuss_free_tx_chns(common); 2268 } 2269 2270 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2271 { 2272 struct device *dev = common->dev; 2273 int i, ret = 0; 2274 2275 for (i = 0; i < common->tx_ch_num; i++) { 2276 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2277 2278 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2279 am65_cpsw_nuss_tx_poll); 2280 hrtimer_init(&tx_chn->tx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2281 tx_chn->tx_hrtimer.function = &am65_cpsw_nuss_tx_timer_callback; 2282 2283 ret = devm_request_irq(dev, tx_chn->irq, 2284 am65_cpsw_nuss_tx_irq, 2285 IRQF_TRIGGER_HIGH, 2286 tx_chn->tx_chn_name, tx_chn); 2287 if (ret) { 2288 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2289 tx_chn->id, tx_chn->irq, ret); 2290 goto err; 2291 } 2292 } 2293 2294 err: 2295 return ret; 2296 } 2297 2298 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 2299 { 2300 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 2301 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 2302 struct device *dev = common->dev; 2303 struct k3_ring_cfg ring_cfg = { 2304 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2305 .mode = K3_RINGACC_RING_MODE_RING, 2306 .flags = 0 2307 }; 2308 u32 hdesc_size, hdesc_size_out; 2309 int i, ret = 0; 2310 2311 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2312 AM65_CPSW_NAV_SW_DATA_SIZE); 2313 2314 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2315 tx_cfg.tx_cfg = ring_cfg; 2316 tx_cfg.txcq_cfg = ring_cfg; 2317 tx_cfg.tx_cfg.size = max_desc_num; 2318 tx_cfg.txcq_cfg.size = max_desc_num; 2319 2320 for (i = 0; i < common->tx_ch_num; i++) { 2321 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2322 2323 snprintf(tx_chn->tx_chn_name, 2324 sizeof(tx_chn->tx_chn_name), "tx%d", i); 2325 2326 spin_lock_init(&tx_chn->lock); 2327 tx_chn->common = common; 2328 tx_chn->id = i; 2329 tx_chn->descs_num = max_desc_num; 2330 2331 tx_chn->tx_chn = 2332 k3_udma_glue_request_tx_chn(dev, 2333 tx_chn->tx_chn_name, 2334 &tx_cfg); 2335 if (IS_ERR(tx_chn->tx_chn)) { 2336 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 2337 "Failed to request tx dma channel\n"); 2338 goto err; 2339 } 2340 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 2341 2342 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 2343 tx_chn->descs_num, 2344 hdesc_size, 2345 tx_chn->tx_chn_name); 2346 if (IS_ERR(tx_chn->desc_pool)) { 2347 ret = PTR_ERR(tx_chn->desc_pool); 2348 dev_err(dev, "Failed to create poll %d\n", ret); 2349 goto err; 2350 } 2351 2352 hdesc_size_out = k3_cppi_desc_pool_desc_size(tx_chn->desc_pool); 2353 tx_chn->dsize_log2 = __fls(hdesc_size_out); 2354 WARN_ON(hdesc_size_out != (1 << tx_chn->dsize_log2)); 2355 2356 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 2357 if (tx_chn->irq < 0) { 2358 dev_err(dev, "Failed to get tx dma irq %d\n", 2359 tx_chn->irq); 2360 ret = tx_chn->irq; 2361 goto err; 2362 } 2363 2364 snprintf(tx_chn->tx_chn_name, 2365 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 2366 dev_name(dev), tx_chn->id); 2367 } 2368 2369 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2370 if (ret) { 2371 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 2372 goto err; 2373 } 2374 2375 err: 2376 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2377 if (i) { 2378 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 2379 return i; 2380 } 2381 2382 return ret; 2383 } 2384 2385 static void am65_cpsw_nuss_free_rx_chns(void *data) 2386 { 2387 struct am65_cpsw_common *common = data; 2388 struct am65_cpsw_rx_chn *rx_chn; 2389 2390 rx_chn = &common->rx_chns; 2391 2392 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 2393 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 2394 2395 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 2396 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 2397 } 2398 2399 static void am65_cpsw_nuss_remove_rx_chns(struct am65_cpsw_common *common) 2400 { 2401 struct device *dev = common->dev; 2402 struct am65_cpsw_rx_chn *rx_chn; 2403 struct am65_cpsw_rx_flow *flows; 2404 int i; 2405 2406 rx_chn = &common->rx_chns; 2407 flows = rx_chn->flows; 2408 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2409 2410 for (i = 0; i < common->rx_ch_num_flows; i++) { 2411 if (!(flows[i].irq < 0)) 2412 devm_free_irq(dev, flows[i].irq, &flows[i]); 2413 netif_napi_del(&flows[i].napi_rx); 2414 } 2415 2416 am65_cpsw_nuss_free_rx_chns(common); 2417 2418 common->rx_flow_id_base = -1; 2419 } 2420 2421 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 2422 { 2423 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 2424 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 2425 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 2426 struct device *dev = common->dev; 2427 struct am65_cpsw_rx_flow *flow; 2428 u32 hdesc_size, hdesc_size_out; 2429 u32 fdqring_id; 2430 int i, ret = 0; 2431 2432 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2433 AM65_CPSW_NAV_SW_DATA_SIZE); 2434 2435 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2436 rx_cfg.flow_id_num = common->rx_ch_num_flows; 2437 rx_cfg.flow_id_base = common->rx_flow_id_base; 2438 2439 /* init all flows */ 2440 rx_chn->dev = dev; 2441 rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; 2442 2443 for (i = 0; i < common->rx_ch_num_flows; i++) { 2444 flow = &rx_chn->flows[i]; 2445 flow->page_pool = NULL; 2446 } 2447 2448 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 2449 if (IS_ERR(rx_chn->rx_chn)) { 2450 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 2451 "Failed to request rx dma channel\n"); 2452 goto err; 2453 } 2454 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 2455 2456 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 2457 rx_chn->descs_num, 2458 hdesc_size, "rx"); 2459 if (IS_ERR(rx_chn->desc_pool)) { 2460 ret = PTR_ERR(rx_chn->desc_pool); 2461 dev_err(dev, "Failed to create rx poll %d\n", ret); 2462 goto err; 2463 } 2464 2465 hdesc_size_out = k3_cppi_desc_pool_desc_size(rx_chn->desc_pool); 2466 rx_chn->dsize_log2 = __fls(hdesc_size_out); 2467 WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); 2468 2469 common->rx_flow_id_base = 2470 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 2471 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 2472 2473 fdqring_id = K3_RINGACC_RING_ID_ANY; 2474 for (i = 0; i < rx_cfg.flow_id_num; i++) { 2475 struct k3_ring_cfg rxring_cfg = { 2476 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2477 .mode = K3_RINGACC_RING_MODE_RING, 2478 .flags = 0, 2479 }; 2480 struct k3_ring_cfg fdqring_cfg = { 2481 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2482 .flags = K3_RINGACC_RING_SHARED, 2483 }; 2484 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 2485 .rx_cfg = rxring_cfg, 2486 .rxfdq_cfg = fdqring_cfg, 2487 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 2488 .src_tag_lo_sel = 2489 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 2490 }; 2491 2492 flow = &rx_chn->flows[i]; 2493 flow->id = i; 2494 flow->common = common; 2495 flow->irq = -EINVAL; 2496 2497 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 2498 rx_flow_cfg.rx_cfg.size = max_desc_num; 2499 /* share same FDQ for all flows */ 2500 rx_flow_cfg.rxfdq_cfg.size = max_desc_num * rx_cfg.flow_id_num; 2501 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 2502 2503 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 2504 i, &rx_flow_cfg); 2505 if (ret) { 2506 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 2507 goto err; 2508 } 2509 if (!i) 2510 fdqring_id = 2511 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 2512 i); 2513 2514 flow->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 2515 if (flow->irq <= 0) { 2516 dev_err(dev, "Failed to get rx dma irq %d\n", 2517 flow->irq); 2518 ret = flow->irq; 2519 goto err; 2520 } 2521 2522 snprintf(flow->name, 2523 sizeof(flow->name), "%s-rx%d", 2524 dev_name(dev), i); 2525 netif_napi_add(common->dma_ndev, &flow->napi_rx, 2526 am65_cpsw_nuss_rx_poll); 2527 hrtimer_init(&flow->rx_hrtimer, CLOCK_MONOTONIC, 2528 HRTIMER_MODE_REL_PINNED); 2529 flow->rx_hrtimer.function = &am65_cpsw_nuss_rx_timer_callback; 2530 2531 ret = devm_request_irq(dev, flow->irq, 2532 am65_cpsw_nuss_rx_irq, 2533 IRQF_TRIGGER_HIGH, 2534 flow->name, flow); 2535 if (ret) { 2536 dev_err(dev, "failure requesting rx %d irq %u, %d\n", 2537 i, flow->irq, ret); 2538 flow->irq = -EINVAL; 2539 goto err; 2540 } 2541 } 2542 2543 /* setup classifier to route priorities to flows */ 2544 cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); 2545 2546 err: 2547 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2548 if (i) { 2549 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 2550 return i; 2551 } 2552 2553 return ret; 2554 } 2555 2556 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 2557 { 2558 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2559 2560 host_p->common = common; 2561 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 2562 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 2563 2564 return 0; 2565 } 2566 2567 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 2568 int slave, u8 *mac_addr) 2569 { 2570 u32 mac_lo, mac_hi, offset; 2571 struct regmap *syscon; 2572 2573 syscon = syscon_regmap_lookup_by_phandle_args(of_node, "ti,syscon-efuse", 2574 1, &offset); 2575 if (IS_ERR(syscon)) { 2576 if (PTR_ERR(syscon) == -ENODEV) 2577 return 0; 2578 return PTR_ERR(syscon); 2579 } 2580 2581 regmap_read(syscon, offset, &mac_lo); 2582 regmap_read(syscon, offset + 4, &mac_hi); 2583 2584 mac_addr[0] = (mac_hi >> 8) & 0xff; 2585 mac_addr[1] = mac_hi & 0xff; 2586 mac_addr[2] = (mac_lo >> 24) & 0xff; 2587 mac_addr[3] = (mac_lo >> 16) & 0xff; 2588 mac_addr[4] = (mac_lo >> 8) & 0xff; 2589 mac_addr[5] = mac_lo & 0xff; 2590 2591 return 0; 2592 } 2593 2594 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 2595 { 2596 struct device *dev = common->dev; 2597 struct device_node *node; 2598 struct am65_cpts *cpts; 2599 void __iomem *reg_base; 2600 2601 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 2602 return 0; 2603 2604 node = of_get_child_by_name(dev->of_node, "cpts"); 2605 if (!node) { 2606 dev_err(dev, "%s cpts not found\n", __func__); 2607 return -ENOENT; 2608 } 2609 2610 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 2611 cpts = am65_cpts_create(dev, reg_base, node); 2612 if (IS_ERR(cpts)) { 2613 int ret = PTR_ERR(cpts); 2614 2615 of_node_put(node); 2616 dev_err(dev, "cpts create err %d\n", ret); 2617 return ret; 2618 } 2619 common->cpts = cpts; 2620 /* Forbid PM runtime if CPTS is running. 2621 * K3 CPSWxG modules may completely lose context during ON->OFF 2622 * transitions depending on integration. 2623 * AM65x/J721E MCU CPSW2G: false 2624 * J721E MAIN_CPSW9G: true 2625 */ 2626 pm_runtime_forbid(dev); 2627 2628 return 0; 2629 } 2630 2631 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2632 { 2633 struct device_node *node, *port_np; 2634 struct device *dev = common->dev; 2635 int ret; 2636 2637 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2638 if (!node) 2639 return -ENOENT; 2640 2641 for_each_child_of_node(node, port_np) { 2642 struct am65_cpsw_port *port; 2643 u32 port_id; 2644 2645 /* it is not a slave port node, continue */ 2646 if (strcmp(port_np->name, "port")) 2647 continue; 2648 2649 ret = of_property_read_u32(port_np, "reg", &port_id); 2650 if (ret < 0) { 2651 dev_err(dev, "%pOF error reading port_id %d\n", 2652 port_np, ret); 2653 goto of_node_put; 2654 } 2655 2656 if (!port_id || port_id > common->port_num) { 2657 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2658 port_np, port_id, port_np->name); 2659 ret = -EINVAL; 2660 goto of_node_put; 2661 } 2662 2663 port = am65_common_get_port(common, port_id); 2664 port->port_id = port_id; 2665 port->common = common; 2666 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2667 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2668 if (common->pdata.extra_modes) 2669 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2670 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2671 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2672 port->name = of_get_property(port_np, "label", NULL); 2673 port->fetch_ram_base = 2674 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2675 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2676 2677 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2678 if (IS_ERR(port->slave.mac_sl)) { 2679 ret = PTR_ERR(port->slave.mac_sl); 2680 goto of_node_put; 2681 } 2682 2683 port->disabled = !of_device_is_available(port_np); 2684 if (port->disabled) { 2685 common->disabled_ports_mask |= BIT(port->port_id); 2686 continue; 2687 } 2688 2689 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2690 if (IS_ERR(port->slave.ifphy)) { 2691 ret = PTR_ERR(port->slave.ifphy); 2692 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2693 port_np, ret); 2694 goto of_node_put; 2695 } 2696 2697 /* Initialize the Serdes PHY for the port */ 2698 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2699 if (ret) 2700 goto of_node_put; 2701 2702 port->slave.mac_only = 2703 of_property_read_bool(port_np, "ti,mac-only"); 2704 2705 /* get phy/link info */ 2706 port->slave.port_np = port_np; 2707 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2708 if (ret) { 2709 dev_err(dev, "%pOF read phy-mode err %d\n", 2710 port_np, ret); 2711 goto of_node_put; 2712 } 2713 2714 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2715 if (ret) 2716 goto of_node_put; 2717 2718 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2719 if (ret) { 2720 am65_cpsw_am654_get_efuse_macid(port_np, 2721 port->port_id, 2722 port->slave.mac_addr); 2723 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2724 eth_random_addr(port->slave.mac_addr); 2725 dev_err(dev, "Use random MAC address\n"); 2726 } 2727 } 2728 2729 /* Reset all Queue priorities to 0 */ 2730 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); 2731 } 2732 of_node_put(node); 2733 2734 /* is there at least one ext.port */ 2735 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2736 dev_err(dev, "No Ext. port are available\n"); 2737 return -ENODEV; 2738 } 2739 2740 return 0; 2741 2742 of_node_put: 2743 of_node_put(port_np); 2744 of_node_put(node); 2745 return ret; 2746 } 2747 2748 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2749 { 2750 struct am65_cpsw_port *port; 2751 int i; 2752 2753 for (i = 0; i < common->port_num; i++) { 2754 port = &common->ports[i]; 2755 if (port->slave.phylink) 2756 phylink_destroy(port->slave.phylink); 2757 } 2758 } 2759 2760 static int 2761 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2762 { 2763 struct am65_cpsw_ndev_priv *ndev_priv; 2764 struct device *dev = common->dev; 2765 struct am65_cpsw_port *port; 2766 struct phylink *phylink; 2767 2768 port = &common->ports[port_idx]; 2769 2770 if (port->disabled) 2771 return 0; 2772 2773 /* alloc netdev */ 2774 port->ndev = alloc_etherdev_mqs(sizeof(struct am65_cpsw_ndev_priv), 2775 AM65_CPSW_MAX_QUEUES, 2776 AM65_CPSW_MAX_QUEUES); 2777 if (!port->ndev) { 2778 dev_err(dev, "error allocating slave net_device %u\n", 2779 port->port_id); 2780 return -ENOMEM; 2781 } 2782 2783 ndev_priv = netdev_priv(port->ndev); 2784 ndev_priv->port = port; 2785 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2786 mutex_init(&ndev_priv->mm_lock); 2787 port->qos.link_speed = SPEED_UNKNOWN; 2788 SET_NETDEV_DEV(port->ndev, dev); 2789 port->ndev->dev.of_node = port->slave.port_np; 2790 2791 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2792 2793 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2794 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE - 2795 (VLAN_ETH_HLEN + ETH_FCS_LEN); 2796 port->ndev->hw_features = NETIF_F_SG | 2797 NETIF_F_RXCSUM | 2798 NETIF_F_HW_CSUM | 2799 NETIF_F_HW_TC; 2800 port->ndev->features = port->ndev->hw_features | 2801 NETIF_F_HW_VLAN_CTAG_FILTER; 2802 port->ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 2803 NETDEV_XDP_ACT_REDIRECT | 2804 NETDEV_XDP_ACT_NDO_XMIT; 2805 port->ndev->vlan_features |= NETIF_F_SG; 2806 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2807 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2808 2809 /* Configuring Phylink */ 2810 port->slave.phylink_config.dev = &port->ndev->dev; 2811 port->slave.phylink_config.type = PHYLINK_NETDEV; 2812 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2813 MAC_1000FD | MAC_5000FD; 2814 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2815 2816 switch (port->slave.phy_if) { 2817 case PHY_INTERFACE_MODE_RGMII: 2818 case PHY_INTERFACE_MODE_RGMII_ID: 2819 case PHY_INTERFACE_MODE_RGMII_RXID: 2820 case PHY_INTERFACE_MODE_RGMII_TXID: 2821 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2822 break; 2823 2824 case PHY_INTERFACE_MODE_RMII: 2825 __set_bit(PHY_INTERFACE_MODE_RMII, 2826 port->slave.phylink_config.supported_interfaces); 2827 break; 2828 2829 case PHY_INTERFACE_MODE_QSGMII: 2830 case PHY_INTERFACE_MODE_SGMII: 2831 case PHY_INTERFACE_MODE_USXGMII: 2832 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2833 __set_bit(port->slave.phy_if, 2834 port->slave.phylink_config.supported_interfaces); 2835 } else { 2836 dev_err(dev, "selected phy-mode is not supported\n"); 2837 return -EOPNOTSUPP; 2838 } 2839 break; 2840 2841 default: 2842 dev_err(dev, "selected phy-mode is not supported\n"); 2843 return -EOPNOTSUPP; 2844 } 2845 2846 phylink = phylink_create(&port->slave.phylink_config, 2847 of_fwnode_handle(port->slave.port_np), 2848 port->slave.phy_if, 2849 &am65_cpsw_phylink_mac_ops); 2850 if (IS_ERR(phylink)) 2851 return PTR_ERR(phylink); 2852 2853 port->slave.phylink = phylink; 2854 2855 /* Disable TX checksum offload by default due to HW bug */ 2856 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2857 port->ndev->features &= ~NETIF_F_HW_CSUM; 2858 2859 port->ndev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 2860 port->xdp_prog = NULL; 2861 2862 if (!common->dma_ndev) 2863 common->dma_ndev = port->ndev; 2864 2865 return 0; 2866 } 2867 2868 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2869 { 2870 int ret; 2871 int i; 2872 2873 for (i = 0; i < common->port_num; i++) { 2874 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2875 if (ret) 2876 return ret; 2877 } 2878 2879 return ret; 2880 } 2881 2882 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2883 { 2884 struct am65_cpsw_port *port; 2885 int i; 2886 2887 for (i = 0; i < common->port_num; i++) { 2888 port = &common->ports[i]; 2889 if (!port->ndev) 2890 continue; 2891 if (port->ndev->reg_state == NETREG_REGISTERED) 2892 unregister_netdev(port->ndev); 2893 free_netdev(port->ndev); 2894 port->ndev = NULL; 2895 } 2896 } 2897 2898 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2899 { 2900 int set_val = 0; 2901 int i; 2902 2903 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2904 set_val = 1; 2905 2906 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2907 2908 for (i = 1; i <= common->port_num; i++) { 2909 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2910 struct am65_cpsw_ndev_priv *priv; 2911 2912 if (!port->ndev) 2913 continue; 2914 2915 priv = am65_ndev_to_priv(port->ndev); 2916 priv->offload_fwd_mark = set_val; 2917 } 2918 } 2919 2920 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2921 { 2922 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2923 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2924 2925 return !common->is_emac_mode; 2926 } 2927 2928 return false; 2929 } 2930 2931 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2932 struct net_device *br_ndev, 2933 struct netlink_ext_ack *extack) 2934 { 2935 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2936 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2937 int err; 2938 2939 if (!common->br_members) { 2940 common->hw_bridge_dev = br_ndev; 2941 } else { 2942 /* This is adding the port to a second bridge, this is 2943 * unsupported 2944 */ 2945 if (common->hw_bridge_dev != br_ndev) 2946 return -EOPNOTSUPP; 2947 } 2948 2949 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2950 false, extack); 2951 if (err) 2952 return err; 2953 2954 common->br_members |= BIT(priv->port->port_id); 2955 2956 am65_cpsw_port_offload_fwd_mark_update(common); 2957 2958 return NOTIFY_DONE; 2959 } 2960 2961 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2962 { 2963 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2964 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2965 2966 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2967 2968 common->br_members &= ~BIT(priv->port->port_id); 2969 2970 am65_cpsw_port_offload_fwd_mark_update(common); 2971 2972 if (!common->br_members) 2973 common->hw_bridge_dev = NULL; 2974 } 2975 2976 /* netdev notifier */ 2977 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2978 unsigned long event, void *ptr) 2979 { 2980 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2981 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2982 struct netdev_notifier_changeupper_info *info; 2983 int ret = NOTIFY_DONE; 2984 2985 if (!am65_cpsw_port_dev_check(ndev)) 2986 return NOTIFY_DONE; 2987 2988 switch (event) { 2989 case NETDEV_CHANGEUPPER: 2990 info = ptr; 2991 2992 if (netif_is_bridge_master(info->upper_dev)) { 2993 if (info->linking) 2994 ret = am65_cpsw_netdevice_port_link(ndev, 2995 info->upper_dev, 2996 extack); 2997 else 2998 am65_cpsw_netdevice_port_unlink(ndev); 2999 } 3000 break; 3001 default: 3002 return NOTIFY_DONE; 3003 } 3004 3005 return notifier_from_errno(ret); 3006 } 3007 3008 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 3009 { 3010 int ret = 0; 3011 3012 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3013 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3014 return 0; 3015 3016 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 3017 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3018 if (ret) { 3019 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 3020 return ret; 3021 } 3022 3023 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 3024 if (ret) 3025 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3026 3027 return ret; 3028 } 3029 3030 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 3031 { 3032 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3033 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3034 return; 3035 3036 am65_cpsw_switchdev_unregister_notifiers(cpsw); 3037 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3038 } 3039 3040 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 3041 3042 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 3043 { 3044 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 3045 ALE_MCAST_BLOCK_LEARN_FWD); 3046 } 3047 3048 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 3049 { 3050 struct am65_cpsw_host *host = am65_common_get_host(common); 3051 3052 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3053 3054 am65_cpsw_init_stp_ale_entry(common); 3055 3056 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 3057 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 3058 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 3059 } 3060 3061 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 3062 { 3063 struct am65_cpsw_host *host = am65_common_get_host(common); 3064 3065 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3066 3067 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 3068 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 3069 3070 /* learning make no sense in multi-mac mode */ 3071 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 3072 } 3073 3074 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 3075 struct devlink_param_gset_ctx *ctx) 3076 { 3077 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3078 struct am65_cpsw_common *common = dl_priv->common; 3079 3080 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 3081 3082 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3083 return -EOPNOTSUPP; 3084 3085 ctx->val.vbool = !common->is_emac_mode; 3086 3087 return 0; 3088 } 3089 3090 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 3091 { 3092 struct am65_cpsw_slave_data *slave = &port->slave; 3093 struct am65_cpsw_common *common = port->common; 3094 u32 port_mask; 3095 3096 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3097 3098 if (slave->mac_only) 3099 /* enable mac-only mode on port */ 3100 cpsw_ale_control_set(common->ale, port->port_id, 3101 ALE_PORT_MACONLY, 1); 3102 3103 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 3104 3105 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3106 3107 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 3108 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 3109 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 3110 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 3111 } 3112 3113 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 3114 { 3115 struct am65_cpsw_slave_data *slave = &port->slave; 3116 struct am65_cpsw_common *cpsw = port->common; 3117 u32 port_mask; 3118 3119 cpsw_ale_control_set(cpsw->ale, port->port_id, 3120 ALE_PORT_NOLEARN, 0); 3121 3122 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 3123 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 3124 slave->port_vlan); 3125 3126 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3127 3128 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 3129 port_mask, ALE_VLAN, slave->port_vlan, 3130 ALE_MCAST_FWD_2); 3131 3132 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3133 3134 cpsw_ale_control_set(cpsw->ale, port->port_id, 3135 ALE_PORT_MACONLY, 0); 3136 } 3137 3138 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 3139 struct devlink_param_gset_ctx *ctx, 3140 struct netlink_ext_ack *extack) 3141 { 3142 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3143 struct am65_cpsw_common *cpsw = dl_priv->common; 3144 bool switch_en = ctx->val.vbool; 3145 bool if_running = false; 3146 int i; 3147 3148 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 3149 3150 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3151 return -EOPNOTSUPP; 3152 3153 if (switch_en == !cpsw->is_emac_mode) 3154 return 0; 3155 3156 if (!switch_en && cpsw->br_members) { 3157 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 3158 return -EINVAL; 3159 } 3160 3161 rtnl_lock(); 3162 3163 cpsw->is_emac_mode = !switch_en; 3164 3165 for (i = 0; i < cpsw->port_num; i++) { 3166 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3167 3168 if (!sl_ndev || !netif_running(sl_ndev)) 3169 continue; 3170 3171 if_running = true; 3172 } 3173 3174 if (!if_running) { 3175 /* all ndevs are down */ 3176 for (i = 0; i < cpsw->port_num; i++) { 3177 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3178 struct am65_cpsw_slave_data *slave; 3179 3180 if (!sl_ndev) 3181 continue; 3182 3183 slave = am65_ndev_to_slave(sl_ndev); 3184 if (switch_en) 3185 slave->port_vlan = cpsw->default_vlan; 3186 else 3187 slave->port_vlan = 0; 3188 } 3189 3190 goto exit; 3191 } 3192 3193 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 3194 /* clean up ALE table */ 3195 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 3196 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 3197 3198 if (switch_en) { 3199 dev_info(cpsw->dev, "Enable switch mode\n"); 3200 3201 am65_cpsw_init_host_port_switch(cpsw); 3202 3203 for (i = 0; i < cpsw->port_num; i++) { 3204 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3205 struct am65_cpsw_slave_data *slave; 3206 struct am65_cpsw_port *port; 3207 3208 if (!sl_ndev) 3209 continue; 3210 3211 port = am65_ndev_to_port(sl_ndev); 3212 slave = am65_ndev_to_slave(sl_ndev); 3213 slave->port_vlan = cpsw->default_vlan; 3214 3215 if (netif_running(sl_ndev)) 3216 am65_cpsw_init_port_switch_ale(port); 3217 } 3218 3219 } else { 3220 dev_info(cpsw->dev, "Disable switch mode\n"); 3221 3222 am65_cpsw_init_host_port_emac(cpsw); 3223 3224 for (i = 0; i < cpsw->port_num; i++) { 3225 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3226 struct am65_cpsw_port *port; 3227 3228 if (!sl_ndev) 3229 continue; 3230 3231 port = am65_ndev_to_port(sl_ndev); 3232 port->slave.port_vlan = 0; 3233 if (netif_running(sl_ndev)) 3234 am65_cpsw_init_port_emac_ale(port); 3235 } 3236 } 3237 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 3238 exit: 3239 rtnl_unlock(); 3240 3241 return 0; 3242 } 3243 3244 static const struct devlink_param am65_cpsw_devlink_params[] = { 3245 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 3246 DEVLINK_PARAM_TYPE_BOOL, 3247 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3248 am65_cpsw_dl_switch_mode_get, 3249 am65_cpsw_dl_switch_mode_set, NULL), 3250 }; 3251 3252 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 3253 { 3254 struct devlink_port_attrs attrs = {}; 3255 struct am65_cpsw_devlink *dl_priv; 3256 struct device *dev = common->dev; 3257 struct devlink_port *dl_port; 3258 struct am65_cpsw_port *port; 3259 int ret = 0; 3260 int i; 3261 3262 common->devlink = 3263 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 3264 if (!common->devlink) 3265 return -ENOMEM; 3266 3267 dl_priv = devlink_priv(common->devlink); 3268 dl_priv->common = common; 3269 3270 /* Provide devlink hook to switch mode when multiple external ports 3271 * are present NUSS switchdev driver is enabled. 3272 */ 3273 if (!AM65_CPSW_IS_CPSW2G(common) && 3274 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 3275 ret = devlink_params_register(common->devlink, 3276 am65_cpsw_devlink_params, 3277 ARRAY_SIZE(am65_cpsw_devlink_params)); 3278 if (ret) { 3279 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 3280 goto dl_unreg; 3281 } 3282 } 3283 3284 for (i = 1; i <= common->port_num; i++) { 3285 port = am65_common_get_port(common, i); 3286 dl_port = &port->devlink_port; 3287 3288 if (port->ndev) 3289 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 3290 else 3291 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 3292 attrs.phys.port_number = port->port_id; 3293 attrs.switch_id.id_len = sizeof(resource_size_t); 3294 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 3295 devlink_port_attrs_set(dl_port, &attrs); 3296 3297 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 3298 if (ret) { 3299 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 3300 port->port_id, ret); 3301 goto dl_port_unreg; 3302 } 3303 } 3304 devlink_register(common->devlink); 3305 return ret; 3306 3307 dl_port_unreg: 3308 for (i = i - 1; i >= 1; i--) { 3309 port = am65_common_get_port(common, i); 3310 dl_port = &port->devlink_port; 3311 3312 devlink_port_unregister(dl_port); 3313 } 3314 dl_unreg: 3315 devlink_free(common->devlink); 3316 return ret; 3317 } 3318 3319 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 3320 { 3321 struct devlink_port *dl_port; 3322 struct am65_cpsw_port *port; 3323 int i; 3324 3325 devlink_unregister(common->devlink); 3326 3327 for (i = 1; i <= common->port_num; i++) { 3328 port = am65_common_get_port(common, i); 3329 dl_port = &port->devlink_port; 3330 3331 devlink_port_unregister(dl_port); 3332 } 3333 3334 if (!AM65_CPSW_IS_CPSW2G(common) && 3335 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3336 devlink_params_unregister(common->devlink, 3337 am65_cpsw_devlink_params, 3338 ARRAY_SIZE(am65_cpsw_devlink_params)); 3339 3340 devlink_free(common->devlink); 3341 } 3342 3343 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 3344 { 3345 struct am65_cpsw_rx_chn *rx_chan = &common->rx_chns; 3346 struct am65_cpsw_tx_chn *tx_chan = common->tx_chns; 3347 struct device *dev = common->dev; 3348 struct am65_cpsw_port *port; 3349 int ret = 0, i; 3350 3351 /* init tx channels */ 3352 ret = am65_cpsw_nuss_init_tx_chns(common); 3353 if (ret) 3354 return ret; 3355 ret = am65_cpsw_nuss_init_rx_chns(common); 3356 if (ret) 3357 return ret; 3358 3359 /* The DMA Channels are not guaranteed to be in a clean state. 3360 * Reset and disable them to ensure that they are back to the 3361 * clean state and ready to be used. 3362 */ 3363 for (i = 0; i < common->tx_ch_num; i++) { 3364 k3_udma_glue_reset_tx_chn(tx_chan[i].tx_chn, &tx_chan[i], 3365 am65_cpsw_nuss_tx_cleanup); 3366 k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); 3367 } 3368 3369 for (i = 0; i < common->rx_ch_num_flows; i++) 3370 k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, 3371 rx_chan, 3372 am65_cpsw_nuss_rx_cleanup, !!i); 3373 3374 k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); 3375 3376 ret = am65_cpsw_nuss_register_devlink(common); 3377 if (ret) 3378 return ret; 3379 3380 for (i = 0; i < common->port_num; i++) { 3381 port = &common->ports[i]; 3382 3383 if (!port->ndev) 3384 continue; 3385 3386 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 3387 3388 ret = register_netdev(port->ndev); 3389 if (ret) { 3390 dev_err(dev, "error registering slave net device%i %d\n", 3391 i, ret); 3392 goto err_cleanup_ndev; 3393 } 3394 } 3395 3396 ret = am65_cpsw_register_notifiers(common); 3397 if (ret) 3398 goto err_cleanup_ndev; 3399 3400 /* can't auto unregister ndev using devm_add_action() due to 3401 * devres release sequence in DD core for DMA 3402 */ 3403 3404 return 0; 3405 3406 err_cleanup_ndev: 3407 am65_cpsw_nuss_cleanup_ndev(common); 3408 am65_cpsw_unregister_devlink(common); 3409 3410 return ret; 3411 } 3412 3413 int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, 3414 int num_tx, int num_rx) 3415 { 3416 int ret; 3417 3418 am65_cpsw_nuss_remove_tx_chns(common); 3419 am65_cpsw_nuss_remove_rx_chns(common); 3420 3421 common->tx_ch_num = num_tx; 3422 common->rx_ch_num_flows = num_rx; 3423 ret = am65_cpsw_nuss_init_tx_chns(common); 3424 if (ret) 3425 return ret; 3426 3427 ret = am65_cpsw_nuss_init_rx_chns(common); 3428 3429 return ret; 3430 } 3431 3432 struct am65_cpsw_soc_pdata { 3433 u32 quirks_dis; 3434 }; 3435 3436 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 3437 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3438 }; 3439 3440 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 3441 { .family = "AM65X", 3442 .revision = "SR2.0", 3443 .data = &am65x_soc_sr2_0 3444 }, 3445 {/* sentinel */} 3446 }; 3447 3448 static const struct am65_cpsw_pdata am65x_sr1_0 = { 3449 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3450 .ale_dev_id = "am65x-cpsw2g", 3451 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3452 }; 3453 3454 static const struct am65_cpsw_pdata j721e_pdata = { 3455 .quirks = 0, 3456 .ale_dev_id = "am65x-cpsw2g", 3457 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3458 }; 3459 3460 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 3461 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 3462 .ale_dev_id = "am64-cpswxg", 3463 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3464 }; 3465 3466 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 3467 .quirks = 0, 3468 .ale_dev_id = "am64-cpswxg", 3469 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3470 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3471 BIT(PHY_INTERFACE_MODE_USXGMII), 3472 }; 3473 3474 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 3475 .quirks = 0, 3476 .ale_dev_id = "am64-cpswxg", 3477 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3478 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3479 }; 3480 3481 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 3482 .quirks = 0, 3483 .ale_dev_id = "am64-cpswxg", 3484 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3485 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3486 BIT(PHY_INTERFACE_MODE_USXGMII), 3487 }; 3488 3489 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 3490 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 3491 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 3492 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 3493 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 3494 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 3495 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 3496 { /* sentinel */ }, 3497 }; 3498 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 3499 3500 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 3501 { 3502 const struct soc_device_attribute *soc; 3503 3504 soc = soc_device_match(am65_cpsw_socinfo); 3505 if (soc && soc->data) { 3506 const struct am65_cpsw_soc_pdata *socdata = soc->data; 3507 3508 /* disable quirks */ 3509 common->pdata.quirks &= ~socdata->quirks_dis; 3510 } 3511 } 3512 3513 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 3514 { 3515 struct cpsw_ale_params ale_params = { 0 }; 3516 const struct of_device_id *of_id; 3517 struct device *dev = &pdev->dev; 3518 struct am65_cpsw_common *common; 3519 struct device_node *node; 3520 struct resource *res; 3521 struct clk *clk; 3522 int ale_entries; 3523 __be64 id_temp; 3524 int ret, i; 3525 3526 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 3527 if (!common) 3528 return -ENOMEM; 3529 common->dev = dev; 3530 3531 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 3532 if (!of_id) 3533 return -EINVAL; 3534 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 3535 3536 am65_cpsw_nuss_apply_socinfo(common); 3537 3538 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 3539 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 3540 if (IS_ERR(common->ss_base)) 3541 return PTR_ERR(common->ss_base); 3542 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 3543 /* Use device's physical base address as switch id */ 3544 id_temp = cpu_to_be64(res->start); 3545 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 3546 3547 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 3548 if (!node) 3549 return -ENOENT; 3550 common->port_num = of_get_child_count(node); 3551 of_node_put(node); 3552 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 3553 return -ENOENT; 3554 3555 common->rx_flow_id_base = -1; 3556 init_completion(&common->tdown_complete); 3557 common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; 3558 common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; 3559 common->pf_p0_rx_ptype_rrobin = true; 3560 common->default_vlan = 1; 3561 3562 common->ports = devm_kcalloc(dev, common->port_num, 3563 sizeof(*common->ports), 3564 GFP_KERNEL); 3565 if (!common->ports) 3566 return -ENOMEM; 3567 3568 clk = devm_clk_get(dev, "fck"); 3569 if (IS_ERR(clk)) 3570 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 3571 common->bus_freq = clk_get_rate(clk); 3572 3573 pm_runtime_enable(dev); 3574 ret = pm_runtime_resume_and_get(dev); 3575 if (ret < 0) { 3576 pm_runtime_disable(dev); 3577 return ret; 3578 } 3579 3580 node = of_get_child_by_name(dev->of_node, "mdio"); 3581 if (!node) { 3582 dev_warn(dev, "MDIO node not found\n"); 3583 } else if (of_device_is_available(node)) { 3584 struct platform_device *mdio_pdev; 3585 3586 mdio_pdev = of_platform_device_create(node, NULL, dev); 3587 if (!mdio_pdev) { 3588 ret = -ENODEV; 3589 goto err_pm_clear; 3590 } 3591 3592 common->mdio_dev = &mdio_pdev->dev; 3593 } 3594 of_node_put(node); 3595 3596 am65_cpsw_nuss_get_ver(common); 3597 3598 ret = am65_cpsw_nuss_init_host_p(common); 3599 if (ret) 3600 goto err_of_clear; 3601 3602 ret = am65_cpsw_nuss_init_slave_ports(common); 3603 if (ret) 3604 goto err_of_clear; 3605 3606 /* init common data */ 3607 ale_params.dev = dev; 3608 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 3609 ale_params.ale_ports = common->port_num + 1; 3610 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 3611 ale_params.dev_id = common->pdata.ale_dev_id; 3612 ale_params.bus_freq = common->bus_freq; 3613 3614 common->ale = cpsw_ale_create(&ale_params); 3615 if (IS_ERR(common->ale)) { 3616 dev_err(dev, "error initializing ale engine\n"); 3617 ret = PTR_ERR(common->ale); 3618 goto err_of_clear; 3619 } 3620 3621 ale_entries = common->ale->params.ale_entries; 3622 common->ale_context = devm_kzalloc(dev, 3623 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 3624 GFP_KERNEL); 3625 ret = am65_cpsw_init_cpts(common); 3626 if (ret) 3627 goto err_of_clear; 3628 3629 /* init ports */ 3630 for (i = 0; i < common->port_num; i++) 3631 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 3632 3633 dev_set_drvdata(dev, common); 3634 3635 common->is_emac_mode = true; 3636 3637 ret = am65_cpsw_nuss_init_ndevs(common); 3638 if (ret) 3639 goto err_ndevs_clear; 3640 3641 ret = am65_cpsw_nuss_register_ndevs(common); 3642 if (ret) 3643 goto err_ndevs_clear; 3644 3645 pm_runtime_put(dev); 3646 return 0; 3647 3648 err_ndevs_clear: 3649 am65_cpsw_nuss_cleanup_ndev(common); 3650 am65_cpsw_nuss_phylink_cleanup(common); 3651 am65_cpts_release(common->cpts); 3652 err_of_clear: 3653 if (common->mdio_dev) 3654 of_platform_device_destroy(common->mdio_dev, NULL); 3655 err_pm_clear: 3656 pm_runtime_put_sync(dev); 3657 pm_runtime_disable(dev); 3658 return ret; 3659 } 3660 3661 static void am65_cpsw_nuss_remove(struct platform_device *pdev) 3662 { 3663 struct device *dev = &pdev->dev; 3664 struct am65_cpsw_common *common; 3665 int ret; 3666 3667 common = dev_get_drvdata(dev); 3668 3669 ret = pm_runtime_resume_and_get(&pdev->dev); 3670 if (ret < 0) { 3671 /* Note, if this error path is taken, we're leaking some 3672 * resources. 3673 */ 3674 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", 3675 ERR_PTR(ret)); 3676 return; 3677 } 3678 3679 am65_cpsw_unregister_notifiers(common); 3680 3681 /* must unregister ndevs here because DD release_driver routine calls 3682 * dma_deconfigure(dev) before devres_release_all(dev) 3683 */ 3684 am65_cpsw_nuss_cleanup_ndev(common); 3685 am65_cpsw_unregister_devlink(common); 3686 am65_cpsw_nuss_phylink_cleanup(common); 3687 am65_cpts_release(common->cpts); 3688 am65_cpsw_disable_serdes_phy(common); 3689 3690 if (common->mdio_dev) 3691 of_platform_device_destroy(common->mdio_dev, NULL); 3692 3693 pm_runtime_put_sync(&pdev->dev); 3694 pm_runtime_disable(&pdev->dev); 3695 } 3696 3697 static int am65_cpsw_nuss_suspend(struct device *dev) 3698 { 3699 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3700 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3701 struct am65_cpsw_port *port; 3702 struct net_device *ndev; 3703 int i, ret; 3704 3705 cpsw_ale_dump(common->ale, common->ale_context); 3706 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3707 for (i = 0; i < common->port_num; i++) { 3708 port = &common->ports[i]; 3709 ndev = port->ndev; 3710 3711 if (!ndev) 3712 continue; 3713 3714 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3715 netif_device_detach(ndev); 3716 if (netif_running(ndev)) { 3717 rtnl_lock(); 3718 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3719 rtnl_unlock(); 3720 if (ret < 0) { 3721 netdev_err(ndev, "failed to stop: %d", ret); 3722 return ret; 3723 } 3724 } 3725 } 3726 3727 am65_cpts_suspend(common->cpts); 3728 3729 am65_cpsw_nuss_remove_rx_chns(common); 3730 am65_cpsw_nuss_remove_tx_chns(common); 3731 3732 return 0; 3733 } 3734 3735 static int am65_cpsw_nuss_resume(struct device *dev) 3736 { 3737 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3738 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3739 struct am65_cpsw_port *port; 3740 struct net_device *ndev; 3741 int i, ret; 3742 3743 ret = am65_cpsw_nuss_init_tx_chns(common); 3744 if (ret) 3745 return ret; 3746 ret = am65_cpsw_nuss_init_rx_chns(common); 3747 if (ret) 3748 return ret; 3749 3750 /* If RX IRQ was disabled before suspend, keep it disabled */ 3751 for (i = 0; i < common->rx_ch_num_flows; i++) { 3752 if (common->rx_chns.flows[i].irq_disabled) 3753 disable_irq(common->rx_chns.flows[i].irq); 3754 } 3755 3756 am65_cpts_resume(common->cpts); 3757 3758 for (i = 0; i < common->port_num; i++) { 3759 port = &common->ports[i]; 3760 ndev = port->ndev; 3761 3762 if (!ndev) 3763 continue; 3764 3765 if (netif_running(ndev)) { 3766 rtnl_lock(); 3767 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3768 rtnl_unlock(); 3769 if (ret < 0) { 3770 netdev_err(ndev, "failed to start: %d", ret); 3771 return ret; 3772 } 3773 } 3774 3775 netif_device_attach(ndev); 3776 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3777 } 3778 3779 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3780 cpsw_ale_restore(common->ale, common->ale_context); 3781 3782 return 0; 3783 } 3784 3785 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3786 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3787 }; 3788 3789 static struct platform_driver am65_cpsw_nuss_driver = { 3790 .driver = { 3791 .name = AM65_CPSW_DRV_NAME, 3792 .of_match_table = am65_cpsw_nuss_of_mtable, 3793 .pm = &am65_cpsw_nuss_dev_pm_ops, 3794 }, 3795 .probe = am65_cpsw_nuss_probe, 3796 .remove = am65_cpsw_nuss_remove, 3797 }; 3798 3799 module_platform_driver(am65_cpsw_nuss_driver); 3800 3801 MODULE_LICENSE("GPL v2"); 3802 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3803 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3804