1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/bpf_trace.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/kmemleak.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/phylink.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/rtnetlink.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/sys_soc.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 #include <net/page_pool/helpers.h> 35 #include <net/dsa.h> 36 #include <net/switchdev.h> 37 38 #include "cpsw_ale.h" 39 #include "cpsw_sl.h" 40 #include "am65-cpsw-nuss.h" 41 #include "am65-cpsw-switchdev.h" 42 #include "k3-cppi-desc-pool.h" 43 #include "am65-cpts.h" 44 45 #define AM65_CPSW_SS_BASE 0x0 46 #define AM65_CPSW_SGMII_BASE 0x100 47 #define AM65_CPSW_XGMII_BASE 0x2100 48 #define AM65_CPSW_CPSW_NU_BASE 0x20000 49 #define AM65_CPSW_NU_PORTS_BASE 0x1000 50 #define AM65_CPSW_NU_FRAM_BASE 0x12000 51 #define AM65_CPSW_NU_STATS_BASE 0x1a000 52 #define AM65_CPSW_NU_ALE_BASE 0x1e000 53 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 54 55 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 56 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 57 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 58 59 #define AM65_CPSW_MAX_PORTS 8 60 61 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 62 #define AM65_CPSW_MAX_PACKET_SIZE 2024 63 64 #define AM65_CPSW_REG_CTL 0x004 65 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 66 #define AM65_CPSW_REG_PTYPE 0x018 67 68 #define AM65_CPSW_P0_REG_CTL 0x004 69 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 70 71 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 72 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 73 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 74 75 #define AM65_CPSW_PORTN_REG_CTL 0x004 76 #define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120 77 #define AM65_CPSW_PORTN_REG_SA_L 0x308 78 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 79 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 80 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 81 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 82 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 83 84 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 85 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 86 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 87 88 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 89 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 90 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 91 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 92 93 /* AM65_CPSW_P0_REG_CTL */ 94 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 95 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 96 97 /* AM65_CPSW_PORT_REG_PRI_CTL */ 98 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 99 100 /* AM65_CPSW_PN_REG_CTL */ 101 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1) 102 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2) 103 104 /* AM65_CPSW_PN_TS_CTL register fields */ 105 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 106 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 107 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 108 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 109 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 110 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 111 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 112 113 #define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0) 114 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1) 115 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2) 116 #define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3) 117 #define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9) 118 119 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 120 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 121 122 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 123 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 124 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 125 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 126 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 127 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 128 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 129 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 130 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 131 132 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 133 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 134 135 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 136 137 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 138 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 139 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 140 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 141 142 #define AM65_CPSW_TS_RX_ANX_ALL_EN \ 143 (AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \ 144 AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \ 145 AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) 146 147 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 148 /* Number of TX/RX descriptors per channel/flow */ 149 #define AM65_CPSW_MAX_TX_DESC 500 150 #define AM65_CPSW_MAX_RX_DESC 500 151 152 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 153 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 154 155 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 156 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 157 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 158 159 #define AM65_CPSW_DEFAULT_TX_CHNS 8 160 #define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 161 162 /* CPPI streaming packet interface */ 163 #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF 164 #define AM65_CPSW_CPPI_TX_PKT_TYPE 0x7 165 166 /* XDP */ 167 #define AM65_CPSW_XDP_CONSUMED BIT(1) 168 #define AM65_CPSW_XDP_REDIRECT BIT(0) 169 #define AM65_CPSW_XDP_PASS 0 170 171 /* Include headroom compatible with both skb and xdpf */ 172 #define AM65_CPSW_HEADROOM_NA (max(NET_SKB_PAD, XDP_PACKET_HEADROOM) + NET_IP_ALIGN) 173 #define AM65_CPSW_HEADROOM ALIGN(AM65_CPSW_HEADROOM_NA, sizeof(long)) 174 175 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 176 const u8 *dev_addr) 177 { 178 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 179 (dev_addr[2] << 16) | (dev_addr[3] << 24); 180 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 181 182 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 183 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 184 } 185 186 #define AM65_CPSW_DSCP_MAX GENMASK(5, 0) 187 #define AM65_CPSW_PRI_MAX GENMASK(2, 0) 188 #define AM65_CPSW_DSCP_PRI_PER_REG 8 189 #define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */ 190 static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri) 191 { 192 int reg_ofs; 193 int bit_ofs; 194 u32 val; 195 196 if (dscp > AM65_CPSW_DSCP_MAX) 197 return -EINVAL; 198 199 if (pri > AM65_CPSW_PRI_MAX) 200 return -EINVAL; 201 202 /* 32-bit register offset to this dscp */ 203 reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4; 204 /* bit field offset to this dscp */ 205 bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG); 206 207 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 208 val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */ 209 val |= pri << bit_ofs; /* set */ 210 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 211 212 return 0; 213 } 214 215 static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave) 216 { 217 int dscp, pri; 218 u32 val; 219 220 /* Default DSCP to User Priority mapping as per: 221 * https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 222 * and 223 * https://datatracker.ietf.org/doc/html/rfc8622#section-11 224 */ 225 for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) { 226 switch (dscp) { 227 case 56: /* CS7 */ 228 case 48: /* CS6 */ 229 pri = 7; 230 break; 231 case 46: /* EF */ 232 case 44: /* VA */ 233 pri = 6; 234 break; 235 case 40: /* CS5 */ 236 pri = 5; 237 break; 238 case 34: /* AF41 */ 239 case 36: /* AF42 */ 240 case 38: /* AF43 */ 241 case 32: /* CS4 */ 242 case 26: /* AF31 */ 243 case 28: /* AF32 */ 244 case 30: /* AF33 */ 245 case 24: /* CS3 */ 246 pri = 4; 247 break; 248 case 18: /* AF21 */ 249 case 20: /* AF22 */ 250 case 22: /* AF23 */ 251 pri = 3; 252 break; 253 case 16: /* CS2 */ 254 case 10: /* AF11 */ 255 case 12: /* AF12 */ 256 case 14: /* AF13 */ 257 case 0: /* DF */ 258 pri = 0; 259 break; 260 case 8: /* CS1 */ 261 case 1: /* LE */ 262 pri = 1; 263 break; 264 default: 265 pri = 0; 266 break; 267 } 268 269 am65_cpsw_port_set_dscp_map(slave, dscp, pri); 270 } 271 272 /* enable port IPV4 and IPV6 DSCP for this port */ 273 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL); 274 val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN | 275 AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN; 276 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL); 277 } 278 279 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 280 { 281 cpsw_sl_reset(port->slave.mac_sl, 100); 282 /* Max length register has to be restored after MAC SL reset */ 283 writel(AM65_CPSW_MAX_PACKET_SIZE, 284 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 285 } 286 287 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 288 { 289 common->nuss_ver = readl(common->ss_base); 290 common->cpsw_ver = readl(common->cpsw_base); 291 dev_info(common->dev, 292 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 293 common->nuss_ver, 294 common->cpsw_ver, 295 common->port_num + 1, 296 common->pdata.quirks); 297 } 298 299 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 300 __be16 proto, u16 vid) 301 { 302 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 303 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 304 u32 port_mask, unreg_mcast = 0; 305 int ret; 306 307 if (!common->is_emac_mode) 308 return 0; 309 310 if (!netif_running(ndev) || !vid) 311 return 0; 312 313 ret = pm_runtime_resume_and_get(common->dev); 314 if (ret < 0) 315 return ret; 316 317 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 318 if (!vid) 319 unreg_mcast = port_mask; 320 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 321 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 322 unreg_mcast, port_mask, 0); 323 324 pm_runtime_put(common->dev); 325 return ret; 326 } 327 328 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 329 __be16 proto, u16 vid) 330 { 331 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 332 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 333 int ret; 334 335 if (!common->is_emac_mode) 336 return 0; 337 338 if (!netif_running(ndev) || !vid) 339 return 0; 340 341 ret = pm_runtime_resume_and_get(common->dev); 342 if (ret < 0) 343 return ret; 344 345 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 346 ret = cpsw_ale_del_vlan(common->ale, vid, 347 BIT(port->port_id) | ALE_PORT_HOST); 348 349 pm_runtime_put(common->dev); 350 return ret; 351 } 352 353 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 354 bool promisc) 355 { 356 struct am65_cpsw_common *common = port->common; 357 358 if (promisc && !common->is_emac_mode) { 359 dev_dbg(common->dev, "promisc mode requested in switch mode"); 360 return; 361 } 362 363 if (promisc) { 364 /* Enable promiscuous mode */ 365 cpsw_ale_control_set(common->ale, port->port_id, 366 ALE_PORT_MACONLY_CAF, 1); 367 dev_dbg(common->dev, "promisc enabled\n"); 368 } else { 369 /* Disable promiscuous mode */ 370 cpsw_ale_control_set(common->ale, port->port_id, 371 ALE_PORT_MACONLY_CAF, 0); 372 dev_dbg(common->dev, "promisc disabled\n"); 373 } 374 } 375 376 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 377 { 378 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 379 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 380 u32 port_mask; 381 bool promisc; 382 383 promisc = !!(ndev->flags & IFF_PROMISC); 384 am65_cpsw_slave_set_promisc(port, promisc); 385 386 if (promisc) 387 return; 388 389 /* Restore allmulti on vlans if necessary */ 390 cpsw_ale_set_allmulti(common->ale, 391 ndev->flags & IFF_ALLMULTI, port->port_id); 392 393 port_mask = ALE_PORT_HOST; 394 /* Clear all mcast from ALE */ 395 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 396 397 if (!netdev_mc_empty(ndev)) { 398 struct netdev_hw_addr *ha; 399 400 /* program multicast address list into ALE register */ 401 netdev_for_each_mc_addr(ha, ndev) { 402 cpsw_ale_add_mcast(common->ale, ha->addr, 403 port_mask, 0, 0, 0); 404 } 405 } 406 } 407 408 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 409 unsigned int txqueue) 410 { 411 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 412 struct am65_cpsw_tx_chn *tx_chn; 413 struct netdev_queue *netif_txq; 414 unsigned long trans_start; 415 416 netif_txq = netdev_get_tx_queue(ndev, txqueue); 417 tx_chn = &common->tx_chns[txqueue]; 418 trans_start = READ_ONCE(netif_txq->trans_start); 419 420 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 421 txqueue, 422 netif_tx_queue_stopped(netif_txq), 423 jiffies_to_msecs(jiffies - trans_start), 424 netdev_queue_dql_avail(netif_txq), 425 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 426 427 if (netif_tx_queue_stopped(netif_txq)) { 428 /* try recover if stopped by us */ 429 txq_trans_update(netif_txq); 430 netif_tx_wake_queue(netif_txq); 431 } 432 } 433 434 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 435 struct page *page, u32 flow_idx) 436 { 437 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 438 struct cppi5_host_desc_t *desc_rx; 439 struct device *dev = common->dev; 440 struct am65_cpsw_swdata *swdata; 441 dma_addr_t desc_dma; 442 dma_addr_t buf_dma; 443 444 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 445 if (!desc_rx) { 446 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 447 return -ENOMEM; 448 } 449 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 450 451 buf_dma = dma_map_single(rx_chn->dma_dev, 452 page_address(page) + AM65_CPSW_HEADROOM, 453 AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); 454 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 455 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 456 dev_err(dev, "Failed to map rx buffer\n"); 457 return -EINVAL; 458 } 459 460 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 461 AM65_CPSW_NAV_PS_DATA_SIZE); 462 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 463 cppi5_hdesc_attach_buf(desc_rx, buf_dma, AM65_CPSW_MAX_PACKET_SIZE, 464 buf_dma, AM65_CPSW_MAX_PACKET_SIZE); 465 swdata = cppi5_hdesc_get_swdata(desc_rx); 466 swdata->page = page; 467 swdata->flow_id = flow_idx; 468 469 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, 470 desc_rx, desc_dma); 471 } 472 473 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 474 { 475 struct am65_cpsw_host *host_p = am65_common_get_host(common); 476 u32 val, pri_map; 477 478 /* P0 set Receive Priority Type */ 479 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 480 481 if (common->pf_p0_rx_ptype_rrobin) { 482 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 483 /* Enet Ports fifos works in fixed priority mode only, so 484 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 485 */ 486 pri_map = 0x0; 487 } else { 488 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 489 /* restore P0_Rx_Pri_Map */ 490 pri_map = 0x76543210; 491 } 492 493 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 494 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 495 } 496 497 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 498 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 499 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 500 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 501 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 502 struct page *page, 503 bool allow_direct); 504 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 505 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 506 507 static void am65_cpsw_destroy_rxq(struct am65_cpsw_common *common, int id) 508 { 509 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 510 struct am65_cpsw_rx_flow *flow; 511 struct xdp_rxq_info *rxq; 512 int port; 513 514 flow = &rx_chn->flows[id]; 515 napi_disable(&flow->napi_rx); 516 hrtimer_cancel(&flow->rx_hrtimer); 517 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, id, rx_chn, 518 am65_cpsw_nuss_rx_cleanup, !!id); 519 520 for (port = 0; port < common->port_num; port++) { 521 if (!common->ports[port].ndev) 522 continue; 523 524 rxq = &common->ports[port].xdp_rxq[id]; 525 526 if (xdp_rxq_info_is_reg(rxq)) 527 xdp_rxq_info_unreg(rxq); 528 } 529 530 if (flow->page_pool) { 531 page_pool_destroy(flow->page_pool); 532 flow->page_pool = NULL; 533 } 534 } 535 536 static void am65_cpsw_destroy_rxqs(struct am65_cpsw_common *common) 537 { 538 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 539 int id; 540 541 reinit_completion(&common->tdown_complete); 542 k3_udma_glue_tdown_rx_chn(rx_chn->rx_chn, true); 543 544 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 545 id = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 546 if (!id) 547 dev_err(common->dev, "rx teardown timeout\n"); 548 } 549 550 for (id = common->rx_ch_num_flows - 1; id >= 0; id--) 551 am65_cpsw_destroy_rxq(common, id); 552 553 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 554 } 555 556 static int am65_cpsw_create_rxq(struct am65_cpsw_common *common, int id) 557 { 558 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 559 struct page_pool_params pp_params = { 560 .flags = PP_FLAG_DMA_MAP, 561 .order = 0, 562 .pool_size = AM65_CPSW_MAX_RX_DESC, 563 .nid = dev_to_node(common->dev), 564 .dev = common->dev, 565 .dma_dir = DMA_BIDIRECTIONAL, 566 /* .napi set dynamically */ 567 }; 568 struct am65_cpsw_rx_flow *flow; 569 struct xdp_rxq_info *rxq; 570 struct page_pool *pool; 571 struct page *page; 572 int port, ret, i; 573 574 flow = &rx_chn->flows[id]; 575 pp_params.napi = &flow->napi_rx; 576 pool = page_pool_create(&pp_params); 577 if (IS_ERR(pool)) { 578 ret = PTR_ERR(pool); 579 return ret; 580 } 581 582 flow->page_pool = pool; 583 584 /* using same page pool is allowed as no running rx handlers 585 * simultaneously for both ndevs 586 */ 587 for (port = 0; port < common->port_num; port++) { 588 if (!common->ports[port].ndev) 589 /* FIXME should we BUG here? */ 590 continue; 591 592 rxq = &common->ports[port].xdp_rxq[id]; 593 ret = xdp_rxq_info_reg(rxq, common->ports[port].ndev, 594 id, flow->napi_rx.napi_id); 595 if (ret) 596 goto err; 597 598 ret = xdp_rxq_info_reg_mem_model(rxq, 599 MEM_TYPE_PAGE_POOL, 600 pool); 601 if (ret) 602 goto err; 603 } 604 605 for (i = 0; i < AM65_CPSW_MAX_RX_DESC; i++) { 606 page = page_pool_dev_alloc_pages(flow->page_pool); 607 if (!page) { 608 dev_err(common->dev, "cannot allocate page in flow %d\n", 609 id); 610 ret = -ENOMEM; 611 goto err; 612 } 613 614 ret = am65_cpsw_nuss_rx_push(common, page, id); 615 if (ret < 0) { 616 dev_err(common->dev, 617 "cannot submit page to rx channel flow %d, error %d\n", 618 id, ret); 619 am65_cpsw_put_page(flow, page, false); 620 goto err; 621 } 622 } 623 624 napi_enable(&flow->napi_rx); 625 return 0; 626 627 err: 628 am65_cpsw_destroy_rxq(common, id); 629 return ret; 630 } 631 632 static int am65_cpsw_create_rxqs(struct am65_cpsw_common *common) 633 { 634 int id, ret; 635 636 for (id = 0; id < common->rx_ch_num_flows; id++) { 637 ret = am65_cpsw_create_rxq(common, id); 638 if (ret) { 639 dev_err(common->dev, "couldn't create rxq %d: %d\n", 640 id, ret); 641 goto err; 642 } 643 } 644 645 ret = k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 646 if (ret) { 647 dev_err(common->dev, "couldn't enable rx chn: %d\n", ret); 648 goto err; 649 } 650 651 return 0; 652 653 err: 654 for (--id; id >= 0; id--) 655 am65_cpsw_destroy_rxq(common, id); 656 657 return ret; 658 } 659 660 static void am65_cpsw_destroy_txq(struct am65_cpsw_common *common, int id) 661 { 662 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[id]; 663 664 napi_disable(&tx_chn->napi_tx); 665 hrtimer_cancel(&tx_chn->tx_hrtimer); 666 k3_udma_glue_reset_tx_chn(tx_chn->tx_chn, tx_chn, 667 am65_cpsw_nuss_tx_cleanup); 668 k3_udma_glue_disable_tx_chn(tx_chn->tx_chn); 669 } 670 671 static void am65_cpsw_destroy_txqs(struct am65_cpsw_common *common) 672 { 673 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 674 int id; 675 676 /* shutdown tx channels */ 677 atomic_set(&common->tdown_cnt, common->tx_ch_num); 678 /* ensure new tdown_cnt value is visible */ 679 smp_mb__after_atomic(); 680 reinit_completion(&common->tdown_complete); 681 682 for (id = 0; id < common->tx_ch_num; id++) 683 k3_udma_glue_tdown_tx_chn(tx_chn[id].tx_chn, false); 684 685 id = wait_for_completion_timeout(&common->tdown_complete, 686 msecs_to_jiffies(1000)); 687 if (!id) 688 dev_err(common->dev, "tx teardown timeout\n"); 689 690 for (id = common->tx_ch_num - 1; id >= 0; id--) 691 am65_cpsw_destroy_txq(common, id); 692 } 693 694 static int am65_cpsw_create_txq(struct am65_cpsw_common *common, int id) 695 { 696 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[id]; 697 int ret; 698 699 ret = k3_udma_glue_enable_tx_chn(tx_chn->tx_chn); 700 if (ret) 701 return ret; 702 703 napi_enable(&tx_chn->napi_tx); 704 705 return 0; 706 } 707 708 static int am65_cpsw_create_txqs(struct am65_cpsw_common *common) 709 { 710 int id, ret; 711 712 for (id = 0; id < common->tx_ch_num; id++) { 713 ret = am65_cpsw_create_txq(common, id); 714 if (ret) { 715 dev_err(common->dev, "couldn't create txq %d: %d\n", 716 id, ret); 717 goto err; 718 } 719 } 720 721 return 0; 722 723 err: 724 for (--id; id >= 0; id--) 725 am65_cpsw_destroy_txq(common, id); 726 727 return ret; 728 } 729 730 static int am65_cpsw_nuss_desc_idx(struct k3_cppi_desc_pool *desc_pool, 731 void *desc, 732 unsigned char dsize_log2) 733 { 734 void *pool_addr = k3_cppi_desc_pool_cpuaddr(desc_pool); 735 736 return (desc - pool_addr) >> dsize_log2; 737 } 738 739 static void am65_cpsw_nuss_set_buf_type(struct am65_cpsw_tx_chn *tx_chn, 740 struct cppi5_host_desc_t *desc, 741 enum am65_cpsw_tx_buf_type buf_type) 742 { 743 int desc_idx; 744 745 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc, 746 tx_chn->dsize_log2); 747 k3_cppi_desc_pool_desc_info_set(tx_chn->desc_pool, desc_idx, 748 (void *)buf_type); 749 } 750 751 static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_chn *tx_chn, 752 dma_addr_t desc_dma) 753 { 754 struct cppi5_host_desc_t *desc_tx; 755 int desc_idx; 756 757 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 758 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc_tx, 759 tx_chn->dsize_log2); 760 761 return (enum am65_cpsw_tx_buf_type)k3_cppi_desc_pool_desc_info(tx_chn->desc_pool, 762 desc_idx); 763 } 764 765 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 766 struct page *page, 767 bool allow_direct) 768 { 769 page_pool_put_full_page(flow->page_pool, page, allow_direct); 770 } 771 772 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 773 { 774 struct am65_cpsw_rx_chn *rx_chn = data; 775 struct cppi5_host_desc_t *desc_rx; 776 struct am65_cpsw_swdata *swdata; 777 dma_addr_t buf_dma; 778 struct page *page; 779 u32 buf_dma_len; 780 u32 flow_id; 781 782 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 783 swdata = cppi5_hdesc_get_swdata(desc_rx); 784 page = swdata->page; 785 flow_id = swdata->flow_id; 786 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 787 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 788 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 789 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 790 am65_cpsw_put_page(&rx_chn->flows[flow_id], page, false); 791 } 792 793 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 794 struct cppi5_host_desc_t *desc) 795 { 796 struct cppi5_host_desc_t *first_desc, *next_desc; 797 dma_addr_t buf_dma, next_desc_dma; 798 u32 buf_dma_len; 799 800 first_desc = desc; 801 next_desc = first_desc; 802 803 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 804 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 805 806 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 807 808 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 809 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 810 while (next_desc_dma) { 811 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 812 next_desc_dma); 813 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 814 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 815 816 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 817 DMA_TO_DEVICE); 818 819 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 820 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 821 822 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 823 } 824 825 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 826 } 827 828 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 829 { 830 struct am65_cpsw_tx_chn *tx_chn = data; 831 struct cppi5_host_desc_t *desc_tx; 832 struct sk_buff *skb; 833 void **swdata; 834 835 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 836 swdata = cppi5_hdesc_get_swdata(desc_tx); 837 skb = *(swdata); 838 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 839 840 dev_kfree_skb_any(skb); 841 } 842 843 static struct sk_buff *am65_cpsw_build_skb(void *page_addr, 844 struct net_device *ndev, 845 unsigned int len) 846 { 847 struct sk_buff *skb; 848 849 len += AM65_CPSW_HEADROOM; 850 851 skb = build_skb(page_addr, len); 852 if (unlikely(!skb)) 853 return NULL; 854 855 skb_reserve(skb, AM65_CPSW_HEADROOM); 856 skb->dev = ndev; 857 858 return skb; 859 } 860 861 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 862 { 863 struct am65_cpsw_host *host_p = am65_common_get_host(common); 864 u32 val, port_mask; 865 int port_idx, ret; 866 867 if (common->usage_count) 868 return 0; 869 870 /* Control register */ 871 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 872 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 873 common->cpsw_base + AM65_CPSW_REG_CTL); 874 /* Max length register */ 875 writel(AM65_CPSW_MAX_PACKET_SIZE, 876 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 877 /* set base flow_id */ 878 writel(common->rx_flow_id_base, 879 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 880 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 881 host_p->port_base + AM65_CPSW_P0_REG_CTL); 882 883 am65_cpsw_nuss_set_p0_ptype(common); 884 885 /* enable statistic */ 886 val = BIT(HOST_PORT_NUM); 887 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 888 struct am65_cpsw_port *port = &common->ports[port_idx]; 889 890 if (!port->disabled) 891 val |= BIT(port->port_id); 892 } 893 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 894 895 /* disable priority elevation */ 896 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 897 898 cpsw_ale_start(common->ale); 899 900 /* limit to one RX flow only */ 901 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 902 ALE_DEFAULT_THREAD_ID, 0); 903 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 904 ALE_DEFAULT_THREAD_ENABLE, 1); 905 /* switch to vlan aware mode */ 906 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 907 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 908 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 909 910 /* default vlan cfg: create mask based on enabled ports */ 911 port_mask = GENMASK(common->port_num, 0) & 912 ~common->disabled_ports_mask; 913 914 cpsw_ale_add_vlan(common->ale, 0, port_mask, 915 port_mask, port_mask, 916 port_mask & ~ALE_PORT_HOST); 917 918 if (common->is_emac_mode) 919 am65_cpsw_init_host_port_emac(common); 920 else 921 am65_cpsw_init_host_port_switch(common); 922 923 am65_cpsw_qos_tx_p0_rate_init(common); 924 925 ret = am65_cpsw_create_rxqs(common); 926 if (ret) 927 return ret; 928 929 ret = am65_cpsw_create_txqs(common); 930 if (ret) 931 goto cleanup_rx; 932 933 dev_dbg(common->dev, "cpsw_nuss started\n"); 934 return 0; 935 936 cleanup_rx: 937 am65_cpsw_destroy_rxqs(common); 938 939 return ret; 940 } 941 942 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 943 { 944 if (common->usage_count != 1) 945 return 0; 946 947 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 948 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 949 950 am65_cpsw_destroy_txqs(common); 951 am65_cpsw_destroy_rxqs(common); 952 cpsw_ale_stop(common->ale); 953 954 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 955 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 956 957 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 958 return 0; 959 } 960 961 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 962 { 963 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 964 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 965 int ret; 966 967 phylink_stop(port->slave.phylink); 968 969 netif_tx_stop_all_queues(ndev); 970 971 phylink_disconnect_phy(port->slave.phylink); 972 973 ret = am65_cpsw_nuss_common_stop(common); 974 if (ret) 975 return ret; 976 977 common->usage_count--; 978 pm_runtime_put(common->dev); 979 return 0; 980 } 981 982 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 983 { 984 struct am65_cpsw_port *port = arg; 985 986 if (!vdev) 987 return 0; 988 989 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 990 } 991 992 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 993 { 994 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 995 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 996 int ret, i; 997 u32 reg; 998 999 ret = pm_runtime_resume_and_get(common->dev); 1000 if (ret < 0) 1001 return ret; 1002 1003 /* Idle MAC port */ 1004 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1005 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1006 cpsw_sl_ctl_reset(port->slave.mac_sl); 1007 1008 /* soft reset MAC */ 1009 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 1010 mdelay(1); 1011 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 1012 if (reg) { 1013 dev_err(common->dev, "soft RESET didn't complete\n"); 1014 ret = -ETIMEDOUT; 1015 goto runtime_put; 1016 } 1017 1018 /* Notify the stack of the actual queue counts. */ 1019 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 1020 if (ret) { 1021 dev_err(common->dev, "cannot set real number of tx queues\n"); 1022 goto runtime_put; 1023 } 1024 1025 ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); 1026 if (ret) { 1027 dev_err(common->dev, "cannot set real number of rx queues\n"); 1028 goto runtime_put; 1029 } 1030 1031 for (i = 0; i < common->tx_ch_num; i++) { 1032 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 1033 1034 netdev_tx_reset_queue(txq); 1035 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 1036 } 1037 1038 ret = am65_cpsw_nuss_common_open(common); 1039 if (ret) 1040 goto runtime_put; 1041 1042 common->usage_count++; 1043 1044 /* VLAN aware CPSW mode is incompatible with some DSA tagging schemes. 1045 * Therefore disable VLAN_AWARE mode if any of the ports is a DSA Port. 1046 */ 1047 if (netdev_uses_dsa(ndev)) { 1048 reg = readl(common->cpsw_base + AM65_CPSW_REG_CTL); 1049 reg &= ~AM65_CPSW_CTL_VLAN_AWARE; 1050 writel(reg, common->cpsw_base + AM65_CPSW_REG_CTL); 1051 } 1052 1053 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 1054 am65_cpsw_port_enable_dscp_map(port); 1055 1056 if (common->is_emac_mode) 1057 am65_cpsw_init_port_emac_ale(port); 1058 else 1059 am65_cpsw_init_port_switch_ale(port); 1060 1061 /* mac_sl should be configured via phy-link interface */ 1062 am65_cpsw_sl_ctl_reset(port); 1063 1064 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.port_np, 0); 1065 if (ret) 1066 goto error_cleanup; 1067 1068 /* restore vlan configurations */ 1069 vlan_for_each(ndev, cpsw_restore_vlans, port); 1070 1071 phylink_start(port->slave.phylink); 1072 1073 return 0; 1074 1075 error_cleanup: 1076 am65_cpsw_nuss_ndo_slave_stop(ndev); 1077 return ret; 1078 1079 runtime_put: 1080 pm_runtime_put(common->dev); 1081 return ret; 1082 } 1083 1084 static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, 1085 struct am65_cpsw_tx_chn *tx_chn, 1086 struct xdp_frame *xdpf, 1087 enum am65_cpsw_tx_buf_type buf_type) 1088 { 1089 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1090 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1091 struct cppi5_host_desc_t *host_desc; 1092 struct netdev_queue *netif_txq; 1093 dma_addr_t dma_desc, dma_buf; 1094 u32 pkt_len = xdpf->len; 1095 void **swdata; 1096 int ret; 1097 1098 host_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1099 if (unlikely(!host_desc)) { 1100 ndev->stats.tx_dropped++; 1101 return AM65_CPSW_XDP_CONSUMED; /* drop */ 1102 } 1103 1104 am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, buf_type); 1105 1106 dma_buf = dma_map_single(tx_chn->dma_dev, xdpf->data, 1107 pkt_len, DMA_TO_DEVICE); 1108 if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { 1109 ndev->stats.tx_dropped++; 1110 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1111 goto pool_free; 1112 } 1113 1114 cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1115 AM65_CPSW_NAV_PS_DATA_SIZE); 1116 cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1117 cppi5_hdesc_set_pktlen(host_desc, pkt_len); 1118 cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1119 cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); 1120 1121 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); 1122 cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); 1123 1124 swdata = cppi5_hdesc_get_swdata(host_desc); 1125 *(swdata) = xdpf; 1126 1127 /* Report BQL before sending the packet */ 1128 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1129 netdev_tx_sent_queue(netif_txq, pkt_len); 1130 1131 dma_desc = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); 1132 if (AM65_CPSW_IS_CPSW2G(common)) { 1133 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1134 dma_desc); 1135 } else { 1136 spin_lock_bh(&tx_chn->lock); 1137 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1138 dma_desc); 1139 spin_unlock_bh(&tx_chn->lock); 1140 } 1141 if (ret) { 1142 /* Inform BQL */ 1143 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1144 ndev->stats.tx_errors++; 1145 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1146 goto dma_unmap; 1147 } 1148 1149 return 0; 1150 1151 dma_unmap: 1152 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); 1153 dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); 1154 pool_free: 1155 k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); 1156 return ret; 1157 } 1158 1159 static int am65_cpsw_run_xdp(struct am65_cpsw_rx_flow *flow, 1160 struct am65_cpsw_port *port, 1161 struct xdp_buff *xdp, 1162 int cpu, int *len) 1163 { 1164 struct am65_cpsw_common *common = flow->common; 1165 struct net_device *ndev = port->ndev; 1166 int ret = AM65_CPSW_XDP_CONSUMED; 1167 struct am65_cpsw_tx_chn *tx_chn; 1168 struct netdev_queue *netif_txq; 1169 struct xdp_frame *xdpf; 1170 struct bpf_prog *prog; 1171 struct page *page; 1172 u32 act; 1173 int err; 1174 1175 prog = READ_ONCE(port->xdp_prog); 1176 if (!prog) 1177 return AM65_CPSW_XDP_PASS; 1178 1179 act = bpf_prog_run_xdp(prog, xdp); 1180 /* XDP prog might have changed packet data and boundaries */ 1181 *len = xdp->data_end - xdp->data; 1182 1183 switch (act) { 1184 case XDP_PASS: 1185 ret = AM65_CPSW_XDP_PASS; 1186 goto out; 1187 case XDP_TX: 1188 tx_chn = &common->tx_chns[cpu % AM65_CPSW_MAX_QUEUES]; 1189 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1190 1191 xdpf = xdp_convert_buff_to_frame(xdp); 1192 if (unlikely(!xdpf)) 1193 goto drop; 1194 1195 __netif_tx_lock(netif_txq, cpu); 1196 err = am65_cpsw_xdp_tx_frame(ndev, tx_chn, xdpf, 1197 AM65_CPSW_TX_BUF_TYPE_XDP_TX); 1198 __netif_tx_unlock(netif_txq); 1199 if (err) 1200 goto drop; 1201 1202 dev_sw_netstats_tx_add(ndev, 1, *len); 1203 ret = AM65_CPSW_XDP_CONSUMED; 1204 goto out; 1205 case XDP_REDIRECT: 1206 if (unlikely(xdp_do_redirect(ndev, xdp, prog))) 1207 goto drop; 1208 1209 dev_sw_netstats_rx_add(ndev, *len); 1210 ret = AM65_CPSW_XDP_REDIRECT; 1211 goto out; 1212 default: 1213 bpf_warn_invalid_xdp_action(ndev, prog, act); 1214 fallthrough; 1215 case XDP_ABORTED: 1216 drop: 1217 trace_xdp_exception(ndev, prog, act); 1218 fallthrough; 1219 case XDP_DROP: 1220 ndev->stats.rx_dropped++; 1221 } 1222 1223 page = virt_to_head_page(xdp->data); 1224 am65_cpsw_put_page(flow, page, true); 1225 1226 out: 1227 return ret; 1228 } 1229 1230 /* RX psdata[2] word format - checksum information */ 1231 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 1232 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 1233 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 1234 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 1235 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 1236 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 1237 1238 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 1239 { 1240 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 1241 * csum information provides in psdata[2] word: 1242 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 1243 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 1244 * bits - indicates IPv4/IPv6 packet 1245 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 1246 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 1247 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 1248 */ 1249 skb_checksum_none_assert(skb); 1250 1251 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 1252 return; 1253 1254 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 1255 AM65_CPSW_RX_PSD_IPV4_VALID)) && 1256 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 1257 /* csum for fragmented packets is unsupported */ 1258 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 1259 skb->ip_summed = CHECKSUM_UNNECESSARY; 1260 } 1261 } 1262 1263 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow, 1264 int cpu, int *xdp_state) 1265 { 1266 struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; 1267 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 1268 struct am65_cpsw_common *common = flow->common; 1269 struct am65_cpsw_ndev_priv *ndev_priv; 1270 struct cppi5_host_desc_t *desc_rx; 1271 struct device *dev = common->dev; 1272 struct am65_cpsw_swdata *swdata; 1273 struct page *page, *new_page; 1274 dma_addr_t desc_dma, buf_dma; 1275 struct am65_cpsw_port *port; 1276 struct net_device *ndev; 1277 u32 flow_idx = flow->id; 1278 struct sk_buff *skb; 1279 struct xdp_buff xdp; 1280 int headroom, ret; 1281 void *page_addr; 1282 u32 *psdata; 1283 1284 *xdp_state = AM65_CPSW_XDP_PASS; 1285 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 1286 if (ret) { 1287 if (ret != -ENODATA) 1288 dev_err(dev, "RX: pop chn fail %d\n", ret); 1289 return ret; 1290 } 1291 1292 if (cppi5_desc_is_tdcm(desc_dma)) { 1293 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 1294 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 1295 complete(&common->tdown_complete); 1296 return 0; 1297 } 1298 1299 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 1300 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 1301 __func__, flow_idx, &desc_dma); 1302 1303 swdata = cppi5_hdesc_get_swdata(desc_rx); 1304 page = swdata->page; 1305 page_addr = page_address(page); 1306 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 1307 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 1308 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 1309 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 1310 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 1311 port = am65_common_get_port(common, port_id); 1312 ndev = port->ndev; 1313 psdata = cppi5_hdesc_get_psdata(desc_rx); 1314 csum_info = psdata[2]; 1315 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 1316 1317 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 1318 1319 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 1320 1321 skb = am65_cpsw_build_skb(page_addr, ndev, 1322 AM65_CPSW_MAX_PACKET_SIZE); 1323 if (unlikely(!skb)) { 1324 new_page = page; 1325 goto requeue; 1326 } 1327 1328 if (port->xdp_prog) { 1329 xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq[flow->id]); 1330 xdp_prepare_buff(&xdp, page_addr, AM65_CPSW_HEADROOM, 1331 pkt_len, false); 1332 *xdp_state = am65_cpsw_run_xdp(flow, port, &xdp, 1333 cpu, &pkt_len); 1334 if (*xdp_state != AM65_CPSW_XDP_PASS) 1335 goto allocate; 1336 1337 /* Compute additional headroom to be reserved */ 1338 headroom = (xdp.data - xdp.data_hard_start) - skb_headroom(skb); 1339 skb_reserve(skb, headroom); 1340 } 1341 1342 ndev_priv = netdev_priv(ndev); 1343 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 1344 skb_put(skb, pkt_len); 1345 if (port->rx_ts_enabled) 1346 am65_cpts_rx_timestamp(common->cpts, skb); 1347 skb_mark_for_recycle(skb); 1348 skb->protocol = eth_type_trans(skb, ndev); 1349 am65_cpsw_nuss_rx_csum(skb, csum_info); 1350 napi_gro_receive(&flow->napi_rx, skb); 1351 1352 dev_sw_netstats_rx_add(ndev, pkt_len); 1353 1354 allocate: 1355 new_page = page_pool_dev_alloc_pages(flow->page_pool); 1356 if (unlikely(!new_page)) { 1357 dev_err(dev, "page alloc failed\n"); 1358 return -ENOMEM; 1359 } 1360 1361 if (netif_dormant(ndev)) { 1362 am65_cpsw_put_page(flow, new_page, true); 1363 ndev->stats.rx_dropped++; 1364 return 0; 1365 } 1366 1367 requeue: 1368 ret = am65_cpsw_nuss_rx_push(common, new_page, flow_idx); 1369 if (WARN_ON(ret < 0)) { 1370 am65_cpsw_put_page(flow, new_page, true); 1371 ndev->stats.rx_errors++; 1372 ndev->stats.rx_dropped++; 1373 } 1374 1375 return ret; 1376 } 1377 1378 static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) 1379 { 1380 struct am65_cpsw_rx_flow *flow = container_of(timer, 1381 struct am65_cpsw_rx_flow, 1382 rx_hrtimer); 1383 1384 enable_irq(flow->irq); 1385 return HRTIMER_NORESTART; 1386 } 1387 1388 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 1389 { 1390 struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); 1391 struct am65_cpsw_common *common = flow->common; 1392 int cpu = smp_processor_id(); 1393 int xdp_state_or = 0; 1394 int cur_budget, ret; 1395 int xdp_state; 1396 int num_rx = 0; 1397 1398 /* process only this flow */ 1399 cur_budget = budget; 1400 while (cur_budget--) { 1401 ret = am65_cpsw_nuss_rx_packets(flow, cpu, &xdp_state); 1402 xdp_state_or |= xdp_state; 1403 if (ret) 1404 break; 1405 num_rx++; 1406 } 1407 1408 if (xdp_state_or & AM65_CPSW_XDP_REDIRECT) 1409 xdp_do_flush(); 1410 1411 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 1412 1413 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1414 if (flow->irq_disabled) { 1415 flow->irq_disabled = false; 1416 if (unlikely(flow->rx_pace_timeout)) { 1417 hrtimer_start(&flow->rx_hrtimer, 1418 ns_to_ktime(flow->rx_pace_timeout), 1419 HRTIMER_MODE_REL_PINNED); 1420 } else { 1421 enable_irq(flow->irq); 1422 } 1423 } 1424 } 1425 1426 return num_rx; 1427 } 1428 1429 static struct sk_buff * 1430 am65_cpsw_nuss_tx_compl_packet_skb(struct am65_cpsw_tx_chn *tx_chn, 1431 dma_addr_t desc_dma) 1432 { 1433 struct cppi5_host_desc_t *desc_tx; 1434 struct sk_buff *skb; 1435 void **swdata; 1436 1437 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 1438 desc_dma); 1439 swdata = cppi5_hdesc_get_swdata(desc_tx); 1440 skb = *(swdata); 1441 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1442 1443 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 1444 1445 dev_sw_netstats_tx_add(skb->dev, 1, skb->len); 1446 1447 return skb; 1448 } 1449 1450 static struct xdp_frame * 1451 am65_cpsw_nuss_tx_compl_packet_xdp(struct am65_cpsw_common *common, 1452 struct am65_cpsw_tx_chn *tx_chn, 1453 dma_addr_t desc_dma, 1454 struct net_device **ndev) 1455 { 1456 struct cppi5_host_desc_t *desc_tx; 1457 struct am65_cpsw_port *port; 1458 struct xdp_frame *xdpf; 1459 u32 port_id = 0; 1460 void **swdata; 1461 1462 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 1463 cppi5_desc_get_tags_ids(&desc_tx->hdr, NULL, &port_id); 1464 swdata = cppi5_hdesc_get_swdata(desc_tx); 1465 xdpf = *(swdata); 1466 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1467 1468 port = am65_common_get_port(common, port_id); 1469 dev_sw_netstats_tx_add(port->ndev, 1, xdpf->len); 1470 *ndev = port->ndev; 1471 1472 return xdpf; 1473 } 1474 1475 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 1476 struct netdev_queue *netif_txq) 1477 { 1478 if (netif_tx_queue_stopped(netif_txq)) { 1479 /* Check whether the queue is stopped due to stalled 1480 * tx dma, if the queue is stopped then wake the queue 1481 * as we have free desc for tx 1482 */ 1483 __netif_tx_lock(netif_txq, smp_processor_id()); 1484 if (netif_running(ndev) && 1485 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 1486 netif_tx_wake_queue(netif_txq); 1487 1488 __netif_tx_unlock(netif_txq); 1489 } 1490 } 1491 1492 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 1493 int chn, unsigned int budget, bool *tdown) 1494 { 1495 enum am65_cpsw_tx_buf_type buf_type; 1496 struct device *dev = common->dev; 1497 struct am65_cpsw_tx_chn *tx_chn; 1498 struct netdev_queue *netif_txq; 1499 unsigned int total_bytes = 0; 1500 struct net_device *ndev; 1501 struct xdp_frame *xdpf; 1502 struct sk_buff *skb; 1503 dma_addr_t desc_dma; 1504 int res, num_tx = 0; 1505 1506 tx_chn = &common->tx_chns[chn]; 1507 1508 while (true) { 1509 spin_lock(&tx_chn->lock); 1510 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1511 spin_unlock(&tx_chn->lock); 1512 if (res == -ENODATA) 1513 break; 1514 1515 if (cppi5_desc_is_tdcm(desc_dma)) { 1516 if (atomic_dec_and_test(&common->tdown_cnt)) 1517 complete(&common->tdown_complete); 1518 *tdown = true; 1519 break; 1520 } 1521 1522 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1523 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1524 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1525 ndev = skb->dev; 1526 total_bytes = skb->len; 1527 napi_consume_skb(skb, budget); 1528 } else { 1529 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1530 desc_dma, &ndev); 1531 total_bytes = xdpf->len; 1532 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1533 xdp_return_frame_rx_napi(xdpf); 1534 else 1535 xdp_return_frame(xdpf); 1536 } 1537 num_tx++; 1538 1539 netif_txq = netdev_get_tx_queue(ndev, chn); 1540 1541 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1542 1543 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1544 } 1545 1546 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1547 1548 return num_tx; 1549 } 1550 1551 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 1552 int chn, unsigned int budget, bool *tdown) 1553 { 1554 enum am65_cpsw_tx_buf_type buf_type; 1555 struct device *dev = common->dev; 1556 struct am65_cpsw_tx_chn *tx_chn; 1557 struct netdev_queue *netif_txq; 1558 unsigned int total_bytes = 0; 1559 struct net_device *ndev; 1560 struct xdp_frame *xdpf; 1561 struct sk_buff *skb; 1562 dma_addr_t desc_dma; 1563 int res, num_tx = 0; 1564 1565 tx_chn = &common->tx_chns[chn]; 1566 1567 while (true) { 1568 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1569 if (res == -ENODATA) 1570 break; 1571 1572 if (cppi5_desc_is_tdcm(desc_dma)) { 1573 if (atomic_dec_and_test(&common->tdown_cnt)) 1574 complete(&common->tdown_complete); 1575 *tdown = true; 1576 break; 1577 } 1578 1579 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1580 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1581 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1582 ndev = skb->dev; 1583 total_bytes += skb->len; 1584 napi_consume_skb(skb, budget); 1585 } else { 1586 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1587 desc_dma, &ndev); 1588 total_bytes += xdpf->len; 1589 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1590 xdp_return_frame_rx_napi(xdpf); 1591 else 1592 xdp_return_frame(xdpf); 1593 } 1594 num_tx++; 1595 } 1596 1597 if (!num_tx) 1598 return 0; 1599 1600 netif_txq = netdev_get_tx_queue(ndev, chn); 1601 1602 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1603 1604 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1605 1606 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1607 1608 return num_tx; 1609 } 1610 1611 static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer) 1612 { 1613 struct am65_cpsw_tx_chn *tx_chns = 1614 container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer); 1615 1616 enable_irq(tx_chns->irq); 1617 return HRTIMER_NORESTART; 1618 } 1619 1620 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1621 { 1622 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1623 bool tdown = false; 1624 int num_tx; 1625 1626 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1627 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, 1628 budget, &tdown); 1629 else 1630 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, 1631 tx_chn->id, budget, &tdown); 1632 1633 if (num_tx >= budget) 1634 return budget; 1635 1636 if (napi_complete_done(napi_tx, num_tx)) { 1637 if (unlikely(tx_chn->tx_pace_timeout && !tdown)) { 1638 hrtimer_start(&tx_chn->tx_hrtimer, 1639 ns_to_ktime(tx_chn->tx_pace_timeout), 1640 HRTIMER_MODE_REL_PINNED); 1641 } else { 1642 enable_irq(tx_chn->irq); 1643 } 1644 } 1645 1646 return 0; 1647 } 1648 1649 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1650 { 1651 struct am65_cpsw_rx_flow *flow = dev_id; 1652 1653 flow->irq_disabled = true; 1654 disable_irq_nosync(irq); 1655 napi_schedule(&flow->napi_rx); 1656 1657 return IRQ_HANDLED; 1658 } 1659 1660 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1661 { 1662 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1663 1664 disable_irq_nosync(irq); 1665 napi_schedule(&tx_chn->napi_tx); 1666 1667 return IRQ_HANDLED; 1668 } 1669 1670 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1671 struct net_device *ndev) 1672 { 1673 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1674 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1675 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1676 struct device *dev = common->dev; 1677 struct am65_cpsw_tx_chn *tx_chn; 1678 struct netdev_queue *netif_txq; 1679 dma_addr_t desc_dma, buf_dma; 1680 int ret, q_idx, i; 1681 void **swdata; 1682 u32 *psdata; 1683 u32 pkt_len; 1684 1685 /* padding enabled in hw */ 1686 pkt_len = skb_headlen(skb); 1687 1688 /* SKB TX timestamp */ 1689 if (port->tx_ts_enabled) 1690 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1691 1692 q_idx = skb_get_queue_mapping(skb); 1693 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1694 1695 tx_chn = &common->tx_chns[q_idx]; 1696 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1697 1698 /* Map the linear buffer */ 1699 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1700 DMA_TO_DEVICE); 1701 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1702 dev_err(dev, "Failed to map tx skb buffer\n"); 1703 ndev->stats.tx_errors++; 1704 goto err_free_skb; 1705 } 1706 1707 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1708 if (!first_desc) { 1709 dev_dbg(dev, "Failed to allocate descriptor\n"); 1710 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1711 DMA_TO_DEVICE); 1712 goto busy_stop_q; 1713 } 1714 1715 am65_cpsw_nuss_set_buf_type(tx_chn, first_desc, 1716 AM65_CPSW_TX_BUF_TYPE_SKB); 1717 1718 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1719 AM65_CPSW_NAV_PS_DATA_SIZE); 1720 cppi5_desc_set_pktids(&first_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1721 cppi5_hdesc_set_pkttype(first_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1722 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1723 1724 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1725 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1726 swdata = cppi5_hdesc_get_swdata(first_desc); 1727 *(swdata) = skb; 1728 psdata = cppi5_hdesc_get_psdata(first_desc); 1729 1730 /* HW csum offload if enabled */ 1731 psdata[2] = 0; 1732 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1733 unsigned int cs_start, cs_offset; 1734 1735 cs_start = skb_transport_offset(skb); 1736 cs_offset = cs_start + skb->csum_offset; 1737 /* HW numerates bytes starting from 1 */ 1738 psdata[2] = ((cs_offset + 1) << 24) | 1739 ((cs_start + 1) << 16) | (skb->len - cs_start); 1740 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1741 } 1742 1743 if (!skb_is_nonlinear(skb)) 1744 goto done_tx; 1745 1746 dev_dbg(dev, "fragmented SKB\n"); 1747 1748 /* Handle the case where skb is fragmented in pages */ 1749 cur_desc = first_desc; 1750 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1751 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1752 u32 frag_size = skb_frag_size(frag); 1753 1754 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1755 if (!next_desc) { 1756 dev_err(dev, "Failed to allocate descriptor\n"); 1757 goto busy_free_descs; 1758 } 1759 1760 am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, 1761 AM65_CPSW_TX_BUF_TYPE_SKB); 1762 1763 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1764 DMA_TO_DEVICE); 1765 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1766 dev_err(dev, "Failed to map tx skb page\n"); 1767 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1768 ndev->stats.tx_errors++; 1769 goto err_free_descs; 1770 } 1771 1772 cppi5_hdesc_reset_hbdesc(next_desc); 1773 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1774 cppi5_hdesc_attach_buf(next_desc, 1775 buf_dma, frag_size, buf_dma, frag_size); 1776 1777 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1778 next_desc); 1779 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1780 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1781 1782 pkt_len += frag_size; 1783 cur_desc = next_desc; 1784 } 1785 WARN_ON(pkt_len != skb->len); 1786 1787 done_tx: 1788 skb_tx_timestamp(skb); 1789 1790 /* report bql before sending packet */ 1791 netdev_tx_sent_queue(netif_txq, pkt_len); 1792 1793 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1794 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1795 if (AM65_CPSW_IS_CPSW2G(common)) { 1796 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1797 } else { 1798 spin_lock_bh(&tx_chn->lock); 1799 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1800 spin_unlock_bh(&tx_chn->lock); 1801 } 1802 if (ret) { 1803 dev_err(dev, "can't push desc %d\n", ret); 1804 /* inform bql */ 1805 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1806 ndev->stats.tx_errors++; 1807 goto err_free_descs; 1808 } 1809 1810 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1811 netif_tx_stop_queue(netif_txq); 1812 /* Barrier, so that stop_queue visible to other cpus */ 1813 smp_mb__after_atomic(); 1814 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1815 1816 /* re-check for smp */ 1817 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1818 MAX_SKB_FRAGS) { 1819 netif_tx_wake_queue(netif_txq); 1820 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1821 } 1822 } 1823 1824 return NETDEV_TX_OK; 1825 1826 err_free_descs: 1827 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1828 err_free_skb: 1829 ndev->stats.tx_dropped++; 1830 dev_kfree_skb_any(skb); 1831 return NETDEV_TX_OK; 1832 1833 busy_free_descs: 1834 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1835 busy_stop_q: 1836 netif_tx_stop_queue(netif_txq); 1837 return NETDEV_TX_BUSY; 1838 } 1839 1840 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1841 void *addr) 1842 { 1843 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1844 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1845 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1846 int ret; 1847 1848 ret = eth_prepare_mac_addr_change(ndev, addr); 1849 if (ret < 0) 1850 return ret; 1851 1852 ret = pm_runtime_resume_and_get(common->dev); 1853 if (ret < 0) 1854 return ret; 1855 1856 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1857 HOST_PORT_NUM, 0, 0); 1858 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1859 HOST_PORT_NUM, ALE_SECURE, 0); 1860 1861 am65_cpsw_port_set_sl_mac(port, addr); 1862 eth_commit_mac_addr_change(ndev, sockaddr); 1863 1864 pm_runtime_put(common->dev); 1865 1866 return 0; 1867 } 1868 1869 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1870 struct ifreq *ifr) 1871 { 1872 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1873 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1874 struct hwtstamp_config cfg; 1875 1876 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1877 return -EOPNOTSUPP; 1878 1879 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1880 return -EFAULT; 1881 1882 /* TX HW timestamp */ 1883 switch (cfg.tx_type) { 1884 case HWTSTAMP_TX_OFF: 1885 case HWTSTAMP_TX_ON: 1886 break; 1887 default: 1888 return -ERANGE; 1889 } 1890 1891 switch (cfg.rx_filter) { 1892 case HWTSTAMP_FILTER_NONE: 1893 port->rx_ts_enabled = false; 1894 break; 1895 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1896 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1897 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1898 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1899 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1900 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1901 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1902 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1903 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1904 port->rx_ts_enabled = true; 1905 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1906 break; 1907 case HWTSTAMP_FILTER_ALL: 1908 case HWTSTAMP_FILTER_SOME: 1909 case HWTSTAMP_FILTER_NTP_ALL: 1910 return -EOPNOTSUPP; 1911 default: 1912 return -ERANGE; 1913 } 1914 1915 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1916 1917 /* cfg TX timestamp */ 1918 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1919 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1920 1921 ts_vlan_ltype = ETH_P_8021Q; 1922 1923 ts_ctrl_ltype2 = ETH_P_1588 | 1924 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1925 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1926 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1927 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1928 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1929 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1930 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1931 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1932 1933 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1934 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1935 1936 if (port->tx_ts_enabled) 1937 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1938 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1939 1940 if (port->rx_ts_enabled) 1941 ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN | 1942 AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN; 1943 1944 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1945 writel(ts_vlan_ltype, port->port_base + 1946 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1947 writel(ts_ctrl_ltype2, port->port_base + 1948 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1949 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1950 1951 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1952 } 1953 1954 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1955 struct ifreq *ifr) 1956 { 1957 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1958 struct hwtstamp_config cfg; 1959 1960 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1961 return -EOPNOTSUPP; 1962 1963 cfg.flags = 0; 1964 cfg.tx_type = port->tx_ts_enabled ? 1965 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1966 cfg.rx_filter = port->rx_ts_enabled ? 1967 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE; 1968 1969 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1970 } 1971 1972 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1973 struct ifreq *req, int cmd) 1974 { 1975 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1976 1977 if (!netif_running(ndev)) 1978 return -EINVAL; 1979 1980 switch (cmd) { 1981 case SIOCSHWTSTAMP: 1982 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1983 case SIOCGHWTSTAMP: 1984 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1985 } 1986 1987 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1988 } 1989 1990 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1991 struct rtnl_link_stats64 *stats) 1992 { 1993 dev_fetch_sw_netstats(stats, dev->tstats); 1994 1995 stats->rx_errors = dev->stats.rx_errors; 1996 stats->rx_dropped = dev->stats.rx_dropped; 1997 stats->tx_dropped = dev->stats.tx_dropped; 1998 } 1999 2000 static int am65_cpsw_xdp_prog_setup(struct net_device *ndev, 2001 struct bpf_prog *prog) 2002 { 2003 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 2004 bool running = netif_running(ndev); 2005 struct bpf_prog *old_prog; 2006 2007 if (running) 2008 am65_cpsw_nuss_ndo_slave_stop(ndev); 2009 2010 old_prog = xchg(&port->xdp_prog, prog); 2011 if (old_prog) 2012 bpf_prog_put(old_prog); 2013 2014 if (running) 2015 return am65_cpsw_nuss_ndo_slave_open(ndev); 2016 2017 return 0; 2018 } 2019 2020 static int am65_cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 2021 { 2022 switch (bpf->command) { 2023 case XDP_SETUP_PROG: 2024 return am65_cpsw_xdp_prog_setup(ndev, bpf->prog); 2025 default: 2026 return -EINVAL; 2027 } 2028 } 2029 2030 static int am65_cpsw_ndo_xdp_xmit(struct net_device *ndev, int n, 2031 struct xdp_frame **frames, u32 flags) 2032 { 2033 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2034 struct am65_cpsw_tx_chn *tx_chn; 2035 struct netdev_queue *netif_txq; 2036 int cpu = smp_processor_id(); 2037 int i, nxmit = 0; 2038 2039 tx_chn = &common->tx_chns[cpu % common->tx_ch_num]; 2040 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 2041 2042 __netif_tx_lock(netif_txq, cpu); 2043 for (i = 0; i < n; i++) { 2044 if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], 2045 AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) 2046 break; 2047 nxmit++; 2048 } 2049 __netif_tx_unlock(netif_txq); 2050 2051 return nxmit; 2052 } 2053 2054 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 2055 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 2056 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 2057 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 2058 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 2059 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 2060 .ndo_validate_addr = eth_validate_addr, 2061 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 2062 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 2063 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 2064 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 2065 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 2066 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 2067 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 2068 .ndo_bpf = am65_cpsw_ndo_bpf, 2069 .ndo_xdp_xmit = am65_cpsw_ndo_xdp_xmit, 2070 }; 2071 2072 static void am65_cpsw_disable_phy(struct phy *phy) 2073 { 2074 phy_power_off(phy); 2075 phy_exit(phy); 2076 } 2077 2078 static int am65_cpsw_enable_phy(struct phy *phy) 2079 { 2080 int ret; 2081 2082 ret = phy_init(phy); 2083 if (ret < 0) 2084 return ret; 2085 2086 ret = phy_power_on(phy); 2087 if (ret < 0) { 2088 phy_exit(phy); 2089 return ret; 2090 } 2091 2092 return 0; 2093 } 2094 2095 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 2096 { 2097 struct am65_cpsw_port *port; 2098 struct phy *phy; 2099 int i; 2100 2101 for (i = 0; i < common->port_num; i++) { 2102 port = &common->ports[i]; 2103 phy = port->slave.serdes_phy; 2104 if (phy) 2105 am65_cpsw_disable_phy(phy); 2106 } 2107 } 2108 2109 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 2110 struct am65_cpsw_port *port) 2111 { 2112 const char *name = "serdes"; 2113 struct phy *phy; 2114 int ret; 2115 2116 phy = devm_of_phy_optional_get(dev, port_np, name); 2117 if (IS_ERR_OR_NULL(phy)) 2118 return PTR_ERR_OR_ZERO(phy); 2119 2120 /* Serdes PHY exists. Store it. */ 2121 port->slave.serdes_phy = phy; 2122 2123 ret = am65_cpsw_enable_phy(phy); 2124 if (ret < 0) 2125 goto err_phy; 2126 2127 return 0; 2128 2129 err_phy: 2130 devm_phy_put(dev, phy); 2131 return ret; 2132 } 2133 2134 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 2135 const struct phylink_link_state *state) 2136 { 2137 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2138 phylink_config); 2139 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2140 struct am65_cpsw_common *common = port->common; 2141 2142 if (common->pdata.extra_modes & BIT(state->interface)) { 2143 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 2144 writel(ADVERTISE_SGMII, 2145 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 2146 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2147 } else { 2148 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2149 } 2150 2151 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 2152 cpsw_sl_ctl_set(port->slave.mac_sl, 2153 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2154 } else { 2155 cpsw_sl_ctl_clr(port->slave.mac_sl, 2156 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2157 } 2158 2159 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 2160 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 2161 } 2162 } 2163 2164 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 2165 phy_interface_t interface) 2166 { 2167 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2168 phylink_config); 2169 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2170 struct am65_cpsw_common *common = port->common; 2171 struct net_device *ndev = port->ndev; 2172 u32 mac_control; 2173 int tmo; 2174 2175 /* disable forwarding */ 2176 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2177 2178 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2179 2180 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 2181 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 2182 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 2183 2184 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 2185 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 2186 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 2187 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 2188 if (phy_interface_mode_is_rgmii(interface)) 2189 mac_control |= CPSW_SL_CTL_EXT_EN; 2190 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 2191 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 2192 2193 am65_cpsw_qos_link_down(ndev); 2194 netif_tx_stop_all_queues(ndev); 2195 } 2196 2197 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 2198 unsigned int mode, phy_interface_t interface, int speed, 2199 int duplex, bool tx_pause, bool rx_pause) 2200 { 2201 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2202 phylink_config); 2203 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2204 struct am65_cpsw_common *common = port->common; 2205 u32 mac_control = CPSW_SL_CTL_GMII_EN; 2206 struct net_device *ndev = port->ndev; 2207 2208 /* Bring the port out of idle state */ 2209 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2210 2211 if (speed == SPEED_1000) 2212 mac_control |= CPSW_SL_CTL_GIG; 2213 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 2214 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 2215 /* Can be used with in band mode only */ 2216 mac_control |= CPSW_SL_CTL_EXT_EN; 2217 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 2218 mac_control |= CPSW_SL_CTL_IFCTL_A; 2219 if (duplex) 2220 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 2221 2222 /* rx_pause/tx_pause */ 2223 if (rx_pause) 2224 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 2225 2226 if (tx_pause) 2227 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 2228 2229 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 2230 2231 /* enable forwarding */ 2232 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2233 2234 am65_cpsw_qos_link_up(ndev, speed); 2235 netif_tx_wake_all_queues(ndev); 2236 } 2237 2238 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 2239 .mac_config = am65_cpsw_nuss_mac_config, 2240 .mac_link_down = am65_cpsw_nuss_mac_link_down, 2241 .mac_link_up = am65_cpsw_nuss_mac_link_up, 2242 }; 2243 2244 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 2245 { 2246 struct am65_cpsw_common *common = port->common; 2247 2248 if (!port->disabled) 2249 return; 2250 2251 cpsw_ale_control_set(common->ale, port->port_id, 2252 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2253 2254 cpsw_sl_reset(port->slave.mac_sl, 100); 2255 cpsw_sl_ctl_reset(port->slave.mac_sl); 2256 } 2257 2258 static void am65_cpsw_nuss_free_tx_chns(void *data) 2259 { 2260 struct am65_cpsw_common *common = data; 2261 int i; 2262 2263 for (i = 0; i < common->tx_ch_num; i++) { 2264 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2265 2266 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2267 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2268 2269 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2270 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2271 2272 memset(tx_chn, 0, sizeof(*tx_chn)); 2273 } 2274 } 2275 2276 static void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 2277 { 2278 struct device *dev = common->dev; 2279 int i; 2280 2281 common->tx_ch_rate_msk = 0; 2282 for (i = 0; i < common->tx_ch_num; i++) { 2283 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2284 2285 if (tx_chn->irq > 0) 2286 devm_free_irq(dev, tx_chn->irq, tx_chn); 2287 2288 netif_napi_del(&tx_chn->napi_tx); 2289 } 2290 2291 am65_cpsw_nuss_free_tx_chns(common); 2292 } 2293 2294 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2295 { 2296 struct device *dev = common->dev; 2297 int i, ret = 0; 2298 2299 for (i = 0; i < common->tx_ch_num; i++) { 2300 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2301 2302 hrtimer_init(&tx_chn->tx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2303 tx_chn->tx_hrtimer.function = &am65_cpsw_nuss_tx_timer_callback; 2304 2305 ret = devm_request_irq(dev, tx_chn->irq, 2306 am65_cpsw_nuss_tx_irq, 2307 IRQF_TRIGGER_HIGH, 2308 tx_chn->tx_chn_name, tx_chn); 2309 if (ret) { 2310 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2311 tx_chn->id, tx_chn->irq, ret); 2312 goto err; 2313 } 2314 2315 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2316 am65_cpsw_nuss_tx_poll); 2317 } 2318 2319 return 0; 2320 2321 err: 2322 for (--i ; i >= 0 ; i--) { 2323 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2324 2325 netif_napi_del(&tx_chn->napi_tx); 2326 devm_free_irq(dev, tx_chn->irq, tx_chn); 2327 } 2328 2329 return ret; 2330 } 2331 2332 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 2333 { 2334 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 2335 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 2336 struct device *dev = common->dev; 2337 struct k3_ring_cfg ring_cfg = { 2338 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2339 .mode = K3_RINGACC_RING_MODE_RING, 2340 .flags = 0 2341 }; 2342 u32 hdesc_size, hdesc_size_out; 2343 int i, ret = 0; 2344 2345 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2346 AM65_CPSW_NAV_SW_DATA_SIZE); 2347 2348 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2349 tx_cfg.tx_cfg = ring_cfg; 2350 tx_cfg.txcq_cfg = ring_cfg; 2351 tx_cfg.tx_cfg.size = max_desc_num; 2352 tx_cfg.txcq_cfg.size = max_desc_num; 2353 2354 for (i = 0; i < common->tx_ch_num; i++) { 2355 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2356 2357 snprintf(tx_chn->tx_chn_name, 2358 sizeof(tx_chn->tx_chn_name), "tx%d", i); 2359 2360 spin_lock_init(&tx_chn->lock); 2361 tx_chn->common = common; 2362 tx_chn->id = i; 2363 tx_chn->descs_num = max_desc_num; 2364 2365 tx_chn->tx_chn = 2366 k3_udma_glue_request_tx_chn(dev, 2367 tx_chn->tx_chn_name, 2368 &tx_cfg); 2369 if (IS_ERR(tx_chn->tx_chn)) { 2370 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 2371 "Failed to request tx dma channel\n"); 2372 goto err; 2373 } 2374 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 2375 2376 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 2377 tx_chn->descs_num, 2378 hdesc_size, 2379 tx_chn->tx_chn_name); 2380 if (IS_ERR(tx_chn->desc_pool)) { 2381 ret = PTR_ERR(tx_chn->desc_pool); 2382 dev_err(dev, "Failed to create poll %d\n", ret); 2383 goto err; 2384 } 2385 2386 hdesc_size_out = k3_cppi_desc_pool_desc_size(tx_chn->desc_pool); 2387 tx_chn->dsize_log2 = __fls(hdesc_size_out); 2388 WARN_ON(hdesc_size_out != (1 << tx_chn->dsize_log2)); 2389 2390 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 2391 if (tx_chn->irq < 0) { 2392 dev_err(dev, "Failed to get tx dma irq %d\n", 2393 tx_chn->irq); 2394 ret = tx_chn->irq; 2395 goto err; 2396 } 2397 2398 snprintf(tx_chn->tx_chn_name, 2399 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 2400 dev_name(dev), tx_chn->id); 2401 } 2402 2403 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2404 if (ret) { 2405 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 2406 goto err; 2407 } 2408 2409 return 0; 2410 2411 err: 2412 am65_cpsw_nuss_free_tx_chns(common); 2413 2414 return ret; 2415 } 2416 2417 static void am65_cpsw_nuss_free_rx_chns(void *data) 2418 { 2419 struct am65_cpsw_common *common = data; 2420 struct am65_cpsw_rx_chn *rx_chn; 2421 2422 rx_chn = &common->rx_chns; 2423 2424 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 2425 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 2426 2427 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 2428 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 2429 } 2430 2431 static void am65_cpsw_nuss_remove_rx_chns(struct am65_cpsw_common *common) 2432 { 2433 struct device *dev = common->dev; 2434 struct am65_cpsw_rx_chn *rx_chn; 2435 struct am65_cpsw_rx_flow *flows; 2436 int i; 2437 2438 rx_chn = &common->rx_chns; 2439 flows = rx_chn->flows; 2440 2441 for (i = 0; i < common->rx_ch_num_flows; i++) { 2442 if (!(flows[i].irq < 0)) 2443 devm_free_irq(dev, flows[i].irq, &flows[i]); 2444 netif_napi_del(&flows[i].napi_rx); 2445 } 2446 2447 am65_cpsw_nuss_free_rx_chns(common); 2448 2449 common->rx_flow_id_base = -1; 2450 } 2451 2452 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 2453 { 2454 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 2455 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 2456 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 2457 struct device *dev = common->dev; 2458 struct am65_cpsw_rx_flow *flow; 2459 u32 hdesc_size, hdesc_size_out; 2460 u32 fdqring_id; 2461 int i, ret = 0; 2462 2463 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2464 AM65_CPSW_NAV_SW_DATA_SIZE); 2465 2466 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2467 rx_cfg.flow_id_num = common->rx_ch_num_flows; 2468 rx_cfg.flow_id_base = common->rx_flow_id_base; 2469 2470 /* init all flows */ 2471 rx_chn->dev = dev; 2472 rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; 2473 2474 for (i = 0; i < common->rx_ch_num_flows; i++) { 2475 flow = &rx_chn->flows[i]; 2476 flow->page_pool = NULL; 2477 } 2478 2479 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 2480 if (IS_ERR(rx_chn->rx_chn)) { 2481 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 2482 "Failed to request rx dma channel\n"); 2483 goto err; 2484 } 2485 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 2486 2487 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 2488 rx_chn->descs_num, 2489 hdesc_size, "rx"); 2490 if (IS_ERR(rx_chn->desc_pool)) { 2491 ret = PTR_ERR(rx_chn->desc_pool); 2492 dev_err(dev, "Failed to create rx poll %d\n", ret); 2493 goto err; 2494 } 2495 2496 hdesc_size_out = k3_cppi_desc_pool_desc_size(rx_chn->desc_pool); 2497 rx_chn->dsize_log2 = __fls(hdesc_size_out); 2498 WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); 2499 2500 common->rx_flow_id_base = 2501 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 2502 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 2503 2504 fdqring_id = K3_RINGACC_RING_ID_ANY; 2505 for (i = 0; i < rx_cfg.flow_id_num; i++) { 2506 struct k3_ring_cfg rxring_cfg = { 2507 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2508 .mode = K3_RINGACC_RING_MODE_RING, 2509 .flags = 0, 2510 }; 2511 struct k3_ring_cfg fdqring_cfg = { 2512 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2513 .flags = K3_RINGACC_RING_SHARED, 2514 }; 2515 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 2516 .rx_cfg = rxring_cfg, 2517 .rxfdq_cfg = fdqring_cfg, 2518 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 2519 .src_tag_lo_sel = 2520 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 2521 }; 2522 2523 flow = &rx_chn->flows[i]; 2524 flow->id = i; 2525 flow->common = common; 2526 flow->irq = -EINVAL; 2527 2528 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 2529 rx_flow_cfg.rx_cfg.size = max_desc_num; 2530 /* share same FDQ for all flows */ 2531 rx_flow_cfg.rxfdq_cfg.size = max_desc_num * rx_cfg.flow_id_num; 2532 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 2533 2534 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 2535 i, &rx_flow_cfg); 2536 if (ret) { 2537 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 2538 goto err_flow; 2539 } 2540 if (!i) 2541 fdqring_id = 2542 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 2543 i); 2544 2545 flow->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 2546 if (flow->irq <= 0) { 2547 dev_err(dev, "Failed to get rx dma irq %d\n", 2548 flow->irq); 2549 ret = flow->irq; 2550 goto err_flow; 2551 } 2552 2553 snprintf(flow->name, 2554 sizeof(flow->name), "%s-rx%d", 2555 dev_name(dev), i); 2556 hrtimer_init(&flow->rx_hrtimer, CLOCK_MONOTONIC, 2557 HRTIMER_MODE_REL_PINNED); 2558 flow->rx_hrtimer.function = &am65_cpsw_nuss_rx_timer_callback; 2559 2560 ret = devm_request_irq(dev, flow->irq, 2561 am65_cpsw_nuss_rx_irq, 2562 IRQF_TRIGGER_HIGH, 2563 flow->name, flow); 2564 if (ret) { 2565 dev_err(dev, "failure requesting rx %d irq %u, %d\n", 2566 i, flow->irq, ret); 2567 flow->irq = -EINVAL; 2568 goto err_flow; 2569 } 2570 2571 netif_napi_add(common->dma_ndev, &flow->napi_rx, 2572 am65_cpsw_nuss_rx_poll); 2573 } 2574 2575 /* setup classifier to route priorities to flows */ 2576 cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); 2577 2578 return 0; 2579 2580 err_flow: 2581 for (--i; i >= 0 ; i--) { 2582 flow = &rx_chn->flows[i]; 2583 netif_napi_del(&flow->napi_rx); 2584 devm_free_irq(dev, flow->irq, flow); 2585 } 2586 2587 err: 2588 am65_cpsw_nuss_free_rx_chns(common); 2589 2590 return ret; 2591 } 2592 2593 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 2594 { 2595 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2596 2597 host_p->common = common; 2598 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 2599 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 2600 2601 return 0; 2602 } 2603 2604 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 2605 int slave, u8 *mac_addr) 2606 { 2607 u32 mac_lo, mac_hi, offset; 2608 struct regmap *syscon; 2609 2610 syscon = syscon_regmap_lookup_by_phandle_args(of_node, "ti,syscon-efuse", 2611 1, &offset); 2612 if (IS_ERR(syscon)) { 2613 if (PTR_ERR(syscon) == -ENODEV) 2614 return 0; 2615 return PTR_ERR(syscon); 2616 } 2617 2618 regmap_read(syscon, offset, &mac_lo); 2619 regmap_read(syscon, offset + 4, &mac_hi); 2620 2621 mac_addr[0] = (mac_hi >> 8) & 0xff; 2622 mac_addr[1] = mac_hi & 0xff; 2623 mac_addr[2] = (mac_lo >> 24) & 0xff; 2624 mac_addr[3] = (mac_lo >> 16) & 0xff; 2625 mac_addr[4] = (mac_lo >> 8) & 0xff; 2626 mac_addr[5] = mac_lo & 0xff; 2627 2628 return 0; 2629 } 2630 2631 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 2632 { 2633 struct device *dev = common->dev; 2634 struct device_node *node; 2635 struct am65_cpts *cpts; 2636 void __iomem *reg_base; 2637 2638 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 2639 return 0; 2640 2641 node = of_get_child_by_name(dev->of_node, "cpts"); 2642 if (!node) { 2643 dev_err(dev, "%s cpts not found\n", __func__); 2644 return -ENOENT; 2645 } 2646 2647 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 2648 cpts = am65_cpts_create(dev, reg_base, node); 2649 if (IS_ERR(cpts)) { 2650 int ret = PTR_ERR(cpts); 2651 2652 of_node_put(node); 2653 dev_err(dev, "cpts create err %d\n", ret); 2654 return ret; 2655 } 2656 common->cpts = cpts; 2657 /* Forbid PM runtime if CPTS is running. 2658 * K3 CPSWxG modules may completely lose context during ON->OFF 2659 * transitions depending on integration. 2660 * AM65x/J721E MCU CPSW2G: false 2661 * J721E MAIN_CPSW9G: true 2662 */ 2663 pm_runtime_forbid(dev); 2664 2665 return 0; 2666 } 2667 2668 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2669 { 2670 struct device_node *node, *port_np; 2671 struct device *dev = common->dev; 2672 int ret; 2673 2674 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2675 if (!node) 2676 return -ENOENT; 2677 2678 for_each_child_of_node(node, port_np) { 2679 struct am65_cpsw_port *port; 2680 u32 port_id; 2681 2682 /* it is not a slave port node, continue */ 2683 if (strcmp(port_np->name, "port")) 2684 continue; 2685 2686 ret = of_property_read_u32(port_np, "reg", &port_id); 2687 if (ret < 0) { 2688 dev_err(dev, "%pOF error reading port_id %d\n", 2689 port_np, ret); 2690 goto of_node_put; 2691 } 2692 2693 if (!port_id || port_id > common->port_num) { 2694 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2695 port_np, port_id, port_np->name); 2696 ret = -EINVAL; 2697 goto of_node_put; 2698 } 2699 2700 port = am65_common_get_port(common, port_id); 2701 port->port_id = port_id; 2702 port->common = common; 2703 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2704 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2705 if (common->pdata.extra_modes) 2706 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2707 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2708 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2709 port->name = of_get_property(port_np, "label", NULL); 2710 port->fetch_ram_base = 2711 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2712 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2713 2714 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2715 if (IS_ERR(port->slave.mac_sl)) { 2716 ret = PTR_ERR(port->slave.mac_sl); 2717 goto of_node_put; 2718 } 2719 2720 port->disabled = !of_device_is_available(port_np); 2721 if (port->disabled) { 2722 common->disabled_ports_mask |= BIT(port->port_id); 2723 continue; 2724 } 2725 2726 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2727 if (IS_ERR(port->slave.ifphy)) { 2728 ret = PTR_ERR(port->slave.ifphy); 2729 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2730 port_np, ret); 2731 goto of_node_put; 2732 } 2733 2734 /* Initialize the Serdes PHY for the port */ 2735 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2736 if (ret) 2737 goto of_node_put; 2738 2739 port->slave.mac_only = 2740 of_property_read_bool(port_np, "ti,mac-only"); 2741 2742 /* get phy/link info */ 2743 port->slave.port_np = port_np; 2744 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2745 if (ret) { 2746 dev_err(dev, "%pOF read phy-mode err %d\n", 2747 port_np, ret); 2748 goto of_node_put; 2749 } 2750 2751 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2752 if (ret) 2753 goto of_node_put; 2754 2755 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2756 if (ret) { 2757 am65_cpsw_am654_get_efuse_macid(port_np, 2758 port->port_id, 2759 port->slave.mac_addr); 2760 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2761 eth_random_addr(port->slave.mac_addr); 2762 dev_err(dev, "Use random MAC address\n"); 2763 } 2764 } 2765 2766 /* Reset all Queue priorities to 0 */ 2767 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); 2768 } 2769 of_node_put(node); 2770 2771 /* is there at least one ext.port */ 2772 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2773 dev_err(dev, "No Ext. port are available\n"); 2774 return -ENODEV; 2775 } 2776 2777 return 0; 2778 2779 of_node_put: 2780 of_node_put(port_np); 2781 of_node_put(node); 2782 return ret; 2783 } 2784 2785 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2786 { 2787 struct am65_cpsw_port *port; 2788 int i; 2789 2790 for (i = 0; i < common->port_num; i++) { 2791 port = &common->ports[i]; 2792 if (port->slave.phylink) 2793 phylink_destroy(port->slave.phylink); 2794 } 2795 } 2796 2797 static int 2798 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2799 { 2800 struct am65_cpsw_ndev_priv *ndev_priv; 2801 struct device *dev = common->dev; 2802 struct am65_cpsw_port *port; 2803 struct phylink *phylink; 2804 2805 port = &common->ports[port_idx]; 2806 2807 if (port->disabled) 2808 return 0; 2809 2810 /* alloc netdev */ 2811 port->ndev = alloc_etherdev_mqs(sizeof(struct am65_cpsw_ndev_priv), 2812 AM65_CPSW_MAX_QUEUES, 2813 AM65_CPSW_MAX_QUEUES); 2814 if (!port->ndev) { 2815 dev_err(dev, "error allocating slave net_device %u\n", 2816 port->port_id); 2817 return -ENOMEM; 2818 } 2819 2820 ndev_priv = netdev_priv(port->ndev); 2821 ndev_priv->port = port; 2822 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2823 mutex_init(&ndev_priv->mm_lock); 2824 port->qos.link_speed = SPEED_UNKNOWN; 2825 SET_NETDEV_DEV(port->ndev, dev); 2826 port->ndev->dev.of_node = port->slave.port_np; 2827 2828 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2829 2830 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2831 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE - 2832 (VLAN_ETH_HLEN + ETH_FCS_LEN); 2833 port->ndev->hw_features = NETIF_F_SG | 2834 NETIF_F_RXCSUM | 2835 NETIF_F_HW_CSUM | 2836 NETIF_F_HW_TC; 2837 port->ndev->features = port->ndev->hw_features | 2838 NETIF_F_HW_VLAN_CTAG_FILTER; 2839 port->ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 2840 NETDEV_XDP_ACT_REDIRECT | 2841 NETDEV_XDP_ACT_NDO_XMIT; 2842 port->ndev->vlan_features |= NETIF_F_SG; 2843 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2844 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2845 2846 /* Configuring Phylink */ 2847 port->slave.phylink_config.dev = &port->ndev->dev; 2848 port->slave.phylink_config.type = PHYLINK_NETDEV; 2849 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2850 MAC_1000FD | MAC_5000FD; 2851 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2852 2853 switch (port->slave.phy_if) { 2854 case PHY_INTERFACE_MODE_RGMII: 2855 case PHY_INTERFACE_MODE_RGMII_ID: 2856 case PHY_INTERFACE_MODE_RGMII_RXID: 2857 case PHY_INTERFACE_MODE_RGMII_TXID: 2858 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2859 break; 2860 2861 case PHY_INTERFACE_MODE_RMII: 2862 __set_bit(PHY_INTERFACE_MODE_RMII, 2863 port->slave.phylink_config.supported_interfaces); 2864 break; 2865 2866 case PHY_INTERFACE_MODE_QSGMII: 2867 case PHY_INTERFACE_MODE_SGMII: 2868 case PHY_INTERFACE_MODE_USXGMII: 2869 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2870 __set_bit(port->slave.phy_if, 2871 port->slave.phylink_config.supported_interfaces); 2872 } else { 2873 dev_err(dev, "selected phy-mode is not supported\n"); 2874 return -EOPNOTSUPP; 2875 } 2876 break; 2877 2878 default: 2879 dev_err(dev, "selected phy-mode is not supported\n"); 2880 return -EOPNOTSUPP; 2881 } 2882 2883 phylink = phylink_create(&port->slave.phylink_config, 2884 of_fwnode_handle(port->slave.port_np), 2885 port->slave.phy_if, 2886 &am65_cpsw_phylink_mac_ops); 2887 if (IS_ERR(phylink)) 2888 return PTR_ERR(phylink); 2889 2890 port->slave.phylink = phylink; 2891 2892 /* Disable TX checksum offload by default due to HW bug */ 2893 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2894 port->ndev->features &= ~NETIF_F_HW_CSUM; 2895 2896 port->ndev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 2897 port->xdp_prog = NULL; 2898 2899 if (!common->dma_ndev) 2900 common->dma_ndev = port->ndev; 2901 2902 return 0; 2903 } 2904 2905 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2906 { 2907 int ret; 2908 int i; 2909 2910 for (i = 0; i < common->port_num; i++) { 2911 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2912 if (ret) 2913 return ret; 2914 } 2915 2916 return ret; 2917 } 2918 2919 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2920 { 2921 struct am65_cpsw_port *port; 2922 int i; 2923 2924 for (i = 0; i < common->port_num; i++) { 2925 port = &common->ports[i]; 2926 if (!port->ndev) 2927 continue; 2928 if (port->ndev->reg_state == NETREG_REGISTERED) 2929 unregister_netdev(port->ndev); 2930 free_netdev(port->ndev); 2931 port->ndev = NULL; 2932 } 2933 } 2934 2935 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2936 { 2937 int set_val = 0; 2938 int i; 2939 2940 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2941 set_val = 1; 2942 2943 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2944 2945 for (i = 1; i <= common->port_num; i++) { 2946 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2947 struct am65_cpsw_ndev_priv *priv; 2948 2949 if (!port->ndev) 2950 continue; 2951 2952 priv = am65_ndev_to_priv(port->ndev); 2953 priv->offload_fwd_mark = set_val; 2954 } 2955 } 2956 2957 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2958 { 2959 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2960 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2961 2962 return !common->is_emac_mode; 2963 } 2964 2965 return false; 2966 } 2967 2968 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2969 struct net_device *br_ndev, 2970 struct netlink_ext_ack *extack) 2971 { 2972 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2973 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2974 int err; 2975 2976 if (!common->br_members) { 2977 common->hw_bridge_dev = br_ndev; 2978 } else { 2979 /* This is adding the port to a second bridge, this is 2980 * unsupported 2981 */ 2982 if (common->hw_bridge_dev != br_ndev) 2983 return -EOPNOTSUPP; 2984 } 2985 2986 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2987 false, extack); 2988 if (err) 2989 return err; 2990 2991 common->br_members |= BIT(priv->port->port_id); 2992 2993 am65_cpsw_port_offload_fwd_mark_update(common); 2994 2995 return NOTIFY_DONE; 2996 } 2997 2998 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2999 { 3000 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 3001 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 3002 3003 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 3004 3005 common->br_members &= ~BIT(priv->port->port_id); 3006 3007 am65_cpsw_port_offload_fwd_mark_update(common); 3008 3009 if (!common->br_members) 3010 common->hw_bridge_dev = NULL; 3011 } 3012 3013 /* netdev notifier */ 3014 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 3015 unsigned long event, void *ptr) 3016 { 3017 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 3018 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 3019 struct netdev_notifier_changeupper_info *info; 3020 int ret = NOTIFY_DONE; 3021 3022 if (!am65_cpsw_port_dev_check(ndev)) 3023 return NOTIFY_DONE; 3024 3025 switch (event) { 3026 case NETDEV_CHANGEUPPER: 3027 info = ptr; 3028 3029 if (netif_is_bridge_master(info->upper_dev)) { 3030 if (info->linking) 3031 ret = am65_cpsw_netdevice_port_link(ndev, 3032 info->upper_dev, 3033 extack); 3034 else 3035 am65_cpsw_netdevice_port_unlink(ndev); 3036 } 3037 break; 3038 default: 3039 return NOTIFY_DONE; 3040 } 3041 3042 return notifier_from_errno(ret); 3043 } 3044 3045 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 3046 { 3047 int ret = 0; 3048 3049 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3050 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3051 return 0; 3052 3053 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 3054 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3055 if (ret) { 3056 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 3057 return ret; 3058 } 3059 3060 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 3061 if (ret) 3062 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3063 3064 return ret; 3065 } 3066 3067 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 3068 { 3069 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3070 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3071 return; 3072 3073 am65_cpsw_switchdev_unregister_notifiers(cpsw); 3074 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3075 } 3076 3077 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 3078 3079 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 3080 { 3081 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 3082 ALE_MCAST_BLOCK_LEARN_FWD); 3083 } 3084 3085 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 3086 { 3087 struct am65_cpsw_host *host = am65_common_get_host(common); 3088 3089 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3090 3091 am65_cpsw_init_stp_ale_entry(common); 3092 3093 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 3094 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 3095 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 3096 } 3097 3098 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 3099 { 3100 struct am65_cpsw_host *host = am65_common_get_host(common); 3101 3102 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3103 3104 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 3105 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 3106 3107 /* learning make no sense in multi-mac mode */ 3108 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 3109 } 3110 3111 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 3112 struct devlink_param_gset_ctx *ctx) 3113 { 3114 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3115 struct am65_cpsw_common *common = dl_priv->common; 3116 3117 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 3118 3119 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3120 return -EOPNOTSUPP; 3121 3122 ctx->val.vbool = !common->is_emac_mode; 3123 3124 return 0; 3125 } 3126 3127 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 3128 { 3129 struct am65_cpsw_slave_data *slave = &port->slave; 3130 struct am65_cpsw_common *common = port->common; 3131 u32 port_mask; 3132 3133 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3134 3135 if (slave->mac_only) 3136 /* enable mac-only mode on port */ 3137 cpsw_ale_control_set(common->ale, port->port_id, 3138 ALE_PORT_MACONLY, 1); 3139 3140 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 3141 3142 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3143 3144 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 3145 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 3146 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 3147 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 3148 } 3149 3150 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 3151 { 3152 struct am65_cpsw_slave_data *slave = &port->slave; 3153 struct am65_cpsw_common *cpsw = port->common; 3154 u32 port_mask; 3155 3156 cpsw_ale_control_set(cpsw->ale, port->port_id, 3157 ALE_PORT_NOLEARN, 0); 3158 3159 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 3160 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 3161 slave->port_vlan); 3162 3163 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3164 3165 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 3166 port_mask, ALE_VLAN, slave->port_vlan, 3167 ALE_MCAST_FWD_2); 3168 3169 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3170 3171 cpsw_ale_control_set(cpsw->ale, port->port_id, 3172 ALE_PORT_MACONLY, 0); 3173 } 3174 3175 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 3176 struct devlink_param_gset_ctx *ctx, 3177 struct netlink_ext_ack *extack) 3178 { 3179 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3180 struct am65_cpsw_common *cpsw = dl_priv->common; 3181 bool switch_en = ctx->val.vbool; 3182 bool if_running = false; 3183 int i; 3184 3185 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 3186 3187 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3188 return -EOPNOTSUPP; 3189 3190 if (switch_en == !cpsw->is_emac_mode) 3191 return 0; 3192 3193 if (!switch_en && cpsw->br_members) { 3194 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 3195 return -EINVAL; 3196 } 3197 3198 rtnl_lock(); 3199 3200 cpsw->is_emac_mode = !switch_en; 3201 3202 for (i = 0; i < cpsw->port_num; i++) { 3203 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3204 3205 if (!sl_ndev || !netif_running(sl_ndev)) 3206 continue; 3207 3208 if_running = true; 3209 } 3210 3211 if (!if_running) { 3212 /* all ndevs are down */ 3213 for (i = 0; i < cpsw->port_num; i++) { 3214 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3215 struct am65_cpsw_slave_data *slave; 3216 3217 if (!sl_ndev) 3218 continue; 3219 3220 slave = am65_ndev_to_slave(sl_ndev); 3221 if (switch_en) 3222 slave->port_vlan = cpsw->default_vlan; 3223 else 3224 slave->port_vlan = 0; 3225 } 3226 3227 goto exit; 3228 } 3229 3230 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 3231 /* clean up ALE table */ 3232 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 3233 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 3234 3235 if (switch_en) { 3236 dev_info(cpsw->dev, "Enable switch mode\n"); 3237 3238 am65_cpsw_init_host_port_switch(cpsw); 3239 3240 for (i = 0; i < cpsw->port_num; i++) { 3241 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3242 struct am65_cpsw_slave_data *slave; 3243 struct am65_cpsw_port *port; 3244 3245 if (!sl_ndev) 3246 continue; 3247 3248 port = am65_ndev_to_port(sl_ndev); 3249 slave = am65_ndev_to_slave(sl_ndev); 3250 slave->port_vlan = cpsw->default_vlan; 3251 3252 if (netif_running(sl_ndev)) 3253 am65_cpsw_init_port_switch_ale(port); 3254 } 3255 3256 } else { 3257 dev_info(cpsw->dev, "Disable switch mode\n"); 3258 3259 am65_cpsw_init_host_port_emac(cpsw); 3260 3261 for (i = 0; i < cpsw->port_num; i++) { 3262 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3263 struct am65_cpsw_port *port; 3264 3265 if (!sl_ndev) 3266 continue; 3267 3268 port = am65_ndev_to_port(sl_ndev); 3269 port->slave.port_vlan = 0; 3270 if (netif_running(sl_ndev)) 3271 am65_cpsw_init_port_emac_ale(port); 3272 } 3273 } 3274 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 3275 exit: 3276 rtnl_unlock(); 3277 3278 return 0; 3279 } 3280 3281 static const struct devlink_param am65_cpsw_devlink_params[] = { 3282 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 3283 DEVLINK_PARAM_TYPE_BOOL, 3284 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3285 am65_cpsw_dl_switch_mode_get, 3286 am65_cpsw_dl_switch_mode_set, NULL), 3287 }; 3288 3289 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 3290 { 3291 struct devlink_port_attrs attrs = {}; 3292 struct am65_cpsw_devlink *dl_priv; 3293 struct device *dev = common->dev; 3294 struct devlink_port *dl_port; 3295 struct am65_cpsw_port *port; 3296 int ret = 0; 3297 int i; 3298 3299 common->devlink = 3300 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 3301 if (!common->devlink) 3302 return -ENOMEM; 3303 3304 dl_priv = devlink_priv(common->devlink); 3305 dl_priv->common = common; 3306 3307 /* Provide devlink hook to switch mode when multiple external ports 3308 * are present NUSS switchdev driver is enabled. 3309 */ 3310 if (!AM65_CPSW_IS_CPSW2G(common) && 3311 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 3312 ret = devlink_params_register(common->devlink, 3313 am65_cpsw_devlink_params, 3314 ARRAY_SIZE(am65_cpsw_devlink_params)); 3315 if (ret) { 3316 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 3317 goto dl_unreg; 3318 } 3319 } 3320 3321 for (i = 1; i <= common->port_num; i++) { 3322 port = am65_common_get_port(common, i); 3323 dl_port = &port->devlink_port; 3324 3325 if (port->ndev) 3326 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 3327 else 3328 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 3329 attrs.phys.port_number = port->port_id; 3330 attrs.switch_id.id_len = sizeof(resource_size_t); 3331 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 3332 devlink_port_attrs_set(dl_port, &attrs); 3333 3334 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 3335 if (ret) { 3336 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 3337 port->port_id, ret); 3338 goto dl_port_unreg; 3339 } 3340 } 3341 devlink_register(common->devlink); 3342 return ret; 3343 3344 dl_port_unreg: 3345 for (i = i - 1; i >= 1; i--) { 3346 port = am65_common_get_port(common, i); 3347 dl_port = &port->devlink_port; 3348 3349 devlink_port_unregister(dl_port); 3350 } 3351 dl_unreg: 3352 devlink_free(common->devlink); 3353 return ret; 3354 } 3355 3356 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 3357 { 3358 struct devlink_port *dl_port; 3359 struct am65_cpsw_port *port; 3360 int i; 3361 3362 devlink_unregister(common->devlink); 3363 3364 for (i = 1; i <= common->port_num; i++) { 3365 port = am65_common_get_port(common, i); 3366 dl_port = &port->devlink_port; 3367 3368 devlink_port_unregister(dl_port); 3369 } 3370 3371 if (!AM65_CPSW_IS_CPSW2G(common) && 3372 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3373 devlink_params_unregister(common->devlink, 3374 am65_cpsw_devlink_params, 3375 ARRAY_SIZE(am65_cpsw_devlink_params)); 3376 3377 devlink_free(common->devlink); 3378 } 3379 3380 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 3381 { 3382 struct am65_cpsw_rx_chn *rx_chan = &common->rx_chns; 3383 struct am65_cpsw_tx_chn *tx_chan = common->tx_chns; 3384 struct device *dev = common->dev; 3385 struct am65_cpsw_port *port; 3386 int ret = 0, i; 3387 3388 /* init tx channels */ 3389 ret = am65_cpsw_nuss_init_tx_chns(common); 3390 if (ret) 3391 return ret; 3392 ret = am65_cpsw_nuss_init_rx_chns(common); 3393 if (ret) 3394 goto err_remove_tx; 3395 3396 /* The DMA Channels are not guaranteed to be in a clean state. 3397 * Reset and disable them to ensure that they are back to the 3398 * clean state and ready to be used. 3399 */ 3400 for (i = 0; i < common->tx_ch_num; i++) { 3401 k3_udma_glue_reset_tx_chn(tx_chan[i].tx_chn, &tx_chan[i], 3402 am65_cpsw_nuss_tx_cleanup); 3403 k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); 3404 } 3405 3406 for (i = 0; i < common->rx_ch_num_flows; i++) 3407 k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, 3408 rx_chan, 3409 am65_cpsw_nuss_rx_cleanup, !!i); 3410 3411 k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); 3412 3413 ret = am65_cpsw_nuss_register_devlink(common); 3414 if (ret) 3415 goto err_remove_rx; 3416 3417 for (i = 0; i < common->port_num; i++) { 3418 port = &common->ports[i]; 3419 3420 if (!port->ndev) 3421 continue; 3422 3423 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 3424 3425 ret = register_netdev(port->ndev); 3426 if (ret) { 3427 dev_err(dev, "error registering slave net device%i %d\n", 3428 i, ret); 3429 goto err_cleanup_ndev; 3430 } 3431 } 3432 3433 ret = am65_cpsw_register_notifiers(common); 3434 if (ret) 3435 goto err_cleanup_ndev; 3436 3437 /* can't auto unregister ndev using devm_add_action() due to 3438 * devres release sequence in DD core for DMA 3439 */ 3440 3441 return 0; 3442 3443 err_cleanup_ndev: 3444 am65_cpsw_nuss_cleanup_ndev(common); 3445 am65_cpsw_unregister_devlink(common); 3446 err_remove_rx: 3447 am65_cpsw_nuss_remove_rx_chns(common); 3448 err_remove_tx: 3449 am65_cpsw_nuss_remove_tx_chns(common); 3450 3451 return ret; 3452 } 3453 3454 int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, 3455 int num_tx, int num_rx) 3456 { 3457 int ret; 3458 3459 am65_cpsw_nuss_remove_tx_chns(common); 3460 am65_cpsw_nuss_remove_rx_chns(common); 3461 3462 common->tx_ch_num = num_tx; 3463 common->rx_ch_num_flows = num_rx; 3464 ret = am65_cpsw_nuss_init_tx_chns(common); 3465 if (ret) 3466 return ret; 3467 3468 ret = am65_cpsw_nuss_init_rx_chns(common); 3469 if (ret) 3470 am65_cpsw_nuss_remove_tx_chns(common); 3471 3472 return ret; 3473 } 3474 3475 struct am65_cpsw_soc_pdata { 3476 u32 quirks_dis; 3477 }; 3478 3479 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 3480 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3481 }; 3482 3483 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 3484 { .family = "AM65X", 3485 .revision = "SR2.0", 3486 .data = &am65x_soc_sr2_0 3487 }, 3488 {/* sentinel */} 3489 }; 3490 3491 static const struct am65_cpsw_pdata am65x_sr1_0 = { 3492 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3493 .ale_dev_id = "am65x-cpsw2g", 3494 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3495 }; 3496 3497 static const struct am65_cpsw_pdata j721e_pdata = { 3498 .quirks = 0, 3499 .ale_dev_id = "am65x-cpsw2g", 3500 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3501 }; 3502 3503 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 3504 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 3505 .ale_dev_id = "am64-cpswxg", 3506 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3507 }; 3508 3509 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 3510 .quirks = 0, 3511 .ale_dev_id = "am64-cpswxg", 3512 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3513 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3514 BIT(PHY_INTERFACE_MODE_USXGMII), 3515 }; 3516 3517 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 3518 .quirks = 0, 3519 .ale_dev_id = "am64-cpswxg", 3520 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3521 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3522 }; 3523 3524 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 3525 .quirks = 0, 3526 .ale_dev_id = "am64-cpswxg", 3527 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3528 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3529 BIT(PHY_INTERFACE_MODE_USXGMII), 3530 }; 3531 3532 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 3533 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 3534 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 3535 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 3536 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 3537 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 3538 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 3539 { /* sentinel */ }, 3540 }; 3541 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 3542 3543 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 3544 { 3545 const struct soc_device_attribute *soc; 3546 3547 soc = soc_device_match(am65_cpsw_socinfo); 3548 if (soc && soc->data) { 3549 const struct am65_cpsw_soc_pdata *socdata = soc->data; 3550 3551 /* disable quirks */ 3552 common->pdata.quirks &= ~socdata->quirks_dis; 3553 } 3554 } 3555 3556 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 3557 { 3558 struct cpsw_ale_params ale_params = { 0 }; 3559 const struct of_device_id *of_id; 3560 struct device *dev = &pdev->dev; 3561 struct am65_cpsw_common *common; 3562 struct device_node *node; 3563 struct resource *res; 3564 struct clk *clk; 3565 int ale_entries; 3566 __be64 id_temp; 3567 int ret, i; 3568 3569 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 3570 if (!common) 3571 return -ENOMEM; 3572 common->dev = dev; 3573 3574 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 3575 if (!of_id) 3576 return -EINVAL; 3577 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 3578 3579 am65_cpsw_nuss_apply_socinfo(common); 3580 3581 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 3582 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 3583 if (IS_ERR(common->ss_base)) 3584 return PTR_ERR(common->ss_base); 3585 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 3586 /* Use device's physical base address as switch id */ 3587 id_temp = cpu_to_be64(res->start); 3588 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 3589 3590 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 3591 if (!node) 3592 return -ENOENT; 3593 common->port_num = of_get_child_count(node); 3594 of_node_put(node); 3595 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 3596 return -ENOENT; 3597 3598 common->rx_flow_id_base = -1; 3599 init_completion(&common->tdown_complete); 3600 common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; 3601 common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; 3602 common->pf_p0_rx_ptype_rrobin = true; 3603 common->default_vlan = 1; 3604 3605 common->ports = devm_kcalloc(dev, common->port_num, 3606 sizeof(*common->ports), 3607 GFP_KERNEL); 3608 if (!common->ports) 3609 return -ENOMEM; 3610 3611 clk = devm_clk_get(dev, "fck"); 3612 if (IS_ERR(clk)) 3613 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 3614 common->bus_freq = clk_get_rate(clk); 3615 3616 pm_runtime_enable(dev); 3617 ret = pm_runtime_resume_and_get(dev); 3618 if (ret < 0) { 3619 pm_runtime_disable(dev); 3620 return ret; 3621 } 3622 3623 node = of_get_child_by_name(dev->of_node, "mdio"); 3624 if (!node) { 3625 dev_warn(dev, "MDIO node not found\n"); 3626 } else if (of_device_is_available(node)) { 3627 struct platform_device *mdio_pdev; 3628 3629 mdio_pdev = of_platform_device_create(node, NULL, dev); 3630 if (!mdio_pdev) { 3631 ret = -ENODEV; 3632 goto err_pm_clear; 3633 } 3634 3635 common->mdio_dev = &mdio_pdev->dev; 3636 } 3637 of_node_put(node); 3638 3639 am65_cpsw_nuss_get_ver(common); 3640 3641 ret = am65_cpsw_nuss_init_host_p(common); 3642 if (ret) 3643 goto err_of_clear; 3644 3645 ret = am65_cpsw_nuss_init_slave_ports(common); 3646 if (ret) 3647 goto err_of_clear; 3648 3649 /* init common data */ 3650 ale_params.dev = dev; 3651 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 3652 ale_params.ale_ports = common->port_num + 1; 3653 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 3654 ale_params.dev_id = common->pdata.ale_dev_id; 3655 ale_params.bus_freq = common->bus_freq; 3656 3657 common->ale = cpsw_ale_create(&ale_params); 3658 if (IS_ERR(common->ale)) { 3659 dev_err(dev, "error initializing ale engine\n"); 3660 ret = PTR_ERR(common->ale); 3661 goto err_of_clear; 3662 } 3663 3664 ale_entries = common->ale->params.ale_entries; 3665 common->ale_context = devm_kzalloc(dev, 3666 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 3667 GFP_KERNEL); 3668 ret = am65_cpsw_init_cpts(common); 3669 if (ret) 3670 goto err_of_clear; 3671 3672 /* init ports */ 3673 for (i = 0; i < common->port_num; i++) 3674 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 3675 3676 dev_set_drvdata(dev, common); 3677 3678 common->is_emac_mode = true; 3679 3680 ret = am65_cpsw_nuss_init_ndevs(common); 3681 if (ret) 3682 goto err_ndevs_clear; 3683 3684 ret = am65_cpsw_nuss_register_ndevs(common); 3685 if (ret) 3686 goto err_ndevs_clear; 3687 3688 pm_runtime_put(dev); 3689 return 0; 3690 3691 err_ndevs_clear: 3692 am65_cpsw_nuss_cleanup_ndev(common); 3693 am65_cpsw_nuss_phylink_cleanup(common); 3694 am65_cpts_release(common->cpts); 3695 err_of_clear: 3696 if (common->mdio_dev) 3697 of_platform_device_destroy(common->mdio_dev, NULL); 3698 err_pm_clear: 3699 pm_runtime_put_sync(dev); 3700 pm_runtime_disable(dev); 3701 return ret; 3702 } 3703 3704 static void am65_cpsw_nuss_remove(struct platform_device *pdev) 3705 { 3706 struct device *dev = &pdev->dev; 3707 struct am65_cpsw_common *common; 3708 int ret; 3709 3710 common = dev_get_drvdata(dev); 3711 3712 ret = pm_runtime_resume_and_get(&pdev->dev); 3713 if (ret < 0) { 3714 /* Note, if this error path is taken, we're leaking some 3715 * resources. 3716 */ 3717 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", 3718 ERR_PTR(ret)); 3719 return; 3720 } 3721 3722 am65_cpsw_unregister_notifiers(common); 3723 3724 /* must unregister ndevs here because DD release_driver routine calls 3725 * dma_deconfigure(dev) before devres_release_all(dev) 3726 */ 3727 am65_cpsw_nuss_cleanup_ndev(common); 3728 am65_cpsw_unregister_devlink(common); 3729 am65_cpsw_nuss_remove_rx_chns(common); 3730 am65_cpsw_nuss_remove_tx_chns(common); 3731 am65_cpsw_nuss_phylink_cleanup(common); 3732 am65_cpts_release(common->cpts); 3733 am65_cpsw_disable_serdes_phy(common); 3734 3735 if (common->mdio_dev) 3736 of_platform_device_destroy(common->mdio_dev, NULL); 3737 3738 pm_runtime_put_sync(&pdev->dev); 3739 pm_runtime_disable(&pdev->dev); 3740 } 3741 3742 static int am65_cpsw_nuss_suspend(struct device *dev) 3743 { 3744 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3745 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3746 struct am65_cpsw_port *port; 3747 struct net_device *ndev; 3748 int i, ret; 3749 3750 cpsw_ale_dump(common->ale, common->ale_context); 3751 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3752 for (i = 0; i < common->port_num; i++) { 3753 port = &common->ports[i]; 3754 ndev = port->ndev; 3755 3756 if (!ndev) 3757 continue; 3758 3759 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3760 netif_device_detach(ndev); 3761 if (netif_running(ndev)) { 3762 rtnl_lock(); 3763 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3764 rtnl_unlock(); 3765 if (ret < 0) { 3766 netdev_err(ndev, "failed to stop: %d", ret); 3767 return ret; 3768 } 3769 } 3770 } 3771 3772 am65_cpts_suspend(common->cpts); 3773 3774 am65_cpsw_nuss_remove_rx_chns(common); 3775 am65_cpsw_nuss_remove_tx_chns(common); 3776 3777 return 0; 3778 } 3779 3780 static int am65_cpsw_nuss_resume(struct device *dev) 3781 { 3782 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3783 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3784 struct am65_cpsw_port *port; 3785 struct net_device *ndev; 3786 int i, ret; 3787 3788 ret = am65_cpsw_nuss_init_tx_chns(common); 3789 if (ret) 3790 return ret; 3791 ret = am65_cpsw_nuss_init_rx_chns(common); 3792 if (ret) { 3793 am65_cpsw_nuss_remove_tx_chns(common); 3794 return ret; 3795 } 3796 3797 /* If RX IRQ was disabled before suspend, keep it disabled */ 3798 for (i = 0; i < common->rx_ch_num_flows; i++) { 3799 if (common->rx_chns.flows[i].irq_disabled) 3800 disable_irq(common->rx_chns.flows[i].irq); 3801 } 3802 3803 am65_cpts_resume(common->cpts); 3804 3805 for (i = 0; i < common->port_num; i++) { 3806 port = &common->ports[i]; 3807 ndev = port->ndev; 3808 3809 if (!ndev) 3810 continue; 3811 3812 if (netif_running(ndev)) { 3813 rtnl_lock(); 3814 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3815 rtnl_unlock(); 3816 if (ret < 0) { 3817 netdev_err(ndev, "failed to start: %d", ret); 3818 return ret; 3819 } 3820 } 3821 3822 netif_device_attach(ndev); 3823 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3824 } 3825 3826 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3827 cpsw_ale_restore(common->ale, common->ale_context); 3828 3829 return 0; 3830 } 3831 3832 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3833 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3834 }; 3835 3836 static struct platform_driver am65_cpsw_nuss_driver = { 3837 .driver = { 3838 .name = AM65_CPSW_DRV_NAME, 3839 .of_match_table = am65_cpsw_nuss_of_mtable, 3840 .pm = &am65_cpsw_nuss_dev_pm_ops, 3841 }, 3842 .probe = am65_cpsw_nuss_probe, 3843 .remove = am65_cpsw_nuss_remove, 3844 }; 3845 3846 module_platform_driver(am65_cpsw_nuss_driver); 3847 3848 MODULE_LICENSE("GPL v2"); 3849 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3850 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3851