1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/bpf_trace.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/kmemleak.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/phylink.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/rtnetlink.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/sys_soc.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 #include <net/page_pool/helpers.h> 35 #include <net/dsa.h> 36 #include <net/switchdev.h> 37 38 #include "cpsw_ale.h" 39 #include "cpsw_sl.h" 40 #include "am65-cpsw-nuss.h" 41 #include "am65-cpsw-switchdev.h" 42 #include "k3-cppi-desc-pool.h" 43 #include "am65-cpts.h" 44 45 #define AM65_CPSW_SS_BASE 0x0 46 #define AM65_CPSW_SGMII_BASE 0x100 47 #define AM65_CPSW_XGMII_BASE 0x2100 48 #define AM65_CPSW_CPSW_NU_BASE 0x20000 49 #define AM65_CPSW_NU_PORTS_BASE 0x1000 50 #define AM65_CPSW_NU_FRAM_BASE 0x12000 51 #define AM65_CPSW_NU_STATS_BASE 0x1a000 52 #define AM65_CPSW_NU_ALE_BASE 0x1e000 53 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 54 55 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 56 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 57 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 58 59 #define AM65_CPSW_MAX_PORTS 8 60 61 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 62 #define AM65_CPSW_MAX_PACKET_SIZE 2024 63 64 #define AM65_CPSW_REG_CTL 0x004 65 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 66 #define AM65_CPSW_REG_PTYPE 0x018 67 68 #define AM65_CPSW_P0_REG_CTL 0x004 69 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 70 71 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 72 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 73 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 74 75 #define AM65_CPSW_PORTN_REG_CTL 0x004 76 #define AM65_CPSW_PORTN_REG_DSCP_MAP 0x120 77 #define AM65_CPSW_PORTN_REG_SA_L 0x308 78 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 79 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 80 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 81 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 82 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 83 84 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 85 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 86 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 87 88 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 89 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 90 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 91 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 92 93 /* AM65_CPSW_P0_REG_CTL */ 94 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 95 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 96 97 /* AM65_CPSW_PORT_REG_PRI_CTL */ 98 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 99 100 /* AM65_CPSW_PN_REG_CTL */ 101 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN BIT(1) 102 #define AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN BIT(2) 103 104 /* AM65_CPSW_PN_TS_CTL register fields */ 105 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 106 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 107 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 108 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 109 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 110 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 111 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 112 113 #define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0) 114 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1) 115 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2) 116 #define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3) 117 #define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9) 118 119 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 120 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 121 122 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 123 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 124 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 125 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 126 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 127 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 128 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 129 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 130 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 131 132 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 133 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 134 135 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 136 137 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 138 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 139 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 140 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 141 142 #define AM65_CPSW_TS_RX_ANX_ALL_EN \ 143 (AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \ 144 AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \ 145 AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) 146 147 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 148 /* Number of TX/RX descriptors per channel/flow */ 149 #define AM65_CPSW_MAX_TX_DESC 500 150 #define AM65_CPSW_MAX_RX_DESC 500 151 152 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 153 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 154 155 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 156 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 157 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 158 159 #define AM65_CPSW_DEFAULT_TX_CHNS 8 160 #define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 161 162 /* CPPI streaming packet interface */ 163 #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF 164 #define AM65_CPSW_CPPI_TX_PKT_TYPE 0x7 165 166 /* XDP */ 167 #define AM65_CPSW_XDP_TX BIT(2) 168 #define AM65_CPSW_XDP_CONSUMED BIT(1) 169 #define AM65_CPSW_XDP_REDIRECT BIT(0) 170 #define AM65_CPSW_XDP_PASS 0 171 172 /* Include headroom compatible with both skb and xdpf */ 173 #define AM65_CPSW_HEADROOM_NA (max(NET_SKB_PAD, XDP_PACKET_HEADROOM) + NET_IP_ALIGN) 174 #define AM65_CPSW_HEADROOM ALIGN(AM65_CPSW_HEADROOM_NA, sizeof(long)) 175 176 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 177 const u8 *dev_addr) 178 { 179 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 180 (dev_addr[2] << 16) | (dev_addr[3] << 24); 181 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 182 183 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 184 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 185 } 186 187 #define AM65_CPSW_DSCP_MAX GENMASK(5, 0) 188 #define AM65_CPSW_PRI_MAX GENMASK(2, 0) 189 #define AM65_CPSW_DSCP_PRI_PER_REG 8 190 #define AM65_CPSW_DSCP_PRI_SIZE 4 /* in bits */ 191 static int am65_cpsw_port_set_dscp_map(struct am65_cpsw_port *slave, u8 dscp, u8 pri) 192 { 193 int reg_ofs; 194 int bit_ofs; 195 u32 val; 196 197 if (dscp > AM65_CPSW_DSCP_MAX) 198 return -EINVAL; 199 200 if (pri > AM65_CPSW_PRI_MAX) 201 return -EINVAL; 202 203 /* 32-bit register offset to this dscp */ 204 reg_ofs = (dscp / AM65_CPSW_DSCP_PRI_PER_REG) * 4; 205 /* bit field offset to this dscp */ 206 bit_ofs = AM65_CPSW_DSCP_PRI_SIZE * (dscp % AM65_CPSW_DSCP_PRI_PER_REG); 207 208 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 209 val &= ~(AM65_CPSW_PRI_MAX << bit_ofs); /* clear */ 210 val |= pri << bit_ofs; /* set */ 211 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_DSCP_MAP + reg_ofs); 212 213 return 0; 214 } 215 216 static void am65_cpsw_port_enable_dscp_map(struct am65_cpsw_port *slave) 217 { 218 int dscp, pri; 219 u32 val; 220 221 /* Default DSCP to User Priority mapping as per: 222 * https://datatracker.ietf.org/doc/html/rfc8325#section-4.3 223 * and 224 * https://datatracker.ietf.org/doc/html/rfc8622#section-11 225 */ 226 for (dscp = 0; dscp <= AM65_CPSW_DSCP_MAX; dscp++) { 227 switch (dscp) { 228 case 56: /* CS7 */ 229 case 48: /* CS6 */ 230 pri = 7; 231 break; 232 case 46: /* EF */ 233 case 44: /* VA */ 234 pri = 6; 235 break; 236 case 40: /* CS5 */ 237 pri = 5; 238 break; 239 case 34: /* AF41 */ 240 case 36: /* AF42 */ 241 case 38: /* AF43 */ 242 case 32: /* CS4 */ 243 case 26: /* AF31 */ 244 case 28: /* AF32 */ 245 case 30: /* AF33 */ 246 case 24: /* CS3 */ 247 pri = 4; 248 break; 249 case 18: /* AF21 */ 250 case 20: /* AF22 */ 251 case 22: /* AF23 */ 252 pri = 3; 253 break; 254 case 16: /* CS2 */ 255 case 10: /* AF11 */ 256 case 12: /* AF12 */ 257 case 14: /* AF13 */ 258 case 0: /* DF */ 259 pri = 0; 260 break; 261 case 8: /* CS1 */ 262 case 1: /* LE */ 263 pri = 1; 264 break; 265 default: 266 pri = 0; 267 break; 268 } 269 270 am65_cpsw_port_set_dscp_map(slave, dscp, pri); 271 } 272 273 /* enable port IPV4 and IPV6 DSCP for this port */ 274 val = readl(slave->port_base + AM65_CPSW_PORTN_REG_CTL); 275 val |= AM65_CPSW_PN_REG_CTL_DSCP_IPV4_EN | 276 AM65_CPSW_PN_REG_CTL_DSCP_IPV6_EN; 277 writel(val, slave->port_base + AM65_CPSW_PORTN_REG_CTL); 278 } 279 280 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 281 { 282 cpsw_sl_reset(port->slave.mac_sl, 100); 283 /* Max length register has to be restored after MAC SL reset */ 284 writel(AM65_CPSW_MAX_PACKET_SIZE, 285 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 286 } 287 288 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 289 { 290 common->nuss_ver = readl(common->ss_base); 291 common->cpsw_ver = readl(common->cpsw_base); 292 dev_info(common->dev, 293 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 294 common->nuss_ver, 295 common->cpsw_ver, 296 common->port_num + 1, 297 common->pdata.quirks); 298 } 299 300 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 301 __be16 proto, u16 vid) 302 { 303 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 304 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 305 u32 port_mask, unreg_mcast = 0; 306 int ret; 307 308 if (!common->is_emac_mode) 309 return 0; 310 311 if (!netif_running(ndev) || !vid) 312 return 0; 313 314 ret = pm_runtime_resume_and_get(common->dev); 315 if (ret < 0) 316 return ret; 317 318 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 319 if (!vid) 320 unreg_mcast = port_mask; 321 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 322 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 323 unreg_mcast, port_mask, 0); 324 325 pm_runtime_put(common->dev); 326 return ret; 327 } 328 329 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 330 __be16 proto, u16 vid) 331 { 332 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 333 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 334 int ret; 335 336 if (!common->is_emac_mode) 337 return 0; 338 339 if (!netif_running(ndev) || !vid) 340 return 0; 341 342 ret = pm_runtime_resume_and_get(common->dev); 343 if (ret < 0) 344 return ret; 345 346 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 347 ret = cpsw_ale_del_vlan(common->ale, vid, 348 BIT(port->port_id) | ALE_PORT_HOST); 349 350 pm_runtime_put(common->dev); 351 return ret; 352 } 353 354 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 355 bool promisc) 356 { 357 struct am65_cpsw_common *common = port->common; 358 359 if (promisc && !common->is_emac_mode) { 360 dev_dbg(common->dev, "promisc mode requested in switch mode"); 361 return; 362 } 363 364 if (promisc) { 365 /* Enable promiscuous mode */ 366 cpsw_ale_control_set(common->ale, port->port_id, 367 ALE_PORT_MACONLY_CAF, 1); 368 dev_dbg(common->dev, "promisc enabled\n"); 369 } else { 370 /* Disable promiscuous mode */ 371 cpsw_ale_control_set(common->ale, port->port_id, 372 ALE_PORT_MACONLY_CAF, 0); 373 dev_dbg(common->dev, "promisc disabled\n"); 374 } 375 } 376 377 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 378 { 379 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 380 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 381 u32 port_mask; 382 bool promisc; 383 384 promisc = !!(ndev->flags & IFF_PROMISC); 385 am65_cpsw_slave_set_promisc(port, promisc); 386 387 if (promisc) 388 return; 389 390 /* Restore allmulti on vlans if necessary */ 391 cpsw_ale_set_allmulti(common->ale, 392 ndev->flags & IFF_ALLMULTI, port->port_id); 393 394 port_mask = ALE_PORT_HOST; 395 /* Clear all mcast from ALE */ 396 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 397 398 if (!netdev_mc_empty(ndev)) { 399 struct netdev_hw_addr *ha; 400 401 /* program multicast address list into ALE register */ 402 netdev_for_each_mc_addr(ha, ndev) { 403 cpsw_ale_add_mcast(common->ale, ha->addr, 404 port_mask, 0, 0, 0); 405 } 406 } 407 } 408 409 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 410 unsigned int txqueue) 411 { 412 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 413 struct am65_cpsw_tx_chn *tx_chn; 414 struct netdev_queue *netif_txq; 415 unsigned long trans_start; 416 417 netif_txq = netdev_get_tx_queue(ndev, txqueue); 418 tx_chn = &common->tx_chns[txqueue]; 419 trans_start = READ_ONCE(netif_txq->trans_start); 420 421 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 422 txqueue, 423 netif_tx_queue_stopped(netif_txq), 424 jiffies_to_msecs(jiffies - trans_start), 425 netdev_queue_dql_avail(netif_txq), 426 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 427 428 if (netif_tx_queue_stopped(netif_txq)) { 429 /* try recover if stopped by us */ 430 txq_trans_update(ndev, netif_txq); 431 netif_tx_wake_queue(netif_txq); 432 } 433 } 434 435 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 436 struct page *page, u32 flow_idx) 437 { 438 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 439 struct cppi5_host_desc_t *desc_rx; 440 struct device *dev = common->dev; 441 struct am65_cpsw_swdata *swdata; 442 dma_addr_t desc_dma; 443 dma_addr_t buf_dma; 444 445 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 446 if (!desc_rx) { 447 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 448 return -ENOMEM; 449 } 450 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 451 452 buf_dma = dma_map_single(rx_chn->dma_dev, 453 page_address(page) + AM65_CPSW_HEADROOM, 454 AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); 455 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 456 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 457 dev_err(dev, "Failed to map rx buffer\n"); 458 return -EINVAL; 459 } 460 461 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 462 AM65_CPSW_NAV_PS_DATA_SIZE); 463 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 464 cppi5_hdesc_attach_buf(desc_rx, buf_dma, AM65_CPSW_MAX_PACKET_SIZE, 465 buf_dma, AM65_CPSW_MAX_PACKET_SIZE); 466 swdata = cppi5_hdesc_get_swdata(desc_rx); 467 swdata->page = page; 468 swdata->flow_id = flow_idx; 469 470 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, 471 desc_rx, desc_dma); 472 } 473 474 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 475 { 476 struct am65_cpsw_host *host_p = am65_common_get_host(common); 477 u32 val, pri_map; 478 479 /* P0 set Receive Priority Type */ 480 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 481 482 if (common->pf_p0_rx_ptype_rrobin) { 483 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 484 /* Enet Ports fifos works in fixed priority mode only, so 485 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 486 */ 487 pri_map = 0x0; 488 } else { 489 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 490 /* restore P0_Rx_Pri_Map */ 491 pri_map = 0x76543210; 492 } 493 494 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 495 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 496 } 497 498 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 499 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 500 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 501 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 502 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 503 struct page *page, 504 bool allow_direct); 505 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 506 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 507 508 static void am65_cpsw_destroy_rxq(struct am65_cpsw_common *common, int id) 509 { 510 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 511 struct am65_cpsw_rx_flow *flow; 512 struct xdp_rxq_info *rxq; 513 int port; 514 515 flow = &rx_chn->flows[id]; 516 napi_disable(&flow->napi_rx); 517 hrtimer_cancel(&flow->rx_hrtimer); 518 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, id, rx_chn, 519 am65_cpsw_nuss_rx_cleanup); 520 521 for (port = 0; port < common->port_num; port++) { 522 if (!common->ports[port].ndev) 523 continue; 524 525 rxq = &common->ports[port].xdp_rxq[id]; 526 527 if (xdp_rxq_info_is_reg(rxq)) 528 xdp_rxq_info_unreg(rxq); 529 } 530 531 if (flow->page_pool) { 532 page_pool_destroy(flow->page_pool); 533 flow->page_pool = NULL; 534 } 535 } 536 537 static void am65_cpsw_destroy_rxqs(struct am65_cpsw_common *common) 538 { 539 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 540 int id; 541 542 reinit_completion(&common->tdown_complete); 543 k3_udma_glue_tdown_rx_chn(rx_chn->rx_chn, true); 544 545 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 546 id = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 547 if (!id) 548 dev_err(common->dev, "rx teardown timeout\n"); 549 } 550 551 for (id = common->rx_ch_num_flows - 1; id >= 0; id--) 552 am65_cpsw_destroy_rxq(common, id); 553 554 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 555 } 556 557 static int am65_cpsw_create_rxq(struct am65_cpsw_common *common, int id) 558 { 559 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 560 struct page_pool_params pp_params = { 561 .flags = PP_FLAG_DMA_MAP, 562 .order = 0, 563 .pool_size = AM65_CPSW_MAX_RX_DESC, 564 .nid = dev_to_node(common->dev), 565 .dev = common->dev, 566 .dma_dir = DMA_BIDIRECTIONAL, 567 /* .napi set dynamically */ 568 }; 569 struct am65_cpsw_rx_flow *flow; 570 struct xdp_rxq_info *rxq; 571 struct page_pool *pool; 572 struct page *page; 573 int port, ret, i; 574 575 flow = &rx_chn->flows[id]; 576 pp_params.napi = &flow->napi_rx; 577 pool = page_pool_create(&pp_params); 578 if (IS_ERR(pool)) { 579 ret = PTR_ERR(pool); 580 return ret; 581 } 582 583 flow->page_pool = pool; 584 585 /* using same page pool is allowed as no running rx handlers 586 * simultaneously for both ndevs 587 */ 588 for (port = 0; port < common->port_num; port++) { 589 if (!common->ports[port].ndev) 590 /* FIXME should we BUG here? */ 591 continue; 592 593 rxq = &common->ports[port].xdp_rxq[id]; 594 ret = xdp_rxq_info_reg(rxq, common->ports[port].ndev, 595 id, flow->napi_rx.napi_id); 596 if (ret) 597 goto err; 598 599 ret = xdp_rxq_info_reg_mem_model(rxq, 600 MEM_TYPE_PAGE_POOL, 601 pool); 602 if (ret) 603 goto err; 604 } 605 606 for (i = 0; i < AM65_CPSW_MAX_RX_DESC; i++) { 607 page = page_pool_dev_alloc_pages(flow->page_pool); 608 if (!page) { 609 dev_err(common->dev, "cannot allocate page in flow %d\n", 610 id); 611 ret = -ENOMEM; 612 goto err; 613 } 614 615 ret = am65_cpsw_nuss_rx_push(common, page, id); 616 if (ret < 0) { 617 dev_err(common->dev, 618 "cannot submit page to rx channel flow %d, error %d\n", 619 id, ret); 620 am65_cpsw_put_page(flow, page, false); 621 goto err; 622 } 623 } 624 625 napi_enable(&flow->napi_rx); 626 return 0; 627 628 err: 629 am65_cpsw_destroy_rxq(common, id); 630 return ret; 631 } 632 633 static int am65_cpsw_create_rxqs(struct am65_cpsw_common *common) 634 { 635 int id, ret; 636 637 for (id = 0; id < common->rx_ch_num_flows; id++) { 638 ret = am65_cpsw_create_rxq(common, id); 639 if (ret) { 640 dev_err(common->dev, "couldn't create rxq %d: %d\n", 641 id, ret); 642 goto err; 643 } 644 } 645 646 ret = k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 647 if (ret) { 648 dev_err(common->dev, "couldn't enable rx chn: %d\n", ret); 649 goto err; 650 } 651 652 return 0; 653 654 err: 655 for (--id; id >= 0; id--) 656 am65_cpsw_destroy_rxq(common, id); 657 658 return ret; 659 } 660 661 static void am65_cpsw_destroy_txq(struct am65_cpsw_common *common, int id) 662 { 663 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[id]; 664 665 napi_disable(&tx_chn->napi_tx); 666 hrtimer_cancel(&tx_chn->tx_hrtimer); 667 k3_udma_glue_reset_tx_chn(tx_chn->tx_chn, tx_chn, 668 am65_cpsw_nuss_tx_cleanup); 669 k3_udma_glue_disable_tx_chn(tx_chn->tx_chn); 670 } 671 672 static void am65_cpsw_destroy_txqs(struct am65_cpsw_common *common) 673 { 674 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 675 int id; 676 677 /* shutdown tx channels */ 678 atomic_set(&common->tdown_cnt, common->tx_ch_num); 679 /* ensure new tdown_cnt value is visible */ 680 smp_mb__after_atomic(); 681 reinit_completion(&common->tdown_complete); 682 683 for (id = 0; id < common->tx_ch_num; id++) 684 k3_udma_glue_tdown_tx_chn(tx_chn[id].tx_chn, false); 685 686 id = wait_for_completion_timeout(&common->tdown_complete, 687 msecs_to_jiffies(1000)); 688 if (!id) 689 dev_err(common->dev, "tx teardown timeout\n"); 690 691 for (id = common->tx_ch_num - 1; id >= 0; id--) 692 am65_cpsw_destroy_txq(common, id); 693 } 694 695 static int am65_cpsw_create_txq(struct am65_cpsw_common *common, int id) 696 { 697 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[id]; 698 int ret; 699 700 ret = k3_udma_glue_enable_tx_chn(tx_chn->tx_chn); 701 if (ret) 702 return ret; 703 704 napi_enable(&tx_chn->napi_tx); 705 706 return 0; 707 } 708 709 static int am65_cpsw_create_txqs(struct am65_cpsw_common *common) 710 { 711 int id, ret; 712 713 for (id = 0; id < common->tx_ch_num; id++) { 714 ret = am65_cpsw_create_txq(common, id); 715 if (ret) { 716 dev_err(common->dev, "couldn't create txq %d: %d\n", 717 id, ret); 718 goto err; 719 } 720 } 721 722 return 0; 723 724 err: 725 for (--id; id >= 0; id--) 726 am65_cpsw_destroy_txq(common, id); 727 728 return ret; 729 } 730 731 static int am65_cpsw_nuss_desc_idx(struct k3_cppi_desc_pool *desc_pool, 732 void *desc, 733 unsigned char dsize_log2) 734 { 735 void *pool_addr = k3_cppi_desc_pool_cpuaddr(desc_pool); 736 737 return (desc - pool_addr) >> dsize_log2; 738 } 739 740 static void am65_cpsw_nuss_set_buf_type(struct am65_cpsw_tx_chn *tx_chn, 741 struct cppi5_host_desc_t *desc, 742 enum am65_cpsw_tx_buf_type buf_type) 743 { 744 int desc_idx; 745 746 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc, 747 tx_chn->dsize_log2); 748 k3_cppi_desc_pool_desc_info_set(tx_chn->desc_pool, desc_idx, 749 (void *)buf_type); 750 } 751 752 static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_chn *tx_chn, 753 dma_addr_t desc_dma) 754 { 755 struct cppi5_host_desc_t *desc_tx; 756 int desc_idx; 757 758 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 759 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc_tx, 760 tx_chn->dsize_log2); 761 762 return (enum am65_cpsw_tx_buf_type)k3_cppi_desc_pool_desc_info(tx_chn->desc_pool, 763 desc_idx); 764 } 765 766 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 767 struct page *page, 768 bool allow_direct) 769 { 770 page_pool_put_full_page(flow->page_pool, page, allow_direct); 771 } 772 773 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 774 { 775 struct am65_cpsw_rx_chn *rx_chn = data; 776 struct cppi5_host_desc_t *desc_rx; 777 struct am65_cpsw_swdata *swdata; 778 dma_addr_t buf_dma; 779 struct page *page; 780 u32 buf_dma_len; 781 u32 flow_id; 782 783 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 784 swdata = cppi5_hdesc_get_swdata(desc_rx); 785 page = swdata->page; 786 flow_id = swdata->flow_id; 787 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 788 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 789 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 790 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 791 am65_cpsw_put_page(&rx_chn->flows[flow_id], page, false); 792 } 793 794 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 795 struct cppi5_host_desc_t *desc) 796 { 797 struct cppi5_host_desc_t *first_desc, *next_desc; 798 dma_addr_t buf_dma, next_desc_dma; 799 u32 buf_dma_len; 800 801 first_desc = desc; 802 next_desc = first_desc; 803 804 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 805 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 806 807 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 808 809 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 810 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 811 while (next_desc_dma) { 812 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 813 next_desc_dma); 814 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 815 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 816 817 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 818 DMA_TO_DEVICE); 819 820 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 821 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 822 823 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 824 } 825 826 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 827 } 828 829 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 830 { 831 struct am65_cpsw_tx_chn *tx_chn = data; 832 enum am65_cpsw_tx_buf_type buf_type; 833 struct am65_cpsw_tx_swdata *swdata; 834 struct cppi5_host_desc_t *desc_tx; 835 struct xdp_frame *xdpf; 836 struct sk_buff *skb; 837 838 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 839 swdata = cppi5_hdesc_get_swdata(desc_tx); 840 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 841 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 842 skb = swdata->skb; 843 dev_kfree_skb_any(skb); 844 } else { 845 xdpf = swdata->xdpf; 846 xdp_return_frame(xdpf); 847 } 848 849 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 850 } 851 852 static struct sk_buff *am65_cpsw_build_skb(void *page_addr, 853 struct net_device *ndev, 854 unsigned int len, 855 unsigned int headroom) 856 { 857 struct sk_buff *skb; 858 859 skb = build_skb(page_addr, len); 860 if (unlikely(!skb)) 861 return NULL; 862 863 skb_reserve(skb, headroom); 864 skb->dev = ndev; 865 866 return skb; 867 } 868 869 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 870 { 871 struct am65_cpsw_host *host_p = am65_common_get_host(common); 872 u32 val, port_mask; 873 int port_idx, ret; 874 875 if (common->usage_count) 876 return 0; 877 878 /* Control register */ 879 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 880 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 881 common->cpsw_base + AM65_CPSW_REG_CTL); 882 /* Max length register */ 883 writel(AM65_CPSW_MAX_PACKET_SIZE, 884 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 885 /* set base flow_id */ 886 writel(common->rx_flow_id_base, 887 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 888 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 889 host_p->port_base + AM65_CPSW_P0_REG_CTL); 890 891 am65_cpsw_nuss_set_p0_ptype(common); 892 893 /* enable statistic */ 894 val = BIT(HOST_PORT_NUM); 895 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 896 struct am65_cpsw_port *port = &common->ports[port_idx]; 897 898 if (!port->disabled) 899 val |= BIT(port->port_id); 900 } 901 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 902 903 /* disable priority elevation */ 904 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 905 906 cpsw_ale_start(common->ale); 907 908 /* limit to one RX flow only */ 909 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 910 ALE_DEFAULT_THREAD_ID, 0); 911 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 912 ALE_DEFAULT_THREAD_ENABLE, 1); 913 /* switch to vlan aware mode */ 914 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 915 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 916 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 917 918 /* default vlan cfg: create mask based on enabled ports */ 919 port_mask = GENMASK(common->port_num, 0) & 920 ~common->disabled_ports_mask; 921 922 cpsw_ale_add_vlan(common->ale, 0, port_mask, 923 port_mask, port_mask, 924 port_mask & ~ALE_PORT_HOST); 925 926 if (common->is_emac_mode) 927 am65_cpsw_init_host_port_emac(common); 928 else 929 am65_cpsw_init_host_port_switch(common); 930 931 am65_cpsw_qos_tx_p0_rate_init(common); 932 933 ret = am65_cpsw_create_rxqs(common); 934 if (ret) 935 return ret; 936 937 ret = am65_cpsw_create_txqs(common); 938 if (ret) 939 goto cleanup_rx; 940 941 dev_dbg(common->dev, "cpsw_nuss started\n"); 942 return 0; 943 944 cleanup_rx: 945 am65_cpsw_destroy_rxqs(common); 946 947 return ret; 948 } 949 950 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 951 { 952 if (common->usage_count != 1) 953 return 0; 954 955 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 956 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 957 958 am65_cpsw_destroy_txqs(common); 959 am65_cpsw_destroy_rxqs(common); 960 cpsw_ale_stop(common->ale); 961 962 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 963 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 964 965 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 966 return 0; 967 } 968 969 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 970 { 971 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 972 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 973 int ret; 974 975 phylink_stop(port->slave.phylink); 976 977 netif_tx_stop_all_queues(ndev); 978 979 phylink_disconnect_phy(port->slave.phylink); 980 981 ret = am65_cpsw_nuss_common_stop(common); 982 if (ret) 983 return ret; 984 985 common->usage_count--; 986 pm_runtime_put(common->dev); 987 return 0; 988 } 989 990 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 991 { 992 struct am65_cpsw_port *port = arg; 993 994 if (!vdev) 995 return 0; 996 997 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 998 } 999 1000 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 1001 { 1002 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1003 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1004 int ret, i; 1005 u32 reg; 1006 1007 ret = pm_runtime_resume_and_get(common->dev); 1008 if (ret < 0) 1009 return ret; 1010 1011 /* Idle MAC port */ 1012 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1013 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1014 cpsw_sl_ctl_reset(port->slave.mac_sl); 1015 1016 /* soft reset MAC */ 1017 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 1018 mdelay(1); 1019 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 1020 if (reg) { 1021 dev_err(common->dev, "soft RESET didn't complete\n"); 1022 ret = -ETIMEDOUT; 1023 goto runtime_put; 1024 } 1025 1026 /* Notify the stack of the actual queue counts. */ 1027 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 1028 if (ret) { 1029 dev_err(common->dev, "cannot set real number of tx queues\n"); 1030 goto runtime_put; 1031 } 1032 1033 ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); 1034 if (ret) { 1035 dev_err(common->dev, "cannot set real number of rx queues\n"); 1036 goto runtime_put; 1037 } 1038 1039 for (i = 0; i < common->tx_ch_num; i++) { 1040 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 1041 1042 netdev_tx_reset_queue(txq); 1043 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 1044 } 1045 1046 ret = am65_cpsw_nuss_common_open(common); 1047 if (ret) 1048 goto runtime_put; 1049 1050 common->usage_count++; 1051 1052 /* VLAN aware CPSW mode is incompatible with some DSA tagging schemes. 1053 * Therefore disable VLAN_AWARE mode if any of the ports is a DSA Port. 1054 */ 1055 if (netdev_uses_dsa(ndev)) { 1056 reg = readl(common->cpsw_base + AM65_CPSW_REG_CTL); 1057 reg &= ~AM65_CPSW_CTL_VLAN_AWARE; 1058 writel(reg, common->cpsw_base + AM65_CPSW_REG_CTL); 1059 } 1060 1061 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 1062 am65_cpsw_port_enable_dscp_map(port); 1063 1064 if (common->is_emac_mode) 1065 am65_cpsw_init_port_emac_ale(port); 1066 else 1067 am65_cpsw_init_port_switch_ale(port); 1068 1069 /* mac_sl should be configured via phy-link interface */ 1070 am65_cpsw_sl_ctl_reset(port); 1071 1072 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.port_np, 0); 1073 if (ret) 1074 goto error_cleanup; 1075 1076 /* restore vlan configurations */ 1077 vlan_for_each(ndev, cpsw_restore_vlans, port); 1078 1079 phylink_start(port->slave.phylink); 1080 1081 return 0; 1082 1083 error_cleanup: 1084 am65_cpsw_nuss_ndo_slave_stop(ndev); 1085 return ret; 1086 1087 runtime_put: 1088 pm_runtime_put(common->dev); 1089 return ret; 1090 } 1091 1092 static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, 1093 struct am65_cpsw_tx_chn *tx_chn, 1094 struct xdp_frame *xdpf, 1095 enum am65_cpsw_tx_buf_type buf_type) 1096 { 1097 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1098 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1099 struct cppi5_host_desc_t *host_desc; 1100 struct am65_cpsw_tx_swdata *swdata; 1101 struct netdev_queue *netif_txq; 1102 dma_addr_t dma_desc, dma_buf; 1103 u32 pkt_len = xdpf->len; 1104 int ret; 1105 1106 host_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1107 if (unlikely(!host_desc)) { 1108 ndev->stats.tx_dropped++; 1109 return AM65_CPSW_XDP_CONSUMED; /* drop */ 1110 } 1111 1112 am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, buf_type); 1113 1114 dma_buf = dma_map_single(tx_chn->dma_dev, xdpf->data, 1115 pkt_len, DMA_TO_DEVICE); 1116 if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { 1117 ndev->stats.tx_dropped++; 1118 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1119 goto pool_free; 1120 } 1121 1122 cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1123 AM65_CPSW_NAV_PS_DATA_SIZE); 1124 cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1125 cppi5_hdesc_set_pktlen(host_desc, pkt_len); 1126 cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1127 cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); 1128 1129 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); 1130 cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); 1131 1132 swdata = cppi5_hdesc_get_swdata(host_desc); 1133 swdata->ndev = ndev; 1134 swdata->xdpf = xdpf; 1135 1136 /* Report BQL before sending the packet */ 1137 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1138 netdev_tx_sent_queue(netif_txq, pkt_len); 1139 1140 dma_desc = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); 1141 if (AM65_CPSW_IS_CPSW2G(common)) { 1142 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1143 dma_desc); 1144 } else { 1145 spin_lock_bh(&tx_chn->lock); 1146 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1147 dma_desc); 1148 spin_unlock_bh(&tx_chn->lock); 1149 } 1150 if (ret) { 1151 /* Inform BQL */ 1152 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1153 ndev->stats.tx_errors++; 1154 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1155 goto dma_unmap; 1156 } 1157 1158 return 0; 1159 1160 dma_unmap: 1161 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); 1162 dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); 1163 pool_free: 1164 k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); 1165 return ret; 1166 } 1167 1168 static int am65_cpsw_run_xdp(struct am65_cpsw_rx_flow *flow, 1169 struct am65_cpsw_port *port, 1170 struct xdp_buff *xdp, int *len) 1171 { 1172 struct am65_cpsw_common *common = flow->common; 1173 struct net_device *ndev = port->ndev; 1174 int ret = AM65_CPSW_XDP_CONSUMED; 1175 struct am65_cpsw_tx_chn *tx_chn; 1176 struct netdev_queue *netif_txq; 1177 int cpu = smp_processor_id(); 1178 struct xdp_frame *xdpf; 1179 struct bpf_prog *prog; 1180 int pkt_len; 1181 u32 act; 1182 int err; 1183 1184 pkt_len = *len; 1185 prog = READ_ONCE(port->xdp_prog); 1186 if (!prog) 1187 return AM65_CPSW_XDP_PASS; 1188 1189 act = bpf_prog_run_xdp(prog, xdp); 1190 /* XDP prog might have changed packet data and boundaries */ 1191 *len = xdp->data_end - xdp->data; 1192 1193 switch (act) { 1194 case XDP_PASS: 1195 return AM65_CPSW_XDP_PASS; 1196 case XDP_TX: 1197 tx_chn = &common->tx_chns[cpu % AM65_CPSW_MAX_QUEUES]; 1198 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1199 1200 xdpf = xdp_convert_buff_to_frame(xdp); 1201 if (unlikely(!xdpf)) { 1202 ndev->stats.tx_dropped++; 1203 goto drop; 1204 } 1205 1206 __netif_tx_lock(netif_txq, cpu); 1207 err = am65_cpsw_xdp_tx_frame(ndev, tx_chn, xdpf, 1208 AM65_CPSW_TX_BUF_TYPE_XDP_TX); 1209 __netif_tx_unlock(netif_txq); 1210 if (err) 1211 goto drop; 1212 1213 dev_sw_netstats_rx_add(ndev, pkt_len); 1214 return AM65_CPSW_XDP_TX; 1215 case XDP_REDIRECT: 1216 if (unlikely(xdp_do_redirect(ndev, xdp, prog))) 1217 goto drop; 1218 1219 dev_sw_netstats_rx_add(ndev, pkt_len); 1220 return AM65_CPSW_XDP_REDIRECT; 1221 default: 1222 bpf_warn_invalid_xdp_action(ndev, prog, act); 1223 fallthrough; 1224 case XDP_ABORTED: 1225 drop: 1226 trace_xdp_exception(ndev, prog, act); 1227 fallthrough; 1228 case XDP_DROP: 1229 ndev->stats.rx_dropped++; 1230 } 1231 1232 return ret; 1233 } 1234 1235 /* RX psdata[2] word format - checksum information */ 1236 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 1237 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 1238 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 1239 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 1240 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 1241 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 1242 1243 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 1244 { 1245 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 1246 * csum information provides in psdata[2] word: 1247 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 1248 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 1249 * bits - indicates IPv4/IPv6 packet 1250 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 1251 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 1252 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 1253 */ 1254 skb_checksum_none_assert(skb); 1255 1256 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 1257 return; 1258 1259 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 1260 AM65_CPSW_RX_PSD_IPV4_VALID)) && 1261 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 1262 /* csum for fragmented packets is unsupported */ 1263 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 1264 skb->ip_summed = CHECKSUM_UNNECESSARY; 1265 } 1266 } 1267 1268 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow, 1269 int *xdp_state) 1270 { 1271 struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; 1272 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 1273 struct am65_cpsw_common *common = flow->common; 1274 struct am65_cpsw_ndev_priv *ndev_priv; 1275 struct cppi5_host_desc_t *desc_rx; 1276 struct device *dev = common->dev; 1277 struct am65_cpsw_swdata *swdata; 1278 struct page *page, *new_page; 1279 dma_addr_t desc_dma, buf_dma; 1280 struct am65_cpsw_port *port; 1281 struct net_device *ndev; 1282 u32 flow_idx = flow->id; 1283 struct sk_buff *skb; 1284 struct xdp_buff xdp; 1285 int headroom, ret; 1286 void *page_addr; 1287 u32 *psdata; 1288 1289 *xdp_state = AM65_CPSW_XDP_PASS; 1290 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 1291 if (ret) { 1292 if (ret != -ENODATA) 1293 dev_err(dev, "RX: pop chn fail %d\n", ret); 1294 return ret; 1295 } 1296 1297 if (cppi5_desc_is_tdcm(desc_dma)) { 1298 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 1299 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 1300 complete(&common->tdown_complete); 1301 return 0; 1302 } 1303 1304 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 1305 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 1306 __func__, flow_idx, &desc_dma); 1307 1308 swdata = cppi5_hdesc_get_swdata(desc_rx); 1309 page = swdata->page; 1310 page_addr = page_address(page); 1311 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 1312 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 1313 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 1314 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 1315 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 1316 port = am65_common_get_port(common, port_id); 1317 ndev = port->ndev; 1318 psdata = cppi5_hdesc_get_psdata(desc_rx); 1319 csum_info = psdata[2]; 1320 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 1321 1322 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 1323 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 1324 1325 if (port->xdp_prog) { 1326 xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq[flow->id]); 1327 xdp_prepare_buff(&xdp, page_addr, AM65_CPSW_HEADROOM, 1328 pkt_len, false); 1329 *xdp_state = am65_cpsw_run_xdp(flow, port, &xdp, &pkt_len); 1330 if (*xdp_state == AM65_CPSW_XDP_CONSUMED) { 1331 page = virt_to_head_page(xdp.data); 1332 am65_cpsw_put_page(flow, page, true); 1333 goto allocate; 1334 } 1335 1336 if (*xdp_state != AM65_CPSW_XDP_PASS) 1337 goto allocate; 1338 1339 headroom = xdp.data - xdp.data_hard_start; 1340 } else { 1341 headroom = AM65_CPSW_HEADROOM; 1342 } 1343 1344 skb = am65_cpsw_build_skb(page_addr, ndev, 1345 PAGE_SIZE, headroom); 1346 if (unlikely(!skb)) { 1347 new_page = page; 1348 goto requeue; 1349 } 1350 1351 ndev_priv = netdev_priv(ndev); 1352 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 1353 skb_put(skb, pkt_len); 1354 if (port->rx_ts_enabled) 1355 am65_cpts_rx_timestamp(common->cpts, skb); 1356 skb_mark_for_recycle(skb); 1357 skb->protocol = eth_type_trans(skb, ndev); 1358 am65_cpsw_nuss_rx_csum(skb, csum_info); 1359 napi_gro_receive(&flow->napi_rx, skb); 1360 1361 dev_sw_netstats_rx_add(ndev, pkt_len); 1362 1363 allocate: 1364 new_page = page_pool_dev_alloc_pages(flow->page_pool); 1365 if (unlikely(!new_page)) { 1366 dev_err(dev, "page alloc failed\n"); 1367 return -ENOMEM; 1368 } 1369 1370 if (netif_dormant(ndev)) { 1371 am65_cpsw_put_page(flow, new_page, true); 1372 ndev->stats.rx_dropped++; 1373 return 0; 1374 } 1375 1376 requeue: 1377 ret = am65_cpsw_nuss_rx_push(common, new_page, flow_idx); 1378 if (WARN_ON(ret < 0)) { 1379 am65_cpsw_put_page(flow, new_page, true); 1380 ndev->stats.rx_errors++; 1381 ndev->stats.rx_dropped++; 1382 } 1383 1384 return ret; 1385 } 1386 1387 static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) 1388 { 1389 struct am65_cpsw_rx_flow *flow = container_of(timer, 1390 struct am65_cpsw_rx_flow, 1391 rx_hrtimer); 1392 1393 enable_irq(flow->irq); 1394 return HRTIMER_NORESTART; 1395 } 1396 1397 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 1398 { 1399 struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); 1400 struct am65_cpsw_common *common = flow->common; 1401 int xdp_state_or = 0; 1402 int cur_budget, ret; 1403 int xdp_state; 1404 int num_rx = 0; 1405 1406 /* process only this flow */ 1407 cur_budget = budget; 1408 while (cur_budget--) { 1409 ret = am65_cpsw_nuss_rx_packets(flow, &xdp_state); 1410 xdp_state_or |= xdp_state; 1411 if (ret) 1412 break; 1413 num_rx++; 1414 } 1415 1416 if (xdp_state_or & AM65_CPSW_XDP_REDIRECT) 1417 xdp_do_flush(); 1418 1419 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 1420 1421 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1422 if (flow->irq_disabled) { 1423 flow->irq_disabled = false; 1424 if (unlikely(flow->rx_pace_timeout)) { 1425 hrtimer_start(&flow->rx_hrtimer, 1426 ns_to_ktime(flow->rx_pace_timeout), 1427 HRTIMER_MODE_REL_PINNED); 1428 } else { 1429 enable_irq(flow->irq); 1430 } 1431 } 1432 } 1433 1434 return num_rx; 1435 } 1436 1437 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 1438 struct netdev_queue *netif_txq) 1439 { 1440 if (netif_tx_queue_stopped(netif_txq)) { 1441 /* Check whether the queue is stopped due to stalled 1442 * tx dma, if the queue is stopped then wake the queue 1443 * as we have free desc for tx 1444 */ 1445 __netif_tx_lock(netif_txq, smp_processor_id()); 1446 if (netif_running(ndev) && 1447 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 1448 netif_tx_wake_queue(netif_txq); 1449 1450 __netif_tx_unlock(netif_txq); 1451 } 1452 } 1453 1454 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 1455 int chn, unsigned int budget, bool *tdown) 1456 { 1457 bool single_port = AM65_CPSW_IS_CPSW2G(common); 1458 enum am65_cpsw_tx_buf_type buf_type; 1459 struct am65_cpsw_tx_swdata *swdata; 1460 struct cppi5_host_desc_t *desc_tx; 1461 struct device *dev = common->dev; 1462 struct am65_cpsw_tx_chn *tx_chn; 1463 struct netdev_queue *netif_txq; 1464 unsigned int total_bytes = 0; 1465 struct net_device *ndev; 1466 struct xdp_frame *xdpf; 1467 unsigned int pkt_len; 1468 struct sk_buff *skb; 1469 dma_addr_t desc_dma; 1470 int res, num_tx = 0; 1471 1472 tx_chn = &common->tx_chns[chn]; 1473 1474 while (true) { 1475 if (!single_port) 1476 spin_lock(&tx_chn->lock); 1477 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1478 if (!single_port) 1479 spin_unlock(&tx_chn->lock); 1480 1481 if (res == -ENODATA) 1482 break; 1483 1484 if (cppi5_desc_is_tdcm(desc_dma)) { 1485 if (atomic_dec_and_test(&common->tdown_cnt)) 1486 complete(&common->tdown_complete); 1487 *tdown = true; 1488 break; 1489 } 1490 1491 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 1492 desc_dma); 1493 swdata = cppi5_hdesc_get_swdata(desc_tx); 1494 ndev = swdata->ndev; 1495 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1496 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1497 skb = swdata->skb; 1498 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 1499 pkt_len = skb->len; 1500 napi_consume_skb(skb, budget); 1501 } else { 1502 xdpf = swdata->xdpf; 1503 pkt_len = xdpf->len; 1504 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1505 xdp_return_frame_rx_napi(xdpf); 1506 else 1507 xdp_return_frame(xdpf); 1508 } 1509 1510 total_bytes += pkt_len; 1511 num_tx++; 1512 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1513 dev_sw_netstats_tx_add(ndev, 1, pkt_len); 1514 if (!single_port) { 1515 /* as packets from multi ports can be interleaved 1516 * on the same channel, we have to figure out the 1517 * port/queue at every packet and report it/wake queue. 1518 */ 1519 netif_txq = netdev_get_tx_queue(ndev, chn); 1520 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1521 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1522 } 1523 } 1524 1525 if (single_port && num_tx) { 1526 netif_txq = netdev_get_tx_queue(ndev, chn); 1527 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1528 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1529 } 1530 1531 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1532 1533 return num_tx; 1534 } 1535 1536 static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer) 1537 { 1538 struct am65_cpsw_tx_chn *tx_chns = 1539 container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer); 1540 1541 enable_irq(tx_chns->irq); 1542 return HRTIMER_NORESTART; 1543 } 1544 1545 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1546 { 1547 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1548 bool tdown = false; 1549 int num_tx; 1550 1551 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, 1552 tx_chn->id, budget, &tdown); 1553 if (num_tx >= budget) 1554 return budget; 1555 1556 if (napi_complete_done(napi_tx, num_tx)) { 1557 if (unlikely(tx_chn->tx_pace_timeout && !tdown)) { 1558 hrtimer_start(&tx_chn->tx_hrtimer, 1559 ns_to_ktime(tx_chn->tx_pace_timeout), 1560 HRTIMER_MODE_REL_PINNED); 1561 } else { 1562 enable_irq(tx_chn->irq); 1563 } 1564 } 1565 1566 return 0; 1567 } 1568 1569 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1570 { 1571 struct am65_cpsw_rx_flow *flow = dev_id; 1572 1573 flow->irq_disabled = true; 1574 disable_irq_nosync(irq); 1575 napi_schedule(&flow->napi_rx); 1576 1577 return IRQ_HANDLED; 1578 } 1579 1580 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1581 { 1582 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1583 1584 disable_irq_nosync(irq); 1585 napi_schedule(&tx_chn->napi_tx); 1586 1587 return IRQ_HANDLED; 1588 } 1589 1590 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1591 struct net_device *ndev) 1592 { 1593 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1594 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1595 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1596 struct am65_cpsw_tx_swdata *swdata; 1597 struct device *dev = common->dev; 1598 struct am65_cpsw_tx_chn *tx_chn; 1599 struct netdev_queue *netif_txq; 1600 dma_addr_t desc_dma, buf_dma; 1601 int ret, q_idx, i; 1602 u32 *psdata; 1603 u32 pkt_len; 1604 1605 /* padding enabled in hw */ 1606 pkt_len = skb_headlen(skb); 1607 1608 /* SKB TX timestamp */ 1609 if (port->tx_ts_enabled) 1610 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1611 1612 q_idx = skb_get_queue_mapping(skb); 1613 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1614 1615 tx_chn = &common->tx_chns[q_idx]; 1616 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1617 1618 /* Map the linear buffer */ 1619 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1620 DMA_TO_DEVICE); 1621 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1622 dev_err(dev, "Failed to map tx skb buffer\n"); 1623 ndev->stats.tx_errors++; 1624 goto err_free_skb; 1625 } 1626 1627 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1628 if (!first_desc) { 1629 dev_dbg(dev, "Failed to allocate descriptor\n"); 1630 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1631 DMA_TO_DEVICE); 1632 goto busy_stop_q; 1633 } 1634 1635 am65_cpsw_nuss_set_buf_type(tx_chn, first_desc, 1636 AM65_CPSW_TX_BUF_TYPE_SKB); 1637 1638 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1639 AM65_CPSW_NAV_PS_DATA_SIZE); 1640 cppi5_desc_set_pktids(&first_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1641 cppi5_hdesc_set_pkttype(first_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1642 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1643 1644 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1645 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1646 swdata = cppi5_hdesc_get_swdata(first_desc); 1647 swdata->ndev = ndev; 1648 swdata->skb = skb; 1649 psdata = cppi5_hdesc_get_psdata(first_desc); 1650 1651 /* HW csum offload if enabled */ 1652 psdata[2] = 0; 1653 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1654 unsigned int cs_start, cs_offset; 1655 1656 cs_start = skb_transport_offset(skb); 1657 cs_offset = cs_start + skb->csum_offset; 1658 /* HW numerates bytes starting from 1 */ 1659 psdata[2] = ((cs_offset + 1) << 24) | 1660 ((cs_start + 1) << 16) | (skb->len - cs_start); 1661 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1662 } 1663 1664 if (!skb_is_nonlinear(skb)) 1665 goto done_tx; 1666 1667 dev_dbg(dev, "fragmented SKB\n"); 1668 1669 /* Handle the case where skb is fragmented in pages */ 1670 cur_desc = first_desc; 1671 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1672 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1673 u32 frag_size = skb_frag_size(frag); 1674 1675 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1676 if (!next_desc) { 1677 dev_err(dev, "Failed to allocate descriptor\n"); 1678 goto busy_free_descs; 1679 } 1680 1681 am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, 1682 AM65_CPSW_TX_BUF_TYPE_SKB); 1683 1684 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1685 DMA_TO_DEVICE); 1686 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1687 dev_err(dev, "Failed to map tx skb page\n"); 1688 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1689 ndev->stats.tx_errors++; 1690 goto err_free_descs; 1691 } 1692 1693 cppi5_hdesc_reset_hbdesc(next_desc); 1694 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1695 cppi5_hdesc_attach_buf(next_desc, 1696 buf_dma, frag_size, buf_dma, frag_size); 1697 1698 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1699 next_desc); 1700 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1701 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1702 1703 pkt_len += frag_size; 1704 cur_desc = next_desc; 1705 } 1706 WARN_ON(pkt_len != skb->len); 1707 1708 done_tx: 1709 skb_tx_timestamp(skb); 1710 1711 /* report bql before sending packet */ 1712 netdev_tx_sent_queue(netif_txq, pkt_len); 1713 1714 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1715 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1716 if (AM65_CPSW_IS_CPSW2G(common)) { 1717 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1718 } else { 1719 spin_lock_bh(&tx_chn->lock); 1720 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1721 spin_unlock_bh(&tx_chn->lock); 1722 } 1723 if (ret) { 1724 dev_err(dev, "can't push desc %d\n", ret); 1725 /* inform bql */ 1726 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1727 ndev->stats.tx_errors++; 1728 goto err_free_descs; 1729 } 1730 1731 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1732 netif_tx_stop_queue(netif_txq); 1733 /* Barrier, so that stop_queue visible to other cpus */ 1734 smp_mb__after_atomic(); 1735 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1736 1737 /* re-check for smp */ 1738 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1739 MAX_SKB_FRAGS) { 1740 netif_tx_wake_queue(netif_txq); 1741 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1742 } 1743 } 1744 1745 return NETDEV_TX_OK; 1746 1747 err_free_descs: 1748 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1749 err_free_skb: 1750 ndev->stats.tx_dropped++; 1751 dev_kfree_skb_any(skb); 1752 return NETDEV_TX_OK; 1753 1754 busy_free_descs: 1755 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1756 busy_stop_q: 1757 netif_tx_stop_queue(netif_txq); 1758 return NETDEV_TX_BUSY; 1759 } 1760 1761 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1762 void *addr) 1763 { 1764 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1765 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1766 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1767 int ret; 1768 1769 ret = eth_prepare_mac_addr_change(ndev, addr); 1770 if (ret < 0) 1771 return ret; 1772 1773 ret = pm_runtime_resume_and_get(common->dev); 1774 if (ret < 0) 1775 return ret; 1776 1777 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1778 HOST_PORT_NUM, 0, 0); 1779 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1780 HOST_PORT_NUM, ALE_SECURE, 0); 1781 1782 am65_cpsw_port_set_sl_mac(port, addr); 1783 eth_commit_mac_addr_change(ndev, sockaddr); 1784 1785 pm_runtime_put(common->dev); 1786 1787 return 0; 1788 } 1789 1790 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1791 struct ifreq *ifr) 1792 { 1793 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1794 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1795 struct hwtstamp_config cfg; 1796 1797 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1798 return -EOPNOTSUPP; 1799 1800 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1801 return -EFAULT; 1802 1803 /* TX HW timestamp */ 1804 switch (cfg.tx_type) { 1805 case HWTSTAMP_TX_OFF: 1806 case HWTSTAMP_TX_ON: 1807 break; 1808 default: 1809 return -ERANGE; 1810 } 1811 1812 switch (cfg.rx_filter) { 1813 case HWTSTAMP_FILTER_NONE: 1814 port->rx_ts_enabled = false; 1815 break; 1816 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1817 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1818 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1819 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1820 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1821 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1822 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1823 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1824 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1825 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1826 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1827 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1828 port->rx_ts_enabled = true; 1829 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT | HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 1830 break; 1831 case HWTSTAMP_FILTER_ALL: 1832 case HWTSTAMP_FILTER_SOME: 1833 case HWTSTAMP_FILTER_NTP_ALL: 1834 return -EOPNOTSUPP; 1835 default: 1836 return -ERANGE; 1837 } 1838 1839 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1840 1841 /* cfg TX timestamp */ 1842 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1843 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1844 1845 ts_vlan_ltype = ETH_P_8021Q; 1846 1847 ts_ctrl_ltype2 = ETH_P_1588 | 1848 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1849 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1850 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1851 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1852 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1853 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1854 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1855 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1856 1857 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1858 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1859 1860 if (port->tx_ts_enabled) 1861 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1862 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1863 1864 if (port->rx_ts_enabled) 1865 ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN | 1866 AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN; 1867 1868 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1869 writel(ts_vlan_ltype, port->port_base + 1870 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1871 writel(ts_ctrl_ltype2, port->port_base + 1872 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1873 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1874 1875 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1876 } 1877 1878 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1879 struct ifreq *ifr) 1880 { 1881 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1882 struct hwtstamp_config cfg; 1883 1884 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1885 return -EOPNOTSUPP; 1886 1887 cfg.flags = 0; 1888 cfg.tx_type = port->tx_ts_enabled ? 1889 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1890 cfg.rx_filter = port->rx_ts_enabled ? HWTSTAMP_FILTER_PTP_V2_EVENT | 1891 HWTSTAMP_FILTER_PTP_V1_L4_EVENT : HWTSTAMP_FILTER_NONE; 1892 1893 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1894 } 1895 1896 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1897 struct ifreq *req, int cmd) 1898 { 1899 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1900 1901 if (!netif_running(ndev)) 1902 return -EINVAL; 1903 1904 switch (cmd) { 1905 case SIOCSHWTSTAMP: 1906 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1907 case SIOCGHWTSTAMP: 1908 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1909 } 1910 1911 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1912 } 1913 1914 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1915 struct rtnl_link_stats64 *stats) 1916 { 1917 dev_fetch_sw_netstats(stats, dev->tstats); 1918 1919 stats->rx_errors = dev->stats.rx_errors; 1920 stats->rx_dropped = dev->stats.rx_dropped; 1921 stats->tx_dropped = dev->stats.tx_dropped; 1922 } 1923 1924 static int am65_cpsw_xdp_prog_setup(struct net_device *ndev, 1925 struct bpf_prog *prog) 1926 { 1927 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1928 bool running = netif_running(ndev); 1929 struct bpf_prog *old_prog; 1930 1931 if (running) 1932 am65_cpsw_nuss_ndo_slave_stop(ndev); 1933 1934 old_prog = xchg(&port->xdp_prog, prog); 1935 if (old_prog) 1936 bpf_prog_put(old_prog); 1937 1938 if (running) 1939 return am65_cpsw_nuss_ndo_slave_open(ndev); 1940 1941 return 0; 1942 } 1943 1944 static int am65_cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 1945 { 1946 switch (bpf->command) { 1947 case XDP_SETUP_PROG: 1948 return am65_cpsw_xdp_prog_setup(ndev, bpf->prog); 1949 default: 1950 return -EINVAL; 1951 } 1952 } 1953 1954 static int am65_cpsw_ndo_xdp_xmit(struct net_device *ndev, int n, 1955 struct xdp_frame **frames, u32 flags) 1956 { 1957 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1958 struct am65_cpsw_tx_chn *tx_chn; 1959 struct netdev_queue *netif_txq; 1960 int cpu = smp_processor_id(); 1961 int i, nxmit = 0; 1962 1963 tx_chn = &common->tx_chns[cpu % common->tx_ch_num]; 1964 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1965 1966 __netif_tx_lock(netif_txq, cpu); 1967 for (i = 0; i < n; i++) { 1968 if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], 1969 AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) 1970 break; 1971 nxmit++; 1972 } 1973 __netif_tx_unlock(netif_txq); 1974 1975 return nxmit; 1976 } 1977 1978 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1979 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1980 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1981 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1982 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1983 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1984 .ndo_validate_addr = eth_validate_addr, 1985 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1986 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1987 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1988 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1989 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1990 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1991 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 1992 .ndo_bpf = am65_cpsw_ndo_bpf, 1993 .ndo_xdp_xmit = am65_cpsw_ndo_xdp_xmit, 1994 }; 1995 1996 static void am65_cpsw_disable_phy(struct phy *phy) 1997 { 1998 phy_power_off(phy); 1999 phy_exit(phy); 2000 } 2001 2002 static int am65_cpsw_enable_phy(struct phy *phy) 2003 { 2004 int ret; 2005 2006 ret = phy_init(phy); 2007 if (ret < 0) 2008 return ret; 2009 2010 ret = phy_power_on(phy); 2011 if (ret < 0) { 2012 phy_exit(phy); 2013 return ret; 2014 } 2015 2016 return 0; 2017 } 2018 2019 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 2020 { 2021 struct am65_cpsw_port *port; 2022 struct phy *phy; 2023 int i; 2024 2025 for (i = 0; i < common->port_num; i++) { 2026 port = &common->ports[i]; 2027 phy = port->slave.serdes_phy; 2028 if (phy) 2029 am65_cpsw_disable_phy(phy); 2030 } 2031 } 2032 2033 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 2034 struct am65_cpsw_port *port) 2035 { 2036 const char *name = "serdes"; 2037 struct phy *phy; 2038 int ret; 2039 2040 phy = devm_of_phy_optional_get(dev, port_np, name); 2041 if (IS_ERR_OR_NULL(phy)) 2042 return PTR_ERR_OR_ZERO(phy); 2043 2044 /* Serdes PHY exists. Store it. */ 2045 port->slave.serdes_phy = phy; 2046 2047 ret = am65_cpsw_enable_phy(phy); 2048 if (ret < 0) 2049 goto err_phy; 2050 2051 return 0; 2052 2053 err_phy: 2054 devm_phy_put(dev, phy); 2055 return ret; 2056 } 2057 2058 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 2059 const struct phylink_link_state *state) 2060 { 2061 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2062 phylink_config); 2063 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2064 struct am65_cpsw_common *common = port->common; 2065 2066 if (common->pdata.extra_modes & BIT(state->interface)) { 2067 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 2068 writel(ADVERTISE_SGMII, 2069 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 2070 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2071 } else { 2072 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2073 } 2074 2075 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 2076 cpsw_sl_ctl_set(port->slave.mac_sl, 2077 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2078 } else { 2079 cpsw_sl_ctl_clr(port->slave.mac_sl, 2080 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2081 } 2082 2083 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 2084 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 2085 } 2086 } 2087 2088 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 2089 phy_interface_t interface) 2090 { 2091 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2092 phylink_config); 2093 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2094 struct am65_cpsw_common *common = port->common; 2095 struct net_device *ndev = port->ndev; 2096 u32 mac_control; 2097 int tmo; 2098 2099 /* disable forwarding */ 2100 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2101 2102 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2103 2104 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 2105 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 2106 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 2107 2108 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 2109 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 2110 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 2111 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 2112 if (phy_interface_mode_is_rgmii(interface)) 2113 mac_control |= CPSW_SL_CTL_EXT_EN; 2114 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 2115 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 2116 2117 am65_cpsw_qos_link_down(ndev); 2118 netif_tx_stop_all_queues(ndev); 2119 } 2120 2121 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 2122 unsigned int mode, phy_interface_t interface, int speed, 2123 int duplex, bool tx_pause, bool rx_pause) 2124 { 2125 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2126 phylink_config); 2127 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2128 struct am65_cpsw_common *common = port->common; 2129 u32 mac_control = CPSW_SL_CTL_GMII_EN; 2130 struct net_device *ndev = port->ndev; 2131 2132 /* Bring the port out of idle state */ 2133 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2134 2135 if (speed == SPEED_1000) 2136 mac_control |= CPSW_SL_CTL_GIG; 2137 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 2138 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 2139 /* Can be used with in band mode only */ 2140 mac_control |= CPSW_SL_CTL_EXT_EN; 2141 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 2142 mac_control |= CPSW_SL_CTL_IFCTL_A; 2143 if (duplex) 2144 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 2145 2146 /* rx_pause/tx_pause */ 2147 if (rx_pause) 2148 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 2149 2150 if (tx_pause) 2151 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 2152 2153 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 2154 2155 /* enable forwarding */ 2156 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2157 2158 am65_cpsw_qos_link_up(ndev, speed); 2159 netif_tx_wake_all_queues(ndev); 2160 } 2161 2162 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 2163 .mac_config = am65_cpsw_nuss_mac_config, 2164 .mac_link_down = am65_cpsw_nuss_mac_link_down, 2165 .mac_link_up = am65_cpsw_nuss_mac_link_up, 2166 }; 2167 2168 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 2169 { 2170 struct am65_cpsw_common *common = port->common; 2171 2172 if (!port->disabled) 2173 return; 2174 2175 cpsw_ale_control_set(common->ale, port->port_id, 2176 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2177 2178 cpsw_sl_reset(port->slave.mac_sl, 100); 2179 cpsw_sl_ctl_reset(port->slave.mac_sl); 2180 } 2181 2182 static void am65_cpsw_nuss_free_tx_chns(void *data) 2183 { 2184 struct am65_cpsw_common *common = data; 2185 int i; 2186 2187 for (i = 0; i < common->tx_ch_num; i++) { 2188 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2189 2190 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2191 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2192 2193 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2194 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2195 2196 memset(tx_chn, 0, sizeof(*tx_chn)); 2197 } 2198 } 2199 2200 static void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 2201 { 2202 struct device *dev = common->dev; 2203 int i; 2204 2205 common->tx_ch_rate_msk = 0; 2206 for (i = 0; i < common->tx_ch_num; i++) { 2207 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2208 2209 if (tx_chn->irq > 0) 2210 devm_free_irq(dev, tx_chn->irq, tx_chn); 2211 2212 netif_napi_del(&tx_chn->napi_tx); 2213 } 2214 2215 am65_cpsw_nuss_free_tx_chns(common); 2216 } 2217 2218 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2219 { 2220 struct device *dev = common->dev; 2221 struct am65_cpsw_tx_chn *tx_chn; 2222 int i, ret = 0; 2223 2224 for (i = 0; i < common->tx_ch_num; i++) { 2225 tx_chn = &common->tx_chns[i]; 2226 2227 hrtimer_setup(&tx_chn->tx_hrtimer, &am65_cpsw_nuss_tx_timer_callback, 2228 CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2229 2230 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2231 am65_cpsw_nuss_tx_poll); 2232 2233 ret = devm_request_irq(dev, tx_chn->irq, 2234 am65_cpsw_nuss_tx_irq, 2235 IRQF_TRIGGER_HIGH, 2236 tx_chn->tx_chn_name, tx_chn); 2237 if (ret) { 2238 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2239 tx_chn->id, tx_chn->irq, ret); 2240 goto err; 2241 } 2242 } 2243 2244 return 0; 2245 2246 err: 2247 netif_napi_del(&tx_chn->napi_tx); 2248 for (--i; i >= 0; i--) { 2249 tx_chn = &common->tx_chns[i]; 2250 devm_free_irq(dev, tx_chn->irq, tx_chn); 2251 netif_napi_del(&tx_chn->napi_tx); 2252 } 2253 2254 return ret; 2255 } 2256 2257 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 2258 { 2259 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 2260 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 2261 struct device *dev = common->dev; 2262 struct k3_ring_cfg ring_cfg = { 2263 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2264 .mode = K3_RINGACC_RING_MODE_RING, 2265 .flags = 0 2266 }; 2267 u32 hdesc_size, hdesc_size_out; 2268 int i, ret = 0; 2269 2270 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2271 AM65_CPSW_NAV_SW_DATA_SIZE); 2272 2273 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2274 tx_cfg.tx_cfg = ring_cfg; 2275 tx_cfg.txcq_cfg = ring_cfg; 2276 tx_cfg.tx_cfg.size = max_desc_num; 2277 tx_cfg.txcq_cfg.size = max_desc_num; 2278 2279 for (i = 0; i < common->tx_ch_num; i++) { 2280 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2281 2282 snprintf(tx_chn->tx_chn_name, 2283 sizeof(tx_chn->tx_chn_name), "tx%d", i); 2284 2285 spin_lock_init(&tx_chn->lock); 2286 tx_chn->common = common; 2287 tx_chn->id = i; 2288 tx_chn->descs_num = max_desc_num; 2289 2290 tx_chn->tx_chn = 2291 k3_udma_glue_request_tx_chn(dev, 2292 tx_chn->tx_chn_name, 2293 &tx_cfg); 2294 if (IS_ERR(tx_chn->tx_chn)) { 2295 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 2296 "Failed to request tx dma channel\n"); 2297 goto err; 2298 } 2299 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 2300 2301 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 2302 tx_chn->descs_num, 2303 hdesc_size, 2304 tx_chn->tx_chn_name); 2305 if (IS_ERR(tx_chn->desc_pool)) { 2306 ret = PTR_ERR(tx_chn->desc_pool); 2307 dev_err(dev, "Failed to create poll %d\n", ret); 2308 goto err; 2309 } 2310 2311 hdesc_size_out = k3_cppi_desc_pool_desc_size(tx_chn->desc_pool); 2312 tx_chn->dsize_log2 = __fls(hdesc_size_out); 2313 WARN_ON(hdesc_size_out != (1 << tx_chn->dsize_log2)); 2314 2315 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 2316 if (tx_chn->irq < 0) { 2317 dev_err(dev, "Failed to get tx dma irq %d\n", 2318 tx_chn->irq); 2319 ret = tx_chn->irq; 2320 goto err; 2321 } 2322 2323 snprintf(tx_chn->tx_chn_name, 2324 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 2325 dev_name(dev), tx_chn->id); 2326 } 2327 2328 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2329 if (ret) { 2330 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 2331 goto err; 2332 } 2333 2334 return 0; 2335 2336 err: 2337 am65_cpsw_nuss_free_tx_chns(common); 2338 2339 return ret; 2340 } 2341 2342 static void am65_cpsw_nuss_free_rx_chns(void *data) 2343 { 2344 struct am65_cpsw_common *common = data; 2345 struct am65_cpsw_rx_chn *rx_chn; 2346 2347 rx_chn = &common->rx_chns; 2348 2349 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 2350 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 2351 2352 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 2353 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 2354 } 2355 2356 static void am65_cpsw_nuss_remove_rx_chns(struct am65_cpsw_common *common) 2357 { 2358 struct device *dev = common->dev; 2359 struct am65_cpsw_rx_chn *rx_chn; 2360 struct am65_cpsw_rx_flow *flows; 2361 int i; 2362 2363 rx_chn = &common->rx_chns; 2364 flows = rx_chn->flows; 2365 2366 for (i = 0; i < common->rx_ch_num_flows; i++) { 2367 if (!(flows[i].irq < 0)) 2368 devm_free_irq(dev, flows[i].irq, &flows[i]); 2369 netif_napi_del(&flows[i].napi_rx); 2370 } 2371 2372 am65_cpsw_nuss_free_rx_chns(common); 2373 2374 common->rx_flow_id_base = -1; 2375 } 2376 2377 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 2378 { 2379 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 2380 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 2381 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 2382 struct device *dev = common->dev; 2383 struct am65_cpsw_rx_flow *flow; 2384 u32 hdesc_size, hdesc_size_out; 2385 u32 fdqring_id; 2386 int i, ret = 0; 2387 2388 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2389 AM65_CPSW_NAV_SW_DATA_SIZE); 2390 2391 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2392 rx_cfg.flow_id_num = common->rx_ch_num_flows; 2393 rx_cfg.flow_id_base = common->rx_flow_id_base; 2394 2395 /* init all flows */ 2396 rx_chn->dev = dev; 2397 rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; 2398 2399 for (i = 0; i < common->rx_ch_num_flows; i++) { 2400 flow = &rx_chn->flows[i]; 2401 flow->page_pool = NULL; 2402 } 2403 2404 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 2405 if (IS_ERR(rx_chn->rx_chn)) { 2406 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 2407 "Failed to request rx dma channel\n"); 2408 goto err; 2409 } 2410 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 2411 2412 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 2413 rx_chn->descs_num, 2414 hdesc_size, "rx"); 2415 if (IS_ERR(rx_chn->desc_pool)) { 2416 ret = PTR_ERR(rx_chn->desc_pool); 2417 dev_err(dev, "Failed to create rx poll %d\n", ret); 2418 goto err; 2419 } 2420 2421 hdesc_size_out = k3_cppi_desc_pool_desc_size(rx_chn->desc_pool); 2422 rx_chn->dsize_log2 = __fls(hdesc_size_out); 2423 WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); 2424 2425 common->rx_flow_id_base = 2426 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 2427 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 2428 2429 fdqring_id = K3_RINGACC_RING_ID_ANY; 2430 for (i = 0; i < rx_cfg.flow_id_num; i++) { 2431 struct k3_ring_cfg rxring_cfg = { 2432 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2433 .mode = K3_RINGACC_RING_MODE_RING, 2434 .flags = 0, 2435 }; 2436 struct k3_ring_cfg fdqring_cfg = { 2437 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2438 .flags = K3_RINGACC_RING_SHARED, 2439 }; 2440 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 2441 .rx_cfg = rxring_cfg, 2442 .rxfdq_cfg = fdqring_cfg, 2443 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 2444 .src_tag_lo_sel = 2445 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 2446 }; 2447 2448 flow = &rx_chn->flows[i]; 2449 flow->id = i; 2450 flow->common = common; 2451 flow->irq = -EINVAL; 2452 2453 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 2454 rx_flow_cfg.rx_cfg.size = max_desc_num; 2455 /* share same FDQ for all flows */ 2456 rx_flow_cfg.rxfdq_cfg.size = max_desc_num * rx_cfg.flow_id_num; 2457 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 2458 2459 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 2460 i, &rx_flow_cfg); 2461 if (ret) { 2462 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 2463 goto err_flow; 2464 } 2465 if (!i) 2466 fdqring_id = 2467 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 2468 i); 2469 2470 flow->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 2471 if (flow->irq <= 0) { 2472 dev_err(dev, "Failed to get rx dma irq %d\n", 2473 flow->irq); 2474 ret = flow->irq; 2475 goto err_flow; 2476 } 2477 2478 snprintf(flow->name, 2479 sizeof(flow->name), "%s-rx%d", 2480 dev_name(dev), i); 2481 hrtimer_setup(&flow->rx_hrtimer, &am65_cpsw_nuss_rx_timer_callback, CLOCK_MONOTONIC, 2482 HRTIMER_MODE_REL_PINNED); 2483 2484 netif_napi_add(common->dma_ndev, &flow->napi_rx, 2485 am65_cpsw_nuss_rx_poll); 2486 2487 ret = devm_request_irq(dev, flow->irq, 2488 am65_cpsw_nuss_rx_irq, 2489 IRQF_TRIGGER_HIGH, 2490 flow->name, flow); 2491 if (ret) { 2492 dev_err(dev, "failure requesting rx %d irq %u, %d\n", 2493 i, flow->irq, ret); 2494 flow->irq = -EINVAL; 2495 goto err_request_irq; 2496 } 2497 } 2498 2499 /* setup classifier to route priorities to flows */ 2500 cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); 2501 2502 return 0; 2503 2504 err_request_irq: 2505 netif_napi_del(&flow->napi_rx); 2506 2507 err_flow: 2508 for (--i; i >= 0; i--) { 2509 flow = &rx_chn->flows[i]; 2510 devm_free_irq(dev, flow->irq, flow); 2511 netif_napi_del(&flow->napi_rx); 2512 } 2513 2514 err: 2515 am65_cpsw_nuss_free_rx_chns(common); 2516 2517 return ret; 2518 } 2519 2520 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 2521 { 2522 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2523 2524 host_p->common = common; 2525 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 2526 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 2527 2528 return 0; 2529 } 2530 2531 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 2532 int slave, u8 *mac_addr) 2533 { 2534 u32 mac_lo, mac_hi, offset; 2535 struct regmap *syscon; 2536 2537 syscon = syscon_regmap_lookup_by_phandle_args(of_node, "ti,syscon-efuse", 2538 1, &offset); 2539 if (IS_ERR(syscon)) { 2540 if (PTR_ERR(syscon) == -ENODEV) 2541 return 0; 2542 return PTR_ERR(syscon); 2543 } 2544 2545 regmap_read(syscon, offset, &mac_lo); 2546 regmap_read(syscon, offset + 4, &mac_hi); 2547 2548 mac_addr[0] = (mac_hi >> 8) & 0xff; 2549 mac_addr[1] = mac_hi & 0xff; 2550 mac_addr[2] = (mac_lo >> 24) & 0xff; 2551 mac_addr[3] = (mac_lo >> 16) & 0xff; 2552 mac_addr[4] = (mac_lo >> 8) & 0xff; 2553 mac_addr[5] = mac_lo & 0xff; 2554 2555 return 0; 2556 } 2557 2558 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 2559 { 2560 struct device *dev = common->dev; 2561 struct device_node *node; 2562 struct am65_cpts *cpts; 2563 void __iomem *reg_base; 2564 2565 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 2566 return 0; 2567 2568 node = of_get_child_by_name(dev->of_node, "cpts"); 2569 if (!node) { 2570 dev_err(dev, "%s cpts not found\n", __func__); 2571 return -ENOENT; 2572 } 2573 2574 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 2575 cpts = am65_cpts_create(dev, reg_base, node); 2576 if (IS_ERR(cpts)) { 2577 int ret = PTR_ERR(cpts); 2578 2579 of_node_put(node); 2580 dev_err(dev, "cpts create err %d\n", ret); 2581 return ret; 2582 } 2583 common->cpts = cpts; 2584 /* Forbid PM runtime if CPTS is running. 2585 * K3 CPSWxG modules may completely lose context during ON->OFF 2586 * transitions depending on integration. 2587 * AM65x/J721E MCU CPSW2G: false 2588 * J721E MAIN_CPSW9G: true 2589 */ 2590 pm_runtime_forbid(dev); 2591 2592 return 0; 2593 } 2594 2595 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2596 { 2597 struct device_node *node, *port_np; 2598 struct device *dev = common->dev; 2599 int ret; 2600 2601 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2602 if (!node) 2603 return -ENOENT; 2604 2605 for_each_child_of_node(node, port_np) { 2606 phy_interface_t phy_if; 2607 struct am65_cpsw_port *port; 2608 u32 port_id; 2609 2610 /* it is not a slave port node, continue */ 2611 if (strcmp(port_np->name, "port")) 2612 continue; 2613 2614 ret = of_property_read_u32(port_np, "reg", &port_id); 2615 if (ret < 0) { 2616 dev_err(dev, "%pOF error reading port_id %d\n", 2617 port_np, ret); 2618 goto of_node_put; 2619 } 2620 2621 if (!port_id || port_id > common->port_num) { 2622 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2623 port_np, port_id, port_np->name); 2624 ret = -EINVAL; 2625 goto of_node_put; 2626 } 2627 2628 port = am65_common_get_port(common, port_id); 2629 port->port_id = port_id; 2630 port->common = common; 2631 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2632 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2633 if (common->pdata.extra_modes) 2634 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2635 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2636 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2637 port->name = of_get_property(port_np, "label", NULL); 2638 port->fetch_ram_base = 2639 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2640 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2641 2642 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2643 if (IS_ERR(port->slave.mac_sl)) { 2644 ret = PTR_ERR(port->slave.mac_sl); 2645 goto of_node_put; 2646 } 2647 2648 port->disabled = !of_device_is_available(port_np); 2649 if (port->disabled) { 2650 common->disabled_ports_mask |= BIT(port->port_id); 2651 continue; 2652 } 2653 2654 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2655 if (IS_ERR(port->slave.ifphy)) { 2656 ret = PTR_ERR(port->slave.ifphy); 2657 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2658 port_np, ret); 2659 goto of_node_put; 2660 } 2661 2662 /* Initialize the Serdes PHY for the port */ 2663 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2664 if (ret) 2665 goto of_node_put; 2666 2667 port->slave.mac_only = 2668 of_property_read_bool(port_np, "ti,mac-only"); 2669 2670 /* get phy/link info */ 2671 port->slave.port_np = of_node_get(port_np); 2672 ret = of_get_phy_mode(port_np, &phy_if); 2673 if (ret) { 2674 dev_err(dev, "%pOF read phy-mode err %d\n", 2675 port_np, ret); 2676 goto of_node_put; 2677 } 2678 2679 /* CPSW controllers supported by this driver have a fixed 2680 * internal TX delay in RGMII mode. Fix up PHY mode to account 2681 * for this and warn about Device Trees that claim to have a TX 2682 * delay on the PCB. 2683 */ 2684 switch (phy_if) { 2685 case PHY_INTERFACE_MODE_RGMII_ID: 2686 phy_if = PHY_INTERFACE_MODE_RGMII_RXID; 2687 break; 2688 case PHY_INTERFACE_MODE_RGMII_TXID: 2689 phy_if = PHY_INTERFACE_MODE_RGMII; 2690 break; 2691 case PHY_INTERFACE_MODE_RGMII: 2692 case PHY_INTERFACE_MODE_RGMII_RXID: 2693 dev_warn(dev, 2694 "RGMII mode without internal TX delay unsupported; please fix your Device Tree\n"); 2695 break; 2696 default: 2697 break; 2698 } 2699 2700 port->slave.phy_if = phy_if; 2701 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, phy_if); 2702 if (ret) 2703 goto of_node_put; 2704 2705 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2706 if (ret == -EPROBE_DEFER) { 2707 goto of_node_put; 2708 } else if (ret) { 2709 am65_cpsw_am654_get_efuse_macid(port_np, 2710 port->port_id, 2711 port->slave.mac_addr); 2712 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2713 eth_random_addr(port->slave.mac_addr); 2714 dev_info(dev, "Use random MAC address\n"); 2715 } 2716 } 2717 2718 /* Reset all Queue priorities to 0 */ 2719 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); 2720 } 2721 of_node_put(node); 2722 2723 /* is there at least one ext.port */ 2724 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2725 dev_err(dev, "No Ext. port are available\n"); 2726 return -ENODEV; 2727 } 2728 2729 return 0; 2730 2731 of_node_put: 2732 of_node_put(port_np); 2733 of_node_put(node); 2734 return ret; 2735 } 2736 2737 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2738 { 2739 struct am65_cpsw_port *port; 2740 int i; 2741 2742 for (i = 0; i < common->port_num; i++) { 2743 port = &common->ports[i]; 2744 if (port->slave.phylink) 2745 phylink_destroy(port->slave.phylink); 2746 } 2747 } 2748 2749 static void am65_cpsw_remove_dt(struct am65_cpsw_common *common) 2750 { 2751 struct am65_cpsw_port *port; 2752 int i; 2753 2754 for (i = 0; i < common->port_num; i++) { 2755 port = &common->ports[i]; 2756 of_node_put(port->slave.port_np); 2757 } 2758 } 2759 2760 static int 2761 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2762 { 2763 struct am65_cpsw_ndev_priv *ndev_priv; 2764 struct device *dev = common->dev; 2765 struct am65_cpsw_port *port; 2766 struct phylink *phylink; 2767 2768 port = &common->ports[port_idx]; 2769 2770 if (port->disabled) 2771 return 0; 2772 2773 /* alloc netdev */ 2774 port->ndev = alloc_etherdev_mqs(sizeof(struct am65_cpsw_ndev_priv), 2775 AM65_CPSW_MAX_QUEUES, 2776 AM65_CPSW_MAX_QUEUES); 2777 if (!port->ndev) { 2778 dev_err(dev, "error allocating slave net_device %u\n", 2779 port->port_id); 2780 return -ENOMEM; 2781 } 2782 2783 ndev_priv = netdev_priv(port->ndev); 2784 ndev_priv->port = port; 2785 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2786 mutex_init(&ndev_priv->mm_lock); 2787 port->qos.link_speed = SPEED_UNKNOWN; 2788 SET_NETDEV_DEV(port->ndev, dev); 2789 device_set_node(&port->ndev->dev, of_fwnode_handle(port->slave.port_np)); 2790 2791 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2792 2793 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2794 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE - 2795 (VLAN_ETH_HLEN + ETH_FCS_LEN); 2796 port->ndev->hw_features = NETIF_F_SG | 2797 NETIF_F_RXCSUM | 2798 NETIF_F_HW_CSUM | 2799 NETIF_F_HW_TC; 2800 port->ndev->features = port->ndev->hw_features | 2801 NETIF_F_HW_VLAN_CTAG_FILTER; 2802 port->ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 2803 NETDEV_XDP_ACT_REDIRECT | 2804 NETDEV_XDP_ACT_NDO_XMIT; 2805 port->ndev->vlan_features |= NETIF_F_SG; 2806 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2807 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2808 2809 /* Configuring Phylink */ 2810 port->slave.phylink_config.dev = &port->ndev->dev; 2811 port->slave.phylink_config.type = PHYLINK_NETDEV; 2812 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2813 MAC_1000FD | MAC_5000FD; 2814 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2815 2816 switch (port->slave.phy_if) { 2817 case PHY_INTERFACE_MODE_RGMII: 2818 case PHY_INTERFACE_MODE_RGMII_ID: 2819 case PHY_INTERFACE_MODE_RGMII_RXID: 2820 case PHY_INTERFACE_MODE_RGMII_TXID: 2821 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2822 break; 2823 2824 case PHY_INTERFACE_MODE_RMII: 2825 __set_bit(PHY_INTERFACE_MODE_RMII, 2826 port->slave.phylink_config.supported_interfaces); 2827 break; 2828 2829 case PHY_INTERFACE_MODE_QSGMII: 2830 case PHY_INTERFACE_MODE_SGMII: 2831 case PHY_INTERFACE_MODE_USXGMII: 2832 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2833 __set_bit(port->slave.phy_if, 2834 port->slave.phylink_config.supported_interfaces); 2835 } else { 2836 dev_err(dev, "selected phy-mode is not supported\n"); 2837 return -EOPNOTSUPP; 2838 } 2839 break; 2840 2841 default: 2842 dev_err(dev, "selected phy-mode is not supported\n"); 2843 return -EOPNOTSUPP; 2844 } 2845 2846 phylink = phylink_create(&port->slave.phylink_config, 2847 of_fwnode_handle(port->slave.port_np), 2848 port->slave.phy_if, 2849 &am65_cpsw_phylink_mac_ops); 2850 if (IS_ERR(phylink)) 2851 return PTR_ERR(phylink); 2852 2853 port->slave.phylink = phylink; 2854 2855 /* Disable TX checksum offload by default due to HW bug */ 2856 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2857 port->ndev->features &= ~NETIF_F_HW_CSUM; 2858 2859 port->ndev->pcpu_stat_type = NETDEV_PCPU_STAT_TSTATS; 2860 port->xdp_prog = NULL; 2861 2862 if (!common->dma_ndev) 2863 common->dma_ndev = port->ndev; 2864 2865 return 0; 2866 } 2867 2868 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2869 { 2870 int ret; 2871 int i; 2872 2873 for (i = 0; i < common->port_num; i++) { 2874 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2875 if (ret) 2876 return ret; 2877 } 2878 2879 return ret; 2880 } 2881 2882 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2883 { 2884 struct am65_cpsw_port *port; 2885 int i; 2886 2887 for (i = 0; i < common->port_num; i++) { 2888 port = &common->ports[i]; 2889 if (!port->ndev) 2890 continue; 2891 if (port->ndev->reg_state == NETREG_REGISTERED) 2892 unregister_netdev(port->ndev); 2893 free_netdev(port->ndev); 2894 port->ndev = NULL; 2895 } 2896 } 2897 2898 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2899 { 2900 int set_val = 0; 2901 int i; 2902 2903 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2904 set_val = 1; 2905 2906 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2907 2908 for (i = 1; i <= common->port_num; i++) { 2909 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2910 struct am65_cpsw_ndev_priv *priv; 2911 2912 if (!port->ndev) 2913 continue; 2914 2915 priv = am65_ndev_to_priv(port->ndev); 2916 priv->offload_fwd_mark = set_val; 2917 } 2918 } 2919 2920 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2921 { 2922 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2923 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2924 2925 return !common->is_emac_mode; 2926 } 2927 2928 return false; 2929 } 2930 2931 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2932 struct net_device *br_ndev, 2933 struct netlink_ext_ack *extack) 2934 { 2935 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2936 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2937 int err; 2938 2939 if (!common->br_members) { 2940 common->hw_bridge_dev = br_ndev; 2941 } else { 2942 /* This is adding the port to a second bridge, this is 2943 * unsupported 2944 */ 2945 if (common->hw_bridge_dev != br_ndev) 2946 return -EOPNOTSUPP; 2947 } 2948 2949 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2950 false, extack); 2951 if (err) 2952 return err; 2953 2954 common->br_members |= BIT(priv->port->port_id); 2955 2956 am65_cpsw_port_offload_fwd_mark_update(common); 2957 2958 return NOTIFY_DONE; 2959 } 2960 2961 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2962 { 2963 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2964 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2965 2966 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2967 2968 common->br_members &= ~BIT(priv->port->port_id); 2969 2970 am65_cpsw_port_offload_fwd_mark_update(common); 2971 2972 if (!common->br_members) 2973 common->hw_bridge_dev = NULL; 2974 } 2975 2976 /* netdev notifier */ 2977 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2978 unsigned long event, void *ptr) 2979 { 2980 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2981 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2982 struct netdev_notifier_changeupper_info *info; 2983 int ret = NOTIFY_DONE; 2984 2985 if (!am65_cpsw_port_dev_check(ndev)) 2986 return NOTIFY_DONE; 2987 2988 switch (event) { 2989 case NETDEV_CHANGEUPPER: 2990 info = ptr; 2991 2992 if (netif_is_bridge_master(info->upper_dev)) { 2993 if (info->linking) 2994 ret = am65_cpsw_netdevice_port_link(ndev, 2995 info->upper_dev, 2996 extack); 2997 else 2998 am65_cpsw_netdevice_port_unlink(ndev); 2999 } 3000 break; 3001 default: 3002 return NOTIFY_DONE; 3003 } 3004 3005 return notifier_from_errno(ret); 3006 } 3007 3008 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 3009 { 3010 int ret = 0; 3011 3012 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3013 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3014 return 0; 3015 3016 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 3017 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3018 if (ret) { 3019 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 3020 return ret; 3021 } 3022 3023 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 3024 if (ret) 3025 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3026 3027 return ret; 3028 } 3029 3030 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 3031 { 3032 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3033 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3034 return; 3035 3036 am65_cpsw_switchdev_unregister_notifiers(cpsw); 3037 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3038 } 3039 3040 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 3041 3042 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 3043 { 3044 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 3045 ALE_MCAST_BLOCK_LEARN_FWD); 3046 } 3047 3048 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 3049 { 3050 struct am65_cpsw_host *host = am65_common_get_host(common); 3051 3052 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3053 3054 am65_cpsw_init_stp_ale_entry(common); 3055 3056 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 3057 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 3058 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 3059 } 3060 3061 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 3062 { 3063 struct am65_cpsw_host *host = am65_common_get_host(common); 3064 3065 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3066 3067 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 3068 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 3069 3070 /* learning make no sense in multi-mac mode */ 3071 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 3072 } 3073 3074 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 3075 struct devlink_param_gset_ctx *ctx) 3076 { 3077 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3078 struct am65_cpsw_common *common = dl_priv->common; 3079 3080 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 3081 3082 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3083 return -EOPNOTSUPP; 3084 3085 ctx->val.vbool = !common->is_emac_mode; 3086 3087 return 0; 3088 } 3089 3090 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 3091 { 3092 struct am65_cpsw_slave_data *slave = &port->slave; 3093 struct am65_cpsw_common *common = port->common; 3094 u32 port_mask; 3095 3096 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3097 3098 if (slave->mac_only) 3099 /* enable mac-only mode on port */ 3100 cpsw_ale_control_set(common->ale, port->port_id, 3101 ALE_PORT_MACONLY, 1); 3102 3103 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 3104 3105 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3106 3107 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 3108 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 3109 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 3110 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 3111 } 3112 3113 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 3114 { 3115 struct am65_cpsw_slave_data *slave = &port->slave; 3116 struct am65_cpsw_common *cpsw = port->common; 3117 u32 port_mask; 3118 3119 cpsw_ale_control_set(cpsw->ale, port->port_id, 3120 ALE_PORT_NOLEARN, 0); 3121 3122 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 3123 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 3124 slave->port_vlan); 3125 3126 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3127 3128 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 3129 port_mask, ALE_VLAN, slave->port_vlan, 3130 ALE_MCAST_FWD_2); 3131 3132 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3133 3134 cpsw_ale_control_set(cpsw->ale, port->port_id, 3135 ALE_PORT_MACONLY, 0); 3136 } 3137 3138 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 3139 struct devlink_param_gset_ctx *ctx, 3140 struct netlink_ext_ack *extack) 3141 { 3142 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3143 struct am65_cpsw_common *cpsw = dl_priv->common; 3144 bool switch_en = ctx->val.vbool; 3145 bool if_running = false; 3146 int i; 3147 3148 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 3149 3150 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3151 return -EOPNOTSUPP; 3152 3153 if (switch_en == !cpsw->is_emac_mode) 3154 return 0; 3155 3156 if (!switch_en && cpsw->br_members) { 3157 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 3158 return -EINVAL; 3159 } 3160 3161 rtnl_lock(); 3162 3163 cpsw->is_emac_mode = !switch_en; 3164 3165 for (i = 0; i < cpsw->port_num; i++) { 3166 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3167 3168 if (!sl_ndev || !netif_running(sl_ndev)) 3169 continue; 3170 3171 if_running = true; 3172 } 3173 3174 if (!if_running) { 3175 /* all ndevs are down */ 3176 for (i = 0; i < cpsw->port_num; i++) { 3177 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3178 struct am65_cpsw_slave_data *slave; 3179 3180 if (!sl_ndev) 3181 continue; 3182 3183 slave = am65_ndev_to_slave(sl_ndev); 3184 if (switch_en) 3185 slave->port_vlan = cpsw->default_vlan; 3186 else 3187 slave->port_vlan = 0; 3188 } 3189 3190 goto exit; 3191 } 3192 3193 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 3194 /* clean up ALE table */ 3195 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 3196 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 3197 3198 if (switch_en) { 3199 dev_info(cpsw->dev, "Enable switch mode\n"); 3200 3201 am65_cpsw_init_host_port_switch(cpsw); 3202 3203 for (i = 0; i < cpsw->port_num; i++) { 3204 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3205 struct am65_cpsw_slave_data *slave; 3206 struct am65_cpsw_port *port; 3207 3208 if (!sl_ndev) 3209 continue; 3210 3211 port = am65_ndev_to_port(sl_ndev); 3212 slave = am65_ndev_to_slave(sl_ndev); 3213 slave->port_vlan = cpsw->default_vlan; 3214 3215 if (netif_running(sl_ndev)) 3216 am65_cpsw_init_port_switch_ale(port); 3217 } 3218 3219 } else { 3220 dev_info(cpsw->dev, "Disable switch mode\n"); 3221 3222 am65_cpsw_init_host_port_emac(cpsw); 3223 3224 for (i = 0; i < cpsw->port_num; i++) { 3225 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3226 struct am65_cpsw_port *port; 3227 3228 if (!sl_ndev) 3229 continue; 3230 3231 port = am65_ndev_to_port(sl_ndev); 3232 port->slave.port_vlan = 0; 3233 if (netif_running(sl_ndev)) 3234 am65_cpsw_init_port_emac_ale(port); 3235 } 3236 } 3237 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 3238 exit: 3239 rtnl_unlock(); 3240 3241 return 0; 3242 } 3243 3244 static const struct devlink_param am65_cpsw_devlink_params[] = { 3245 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 3246 DEVLINK_PARAM_TYPE_BOOL, 3247 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3248 am65_cpsw_dl_switch_mode_get, 3249 am65_cpsw_dl_switch_mode_set, NULL), 3250 }; 3251 3252 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 3253 { 3254 struct devlink_port_attrs attrs = {}; 3255 struct am65_cpsw_devlink *dl_priv; 3256 struct device *dev = common->dev; 3257 struct devlink_port *dl_port; 3258 struct am65_cpsw_port *port; 3259 int ret = 0; 3260 int i; 3261 3262 common->devlink = 3263 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 3264 if (!common->devlink) 3265 return -ENOMEM; 3266 3267 dl_priv = devlink_priv(common->devlink); 3268 dl_priv->common = common; 3269 3270 /* Provide devlink hook to switch mode when multiple external ports 3271 * are present NUSS switchdev driver is enabled. 3272 */ 3273 if (!AM65_CPSW_IS_CPSW2G(common) && 3274 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 3275 ret = devlink_params_register(common->devlink, 3276 am65_cpsw_devlink_params, 3277 ARRAY_SIZE(am65_cpsw_devlink_params)); 3278 if (ret) { 3279 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 3280 goto dl_unreg; 3281 } 3282 } 3283 3284 for (i = 1; i <= common->port_num; i++) { 3285 port = am65_common_get_port(common, i); 3286 dl_port = &port->devlink_port; 3287 3288 if (port->ndev) 3289 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 3290 else 3291 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 3292 attrs.phys.port_number = port->port_id; 3293 attrs.switch_id.id_len = sizeof(resource_size_t); 3294 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 3295 devlink_port_attrs_set(dl_port, &attrs); 3296 3297 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 3298 if (ret) { 3299 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 3300 port->port_id, ret); 3301 goto dl_port_unreg; 3302 } 3303 } 3304 devlink_register(common->devlink); 3305 return ret; 3306 3307 dl_port_unreg: 3308 for (i = i - 1; i >= 1; i--) { 3309 port = am65_common_get_port(common, i); 3310 dl_port = &port->devlink_port; 3311 3312 devlink_port_unregister(dl_port); 3313 } 3314 dl_unreg: 3315 devlink_free(common->devlink); 3316 return ret; 3317 } 3318 3319 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 3320 { 3321 struct devlink_port *dl_port; 3322 struct am65_cpsw_port *port; 3323 int i; 3324 3325 devlink_unregister(common->devlink); 3326 3327 for (i = 1; i <= common->port_num; i++) { 3328 port = am65_common_get_port(common, i); 3329 dl_port = &port->devlink_port; 3330 3331 devlink_port_unregister(dl_port); 3332 } 3333 3334 if (!AM65_CPSW_IS_CPSW2G(common) && 3335 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3336 devlink_params_unregister(common->devlink, 3337 am65_cpsw_devlink_params, 3338 ARRAY_SIZE(am65_cpsw_devlink_params)); 3339 3340 devlink_free(common->devlink); 3341 } 3342 3343 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 3344 { 3345 struct am65_cpsw_rx_chn *rx_chan = &common->rx_chns; 3346 struct am65_cpsw_tx_chn *tx_chan = common->tx_chns; 3347 struct device *dev = common->dev; 3348 struct am65_cpsw_port *port; 3349 int ret = 0, i; 3350 3351 /* init tx channels */ 3352 ret = am65_cpsw_nuss_init_tx_chns(common); 3353 if (ret) 3354 return ret; 3355 ret = am65_cpsw_nuss_init_rx_chns(common); 3356 if (ret) 3357 goto err_remove_tx; 3358 3359 /* The DMA Channels are not guaranteed to be in a clean state. 3360 * Reset and disable them to ensure that they are back to the 3361 * clean state and ready to be used. 3362 */ 3363 for (i = 0; i < common->tx_ch_num; i++) { 3364 k3_udma_glue_reset_tx_chn(tx_chan[i].tx_chn, &tx_chan[i], 3365 am65_cpsw_nuss_tx_cleanup); 3366 k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); 3367 } 3368 3369 for (i = 0; i < common->rx_ch_num_flows; i++) 3370 k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, 3371 rx_chan, 3372 am65_cpsw_nuss_rx_cleanup); 3373 3374 k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); 3375 3376 ret = am65_cpsw_nuss_register_devlink(common); 3377 if (ret) 3378 goto err_remove_rx; 3379 3380 for (i = 0; i < common->port_num; i++) { 3381 port = &common->ports[i]; 3382 3383 if (!port->ndev) 3384 continue; 3385 3386 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 3387 3388 ret = register_netdev(port->ndev); 3389 if (ret) { 3390 dev_err(dev, "error registering slave net device%i %d\n", 3391 i, ret); 3392 goto err_cleanup_ndev; 3393 } 3394 } 3395 3396 ret = am65_cpsw_register_notifiers(common); 3397 if (ret) 3398 goto err_cleanup_ndev; 3399 3400 /* can't auto unregister ndev using devm_add_action() due to 3401 * devres release sequence in DD core for DMA 3402 */ 3403 3404 return 0; 3405 3406 err_cleanup_ndev: 3407 am65_cpsw_nuss_cleanup_ndev(common); 3408 am65_cpsw_unregister_devlink(common); 3409 err_remove_rx: 3410 am65_cpsw_nuss_remove_rx_chns(common); 3411 err_remove_tx: 3412 am65_cpsw_nuss_remove_tx_chns(common); 3413 3414 return ret; 3415 } 3416 3417 int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, 3418 int num_tx, int num_rx) 3419 { 3420 int ret; 3421 3422 am65_cpsw_nuss_remove_tx_chns(common); 3423 am65_cpsw_nuss_remove_rx_chns(common); 3424 3425 common->tx_ch_num = num_tx; 3426 common->rx_ch_num_flows = num_rx; 3427 ret = am65_cpsw_nuss_init_tx_chns(common); 3428 if (ret) 3429 return ret; 3430 3431 ret = am65_cpsw_nuss_init_rx_chns(common); 3432 if (ret) 3433 am65_cpsw_nuss_remove_tx_chns(common); 3434 3435 return ret; 3436 } 3437 3438 struct am65_cpsw_soc_pdata { 3439 u32 quirks_dis; 3440 }; 3441 3442 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 3443 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3444 }; 3445 3446 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 3447 { .family = "AM65X", 3448 .revision = "SR2.0", 3449 .data = &am65x_soc_sr2_0 3450 }, 3451 {/* sentinel */} 3452 }; 3453 3454 static const struct am65_cpsw_pdata am65x_sr1_0 = { 3455 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3456 .ale_dev_id = "am65x-cpsw2g", 3457 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3458 }; 3459 3460 static const struct am65_cpsw_pdata j721e_pdata = { 3461 .quirks = 0, 3462 .ale_dev_id = "am65x-cpsw2g", 3463 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3464 }; 3465 3466 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 3467 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 3468 .ale_dev_id = "am64-cpswxg", 3469 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3470 }; 3471 3472 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 3473 .quirks = 0, 3474 .ale_dev_id = "am64-cpswxg", 3475 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3476 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3477 BIT(PHY_INTERFACE_MODE_USXGMII), 3478 }; 3479 3480 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 3481 .quirks = 0, 3482 .ale_dev_id = "am64-cpswxg", 3483 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3484 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3485 }; 3486 3487 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 3488 .quirks = 0, 3489 .ale_dev_id = "am64-cpswxg", 3490 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3491 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3492 BIT(PHY_INTERFACE_MODE_USXGMII), 3493 }; 3494 3495 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 3496 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 3497 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 3498 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 3499 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 3500 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 3501 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 3502 { /* sentinel */ }, 3503 }; 3504 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 3505 3506 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 3507 { 3508 const struct soc_device_attribute *soc; 3509 3510 soc = soc_device_match(am65_cpsw_socinfo); 3511 if (soc && soc->data) { 3512 const struct am65_cpsw_soc_pdata *socdata = soc->data; 3513 3514 /* disable quirks */ 3515 common->pdata.quirks &= ~socdata->quirks_dis; 3516 } 3517 } 3518 3519 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 3520 { 3521 struct cpsw_ale_params ale_params = { 0 }; 3522 const struct of_device_id *of_id; 3523 struct device *dev = &pdev->dev; 3524 struct am65_cpsw_common *common; 3525 struct device_node *node; 3526 struct resource *res; 3527 struct clk *clk; 3528 int ale_entries; 3529 __be64 id_temp; 3530 int ret, i; 3531 3532 BUILD_BUG_ON_MSG(sizeof(struct am65_cpsw_tx_swdata) > AM65_CPSW_NAV_SW_DATA_SIZE, 3533 "TX SW_DATA size exceeds AM65_CPSW_NAV_SW_DATA_SIZE"); 3534 BUILD_BUG_ON_MSG(sizeof(struct am65_cpsw_swdata) > AM65_CPSW_NAV_SW_DATA_SIZE, 3535 "SW_DATA size exceeds AM65_CPSW_NAV_SW_DATA_SIZE"); 3536 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 3537 if (!common) 3538 return -ENOMEM; 3539 common->dev = dev; 3540 3541 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 3542 if (!of_id) 3543 return -EINVAL; 3544 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 3545 3546 am65_cpsw_nuss_apply_socinfo(common); 3547 3548 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 3549 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 3550 if (IS_ERR(common->ss_base)) 3551 return PTR_ERR(common->ss_base); 3552 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 3553 /* Use device's physical base address as switch id */ 3554 id_temp = cpu_to_be64(res->start); 3555 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 3556 3557 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 3558 if (!node) 3559 return -ENOENT; 3560 common->port_num = of_get_child_count(node); 3561 of_node_put(node); 3562 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 3563 return -ENOENT; 3564 3565 common->rx_flow_id_base = -1; 3566 init_completion(&common->tdown_complete); 3567 common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; 3568 common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; 3569 common->pf_p0_rx_ptype_rrobin = true; 3570 common->default_vlan = 1; 3571 3572 common->ports = devm_kcalloc(dev, common->port_num, 3573 sizeof(*common->ports), 3574 GFP_KERNEL); 3575 if (!common->ports) 3576 return -ENOMEM; 3577 3578 clk = devm_clk_get(dev, "fck"); 3579 if (IS_ERR(clk)) 3580 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 3581 common->bus_freq = clk_get_rate(clk); 3582 3583 pm_runtime_enable(dev); 3584 ret = pm_runtime_resume_and_get(dev); 3585 if (ret < 0) { 3586 pm_runtime_disable(dev); 3587 return ret; 3588 } 3589 3590 am65_cpsw_nuss_get_ver(common); 3591 3592 ret = am65_cpsw_nuss_init_host_p(common); 3593 if (ret) 3594 goto err_pm_clear; 3595 3596 ret = am65_cpsw_nuss_init_slave_ports(common); 3597 if (ret) 3598 goto err_pm_clear; 3599 3600 node = of_get_child_by_name(dev->of_node, "mdio"); 3601 if (!node) { 3602 dev_warn(dev, "MDIO node not found\n"); 3603 } else if (of_device_is_available(node)) { 3604 struct platform_device *mdio_pdev; 3605 3606 mdio_pdev = of_platform_device_create(node, NULL, dev); 3607 if (!mdio_pdev) { 3608 ret = -ENODEV; 3609 goto err_pm_clear; 3610 } 3611 3612 common->mdio_dev = &mdio_pdev->dev; 3613 } 3614 of_node_put(node); 3615 3616 /* init common data */ 3617 ale_params.dev = dev; 3618 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 3619 ale_params.ale_ports = common->port_num + 1; 3620 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 3621 ale_params.dev_id = common->pdata.ale_dev_id; 3622 ale_params.bus_freq = common->bus_freq; 3623 3624 common->ale = cpsw_ale_create(&ale_params); 3625 if (IS_ERR(common->ale)) { 3626 dev_err(dev, "error initializing ale engine\n"); 3627 ret = PTR_ERR(common->ale); 3628 goto err_of_clear; 3629 } 3630 3631 ale_entries = common->ale->params.ale_entries; 3632 common->ale_context = devm_kzalloc(dev, 3633 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 3634 GFP_KERNEL); 3635 ret = am65_cpsw_init_cpts(common); 3636 if (ret) 3637 goto err_of_clear; 3638 3639 /* init ports */ 3640 for (i = 0; i < common->port_num; i++) 3641 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 3642 3643 dev_set_drvdata(dev, common); 3644 3645 common->is_emac_mode = true; 3646 3647 ret = am65_cpsw_nuss_init_ndevs(common); 3648 if (ret) 3649 goto err_ndevs_clear; 3650 3651 ret = am65_cpsw_nuss_register_ndevs(common); 3652 if (ret) 3653 goto err_ndevs_clear; 3654 3655 pm_runtime_put(dev); 3656 return 0; 3657 3658 err_ndevs_clear: 3659 am65_cpsw_nuss_cleanup_ndev(common); 3660 am65_cpsw_nuss_phylink_cleanup(common); 3661 am65_cpts_release(common->cpts); 3662 am65_cpsw_remove_dt(common); 3663 err_of_clear: 3664 if (common->mdio_dev) 3665 of_platform_device_destroy(common->mdio_dev, NULL); 3666 err_pm_clear: 3667 pm_runtime_put_sync(dev); 3668 pm_runtime_disable(dev); 3669 return ret; 3670 } 3671 3672 static void am65_cpsw_nuss_remove(struct platform_device *pdev) 3673 { 3674 struct device *dev = &pdev->dev; 3675 struct am65_cpsw_common *common; 3676 int ret; 3677 3678 common = dev_get_drvdata(dev); 3679 3680 ret = pm_runtime_resume_and_get(&pdev->dev); 3681 if (ret < 0) { 3682 /* Note, if this error path is taken, we're leaking some 3683 * resources. 3684 */ 3685 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", 3686 ERR_PTR(ret)); 3687 return; 3688 } 3689 3690 am65_cpsw_unregister_notifiers(common); 3691 3692 /* must unregister ndevs here because DD release_driver routine calls 3693 * dma_deconfigure(dev) before devres_release_all(dev) 3694 */ 3695 am65_cpsw_nuss_cleanup_ndev(common); 3696 am65_cpsw_unregister_devlink(common); 3697 am65_cpsw_nuss_remove_rx_chns(common); 3698 am65_cpsw_nuss_remove_tx_chns(common); 3699 am65_cpsw_nuss_phylink_cleanup(common); 3700 am65_cpts_release(common->cpts); 3701 am65_cpsw_disable_serdes_phy(common); 3702 am65_cpsw_remove_dt(common); 3703 3704 if (common->mdio_dev) 3705 of_platform_device_destroy(common->mdio_dev, NULL); 3706 3707 pm_runtime_put_sync(&pdev->dev); 3708 pm_runtime_disable(&pdev->dev); 3709 } 3710 3711 static int am65_cpsw_nuss_suspend(struct device *dev) 3712 { 3713 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3714 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3715 struct am65_cpsw_port *port; 3716 struct net_device *ndev; 3717 int i, ret; 3718 3719 cpsw_ale_dump(common->ale, common->ale_context); 3720 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3721 for (i = 0; i < common->port_num; i++) { 3722 port = &common->ports[i]; 3723 ndev = port->ndev; 3724 3725 if (!ndev) 3726 continue; 3727 3728 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3729 netif_device_detach(ndev); 3730 if (netif_running(ndev)) { 3731 rtnl_lock(); 3732 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3733 rtnl_unlock(); 3734 if (ret < 0) { 3735 netdev_err(ndev, "failed to stop: %d", ret); 3736 return ret; 3737 } 3738 } 3739 } 3740 3741 am65_cpts_suspend(common->cpts); 3742 3743 am65_cpsw_nuss_remove_rx_chns(common); 3744 am65_cpsw_nuss_remove_tx_chns(common); 3745 3746 return 0; 3747 } 3748 3749 static int am65_cpsw_nuss_resume(struct device *dev) 3750 { 3751 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3752 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3753 struct am65_cpsw_port *port; 3754 struct net_device *ndev; 3755 int i, ret; 3756 3757 ret = am65_cpsw_nuss_init_tx_chns(common); 3758 if (ret) 3759 return ret; 3760 ret = am65_cpsw_nuss_init_rx_chns(common); 3761 if (ret) { 3762 am65_cpsw_nuss_remove_tx_chns(common); 3763 return ret; 3764 } 3765 3766 /* If RX IRQ was disabled before suspend, keep it disabled */ 3767 for (i = 0; i < common->rx_ch_num_flows; i++) { 3768 if (common->rx_chns.flows[i].irq_disabled) 3769 disable_irq(common->rx_chns.flows[i].irq); 3770 } 3771 3772 am65_cpts_resume(common->cpts); 3773 3774 for (i = 0; i < common->port_num; i++) { 3775 port = &common->ports[i]; 3776 ndev = port->ndev; 3777 3778 if (!ndev) 3779 continue; 3780 3781 if (netif_running(ndev)) { 3782 rtnl_lock(); 3783 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3784 rtnl_unlock(); 3785 if (ret < 0) { 3786 netdev_err(ndev, "failed to start: %d", ret); 3787 return ret; 3788 } 3789 } 3790 3791 netif_device_attach(ndev); 3792 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3793 } 3794 3795 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3796 cpsw_ale_restore(common->ale, common->ale_context); 3797 3798 return 0; 3799 } 3800 3801 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3802 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3803 }; 3804 3805 static struct platform_driver am65_cpsw_nuss_driver = { 3806 .driver = { 3807 .name = AM65_CPSW_DRV_NAME, 3808 .of_match_table = am65_cpsw_nuss_of_mtable, 3809 .pm = &am65_cpsw_nuss_dev_pm_ops, 3810 }, 3811 .probe = am65_cpsw_nuss_probe, 3812 .remove = am65_cpsw_nuss_remove, 3813 }; 3814 3815 module_platform_driver(am65_cpsw_nuss_driver); 3816 3817 MODULE_LICENSE("GPL v2"); 3818 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3819 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3820