1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/etherdevice.h> 9 #include <linux/if_vlan.h> 10 #include <linux/interrupt.h> 11 #include <linux/kernel.h> 12 #include <linux/kmemleak.h> 13 #include <linux/module.h> 14 #include <linux/netdevice.h> 15 #include <linux/net_tstamp.h> 16 #include <linux/of.h> 17 #include <linux/of_mdio.h> 18 #include <linux/of_net.h> 19 #include <linux/of_device.h> 20 #include <linux/phy.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/regmap.h> 25 #include <linux/mfd/syscon.h> 26 #include <linux/dma/ti-cppi5.h> 27 #include <linux/dma/k3-udma-glue.h> 28 29 #include "cpsw_ale.h" 30 #include "cpsw_sl.h" 31 #include "am65-cpsw-nuss.h" 32 #include "k3-cppi-desc-pool.h" 33 #include "am65-cpts.h" 34 35 #define AM65_CPSW_SS_BASE 0x0 36 #define AM65_CPSW_SGMII_BASE 0x100 37 #define AM65_CPSW_XGMII_BASE 0x2100 38 #define AM65_CPSW_CPSW_NU_BASE 0x20000 39 #define AM65_CPSW_NU_PORTS_BASE 0x1000 40 #define AM65_CPSW_NU_STATS_BASE 0x1a000 41 #define AM65_CPSW_NU_ALE_BASE 0x1e000 42 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 43 44 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 45 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 46 47 #define AM65_CPSW_MAX_PORTS 8 48 49 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 50 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 51 52 #define AM65_CPSW_REG_CTL 0x004 53 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 54 #define AM65_CPSW_REG_PTYPE 0x018 55 56 #define AM65_CPSW_P0_REG_CTL 0x004 57 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 58 59 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 60 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 61 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 62 63 #define AM65_CPSW_PORTN_REG_SA_L 0x308 64 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 65 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 66 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 67 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 68 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 69 70 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 71 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 72 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 73 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 74 75 /* AM65_CPSW_P0_REG_CTL */ 76 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 77 78 /* AM65_CPSW_PORT_REG_PRI_CTL */ 79 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 80 81 /* AM65_CPSW_PN_TS_CTL register fields */ 82 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 83 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 84 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 85 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 86 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 87 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 88 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 89 90 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 91 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 92 93 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 94 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 95 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 96 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 97 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 98 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 99 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 102 103 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 104 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 105 106 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 107 108 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 109 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 110 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 111 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 112 113 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 114 /* Number of TX/RX descriptors */ 115 #define AM65_CPSW_MAX_TX_DESC 500 116 #define AM65_CPSW_MAX_RX_DESC 500 117 118 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 119 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 120 121 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 122 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 123 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 124 125 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 126 const u8 *dev_addr) 127 { 128 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 129 (dev_addr[2] << 16) | (dev_addr[3] << 24); 130 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 131 132 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 133 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 134 } 135 136 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 137 { 138 cpsw_sl_reset(port->slave.mac_sl, 100); 139 /* Max length register has to be restored after MAC SL reset */ 140 writel(AM65_CPSW_MAX_PACKET_SIZE, 141 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 142 } 143 144 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 145 { 146 common->nuss_ver = readl(common->ss_base); 147 common->cpsw_ver = readl(common->cpsw_base); 148 dev_info(common->dev, 149 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u\n", 150 common->nuss_ver, 151 common->cpsw_ver, 152 common->port_num + 1); 153 } 154 155 void am65_cpsw_nuss_adjust_link(struct net_device *ndev) 156 { 157 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 158 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 159 struct phy_device *phy = port->slave.phy; 160 u32 mac_control = 0; 161 162 if (!phy) 163 return; 164 165 if (phy->link) { 166 mac_control = CPSW_SL_CTL_GMII_EN; 167 168 if (phy->speed == 1000) 169 mac_control |= CPSW_SL_CTL_GIG; 170 if (phy->speed == 10 && phy_interface_is_rgmii(phy)) 171 /* Can be used with in band mode only */ 172 mac_control |= CPSW_SL_CTL_EXT_EN; 173 if (phy->duplex) 174 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 175 176 /* RGMII speed is 100M if !CPSW_SL_CTL_GIG*/ 177 178 /* rx_pause/tx_pause */ 179 if (port->slave.rx_pause) 180 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 181 182 if (port->slave.tx_pause) 183 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 184 185 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 186 187 /* enable forwarding */ 188 cpsw_ale_control_set(common->ale, port->port_id, 189 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 190 191 netif_tx_wake_all_queues(ndev); 192 } else { 193 int tmo; 194 /* disable forwarding */ 195 cpsw_ale_control_set(common->ale, port->port_id, 196 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 197 198 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 199 200 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 201 dev_dbg(common->dev, "donw msc_sl %08x tmo %d\n", 202 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), 203 tmo); 204 205 cpsw_sl_ctl_reset(port->slave.mac_sl); 206 207 netif_tx_stop_all_queues(ndev); 208 } 209 210 phy_print_status(phy); 211 } 212 213 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 214 __be16 proto, u16 vid) 215 { 216 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 217 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 218 u32 port_mask, unreg_mcast = 0; 219 int ret; 220 221 ret = pm_runtime_get_sync(common->dev); 222 if (ret < 0) { 223 pm_runtime_put_noidle(common->dev); 224 return ret; 225 } 226 227 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 228 if (!vid) 229 unreg_mcast = port_mask; 230 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 231 ret = cpsw_ale_add_vlan(common->ale, vid, port_mask, 232 unreg_mcast, port_mask, 0); 233 234 pm_runtime_put(common->dev); 235 return ret; 236 } 237 238 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 239 __be16 proto, u16 vid) 240 { 241 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 242 int ret; 243 244 ret = pm_runtime_get_sync(common->dev); 245 if (ret < 0) { 246 pm_runtime_put_noidle(common->dev); 247 return ret; 248 } 249 250 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 251 ret = cpsw_ale_del_vlan(common->ale, vid, 0); 252 253 pm_runtime_put(common->dev); 254 return ret; 255 } 256 257 static void am65_cpsw_slave_set_promisc_2g(struct am65_cpsw_port *port, 258 bool promisc) 259 { 260 struct am65_cpsw_common *common = port->common; 261 262 if (promisc) { 263 /* Enable promiscuous mode */ 264 cpsw_ale_control_set(common->ale, port->port_id, 265 ALE_PORT_MACONLY_CAF, 1); 266 dev_dbg(common->dev, "promisc enabled\n"); 267 } else { 268 /* Disable promiscuous mode */ 269 cpsw_ale_control_set(common->ale, port->port_id, 270 ALE_PORT_MACONLY_CAF, 0); 271 dev_dbg(common->dev, "promisc disabled\n"); 272 } 273 } 274 275 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 276 { 277 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 278 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 279 u32 port_mask; 280 bool promisc; 281 282 promisc = !!(ndev->flags & IFF_PROMISC); 283 am65_cpsw_slave_set_promisc_2g(port, promisc); 284 285 if (promisc) 286 return; 287 288 /* Restore allmulti on vlans if necessary */ 289 cpsw_ale_set_allmulti(common->ale, 290 ndev->flags & IFF_ALLMULTI, port->port_id); 291 292 port_mask = ALE_PORT_HOST; 293 /* Clear all mcast from ALE */ 294 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 295 296 if (!netdev_mc_empty(ndev)) { 297 struct netdev_hw_addr *ha; 298 299 /* program multicast address list into ALE register */ 300 netdev_for_each_mc_addr(ha, ndev) { 301 cpsw_ale_add_mcast(common->ale, ha->addr, 302 port_mask, 0, 0, 0); 303 } 304 } 305 } 306 307 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 308 unsigned int txqueue) 309 { 310 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 311 struct am65_cpsw_tx_chn *tx_chn; 312 struct netdev_queue *netif_txq; 313 unsigned long trans_start; 314 315 netif_txq = netdev_get_tx_queue(ndev, txqueue); 316 tx_chn = &common->tx_chns[txqueue]; 317 trans_start = netif_txq->trans_start; 318 319 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 320 txqueue, 321 netif_tx_queue_stopped(netif_txq), 322 jiffies_to_msecs(jiffies - trans_start), 323 dql_avail(&netif_txq->dql), 324 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 325 326 if (netif_tx_queue_stopped(netif_txq)) { 327 /* try recover if stopped by us */ 328 txq_trans_update(netif_txq); 329 netif_tx_wake_queue(netif_txq); 330 } 331 } 332 333 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 334 struct sk_buff *skb) 335 { 336 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 337 struct cppi5_host_desc_t *desc_rx; 338 struct device *dev = common->dev; 339 u32 pkt_len = skb_tailroom(skb); 340 dma_addr_t desc_dma; 341 dma_addr_t buf_dma; 342 void *swdata; 343 344 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 345 if (!desc_rx) { 346 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 347 return -ENOMEM; 348 } 349 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 350 351 buf_dma = dma_map_single(dev, skb->data, pkt_len, DMA_FROM_DEVICE); 352 if (unlikely(dma_mapping_error(dev, buf_dma))) { 353 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 354 dev_err(dev, "Failed to map rx skb buffer\n"); 355 return -EINVAL; 356 } 357 358 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 359 AM65_CPSW_NAV_PS_DATA_SIZE); 360 cppi5_hdesc_attach_buf(desc_rx, 0, 0, buf_dma, skb_tailroom(skb)); 361 swdata = cppi5_hdesc_get_swdata(desc_rx); 362 *((void **)swdata) = skb; 363 364 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 365 } 366 367 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 368 { 369 struct am65_cpsw_host *host_p = am65_common_get_host(common); 370 u32 val, pri_map; 371 372 /* P0 set Receive Priority Type */ 373 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 374 375 if (common->pf_p0_rx_ptype_rrobin) { 376 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 377 /* Enet Ports fifos works in fixed priority mode only, so 378 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 379 */ 380 pri_map = 0x0; 381 } else { 382 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 383 /* restore P0_Rx_Pri_Map */ 384 pri_map = 0x76543210; 385 } 386 387 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 388 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 389 } 390 391 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common, 392 netdev_features_t features) 393 { 394 struct am65_cpsw_host *host_p = am65_common_get_host(common); 395 int port_idx, i, ret; 396 struct sk_buff *skb; 397 u32 val, port_mask; 398 399 if (common->usage_count) 400 return 0; 401 402 /* Control register */ 403 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 404 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 405 common->cpsw_base + AM65_CPSW_REG_CTL); 406 /* Max length register */ 407 writel(AM65_CPSW_MAX_PACKET_SIZE, 408 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 409 /* set base flow_id */ 410 writel(common->rx_flow_id_base, 411 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 412 /* en tx crc offload */ 413 if (features & NETIF_F_HW_CSUM) 414 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, 415 host_p->port_base + AM65_CPSW_P0_REG_CTL); 416 417 am65_cpsw_nuss_set_p0_ptype(common); 418 419 /* enable statistic */ 420 val = BIT(HOST_PORT_NUM); 421 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 422 struct am65_cpsw_port *port = &common->ports[port_idx]; 423 424 if (!port->disabled) 425 val |= BIT(port->port_id); 426 } 427 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 428 429 /* disable priority elevation */ 430 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 431 432 cpsw_ale_start(common->ale); 433 434 /* limit to one RX flow only */ 435 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 436 ALE_DEFAULT_THREAD_ID, 0); 437 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 438 ALE_DEFAULT_THREAD_ENABLE, 1); 439 if (AM65_CPSW_IS_CPSW2G(common)) 440 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 441 ALE_PORT_NOLEARN, 1); 442 /* switch to vlan unaware mode */ 443 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 444 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 445 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 446 447 /* default vlan cfg: create mask based on enabled ports */ 448 port_mask = GENMASK(common->port_num, 0) & 449 ~common->disabled_ports_mask; 450 451 cpsw_ale_add_vlan(common->ale, 0, port_mask, 452 port_mask, port_mask, 453 port_mask & ~ALE_PORT_HOST); 454 455 for (i = 0; i < common->rx_chns.descs_num; i++) { 456 skb = __netdev_alloc_skb_ip_align(NULL, 457 AM65_CPSW_MAX_PACKET_SIZE, 458 GFP_KERNEL); 459 if (!skb) { 460 dev_err(common->dev, "cannot allocate skb\n"); 461 return -ENOMEM; 462 } 463 464 ret = am65_cpsw_nuss_rx_push(common, skb); 465 if (ret < 0) { 466 dev_err(common->dev, 467 "cannot submit skb to channel rx, error %d\n", 468 ret); 469 kfree_skb(skb); 470 return ret; 471 } 472 kmemleak_not_leak(skb); 473 } 474 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 475 476 for (i = 0; i < common->tx_ch_num; i++) { 477 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 478 if (ret) 479 return ret; 480 napi_enable(&common->tx_chns[i].napi_tx); 481 } 482 483 napi_enable(&common->napi_rx); 484 485 dev_dbg(common->dev, "cpsw_nuss started\n"); 486 return 0; 487 } 488 489 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 490 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 491 492 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 493 { 494 int i; 495 496 if (common->usage_count != 1) 497 return 0; 498 499 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 500 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 501 502 /* shutdown tx channels */ 503 atomic_set(&common->tdown_cnt, common->tx_ch_num); 504 /* ensure new tdown_cnt value is visible */ 505 smp_mb__after_atomic(); 506 reinit_completion(&common->tdown_complete); 507 508 for (i = 0; i < common->tx_ch_num; i++) 509 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 510 511 i = wait_for_completion_timeout(&common->tdown_complete, 512 msecs_to_jiffies(1000)); 513 if (!i) 514 dev_err(common->dev, "tx timeout\n"); 515 for (i = 0; i < common->tx_ch_num; i++) 516 napi_disable(&common->tx_chns[i].napi_tx); 517 518 for (i = 0; i < common->tx_ch_num; i++) { 519 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 520 &common->tx_chns[i], 521 am65_cpsw_nuss_tx_cleanup); 522 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 523 } 524 525 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 526 napi_disable(&common->napi_rx); 527 528 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 529 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 530 &common->rx_chns, 531 am65_cpsw_nuss_rx_cleanup, !!i); 532 533 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 534 535 cpsw_ale_stop(common->ale); 536 537 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 538 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 539 540 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 541 return 0; 542 } 543 544 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 545 { 546 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 547 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 548 int ret; 549 550 if (port->slave.phy) 551 phy_stop(port->slave.phy); 552 553 netif_tx_stop_all_queues(ndev); 554 555 if (port->slave.phy) { 556 phy_disconnect(port->slave.phy); 557 port->slave.phy = NULL; 558 } 559 560 ret = am65_cpsw_nuss_common_stop(common); 561 if (ret) 562 return ret; 563 564 common->usage_count--; 565 pm_runtime_put(common->dev); 566 return 0; 567 } 568 569 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 570 { 571 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 572 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 573 u32 port_mask; 574 int ret, i; 575 576 ret = pm_runtime_get_sync(common->dev); 577 if (ret < 0) { 578 pm_runtime_put_noidle(common->dev); 579 return ret; 580 } 581 582 /* Notify the stack of the actual queue counts. */ 583 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 584 if (ret) { 585 dev_err(common->dev, "cannot set real number of tx queues\n"); 586 return ret; 587 } 588 589 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 590 if (ret) { 591 dev_err(common->dev, "cannot set real number of rx queues\n"); 592 return ret; 593 } 594 595 for (i = 0; i < common->tx_ch_num; i++) 596 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 597 598 ret = am65_cpsw_nuss_common_open(common, ndev->features); 599 if (ret) 600 return ret; 601 602 common->usage_count++; 603 604 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 605 606 if (port->slave.mac_only) 607 /* enable mac-only mode on port */ 608 cpsw_ale_control_set(common->ale, port->port_id, 609 ALE_PORT_MACONLY, 1); 610 if (AM65_CPSW_IS_CPSW2G(common)) 611 cpsw_ale_control_set(common->ale, port->port_id, 612 ALE_PORT_NOLEARN, 1); 613 614 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 615 cpsw_ale_add_ucast(common->ale, ndev->dev_addr, 616 HOST_PORT_NUM, ALE_SECURE, 0); 617 cpsw_ale_add_mcast(common->ale, ndev->broadcast, 618 port_mask, 0, 0, ALE_MCAST_FWD_2); 619 620 /* mac_sl should be configured via phy-link interface */ 621 am65_cpsw_sl_ctl_reset(port); 622 623 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, 624 port->slave.phy_if); 625 if (ret) 626 goto error_cleanup; 627 628 if (port->slave.phy_node) { 629 port->slave.phy = of_phy_connect(ndev, 630 port->slave.phy_node, 631 &am65_cpsw_nuss_adjust_link, 632 0, port->slave.phy_if); 633 if (!port->slave.phy) { 634 dev_err(common->dev, "phy %pOF not found on slave %d\n", 635 port->slave.phy_node, 636 port->port_id); 637 ret = -ENODEV; 638 goto error_cleanup; 639 } 640 } 641 642 phy_attached_info(port->slave.phy); 643 phy_start(port->slave.phy); 644 645 return 0; 646 647 error_cleanup: 648 am65_cpsw_nuss_ndo_slave_stop(ndev); 649 return ret; 650 } 651 652 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 653 { 654 struct am65_cpsw_rx_chn *rx_chn = data; 655 struct cppi5_host_desc_t *desc_rx; 656 struct sk_buff *skb; 657 dma_addr_t buf_dma; 658 u32 buf_dma_len; 659 void **swdata; 660 661 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 662 swdata = cppi5_hdesc_get_swdata(desc_rx); 663 skb = *swdata; 664 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 665 666 dma_unmap_single(rx_chn->dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 667 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 668 669 dev_kfree_skb_any(skb); 670 } 671 672 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 673 { 674 struct skb_shared_hwtstamps *ssh; 675 u64 ns; 676 677 ns = ((u64)psdata[1] << 32) | psdata[0]; 678 679 ssh = skb_hwtstamps(skb); 680 memset(ssh, 0, sizeof(*ssh)); 681 ssh->hwtstamp = ns_to_ktime(ns); 682 } 683 684 /* RX psdata[2] word format - checksum information */ 685 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 686 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 687 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 688 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 689 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 690 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 691 692 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 693 { 694 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 695 * csum information provides in psdata[2] word: 696 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 697 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 698 * bits - indicates IPv4/IPv6 packet 699 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 700 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 701 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 702 */ 703 skb_checksum_none_assert(skb); 704 705 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 706 return; 707 708 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 709 AM65_CPSW_RX_PSD_IPV4_VALID)) && 710 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 711 /* csum for fragmented packets is unsupported */ 712 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 713 skb->ip_summed = CHECKSUM_UNNECESSARY; 714 } 715 } 716 717 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 718 u32 flow_idx) 719 { 720 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 721 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 722 struct am65_cpsw_ndev_priv *ndev_priv; 723 struct am65_cpsw_ndev_stats *stats; 724 struct cppi5_host_desc_t *desc_rx; 725 struct device *dev = common->dev; 726 struct sk_buff *skb, *new_skb; 727 dma_addr_t desc_dma, buf_dma; 728 struct am65_cpsw_port *port; 729 struct net_device *ndev; 730 void **swdata; 731 u32 *psdata; 732 int ret = 0; 733 734 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 735 if (ret) { 736 if (ret != -ENODATA) 737 dev_err(dev, "RX: pop chn fail %d\n", ret); 738 return ret; 739 } 740 741 if (desc_dma & 0x1) { 742 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 743 return 0; 744 } 745 746 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 747 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 748 __func__, flow_idx, &desc_dma); 749 750 swdata = cppi5_hdesc_get_swdata(desc_rx); 751 skb = *swdata; 752 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 753 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 754 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 755 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 756 port = am65_common_get_port(common, port_id); 757 ndev = port->ndev; 758 skb->dev = ndev; 759 760 psdata = cppi5_hdesc_get_psdata(desc_rx); 761 /* add RX timestamp */ 762 if (port->rx_ts_enabled) 763 am65_cpsw_nuss_rx_ts(skb, psdata); 764 csum_info = psdata[2]; 765 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 766 767 dma_unmap_single(dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 768 769 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 770 771 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 772 if (new_skb) { 773 skb_put(skb, pkt_len); 774 skb->protocol = eth_type_trans(skb, ndev); 775 am65_cpsw_nuss_rx_csum(skb, csum_info); 776 napi_gro_receive(&common->napi_rx, skb); 777 778 ndev_priv = netdev_priv(ndev); 779 stats = this_cpu_ptr(ndev_priv->stats); 780 781 u64_stats_update_begin(&stats->syncp); 782 stats->rx_packets++; 783 stats->rx_bytes += pkt_len; 784 u64_stats_update_end(&stats->syncp); 785 kmemleak_not_leak(new_skb); 786 } else { 787 ndev->stats.rx_dropped++; 788 new_skb = skb; 789 } 790 791 if (netif_dormant(ndev)) { 792 dev_kfree_skb_any(new_skb); 793 ndev->stats.rx_dropped++; 794 return 0; 795 } 796 797 ret = am65_cpsw_nuss_rx_push(common, new_skb); 798 if (WARN_ON(ret < 0)) { 799 dev_kfree_skb_any(new_skb); 800 ndev->stats.rx_errors++; 801 ndev->stats.rx_dropped++; 802 } 803 804 return ret; 805 } 806 807 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 808 { 809 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 810 int flow = AM65_CPSW_MAX_RX_FLOWS; 811 int cur_budget, ret; 812 int num_rx = 0; 813 814 /* process every flow */ 815 while (flow--) { 816 cur_budget = budget - num_rx; 817 818 while (cur_budget--) { 819 ret = am65_cpsw_nuss_rx_packets(common, flow); 820 if (ret) 821 break; 822 num_rx++; 823 } 824 825 if (num_rx >= budget) 826 break; 827 } 828 829 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 830 831 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) 832 enable_irq(common->rx_chns.irq); 833 834 return num_rx; 835 } 836 837 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 838 struct device *dev, 839 struct cppi5_host_desc_t *desc) 840 { 841 struct cppi5_host_desc_t *first_desc, *next_desc; 842 dma_addr_t buf_dma, next_desc_dma; 843 u32 buf_dma_len; 844 845 first_desc = desc; 846 next_desc = first_desc; 847 848 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 849 850 dma_unmap_single(dev, buf_dma, buf_dma_len, 851 DMA_TO_DEVICE); 852 853 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 854 while (next_desc_dma) { 855 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 856 next_desc_dma); 857 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 858 859 dma_unmap_page(dev, buf_dma, buf_dma_len, 860 DMA_TO_DEVICE); 861 862 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 863 864 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 865 } 866 867 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 868 } 869 870 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 871 { 872 struct am65_cpsw_tx_chn *tx_chn = data; 873 struct cppi5_host_desc_t *desc_tx; 874 struct sk_buff *skb; 875 void **swdata; 876 877 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 878 swdata = cppi5_hdesc_get_swdata(desc_tx); 879 skb = *(swdata); 880 am65_cpsw_nuss_xmit_free(tx_chn, tx_chn->common->dev, desc_tx); 881 882 dev_kfree_skb_any(skb); 883 } 884 885 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 886 int chn, unsigned int budget) 887 { 888 struct cppi5_host_desc_t *desc_tx; 889 struct device *dev = common->dev; 890 struct am65_cpsw_tx_chn *tx_chn; 891 struct netdev_queue *netif_txq; 892 unsigned int total_bytes = 0; 893 struct net_device *ndev; 894 struct sk_buff *skb; 895 dma_addr_t desc_dma; 896 int res, num_tx = 0; 897 void **swdata; 898 899 tx_chn = &common->tx_chns[chn]; 900 901 while (true) { 902 struct am65_cpsw_ndev_priv *ndev_priv; 903 struct am65_cpsw_ndev_stats *stats; 904 905 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 906 if (res == -ENODATA) 907 break; 908 909 if (desc_dma & 0x1) { 910 if (atomic_dec_and_test(&common->tdown_cnt)) 911 complete(&common->tdown_complete); 912 break; 913 } 914 915 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 916 desc_dma); 917 swdata = cppi5_hdesc_get_swdata(desc_tx); 918 skb = *(swdata); 919 am65_cpsw_nuss_xmit_free(tx_chn, dev, desc_tx); 920 921 ndev = skb->dev; 922 923 am65_cpts_tx_timestamp(common->cpts, skb); 924 925 ndev_priv = netdev_priv(ndev); 926 stats = this_cpu_ptr(ndev_priv->stats); 927 u64_stats_update_begin(&stats->syncp); 928 stats->tx_packets++; 929 stats->tx_bytes += skb->len; 930 u64_stats_update_end(&stats->syncp); 931 932 total_bytes += skb->len; 933 napi_consume_skb(skb, budget); 934 num_tx++; 935 } 936 937 if (!num_tx) 938 return 0; 939 940 netif_txq = netdev_get_tx_queue(ndev, chn); 941 942 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 943 944 if (netif_tx_queue_stopped(netif_txq)) { 945 /* Check whether the queue is stopped due to stalled tx dma, 946 * if the queue is stopped then wake the queue as 947 * we have free desc for tx 948 */ 949 __netif_tx_lock(netif_txq, smp_processor_id()); 950 if (netif_running(ndev) && 951 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 952 MAX_SKB_FRAGS)) 953 netif_tx_wake_queue(netif_txq); 954 955 __netif_tx_unlock(netif_txq); 956 } 957 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 958 959 return num_tx; 960 } 961 962 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 963 { 964 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 965 int num_tx; 966 967 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, 968 budget); 969 num_tx = min(num_tx, budget); 970 if (num_tx < budget) { 971 napi_complete(napi_tx); 972 enable_irq(tx_chn->irq); 973 } 974 975 return num_tx; 976 } 977 978 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 979 { 980 struct am65_cpsw_common *common = dev_id; 981 982 disable_irq_nosync(irq); 983 napi_schedule(&common->napi_rx); 984 985 return IRQ_HANDLED; 986 } 987 988 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 989 { 990 struct am65_cpsw_tx_chn *tx_chn = dev_id; 991 992 disable_irq_nosync(irq); 993 napi_schedule(&tx_chn->napi_tx); 994 995 return IRQ_HANDLED; 996 } 997 998 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 999 struct net_device *ndev) 1000 { 1001 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1002 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1003 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1004 struct device *dev = common->dev; 1005 struct am65_cpsw_tx_chn *tx_chn; 1006 struct netdev_queue *netif_txq; 1007 dma_addr_t desc_dma, buf_dma; 1008 int ret, q_idx, i; 1009 void **swdata; 1010 u32 *psdata; 1011 u32 pkt_len; 1012 1013 /* padding enabled in hw */ 1014 pkt_len = skb_headlen(skb); 1015 1016 /* SKB TX timestamp */ 1017 if (port->tx_ts_enabled) 1018 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1019 1020 q_idx = skb_get_queue_mapping(skb); 1021 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1022 1023 tx_chn = &common->tx_chns[q_idx]; 1024 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1025 1026 /* Map the linear buffer */ 1027 buf_dma = dma_map_single(dev, skb->data, pkt_len, 1028 DMA_TO_DEVICE); 1029 if (unlikely(dma_mapping_error(dev, buf_dma))) { 1030 dev_err(dev, "Failed to map tx skb buffer\n"); 1031 ndev->stats.tx_errors++; 1032 goto err_free_skb; 1033 } 1034 1035 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1036 if (!first_desc) { 1037 dev_dbg(dev, "Failed to allocate descriptor\n"); 1038 dma_unmap_single(dev, buf_dma, pkt_len, DMA_TO_DEVICE); 1039 goto busy_stop_q; 1040 } 1041 1042 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1043 AM65_CPSW_NAV_PS_DATA_SIZE); 1044 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1045 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1046 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1047 1048 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1049 swdata = cppi5_hdesc_get_swdata(first_desc); 1050 *(swdata) = skb; 1051 psdata = cppi5_hdesc_get_psdata(first_desc); 1052 1053 /* HW csum offload if enabled */ 1054 psdata[2] = 0; 1055 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1056 unsigned int cs_start, cs_offset; 1057 1058 cs_start = skb_transport_offset(skb); 1059 cs_offset = cs_start + skb->csum_offset; 1060 /* HW numerates bytes starting from 1 */ 1061 psdata[2] = ((cs_offset + 1) << 24) | 1062 ((cs_start + 1) << 16) | (skb->len - cs_start); 1063 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1064 } 1065 1066 if (!skb_is_nonlinear(skb)) 1067 goto done_tx; 1068 1069 dev_dbg(dev, "fragmented SKB\n"); 1070 1071 /* Handle the case where skb is fragmented in pages */ 1072 cur_desc = first_desc; 1073 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1074 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1075 u32 frag_size = skb_frag_size(frag); 1076 1077 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1078 if (!next_desc) { 1079 dev_err(dev, "Failed to allocate descriptor\n"); 1080 goto busy_free_descs; 1081 } 1082 1083 buf_dma = skb_frag_dma_map(dev, frag, 0, frag_size, 1084 DMA_TO_DEVICE); 1085 if (unlikely(dma_mapping_error(dev, buf_dma))) { 1086 dev_err(dev, "Failed to map tx skb page\n"); 1087 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1088 ndev->stats.tx_errors++; 1089 goto err_free_descs; 1090 } 1091 1092 cppi5_hdesc_reset_hbdesc(next_desc); 1093 cppi5_hdesc_attach_buf(next_desc, 1094 buf_dma, frag_size, buf_dma, frag_size); 1095 1096 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1097 next_desc); 1098 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1099 1100 pkt_len += frag_size; 1101 cur_desc = next_desc; 1102 } 1103 WARN_ON(pkt_len != skb->len); 1104 1105 done_tx: 1106 skb_tx_timestamp(skb); 1107 1108 /* report bql before sending packet */ 1109 netdev_tx_sent_queue(netif_txq, pkt_len); 1110 1111 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1112 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1113 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1114 if (ret) { 1115 dev_err(dev, "can't push desc %d\n", ret); 1116 /* inform bql */ 1117 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1118 ndev->stats.tx_errors++; 1119 goto err_free_descs; 1120 } 1121 1122 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1123 netif_tx_stop_queue(netif_txq); 1124 /* Barrier, so that stop_queue visible to other cpus */ 1125 smp_mb__after_atomic(); 1126 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1127 1128 /* re-check for smp */ 1129 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1130 MAX_SKB_FRAGS) { 1131 netif_tx_wake_queue(netif_txq); 1132 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1133 } 1134 } 1135 1136 return NETDEV_TX_OK; 1137 1138 err_free_descs: 1139 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc); 1140 err_free_skb: 1141 ndev->stats.tx_dropped++; 1142 dev_kfree_skb_any(skb); 1143 return NETDEV_TX_OK; 1144 1145 busy_free_descs: 1146 am65_cpsw_nuss_xmit_free(tx_chn, dev, first_desc); 1147 busy_stop_q: 1148 netif_tx_stop_queue(netif_txq); 1149 return NETDEV_TX_BUSY; 1150 } 1151 1152 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1153 void *addr) 1154 { 1155 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1156 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1157 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1158 int ret; 1159 1160 ret = eth_prepare_mac_addr_change(ndev, addr); 1161 if (ret < 0) 1162 return ret; 1163 1164 ret = pm_runtime_get_sync(common->dev); 1165 if (ret < 0) { 1166 pm_runtime_put_noidle(common->dev); 1167 return ret; 1168 } 1169 1170 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1171 HOST_PORT_NUM, 0, 0); 1172 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1173 HOST_PORT_NUM, ALE_SECURE, 0); 1174 1175 am65_cpsw_port_set_sl_mac(port, addr); 1176 eth_commit_mac_addr_change(ndev, sockaddr); 1177 1178 pm_runtime_put(common->dev); 1179 1180 return 0; 1181 } 1182 1183 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1184 struct ifreq *ifr) 1185 { 1186 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1187 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1188 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1189 struct hwtstamp_config cfg; 1190 1191 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1192 return -EOPNOTSUPP; 1193 1194 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1195 return -EFAULT; 1196 1197 /* TX HW timestamp */ 1198 switch (cfg.tx_type) { 1199 case HWTSTAMP_TX_OFF: 1200 case HWTSTAMP_TX_ON: 1201 break; 1202 default: 1203 return -ERANGE; 1204 } 1205 1206 switch (cfg.rx_filter) { 1207 case HWTSTAMP_FILTER_NONE: 1208 port->rx_ts_enabled = false; 1209 break; 1210 case HWTSTAMP_FILTER_ALL: 1211 case HWTSTAMP_FILTER_SOME: 1212 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1213 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1214 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1215 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1216 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1217 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1218 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1219 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1220 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1221 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1222 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1223 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1224 case HWTSTAMP_FILTER_NTP_ALL: 1225 port->rx_ts_enabled = true; 1226 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1227 break; 1228 default: 1229 return -ERANGE; 1230 } 1231 1232 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1233 1234 /* cfg TX timestamp */ 1235 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1236 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1237 1238 ts_vlan_ltype = ETH_P_8021Q; 1239 1240 ts_ctrl_ltype2 = ETH_P_1588 | 1241 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1242 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1243 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1244 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1245 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1246 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1247 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1248 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1249 1250 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1251 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1252 1253 if (port->tx_ts_enabled) 1254 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1255 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1256 1257 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1258 writel(ts_vlan_ltype, port->port_base + 1259 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1260 writel(ts_ctrl_ltype2, port->port_base + 1261 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1262 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1263 1264 /* en/dis RX timestamp */ 1265 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1266 1267 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1268 } 1269 1270 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1271 struct ifreq *ifr) 1272 { 1273 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1274 struct hwtstamp_config cfg; 1275 1276 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1277 return -EOPNOTSUPP; 1278 1279 cfg.flags = 0; 1280 cfg.tx_type = port->tx_ts_enabled ? 1281 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1282 cfg.rx_filter = port->rx_ts_enabled ? 1283 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1284 1285 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1286 } 1287 1288 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1289 struct ifreq *req, int cmd) 1290 { 1291 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1292 1293 if (!netif_running(ndev)) 1294 return -EINVAL; 1295 1296 switch (cmd) { 1297 case SIOCSHWTSTAMP: 1298 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1299 case SIOCGHWTSTAMP: 1300 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1301 } 1302 1303 if (!port->slave.phy) 1304 return -EOPNOTSUPP; 1305 1306 return phy_mii_ioctl(port->slave.phy, req, cmd); 1307 } 1308 1309 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1310 struct rtnl_link_stats64 *stats) 1311 { 1312 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1313 unsigned int start; 1314 int cpu; 1315 1316 for_each_possible_cpu(cpu) { 1317 struct am65_cpsw_ndev_stats *cpu_stats; 1318 u64 rx_packets; 1319 u64 rx_bytes; 1320 u64 tx_packets; 1321 u64 tx_bytes; 1322 1323 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1324 do { 1325 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1326 rx_packets = cpu_stats->rx_packets; 1327 rx_bytes = cpu_stats->rx_bytes; 1328 tx_packets = cpu_stats->tx_packets; 1329 tx_bytes = cpu_stats->tx_bytes; 1330 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1331 1332 stats->rx_packets += rx_packets; 1333 stats->rx_bytes += rx_bytes; 1334 stats->tx_packets += tx_packets; 1335 stats->tx_bytes += tx_bytes; 1336 } 1337 1338 stats->rx_errors = dev->stats.rx_errors; 1339 stats->rx_dropped = dev->stats.rx_dropped; 1340 stats->tx_dropped = dev->stats.tx_dropped; 1341 } 1342 1343 static int am65_cpsw_nuss_ndo_slave_set_features(struct net_device *ndev, 1344 netdev_features_t features) 1345 { 1346 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1347 netdev_features_t changes = features ^ ndev->features; 1348 struct am65_cpsw_host *host_p; 1349 1350 host_p = am65_common_get_host(common); 1351 1352 if (changes & NETIF_F_HW_CSUM) { 1353 bool enable = !!(features & NETIF_F_HW_CSUM); 1354 1355 dev_info(common->dev, "Turn %s tx-checksum-ip-generic\n", 1356 enable ? "ON" : "OFF"); 1357 if (enable) 1358 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, 1359 host_p->port_base + AM65_CPSW_P0_REG_CTL); 1360 else 1361 writel(0, 1362 host_p->port_base + AM65_CPSW_P0_REG_CTL); 1363 } 1364 1365 return 0; 1366 } 1367 1368 static const struct net_device_ops am65_cpsw_nuss_netdev_ops_2g = { 1369 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1370 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1371 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1372 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1373 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1374 .ndo_validate_addr = eth_validate_addr, 1375 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1376 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1377 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1378 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1379 .ndo_do_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1380 .ndo_set_features = am65_cpsw_nuss_ndo_slave_set_features, 1381 }; 1382 1383 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1384 { 1385 struct am65_cpsw_common *common = port->common; 1386 1387 if (!port->disabled) 1388 return; 1389 1390 common->disabled_ports_mask |= BIT(port->port_id); 1391 cpsw_ale_control_set(common->ale, port->port_id, 1392 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1393 1394 cpsw_sl_reset(port->slave.mac_sl, 100); 1395 cpsw_sl_ctl_reset(port->slave.mac_sl); 1396 } 1397 1398 static void am65_cpsw_nuss_free_tx_chns(void *data) 1399 { 1400 struct am65_cpsw_common *common = data; 1401 int i; 1402 1403 for (i = 0; i < common->tx_ch_num; i++) { 1404 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1405 1406 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1407 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1408 1409 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1410 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1411 1412 memset(tx_chn, 0, sizeof(*tx_chn)); 1413 } 1414 } 1415 1416 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1417 { 1418 struct device *dev = common->dev; 1419 int i; 1420 1421 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1422 1423 for (i = 0; i < common->tx_ch_num; i++) { 1424 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1425 1426 if (tx_chn->irq) 1427 devm_free_irq(dev, tx_chn->irq, tx_chn); 1428 1429 netif_napi_del(&tx_chn->napi_tx); 1430 1431 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1432 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1433 1434 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1435 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1436 1437 memset(tx_chn, 0, sizeof(*tx_chn)); 1438 } 1439 } 1440 1441 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1442 { 1443 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1444 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1445 struct device *dev = common->dev; 1446 struct k3_ring_cfg ring_cfg = { 1447 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1448 .mode = K3_RINGACC_RING_MODE_RING, 1449 .flags = 0 1450 }; 1451 u32 hdesc_size; 1452 int i, ret = 0; 1453 1454 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1455 AM65_CPSW_NAV_SW_DATA_SIZE); 1456 1457 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1458 tx_cfg.tx_cfg = ring_cfg; 1459 tx_cfg.txcq_cfg = ring_cfg; 1460 tx_cfg.tx_cfg.size = max_desc_num; 1461 tx_cfg.txcq_cfg.size = max_desc_num; 1462 1463 for (i = 0; i < common->tx_ch_num; i++) { 1464 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1465 1466 snprintf(tx_chn->tx_chn_name, 1467 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1468 1469 tx_chn->common = common; 1470 tx_chn->id = i; 1471 tx_chn->descs_num = max_desc_num; 1472 tx_chn->desc_pool = 1473 k3_cppi_desc_pool_create_name(dev, 1474 tx_chn->descs_num, 1475 hdesc_size, 1476 tx_chn->tx_chn_name); 1477 if (IS_ERR(tx_chn->desc_pool)) { 1478 ret = PTR_ERR(tx_chn->desc_pool); 1479 dev_err(dev, "Failed to create poll %d\n", ret); 1480 goto err; 1481 } 1482 1483 tx_chn->tx_chn = 1484 k3_udma_glue_request_tx_chn(dev, 1485 tx_chn->tx_chn_name, 1486 &tx_cfg); 1487 if (IS_ERR(tx_chn->tx_chn)) { 1488 ret = PTR_ERR(tx_chn->tx_chn); 1489 dev_err(dev, "Failed to request tx dma channel %d\n", 1490 ret); 1491 goto err; 1492 } 1493 1494 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1495 if (tx_chn->irq <= 0) { 1496 dev_err(dev, "Failed to get tx dma irq %d\n", 1497 tx_chn->irq); 1498 goto err; 1499 } 1500 1501 snprintf(tx_chn->tx_chn_name, 1502 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1503 dev_name(dev), tx_chn->id); 1504 } 1505 1506 err: 1507 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1508 if (i) { 1509 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1510 return i; 1511 } 1512 1513 return ret; 1514 } 1515 1516 static void am65_cpsw_nuss_free_rx_chns(void *data) 1517 { 1518 struct am65_cpsw_common *common = data; 1519 struct am65_cpsw_rx_chn *rx_chn; 1520 1521 rx_chn = &common->rx_chns; 1522 1523 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1524 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1525 1526 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1527 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1528 } 1529 1530 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1531 { 1532 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1533 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1534 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1535 struct device *dev = common->dev; 1536 u32 hdesc_size; 1537 u32 fdqring_id; 1538 int i, ret = 0; 1539 1540 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1541 AM65_CPSW_NAV_SW_DATA_SIZE); 1542 1543 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1544 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1545 rx_cfg.flow_id_base = common->rx_flow_id_base; 1546 1547 /* init all flows */ 1548 rx_chn->dev = dev; 1549 rx_chn->descs_num = max_desc_num; 1550 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(dev, 1551 rx_chn->descs_num, 1552 hdesc_size, "rx"); 1553 if (IS_ERR(rx_chn->desc_pool)) { 1554 ret = PTR_ERR(rx_chn->desc_pool); 1555 dev_err(dev, "Failed to create rx poll %d\n", ret); 1556 goto err; 1557 } 1558 1559 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1560 if (IS_ERR(rx_chn->rx_chn)) { 1561 ret = PTR_ERR(rx_chn->rx_chn); 1562 dev_err(dev, "Failed to request rx dma channel %d\n", ret); 1563 goto err; 1564 } 1565 1566 common->rx_flow_id_base = 1567 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1568 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1569 1570 fdqring_id = K3_RINGACC_RING_ID_ANY; 1571 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1572 struct k3_ring_cfg rxring_cfg = { 1573 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1574 .mode = K3_RINGACC_RING_MODE_RING, 1575 .flags = 0, 1576 }; 1577 struct k3_ring_cfg fdqring_cfg = { 1578 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1579 .mode = K3_RINGACC_RING_MODE_MESSAGE, 1580 .flags = K3_RINGACC_RING_SHARED, 1581 }; 1582 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1583 .rx_cfg = rxring_cfg, 1584 .rxfdq_cfg = fdqring_cfg, 1585 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1586 .src_tag_lo_sel = 1587 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1588 }; 1589 1590 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1591 rx_flow_cfg.rx_cfg.size = max_desc_num; 1592 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1593 1594 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1595 i, &rx_flow_cfg); 1596 if (ret) { 1597 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1598 goto err; 1599 } 1600 if (!i) 1601 fdqring_id = 1602 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1603 i); 1604 1605 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1606 1607 if (rx_chn->irq <= 0) { 1608 dev_err(dev, "Failed to get rx dma irq %d\n", 1609 rx_chn->irq); 1610 ret = -ENXIO; 1611 goto err; 1612 } 1613 } 1614 1615 err: 1616 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1617 if (i) { 1618 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1619 return i; 1620 } 1621 1622 return ret; 1623 } 1624 1625 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1626 { 1627 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1628 1629 host_p->common = common; 1630 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1631 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1632 1633 return 0; 1634 } 1635 1636 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1637 int slave, u8 *mac_addr) 1638 { 1639 u32 mac_lo, mac_hi, offset; 1640 struct regmap *syscon; 1641 int ret; 1642 1643 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1644 if (IS_ERR(syscon)) { 1645 if (PTR_ERR(syscon) == -ENODEV) 1646 return 0; 1647 return PTR_ERR(syscon); 1648 } 1649 1650 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1651 &offset); 1652 if (ret) 1653 return ret; 1654 1655 regmap_read(syscon, offset, &mac_lo); 1656 regmap_read(syscon, offset + 4, &mac_hi); 1657 1658 mac_addr[0] = (mac_hi >> 8) & 0xff; 1659 mac_addr[1] = mac_hi & 0xff; 1660 mac_addr[2] = (mac_lo >> 24) & 0xff; 1661 mac_addr[3] = (mac_lo >> 16) & 0xff; 1662 mac_addr[4] = (mac_lo >> 8) & 0xff; 1663 mac_addr[5] = mac_lo & 0xff; 1664 1665 return 0; 1666 } 1667 1668 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1669 { 1670 struct device *dev = common->dev; 1671 struct device_node *node; 1672 struct am65_cpts *cpts; 1673 void __iomem *reg_base; 1674 1675 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1676 return 0; 1677 1678 node = of_get_child_by_name(dev->of_node, "cpts"); 1679 if (!node) { 1680 dev_err(dev, "%s cpts not found\n", __func__); 1681 return -ENOENT; 1682 } 1683 1684 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1685 cpts = am65_cpts_create(dev, reg_base, node); 1686 if (IS_ERR(cpts)) { 1687 int ret = PTR_ERR(cpts); 1688 1689 if (ret == -EOPNOTSUPP) { 1690 dev_info(dev, "cpts disabled\n"); 1691 return 0; 1692 } 1693 1694 dev_err(dev, "cpts create err %d\n", ret); 1695 return ret; 1696 } 1697 common->cpts = cpts; 1698 1699 return 0; 1700 } 1701 1702 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1703 { 1704 struct device_node *node, *port_np; 1705 struct device *dev = common->dev; 1706 int ret; 1707 1708 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1709 if (!node) 1710 return -ENOENT; 1711 1712 for_each_child_of_node(node, port_np) { 1713 struct am65_cpsw_port *port; 1714 const void *mac_addr; 1715 u32 port_id; 1716 1717 /* it is not a slave port node, continue */ 1718 if (strcmp(port_np->name, "port")) 1719 continue; 1720 1721 ret = of_property_read_u32(port_np, "reg", &port_id); 1722 if (ret < 0) { 1723 dev_err(dev, "%pOF error reading port_id %d\n", 1724 port_np, ret); 1725 return ret; 1726 } 1727 1728 if (!port_id || port_id > common->port_num) { 1729 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1730 port_np, port_id, port_np->name); 1731 return -EINVAL; 1732 } 1733 1734 port = am65_common_get_port(common, port_id); 1735 port->port_id = port_id; 1736 port->common = common; 1737 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1738 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1739 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1740 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1741 port->name = of_get_property(port_np, "label", NULL); 1742 1743 port->disabled = !of_device_is_available(port_np); 1744 if (port->disabled) 1745 continue; 1746 1747 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1748 if (IS_ERR(port->slave.ifphy)) { 1749 ret = PTR_ERR(port->slave.ifphy); 1750 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1751 port_np, ret); 1752 return ret; 1753 } 1754 1755 port->slave.mac_only = 1756 of_property_read_bool(port_np, "ti,mac-only"); 1757 1758 /* get phy/link info */ 1759 if (of_phy_is_fixed_link(port_np)) { 1760 ret = of_phy_register_fixed_link(port_np); 1761 if (ret) { 1762 if (ret != -EPROBE_DEFER) 1763 dev_err(dev, "%pOF failed to register fixed-link phy: %d\n", 1764 port_np, ret); 1765 return ret; 1766 } 1767 port->slave.phy_node = of_node_get(port_np); 1768 } else { 1769 port->slave.phy_node = 1770 of_parse_phandle(port_np, "phy-handle", 0); 1771 } 1772 1773 if (!port->slave.phy_node) { 1774 dev_err(dev, 1775 "slave[%d] no phy found\n", port_id); 1776 return -ENODEV; 1777 } 1778 1779 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1780 if (ret) { 1781 dev_err(dev, "%pOF read phy-mode err %d\n", 1782 port_np, ret); 1783 return ret; 1784 } 1785 1786 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1787 if (IS_ERR(port->slave.mac_sl)) 1788 return PTR_ERR(port->slave.mac_sl); 1789 1790 mac_addr = of_get_mac_address(port_np); 1791 if (!IS_ERR(mac_addr)) { 1792 ether_addr_copy(port->slave.mac_addr, mac_addr); 1793 } else if (am65_cpsw_am654_get_efuse_macid(port_np, 1794 port->port_id, 1795 port->slave.mac_addr) || 1796 !is_valid_ether_addr(port->slave.mac_addr)) { 1797 random_ether_addr(port->slave.mac_addr); 1798 dev_err(dev, "Use random MAC address\n"); 1799 } 1800 } 1801 of_node_put(node); 1802 1803 return 0; 1804 } 1805 1806 static void am65_cpsw_pcpu_stats_free(void *data) 1807 { 1808 struct am65_cpsw_ndev_stats __percpu *stats = data; 1809 1810 free_percpu(stats); 1811 } 1812 1813 static int am65_cpsw_nuss_init_ndev_2g(struct am65_cpsw_common *common) 1814 { 1815 struct am65_cpsw_ndev_priv *ndev_priv; 1816 struct device *dev = common->dev; 1817 struct am65_cpsw_port *port; 1818 int ret; 1819 1820 port = am65_common_get_port(common, 1); 1821 1822 /* alloc netdev */ 1823 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1824 sizeof(struct am65_cpsw_ndev_priv), 1825 AM65_CPSW_MAX_TX_QUEUES, 1826 AM65_CPSW_MAX_RX_QUEUES); 1827 if (!port->ndev) { 1828 dev_err(dev, "error allocating slave net_device %u\n", 1829 port->port_id); 1830 return -ENOMEM; 1831 } 1832 1833 ndev_priv = netdev_priv(port->ndev); 1834 ndev_priv->port = port; 1835 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1836 SET_NETDEV_DEV(port->ndev, dev); 1837 1838 ether_addr_copy(port->ndev->dev_addr, port->slave.mac_addr); 1839 1840 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1841 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1842 port->ndev->hw_features = NETIF_F_SG | 1843 NETIF_F_RXCSUM | 1844 NETIF_F_HW_CSUM; 1845 port->ndev->features = port->ndev->hw_features | 1846 NETIF_F_HW_VLAN_CTAG_FILTER; 1847 port->ndev->vlan_features |= NETIF_F_SG; 1848 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops_2g; 1849 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1850 1851 /* Disable TX checksum offload by default due to HW bug */ 1852 if (common->pdata->quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 1853 port->ndev->features &= ~NETIF_F_HW_CSUM; 1854 1855 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 1856 if (!ndev_priv->stats) 1857 return -ENOMEM; 1858 1859 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 1860 ndev_priv->stats); 1861 if (ret) { 1862 dev_err(dev, "Failed to add percpu stat free action %d\n", ret); 1863 return ret; 1864 } 1865 1866 netif_napi_add(port->ndev, &common->napi_rx, 1867 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT); 1868 1869 common->pf_p0_rx_ptype_rrobin = false; 1870 1871 return ret; 1872 } 1873 1874 static int am65_cpsw_nuss_ndev_add_napi_2g(struct am65_cpsw_common *common) 1875 { 1876 struct device *dev = common->dev; 1877 struct am65_cpsw_port *port; 1878 int i, ret = 0; 1879 1880 port = am65_common_get_port(common, 1); 1881 1882 for (i = 0; i < common->tx_ch_num; i++) { 1883 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1884 1885 netif_tx_napi_add(port->ndev, &tx_chn->napi_tx, 1886 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT); 1887 1888 ret = devm_request_irq(dev, tx_chn->irq, 1889 am65_cpsw_nuss_tx_irq, 1890 IRQF_TRIGGER_HIGH, 1891 tx_chn->tx_chn_name, tx_chn); 1892 if (ret) { 1893 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1894 tx_chn->id, tx_chn->irq, ret); 1895 goto err; 1896 } 1897 } 1898 1899 err: 1900 return ret; 1901 } 1902 1903 static int am65_cpsw_nuss_ndev_reg_2g(struct am65_cpsw_common *common) 1904 { 1905 struct device *dev = common->dev; 1906 struct am65_cpsw_port *port; 1907 int ret = 0; 1908 1909 port = am65_common_get_port(common, 1); 1910 ret = am65_cpsw_nuss_ndev_add_napi_2g(common); 1911 if (ret) 1912 goto err; 1913 1914 ret = devm_request_irq(dev, common->rx_chns.irq, 1915 am65_cpsw_nuss_rx_irq, 1916 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1917 if (ret) { 1918 dev_err(dev, "failure requesting rx irq %u, %d\n", 1919 common->rx_chns.irq, ret); 1920 goto err; 1921 } 1922 1923 ret = register_netdev(port->ndev); 1924 if (ret) 1925 dev_err(dev, "error registering slave net device %d\n", ret); 1926 1927 /* can't auto unregister ndev using devm_add_action() due to 1928 * devres release sequence in DD core for DMA 1929 */ 1930 err: 1931 return ret; 1932 } 1933 1934 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 1935 { 1936 int ret; 1937 1938 common->tx_ch_num = num_tx; 1939 ret = am65_cpsw_nuss_init_tx_chns(common); 1940 if (ret) 1941 return ret; 1942 1943 return am65_cpsw_nuss_ndev_add_napi_2g(common); 1944 } 1945 1946 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 1947 { 1948 struct am65_cpsw_port *port; 1949 int i; 1950 1951 for (i = 0; i < common->port_num; i++) { 1952 port = &common->ports[i]; 1953 if (port->ndev) 1954 unregister_netdev(port->ndev); 1955 } 1956 } 1957 1958 static const struct am65_cpsw_pdata am65x_sr1_0 = { 1959 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 1960 }; 1961 1962 static const struct am65_cpsw_pdata j721e_sr1_0 = { 1963 .quirks = 0, 1964 }; 1965 1966 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 1967 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0 }, 1968 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_sr1_0 }, 1969 { /* sentinel */ }, 1970 }; 1971 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 1972 1973 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 1974 { 1975 struct cpsw_ale_params ale_params; 1976 const struct of_device_id *of_id; 1977 struct device *dev = &pdev->dev; 1978 struct am65_cpsw_common *common; 1979 struct device_node *node; 1980 struct resource *res; 1981 int ret, i; 1982 1983 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 1984 if (!common) 1985 return -ENOMEM; 1986 common->dev = dev; 1987 1988 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 1989 if (!of_id) 1990 return -EINVAL; 1991 common->pdata = of_id->data; 1992 1993 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 1994 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 1995 if (IS_ERR(common->ss_base)) 1996 return PTR_ERR(common->ss_base); 1997 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 1998 1999 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2000 if (!node) 2001 return -ENOENT; 2002 common->port_num = of_get_child_count(node); 2003 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2004 return -ENOENT; 2005 of_node_put(node); 2006 2007 if (common->port_num != 1) 2008 return -EOPNOTSUPP; 2009 2010 common->rx_flow_id_base = -1; 2011 init_completion(&common->tdown_complete); 2012 common->tx_ch_num = 1; 2013 2014 ret = dma_coerce_mask_and_coherent(dev, DMA_BIT_MASK(48)); 2015 if (ret) { 2016 dev_err(dev, "error setting dma mask: %d\n", ret); 2017 return ret; 2018 } 2019 2020 common->ports = devm_kcalloc(dev, common->port_num, 2021 sizeof(*common->ports), 2022 GFP_KERNEL); 2023 if (!common->ports) 2024 return -ENOMEM; 2025 2026 pm_runtime_enable(dev); 2027 ret = pm_runtime_get_sync(dev); 2028 if (ret < 0) { 2029 pm_runtime_put_noidle(dev); 2030 pm_runtime_disable(dev); 2031 return ret; 2032 } 2033 2034 node = of_get_child_by_name(dev->of_node, "mdio"); 2035 if (!node) { 2036 dev_warn(dev, "MDIO node not found\n"); 2037 } else if (of_device_is_available(node)) { 2038 struct platform_device *mdio_pdev; 2039 2040 mdio_pdev = of_platform_device_create(node, NULL, dev); 2041 if (!mdio_pdev) { 2042 ret = -ENODEV; 2043 goto err_pm_clear; 2044 } 2045 2046 common->mdio_dev = &mdio_pdev->dev; 2047 } 2048 of_node_put(node); 2049 2050 am65_cpsw_nuss_get_ver(common); 2051 2052 /* init tx channels */ 2053 ret = am65_cpsw_nuss_init_tx_chns(common); 2054 if (ret) 2055 goto err_of_clear; 2056 ret = am65_cpsw_nuss_init_rx_chns(common); 2057 if (ret) 2058 goto err_of_clear; 2059 2060 ret = am65_cpsw_nuss_init_host_p(common); 2061 if (ret) 2062 goto err_of_clear; 2063 2064 ret = am65_cpsw_nuss_init_slave_ports(common); 2065 if (ret) 2066 goto err_of_clear; 2067 2068 /* init common data */ 2069 ale_params.dev = dev; 2070 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2071 ale_params.ale_entries = 0; 2072 ale_params.ale_ports = common->port_num + 1; 2073 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2074 ale_params.nu_switch_ale = true; 2075 2076 common->ale = cpsw_ale_create(&ale_params); 2077 if (!common->ale) { 2078 dev_err(dev, "error initializing ale engine\n"); 2079 goto err_of_clear; 2080 } 2081 2082 ret = am65_cpsw_init_cpts(common); 2083 if (ret) 2084 goto err_of_clear; 2085 2086 /* init ports */ 2087 for (i = 0; i < common->port_num; i++) 2088 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2089 2090 dev_set_drvdata(dev, common); 2091 2092 ret = am65_cpsw_nuss_init_ndev_2g(common); 2093 if (ret) 2094 goto err_of_clear; 2095 2096 ret = am65_cpsw_nuss_ndev_reg_2g(common); 2097 if (ret) 2098 goto err_of_clear; 2099 2100 pm_runtime_put(dev); 2101 return 0; 2102 2103 err_of_clear: 2104 of_platform_device_destroy(common->mdio_dev, NULL); 2105 err_pm_clear: 2106 pm_runtime_put_sync(dev); 2107 pm_runtime_disable(dev); 2108 return ret; 2109 } 2110 2111 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2112 { 2113 struct device *dev = &pdev->dev; 2114 struct am65_cpsw_common *common; 2115 int ret; 2116 2117 common = dev_get_drvdata(dev); 2118 2119 ret = pm_runtime_get_sync(&pdev->dev); 2120 if (ret < 0) { 2121 pm_runtime_put_noidle(&pdev->dev); 2122 return ret; 2123 } 2124 2125 /* must unregister ndevs here because DD release_driver routine calls 2126 * dma_deconfigure(dev) before devres_release_all(dev) 2127 */ 2128 am65_cpsw_nuss_cleanup_ndev(common); 2129 2130 of_platform_device_destroy(common->mdio_dev, NULL); 2131 2132 pm_runtime_put_sync(&pdev->dev); 2133 pm_runtime_disable(&pdev->dev); 2134 return 0; 2135 } 2136 2137 static struct platform_driver am65_cpsw_nuss_driver = { 2138 .driver = { 2139 .name = AM65_CPSW_DRV_NAME, 2140 .of_match_table = am65_cpsw_nuss_of_mtable, 2141 }, 2142 .probe = am65_cpsw_nuss_probe, 2143 .remove = am65_cpsw_nuss_remove, 2144 }; 2145 2146 module_platform_driver(am65_cpsw_nuss_driver); 2147 2148 MODULE_LICENSE("GPL v2"); 2149 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2150 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2151