1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/phylink.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/rtnetlink.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/sys_soc.h> 30 #include <linux/dma/ti-cppi5.h> 31 #include <linux/dma/k3-udma-glue.h> 32 #include <net/switchdev.h> 33 34 #include "cpsw_ale.h" 35 #include "cpsw_sl.h" 36 #include "am65-cpsw-nuss.h" 37 #include "am65-cpsw-switchdev.h" 38 #include "k3-cppi-desc-pool.h" 39 #include "am65-cpts.h" 40 41 #define AM65_CPSW_SS_BASE 0x0 42 #define AM65_CPSW_SGMII_BASE 0x100 43 #define AM65_CPSW_XGMII_BASE 0x2100 44 #define AM65_CPSW_CPSW_NU_BASE 0x20000 45 #define AM65_CPSW_NU_PORTS_BASE 0x1000 46 #define AM65_CPSW_NU_FRAM_BASE 0x12000 47 #define AM65_CPSW_NU_STATS_BASE 0x1a000 48 #define AM65_CPSW_NU_ALE_BASE 0x1e000 49 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 50 51 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 52 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 53 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 54 55 #define AM65_CPSW_MAX_PORTS 8 56 57 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 58 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 59 60 #define AM65_CPSW_REG_CTL 0x004 61 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 62 #define AM65_CPSW_REG_PTYPE 0x018 63 64 #define AM65_CPSW_P0_REG_CTL 0x004 65 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 66 67 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 68 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 69 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 70 71 #define AM65_CPSW_PORTN_REG_SA_L 0x308 72 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 73 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 74 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 75 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 76 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 77 78 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 79 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 80 81 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 82 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 83 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 84 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 85 86 /* AM65_CPSW_P0_REG_CTL */ 87 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 88 89 /* AM65_CPSW_PORT_REG_PRI_CTL */ 90 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 91 92 /* AM65_CPSW_PN_TS_CTL register fields */ 93 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 94 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 95 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 97 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 98 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 99 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 100 101 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 102 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 103 104 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 113 114 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 115 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 116 117 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 118 119 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 120 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 121 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 122 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 123 124 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 125 /* Number of TX/RX descriptors */ 126 #define AM65_CPSW_MAX_TX_DESC 500 127 #define AM65_CPSW_MAX_RX_DESC 500 128 129 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 130 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 131 132 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 133 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 134 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 135 136 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 137 const u8 *dev_addr) 138 { 139 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 140 (dev_addr[2] << 16) | (dev_addr[3] << 24); 141 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 142 143 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 144 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 145 } 146 147 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 148 { 149 cpsw_sl_reset(port->slave.mac_sl, 100); 150 /* Max length register has to be restored after MAC SL reset */ 151 writel(AM65_CPSW_MAX_PACKET_SIZE, 152 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 153 } 154 155 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 156 { 157 common->nuss_ver = readl(common->ss_base); 158 common->cpsw_ver = readl(common->cpsw_base); 159 dev_info(common->dev, 160 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 161 common->nuss_ver, 162 common->cpsw_ver, 163 common->port_num + 1, 164 common->pdata.quirks); 165 } 166 167 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 168 __be16 proto, u16 vid) 169 { 170 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 171 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 172 u32 port_mask, unreg_mcast = 0; 173 int ret; 174 175 if (!common->is_emac_mode) 176 return 0; 177 178 if (!netif_running(ndev) || !vid) 179 return 0; 180 181 ret = pm_runtime_resume_and_get(common->dev); 182 if (ret < 0) 183 return ret; 184 185 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 186 if (!vid) 187 unreg_mcast = port_mask; 188 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 189 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 190 unreg_mcast, port_mask, 0); 191 192 pm_runtime_put(common->dev); 193 return ret; 194 } 195 196 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 197 __be16 proto, u16 vid) 198 { 199 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 200 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 201 int ret; 202 203 if (!common->is_emac_mode) 204 return 0; 205 206 if (!netif_running(ndev) || !vid) 207 return 0; 208 209 ret = pm_runtime_resume_and_get(common->dev); 210 if (ret < 0) 211 return ret; 212 213 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 214 ret = cpsw_ale_del_vlan(common->ale, vid, 215 BIT(port->port_id) | ALE_PORT_HOST); 216 217 pm_runtime_put(common->dev); 218 return ret; 219 } 220 221 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 222 bool promisc) 223 { 224 struct am65_cpsw_common *common = port->common; 225 226 if (promisc && !common->is_emac_mode) { 227 dev_dbg(common->dev, "promisc mode requested in switch mode"); 228 return; 229 } 230 231 if (promisc) { 232 /* Enable promiscuous mode */ 233 cpsw_ale_control_set(common->ale, port->port_id, 234 ALE_PORT_MACONLY_CAF, 1); 235 dev_dbg(common->dev, "promisc enabled\n"); 236 } else { 237 /* Disable promiscuous mode */ 238 cpsw_ale_control_set(common->ale, port->port_id, 239 ALE_PORT_MACONLY_CAF, 0); 240 dev_dbg(common->dev, "promisc disabled\n"); 241 } 242 } 243 244 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 245 { 246 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 247 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 248 u32 port_mask; 249 bool promisc; 250 251 promisc = !!(ndev->flags & IFF_PROMISC); 252 am65_cpsw_slave_set_promisc(port, promisc); 253 254 if (promisc) 255 return; 256 257 /* Restore allmulti on vlans if necessary */ 258 cpsw_ale_set_allmulti(common->ale, 259 ndev->flags & IFF_ALLMULTI, port->port_id); 260 261 port_mask = ALE_PORT_HOST; 262 /* Clear all mcast from ALE */ 263 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 264 265 if (!netdev_mc_empty(ndev)) { 266 struct netdev_hw_addr *ha; 267 268 /* program multicast address list into ALE register */ 269 netdev_for_each_mc_addr(ha, ndev) { 270 cpsw_ale_add_mcast(common->ale, ha->addr, 271 port_mask, 0, 0, 0); 272 } 273 } 274 } 275 276 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 277 unsigned int txqueue) 278 { 279 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 280 struct am65_cpsw_tx_chn *tx_chn; 281 struct netdev_queue *netif_txq; 282 unsigned long trans_start; 283 284 netif_txq = netdev_get_tx_queue(ndev, txqueue); 285 tx_chn = &common->tx_chns[txqueue]; 286 trans_start = READ_ONCE(netif_txq->trans_start); 287 288 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 289 txqueue, 290 netif_tx_queue_stopped(netif_txq), 291 jiffies_to_msecs(jiffies - trans_start), 292 dql_avail(&netif_txq->dql), 293 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 294 295 if (netif_tx_queue_stopped(netif_txq)) { 296 /* try recover if stopped by us */ 297 txq_trans_update(netif_txq); 298 netif_tx_wake_queue(netif_txq); 299 } 300 } 301 302 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 303 struct sk_buff *skb) 304 { 305 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 306 struct cppi5_host_desc_t *desc_rx; 307 struct device *dev = common->dev; 308 u32 pkt_len = skb_tailroom(skb); 309 dma_addr_t desc_dma; 310 dma_addr_t buf_dma; 311 void *swdata; 312 313 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 314 if (!desc_rx) { 315 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 316 return -ENOMEM; 317 } 318 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 319 320 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 321 DMA_FROM_DEVICE); 322 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 323 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 324 dev_err(dev, "Failed to map rx skb buffer\n"); 325 return -EINVAL; 326 } 327 328 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 329 AM65_CPSW_NAV_PS_DATA_SIZE); 330 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 331 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 332 swdata = cppi5_hdesc_get_swdata(desc_rx); 333 *((void **)swdata) = skb; 334 335 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 336 } 337 338 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 339 { 340 struct am65_cpsw_host *host_p = am65_common_get_host(common); 341 u32 val, pri_map; 342 343 /* P0 set Receive Priority Type */ 344 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 345 346 if (common->pf_p0_rx_ptype_rrobin) { 347 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 348 /* Enet Ports fifos works in fixed priority mode only, so 349 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 350 */ 351 pri_map = 0x0; 352 } else { 353 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 354 /* restore P0_Rx_Pri_Map */ 355 pri_map = 0x76543210; 356 } 357 358 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 359 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 360 } 361 362 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 363 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 364 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 365 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 366 367 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 368 { 369 struct am65_cpsw_host *host_p = am65_common_get_host(common); 370 int port_idx, i, ret; 371 struct sk_buff *skb; 372 u32 val, port_mask; 373 374 if (common->usage_count) 375 return 0; 376 377 /* Control register */ 378 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 379 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 380 common->cpsw_base + AM65_CPSW_REG_CTL); 381 /* Max length register */ 382 writel(AM65_CPSW_MAX_PACKET_SIZE, 383 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 384 /* set base flow_id */ 385 writel(common->rx_flow_id_base, 386 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 387 /* en tx crc offload */ 388 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 389 390 am65_cpsw_nuss_set_p0_ptype(common); 391 392 /* enable statistic */ 393 val = BIT(HOST_PORT_NUM); 394 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 395 struct am65_cpsw_port *port = &common->ports[port_idx]; 396 397 if (!port->disabled) 398 val |= BIT(port->port_id); 399 } 400 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 401 402 /* disable priority elevation */ 403 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 404 405 cpsw_ale_start(common->ale); 406 407 /* limit to one RX flow only */ 408 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 409 ALE_DEFAULT_THREAD_ID, 0); 410 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 411 ALE_DEFAULT_THREAD_ENABLE, 1); 412 /* switch to vlan unaware mode */ 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 414 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 415 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 416 417 /* default vlan cfg: create mask based on enabled ports */ 418 port_mask = GENMASK(common->port_num, 0) & 419 ~common->disabled_ports_mask; 420 421 cpsw_ale_add_vlan(common->ale, 0, port_mask, 422 port_mask, port_mask, 423 port_mask & ~ALE_PORT_HOST); 424 425 if (common->is_emac_mode) 426 am65_cpsw_init_host_port_emac(common); 427 else 428 am65_cpsw_init_host_port_switch(common); 429 430 for (i = 0; i < common->rx_chns.descs_num; i++) { 431 skb = __netdev_alloc_skb_ip_align(NULL, 432 AM65_CPSW_MAX_PACKET_SIZE, 433 GFP_KERNEL); 434 if (!skb) { 435 dev_err(common->dev, "cannot allocate skb\n"); 436 return -ENOMEM; 437 } 438 439 ret = am65_cpsw_nuss_rx_push(common, skb); 440 if (ret < 0) { 441 dev_err(common->dev, 442 "cannot submit skb to channel rx, error %d\n", 443 ret); 444 kfree_skb(skb); 445 return ret; 446 } 447 kmemleak_not_leak(skb); 448 } 449 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 450 451 for (i = 0; i < common->tx_ch_num; i++) { 452 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 453 if (ret) 454 return ret; 455 napi_enable(&common->tx_chns[i].napi_tx); 456 } 457 458 napi_enable(&common->napi_rx); 459 if (common->rx_irq_disabled) { 460 common->rx_irq_disabled = false; 461 enable_irq(common->rx_chns.irq); 462 } 463 464 dev_dbg(common->dev, "cpsw_nuss started\n"); 465 return 0; 466 } 467 468 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 469 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 470 471 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 472 { 473 int i; 474 475 if (common->usage_count != 1) 476 return 0; 477 478 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 479 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 480 481 /* shutdown tx channels */ 482 atomic_set(&common->tdown_cnt, common->tx_ch_num); 483 /* ensure new tdown_cnt value is visible */ 484 smp_mb__after_atomic(); 485 reinit_completion(&common->tdown_complete); 486 487 for (i = 0; i < common->tx_ch_num; i++) 488 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 489 490 i = wait_for_completion_timeout(&common->tdown_complete, 491 msecs_to_jiffies(1000)); 492 if (!i) 493 dev_err(common->dev, "tx timeout\n"); 494 for (i = 0; i < common->tx_ch_num; i++) 495 napi_disable(&common->tx_chns[i].napi_tx); 496 497 for (i = 0; i < common->tx_ch_num; i++) { 498 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 499 &common->tx_chns[i], 500 am65_cpsw_nuss_tx_cleanup); 501 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 502 } 503 504 reinit_completion(&common->tdown_complete); 505 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 506 507 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 508 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 509 if (!i) 510 dev_err(common->dev, "rx teardown timeout\n"); 511 } 512 513 napi_disable(&common->napi_rx); 514 515 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 516 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 517 &common->rx_chns, 518 am65_cpsw_nuss_rx_cleanup, !!i); 519 520 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 521 522 cpsw_ale_stop(common->ale); 523 524 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 525 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 526 527 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 528 return 0; 529 } 530 531 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 532 { 533 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 534 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 535 int ret; 536 537 phylink_stop(port->slave.phylink); 538 539 netif_tx_stop_all_queues(ndev); 540 541 phylink_disconnect_phy(port->slave.phylink); 542 543 ret = am65_cpsw_nuss_common_stop(common); 544 if (ret) 545 return ret; 546 547 common->usage_count--; 548 pm_runtime_put(common->dev); 549 return 0; 550 } 551 552 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 553 { 554 struct am65_cpsw_port *port = arg; 555 556 if (!vdev) 557 return 0; 558 559 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 560 } 561 562 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 563 { 564 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 565 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 566 int ret, i; 567 u32 reg; 568 569 ret = pm_runtime_resume_and_get(common->dev); 570 if (ret < 0) 571 return ret; 572 573 /* Idle MAC port */ 574 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 575 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 576 cpsw_sl_ctl_reset(port->slave.mac_sl); 577 578 /* soft reset MAC */ 579 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 580 mdelay(1); 581 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 582 if (reg) { 583 dev_err(common->dev, "soft RESET didn't complete\n"); 584 ret = -ETIMEDOUT; 585 goto runtime_put; 586 } 587 588 /* Notify the stack of the actual queue counts. */ 589 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 590 if (ret) { 591 dev_err(common->dev, "cannot set real number of tx queues\n"); 592 goto runtime_put; 593 } 594 595 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 596 if (ret) { 597 dev_err(common->dev, "cannot set real number of rx queues\n"); 598 goto runtime_put; 599 } 600 601 for (i = 0; i < common->tx_ch_num; i++) 602 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 603 604 ret = am65_cpsw_nuss_common_open(common); 605 if (ret) 606 goto runtime_put; 607 608 common->usage_count++; 609 610 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 611 612 if (common->is_emac_mode) 613 am65_cpsw_init_port_emac_ale(port); 614 else 615 am65_cpsw_init_port_switch_ale(port); 616 617 /* mac_sl should be configured via phy-link interface */ 618 am65_cpsw_sl_ctl_reset(port); 619 620 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 621 if (ret) 622 goto error_cleanup; 623 624 /* restore vlan configurations */ 625 vlan_for_each(ndev, cpsw_restore_vlans, port); 626 627 phylink_start(port->slave.phylink); 628 629 return 0; 630 631 error_cleanup: 632 am65_cpsw_nuss_ndo_slave_stop(ndev); 633 return ret; 634 635 runtime_put: 636 pm_runtime_put(common->dev); 637 return ret; 638 } 639 640 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 641 { 642 struct am65_cpsw_rx_chn *rx_chn = data; 643 struct cppi5_host_desc_t *desc_rx; 644 struct sk_buff *skb; 645 dma_addr_t buf_dma; 646 u32 buf_dma_len; 647 void **swdata; 648 649 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 650 swdata = cppi5_hdesc_get_swdata(desc_rx); 651 skb = *swdata; 652 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 653 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 654 655 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 656 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 657 658 dev_kfree_skb_any(skb); 659 } 660 661 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 662 { 663 struct skb_shared_hwtstamps *ssh; 664 u64 ns; 665 666 ns = ((u64)psdata[1] << 32) | psdata[0]; 667 668 ssh = skb_hwtstamps(skb); 669 memset(ssh, 0, sizeof(*ssh)); 670 ssh->hwtstamp = ns_to_ktime(ns); 671 } 672 673 /* RX psdata[2] word format - checksum information */ 674 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 675 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 676 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 677 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 678 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 679 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 680 681 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 682 { 683 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 684 * csum information provides in psdata[2] word: 685 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 686 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 687 * bits - indicates IPv4/IPv6 packet 688 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 689 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 690 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 691 */ 692 skb_checksum_none_assert(skb); 693 694 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 695 return; 696 697 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 698 AM65_CPSW_RX_PSD_IPV4_VALID)) && 699 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 700 /* csum for fragmented packets is unsupported */ 701 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 702 skb->ip_summed = CHECKSUM_UNNECESSARY; 703 } 704 } 705 706 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 707 u32 flow_idx) 708 { 709 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 710 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 711 struct am65_cpsw_ndev_priv *ndev_priv; 712 struct am65_cpsw_ndev_stats *stats; 713 struct cppi5_host_desc_t *desc_rx; 714 struct device *dev = common->dev; 715 struct sk_buff *skb, *new_skb; 716 dma_addr_t desc_dma, buf_dma; 717 struct am65_cpsw_port *port; 718 struct net_device *ndev; 719 void **swdata; 720 u32 *psdata; 721 int ret = 0; 722 723 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 724 if (ret) { 725 if (ret != -ENODATA) 726 dev_err(dev, "RX: pop chn fail %d\n", ret); 727 return ret; 728 } 729 730 if (cppi5_desc_is_tdcm(desc_dma)) { 731 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 732 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 733 complete(&common->tdown_complete); 734 return 0; 735 } 736 737 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 738 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 739 __func__, flow_idx, &desc_dma); 740 741 swdata = cppi5_hdesc_get_swdata(desc_rx); 742 skb = *swdata; 743 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 744 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 745 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 746 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 747 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 748 port = am65_common_get_port(common, port_id); 749 ndev = port->ndev; 750 skb->dev = ndev; 751 752 psdata = cppi5_hdesc_get_psdata(desc_rx); 753 /* add RX timestamp */ 754 if (port->rx_ts_enabled) 755 am65_cpsw_nuss_rx_ts(skb, psdata); 756 csum_info = psdata[2]; 757 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 758 759 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 760 761 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 762 763 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 764 if (new_skb) { 765 ndev_priv = netdev_priv(ndev); 766 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 767 skb_put(skb, pkt_len); 768 skb->protocol = eth_type_trans(skb, ndev); 769 am65_cpsw_nuss_rx_csum(skb, csum_info); 770 napi_gro_receive(&common->napi_rx, skb); 771 772 stats = this_cpu_ptr(ndev_priv->stats); 773 774 u64_stats_update_begin(&stats->syncp); 775 stats->rx_packets++; 776 stats->rx_bytes += pkt_len; 777 u64_stats_update_end(&stats->syncp); 778 kmemleak_not_leak(new_skb); 779 } else { 780 ndev->stats.rx_dropped++; 781 new_skb = skb; 782 } 783 784 if (netif_dormant(ndev)) { 785 dev_kfree_skb_any(new_skb); 786 ndev->stats.rx_dropped++; 787 return 0; 788 } 789 790 ret = am65_cpsw_nuss_rx_push(common, new_skb); 791 if (WARN_ON(ret < 0)) { 792 dev_kfree_skb_any(new_skb); 793 ndev->stats.rx_errors++; 794 ndev->stats.rx_dropped++; 795 } 796 797 return ret; 798 } 799 800 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 801 { 802 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 803 int flow = AM65_CPSW_MAX_RX_FLOWS; 804 int cur_budget, ret; 805 int num_rx = 0; 806 807 /* process every flow */ 808 while (flow--) { 809 cur_budget = budget - num_rx; 810 811 while (cur_budget--) { 812 ret = am65_cpsw_nuss_rx_packets(common, flow); 813 if (ret) 814 break; 815 num_rx++; 816 } 817 818 if (num_rx >= budget) 819 break; 820 } 821 822 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 823 824 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 825 if (common->rx_irq_disabled) { 826 common->rx_irq_disabled = false; 827 enable_irq(common->rx_chns.irq); 828 } 829 } 830 831 return num_rx; 832 } 833 834 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 835 struct cppi5_host_desc_t *desc) 836 { 837 struct cppi5_host_desc_t *first_desc, *next_desc; 838 dma_addr_t buf_dma, next_desc_dma; 839 u32 buf_dma_len; 840 841 first_desc = desc; 842 next_desc = first_desc; 843 844 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 845 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 846 847 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 848 849 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 850 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 851 while (next_desc_dma) { 852 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 853 next_desc_dma); 854 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 855 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 856 857 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 858 DMA_TO_DEVICE); 859 860 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 861 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 862 863 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 864 } 865 866 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 867 } 868 869 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 870 { 871 struct am65_cpsw_tx_chn *tx_chn = data; 872 struct cppi5_host_desc_t *desc_tx; 873 struct sk_buff *skb; 874 void **swdata; 875 876 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 877 swdata = cppi5_hdesc_get_swdata(desc_tx); 878 skb = *(swdata); 879 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 880 881 dev_kfree_skb_any(skb); 882 } 883 884 static struct sk_buff * 885 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 886 dma_addr_t desc_dma) 887 { 888 struct am65_cpsw_ndev_priv *ndev_priv; 889 struct am65_cpsw_ndev_stats *stats; 890 struct cppi5_host_desc_t *desc_tx; 891 struct net_device *ndev; 892 struct sk_buff *skb; 893 void **swdata; 894 895 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 896 desc_dma); 897 swdata = cppi5_hdesc_get_swdata(desc_tx); 898 skb = *(swdata); 899 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 900 901 ndev = skb->dev; 902 903 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 904 905 ndev_priv = netdev_priv(ndev); 906 stats = this_cpu_ptr(ndev_priv->stats); 907 u64_stats_update_begin(&stats->syncp); 908 stats->tx_packets++; 909 stats->tx_bytes += skb->len; 910 u64_stats_update_end(&stats->syncp); 911 912 return skb; 913 } 914 915 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 916 struct netdev_queue *netif_txq) 917 { 918 if (netif_tx_queue_stopped(netif_txq)) { 919 /* Check whether the queue is stopped due to stalled 920 * tx dma, if the queue is stopped then wake the queue 921 * as we have free desc for tx 922 */ 923 __netif_tx_lock(netif_txq, smp_processor_id()); 924 if (netif_running(ndev) && 925 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 926 netif_tx_wake_queue(netif_txq); 927 928 __netif_tx_unlock(netif_txq); 929 } 930 } 931 932 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 933 int chn, unsigned int budget) 934 { 935 struct device *dev = common->dev; 936 struct am65_cpsw_tx_chn *tx_chn; 937 struct netdev_queue *netif_txq; 938 unsigned int total_bytes = 0; 939 struct net_device *ndev; 940 struct sk_buff *skb; 941 dma_addr_t desc_dma; 942 int res, num_tx = 0; 943 944 tx_chn = &common->tx_chns[chn]; 945 946 while (true) { 947 spin_lock(&tx_chn->lock); 948 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 949 spin_unlock(&tx_chn->lock); 950 if (res == -ENODATA) 951 break; 952 953 if (cppi5_desc_is_tdcm(desc_dma)) { 954 if (atomic_dec_and_test(&common->tdown_cnt)) 955 complete(&common->tdown_complete); 956 break; 957 } 958 959 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 960 total_bytes = skb->len; 961 ndev = skb->dev; 962 napi_consume_skb(skb, budget); 963 num_tx++; 964 965 netif_txq = netdev_get_tx_queue(ndev, chn); 966 967 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 968 969 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 970 } 971 972 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 973 974 return num_tx; 975 } 976 977 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 978 int chn, unsigned int budget) 979 { 980 struct device *dev = common->dev; 981 struct am65_cpsw_tx_chn *tx_chn; 982 struct netdev_queue *netif_txq; 983 unsigned int total_bytes = 0; 984 struct net_device *ndev; 985 struct sk_buff *skb; 986 dma_addr_t desc_dma; 987 int res, num_tx = 0; 988 989 tx_chn = &common->tx_chns[chn]; 990 991 while (true) { 992 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 993 if (res == -ENODATA) 994 break; 995 996 if (cppi5_desc_is_tdcm(desc_dma)) { 997 if (atomic_dec_and_test(&common->tdown_cnt)) 998 complete(&common->tdown_complete); 999 break; 1000 } 1001 1002 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 1003 1004 ndev = skb->dev; 1005 total_bytes += skb->len; 1006 napi_consume_skb(skb, budget); 1007 num_tx++; 1008 } 1009 1010 if (!num_tx) 1011 return 0; 1012 1013 netif_txq = netdev_get_tx_queue(ndev, chn); 1014 1015 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1016 1017 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1018 1019 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1020 1021 return num_tx; 1022 } 1023 1024 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1025 { 1026 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1027 int num_tx; 1028 1029 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1030 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1031 else 1032 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1033 1034 if (num_tx >= budget) 1035 return budget; 1036 1037 if (napi_complete_done(napi_tx, num_tx)) 1038 enable_irq(tx_chn->irq); 1039 1040 return 0; 1041 } 1042 1043 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1044 { 1045 struct am65_cpsw_common *common = dev_id; 1046 1047 common->rx_irq_disabled = true; 1048 disable_irq_nosync(irq); 1049 napi_schedule(&common->napi_rx); 1050 1051 return IRQ_HANDLED; 1052 } 1053 1054 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1055 { 1056 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1057 1058 disable_irq_nosync(irq); 1059 napi_schedule(&tx_chn->napi_tx); 1060 1061 return IRQ_HANDLED; 1062 } 1063 1064 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1065 struct net_device *ndev) 1066 { 1067 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1068 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1069 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1070 struct device *dev = common->dev; 1071 struct am65_cpsw_tx_chn *tx_chn; 1072 struct netdev_queue *netif_txq; 1073 dma_addr_t desc_dma, buf_dma; 1074 int ret, q_idx, i; 1075 void **swdata; 1076 u32 *psdata; 1077 u32 pkt_len; 1078 1079 /* padding enabled in hw */ 1080 pkt_len = skb_headlen(skb); 1081 1082 /* SKB TX timestamp */ 1083 if (port->tx_ts_enabled) 1084 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1085 1086 q_idx = skb_get_queue_mapping(skb); 1087 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1088 1089 tx_chn = &common->tx_chns[q_idx]; 1090 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1091 1092 /* Map the linear buffer */ 1093 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1094 DMA_TO_DEVICE); 1095 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1096 dev_err(dev, "Failed to map tx skb buffer\n"); 1097 ndev->stats.tx_errors++; 1098 goto err_free_skb; 1099 } 1100 1101 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1102 if (!first_desc) { 1103 dev_dbg(dev, "Failed to allocate descriptor\n"); 1104 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1105 DMA_TO_DEVICE); 1106 goto busy_stop_q; 1107 } 1108 1109 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1110 AM65_CPSW_NAV_PS_DATA_SIZE); 1111 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1112 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1113 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1114 1115 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1116 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1117 swdata = cppi5_hdesc_get_swdata(first_desc); 1118 *(swdata) = skb; 1119 psdata = cppi5_hdesc_get_psdata(first_desc); 1120 1121 /* HW csum offload if enabled */ 1122 psdata[2] = 0; 1123 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1124 unsigned int cs_start, cs_offset; 1125 1126 cs_start = skb_transport_offset(skb); 1127 cs_offset = cs_start + skb->csum_offset; 1128 /* HW numerates bytes starting from 1 */ 1129 psdata[2] = ((cs_offset + 1) << 24) | 1130 ((cs_start + 1) << 16) | (skb->len - cs_start); 1131 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1132 } 1133 1134 if (!skb_is_nonlinear(skb)) 1135 goto done_tx; 1136 1137 dev_dbg(dev, "fragmented SKB\n"); 1138 1139 /* Handle the case where skb is fragmented in pages */ 1140 cur_desc = first_desc; 1141 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1142 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1143 u32 frag_size = skb_frag_size(frag); 1144 1145 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1146 if (!next_desc) { 1147 dev_err(dev, "Failed to allocate descriptor\n"); 1148 goto busy_free_descs; 1149 } 1150 1151 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1152 DMA_TO_DEVICE); 1153 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1154 dev_err(dev, "Failed to map tx skb page\n"); 1155 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1156 ndev->stats.tx_errors++; 1157 goto err_free_descs; 1158 } 1159 1160 cppi5_hdesc_reset_hbdesc(next_desc); 1161 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1162 cppi5_hdesc_attach_buf(next_desc, 1163 buf_dma, frag_size, buf_dma, frag_size); 1164 1165 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1166 next_desc); 1167 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1168 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1169 1170 pkt_len += frag_size; 1171 cur_desc = next_desc; 1172 } 1173 WARN_ON(pkt_len != skb->len); 1174 1175 done_tx: 1176 skb_tx_timestamp(skb); 1177 1178 /* report bql before sending packet */ 1179 netdev_tx_sent_queue(netif_txq, pkt_len); 1180 1181 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1182 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1183 if (AM65_CPSW_IS_CPSW2G(common)) { 1184 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1185 } else { 1186 spin_lock_bh(&tx_chn->lock); 1187 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1188 spin_unlock_bh(&tx_chn->lock); 1189 } 1190 if (ret) { 1191 dev_err(dev, "can't push desc %d\n", ret); 1192 /* inform bql */ 1193 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1194 ndev->stats.tx_errors++; 1195 goto err_free_descs; 1196 } 1197 1198 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1199 netif_tx_stop_queue(netif_txq); 1200 /* Barrier, so that stop_queue visible to other cpus */ 1201 smp_mb__after_atomic(); 1202 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1203 1204 /* re-check for smp */ 1205 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1206 MAX_SKB_FRAGS) { 1207 netif_tx_wake_queue(netif_txq); 1208 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1209 } 1210 } 1211 1212 return NETDEV_TX_OK; 1213 1214 err_free_descs: 1215 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1216 err_free_skb: 1217 ndev->stats.tx_dropped++; 1218 dev_kfree_skb_any(skb); 1219 return NETDEV_TX_OK; 1220 1221 busy_free_descs: 1222 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1223 busy_stop_q: 1224 netif_tx_stop_queue(netif_txq); 1225 return NETDEV_TX_BUSY; 1226 } 1227 1228 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1229 void *addr) 1230 { 1231 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1232 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1233 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1234 int ret; 1235 1236 ret = eth_prepare_mac_addr_change(ndev, addr); 1237 if (ret < 0) 1238 return ret; 1239 1240 ret = pm_runtime_resume_and_get(common->dev); 1241 if (ret < 0) 1242 return ret; 1243 1244 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1245 HOST_PORT_NUM, 0, 0); 1246 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1247 HOST_PORT_NUM, ALE_SECURE, 0); 1248 1249 am65_cpsw_port_set_sl_mac(port, addr); 1250 eth_commit_mac_addr_change(ndev, sockaddr); 1251 1252 pm_runtime_put(common->dev); 1253 1254 return 0; 1255 } 1256 1257 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1258 struct ifreq *ifr) 1259 { 1260 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1261 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1262 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1263 struct hwtstamp_config cfg; 1264 1265 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1266 return -EOPNOTSUPP; 1267 1268 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1269 return -EFAULT; 1270 1271 /* TX HW timestamp */ 1272 switch (cfg.tx_type) { 1273 case HWTSTAMP_TX_OFF: 1274 case HWTSTAMP_TX_ON: 1275 break; 1276 default: 1277 return -ERANGE; 1278 } 1279 1280 switch (cfg.rx_filter) { 1281 case HWTSTAMP_FILTER_NONE: 1282 port->rx_ts_enabled = false; 1283 break; 1284 case HWTSTAMP_FILTER_ALL: 1285 case HWTSTAMP_FILTER_SOME: 1286 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1287 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1288 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1289 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1290 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1291 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1292 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1293 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1294 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1295 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1296 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1297 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1298 case HWTSTAMP_FILTER_NTP_ALL: 1299 port->rx_ts_enabled = true; 1300 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1301 break; 1302 default: 1303 return -ERANGE; 1304 } 1305 1306 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1307 1308 /* cfg TX timestamp */ 1309 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1310 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1311 1312 ts_vlan_ltype = ETH_P_8021Q; 1313 1314 ts_ctrl_ltype2 = ETH_P_1588 | 1315 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1316 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1317 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1318 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1319 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1320 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1321 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1322 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1323 1324 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1325 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1326 1327 if (port->tx_ts_enabled) 1328 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1329 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1330 1331 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1332 writel(ts_vlan_ltype, port->port_base + 1333 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1334 writel(ts_ctrl_ltype2, port->port_base + 1335 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1336 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1337 1338 /* en/dis RX timestamp */ 1339 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1340 1341 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1342 } 1343 1344 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1345 struct ifreq *ifr) 1346 { 1347 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1348 struct hwtstamp_config cfg; 1349 1350 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1351 return -EOPNOTSUPP; 1352 1353 cfg.flags = 0; 1354 cfg.tx_type = port->tx_ts_enabled ? 1355 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1356 cfg.rx_filter = port->rx_ts_enabled ? 1357 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1358 1359 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1360 } 1361 1362 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1363 struct ifreq *req, int cmd) 1364 { 1365 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1366 1367 if (!netif_running(ndev)) 1368 return -EINVAL; 1369 1370 switch (cmd) { 1371 case SIOCSHWTSTAMP: 1372 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1373 case SIOCGHWTSTAMP: 1374 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1375 } 1376 1377 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1378 } 1379 1380 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1381 struct rtnl_link_stats64 *stats) 1382 { 1383 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1384 unsigned int start; 1385 int cpu; 1386 1387 for_each_possible_cpu(cpu) { 1388 struct am65_cpsw_ndev_stats *cpu_stats; 1389 u64 rx_packets; 1390 u64 rx_bytes; 1391 u64 tx_packets; 1392 u64 tx_bytes; 1393 1394 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1395 do { 1396 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1397 rx_packets = cpu_stats->rx_packets; 1398 rx_bytes = cpu_stats->rx_bytes; 1399 tx_packets = cpu_stats->tx_packets; 1400 tx_bytes = cpu_stats->tx_bytes; 1401 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1402 1403 stats->rx_packets += rx_packets; 1404 stats->rx_bytes += rx_bytes; 1405 stats->tx_packets += tx_packets; 1406 stats->tx_bytes += tx_bytes; 1407 } 1408 1409 stats->rx_errors = dev->stats.rx_errors; 1410 stats->rx_dropped = dev->stats.rx_dropped; 1411 stats->tx_dropped = dev->stats.tx_dropped; 1412 } 1413 1414 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1415 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1416 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1417 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1418 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1419 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1420 .ndo_validate_addr = eth_validate_addr, 1421 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1422 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1423 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1424 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1425 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1426 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1427 }; 1428 1429 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1430 const struct phylink_link_state *state) 1431 { 1432 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1433 phylink_config); 1434 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1435 struct am65_cpsw_common *common = port->common; 1436 1437 if (common->pdata.extra_modes & BIT(state->interface)) 1438 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1439 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1440 } 1441 1442 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1443 phy_interface_t interface) 1444 { 1445 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1446 phylink_config); 1447 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1448 struct am65_cpsw_common *common = port->common; 1449 struct net_device *ndev = port->ndev; 1450 int tmo; 1451 1452 /* disable forwarding */ 1453 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1454 1455 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1456 1457 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1458 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1459 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1460 1461 cpsw_sl_ctl_reset(port->slave.mac_sl); 1462 1463 am65_cpsw_qos_link_down(ndev); 1464 netif_tx_stop_all_queues(ndev); 1465 } 1466 1467 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1468 unsigned int mode, phy_interface_t interface, int speed, 1469 int duplex, bool tx_pause, bool rx_pause) 1470 { 1471 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1472 phylink_config); 1473 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1474 struct am65_cpsw_common *common = port->common; 1475 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1476 struct net_device *ndev = port->ndev; 1477 1478 if (speed == SPEED_1000) 1479 mac_control |= CPSW_SL_CTL_GIG; 1480 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 1481 /* Can be used with in band mode only */ 1482 mac_control |= CPSW_SL_CTL_EXT_EN; 1483 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1484 mac_control |= CPSW_SL_CTL_IFCTL_A; 1485 if (duplex) 1486 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1487 1488 /* rx_pause/tx_pause */ 1489 if (rx_pause) 1490 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1491 1492 if (tx_pause) 1493 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1494 1495 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1496 1497 /* enable forwarding */ 1498 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1499 1500 am65_cpsw_qos_link_up(ndev, speed); 1501 netif_tx_wake_all_queues(ndev); 1502 } 1503 1504 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1505 .mac_config = am65_cpsw_nuss_mac_config, 1506 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1507 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1508 }; 1509 1510 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1511 { 1512 struct am65_cpsw_common *common = port->common; 1513 1514 if (!port->disabled) 1515 return; 1516 1517 cpsw_ale_control_set(common->ale, port->port_id, 1518 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1519 1520 cpsw_sl_reset(port->slave.mac_sl, 100); 1521 cpsw_sl_ctl_reset(port->slave.mac_sl); 1522 } 1523 1524 static void am65_cpsw_nuss_free_tx_chns(void *data) 1525 { 1526 struct am65_cpsw_common *common = data; 1527 int i; 1528 1529 for (i = 0; i < common->tx_ch_num; i++) { 1530 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1531 1532 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1533 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1534 1535 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1536 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1537 1538 memset(tx_chn, 0, sizeof(*tx_chn)); 1539 } 1540 } 1541 1542 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1543 { 1544 struct device *dev = common->dev; 1545 int i; 1546 1547 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1548 1549 for (i = 0; i < common->tx_ch_num; i++) { 1550 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1551 1552 if (tx_chn->irq) 1553 devm_free_irq(dev, tx_chn->irq, tx_chn); 1554 1555 netif_napi_del(&tx_chn->napi_tx); 1556 1557 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1558 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1559 1560 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1561 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1562 1563 memset(tx_chn, 0, sizeof(*tx_chn)); 1564 } 1565 } 1566 1567 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 1568 { 1569 struct device *dev = common->dev; 1570 int i, ret = 0; 1571 1572 for (i = 0; i < common->tx_ch_num; i++) { 1573 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1574 1575 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 1576 am65_cpsw_nuss_tx_poll); 1577 1578 ret = devm_request_irq(dev, tx_chn->irq, 1579 am65_cpsw_nuss_tx_irq, 1580 IRQF_TRIGGER_HIGH, 1581 tx_chn->tx_chn_name, tx_chn); 1582 if (ret) { 1583 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1584 tx_chn->id, tx_chn->irq, ret); 1585 goto err; 1586 } 1587 } 1588 1589 err: 1590 return ret; 1591 } 1592 1593 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1594 { 1595 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1596 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1597 struct device *dev = common->dev; 1598 struct k3_ring_cfg ring_cfg = { 1599 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1600 .mode = K3_RINGACC_RING_MODE_RING, 1601 .flags = 0 1602 }; 1603 u32 hdesc_size; 1604 int i, ret = 0; 1605 1606 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1607 AM65_CPSW_NAV_SW_DATA_SIZE); 1608 1609 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1610 tx_cfg.tx_cfg = ring_cfg; 1611 tx_cfg.txcq_cfg = ring_cfg; 1612 tx_cfg.tx_cfg.size = max_desc_num; 1613 tx_cfg.txcq_cfg.size = max_desc_num; 1614 1615 for (i = 0; i < common->tx_ch_num; i++) { 1616 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1617 1618 snprintf(tx_chn->tx_chn_name, 1619 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1620 1621 spin_lock_init(&tx_chn->lock); 1622 tx_chn->common = common; 1623 tx_chn->id = i; 1624 tx_chn->descs_num = max_desc_num; 1625 1626 tx_chn->tx_chn = 1627 k3_udma_glue_request_tx_chn(dev, 1628 tx_chn->tx_chn_name, 1629 &tx_cfg); 1630 if (IS_ERR(tx_chn->tx_chn)) { 1631 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1632 "Failed to request tx dma channel\n"); 1633 goto err; 1634 } 1635 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1636 1637 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1638 tx_chn->descs_num, 1639 hdesc_size, 1640 tx_chn->tx_chn_name); 1641 if (IS_ERR(tx_chn->desc_pool)) { 1642 ret = PTR_ERR(tx_chn->desc_pool); 1643 dev_err(dev, "Failed to create poll %d\n", ret); 1644 goto err; 1645 } 1646 1647 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1648 if (tx_chn->irq <= 0) { 1649 dev_err(dev, "Failed to get tx dma irq %d\n", 1650 tx_chn->irq); 1651 goto err; 1652 } 1653 1654 snprintf(tx_chn->tx_chn_name, 1655 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1656 dev_name(dev), tx_chn->id); 1657 } 1658 1659 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 1660 if (ret) { 1661 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 1662 goto err; 1663 } 1664 1665 err: 1666 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1667 if (i) { 1668 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1669 return i; 1670 } 1671 1672 return ret; 1673 } 1674 1675 static void am65_cpsw_nuss_free_rx_chns(void *data) 1676 { 1677 struct am65_cpsw_common *common = data; 1678 struct am65_cpsw_rx_chn *rx_chn; 1679 1680 rx_chn = &common->rx_chns; 1681 1682 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1683 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1684 1685 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1686 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1687 } 1688 1689 static void am65_cpsw_nuss_remove_rx_chns(void *data) 1690 { 1691 struct am65_cpsw_common *common = data; 1692 struct am65_cpsw_rx_chn *rx_chn; 1693 struct device *dev = common->dev; 1694 1695 rx_chn = &common->rx_chns; 1696 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1697 1698 if (!(rx_chn->irq < 0)) 1699 devm_free_irq(dev, rx_chn->irq, common); 1700 1701 netif_napi_del(&common->napi_rx); 1702 1703 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1704 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1705 1706 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1707 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1708 1709 common->rx_flow_id_base = -1; 1710 } 1711 1712 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1713 { 1714 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1715 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1716 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1717 struct device *dev = common->dev; 1718 u32 hdesc_size; 1719 u32 fdqring_id; 1720 int i, ret = 0; 1721 1722 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1723 AM65_CPSW_NAV_SW_DATA_SIZE); 1724 1725 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1726 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1727 rx_cfg.flow_id_base = common->rx_flow_id_base; 1728 1729 /* init all flows */ 1730 rx_chn->dev = dev; 1731 rx_chn->descs_num = max_desc_num; 1732 1733 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1734 if (IS_ERR(rx_chn->rx_chn)) { 1735 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1736 "Failed to request rx dma channel\n"); 1737 goto err; 1738 } 1739 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1740 1741 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1742 rx_chn->descs_num, 1743 hdesc_size, "rx"); 1744 if (IS_ERR(rx_chn->desc_pool)) { 1745 ret = PTR_ERR(rx_chn->desc_pool); 1746 dev_err(dev, "Failed to create rx poll %d\n", ret); 1747 goto err; 1748 } 1749 1750 common->rx_flow_id_base = 1751 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1752 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1753 1754 fdqring_id = K3_RINGACC_RING_ID_ANY; 1755 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1756 struct k3_ring_cfg rxring_cfg = { 1757 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1758 .mode = K3_RINGACC_RING_MODE_RING, 1759 .flags = 0, 1760 }; 1761 struct k3_ring_cfg fdqring_cfg = { 1762 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1763 .flags = K3_RINGACC_RING_SHARED, 1764 }; 1765 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1766 .rx_cfg = rxring_cfg, 1767 .rxfdq_cfg = fdqring_cfg, 1768 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1769 .src_tag_lo_sel = 1770 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1771 }; 1772 1773 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1774 rx_flow_cfg.rx_cfg.size = max_desc_num; 1775 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1776 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1777 1778 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1779 i, &rx_flow_cfg); 1780 if (ret) { 1781 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1782 goto err; 1783 } 1784 if (!i) 1785 fdqring_id = 1786 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1787 i); 1788 1789 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1790 1791 if (rx_chn->irq <= 0) { 1792 dev_err(dev, "Failed to get rx dma irq %d\n", 1793 rx_chn->irq); 1794 ret = -ENXIO; 1795 goto err; 1796 } 1797 } 1798 1799 netif_napi_add(common->dma_ndev, &common->napi_rx, 1800 am65_cpsw_nuss_rx_poll); 1801 1802 ret = devm_request_irq(dev, rx_chn->irq, 1803 am65_cpsw_nuss_rx_irq, 1804 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1805 if (ret) { 1806 dev_err(dev, "failure requesting rx irq %u, %d\n", 1807 rx_chn->irq, ret); 1808 goto err; 1809 } 1810 1811 err: 1812 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1813 if (i) { 1814 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1815 return i; 1816 } 1817 1818 return ret; 1819 } 1820 1821 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1822 { 1823 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1824 1825 host_p->common = common; 1826 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1827 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1828 1829 return 0; 1830 } 1831 1832 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1833 int slave, u8 *mac_addr) 1834 { 1835 u32 mac_lo, mac_hi, offset; 1836 struct regmap *syscon; 1837 int ret; 1838 1839 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1840 if (IS_ERR(syscon)) { 1841 if (PTR_ERR(syscon) == -ENODEV) 1842 return 0; 1843 return PTR_ERR(syscon); 1844 } 1845 1846 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1847 &offset); 1848 if (ret) 1849 return ret; 1850 1851 regmap_read(syscon, offset, &mac_lo); 1852 regmap_read(syscon, offset + 4, &mac_hi); 1853 1854 mac_addr[0] = (mac_hi >> 8) & 0xff; 1855 mac_addr[1] = mac_hi & 0xff; 1856 mac_addr[2] = (mac_lo >> 24) & 0xff; 1857 mac_addr[3] = (mac_lo >> 16) & 0xff; 1858 mac_addr[4] = (mac_lo >> 8) & 0xff; 1859 mac_addr[5] = mac_lo & 0xff; 1860 1861 return 0; 1862 } 1863 1864 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1865 { 1866 struct device *dev = common->dev; 1867 struct device_node *node; 1868 struct am65_cpts *cpts; 1869 void __iomem *reg_base; 1870 1871 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1872 return 0; 1873 1874 node = of_get_child_by_name(dev->of_node, "cpts"); 1875 if (!node) { 1876 dev_err(dev, "%s cpts not found\n", __func__); 1877 return -ENOENT; 1878 } 1879 1880 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1881 cpts = am65_cpts_create(dev, reg_base, node); 1882 if (IS_ERR(cpts)) { 1883 int ret = PTR_ERR(cpts); 1884 1885 of_node_put(node); 1886 if (ret == -EOPNOTSUPP) { 1887 dev_info(dev, "cpts disabled\n"); 1888 return 0; 1889 } 1890 1891 dev_err(dev, "cpts create err %d\n", ret); 1892 return ret; 1893 } 1894 common->cpts = cpts; 1895 /* Forbid PM runtime if CPTS is running. 1896 * K3 CPSWxG modules may completely lose context during ON->OFF 1897 * transitions depending on integration. 1898 * AM65x/J721E MCU CPSW2G: false 1899 * J721E MAIN_CPSW9G: true 1900 */ 1901 pm_runtime_forbid(dev); 1902 1903 return 0; 1904 } 1905 1906 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1907 { 1908 struct device_node *node, *port_np; 1909 struct device *dev = common->dev; 1910 int ret; 1911 1912 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1913 if (!node) 1914 return -ENOENT; 1915 1916 for_each_child_of_node(node, port_np) { 1917 struct am65_cpsw_port *port; 1918 u32 port_id; 1919 1920 /* it is not a slave port node, continue */ 1921 if (strcmp(port_np->name, "port")) 1922 continue; 1923 1924 ret = of_property_read_u32(port_np, "reg", &port_id); 1925 if (ret < 0) { 1926 dev_err(dev, "%pOF error reading port_id %d\n", 1927 port_np, ret); 1928 goto of_node_put; 1929 } 1930 1931 if (!port_id || port_id > common->port_num) { 1932 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1933 port_np, port_id, port_np->name); 1934 ret = -EINVAL; 1935 goto of_node_put; 1936 } 1937 1938 port = am65_common_get_port(common, port_id); 1939 port->port_id = port_id; 1940 port->common = common; 1941 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1942 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1943 if (common->pdata.extra_modes) 1944 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 1945 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1946 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1947 port->name = of_get_property(port_np, "label", NULL); 1948 port->fetch_ram_base = 1949 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1950 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1951 1952 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1953 if (IS_ERR(port->slave.mac_sl)) { 1954 ret = PTR_ERR(port->slave.mac_sl); 1955 goto of_node_put; 1956 } 1957 1958 port->disabled = !of_device_is_available(port_np); 1959 if (port->disabled) { 1960 common->disabled_ports_mask |= BIT(port->port_id); 1961 continue; 1962 } 1963 1964 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1965 if (IS_ERR(port->slave.ifphy)) { 1966 ret = PTR_ERR(port->slave.ifphy); 1967 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1968 port_np, ret); 1969 goto of_node_put; 1970 } 1971 1972 port->slave.mac_only = 1973 of_property_read_bool(port_np, "ti,mac-only"); 1974 1975 /* get phy/link info */ 1976 port->slave.phy_node = port_np; 1977 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1978 if (ret) { 1979 dev_err(dev, "%pOF read phy-mode err %d\n", 1980 port_np, ret); 1981 goto of_node_put; 1982 } 1983 1984 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 1985 if (ret) 1986 goto of_node_put; 1987 1988 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1989 if (ret) { 1990 am65_cpsw_am654_get_efuse_macid(port_np, 1991 port->port_id, 1992 port->slave.mac_addr); 1993 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1994 eth_random_addr(port->slave.mac_addr); 1995 dev_err(dev, "Use random MAC address\n"); 1996 } 1997 } 1998 } 1999 of_node_put(node); 2000 2001 /* is there at least one ext.port */ 2002 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2003 dev_err(dev, "No Ext. port are available\n"); 2004 return -ENODEV; 2005 } 2006 2007 return 0; 2008 2009 of_node_put: 2010 of_node_put(port_np); 2011 of_node_put(node); 2012 return ret; 2013 } 2014 2015 static void am65_cpsw_pcpu_stats_free(void *data) 2016 { 2017 struct am65_cpsw_ndev_stats __percpu *stats = data; 2018 2019 free_percpu(stats); 2020 } 2021 2022 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2023 { 2024 struct am65_cpsw_port *port; 2025 int i; 2026 2027 for (i = 0; i < common->port_num; i++) { 2028 port = &common->ports[i]; 2029 if (port->slave.phylink) 2030 phylink_destroy(port->slave.phylink); 2031 } 2032 } 2033 2034 static int 2035 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2036 { 2037 struct am65_cpsw_ndev_priv *ndev_priv; 2038 struct device *dev = common->dev; 2039 struct am65_cpsw_port *port; 2040 struct phylink *phylink; 2041 int ret; 2042 2043 port = &common->ports[port_idx]; 2044 2045 if (port->disabled) 2046 return 0; 2047 2048 /* alloc netdev */ 2049 port->ndev = devm_alloc_etherdev_mqs(common->dev, 2050 sizeof(struct am65_cpsw_ndev_priv), 2051 AM65_CPSW_MAX_TX_QUEUES, 2052 AM65_CPSW_MAX_RX_QUEUES); 2053 if (!port->ndev) { 2054 dev_err(dev, "error allocating slave net_device %u\n", 2055 port->port_id); 2056 return -ENOMEM; 2057 } 2058 2059 ndev_priv = netdev_priv(port->ndev); 2060 ndev_priv->port = port; 2061 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2062 SET_NETDEV_DEV(port->ndev, dev); 2063 2064 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2065 2066 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2067 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 2068 port->ndev->hw_features = NETIF_F_SG | 2069 NETIF_F_RXCSUM | 2070 NETIF_F_HW_CSUM | 2071 NETIF_F_HW_TC; 2072 port->ndev->features = port->ndev->hw_features | 2073 NETIF_F_HW_VLAN_CTAG_FILTER; 2074 port->ndev->vlan_features |= NETIF_F_SG; 2075 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2076 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2077 2078 /* Configuring Phylink */ 2079 port->slave.phylink_config.dev = &port->ndev->dev; 2080 port->slave.phylink_config.type = PHYLINK_NETDEV; 2081 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 2082 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2083 2084 if (phy_interface_mode_is_rgmii(port->slave.phy_if)) { 2085 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2086 } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) { 2087 __set_bit(PHY_INTERFACE_MODE_RMII, 2088 port->slave.phylink_config.supported_interfaces); 2089 } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2090 __set_bit(PHY_INTERFACE_MODE_QSGMII, 2091 port->slave.phylink_config.supported_interfaces); 2092 } else { 2093 dev_err(dev, "selected phy-mode is not supported\n"); 2094 return -EOPNOTSUPP; 2095 } 2096 2097 phylink = phylink_create(&port->slave.phylink_config, 2098 of_node_to_fwnode(port->slave.phy_node), 2099 port->slave.phy_if, 2100 &am65_cpsw_phylink_mac_ops); 2101 if (IS_ERR(phylink)) 2102 return PTR_ERR(phylink); 2103 2104 port->slave.phylink = phylink; 2105 2106 /* Disable TX checksum offload by default due to HW bug */ 2107 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2108 port->ndev->features &= ~NETIF_F_HW_CSUM; 2109 2110 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2111 if (!ndev_priv->stats) 2112 return -ENOMEM; 2113 2114 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2115 ndev_priv->stats); 2116 if (ret) 2117 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2118 2119 if (!common->dma_ndev) 2120 common->dma_ndev = port->ndev; 2121 2122 return ret; 2123 } 2124 2125 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2126 { 2127 int ret; 2128 int i; 2129 2130 for (i = 0; i < common->port_num; i++) { 2131 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2132 if (ret) 2133 return ret; 2134 } 2135 2136 return ret; 2137 } 2138 2139 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2140 { 2141 struct am65_cpsw_port *port; 2142 int i; 2143 2144 for (i = 0; i < common->port_num; i++) { 2145 port = &common->ports[i]; 2146 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED) 2147 unregister_netdev(port->ndev); 2148 } 2149 } 2150 2151 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2152 { 2153 int set_val = 0; 2154 int i; 2155 2156 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2157 set_val = 1; 2158 2159 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2160 2161 for (i = 1; i <= common->port_num; i++) { 2162 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2163 struct am65_cpsw_ndev_priv *priv; 2164 2165 if (!port->ndev) 2166 continue; 2167 2168 priv = am65_ndev_to_priv(port->ndev); 2169 priv->offload_fwd_mark = set_val; 2170 } 2171 } 2172 2173 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2174 { 2175 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2176 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2177 2178 return !common->is_emac_mode; 2179 } 2180 2181 return false; 2182 } 2183 2184 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2185 struct net_device *br_ndev, 2186 struct netlink_ext_ack *extack) 2187 { 2188 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2189 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2190 int err; 2191 2192 if (!common->br_members) { 2193 common->hw_bridge_dev = br_ndev; 2194 } else { 2195 /* This is adding the port to a second bridge, this is 2196 * unsupported 2197 */ 2198 if (common->hw_bridge_dev != br_ndev) 2199 return -EOPNOTSUPP; 2200 } 2201 2202 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2203 false, extack); 2204 if (err) 2205 return err; 2206 2207 common->br_members |= BIT(priv->port->port_id); 2208 2209 am65_cpsw_port_offload_fwd_mark_update(common); 2210 2211 return NOTIFY_DONE; 2212 } 2213 2214 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2215 { 2216 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2217 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2218 2219 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2220 2221 common->br_members &= ~BIT(priv->port->port_id); 2222 2223 am65_cpsw_port_offload_fwd_mark_update(common); 2224 2225 if (!common->br_members) 2226 common->hw_bridge_dev = NULL; 2227 } 2228 2229 /* netdev notifier */ 2230 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2231 unsigned long event, void *ptr) 2232 { 2233 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2234 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2235 struct netdev_notifier_changeupper_info *info; 2236 int ret = NOTIFY_DONE; 2237 2238 if (!am65_cpsw_port_dev_check(ndev)) 2239 return NOTIFY_DONE; 2240 2241 switch (event) { 2242 case NETDEV_CHANGEUPPER: 2243 info = ptr; 2244 2245 if (netif_is_bridge_master(info->upper_dev)) { 2246 if (info->linking) 2247 ret = am65_cpsw_netdevice_port_link(ndev, 2248 info->upper_dev, 2249 extack); 2250 else 2251 am65_cpsw_netdevice_port_unlink(ndev); 2252 } 2253 break; 2254 default: 2255 return NOTIFY_DONE; 2256 } 2257 2258 return notifier_from_errno(ret); 2259 } 2260 2261 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2262 { 2263 int ret = 0; 2264 2265 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2266 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2267 return 0; 2268 2269 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2270 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2271 if (ret) { 2272 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2273 return ret; 2274 } 2275 2276 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2277 if (ret) 2278 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2279 2280 return ret; 2281 } 2282 2283 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2284 { 2285 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2286 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2287 return; 2288 2289 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2290 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2291 } 2292 2293 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2294 2295 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2296 { 2297 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2298 ALE_MCAST_BLOCK_LEARN_FWD); 2299 } 2300 2301 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2302 { 2303 struct am65_cpsw_host *host = am65_common_get_host(common); 2304 2305 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2306 2307 am65_cpsw_init_stp_ale_entry(common); 2308 2309 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2310 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2311 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2312 } 2313 2314 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2315 { 2316 struct am65_cpsw_host *host = am65_common_get_host(common); 2317 2318 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2319 2320 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2321 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2322 2323 /* learning make no sense in multi-mac mode */ 2324 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2325 } 2326 2327 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2328 struct devlink_param_gset_ctx *ctx) 2329 { 2330 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2331 struct am65_cpsw_common *common = dl_priv->common; 2332 2333 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2334 2335 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2336 return -EOPNOTSUPP; 2337 2338 ctx->val.vbool = !common->is_emac_mode; 2339 2340 return 0; 2341 } 2342 2343 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2344 { 2345 struct am65_cpsw_slave_data *slave = &port->slave; 2346 struct am65_cpsw_common *common = port->common; 2347 u32 port_mask; 2348 2349 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2350 2351 if (slave->mac_only) 2352 /* enable mac-only mode on port */ 2353 cpsw_ale_control_set(common->ale, port->port_id, 2354 ALE_PORT_MACONLY, 1); 2355 2356 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2357 2358 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2359 2360 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2361 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2362 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2363 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2364 } 2365 2366 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2367 { 2368 struct am65_cpsw_slave_data *slave = &port->slave; 2369 struct am65_cpsw_common *cpsw = port->common; 2370 u32 port_mask; 2371 2372 cpsw_ale_control_set(cpsw->ale, port->port_id, 2373 ALE_PORT_NOLEARN, 0); 2374 2375 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2376 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2377 slave->port_vlan); 2378 2379 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2380 2381 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2382 port_mask, ALE_VLAN, slave->port_vlan, 2383 ALE_MCAST_FWD_2); 2384 2385 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2386 2387 cpsw_ale_control_set(cpsw->ale, port->port_id, 2388 ALE_PORT_MACONLY, 0); 2389 } 2390 2391 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2392 struct devlink_param_gset_ctx *ctx) 2393 { 2394 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2395 struct am65_cpsw_common *cpsw = dl_priv->common; 2396 bool switch_en = ctx->val.vbool; 2397 bool if_running = false; 2398 int i; 2399 2400 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2401 2402 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2403 return -EOPNOTSUPP; 2404 2405 if (switch_en == !cpsw->is_emac_mode) 2406 return 0; 2407 2408 if (!switch_en && cpsw->br_members) { 2409 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2410 return -EINVAL; 2411 } 2412 2413 rtnl_lock(); 2414 2415 cpsw->is_emac_mode = !switch_en; 2416 2417 for (i = 0; i < cpsw->port_num; i++) { 2418 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2419 2420 if (!sl_ndev || !netif_running(sl_ndev)) 2421 continue; 2422 2423 if_running = true; 2424 } 2425 2426 if (!if_running) { 2427 /* all ndevs are down */ 2428 for (i = 0; i < cpsw->port_num; i++) { 2429 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2430 struct am65_cpsw_slave_data *slave; 2431 2432 if (!sl_ndev) 2433 continue; 2434 2435 slave = am65_ndev_to_slave(sl_ndev); 2436 if (switch_en) 2437 slave->port_vlan = cpsw->default_vlan; 2438 else 2439 slave->port_vlan = 0; 2440 } 2441 2442 goto exit; 2443 } 2444 2445 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2446 /* clean up ALE table */ 2447 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2448 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2449 2450 if (switch_en) { 2451 dev_info(cpsw->dev, "Enable switch mode\n"); 2452 2453 am65_cpsw_init_host_port_switch(cpsw); 2454 2455 for (i = 0; i < cpsw->port_num; i++) { 2456 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2457 struct am65_cpsw_slave_data *slave; 2458 struct am65_cpsw_port *port; 2459 2460 if (!sl_ndev) 2461 continue; 2462 2463 port = am65_ndev_to_port(sl_ndev); 2464 slave = am65_ndev_to_slave(sl_ndev); 2465 slave->port_vlan = cpsw->default_vlan; 2466 2467 if (netif_running(sl_ndev)) 2468 am65_cpsw_init_port_switch_ale(port); 2469 } 2470 2471 } else { 2472 dev_info(cpsw->dev, "Disable switch mode\n"); 2473 2474 am65_cpsw_init_host_port_emac(cpsw); 2475 2476 for (i = 0; i < cpsw->port_num; i++) { 2477 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2478 struct am65_cpsw_port *port; 2479 2480 if (!sl_ndev) 2481 continue; 2482 2483 port = am65_ndev_to_port(sl_ndev); 2484 port->slave.port_vlan = 0; 2485 if (netif_running(sl_ndev)) 2486 am65_cpsw_init_port_emac_ale(port); 2487 } 2488 } 2489 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2490 exit: 2491 rtnl_unlock(); 2492 2493 return 0; 2494 } 2495 2496 static const struct devlink_param am65_cpsw_devlink_params[] = { 2497 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2498 DEVLINK_PARAM_TYPE_BOOL, 2499 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2500 am65_cpsw_dl_switch_mode_get, 2501 am65_cpsw_dl_switch_mode_set, NULL), 2502 }; 2503 2504 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2505 { 2506 struct devlink_port_attrs attrs = {}; 2507 struct am65_cpsw_devlink *dl_priv; 2508 struct device *dev = common->dev; 2509 struct devlink_port *dl_port; 2510 struct am65_cpsw_port *port; 2511 int ret = 0; 2512 int i; 2513 2514 common->devlink = 2515 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2516 if (!common->devlink) 2517 return -ENOMEM; 2518 2519 dl_priv = devlink_priv(common->devlink); 2520 dl_priv->common = common; 2521 2522 /* Provide devlink hook to switch mode when multiple external ports 2523 * are present NUSS switchdev driver is enabled. 2524 */ 2525 if (!AM65_CPSW_IS_CPSW2G(common) && 2526 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2527 ret = devlink_params_register(common->devlink, 2528 am65_cpsw_devlink_params, 2529 ARRAY_SIZE(am65_cpsw_devlink_params)); 2530 if (ret) { 2531 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2532 goto dl_unreg; 2533 } 2534 } 2535 2536 for (i = 1; i <= common->port_num; i++) { 2537 port = am65_common_get_port(common, i); 2538 dl_port = &port->devlink_port; 2539 2540 if (port->ndev) 2541 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2542 else 2543 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 2544 attrs.phys.port_number = port->port_id; 2545 attrs.switch_id.id_len = sizeof(resource_size_t); 2546 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2547 devlink_port_attrs_set(dl_port, &attrs); 2548 2549 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2550 if (ret) { 2551 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2552 port->port_id, ret); 2553 goto dl_port_unreg; 2554 } 2555 } 2556 devlink_register(common->devlink); 2557 return ret; 2558 2559 dl_port_unreg: 2560 for (i = i - 1; i >= 1; i--) { 2561 port = am65_common_get_port(common, i); 2562 dl_port = &port->devlink_port; 2563 2564 devlink_port_unregister(dl_port); 2565 } 2566 dl_unreg: 2567 devlink_free(common->devlink); 2568 return ret; 2569 } 2570 2571 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2572 { 2573 struct devlink_port *dl_port; 2574 struct am65_cpsw_port *port; 2575 int i; 2576 2577 devlink_unregister(common->devlink); 2578 2579 for (i = 1; i <= common->port_num; i++) { 2580 port = am65_common_get_port(common, i); 2581 dl_port = &port->devlink_port; 2582 2583 devlink_port_unregister(dl_port); 2584 } 2585 2586 if (!AM65_CPSW_IS_CPSW2G(common) && 2587 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2588 devlink_params_unregister(common->devlink, 2589 am65_cpsw_devlink_params, 2590 ARRAY_SIZE(am65_cpsw_devlink_params)); 2591 2592 devlink_free(common->devlink); 2593 } 2594 2595 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2596 { 2597 struct device *dev = common->dev; 2598 struct am65_cpsw_port *port; 2599 int ret = 0, i; 2600 2601 /* init tx channels */ 2602 ret = am65_cpsw_nuss_init_tx_chns(common); 2603 if (ret) 2604 return ret; 2605 ret = am65_cpsw_nuss_init_rx_chns(common); 2606 if (ret) 2607 return ret; 2608 2609 ret = am65_cpsw_nuss_register_devlink(common); 2610 if (ret) 2611 return ret; 2612 2613 for (i = 0; i < common->port_num; i++) { 2614 port = &common->ports[i]; 2615 2616 if (!port->ndev) 2617 continue; 2618 2619 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 2620 2621 ret = register_netdev(port->ndev); 2622 if (ret) { 2623 dev_err(dev, "error registering slave net device%i %d\n", 2624 i, ret); 2625 goto err_cleanup_ndev; 2626 } 2627 } 2628 2629 ret = am65_cpsw_register_notifiers(common); 2630 if (ret) 2631 goto err_cleanup_ndev; 2632 2633 /* can't auto unregister ndev using devm_add_action() due to 2634 * devres release sequence in DD core for DMA 2635 */ 2636 2637 return 0; 2638 2639 err_cleanup_ndev: 2640 am65_cpsw_nuss_cleanup_ndev(common); 2641 am65_cpsw_unregister_devlink(common); 2642 2643 return ret; 2644 } 2645 2646 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2647 { 2648 int ret; 2649 2650 common->tx_ch_num = num_tx; 2651 ret = am65_cpsw_nuss_init_tx_chns(common); 2652 2653 return ret; 2654 } 2655 2656 struct am65_cpsw_soc_pdata { 2657 u32 quirks_dis; 2658 }; 2659 2660 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2661 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2662 }; 2663 2664 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2665 { .family = "AM65X", 2666 .revision = "SR2.0", 2667 .data = &am65x_soc_sr2_0 2668 }, 2669 {/* sentinel */} 2670 }; 2671 2672 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2673 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2674 .ale_dev_id = "am65x-cpsw2g", 2675 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2676 }; 2677 2678 static const struct am65_cpsw_pdata j721e_pdata = { 2679 .quirks = 0, 2680 .ale_dev_id = "am65x-cpsw2g", 2681 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2682 }; 2683 2684 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2685 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 2686 .ale_dev_id = "am64-cpswxg", 2687 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2688 }; 2689 2690 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2691 .quirks = 0, 2692 .ale_dev_id = "am64-cpswxg", 2693 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2694 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2695 }; 2696 2697 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2698 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2699 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2700 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2701 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2702 { /* sentinel */ }, 2703 }; 2704 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2705 2706 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2707 { 2708 const struct soc_device_attribute *soc; 2709 2710 soc = soc_device_match(am65_cpsw_socinfo); 2711 if (soc && soc->data) { 2712 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2713 2714 /* disable quirks */ 2715 common->pdata.quirks &= ~socdata->quirks_dis; 2716 } 2717 } 2718 2719 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2720 { 2721 struct cpsw_ale_params ale_params = { 0 }; 2722 const struct of_device_id *of_id; 2723 struct device *dev = &pdev->dev; 2724 struct am65_cpsw_common *common; 2725 struct device_node *node; 2726 struct resource *res; 2727 struct clk *clk; 2728 u64 id_temp; 2729 int ret, i; 2730 int ale_entries; 2731 2732 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2733 if (!common) 2734 return -ENOMEM; 2735 common->dev = dev; 2736 2737 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2738 if (!of_id) 2739 return -EINVAL; 2740 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2741 2742 am65_cpsw_nuss_apply_socinfo(common); 2743 2744 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2745 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2746 if (IS_ERR(common->ss_base)) 2747 return PTR_ERR(common->ss_base); 2748 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2749 /* Use device's physical base address as switch id */ 2750 id_temp = cpu_to_be64(res->start); 2751 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2752 2753 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2754 if (!node) 2755 return -ENOENT; 2756 common->port_num = of_get_child_count(node); 2757 of_node_put(node); 2758 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2759 return -ENOENT; 2760 2761 common->rx_flow_id_base = -1; 2762 init_completion(&common->tdown_complete); 2763 common->tx_ch_num = 1; 2764 common->pf_p0_rx_ptype_rrobin = false; 2765 common->default_vlan = 1; 2766 2767 common->ports = devm_kcalloc(dev, common->port_num, 2768 sizeof(*common->ports), 2769 GFP_KERNEL); 2770 if (!common->ports) 2771 return -ENOMEM; 2772 2773 clk = devm_clk_get(dev, "fck"); 2774 if (IS_ERR(clk)) 2775 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2776 common->bus_freq = clk_get_rate(clk); 2777 2778 pm_runtime_enable(dev); 2779 ret = pm_runtime_resume_and_get(dev); 2780 if (ret < 0) { 2781 pm_runtime_disable(dev); 2782 return ret; 2783 } 2784 2785 node = of_get_child_by_name(dev->of_node, "mdio"); 2786 if (!node) { 2787 dev_warn(dev, "MDIO node not found\n"); 2788 } else if (of_device_is_available(node)) { 2789 struct platform_device *mdio_pdev; 2790 2791 mdio_pdev = of_platform_device_create(node, NULL, dev); 2792 if (!mdio_pdev) { 2793 ret = -ENODEV; 2794 goto err_pm_clear; 2795 } 2796 2797 common->mdio_dev = &mdio_pdev->dev; 2798 } 2799 of_node_put(node); 2800 2801 am65_cpsw_nuss_get_ver(common); 2802 2803 ret = am65_cpsw_nuss_init_host_p(common); 2804 if (ret) 2805 goto err_of_clear; 2806 2807 ret = am65_cpsw_nuss_init_slave_ports(common); 2808 if (ret) 2809 goto err_of_clear; 2810 2811 /* init common data */ 2812 ale_params.dev = dev; 2813 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2814 ale_params.ale_ports = common->port_num + 1; 2815 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2816 ale_params.dev_id = common->pdata.ale_dev_id; 2817 ale_params.bus_freq = common->bus_freq; 2818 2819 common->ale = cpsw_ale_create(&ale_params); 2820 if (IS_ERR(common->ale)) { 2821 dev_err(dev, "error initializing ale engine\n"); 2822 ret = PTR_ERR(common->ale); 2823 goto err_of_clear; 2824 } 2825 2826 ale_entries = common->ale->params.ale_entries; 2827 common->ale_context = devm_kzalloc(dev, 2828 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 2829 GFP_KERNEL); 2830 ret = am65_cpsw_init_cpts(common); 2831 if (ret) 2832 goto err_of_clear; 2833 2834 /* init ports */ 2835 for (i = 0; i < common->port_num; i++) 2836 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2837 2838 dev_set_drvdata(dev, common); 2839 2840 common->is_emac_mode = true; 2841 2842 ret = am65_cpsw_nuss_init_ndevs(common); 2843 if (ret) 2844 goto err_free_phylink; 2845 2846 ret = am65_cpsw_nuss_register_ndevs(common); 2847 if (ret) 2848 goto err_free_phylink; 2849 2850 pm_runtime_put(dev); 2851 return 0; 2852 2853 err_free_phylink: 2854 am65_cpsw_nuss_phylink_cleanup(common); 2855 err_of_clear: 2856 of_platform_device_destroy(common->mdio_dev, NULL); 2857 err_pm_clear: 2858 pm_runtime_put_sync(dev); 2859 pm_runtime_disable(dev); 2860 return ret; 2861 } 2862 2863 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2864 { 2865 struct device *dev = &pdev->dev; 2866 struct am65_cpsw_common *common; 2867 int ret; 2868 2869 common = dev_get_drvdata(dev); 2870 2871 ret = pm_runtime_resume_and_get(&pdev->dev); 2872 if (ret < 0) 2873 return ret; 2874 2875 am65_cpsw_unregister_devlink(common); 2876 am65_cpsw_unregister_notifiers(common); 2877 2878 /* must unregister ndevs here because DD release_driver routine calls 2879 * dma_deconfigure(dev) before devres_release_all(dev) 2880 */ 2881 am65_cpsw_nuss_cleanup_ndev(common); 2882 am65_cpsw_nuss_phylink_cleanup(common); 2883 2884 of_platform_device_destroy(common->mdio_dev, NULL); 2885 2886 pm_runtime_put_sync(&pdev->dev); 2887 pm_runtime_disable(&pdev->dev); 2888 return 0; 2889 } 2890 2891 static int am65_cpsw_nuss_suspend(struct device *dev) 2892 { 2893 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2894 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2895 struct am65_cpsw_port *port; 2896 struct net_device *ndev; 2897 int i, ret; 2898 2899 cpsw_ale_dump(common->ale, common->ale_context); 2900 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2901 for (i = 0; i < common->port_num; i++) { 2902 port = &common->ports[i]; 2903 ndev = port->ndev; 2904 2905 if (!ndev) 2906 continue; 2907 2908 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2909 netif_device_detach(ndev); 2910 if (netif_running(ndev)) { 2911 rtnl_lock(); 2912 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 2913 rtnl_unlock(); 2914 if (ret < 0) { 2915 netdev_err(ndev, "failed to stop: %d", ret); 2916 return ret; 2917 } 2918 } 2919 } 2920 2921 am65_cpts_suspend(common->cpts); 2922 2923 am65_cpsw_nuss_remove_rx_chns(common); 2924 am65_cpsw_nuss_remove_tx_chns(common); 2925 2926 return 0; 2927 } 2928 2929 static int am65_cpsw_nuss_resume(struct device *dev) 2930 { 2931 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2932 struct am65_cpsw_port *port; 2933 struct net_device *ndev; 2934 int i, ret; 2935 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2936 2937 ret = am65_cpsw_nuss_init_tx_chns(common); 2938 if (ret) 2939 return ret; 2940 ret = am65_cpsw_nuss_init_rx_chns(common); 2941 if (ret) 2942 return ret; 2943 2944 /* If RX IRQ was disabled before suspend, keep it disabled */ 2945 if (common->rx_irq_disabled) 2946 disable_irq(common->rx_chns.irq); 2947 2948 am65_cpts_resume(common->cpts); 2949 2950 for (i = 0; i < common->port_num; i++) { 2951 port = &common->ports[i]; 2952 ndev = port->ndev; 2953 2954 if (!ndev) 2955 continue; 2956 2957 if (netif_running(ndev)) { 2958 rtnl_lock(); 2959 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 2960 rtnl_unlock(); 2961 if (ret < 0) { 2962 netdev_err(ndev, "failed to start: %d", ret); 2963 return ret; 2964 } 2965 } 2966 2967 netif_device_attach(ndev); 2968 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2969 } 2970 2971 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2972 cpsw_ale_restore(common->ale, common->ale_context); 2973 2974 return 0; 2975 } 2976 2977 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 2978 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 2979 }; 2980 2981 static struct platform_driver am65_cpsw_nuss_driver = { 2982 .driver = { 2983 .name = AM65_CPSW_DRV_NAME, 2984 .of_match_table = am65_cpsw_nuss_of_mtable, 2985 .pm = &am65_cpsw_nuss_dev_pm_ops, 2986 }, 2987 .probe = am65_cpsw_nuss_probe, 2988 .remove = am65_cpsw_nuss_remove, 2989 }; 2990 2991 module_platform_driver(am65_cpsw_nuss_driver); 2992 2993 MODULE_LICENSE("GPL v2"); 2994 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2995 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2996