1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/bpf_trace.h> 9 #include <linux/clk.h> 10 #include <linux/etherdevice.h> 11 #include <linux/if_vlan.h> 12 #include <linux/interrupt.h> 13 #include <linux/irqdomain.h> 14 #include <linux/kernel.h> 15 #include <linux/kmemleak.h> 16 #include <linux/module.h> 17 #include <linux/netdevice.h> 18 #include <linux/net_tstamp.h> 19 #include <linux/of.h> 20 #include <linux/of_mdio.h> 21 #include <linux/of_net.h> 22 #include <linux/of_device.h> 23 #include <linux/of_platform.h> 24 #include <linux/phylink.h> 25 #include <linux/phy/phy.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regmap.h> 29 #include <linux/rtnetlink.h> 30 #include <linux/mfd/syscon.h> 31 #include <linux/sys_soc.h> 32 #include <linux/dma/ti-cppi5.h> 33 #include <linux/dma/k3-udma-glue.h> 34 #include <net/page_pool/helpers.h> 35 #include <net/switchdev.h> 36 37 #include "cpsw_ale.h" 38 #include "cpsw_sl.h" 39 #include "am65-cpsw-nuss.h" 40 #include "am65-cpsw-switchdev.h" 41 #include "k3-cppi-desc-pool.h" 42 #include "am65-cpts.h" 43 44 #define AM65_CPSW_SS_BASE 0x0 45 #define AM65_CPSW_SGMII_BASE 0x100 46 #define AM65_CPSW_XGMII_BASE 0x2100 47 #define AM65_CPSW_CPSW_NU_BASE 0x20000 48 #define AM65_CPSW_NU_PORTS_BASE 0x1000 49 #define AM65_CPSW_NU_FRAM_BASE 0x12000 50 #define AM65_CPSW_NU_STATS_BASE 0x1a000 51 #define AM65_CPSW_NU_ALE_BASE 0x1e000 52 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 53 54 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 55 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 56 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 57 58 #define AM65_CPSW_MAX_PORTS 8 59 60 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 61 #define AM65_CPSW_MAX_PACKET_SIZE 2024 62 63 #define AM65_CPSW_REG_CTL 0x004 64 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 65 #define AM65_CPSW_REG_PTYPE 0x018 66 67 #define AM65_CPSW_P0_REG_CTL 0x004 68 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 69 70 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 71 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 72 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 73 74 #define AM65_CPSW_PORTN_REG_SA_L 0x308 75 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 76 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 77 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 78 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 79 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 80 81 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 82 #define AM65_CPSW_SGMII_MR_ADV_ABILITY_REG 0x018 83 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 84 85 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 86 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 87 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 88 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 89 90 /* AM65_CPSW_P0_REG_CTL */ 91 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 92 #define AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN BIT(16) 93 94 /* AM65_CPSW_PORT_REG_PRI_CTL */ 95 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 96 97 /* AM65_CPSW_PN_TS_CTL register fields */ 98 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 99 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 100 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 101 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 102 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 103 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 104 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 105 106 #define AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN BIT(0) 107 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN BIT(1) 108 #define AM65_CPSW_PN_TS_CTL_RX_VLAN_LT2_EN BIT(2) 109 #define AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN BIT(3) 110 #define AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN BIT(9) 111 112 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 113 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 114 115 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 116 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 117 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 118 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 119 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 120 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 121 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 122 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 123 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 124 125 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 126 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 127 128 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 129 130 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 131 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 132 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 133 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 134 135 #define AM65_CPSW_TS_RX_ANX_ALL_EN \ 136 (AM65_CPSW_PN_TS_CTL_RX_ANX_D_EN | \ 137 AM65_CPSW_PN_TS_CTL_RX_ANX_E_EN | \ 138 AM65_CPSW_PN_TS_CTL_RX_ANX_F_EN) 139 140 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 141 /* Number of TX/RX descriptors per channel/flow */ 142 #define AM65_CPSW_MAX_TX_DESC 500 143 #define AM65_CPSW_MAX_RX_DESC 500 144 145 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 146 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 147 148 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 149 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 150 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 151 152 #define AM65_CPSW_DEFAULT_TX_CHNS 8 153 #define AM65_CPSW_DEFAULT_RX_CHN_FLOWS 1 154 155 /* CPPI streaming packet interface */ 156 #define AM65_CPSW_CPPI_TX_FLOW_ID 0x3FFF 157 #define AM65_CPSW_CPPI_TX_PKT_TYPE 0x7 158 159 /* XDP */ 160 #define AM65_CPSW_XDP_CONSUMED BIT(1) 161 #define AM65_CPSW_XDP_REDIRECT BIT(0) 162 #define AM65_CPSW_XDP_PASS 0 163 164 /* Include headroom compatible with both skb and xdpf */ 165 #define AM65_CPSW_HEADROOM_NA (max(NET_SKB_PAD, XDP_PACKET_HEADROOM) + NET_IP_ALIGN) 166 #define AM65_CPSW_HEADROOM ALIGN(AM65_CPSW_HEADROOM_NA, sizeof(long)) 167 168 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 169 const u8 *dev_addr) 170 { 171 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 172 (dev_addr[2] << 16) | (dev_addr[3] << 24); 173 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 174 175 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 176 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 177 } 178 179 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 180 { 181 cpsw_sl_reset(port->slave.mac_sl, 100); 182 /* Max length register has to be restored after MAC SL reset */ 183 writel(AM65_CPSW_MAX_PACKET_SIZE, 184 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 185 } 186 187 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 188 { 189 common->nuss_ver = readl(common->ss_base); 190 common->cpsw_ver = readl(common->cpsw_base); 191 dev_info(common->dev, 192 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 193 common->nuss_ver, 194 common->cpsw_ver, 195 common->port_num + 1, 196 common->pdata.quirks); 197 } 198 199 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 200 __be16 proto, u16 vid) 201 { 202 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 203 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 204 u32 port_mask, unreg_mcast = 0; 205 int ret; 206 207 if (!common->is_emac_mode) 208 return 0; 209 210 if (!netif_running(ndev) || !vid) 211 return 0; 212 213 ret = pm_runtime_resume_and_get(common->dev); 214 if (ret < 0) 215 return ret; 216 217 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 218 if (!vid) 219 unreg_mcast = port_mask; 220 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 221 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 222 unreg_mcast, port_mask, 0); 223 224 pm_runtime_put(common->dev); 225 return ret; 226 } 227 228 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 229 __be16 proto, u16 vid) 230 { 231 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 232 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 233 int ret; 234 235 if (!common->is_emac_mode) 236 return 0; 237 238 if (!netif_running(ndev) || !vid) 239 return 0; 240 241 ret = pm_runtime_resume_and_get(common->dev); 242 if (ret < 0) 243 return ret; 244 245 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 246 ret = cpsw_ale_del_vlan(common->ale, vid, 247 BIT(port->port_id) | ALE_PORT_HOST); 248 249 pm_runtime_put(common->dev); 250 return ret; 251 } 252 253 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 254 bool promisc) 255 { 256 struct am65_cpsw_common *common = port->common; 257 258 if (promisc && !common->is_emac_mode) { 259 dev_dbg(common->dev, "promisc mode requested in switch mode"); 260 return; 261 } 262 263 if (promisc) { 264 /* Enable promiscuous mode */ 265 cpsw_ale_control_set(common->ale, port->port_id, 266 ALE_PORT_MACONLY_CAF, 1); 267 dev_dbg(common->dev, "promisc enabled\n"); 268 } else { 269 /* Disable promiscuous mode */ 270 cpsw_ale_control_set(common->ale, port->port_id, 271 ALE_PORT_MACONLY_CAF, 0); 272 dev_dbg(common->dev, "promisc disabled\n"); 273 } 274 } 275 276 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 277 { 278 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 279 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 280 u32 port_mask; 281 bool promisc; 282 283 promisc = !!(ndev->flags & IFF_PROMISC); 284 am65_cpsw_slave_set_promisc(port, promisc); 285 286 if (promisc) 287 return; 288 289 /* Restore allmulti on vlans if necessary */ 290 cpsw_ale_set_allmulti(common->ale, 291 ndev->flags & IFF_ALLMULTI, port->port_id); 292 293 port_mask = ALE_PORT_HOST; 294 /* Clear all mcast from ALE */ 295 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 296 297 if (!netdev_mc_empty(ndev)) { 298 struct netdev_hw_addr *ha; 299 300 /* program multicast address list into ALE register */ 301 netdev_for_each_mc_addr(ha, ndev) { 302 cpsw_ale_add_mcast(common->ale, ha->addr, 303 port_mask, 0, 0, 0); 304 } 305 } 306 } 307 308 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 309 unsigned int txqueue) 310 { 311 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 312 struct am65_cpsw_tx_chn *tx_chn; 313 struct netdev_queue *netif_txq; 314 unsigned long trans_start; 315 316 netif_txq = netdev_get_tx_queue(ndev, txqueue); 317 tx_chn = &common->tx_chns[txqueue]; 318 trans_start = READ_ONCE(netif_txq->trans_start); 319 320 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 321 txqueue, 322 netif_tx_queue_stopped(netif_txq), 323 jiffies_to_msecs(jiffies - trans_start), 324 netdev_queue_dql_avail(netif_txq), 325 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 326 327 if (netif_tx_queue_stopped(netif_txq)) { 328 /* try recover if stopped by us */ 329 txq_trans_update(netif_txq); 330 netif_tx_wake_queue(netif_txq); 331 } 332 } 333 334 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 335 struct page *page, u32 flow_idx) 336 { 337 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 338 struct cppi5_host_desc_t *desc_rx; 339 struct device *dev = common->dev; 340 dma_addr_t desc_dma; 341 dma_addr_t buf_dma; 342 void *swdata; 343 344 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 345 if (!desc_rx) { 346 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 347 return -ENOMEM; 348 } 349 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 350 351 buf_dma = dma_map_single(rx_chn->dma_dev, 352 page_address(page) + AM65_CPSW_HEADROOM, 353 AM65_CPSW_MAX_PACKET_SIZE, DMA_FROM_DEVICE); 354 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 355 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 356 dev_err(dev, "Failed to map rx buffer\n"); 357 return -EINVAL; 358 } 359 360 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 361 AM65_CPSW_NAV_PS_DATA_SIZE); 362 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 363 cppi5_hdesc_attach_buf(desc_rx, buf_dma, AM65_CPSW_MAX_PACKET_SIZE, 364 buf_dma, AM65_CPSW_MAX_PACKET_SIZE); 365 swdata = cppi5_hdesc_get_swdata(desc_rx); 366 *((void **)swdata) = page_address(page); 367 368 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, flow_idx, 369 desc_rx, desc_dma); 370 } 371 372 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 373 { 374 struct am65_cpsw_host *host_p = am65_common_get_host(common); 375 u32 val, pri_map; 376 377 /* P0 set Receive Priority Type */ 378 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 379 380 if (common->pf_p0_rx_ptype_rrobin) { 381 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 382 /* Enet Ports fifos works in fixed priority mode only, so 383 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 384 */ 385 pri_map = 0x0; 386 } else { 387 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 388 /* restore P0_Rx_Pri_Map */ 389 pri_map = 0x76543210; 390 } 391 392 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 393 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 394 } 395 396 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 397 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 398 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 399 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 400 401 static void am65_cpsw_destroy_xdp_rxqs(struct am65_cpsw_common *common) 402 { 403 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 404 struct am65_cpsw_rx_flow *flow; 405 struct xdp_rxq_info *rxq; 406 int id, port; 407 408 for (id = 0; id < common->rx_ch_num_flows; id++) { 409 flow = &rx_chn->flows[id]; 410 411 for (port = 0; port < common->port_num; port++) { 412 if (!common->ports[port].ndev) 413 continue; 414 415 rxq = &common->ports[port].xdp_rxq[id]; 416 417 if (xdp_rxq_info_is_reg(rxq)) 418 xdp_rxq_info_unreg(rxq); 419 } 420 421 if (flow->page_pool) { 422 page_pool_destroy(flow->page_pool); 423 flow->page_pool = NULL; 424 } 425 } 426 } 427 428 static int am65_cpsw_create_xdp_rxqs(struct am65_cpsw_common *common) 429 { 430 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 431 struct page_pool_params pp_params = { 432 .flags = PP_FLAG_DMA_MAP, 433 .order = 0, 434 .pool_size = AM65_CPSW_MAX_RX_DESC, 435 .nid = dev_to_node(common->dev), 436 .dev = common->dev, 437 .dma_dir = DMA_BIDIRECTIONAL, 438 /* .napi set dynamically */ 439 }; 440 struct am65_cpsw_rx_flow *flow; 441 struct xdp_rxq_info *rxq; 442 struct page_pool *pool; 443 int id, port, ret; 444 445 for (id = 0; id < common->rx_ch_num_flows; id++) { 446 flow = &rx_chn->flows[id]; 447 pp_params.napi = &flow->napi_rx; 448 pool = page_pool_create(&pp_params); 449 if (IS_ERR(pool)) { 450 ret = PTR_ERR(pool); 451 goto err; 452 } 453 454 flow->page_pool = pool; 455 456 /* using same page pool is allowed as no running rx handlers 457 * simultaneously for both ndevs 458 */ 459 for (port = 0; port < common->port_num; port++) { 460 if (!common->ports[port].ndev) 461 continue; 462 463 rxq = &common->ports[port].xdp_rxq[id]; 464 465 ret = xdp_rxq_info_reg(rxq, common->ports[port].ndev, 466 id, flow->napi_rx.napi_id); 467 if (ret) 468 goto err; 469 470 ret = xdp_rxq_info_reg_mem_model(rxq, 471 MEM_TYPE_PAGE_POOL, 472 pool); 473 if (ret) 474 goto err; 475 } 476 } 477 478 return 0; 479 480 err: 481 am65_cpsw_destroy_xdp_rxqs(common); 482 return ret; 483 } 484 485 static int am65_cpsw_nuss_desc_idx(struct k3_cppi_desc_pool *desc_pool, 486 void *desc, 487 unsigned char dsize_log2) 488 { 489 void *pool_addr = k3_cppi_desc_pool_cpuaddr(desc_pool); 490 491 return (desc - pool_addr) >> dsize_log2; 492 } 493 494 static void am65_cpsw_nuss_set_buf_type(struct am65_cpsw_tx_chn *tx_chn, 495 struct cppi5_host_desc_t *desc, 496 enum am65_cpsw_tx_buf_type buf_type) 497 { 498 int desc_idx; 499 500 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc, 501 tx_chn->dsize_log2); 502 k3_cppi_desc_pool_desc_info_set(tx_chn->desc_pool, desc_idx, 503 (void *)buf_type); 504 } 505 506 static enum am65_cpsw_tx_buf_type am65_cpsw_nuss_buf_type(struct am65_cpsw_tx_chn *tx_chn, 507 dma_addr_t desc_dma) 508 { 509 struct cppi5_host_desc_t *desc_tx; 510 int desc_idx; 511 512 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 513 desc_idx = am65_cpsw_nuss_desc_idx(tx_chn->desc_pool, desc_tx, 514 tx_chn->dsize_log2); 515 516 return (enum am65_cpsw_tx_buf_type)k3_cppi_desc_pool_desc_info(tx_chn->desc_pool, 517 desc_idx); 518 } 519 520 static inline void am65_cpsw_put_page(struct am65_cpsw_rx_flow *flow, 521 struct page *page, 522 bool allow_direct, 523 int desc_idx) 524 { 525 page_pool_put_full_page(flow->page_pool, page, allow_direct); 526 flow->pages[desc_idx] = NULL; 527 } 528 529 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 530 { 531 struct am65_cpsw_rx_flow *flow = data; 532 struct cppi5_host_desc_t *desc_rx; 533 struct am65_cpsw_rx_chn *rx_chn; 534 dma_addr_t buf_dma; 535 u32 buf_dma_len; 536 void *page_addr; 537 void **swdata; 538 int desc_idx; 539 540 rx_chn = &flow->common->rx_chns; 541 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 542 swdata = cppi5_hdesc_get_swdata(desc_rx); 543 page_addr = *swdata; 544 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 545 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 546 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 547 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 548 549 desc_idx = am65_cpsw_nuss_desc_idx(rx_chn->desc_pool, desc_rx, 550 rx_chn->dsize_log2); 551 am65_cpsw_put_page(flow, virt_to_page(page_addr), false, desc_idx); 552 } 553 554 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 555 struct cppi5_host_desc_t *desc) 556 { 557 struct cppi5_host_desc_t *first_desc, *next_desc; 558 dma_addr_t buf_dma, next_desc_dma; 559 u32 buf_dma_len; 560 561 first_desc = desc; 562 next_desc = first_desc; 563 564 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 565 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 566 567 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 568 569 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 570 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 571 while (next_desc_dma) { 572 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 573 next_desc_dma); 574 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 575 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 576 577 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 578 DMA_TO_DEVICE); 579 580 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 581 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 582 583 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 584 } 585 586 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 587 } 588 589 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 590 { 591 struct am65_cpsw_tx_chn *tx_chn = data; 592 struct cppi5_host_desc_t *desc_tx; 593 struct sk_buff *skb; 594 void **swdata; 595 596 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 597 swdata = cppi5_hdesc_get_swdata(desc_tx); 598 skb = *(swdata); 599 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 600 601 dev_kfree_skb_any(skb); 602 } 603 604 static struct sk_buff *am65_cpsw_build_skb(void *page_addr, 605 struct net_device *ndev, 606 unsigned int len) 607 { 608 struct sk_buff *skb; 609 610 len += AM65_CPSW_HEADROOM; 611 612 skb = build_skb(page_addr, len); 613 if (unlikely(!skb)) 614 return NULL; 615 616 skb_reserve(skb, AM65_CPSW_HEADROOM); 617 skb->dev = ndev; 618 619 return skb; 620 } 621 622 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 623 { 624 struct am65_cpsw_host *host_p = am65_common_get_host(common); 625 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 626 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 627 int port_idx, i, ret, tx, flow_idx; 628 struct am65_cpsw_rx_flow *flow; 629 u32 val, port_mask; 630 struct page *page; 631 632 if (common->usage_count) 633 return 0; 634 635 /* Control register */ 636 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 637 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 638 common->cpsw_base + AM65_CPSW_REG_CTL); 639 /* Max length register */ 640 writel(AM65_CPSW_MAX_PACKET_SIZE, 641 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 642 /* set base flow_id */ 643 writel(common->rx_flow_id_base, 644 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 645 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN | AM65_CPSW_P0_REG_CTL_RX_REMAP_VLAN, 646 host_p->port_base + AM65_CPSW_P0_REG_CTL); 647 648 am65_cpsw_nuss_set_p0_ptype(common); 649 650 /* enable statistic */ 651 val = BIT(HOST_PORT_NUM); 652 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 653 struct am65_cpsw_port *port = &common->ports[port_idx]; 654 655 if (!port->disabled) 656 val |= BIT(port->port_id); 657 } 658 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 659 660 /* disable priority elevation */ 661 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 662 663 cpsw_ale_start(common->ale); 664 665 /* limit to one RX flow only */ 666 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 667 ALE_DEFAULT_THREAD_ID, 0); 668 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 669 ALE_DEFAULT_THREAD_ENABLE, 1); 670 /* switch to vlan unaware mode */ 671 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 672 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 673 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 674 675 /* default vlan cfg: create mask based on enabled ports */ 676 port_mask = GENMASK(common->port_num, 0) & 677 ~common->disabled_ports_mask; 678 679 cpsw_ale_add_vlan(common->ale, 0, port_mask, 680 port_mask, port_mask, 681 port_mask & ~ALE_PORT_HOST); 682 683 if (common->is_emac_mode) 684 am65_cpsw_init_host_port_emac(common); 685 else 686 am65_cpsw_init_host_port_switch(common); 687 688 am65_cpsw_qos_tx_p0_rate_init(common); 689 690 ret = am65_cpsw_create_xdp_rxqs(common); 691 if (ret) { 692 dev_err(common->dev, "Failed to create XDP rx queues\n"); 693 return ret; 694 } 695 696 for (flow_idx = 0; flow_idx < common->rx_ch_num_flows; flow_idx++) { 697 flow = &rx_chn->flows[flow_idx]; 698 for (i = 0; i < AM65_CPSW_MAX_RX_DESC; i++) { 699 page = page_pool_dev_alloc_pages(flow->page_pool); 700 if (!page) { 701 dev_err(common->dev, "cannot allocate page in flow %d\n", 702 flow_idx); 703 ret = -ENOMEM; 704 goto fail_rx; 705 } 706 flow->pages[i] = page; 707 708 ret = am65_cpsw_nuss_rx_push(common, page, flow_idx); 709 if (ret < 0) { 710 dev_err(common->dev, 711 "cannot submit page to rx channel flow %d, error %d\n", 712 flow_idx, ret); 713 am65_cpsw_put_page(flow, page, false, i); 714 goto fail_rx; 715 } 716 } 717 } 718 719 ret = k3_udma_glue_enable_rx_chn(rx_chn->rx_chn); 720 if (ret) { 721 dev_err(common->dev, "couldn't enable rx chn: %d\n", ret); 722 goto fail_rx; 723 } 724 725 for (i = 0; i < common->rx_ch_num_flows ; i++) { 726 napi_enable(&rx_chn->flows[i].napi_rx); 727 if (rx_chn->flows[i].irq_disabled) { 728 rx_chn->flows[i].irq_disabled = false; 729 enable_irq(rx_chn->flows[i].irq); 730 } 731 } 732 733 for (tx = 0; tx < common->tx_ch_num; tx++) { 734 ret = k3_udma_glue_enable_tx_chn(tx_chn[tx].tx_chn); 735 if (ret) { 736 dev_err(common->dev, "couldn't enable tx chn %d: %d\n", 737 tx, ret); 738 tx--; 739 goto fail_tx; 740 } 741 napi_enable(&tx_chn[tx].napi_tx); 742 } 743 744 dev_dbg(common->dev, "cpsw_nuss started\n"); 745 return 0; 746 747 fail_tx: 748 while (tx >= 0) { 749 napi_disable(&tx_chn[tx].napi_tx); 750 k3_udma_glue_disable_tx_chn(tx_chn[tx].tx_chn); 751 tx--; 752 } 753 754 for (flow_idx = 0; i < common->rx_ch_num_flows; flow_idx++) { 755 flow = &rx_chn->flows[flow_idx]; 756 if (!flow->irq_disabled) { 757 disable_irq(flow->irq); 758 flow->irq_disabled = true; 759 } 760 napi_disable(&flow->napi_rx); 761 } 762 763 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 764 765 fail_rx: 766 for (i = 0; i < common->rx_ch_num_flows; i++) 767 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, &rx_chn->flows[i], 768 am65_cpsw_nuss_rx_cleanup, 0); 769 770 am65_cpsw_destroy_xdp_rxqs(common); 771 772 return ret; 773 } 774 775 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 776 { 777 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 778 struct am65_cpsw_tx_chn *tx_chn = common->tx_chns; 779 int i; 780 781 if (common->usage_count != 1) 782 return 0; 783 784 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 785 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 786 787 /* shutdown tx channels */ 788 atomic_set(&common->tdown_cnt, common->tx_ch_num); 789 /* ensure new tdown_cnt value is visible */ 790 smp_mb__after_atomic(); 791 reinit_completion(&common->tdown_complete); 792 793 for (i = 0; i < common->tx_ch_num; i++) 794 k3_udma_glue_tdown_tx_chn(tx_chn[i].tx_chn, false); 795 796 i = wait_for_completion_timeout(&common->tdown_complete, 797 msecs_to_jiffies(1000)); 798 if (!i) 799 dev_err(common->dev, "tx timeout\n"); 800 for (i = 0; i < common->tx_ch_num; i++) { 801 napi_disable(&tx_chn[i].napi_tx); 802 hrtimer_cancel(&tx_chn[i].tx_hrtimer); 803 } 804 805 for (i = 0; i < common->tx_ch_num; i++) { 806 k3_udma_glue_reset_tx_chn(tx_chn[i].tx_chn, &tx_chn[i], 807 am65_cpsw_nuss_tx_cleanup); 808 k3_udma_glue_disable_tx_chn(tx_chn[i].tx_chn); 809 } 810 811 reinit_completion(&common->tdown_complete); 812 k3_udma_glue_tdown_rx_chn(rx_chn->rx_chn, true); 813 814 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) { 815 i = wait_for_completion_timeout(&common->tdown_complete, msecs_to_jiffies(1000)); 816 if (!i) 817 dev_err(common->dev, "rx teardown timeout\n"); 818 } 819 820 for (i = 0; i < common->rx_ch_num_flows; i++) { 821 napi_disable(&rx_chn->flows[i].napi_rx); 822 hrtimer_cancel(&rx_chn->flows[i].rx_hrtimer); 823 k3_udma_glue_reset_rx_chn(rx_chn->rx_chn, i, &rx_chn->flows[i], 824 am65_cpsw_nuss_rx_cleanup, 0); 825 } 826 827 k3_udma_glue_disable_rx_chn(rx_chn->rx_chn); 828 829 cpsw_ale_stop(common->ale); 830 831 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 832 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 833 834 am65_cpsw_destroy_xdp_rxqs(common); 835 836 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 837 return 0; 838 } 839 840 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 841 { 842 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 843 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 844 int ret; 845 846 phylink_stop(port->slave.phylink); 847 848 netif_tx_stop_all_queues(ndev); 849 850 phylink_disconnect_phy(port->slave.phylink); 851 852 ret = am65_cpsw_nuss_common_stop(common); 853 if (ret) 854 return ret; 855 856 common->usage_count--; 857 pm_runtime_put(common->dev); 858 return 0; 859 } 860 861 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 862 { 863 struct am65_cpsw_port *port = arg; 864 865 if (!vdev) 866 return 0; 867 868 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 869 } 870 871 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 872 { 873 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 874 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 875 int ret, i; 876 u32 reg; 877 878 ret = pm_runtime_resume_and_get(common->dev); 879 if (ret < 0) 880 return ret; 881 882 /* Idle MAC port */ 883 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 884 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 885 cpsw_sl_ctl_reset(port->slave.mac_sl); 886 887 /* soft reset MAC */ 888 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 889 mdelay(1); 890 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 891 if (reg) { 892 dev_err(common->dev, "soft RESET didn't complete\n"); 893 ret = -ETIMEDOUT; 894 goto runtime_put; 895 } 896 897 /* Notify the stack of the actual queue counts. */ 898 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 899 if (ret) { 900 dev_err(common->dev, "cannot set real number of tx queues\n"); 901 goto runtime_put; 902 } 903 904 ret = netif_set_real_num_rx_queues(ndev, common->rx_ch_num_flows); 905 if (ret) { 906 dev_err(common->dev, "cannot set real number of rx queues\n"); 907 goto runtime_put; 908 } 909 910 for (i = 0; i < common->tx_ch_num; i++) { 911 struct netdev_queue *txq = netdev_get_tx_queue(ndev, i); 912 913 netdev_tx_reset_queue(txq); 914 txq->tx_maxrate = common->tx_chns[i].rate_mbps; 915 } 916 917 ret = am65_cpsw_nuss_common_open(common); 918 if (ret) 919 goto runtime_put; 920 921 common->usage_count++; 922 923 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 924 925 if (common->is_emac_mode) 926 am65_cpsw_init_port_emac_ale(port); 927 else 928 am65_cpsw_init_port_switch_ale(port); 929 930 /* mac_sl should be configured via phy-link interface */ 931 am65_cpsw_sl_ctl_reset(port); 932 933 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.port_np, 0); 934 if (ret) 935 goto error_cleanup; 936 937 /* restore vlan configurations */ 938 vlan_for_each(ndev, cpsw_restore_vlans, port); 939 940 phylink_start(port->slave.phylink); 941 942 return 0; 943 944 error_cleanup: 945 am65_cpsw_nuss_ndo_slave_stop(ndev); 946 return ret; 947 948 runtime_put: 949 pm_runtime_put(common->dev); 950 return ret; 951 } 952 953 static int am65_cpsw_xdp_tx_frame(struct net_device *ndev, 954 struct am65_cpsw_tx_chn *tx_chn, 955 struct xdp_frame *xdpf, 956 enum am65_cpsw_tx_buf_type buf_type) 957 { 958 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 959 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 960 struct cppi5_host_desc_t *host_desc; 961 struct netdev_queue *netif_txq; 962 dma_addr_t dma_desc, dma_buf; 963 u32 pkt_len = xdpf->len; 964 void **swdata; 965 int ret; 966 967 host_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 968 if (unlikely(!host_desc)) { 969 ndev->stats.tx_dropped++; 970 return AM65_CPSW_XDP_CONSUMED; /* drop */ 971 } 972 973 am65_cpsw_nuss_set_buf_type(tx_chn, host_desc, buf_type); 974 975 dma_buf = dma_map_single(tx_chn->dma_dev, xdpf->data, 976 pkt_len, DMA_TO_DEVICE); 977 if (unlikely(dma_mapping_error(tx_chn->dma_dev, dma_buf))) { 978 ndev->stats.tx_dropped++; 979 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 980 goto pool_free; 981 } 982 983 cppi5_hdesc_init(host_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 984 AM65_CPSW_NAV_PS_DATA_SIZE); 985 cppi5_hdesc_set_pkttype(host_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 986 cppi5_hdesc_set_pktlen(host_desc, pkt_len); 987 cppi5_desc_set_pktids(&host_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 988 cppi5_desc_set_tags_ids(&host_desc->hdr, 0, port->port_id); 989 990 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &dma_buf); 991 cppi5_hdesc_attach_buf(host_desc, dma_buf, pkt_len, dma_buf, pkt_len); 992 993 swdata = cppi5_hdesc_get_swdata(host_desc); 994 *(swdata) = xdpf; 995 996 /* Report BQL before sending the packet */ 997 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 998 netdev_tx_sent_queue(netif_txq, pkt_len); 999 1000 dma_desc = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, host_desc); 1001 if (AM65_CPSW_IS_CPSW2G(common)) { 1002 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1003 dma_desc); 1004 } else { 1005 spin_lock_bh(&tx_chn->lock); 1006 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, host_desc, 1007 dma_desc); 1008 spin_unlock_bh(&tx_chn->lock); 1009 } 1010 if (ret) { 1011 /* Inform BQL */ 1012 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1013 ndev->stats.tx_errors++; 1014 ret = AM65_CPSW_XDP_CONSUMED; /* drop */ 1015 goto dma_unmap; 1016 } 1017 1018 return 0; 1019 1020 dma_unmap: 1021 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &dma_buf); 1022 dma_unmap_single(tx_chn->dma_dev, dma_buf, pkt_len, DMA_TO_DEVICE); 1023 pool_free: 1024 k3_cppi_desc_pool_free(tx_chn->desc_pool, host_desc); 1025 return ret; 1026 } 1027 1028 static int am65_cpsw_run_xdp(struct am65_cpsw_rx_flow *flow, 1029 struct am65_cpsw_port *port, 1030 struct xdp_buff *xdp, 1031 int desc_idx, int cpu, int *len) 1032 { 1033 struct am65_cpsw_common *common = flow->common; 1034 struct am65_cpsw_ndev_priv *ndev_priv; 1035 struct net_device *ndev = port->ndev; 1036 struct am65_cpsw_ndev_stats *stats; 1037 int ret = AM65_CPSW_XDP_CONSUMED; 1038 struct am65_cpsw_tx_chn *tx_chn; 1039 struct netdev_queue *netif_txq; 1040 struct xdp_frame *xdpf; 1041 struct bpf_prog *prog; 1042 struct page *page; 1043 u32 act; 1044 int err; 1045 1046 prog = READ_ONCE(port->xdp_prog); 1047 if (!prog) 1048 return AM65_CPSW_XDP_PASS; 1049 1050 act = bpf_prog_run_xdp(prog, xdp); 1051 /* XDP prog might have changed packet data and boundaries */ 1052 *len = xdp->data_end - xdp->data; 1053 1054 ndev_priv = netdev_priv(ndev); 1055 stats = this_cpu_ptr(ndev_priv->stats); 1056 1057 switch (act) { 1058 case XDP_PASS: 1059 ret = AM65_CPSW_XDP_PASS; 1060 goto out; 1061 case XDP_TX: 1062 tx_chn = &common->tx_chns[cpu % AM65_CPSW_MAX_QUEUES]; 1063 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1064 1065 xdpf = xdp_convert_buff_to_frame(xdp); 1066 if (unlikely(!xdpf)) 1067 goto drop; 1068 1069 __netif_tx_lock(netif_txq, cpu); 1070 err = am65_cpsw_xdp_tx_frame(ndev, tx_chn, xdpf, 1071 AM65_CPSW_TX_BUF_TYPE_XDP_TX); 1072 __netif_tx_unlock(netif_txq); 1073 if (err) 1074 goto drop; 1075 1076 u64_stats_update_begin(&stats->syncp); 1077 stats->rx_bytes += *len; 1078 stats->rx_packets++; 1079 u64_stats_update_end(&stats->syncp); 1080 ret = AM65_CPSW_XDP_CONSUMED; 1081 goto out; 1082 case XDP_REDIRECT: 1083 if (unlikely(xdp_do_redirect(ndev, xdp, prog))) 1084 goto drop; 1085 1086 u64_stats_update_begin(&stats->syncp); 1087 stats->rx_bytes += *len; 1088 stats->rx_packets++; 1089 u64_stats_update_end(&stats->syncp); 1090 ret = AM65_CPSW_XDP_REDIRECT; 1091 goto out; 1092 default: 1093 bpf_warn_invalid_xdp_action(ndev, prog, act); 1094 fallthrough; 1095 case XDP_ABORTED: 1096 drop: 1097 trace_xdp_exception(ndev, prog, act); 1098 fallthrough; 1099 case XDP_DROP: 1100 ndev->stats.rx_dropped++; 1101 } 1102 1103 page = virt_to_head_page(xdp->data); 1104 am65_cpsw_put_page(flow, page, true, desc_idx); 1105 1106 out: 1107 return ret; 1108 } 1109 1110 /* RX psdata[2] word format - checksum information */ 1111 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 1112 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 1113 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 1114 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 1115 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 1116 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 1117 1118 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 1119 { 1120 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 1121 * csum information provides in psdata[2] word: 1122 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 1123 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 1124 * bits - indicates IPv4/IPv6 packet 1125 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 1126 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 1127 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 1128 */ 1129 skb_checksum_none_assert(skb); 1130 1131 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 1132 return; 1133 1134 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 1135 AM65_CPSW_RX_PSD_IPV4_VALID)) && 1136 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 1137 /* csum for fragmented packets is unsupported */ 1138 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 1139 skb->ip_summed = CHECKSUM_UNNECESSARY; 1140 } 1141 } 1142 1143 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_rx_flow *flow, 1144 int cpu, int *xdp_state) 1145 { 1146 struct am65_cpsw_rx_chn *rx_chn = &flow->common->rx_chns; 1147 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 1148 struct am65_cpsw_common *common = flow->common; 1149 struct am65_cpsw_ndev_priv *ndev_priv; 1150 struct am65_cpsw_ndev_stats *stats; 1151 struct cppi5_host_desc_t *desc_rx; 1152 struct device *dev = common->dev; 1153 struct page *page, *new_page; 1154 dma_addr_t desc_dma, buf_dma; 1155 struct am65_cpsw_port *port; 1156 int headroom, desc_idx, ret; 1157 struct net_device *ndev; 1158 u32 flow_idx = flow->id; 1159 struct sk_buff *skb; 1160 struct xdp_buff xdp; 1161 void *page_addr; 1162 void **swdata; 1163 u32 *psdata; 1164 1165 *xdp_state = AM65_CPSW_XDP_PASS; 1166 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 1167 if (ret) { 1168 if (ret != -ENODATA) 1169 dev_err(dev, "RX: pop chn fail %d\n", ret); 1170 return ret; 1171 } 1172 1173 if (cppi5_desc_is_tdcm(desc_dma)) { 1174 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 1175 if (common->pdata.quirks & AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ) 1176 complete(&common->tdown_complete); 1177 return 0; 1178 } 1179 1180 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 1181 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 1182 __func__, flow_idx, &desc_dma); 1183 1184 swdata = cppi5_hdesc_get_swdata(desc_rx); 1185 page_addr = *swdata; 1186 page = virt_to_page(page_addr); 1187 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 1188 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 1189 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 1190 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 1191 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 1192 port = am65_common_get_port(common, port_id); 1193 ndev = port->ndev; 1194 psdata = cppi5_hdesc_get_psdata(desc_rx); 1195 csum_info = psdata[2]; 1196 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 1197 1198 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 1199 1200 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 1201 1202 desc_idx = am65_cpsw_nuss_desc_idx(rx_chn->desc_pool, desc_rx, 1203 rx_chn->dsize_log2); 1204 1205 skb = am65_cpsw_build_skb(page_addr, ndev, 1206 AM65_CPSW_MAX_PACKET_SIZE); 1207 if (unlikely(!skb)) { 1208 new_page = page; 1209 goto requeue; 1210 } 1211 1212 if (port->xdp_prog) { 1213 xdp_init_buff(&xdp, PAGE_SIZE, &port->xdp_rxq[flow->id]); 1214 xdp_prepare_buff(&xdp, page_addr, AM65_CPSW_HEADROOM, 1215 pkt_len, false); 1216 *xdp_state = am65_cpsw_run_xdp(flow, port, &xdp, desc_idx, 1217 cpu, &pkt_len); 1218 if (*xdp_state != AM65_CPSW_XDP_PASS) 1219 goto allocate; 1220 1221 /* Compute additional headroom to be reserved */ 1222 headroom = (xdp.data - xdp.data_hard_start) - skb_headroom(skb); 1223 skb_reserve(skb, headroom); 1224 } 1225 1226 ndev_priv = netdev_priv(ndev); 1227 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 1228 skb_put(skb, pkt_len); 1229 if (port->rx_ts_enabled) 1230 am65_cpts_rx_timestamp(common->cpts, skb); 1231 skb_mark_for_recycle(skb); 1232 skb->protocol = eth_type_trans(skb, ndev); 1233 am65_cpsw_nuss_rx_csum(skb, csum_info); 1234 napi_gro_receive(&flow->napi_rx, skb); 1235 1236 stats = this_cpu_ptr(ndev_priv->stats); 1237 1238 u64_stats_update_begin(&stats->syncp); 1239 stats->rx_packets++; 1240 stats->rx_bytes += pkt_len; 1241 u64_stats_update_end(&stats->syncp); 1242 1243 allocate: 1244 new_page = page_pool_dev_alloc_pages(flow->page_pool); 1245 if (unlikely(!new_page)) { 1246 dev_err(dev, "page alloc failed\n"); 1247 return -ENOMEM; 1248 } 1249 1250 flow->pages[desc_idx] = new_page; 1251 1252 if (netif_dormant(ndev)) { 1253 am65_cpsw_put_page(flow, new_page, true, desc_idx); 1254 ndev->stats.rx_dropped++; 1255 return 0; 1256 } 1257 1258 requeue: 1259 ret = am65_cpsw_nuss_rx_push(common, new_page, flow_idx); 1260 if (WARN_ON(ret < 0)) { 1261 am65_cpsw_put_page(flow, new_page, true, desc_idx); 1262 ndev->stats.rx_errors++; 1263 ndev->stats.rx_dropped++; 1264 } 1265 1266 return ret; 1267 } 1268 1269 static enum hrtimer_restart am65_cpsw_nuss_rx_timer_callback(struct hrtimer *timer) 1270 { 1271 struct am65_cpsw_rx_flow *flow = container_of(timer, 1272 struct am65_cpsw_rx_flow, 1273 rx_hrtimer); 1274 1275 enable_irq(flow->irq); 1276 return HRTIMER_NORESTART; 1277 } 1278 1279 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 1280 { 1281 struct am65_cpsw_rx_flow *flow = am65_cpsw_napi_to_rx_flow(napi_rx); 1282 struct am65_cpsw_common *common = flow->common; 1283 int cpu = smp_processor_id(); 1284 int xdp_state_or = 0; 1285 int cur_budget, ret; 1286 int xdp_state; 1287 int num_rx = 0; 1288 1289 /* process only this flow */ 1290 cur_budget = budget; 1291 while (cur_budget--) { 1292 ret = am65_cpsw_nuss_rx_packets(flow, cpu, &xdp_state); 1293 xdp_state_or |= xdp_state; 1294 if (ret) 1295 break; 1296 num_rx++; 1297 } 1298 1299 if (xdp_state_or & AM65_CPSW_XDP_REDIRECT) 1300 xdp_do_flush(); 1301 1302 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 1303 1304 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 1305 if (flow->irq_disabled) { 1306 flow->irq_disabled = false; 1307 if (unlikely(flow->rx_pace_timeout)) { 1308 hrtimer_start(&flow->rx_hrtimer, 1309 ns_to_ktime(flow->rx_pace_timeout), 1310 HRTIMER_MODE_REL_PINNED); 1311 } else { 1312 enable_irq(flow->irq); 1313 } 1314 } 1315 } 1316 1317 return num_rx; 1318 } 1319 1320 static struct sk_buff * 1321 am65_cpsw_nuss_tx_compl_packet_skb(struct am65_cpsw_tx_chn *tx_chn, 1322 dma_addr_t desc_dma) 1323 { 1324 struct am65_cpsw_ndev_priv *ndev_priv; 1325 struct am65_cpsw_ndev_stats *stats; 1326 struct cppi5_host_desc_t *desc_tx; 1327 struct net_device *ndev; 1328 struct sk_buff *skb; 1329 void **swdata; 1330 1331 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 1332 desc_dma); 1333 swdata = cppi5_hdesc_get_swdata(desc_tx); 1334 skb = *(swdata); 1335 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1336 1337 ndev = skb->dev; 1338 1339 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 1340 1341 ndev_priv = netdev_priv(ndev); 1342 stats = this_cpu_ptr(ndev_priv->stats); 1343 u64_stats_update_begin(&stats->syncp); 1344 stats->tx_packets++; 1345 stats->tx_bytes += skb->len; 1346 u64_stats_update_end(&stats->syncp); 1347 1348 return skb; 1349 } 1350 1351 static struct xdp_frame * 1352 am65_cpsw_nuss_tx_compl_packet_xdp(struct am65_cpsw_common *common, 1353 struct am65_cpsw_tx_chn *tx_chn, 1354 dma_addr_t desc_dma, 1355 struct net_device **ndev) 1356 { 1357 struct am65_cpsw_ndev_priv *ndev_priv; 1358 struct am65_cpsw_ndev_stats *stats; 1359 struct cppi5_host_desc_t *desc_tx; 1360 struct am65_cpsw_port *port; 1361 struct xdp_frame *xdpf; 1362 u32 port_id = 0; 1363 void **swdata; 1364 1365 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 1366 cppi5_desc_get_tags_ids(&desc_tx->hdr, NULL, &port_id); 1367 swdata = cppi5_hdesc_get_swdata(desc_tx); 1368 xdpf = *(swdata); 1369 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 1370 1371 port = am65_common_get_port(common, port_id); 1372 *ndev = port->ndev; 1373 1374 ndev_priv = netdev_priv(*ndev); 1375 stats = this_cpu_ptr(ndev_priv->stats); 1376 u64_stats_update_begin(&stats->syncp); 1377 stats->tx_packets++; 1378 stats->tx_bytes += xdpf->len; 1379 u64_stats_update_end(&stats->syncp); 1380 1381 return xdpf; 1382 } 1383 1384 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 1385 struct netdev_queue *netif_txq) 1386 { 1387 if (netif_tx_queue_stopped(netif_txq)) { 1388 /* Check whether the queue is stopped due to stalled 1389 * tx dma, if the queue is stopped then wake the queue 1390 * as we have free desc for tx 1391 */ 1392 __netif_tx_lock(netif_txq, smp_processor_id()); 1393 if (netif_running(ndev) && 1394 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 1395 netif_tx_wake_queue(netif_txq); 1396 1397 __netif_tx_unlock(netif_txq); 1398 } 1399 } 1400 1401 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 1402 int chn, unsigned int budget, bool *tdown) 1403 { 1404 enum am65_cpsw_tx_buf_type buf_type; 1405 struct device *dev = common->dev; 1406 struct am65_cpsw_tx_chn *tx_chn; 1407 struct netdev_queue *netif_txq; 1408 unsigned int total_bytes = 0; 1409 struct net_device *ndev; 1410 struct xdp_frame *xdpf; 1411 struct sk_buff *skb; 1412 dma_addr_t desc_dma; 1413 int res, num_tx = 0; 1414 1415 tx_chn = &common->tx_chns[chn]; 1416 1417 while (true) { 1418 spin_lock(&tx_chn->lock); 1419 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1420 spin_unlock(&tx_chn->lock); 1421 if (res == -ENODATA) 1422 break; 1423 1424 if (cppi5_desc_is_tdcm(desc_dma)) { 1425 if (atomic_dec_and_test(&common->tdown_cnt)) 1426 complete(&common->tdown_complete); 1427 *tdown = true; 1428 break; 1429 } 1430 1431 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1432 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1433 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1434 ndev = skb->dev; 1435 total_bytes = skb->len; 1436 napi_consume_skb(skb, budget); 1437 } else { 1438 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1439 desc_dma, &ndev); 1440 total_bytes = xdpf->len; 1441 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1442 xdp_return_frame_rx_napi(xdpf); 1443 else 1444 xdp_return_frame(xdpf); 1445 } 1446 num_tx++; 1447 1448 netif_txq = netdev_get_tx_queue(ndev, chn); 1449 1450 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1451 1452 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1453 } 1454 1455 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1456 1457 return num_tx; 1458 } 1459 1460 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 1461 int chn, unsigned int budget, bool *tdown) 1462 { 1463 enum am65_cpsw_tx_buf_type buf_type; 1464 struct device *dev = common->dev; 1465 struct am65_cpsw_tx_chn *tx_chn; 1466 struct netdev_queue *netif_txq; 1467 unsigned int total_bytes = 0; 1468 struct net_device *ndev; 1469 struct xdp_frame *xdpf; 1470 struct sk_buff *skb; 1471 dma_addr_t desc_dma; 1472 int res, num_tx = 0; 1473 1474 tx_chn = &common->tx_chns[chn]; 1475 1476 while (true) { 1477 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 1478 if (res == -ENODATA) 1479 break; 1480 1481 if (cppi5_desc_is_tdcm(desc_dma)) { 1482 if (atomic_dec_and_test(&common->tdown_cnt)) 1483 complete(&common->tdown_complete); 1484 *tdown = true; 1485 break; 1486 } 1487 1488 buf_type = am65_cpsw_nuss_buf_type(tx_chn, desc_dma); 1489 if (buf_type == AM65_CPSW_TX_BUF_TYPE_SKB) { 1490 skb = am65_cpsw_nuss_tx_compl_packet_skb(tx_chn, desc_dma); 1491 ndev = skb->dev; 1492 total_bytes += skb->len; 1493 napi_consume_skb(skb, budget); 1494 } else { 1495 xdpf = am65_cpsw_nuss_tx_compl_packet_xdp(common, tx_chn, 1496 desc_dma, &ndev); 1497 total_bytes += xdpf->len; 1498 if (buf_type == AM65_CPSW_TX_BUF_TYPE_XDP_TX) 1499 xdp_return_frame_rx_napi(xdpf); 1500 else 1501 xdp_return_frame(xdpf); 1502 } 1503 num_tx++; 1504 } 1505 1506 if (!num_tx) 1507 return 0; 1508 1509 netif_txq = netdev_get_tx_queue(ndev, chn); 1510 1511 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1512 1513 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1514 1515 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1516 1517 return num_tx; 1518 } 1519 1520 static enum hrtimer_restart am65_cpsw_nuss_tx_timer_callback(struct hrtimer *timer) 1521 { 1522 struct am65_cpsw_tx_chn *tx_chns = 1523 container_of(timer, struct am65_cpsw_tx_chn, tx_hrtimer); 1524 1525 enable_irq(tx_chns->irq); 1526 return HRTIMER_NORESTART; 1527 } 1528 1529 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1530 { 1531 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1532 bool tdown = false; 1533 int num_tx; 1534 1535 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1536 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, 1537 budget, &tdown); 1538 else 1539 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, 1540 tx_chn->id, budget, &tdown); 1541 1542 if (num_tx >= budget) 1543 return budget; 1544 1545 if (napi_complete_done(napi_tx, num_tx)) { 1546 if (unlikely(tx_chn->tx_pace_timeout && !tdown)) { 1547 hrtimer_start(&tx_chn->tx_hrtimer, 1548 ns_to_ktime(tx_chn->tx_pace_timeout), 1549 HRTIMER_MODE_REL_PINNED); 1550 } else { 1551 enable_irq(tx_chn->irq); 1552 } 1553 } 1554 1555 return 0; 1556 } 1557 1558 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1559 { 1560 struct am65_cpsw_rx_flow *flow = dev_id; 1561 1562 flow->irq_disabled = true; 1563 disable_irq_nosync(irq); 1564 napi_schedule(&flow->napi_rx); 1565 1566 return IRQ_HANDLED; 1567 } 1568 1569 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1570 { 1571 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1572 1573 disable_irq_nosync(irq); 1574 napi_schedule(&tx_chn->napi_tx); 1575 1576 return IRQ_HANDLED; 1577 } 1578 1579 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1580 struct net_device *ndev) 1581 { 1582 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1583 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1584 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1585 struct device *dev = common->dev; 1586 struct am65_cpsw_tx_chn *tx_chn; 1587 struct netdev_queue *netif_txq; 1588 dma_addr_t desc_dma, buf_dma; 1589 int ret, q_idx, i; 1590 void **swdata; 1591 u32 *psdata; 1592 u32 pkt_len; 1593 1594 /* padding enabled in hw */ 1595 pkt_len = skb_headlen(skb); 1596 1597 /* SKB TX timestamp */ 1598 if (port->tx_ts_enabled) 1599 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1600 1601 q_idx = skb_get_queue_mapping(skb); 1602 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1603 1604 tx_chn = &common->tx_chns[q_idx]; 1605 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1606 1607 /* Map the linear buffer */ 1608 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1609 DMA_TO_DEVICE); 1610 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1611 dev_err(dev, "Failed to map tx skb buffer\n"); 1612 ndev->stats.tx_errors++; 1613 goto err_free_skb; 1614 } 1615 1616 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1617 if (!first_desc) { 1618 dev_dbg(dev, "Failed to allocate descriptor\n"); 1619 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1620 DMA_TO_DEVICE); 1621 goto busy_stop_q; 1622 } 1623 1624 am65_cpsw_nuss_set_buf_type(tx_chn, first_desc, 1625 AM65_CPSW_TX_BUF_TYPE_SKB); 1626 1627 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1628 AM65_CPSW_NAV_PS_DATA_SIZE); 1629 cppi5_desc_set_pktids(&first_desc->hdr, 0, AM65_CPSW_CPPI_TX_FLOW_ID); 1630 cppi5_hdesc_set_pkttype(first_desc, AM65_CPSW_CPPI_TX_PKT_TYPE); 1631 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1632 1633 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1634 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1635 swdata = cppi5_hdesc_get_swdata(first_desc); 1636 *(swdata) = skb; 1637 psdata = cppi5_hdesc_get_psdata(first_desc); 1638 1639 /* HW csum offload if enabled */ 1640 psdata[2] = 0; 1641 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1642 unsigned int cs_start, cs_offset; 1643 1644 cs_start = skb_transport_offset(skb); 1645 cs_offset = cs_start + skb->csum_offset; 1646 /* HW numerates bytes starting from 1 */ 1647 psdata[2] = ((cs_offset + 1) << 24) | 1648 ((cs_start + 1) << 16) | (skb->len - cs_start); 1649 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1650 } 1651 1652 if (!skb_is_nonlinear(skb)) 1653 goto done_tx; 1654 1655 dev_dbg(dev, "fragmented SKB\n"); 1656 1657 /* Handle the case where skb is fragmented in pages */ 1658 cur_desc = first_desc; 1659 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1660 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1661 u32 frag_size = skb_frag_size(frag); 1662 1663 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1664 if (!next_desc) { 1665 dev_err(dev, "Failed to allocate descriptor\n"); 1666 goto busy_free_descs; 1667 } 1668 1669 am65_cpsw_nuss_set_buf_type(tx_chn, next_desc, 1670 AM65_CPSW_TX_BUF_TYPE_SKB); 1671 1672 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1673 DMA_TO_DEVICE); 1674 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1675 dev_err(dev, "Failed to map tx skb page\n"); 1676 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1677 ndev->stats.tx_errors++; 1678 goto err_free_descs; 1679 } 1680 1681 cppi5_hdesc_reset_hbdesc(next_desc); 1682 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1683 cppi5_hdesc_attach_buf(next_desc, 1684 buf_dma, frag_size, buf_dma, frag_size); 1685 1686 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1687 next_desc); 1688 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1689 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1690 1691 pkt_len += frag_size; 1692 cur_desc = next_desc; 1693 } 1694 WARN_ON(pkt_len != skb->len); 1695 1696 done_tx: 1697 skb_tx_timestamp(skb); 1698 1699 /* report bql before sending packet */ 1700 netdev_tx_sent_queue(netif_txq, pkt_len); 1701 1702 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1703 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1704 if (AM65_CPSW_IS_CPSW2G(common)) { 1705 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1706 } else { 1707 spin_lock_bh(&tx_chn->lock); 1708 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1709 spin_unlock_bh(&tx_chn->lock); 1710 } 1711 if (ret) { 1712 dev_err(dev, "can't push desc %d\n", ret); 1713 /* inform bql */ 1714 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1715 ndev->stats.tx_errors++; 1716 goto err_free_descs; 1717 } 1718 1719 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1720 netif_tx_stop_queue(netif_txq); 1721 /* Barrier, so that stop_queue visible to other cpus */ 1722 smp_mb__after_atomic(); 1723 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1724 1725 /* re-check for smp */ 1726 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1727 MAX_SKB_FRAGS) { 1728 netif_tx_wake_queue(netif_txq); 1729 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1730 } 1731 } 1732 1733 return NETDEV_TX_OK; 1734 1735 err_free_descs: 1736 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1737 err_free_skb: 1738 ndev->stats.tx_dropped++; 1739 dev_kfree_skb_any(skb); 1740 return NETDEV_TX_OK; 1741 1742 busy_free_descs: 1743 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1744 busy_stop_q: 1745 netif_tx_stop_queue(netif_txq); 1746 return NETDEV_TX_BUSY; 1747 } 1748 1749 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1750 void *addr) 1751 { 1752 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1753 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1754 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1755 int ret; 1756 1757 ret = eth_prepare_mac_addr_change(ndev, addr); 1758 if (ret < 0) 1759 return ret; 1760 1761 ret = pm_runtime_resume_and_get(common->dev); 1762 if (ret < 0) 1763 return ret; 1764 1765 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1766 HOST_PORT_NUM, 0, 0); 1767 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1768 HOST_PORT_NUM, ALE_SECURE, 0); 1769 1770 am65_cpsw_port_set_sl_mac(port, addr); 1771 eth_commit_mac_addr_change(ndev, sockaddr); 1772 1773 pm_runtime_put(common->dev); 1774 1775 return 0; 1776 } 1777 1778 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1779 struct ifreq *ifr) 1780 { 1781 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1782 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1783 struct hwtstamp_config cfg; 1784 1785 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1786 return -EOPNOTSUPP; 1787 1788 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1789 return -EFAULT; 1790 1791 /* TX HW timestamp */ 1792 switch (cfg.tx_type) { 1793 case HWTSTAMP_TX_OFF: 1794 case HWTSTAMP_TX_ON: 1795 break; 1796 default: 1797 return -ERANGE; 1798 } 1799 1800 switch (cfg.rx_filter) { 1801 case HWTSTAMP_FILTER_NONE: 1802 port->rx_ts_enabled = false; 1803 break; 1804 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1805 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1806 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1807 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1808 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1809 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1810 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1811 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1812 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1813 port->rx_ts_enabled = true; 1814 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 1815 break; 1816 case HWTSTAMP_FILTER_ALL: 1817 case HWTSTAMP_FILTER_SOME: 1818 case HWTSTAMP_FILTER_NTP_ALL: 1819 return -EOPNOTSUPP; 1820 default: 1821 return -ERANGE; 1822 } 1823 1824 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1825 1826 /* cfg TX timestamp */ 1827 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1828 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1829 1830 ts_vlan_ltype = ETH_P_8021Q; 1831 1832 ts_ctrl_ltype2 = ETH_P_1588 | 1833 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1834 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1835 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1836 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1837 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1838 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1839 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1840 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1841 1842 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1843 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1844 1845 if (port->tx_ts_enabled) 1846 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1847 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1848 1849 if (port->rx_ts_enabled) 1850 ts_ctrl |= AM65_CPSW_TS_RX_ANX_ALL_EN | 1851 AM65_CPSW_PN_TS_CTL_RX_VLAN_LT1_EN; 1852 1853 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1854 writel(ts_vlan_ltype, port->port_base + 1855 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1856 writel(ts_ctrl_ltype2, port->port_base + 1857 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1858 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1859 1860 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1861 } 1862 1863 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1864 struct ifreq *ifr) 1865 { 1866 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1867 struct hwtstamp_config cfg; 1868 1869 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1870 return -EOPNOTSUPP; 1871 1872 cfg.flags = 0; 1873 cfg.tx_type = port->tx_ts_enabled ? 1874 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1875 cfg.rx_filter = port->rx_ts_enabled ? 1876 HWTSTAMP_FILTER_PTP_V2_EVENT : HWTSTAMP_FILTER_NONE; 1877 1878 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1879 } 1880 1881 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1882 struct ifreq *req, int cmd) 1883 { 1884 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1885 1886 if (!netif_running(ndev)) 1887 return -EINVAL; 1888 1889 switch (cmd) { 1890 case SIOCSHWTSTAMP: 1891 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1892 case SIOCGHWTSTAMP: 1893 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1894 } 1895 1896 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1897 } 1898 1899 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1900 struct rtnl_link_stats64 *stats) 1901 { 1902 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1903 unsigned int start; 1904 int cpu; 1905 1906 for_each_possible_cpu(cpu) { 1907 struct am65_cpsw_ndev_stats *cpu_stats; 1908 u64 rx_packets; 1909 u64 rx_bytes; 1910 u64 tx_packets; 1911 u64 tx_bytes; 1912 1913 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1914 do { 1915 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1916 rx_packets = cpu_stats->rx_packets; 1917 rx_bytes = cpu_stats->rx_bytes; 1918 tx_packets = cpu_stats->tx_packets; 1919 tx_bytes = cpu_stats->tx_bytes; 1920 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1921 1922 stats->rx_packets += rx_packets; 1923 stats->rx_bytes += rx_bytes; 1924 stats->tx_packets += tx_packets; 1925 stats->tx_bytes += tx_bytes; 1926 } 1927 1928 stats->rx_errors = dev->stats.rx_errors; 1929 stats->rx_dropped = dev->stats.rx_dropped; 1930 stats->tx_dropped = dev->stats.tx_dropped; 1931 } 1932 1933 static int am65_cpsw_xdp_prog_setup(struct net_device *ndev, 1934 struct bpf_prog *prog) 1935 { 1936 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1937 bool running = netif_running(ndev); 1938 struct bpf_prog *old_prog; 1939 1940 if (running) 1941 am65_cpsw_nuss_ndo_slave_stop(ndev); 1942 1943 old_prog = xchg(&port->xdp_prog, prog); 1944 if (old_prog) 1945 bpf_prog_put(old_prog); 1946 1947 if (running) 1948 return am65_cpsw_nuss_ndo_slave_open(ndev); 1949 1950 return 0; 1951 } 1952 1953 static int am65_cpsw_ndo_bpf(struct net_device *ndev, struct netdev_bpf *bpf) 1954 { 1955 switch (bpf->command) { 1956 case XDP_SETUP_PROG: 1957 return am65_cpsw_xdp_prog_setup(ndev, bpf->prog); 1958 default: 1959 return -EINVAL; 1960 } 1961 } 1962 1963 static int am65_cpsw_ndo_xdp_xmit(struct net_device *ndev, int n, 1964 struct xdp_frame **frames, u32 flags) 1965 { 1966 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1967 struct am65_cpsw_tx_chn *tx_chn; 1968 struct netdev_queue *netif_txq; 1969 int cpu = smp_processor_id(); 1970 int i, nxmit = 0; 1971 1972 tx_chn = &common->tx_chns[cpu % common->tx_ch_num]; 1973 netif_txq = netdev_get_tx_queue(ndev, tx_chn->id); 1974 1975 __netif_tx_lock(netif_txq, cpu); 1976 for (i = 0; i < n; i++) { 1977 if (am65_cpsw_xdp_tx_frame(ndev, tx_chn, frames[i], 1978 AM65_CPSW_TX_BUF_TYPE_XDP_NDO)) 1979 break; 1980 nxmit++; 1981 } 1982 __netif_tx_unlock(netif_txq); 1983 1984 return nxmit; 1985 } 1986 1987 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1988 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1989 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1990 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1991 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1992 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1993 .ndo_validate_addr = eth_validate_addr, 1994 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1995 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1996 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1997 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1998 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1999 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 2000 .ndo_set_tx_maxrate = am65_cpsw_qos_ndo_tx_p0_set_maxrate, 2001 .ndo_bpf = am65_cpsw_ndo_bpf, 2002 .ndo_xdp_xmit = am65_cpsw_ndo_xdp_xmit, 2003 }; 2004 2005 static void am65_cpsw_disable_phy(struct phy *phy) 2006 { 2007 phy_power_off(phy); 2008 phy_exit(phy); 2009 } 2010 2011 static int am65_cpsw_enable_phy(struct phy *phy) 2012 { 2013 int ret; 2014 2015 ret = phy_init(phy); 2016 if (ret < 0) 2017 return ret; 2018 2019 ret = phy_power_on(phy); 2020 if (ret < 0) { 2021 phy_exit(phy); 2022 return ret; 2023 } 2024 2025 return 0; 2026 } 2027 2028 static void am65_cpsw_disable_serdes_phy(struct am65_cpsw_common *common) 2029 { 2030 struct am65_cpsw_port *port; 2031 struct phy *phy; 2032 int i; 2033 2034 for (i = 0; i < common->port_num; i++) { 2035 port = &common->ports[i]; 2036 phy = port->slave.serdes_phy; 2037 if (phy) 2038 am65_cpsw_disable_phy(phy); 2039 } 2040 } 2041 2042 static int am65_cpsw_init_serdes_phy(struct device *dev, struct device_node *port_np, 2043 struct am65_cpsw_port *port) 2044 { 2045 const char *name = "serdes"; 2046 struct phy *phy; 2047 int ret; 2048 2049 phy = devm_of_phy_optional_get(dev, port_np, name); 2050 if (IS_ERR_OR_NULL(phy)) 2051 return PTR_ERR_OR_ZERO(phy); 2052 2053 /* Serdes PHY exists. Store it. */ 2054 port->slave.serdes_phy = phy; 2055 2056 ret = am65_cpsw_enable_phy(phy); 2057 if (ret < 0) 2058 goto err_phy; 2059 2060 return 0; 2061 2062 err_phy: 2063 devm_phy_put(dev, phy); 2064 return ret; 2065 } 2066 2067 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 2068 const struct phylink_link_state *state) 2069 { 2070 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2071 phylink_config); 2072 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2073 struct am65_cpsw_common *common = port->common; 2074 2075 if (common->pdata.extra_modes & BIT(state->interface)) { 2076 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 2077 writel(ADVERTISE_SGMII, 2078 port->sgmii_base + AM65_CPSW_SGMII_MR_ADV_ABILITY_REG); 2079 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2080 } else { 2081 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_EXT_EN); 2082 } 2083 2084 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 2085 cpsw_sl_ctl_set(port->slave.mac_sl, 2086 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2087 } else { 2088 cpsw_sl_ctl_clr(port->slave.mac_sl, 2089 CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN); 2090 } 2091 2092 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 2093 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 2094 } 2095 } 2096 2097 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 2098 phy_interface_t interface) 2099 { 2100 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2101 phylink_config); 2102 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2103 struct am65_cpsw_common *common = port->common; 2104 struct net_device *ndev = port->ndev; 2105 u32 mac_control; 2106 int tmo; 2107 2108 /* disable forwarding */ 2109 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2110 2111 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2112 2113 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 2114 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 2115 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 2116 2117 /* All the bits that am65_cpsw_nuss_mac_link_up() can possibly set */ 2118 mac_control = CPSW_SL_CTL_GMII_EN | CPSW_SL_CTL_GIG | CPSW_SL_CTL_IFCTL_A | 2119 CPSW_SL_CTL_FULLDUPLEX | CPSW_SL_CTL_RX_FLOW_EN | CPSW_SL_CTL_TX_FLOW_EN; 2120 /* If interface mode is RGMII, CPSW_SL_CTL_EXT_EN might have been set for 10 Mbps */ 2121 if (phy_interface_mode_is_rgmii(interface)) 2122 mac_control |= CPSW_SL_CTL_EXT_EN; 2123 /* Only clear those bits that can be set by am65_cpsw_nuss_mac_link_up() */ 2124 cpsw_sl_ctl_clr(port->slave.mac_sl, mac_control); 2125 2126 am65_cpsw_qos_link_down(ndev); 2127 netif_tx_stop_all_queues(ndev); 2128 } 2129 2130 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 2131 unsigned int mode, phy_interface_t interface, int speed, 2132 int duplex, bool tx_pause, bool rx_pause) 2133 { 2134 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 2135 phylink_config); 2136 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 2137 struct am65_cpsw_common *common = port->common; 2138 u32 mac_control = CPSW_SL_CTL_GMII_EN; 2139 struct net_device *ndev = port->ndev; 2140 2141 /* Bring the port out of idle state */ 2142 cpsw_sl_ctl_clr(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 2143 2144 if (speed == SPEED_1000) 2145 mac_control |= CPSW_SL_CTL_GIG; 2146 /* TODO: Verify whether in-band is necessary for 10 Mbps RGMII */ 2147 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 2148 /* Can be used with in band mode only */ 2149 mac_control |= CPSW_SL_CTL_EXT_EN; 2150 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 2151 mac_control |= CPSW_SL_CTL_IFCTL_A; 2152 if (duplex) 2153 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 2154 2155 /* rx_pause/tx_pause */ 2156 if (rx_pause) 2157 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 2158 2159 if (tx_pause) 2160 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 2161 2162 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 2163 2164 /* enable forwarding */ 2165 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 2166 2167 am65_cpsw_qos_link_up(ndev, speed); 2168 netif_tx_wake_all_queues(ndev); 2169 } 2170 2171 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 2172 .mac_config = am65_cpsw_nuss_mac_config, 2173 .mac_link_down = am65_cpsw_nuss_mac_link_down, 2174 .mac_link_up = am65_cpsw_nuss_mac_link_up, 2175 }; 2176 2177 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 2178 { 2179 struct am65_cpsw_common *common = port->common; 2180 2181 if (!port->disabled) 2182 return; 2183 2184 cpsw_ale_control_set(common->ale, port->port_id, 2185 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 2186 2187 cpsw_sl_reset(port->slave.mac_sl, 100); 2188 cpsw_sl_ctl_reset(port->slave.mac_sl); 2189 } 2190 2191 static void am65_cpsw_nuss_free_tx_chns(void *data) 2192 { 2193 struct am65_cpsw_common *common = data; 2194 int i; 2195 2196 for (i = 0; i < common->tx_ch_num; i++) { 2197 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2198 2199 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 2200 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 2201 2202 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 2203 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 2204 2205 memset(tx_chn, 0, sizeof(*tx_chn)); 2206 } 2207 } 2208 2209 static void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 2210 { 2211 struct device *dev = common->dev; 2212 int i; 2213 2214 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2215 2216 common->tx_ch_rate_msk = 0; 2217 for (i = 0; i < common->tx_ch_num; i++) { 2218 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2219 2220 if (tx_chn->irq) 2221 devm_free_irq(dev, tx_chn->irq, tx_chn); 2222 2223 netif_napi_del(&tx_chn->napi_tx); 2224 } 2225 2226 am65_cpsw_nuss_free_tx_chns(common); 2227 } 2228 2229 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2230 { 2231 struct device *dev = common->dev; 2232 int i, ret = 0; 2233 2234 for (i = 0; i < common->tx_ch_num; i++) { 2235 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2236 2237 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 2238 am65_cpsw_nuss_tx_poll); 2239 hrtimer_init(&tx_chn->tx_hrtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL_PINNED); 2240 tx_chn->tx_hrtimer.function = &am65_cpsw_nuss_tx_timer_callback; 2241 2242 ret = devm_request_irq(dev, tx_chn->irq, 2243 am65_cpsw_nuss_tx_irq, 2244 IRQF_TRIGGER_HIGH, 2245 tx_chn->tx_chn_name, tx_chn); 2246 if (ret) { 2247 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2248 tx_chn->id, tx_chn->irq, ret); 2249 goto err; 2250 } 2251 } 2252 2253 err: 2254 return ret; 2255 } 2256 2257 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 2258 { 2259 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 2260 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 2261 struct device *dev = common->dev; 2262 struct k3_ring_cfg ring_cfg = { 2263 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2264 .mode = K3_RINGACC_RING_MODE_RING, 2265 .flags = 0 2266 }; 2267 u32 hdesc_size, hdesc_size_out; 2268 int i, ret = 0; 2269 2270 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2271 AM65_CPSW_NAV_SW_DATA_SIZE); 2272 2273 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2274 tx_cfg.tx_cfg = ring_cfg; 2275 tx_cfg.txcq_cfg = ring_cfg; 2276 tx_cfg.tx_cfg.size = max_desc_num; 2277 tx_cfg.txcq_cfg.size = max_desc_num; 2278 2279 for (i = 0; i < common->tx_ch_num; i++) { 2280 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2281 2282 snprintf(tx_chn->tx_chn_name, 2283 sizeof(tx_chn->tx_chn_name), "tx%d", i); 2284 2285 spin_lock_init(&tx_chn->lock); 2286 tx_chn->common = common; 2287 tx_chn->id = i; 2288 tx_chn->descs_num = max_desc_num; 2289 2290 tx_chn->tx_chn = 2291 k3_udma_glue_request_tx_chn(dev, 2292 tx_chn->tx_chn_name, 2293 &tx_cfg); 2294 if (IS_ERR(tx_chn->tx_chn)) { 2295 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 2296 "Failed to request tx dma channel\n"); 2297 goto err; 2298 } 2299 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 2300 2301 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 2302 tx_chn->descs_num, 2303 hdesc_size, 2304 tx_chn->tx_chn_name); 2305 if (IS_ERR(tx_chn->desc_pool)) { 2306 ret = PTR_ERR(tx_chn->desc_pool); 2307 dev_err(dev, "Failed to create poll %d\n", ret); 2308 goto err; 2309 } 2310 2311 hdesc_size_out = k3_cppi_desc_pool_desc_size(tx_chn->desc_pool); 2312 tx_chn->dsize_log2 = __fls(hdesc_size_out); 2313 WARN_ON(hdesc_size_out != (1 << tx_chn->dsize_log2)); 2314 2315 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 2316 if (tx_chn->irq < 0) { 2317 dev_err(dev, "Failed to get tx dma irq %d\n", 2318 tx_chn->irq); 2319 ret = tx_chn->irq; 2320 goto err; 2321 } 2322 2323 snprintf(tx_chn->tx_chn_name, 2324 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 2325 dev_name(dev), tx_chn->id); 2326 } 2327 2328 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2329 if (ret) { 2330 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 2331 goto err; 2332 } 2333 2334 err: 2335 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 2336 if (i) { 2337 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 2338 return i; 2339 } 2340 2341 return ret; 2342 } 2343 2344 static void am65_cpsw_nuss_free_rx_chns(void *data) 2345 { 2346 struct am65_cpsw_common *common = data; 2347 struct am65_cpsw_rx_chn *rx_chn; 2348 2349 rx_chn = &common->rx_chns; 2350 2351 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 2352 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 2353 2354 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 2355 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 2356 } 2357 2358 static void am65_cpsw_nuss_remove_rx_chns(struct am65_cpsw_common *common) 2359 { 2360 struct device *dev = common->dev; 2361 struct am65_cpsw_rx_chn *rx_chn; 2362 struct am65_cpsw_rx_flow *flows; 2363 int i; 2364 2365 rx_chn = &common->rx_chns; 2366 flows = rx_chn->flows; 2367 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2368 2369 for (i = 0; i < common->rx_ch_num_flows; i++) { 2370 if (!(flows[i].irq < 0)) 2371 devm_free_irq(dev, flows[i].irq, &flows[i]); 2372 netif_napi_del(&flows[i].napi_rx); 2373 } 2374 2375 am65_cpsw_nuss_free_rx_chns(common); 2376 2377 common->rx_flow_id_base = -1; 2378 } 2379 2380 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 2381 { 2382 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 2383 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 2384 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 2385 struct device *dev = common->dev; 2386 struct am65_cpsw_rx_flow *flow; 2387 u32 hdesc_size, hdesc_size_out; 2388 u32 fdqring_id; 2389 int i, ret = 0; 2390 2391 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 2392 AM65_CPSW_NAV_SW_DATA_SIZE); 2393 2394 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 2395 rx_cfg.flow_id_num = common->rx_ch_num_flows; 2396 rx_cfg.flow_id_base = common->rx_flow_id_base; 2397 2398 /* init all flows */ 2399 rx_chn->dev = dev; 2400 rx_chn->descs_num = max_desc_num * rx_cfg.flow_id_num; 2401 2402 for (i = 0; i < common->rx_ch_num_flows; i++) { 2403 flow = &rx_chn->flows[i]; 2404 flow->page_pool = NULL; 2405 flow->pages = devm_kcalloc(dev, AM65_CPSW_MAX_RX_DESC, 2406 sizeof(*flow->pages), GFP_KERNEL); 2407 if (!flow->pages) 2408 return -ENOMEM; 2409 } 2410 2411 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 2412 if (IS_ERR(rx_chn->rx_chn)) { 2413 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 2414 "Failed to request rx dma channel\n"); 2415 goto err; 2416 } 2417 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 2418 2419 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 2420 rx_chn->descs_num, 2421 hdesc_size, "rx"); 2422 if (IS_ERR(rx_chn->desc_pool)) { 2423 ret = PTR_ERR(rx_chn->desc_pool); 2424 dev_err(dev, "Failed to create rx poll %d\n", ret); 2425 goto err; 2426 } 2427 2428 hdesc_size_out = k3_cppi_desc_pool_desc_size(rx_chn->desc_pool); 2429 rx_chn->dsize_log2 = __fls(hdesc_size_out); 2430 WARN_ON(hdesc_size_out != (1 << rx_chn->dsize_log2)); 2431 2432 common->rx_flow_id_base = 2433 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 2434 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 2435 2436 fdqring_id = K3_RINGACC_RING_ID_ANY; 2437 for (i = 0; i < rx_cfg.flow_id_num; i++) { 2438 struct k3_ring_cfg rxring_cfg = { 2439 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2440 .mode = K3_RINGACC_RING_MODE_RING, 2441 .flags = 0, 2442 }; 2443 struct k3_ring_cfg fdqring_cfg = { 2444 .elm_size = K3_RINGACC_RING_ELSIZE_8, 2445 .flags = K3_RINGACC_RING_SHARED, 2446 }; 2447 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 2448 .rx_cfg = rxring_cfg, 2449 .rxfdq_cfg = fdqring_cfg, 2450 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 2451 .src_tag_lo_sel = 2452 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 2453 }; 2454 2455 flow = &rx_chn->flows[i]; 2456 flow->id = i; 2457 flow->common = common; 2458 2459 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 2460 rx_flow_cfg.rx_cfg.size = max_desc_num; 2461 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 2462 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 2463 2464 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 2465 i, &rx_flow_cfg); 2466 if (ret) { 2467 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 2468 goto err; 2469 } 2470 if (!i) 2471 fdqring_id = 2472 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 2473 i); 2474 2475 flow->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 2476 if (flow->irq <= 0) { 2477 dev_err(dev, "Failed to get rx dma irq %d\n", 2478 flow->irq); 2479 ret = flow->irq; 2480 goto err; 2481 } 2482 2483 snprintf(flow->name, 2484 sizeof(flow->name), "%s-rx%d", 2485 dev_name(dev), i); 2486 netif_napi_add(common->dma_ndev, &flow->napi_rx, 2487 am65_cpsw_nuss_rx_poll); 2488 hrtimer_init(&flow->rx_hrtimer, CLOCK_MONOTONIC, 2489 HRTIMER_MODE_REL_PINNED); 2490 flow->rx_hrtimer.function = &am65_cpsw_nuss_rx_timer_callback; 2491 2492 ret = devm_request_irq(dev, flow->irq, 2493 am65_cpsw_nuss_rx_irq, 2494 IRQF_TRIGGER_HIGH, 2495 flow->name, flow); 2496 if (ret) { 2497 dev_err(dev, "failure requesting rx %d irq %u, %d\n", 2498 i, flow->irq, ret); 2499 goto err; 2500 } 2501 } 2502 2503 /* setup classifier to route priorities to flows */ 2504 cpsw_ale_classifier_setup_default(common->ale, common->rx_ch_num_flows); 2505 2506 err: 2507 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 2508 if (i) { 2509 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 2510 return i; 2511 } 2512 2513 return ret; 2514 } 2515 2516 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 2517 { 2518 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2519 2520 host_p->common = common; 2521 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 2522 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 2523 2524 return 0; 2525 } 2526 2527 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 2528 int slave, u8 *mac_addr) 2529 { 2530 u32 mac_lo, mac_hi, offset; 2531 struct regmap *syscon; 2532 int ret; 2533 2534 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 2535 if (IS_ERR(syscon)) { 2536 if (PTR_ERR(syscon) == -ENODEV) 2537 return 0; 2538 return PTR_ERR(syscon); 2539 } 2540 2541 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 2542 &offset); 2543 if (ret) 2544 return ret; 2545 2546 regmap_read(syscon, offset, &mac_lo); 2547 regmap_read(syscon, offset + 4, &mac_hi); 2548 2549 mac_addr[0] = (mac_hi >> 8) & 0xff; 2550 mac_addr[1] = mac_hi & 0xff; 2551 mac_addr[2] = (mac_lo >> 24) & 0xff; 2552 mac_addr[3] = (mac_lo >> 16) & 0xff; 2553 mac_addr[4] = (mac_lo >> 8) & 0xff; 2554 mac_addr[5] = mac_lo & 0xff; 2555 2556 return 0; 2557 } 2558 2559 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 2560 { 2561 struct device *dev = common->dev; 2562 struct device_node *node; 2563 struct am65_cpts *cpts; 2564 void __iomem *reg_base; 2565 2566 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 2567 return 0; 2568 2569 node = of_get_child_by_name(dev->of_node, "cpts"); 2570 if (!node) { 2571 dev_err(dev, "%s cpts not found\n", __func__); 2572 return -ENOENT; 2573 } 2574 2575 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 2576 cpts = am65_cpts_create(dev, reg_base, node); 2577 if (IS_ERR(cpts)) { 2578 int ret = PTR_ERR(cpts); 2579 2580 of_node_put(node); 2581 dev_err(dev, "cpts create err %d\n", ret); 2582 return ret; 2583 } 2584 common->cpts = cpts; 2585 /* Forbid PM runtime if CPTS is running. 2586 * K3 CPSWxG modules may completely lose context during ON->OFF 2587 * transitions depending on integration. 2588 * AM65x/J721E MCU CPSW2G: false 2589 * J721E MAIN_CPSW9G: true 2590 */ 2591 pm_runtime_forbid(dev); 2592 2593 return 0; 2594 } 2595 2596 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 2597 { 2598 struct device_node *node, *port_np; 2599 struct device *dev = common->dev; 2600 int ret; 2601 2602 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2603 if (!node) 2604 return -ENOENT; 2605 2606 for_each_child_of_node(node, port_np) { 2607 struct am65_cpsw_port *port; 2608 u32 port_id; 2609 2610 /* it is not a slave port node, continue */ 2611 if (strcmp(port_np->name, "port")) 2612 continue; 2613 2614 ret = of_property_read_u32(port_np, "reg", &port_id); 2615 if (ret < 0) { 2616 dev_err(dev, "%pOF error reading port_id %d\n", 2617 port_np, ret); 2618 goto of_node_put; 2619 } 2620 2621 if (!port_id || port_id > common->port_num) { 2622 dev_err(dev, "%pOF has invalid port_id %u %s\n", 2623 port_np, port_id, port_np->name); 2624 ret = -EINVAL; 2625 goto of_node_put; 2626 } 2627 2628 port = am65_common_get_port(common, port_id); 2629 port->port_id = port_id; 2630 port->common = common; 2631 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 2632 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 2633 if (common->pdata.extra_modes) 2634 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 2635 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 2636 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 2637 port->name = of_get_property(port_np, "label", NULL); 2638 port->fetch_ram_base = 2639 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 2640 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 2641 2642 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 2643 if (IS_ERR(port->slave.mac_sl)) { 2644 ret = PTR_ERR(port->slave.mac_sl); 2645 goto of_node_put; 2646 } 2647 2648 port->disabled = !of_device_is_available(port_np); 2649 if (port->disabled) { 2650 common->disabled_ports_mask |= BIT(port->port_id); 2651 continue; 2652 } 2653 2654 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 2655 if (IS_ERR(port->slave.ifphy)) { 2656 ret = PTR_ERR(port->slave.ifphy); 2657 dev_err(dev, "%pOF error retrieving port phy: %d\n", 2658 port_np, ret); 2659 goto of_node_put; 2660 } 2661 2662 /* Initialize the Serdes PHY for the port */ 2663 ret = am65_cpsw_init_serdes_phy(dev, port_np, port); 2664 if (ret) 2665 goto of_node_put; 2666 2667 port->slave.mac_only = 2668 of_property_read_bool(port_np, "ti,mac-only"); 2669 2670 /* get phy/link info */ 2671 port->slave.port_np = port_np; 2672 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 2673 if (ret) { 2674 dev_err(dev, "%pOF read phy-mode err %d\n", 2675 port_np, ret); 2676 goto of_node_put; 2677 } 2678 2679 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 2680 if (ret) 2681 goto of_node_put; 2682 2683 ret = of_get_mac_address(port_np, port->slave.mac_addr); 2684 if (ret) { 2685 am65_cpsw_am654_get_efuse_macid(port_np, 2686 port->port_id, 2687 port->slave.mac_addr); 2688 if (!is_valid_ether_addr(port->slave.mac_addr)) { 2689 eth_random_addr(port->slave.mac_addr); 2690 dev_err(dev, "Use random MAC address\n"); 2691 } 2692 } 2693 2694 /* Reset all Queue priorities to 0 */ 2695 writel(0, port->port_base + AM65_CPSW_PN_REG_TX_PRI_MAP); 2696 } 2697 of_node_put(node); 2698 2699 /* is there at least one ext.port */ 2700 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 2701 dev_err(dev, "No Ext. port are available\n"); 2702 return -ENODEV; 2703 } 2704 2705 return 0; 2706 2707 of_node_put: 2708 of_node_put(port_np); 2709 of_node_put(node); 2710 return ret; 2711 } 2712 2713 static void am65_cpsw_pcpu_stats_free(void *data) 2714 { 2715 struct am65_cpsw_ndev_stats __percpu *stats = data; 2716 2717 free_percpu(stats); 2718 } 2719 2720 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2721 { 2722 struct am65_cpsw_port *port; 2723 int i; 2724 2725 for (i = 0; i < common->port_num; i++) { 2726 port = &common->ports[i]; 2727 if (port->slave.phylink) 2728 phylink_destroy(port->slave.phylink); 2729 } 2730 } 2731 2732 static int 2733 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2734 { 2735 struct am65_cpsw_ndev_priv *ndev_priv; 2736 struct device *dev = common->dev; 2737 struct am65_cpsw_port *port; 2738 struct phylink *phylink; 2739 int ret; 2740 2741 port = &common->ports[port_idx]; 2742 2743 if (port->disabled) 2744 return 0; 2745 2746 /* alloc netdev */ 2747 port->ndev = alloc_etherdev_mqs(sizeof(struct am65_cpsw_ndev_priv), 2748 AM65_CPSW_MAX_QUEUES, 2749 AM65_CPSW_MAX_QUEUES); 2750 if (!port->ndev) { 2751 dev_err(dev, "error allocating slave net_device %u\n", 2752 port->port_id); 2753 return -ENOMEM; 2754 } 2755 2756 ndev_priv = netdev_priv(port->ndev); 2757 ndev_priv->port = port; 2758 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2759 mutex_init(&ndev_priv->mm_lock); 2760 port->qos.link_speed = SPEED_UNKNOWN; 2761 SET_NETDEV_DEV(port->ndev, dev); 2762 port->ndev->dev.of_node = port->slave.port_np; 2763 2764 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2765 2766 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2767 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE - 2768 (VLAN_ETH_HLEN + ETH_FCS_LEN); 2769 port->ndev->hw_features = NETIF_F_SG | 2770 NETIF_F_RXCSUM | 2771 NETIF_F_HW_CSUM | 2772 NETIF_F_HW_TC; 2773 port->ndev->features = port->ndev->hw_features | 2774 NETIF_F_HW_VLAN_CTAG_FILTER; 2775 port->ndev->xdp_features = NETDEV_XDP_ACT_BASIC | 2776 NETDEV_XDP_ACT_REDIRECT | 2777 NETDEV_XDP_ACT_NDO_XMIT; 2778 port->ndev->vlan_features |= NETIF_F_SG; 2779 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2780 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2781 2782 /* Configuring Phylink */ 2783 port->slave.phylink_config.dev = &port->ndev->dev; 2784 port->slave.phylink_config.type = PHYLINK_NETDEV; 2785 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 2786 MAC_1000FD | MAC_5000FD; 2787 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2788 2789 switch (port->slave.phy_if) { 2790 case PHY_INTERFACE_MODE_RGMII: 2791 case PHY_INTERFACE_MODE_RGMII_ID: 2792 case PHY_INTERFACE_MODE_RGMII_RXID: 2793 case PHY_INTERFACE_MODE_RGMII_TXID: 2794 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2795 break; 2796 2797 case PHY_INTERFACE_MODE_RMII: 2798 __set_bit(PHY_INTERFACE_MODE_RMII, 2799 port->slave.phylink_config.supported_interfaces); 2800 break; 2801 2802 case PHY_INTERFACE_MODE_QSGMII: 2803 case PHY_INTERFACE_MODE_SGMII: 2804 case PHY_INTERFACE_MODE_USXGMII: 2805 if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2806 __set_bit(port->slave.phy_if, 2807 port->slave.phylink_config.supported_interfaces); 2808 } else { 2809 dev_err(dev, "selected phy-mode is not supported\n"); 2810 return -EOPNOTSUPP; 2811 } 2812 break; 2813 2814 default: 2815 dev_err(dev, "selected phy-mode is not supported\n"); 2816 return -EOPNOTSUPP; 2817 } 2818 2819 phylink = phylink_create(&port->slave.phylink_config, 2820 of_fwnode_handle(port->slave.port_np), 2821 port->slave.phy_if, 2822 &am65_cpsw_phylink_mac_ops); 2823 if (IS_ERR(phylink)) 2824 return PTR_ERR(phylink); 2825 2826 port->slave.phylink = phylink; 2827 2828 /* Disable TX checksum offload by default due to HW bug */ 2829 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2830 port->ndev->features &= ~NETIF_F_HW_CSUM; 2831 2832 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2833 if (!ndev_priv->stats) 2834 return -ENOMEM; 2835 2836 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2837 ndev_priv->stats); 2838 if (ret) 2839 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2840 2841 port->xdp_prog = NULL; 2842 2843 if (!common->dma_ndev) 2844 common->dma_ndev = port->ndev; 2845 2846 return ret; 2847 } 2848 2849 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2850 { 2851 int ret; 2852 int i; 2853 2854 for (i = 0; i < common->port_num; i++) { 2855 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2856 if (ret) 2857 return ret; 2858 } 2859 2860 return ret; 2861 } 2862 2863 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2864 { 2865 struct am65_cpsw_port *port; 2866 int i; 2867 2868 for (i = 0; i < common->port_num; i++) { 2869 port = &common->ports[i]; 2870 if (!port->ndev) 2871 continue; 2872 if (port->ndev->reg_state == NETREG_REGISTERED) 2873 unregister_netdev(port->ndev); 2874 free_netdev(port->ndev); 2875 port->ndev = NULL; 2876 } 2877 } 2878 2879 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2880 { 2881 int set_val = 0; 2882 int i; 2883 2884 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2885 set_val = 1; 2886 2887 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2888 2889 for (i = 1; i <= common->port_num; i++) { 2890 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2891 struct am65_cpsw_ndev_priv *priv; 2892 2893 if (!port->ndev) 2894 continue; 2895 2896 priv = am65_ndev_to_priv(port->ndev); 2897 priv->offload_fwd_mark = set_val; 2898 } 2899 } 2900 2901 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2902 { 2903 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2904 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2905 2906 return !common->is_emac_mode; 2907 } 2908 2909 return false; 2910 } 2911 2912 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2913 struct net_device *br_ndev, 2914 struct netlink_ext_ack *extack) 2915 { 2916 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2917 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2918 int err; 2919 2920 if (!common->br_members) { 2921 common->hw_bridge_dev = br_ndev; 2922 } else { 2923 /* This is adding the port to a second bridge, this is 2924 * unsupported 2925 */ 2926 if (common->hw_bridge_dev != br_ndev) 2927 return -EOPNOTSUPP; 2928 } 2929 2930 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2931 false, extack); 2932 if (err) 2933 return err; 2934 2935 common->br_members |= BIT(priv->port->port_id); 2936 2937 am65_cpsw_port_offload_fwd_mark_update(common); 2938 2939 return NOTIFY_DONE; 2940 } 2941 2942 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2943 { 2944 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2945 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2946 2947 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2948 2949 common->br_members &= ~BIT(priv->port->port_id); 2950 2951 am65_cpsw_port_offload_fwd_mark_update(common); 2952 2953 if (!common->br_members) 2954 common->hw_bridge_dev = NULL; 2955 } 2956 2957 /* netdev notifier */ 2958 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2959 unsigned long event, void *ptr) 2960 { 2961 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2962 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2963 struct netdev_notifier_changeupper_info *info; 2964 int ret = NOTIFY_DONE; 2965 2966 if (!am65_cpsw_port_dev_check(ndev)) 2967 return NOTIFY_DONE; 2968 2969 switch (event) { 2970 case NETDEV_CHANGEUPPER: 2971 info = ptr; 2972 2973 if (netif_is_bridge_master(info->upper_dev)) { 2974 if (info->linking) 2975 ret = am65_cpsw_netdevice_port_link(ndev, 2976 info->upper_dev, 2977 extack); 2978 else 2979 am65_cpsw_netdevice_port_unlink(ndev); 2980 } 2981 break; 2982 default: 2983 return NOTIFY_DONE; 2984 } 2985 2986 return notifier_from_errno(ret); 2987 } 2988 2989 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2990 { 2991 int ret = 0; 2992 2993 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2994 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2995 return 0; 2996 2997 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2998 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2999 if (ret) { 3000 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 3001 return ret; 3002 } 3003 3004 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 3005 if (ret) 3006 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3007 3008 return ret; 3009 } 3010 3011 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 3012 { 3013 if (AM65_CPSW_IS_CPSW2G(cpsw) || 3014 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3015 return; 3016 3017 am65_cpsw_switchdev_unregister_notifiers(cpsw); 3018 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 3019 } 3020 3021 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 3022 3023 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 3024 { 3025 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 3026 ALE_MCAST_BLOCK_LEARN_FWD); 3027 } 3028 3029 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 3030 { 3031 struct am65_cpsw_host *host = am65_common_get_host(common); 3032 3033 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3034 3035 am65_cpsw_init_stp_ale_entry(common); 3036 3037 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 3038 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 3039 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 3040 } 3041 3042 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 3043 { 3044 struct am65_cpsw_host *host = am65_common_get_host(common); 3045 3046 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3047 3048 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 3049 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 3050 3051 /* learning make no sense in multi-mac mode */ 3052 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 3053 } 3054 3055 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 3056 struct devlink_param_gset_ctx *ctx) 3057 { 3058 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3059 struct am65_cpsw_common *common = dl_priv->common; 3060 3061 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 3062 3063 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3064 return -EOPNOTSUPP; 3065 3066 ctx->val.vbool = !common->is_emac_mode; 3067 3068 return 0; 3069 } 3070 3071 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 3072 { 3073 struct am65_cpsw_slave_data *slave = &port->slave; 3074 struct am65_cpsw_common *common = port->common; 3075 u32 port_mask; 3076 3077 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3078 3079 if (slave->mac_only) 3080 /* enable mac-only mode on port */ 3081 cpsw_ale_control_set(common->ale, port->port_id, 3082 ALE_PORT_MACONLY, 1); 3083 3084 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 3085 3086 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3087 3088 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 3089 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 3090 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 3091 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 3092 } 3093 3094 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 3095 { 3096 struct am65_cpsw_slave_data *slave = &port->slave; 3097 struct am65_cpsw_common *cpsw = port->common; 3098 u32 port_mask; 3099 3100 cpsw_ale_control_set(cpsw->ale, port->port_id, 3101 ALE_PORT_NOLEARN, 0); 3102 3103 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 3104 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 3105 slave->port_vlan); 3106 3107 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 3108 3109 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 3110 port_mask, ALE_VLAN, slave->port_vlan, 3111 ALE_MCAST_FWD_2); 3112 3113 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3114 3115 cpsw_ale_control_set(cpsw->ale, port->port_id, 3116 ALE_PORT_MACONLY, 0); 3117 } 3118 3119 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 3120 struct devlink_param_gset_ctx *ctx, 3121 struct netlink_ext_ack *extack) 3122 { 3123 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 3124 struct am65_cpsw_common *cpsw = dl_priv->common; 3125 bool switch_en = ctx->val.vbool; 3126 bool if_running = false; 3127 int i; 3128 3129 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 3130 3131 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 3132 return -EOPNOTSUPP; 3133 3134 if (switch_en == !cpsw->is_emac_mode) 3135 return 0; 3136 3137 if (!switch_en && cpsw->br_members) { 3138 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 3139 return -EINVAL; 3140 } 3141 3142 rtnl_lock(); 3143 3144 cpsw->is_emac_mode = !switch_en; 3145 3146 for (i = 0; i < cpsw->port_num; i++) { 3147 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3148 3149 if (!sl_ndev || !netif_running(sl_ndev)) 3150 continue; 3151 3152 if_running = true; 3153 } 3154 3155 if (!if_running) { 3156 /* all ndevs are down */ 3157 for (i = 0; i < cpsw->port_num; i++) { 3158 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3159 struct am65_cpsw_slave_data *slave; 3160 3161 if (!sl_ndev) 3162 continue; 3163 3164 slave = am65_ndev_to_slave(sl_ndev); 3165 if (switch_en) 3166 slave->port_vlan = cpsw->default_vlan; 3167 else 3168 slave->port_vlan = 0; 3169 } 3170 3171 goto exit; 3172 } 3173 3174 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 3175 /* clean up ALE table */ 3176 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 3177 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 3178 3179 if (switch_en) { 3180 dev_info(cpsw->dev, "Enable switch mode\n"); 3181 3182 am65_cpsw_init_host_port_switch(cpsw); 3183 3184 for (i = 0; i < cpsw->port_num; i++) { 3185 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3186 struct am65_cpsw_slave_data *slave; 3187 struct am65_cpsw_port *port; 3188 3189 if (!sl_ndev) 3190 continue; 3191 3192 port = am65_ndev_to_port(sl_ndev); 3193 slave = am65_ndev_to_slave(sl_ndev); 3194 slave->port_vlan = cpsw->default_vlan; 3195 3196 if (netif_running(sl_ndev)) 3197 am65_cpsw_init_port_switch_ale(port); 3198 } 3199 3200 } else { 3201 dev_info(cpsw->dev, "Disable switch mode\n"); 3202 3203 am65_cpsw_init_host_port_emac(cpsw); 3204 3205 for (i = 0; i < cpsw->port_num; i++) { 3206 struct net_device *sl_ndev = cpsw->ports[i].ndev; 3207 struct am65_cpsw_port *port; 3208 3209 if (!sl_ndev) 3210 continue; 3211 3212 port = am65_ndev_to_port(sl_ndev); 3213 port->slave.port_vlan = 0; 3214 if (netif_running(sl_ndev)) 3215 am65_cpsw_init_port_emac_ale(port); 3216 } 3217 } 3218 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 3219 exit: 3220 rtnl_unlock(); 3221 3222 return 0; 3223 } 3224 3225 static const struct devlink_param am65_cpsw_devlink_params[] = { 3226 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 3227 DEVLINK_PARAM_TYPE_BOOL, 3228 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 3229 am65_cpsw_dl_switch_mode_get, 3230 am65_cpsw_dl_switch_mode_set, NULL), 3231 }; 3232 3233 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 3234 { 3235 struct devlink_port_attrs attrs = {}; 3236 struct am65_cpsw_devlink *dl_priv; 3237 struct device *dev = common->dev; 3238 struct devlink_port *dl_port; 3239 struct am65_cpsw_port *port; 3240 int ret = 0; 3241 int i; 3242 3243 common->devlink = 3244 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 3245 if (!common->devlink) 3246 return -ENOMEM; 3247 3248 dl_priv = devlink_priv(common->devlink); 3249 dl_priv->common = common; 3250 3251 /* Provide devlink hook to switch mode when multiple external ports 3252 * are present NUSS switchdev driver is enabled. 3253 */ 3254 if (!AM65_CPSW_IS_CPSW2G(common) && 3255 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 3256 ret = devlink_params_register(common->devlink, 3257 am65_cpsw_devlink_params, 3258 ARRAY_SIZE(am65_cpsw_devlink_params)); 3259 if (ret) { 3260 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 3261 goto dl_unreg; 3262 } 3263 } 3264 3265 for (i = 1; i <= common->port_num; i++) { 3266 port = am65_common_get_port(common, i); 3267 dl_port = &port->devlink_port; 3268 3269 if (port->ndev) 3270 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 3271 else 3272 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 3273 attrs.phys.port_number = port->port_id; 3274 attrs.switch_id.id_len = sizeof(resource_size_t); 3275 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 3276 devlink_port_attrs_set(dl_port, &attrs); 3277 3278 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 3279 if (ret) { 3280 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 3281 port->port_id, ret); 3282 goto dl_port_unreg; 3283 } 3284 } 3285 devlink_register(common->devlink); 3286 return ret; 3287 3288 dl_port_unreg: 3289 for (i = i - 1; i >= 1; i--) { 3290 port = am65_common_get_port(common, i); 3291 dl_port = &port->devlink_port; 3292 3293 devlink_port_unregister(dl_port); 3294 } 3295 dl_unreg: 3296 devlink_free(common->devlink); 3297 return ret; 3298 } 3299 3300 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 3301 { 3302 struct devlink_port *dl_port; 3303 struct am65_cpsw_port *port; 3304 int i; 3305 3306 devlink_unregister(common->devlink); 3307 3308 for (i = 1; i <= common->port_num; i++) { 3309 port = am65_common_get_port(common, i); 3310 dl_port = &port->devlink_port; 3311 3312 devlink_port_unregister(dl_port); 3313 } 3314 3315 if (!AM65_CPSW_IS_CPSW2G(common) && 3316 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 3317 devlink_params_unregister(common->devlink, 3318 am65_cpsw_devlink_params, 3319 ARRAY_SIZE(am65_cpsw_devlink_params)); 3320 3321 devlink_free(common->devlink); 3322 } 3323 3324 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 3325 { 3326 struct am65_cpsw_rx_chn *rx_chan = &common->rx_chns; 3327 struct am65_cpsw_tx_chn *tx_chan = common->tx_chns; 3328 struct device *dev = common->dev; 3329 struct am65_cpsw_port *port; 3330 int ret = 0, i; 3331 3332 /* init tx channels */ 3333 ret = am65_cpsw_nuss_init_tx_chns(common); 3334 if (ret) 3335 return ret; 3336 ret = am65_cpsw_nuss_init_rx_chns(common); 3337 if (ret) 3338 return ret; 3339 3340 /* The DMA Channels are not guaranteed to be in a clean state. 3341 * Reset and disable them to ensure that they are back to the 3342 * clean state and ready to be used. 3343 */ 3344 for (i = 0; i < common->tx_ch_num; i++) { 3345 k3_udma_glue_reset_tx_chn(tx_chan[i].tx_chn, &tx_chan[i], 3346 am65_cpsw_nuss_tx_cleanup); 3347 k3_udma_glue_disable_tx_chn(tx_chan[i].tx_chn); 3348 } 3349 3350 for (i = 0; i < common->rx_ch_num_flows; i++) 3351 k3_udma_glue_reset_rx_chn(rx_chan->rx_chn, i, 3352 &rx_chan->flows[i], 3353 am65_cpsw_nuss_rx_cleanup, 0); 3354 3355 k3_udma_glue_disable_rx_chn(rx_chan->rx_chn); 3356 3357 ret = am65_cpsw_nuss_register_devlink(common); 3358 if (ret) 3359 return ret; 3360 3361 for (i = 0; i < common->port_num; i++) { 3362 port = &common->ports[i]; 3363 3364 if (!port->ndev) 3365 continue; 3366 3367 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 3368 3369 ret = register_netdev(port->ndev); 3370 if (ret) { 3371 dev_err(dev, "error registering slave net device%i %d\n", 3372 i, ret); 3373 goto err_cleanup_ndev; 3374 } 3375 } 3376 3377 ret = am65_cpsw_register_notifiers(common); 3378 if (ret) 3379 goto err_cleanup_ndev; 3380 3381 /* can't auto unregister ndev using devm_add_action() due to 3382 * devres release sequence in DD core for DMA 3383 */ 3384 3385 return 0; 3386 3387 err_cleanup_ndev: 3388 am65_cpsw_nuss_cleanup_ndev(common); 3389 am65_cpsw_unregister_devlink(common); 3390 3391 return ret; 3392 } 3393 3394 int am65_cpsw_nuss_update_tx_rx_chns(struct am65_cpsw_common *common, 3395 int num_tx, int num_rx) 3396 { 3397 int ret; 3398 3399 am65_cpsw_nuss_remove_tx_chns(common); 3400 am65_cpsw_nuss_remove_rx_chns(common); 3401 3402 common->tx_ch_num = num_tx; 3403 common->rx_ch_num_flows = num_rx; 3404 ret = am65_cpsw_nuss_init_tx_chns(common); 3405 if (ret) 3406 return ret; 3407 3408 ret = am65_cpsw_nuss_init_rx_chns(common); 3409 3410 return ret; 3411 } 3412 3413 struct am65_cpsw_soc_pdata { 3414 u32 quirks_dis; 3415 }; 3416 3417 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 3418 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3419 }; 3420 3421 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 3422 { .family = "AM65X", 3423 .revision = "SR2.0", 3424 .data = &am65x_soc_sr2_0 3425 }, 3426 {/* sentinel */} 3427 }; 3428 3429 static const struct am65_cpsw_pdata am65x_sr1_0 = { 3430 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 3431 .ale_dev_id = "am65x-cpsw2g", 3432 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3433 }; 3434 3435 static const struct am65_cpsw_pdata j721e_pdata = { 3436 .quirks = 0, 3437 .ale_dev_id = "am65x-cpsw2g", 3438 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3439 }; 3440 3441 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 3442 .quirks = AM64_CPSW_QUIRK_DMA_RX_TDOWN_IRQ, 3443 .ale_dev_id = "am64-cpswxg", 3444 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3445 }; 3446 3447 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 3448 .quirks = 0, 3449 .ale_dev_id = "am64-cpswxg", 3450 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 3451 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3452 }; 3453 3454 static const struct am65_cpsw_pdata j721e_cpswxg_pdata = { 3455 .quirks = 0, 3456 .ale_dev_id = "am64-cpswxg", 3457 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3458 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII), 3459 }; 3460 3461 static const struct am65_cpsw_pdata j784s4_cpswxg_pdata = { 3462 .quirks = 0, 3463 .ale_dev_id = "am64-cpswxg", 3464 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 3465 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) | 3466 BIT(PHY_INTERFACE_MODE_USXGMII), 3467 }; 3468 3469 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 3470 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 3471 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 3472 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 3473 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 3474 { .compatible = "ti,j721e-cpswxg-nuss", .data = &j721e_cpswxg_pdata}, 3475 { .compatible = "ti,j784s4-cpswxg-nuss", .data = &j784s4_cpswxg_pdata}, 3476 { /* sentinel */ }, 3477 }; 3478 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 3479 3480 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 3481 { 3482 const struct soc_device_attribute *soc; 3483 3484 soc = soc_device_match(am65_cpsw_socinfo); 3485 if (soc && soc->data) { 3486 const struct am65_cpsw_soc_pdata *socdata = soc->data; 3487 3488 /* disable quirks */ 3489 common->pdata.quirks &= ~socdata->quirks_dis; 3490 } 3491 } 3492 3493 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 3494 { 3495 struct cpsw_ale_params ale_params = { 0 }; 3496 const struct of_device_id *of_id; 3497 struct device *dev = &pdev->dev; 3498 struct am65_cpsw_common *common; 3499 struct device_node *node; 3500 struct resource *res; 3501 struct clk *clk; 3502 int ale_entries; 3503 u64 id_temp; 3504 int ret, i; 3505 3506 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 3507 if (!common) 3508 return -ENOMEM; 3509 common->dev = dev; 3510 3511 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 3512 if (!of_id) 3513 return -EINVAL; 3514 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 3515 3516 am65_cpsw_nuss_apply_socinfo(common); 3517 3518 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 3519 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 3520 if (IS_ERR(common->ss_base)) 3521 return PTR_ERR(common->ss_base); 3522 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 3523 /* Use device's physical base address as switch id */ 3524 id_temp = cpu_to_be64(res->start); 3525 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 3526 3527 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 3528 if (!node) 3529 return -ENOENT; 3530 common->port_num = of_get_child_count(node); 3531 of_node_put(node); 3532 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 3533 return -ENOENT; 3534 3535 common->rx_flow_id_base = -1; 3536 init_completion(&common->tdown_complete); 3537 common->tx_ch_num = AM65_CPSW_DEFAULT_TX_CHNS; 3538 common->rx_ch_num_flows = AM65_CPSW_DEFAULT_RX_CHN_FLOWS; 3539 common->pf_p0_rx_ptype_rrobin = false; 3540 common->default_vlan = 1; 3541 3542 common->ports = devm_kcalloc(dev, common->port_num, 3543 sizeof(*common->ports), 3544 GFP_KERNEL); 3545 if (!common->ports) 3546 return -ENOMEM; 3547 3548 clk = devm_clk_get(dev, "fck"); 3549 if (IS_ERR(clk)) 3550 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 3551 common->bus_freq = clk_get_rate(clk); 3552 3553 pm_runtime_enable(dev); 3554 ret = pm_runtime_resume_and_get(dev); 3555 if (ret < 0) { 3556 pm_runtime_disable(dev); 3557 return ret; 3558 } 3559 3560 node = of_get_child_by_name(dev->of_node, "mdio"); 3561 if (!node) { 3562 dev_warn(dev, "MDIO node not found\n"); 3563 } else if (of_device_is_available(node)) { 3564 struct platform_device *mdio_pdev; 3565 3566 mdio_pdev = of_platform_device_create(node, NULL, dev); 3567 if (!mdio_pdev) { 3568 ret = -ENODEV; 3569 goto err_pm_clear; 3570 } 3571 3572 common->mdio_dev = &mdio_pdev->dev; 3573 } 3574 of_node_put(node); 3575 3576 am65_cpsw_nuss_get_ver(common); 3577 3578 ret = am65_cpsw_nuss_init_host_p(common); 3579 if (ret) 3580 goto err_of_clear; 3581 3582 ret = am65_cpsw_nuss_init_slave_ports(common); 3583 if (ret) 3584 goto err_of_clear; 3585 3586 /* init common data */ 3587 ale_params.dev = dev; 3588 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 3589 ale_params.ale_ports = common->port_num + 1; 3590 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 3591 ale_params.dev_id = common->pdata.ale_dev_id; 3592 ale_params.bus_freq = common->bus_freq; 3593 3594 common->ale = cpsw_ale_create(&ale_params); 3595 if (IS_ERR(common->ale)) { 3596 dev_err(dev, "error initializing ale engine\n"); 3597 ret = PTR_ERR(common->ale); 3598 goto err_of_clear; 3599 } 3600 3601 ale_entries = common->ale->params.ale_entries; 3602 common->ale_context = devm_kzalloc(dev, 3603 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 3604 GFP_KERNEL); 3605 ret = am65_cpsw_init_cpts(common); 3606 if (ret) 3607 goto err_of_clear; 3608 3609 /* init ports */ 3610 for (i = 0; i < common->port_num; i++) 3611 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 3612 3613 dev_set_drvdata(dev, common); 3614 3615 common->is_emac_mode = true; 3616 3617 ret = am65_cpsw_nuss_init_ndevs(common); 3618 if (ret) 3619 goto err_ndevs_clear; 3620 3621 ret = am65_cpsw_nuss_register_ndevs(common); 3622 if (ret) 3623 goto err_ndevs_clear; 3624 3625 pm_runtime_put(dev); 3626 return 0; 3627 3628 err_ndevs_clear: 3629 am65_cpsw_nuss_cleanup_ndev(common); 3630 am65_cpsw_nuss_phylink_cleanup(common); 3631 am65_cpts_release(common->cpts); 3632 err_of_clear: 3633 if (common->mdio_dev) 3634 of_platform_device_destroy(common->mdio_dev, NULL); 3635 err_pm_clear: 3636 pm_runtime_put_sync(dev); 3637 pm_runtime_disable(dev); 3638 return ret; 3639 } 3640 3641 static void am65_cpsw_nuss_remove(struct platform_device *pdev) 3642 { 3643 struct device *dev = &pdev->dev; 3644 struct am65_cpsw_common *common; 3645 int ret; 3646 3647 common = dev_get_drvdata(dev); 3648 3649 ret = pm_runtime_resume_and_get(&pdev->dev); 3650 if (ret < 0) { 3651 /* Note, if this error path is taken, we're leaking some 3652 * resources. 3653 */ 3654 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", 3655 ERR_PTR(ret)); 3656 return; 3657 } 3658 3659 am65_cpsw_unregister_notifiers(common); 3660 3661 /* must unregister ndevs here because DD release_driver routine calls 3662 * dma_deconfigure(dev) before devres_release_all(dev) 3663 */ 3664 am65_cpsw_nuss_cleanup_ndev(common); 3665 am65_cpsw_unregister_devlink(common); 3666 am65_cpsw_nuss_phylink_cleanup(common); 3667 am65_cpts_release(common->cpts); 3668 am65_cpsw_disable_serdes_phy(common); 3669 3670 if (common->mdio_dev) 3671 of_platform_device_destroy(common->mdio_dev, NULL); 3672 3673 pm_runtime_put_sync(&pdev->dev); 3674 pm_runtime_disable(&pdev->dev); 3675 } 3676 3677 static int am65_cpsw_nuss_suspend(struct device *dev) 3678 { 3679 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3680 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3681 struct am65_cpsw_port *port; 3682 struct net_device *ndev; 3683 int i, ret; 3684 3685 cpsw_ale_dump(common->ale, common->ale_context); 3686 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3687 for (i = 0; i < common->port_num; i++) { 3688 port = &common->ports[i]; 3689 ndev = port->ndev; 3690 3691 if (!ndev) 3692 continue; 3693 3694 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3695 netif_device_detach(ndev); 3696 if (netif_running(ndev)) { 3697 rtnl_lock(); 3698 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 3699 rtnl_unlock(); 3700 if (ret < 0) { 3701 netdev_err(ndev, "failed to stop: %d", ret); 3702 return ret; 3703 } 3704 } 3705 } 3706 3707 am65_cpts_suspend(common->cpts); 3708 3709 am65_cpsw_nuss_remove_rx_chns(common); 3710 am65_cpsw_nuss_remove_tx_chns(common); 3711 3712 return 0; 3713 } 3714 3715 static int am65_cpsw_nuss_resume(struct device *dev) 3716 { 3717 struct am65_cpsw_common *common = dev_get_drvdata(dev); 3718 struct am65_cpsw_host *host_p = am65_common_get_host(common); 3719 struct am65_cpsw_port *port; 3720 struct net_device *ndev; 3721 int i, ret; 3722 3723 ret = am65_cpsw_nuss_init_tx_chns(common); 3724 if (ret) 3725 return ret; 3726 ret = am65_cpsw_nuss_init_rx_chns(common); 3727 if (ret) 3728 return ret; 3729 3730 /* If RX IRQ was disabled before suspend, keep it disabled */ 3731 for (i = 0; i < common->rx_ch_num_flows; i++) { 3732 if (common->rx_chns.flows[i].irq_disabled) 3733 disable_irq(common->rx_chns.flows[i].irq); 3734 } 3735 3736 am65_cpts_resume(common->cpts); 3737 3738 for (i = 0; i < common->port_num; i++) { 3739 port = &common->ports[i]; 3740 ndev = port->ndev; 3741 3742 if (!ndev) 3743 continue; 3744 3745 if (netif_running(ndev)) { 3746 rtnl_lock(); 3747 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 3748 rtnl_unlock(); 3749 if (ret < 0) { 3750 netdev_err(ndev, "failed to start: %d", ret); 3751 return ret; 3752 } 3753 } 3754 3755 netif_device_attach(ndev); 3756 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3757 } 3758 3759 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 3760 cpsw_ale_restore(common->ale, common->ale_context); 3761 3762 return 0; 3763 } 3764 3765 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 3766 SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 3767 }; 3768 3769 static struct platform_driver am65_cpsw_nuss_driver = { 3770 .driver = { 3771 .name = AM65_CPSW_DRV_NAME, 3772 .of_match_table = am65_cpsw_nuss_of_mtable, 3773 .pm = &am65_cpsw_nuss_dev_pm_ops, 3774 }, 3775 .probe = am65_cpsw_nuss_probe, 3776 .remove_new = am65_cpsw_nuss_remove, 3777 }; 3778 3779 module_platform_driver(am65_cpsw_nuss_driver); 3780 3781 MODULE_LICENSE("GPL v2"); 3782 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 3783 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 3784