1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/kernel.h> 13 #include <linux/kmemleak.h> 14 #include <linux/module.h> 15 #include <linux/netdevice.h> 16 #include <linux/net_tstamp.h> 17 #include <linux/of.h> 18 #include <linux/of_mdio.h> 19 #include <linux/of_net.h> 20 #include <linux/of_device.h> 21 #include <linux/phylink.h> 22 #include <linux/phy/phy.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/regmap.h> 26 #include <linux/mfd/syscon.h> 27 #include <linux/sys_soc.h> 28 #include <linux/dma/ti-cppi5.h> 29 #include <linux/dma/k3-udma-glue.h> 30 #include <net/switchdev.h> 31 32 #include "cpsw_ale.h" 33 #include "cpsw_sl.h" 34 #include "am65-cpsw-nuss.h" 35 #include "am65-cpsw-switchdev.h" 36 #include "k3-cppi-desc-pool.h" 37 #include "am65-cpts.h" 38 39 #define AM65_CPSW_SS_BASE 0x0 40 #define AM65_CPSW_SGMII_BASE 0x100 41 #define AM65_CPSW_XGMII_BASE 0x2100 42 #define AM65_CPSW_CPSW_NU_BASE 0x20000 43 #define AM65_CPSW_NU_PORTS_BASE 0x1000 44 #define AM65_CPSW_NU_FRAM_BASE 0x12000 45 #define AM65_CPSW_NU_STATS_BASE 0x1a000 46 #define AM65_CPSW_NU_ALE_BASE 0x1e000 47 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 48 49 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 50 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 51 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 52 53 #define AM65_CPSW_MAX_PORTS 8 54 55 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 56 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 57 58 #define AM65_CPSW_REG_CTL 0x004 59 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 60 #define AM65_CPSW_REG_PTYPE 0x018 61 62 #define AM65_CPSW_P0_REG_CTL 0x004 63 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 64 65 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 66 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 67 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 68 69 #define AM65_CPSW_PORTN_REG_SA_L 0x308 70 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 71 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 72 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 73 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 74 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 75 76 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 77 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 78 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 79 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 80 81 /* AM65_CPSW_P0_REG_CTL */ 82 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 83 84 /* AM65_CPSW_PORT_REG_PRI_CTL */ 85 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 86 87 /* AM65_CPSW_PN_TS_CTL register fields */ 88 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 89 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 90 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 91 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 92 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 93 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 94 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 95 96 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 97 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 98 99 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 100 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 101 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 102 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 103 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 104 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 108 109 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 110 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 111 112 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 113 114 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 115 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 116 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 117 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 118 119 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 120 /* Number of TX/RX descriptors */ 121 #define AM65_CPSW_MAX_TX_DESC 500 122 #define AM65_CPSW_MAX_RX_DESC 500 123 124 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 125 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 126 127 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 128 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 129 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 130 131 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 132 const u8 *dev_addr) 133 { 134 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 135 (dev_addr[2] << 16) | (dev_addr[3] << 24); 136 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 137 138 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 139 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 140 } 141 142 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 143 { 144 cpsw_sl_reset(port->slave.mac_sl, 100); 145 /* Max length register has to be restored after MAC SL reset */ 146 writel(AM65_CPSW_MAX_PACKET_SIZE, 147 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 148 } 149 150 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 151 { 152 common->nuss_ver = readl(common->ss_base); 153 common->cpsw_ver = readl(common->cpsw_base); 154 dev_info(common->dev, 155 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 156 common->nuss_ver, 157 common->cpsw_ver, 158 common->port_num + 1, 159 common->pdata.quirks); 160 } 161 162 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 163 __be16 proto, u16 vid) 164 { 165 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 166 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 167 u32 port_mask, unreg_mcast = 0; 168 int ret; 169 170 if (!common->is_emac_mode) 171 return 0; 172 173 if (!netif_running(ndev) || !vid) 174 return 0; 175 176 ret = pm_runtime_resume_and_get(common->dev); 177 if (ret < 0) 178 return ret; 179 180 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 181 if (!vid) 182 unreg_mcast = port_mask; 183 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 184 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 185 unreg_mcast, port_mask, 0); 186 187 pm_runtime_put(common->dev); 188 return ret; 189 } 190 191 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 192 __be16 proto, u16 vid) 193 { 194 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 195 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 196 int ret; 197 198 if (!common->is_emac_mode) 199 return 0; 200 201 if (!netif_running(ndev) || !vid) 202 return 0; 203 204 ret = pm_runtime_resume_and_get(common->dev); 205 if (ret < 0) 206 return ret; 207 208 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 209 ret = cpsw_ale_del_vlan(common->ale, vid, 210 BIT(port->port_id) | ALE_PORT_HOST); 211 212 pm_runtime_put(common->dev); 213 return ret; 214 } 215 216 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 217 bool promisc) 218 { 219 struct am65_cpsw_common *common = port->common; 220 221 if (promisc && !common->is_emac_mode) { 222 dev_dbg(common->dev, "promisc mode requested in switch mode"); 223 return; 224 } 225 226 if (promisc) { 227 /* Enable promiscuous mode */ 228 cpsw_ale_control_set(common->ale, port->port_id, 229 ALE_PORT_MACONLY_CAF, 1); 230 dev_dbg(common->dev, "promisc enabled\n"); 231 } else { 232 /* Disable promiscuous mode */ 233 cpsw_ale_control_set(common->ale, port->port_id, 234 ALE_PORT_MACONLY_CAF, 0); 235 dev_dbg(common->dev, "promisc disabled\n"); 236 } 237 } 238 239 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 240 { 241 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 242 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 243 u32 port_mask; 244 bool promisc; 245 246 promisc = !!(ndev->flags & IFF_PROMISC); 247 am65_cpsw_slave_set_promisc(port, promisc); 248 249 if (promisc) 250 return; 251 252 /* Restore allmulti on vlans if necessary */ 253 cpsw_ale_set_allmulti(common->ale, 254 ndev->flags & IFF_ALLMULTI, port->port_id); 255 256 port_mask = ALE_PORT_HOST; 257 /* Clear all mcast from ALE */ 258 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 259 260 if (!netdev_mc_empty(ndev)) { 261 struct netdev_hw_addr *ha; 262 263 /* program multicast address list into ALE register */ 264 netdev_for_each_mc_addr(ha, ndev) { 265 cpsw_ale_add_mcast(common->ale, ha->addr, 266 port_mask, 0, 0, 0); 267 } 268 } 269 } 270 271 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 272 unsigned int txqueue) 273 { 274 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 275 struct am65_cpsw_tx_chn *tx_chn; 276 struct netdev_queue *netif_txq; 277 unsigned long trans_start; 278 279 netif_txq = netdev_get_tx_queue(ndev, txqueue); 280 tx_chn = &common->tx_chns[txqueue]; 281 trans_start = READ_ONCE(netif_txq->trans_start); 282 283 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 284 txqueue, 285 netif_tx_queue_stopped(netif_txq), 286 jiffies_to_msecs(jiffies - trans_start), 287 dql_avail(&netif_txq->dql), 288 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 289 290 if (netif_tx_queue_stopped(netif_txq)) { 291 /* try recover if stopped by us */ 292 txq_trans_update(netif_txq); 293 netif_tx_wake_queue(netif_txq); 294 } 295 } 296 297 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 298 struct sk_buff *skb) 299 { 300 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 301 struct cppi5_host_desc_t *desc_rx; 302 struct device *dev = common->dev; 303 u32 pkt_len = skb_tailroom(skb); 304 dma_addr_t desc_dma; 305 dma_addr_t buf_dma; 306 void *swdata; 307 308 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 309 if (!desc_rx) { 310 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 311 return -ENOMEM; 312 } 313 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 314 315 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 316 DMA_FROM_DEVICE); 317 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 318 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 319 dev_err(dev, "Failed to map rx skb buffer\n"); 320 return -EINVAL; 321 } 322 323 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 324 AM65_CPSW_NAV_PS_DATA_SIZE); 325 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 326 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 327 swdata = cppi5_hdesc_get_swdata(desc_rx); 328 *((void **)swdata) = skb; 329 330 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 331 } 332 333 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 334 { 335 struct am65_cpsw_host *host_p = am65_common_get_host(common); 336 u32 val, pri_map; 337 338 /* P0 set Receive Priority Type */ 339 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 340 341 if (common->pf_p0_rx_ptype_rrobin) { 342 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 343 /* Enet Ports fifos works in fixed priority mode only, so 344 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 345 */ 346 pri_map = 0x0; 347 } else { 348 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 349 /* restore P0_Rx_Pri_Map */ 350 pri_map = 0x76543210; 351 } 352 353 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 354 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 355 } 356 357 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 358 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 359 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 360 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 361 362 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common, 363 netdev_features_t features) 364 { 365 struct am65_cpsw_host *host_p = am65_common_get_host(common); 366 int port_idx, i, ret; 367 struct sk_buff *skb; 368 u32 val, port_mask; 369 370 if (common->usage_count) 371 return 0; 372 373 /* Control register */ 374 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 375 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 376 common->cpsw_base + AM65_CPSW_REG_CTL); 377 /* Max length register */ 378 writel(AM65_CPSW_MAX_PACKET_SIZE, 379 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 380 /* set base flow_id */ 381 writel(common->rx_flow_id_base, 382 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 383 /* en tx crc offload */ 384 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 385 386 am65_cpsw_nuss_set_p0_ptype(common); 387 388 /* enable statistic */ 389 val = BIT(HOST_PORT_NUM); 390 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 391 struct am65_cpsw_port *port = &common->ports[port_idx]; 392 393 if (!port->disabled) 394 val |= BIT(port->port_id); 395 } 396 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 397 398 /* disable priority elevation */ 399 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 400 401 cpsw_ale_start(common->ale); 402 403 /* limit to one RX flow only */ 404 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 405 ALE_DEFAULT_THREAD_ID, 0); 406 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 407 ALE_DEFAULT_THREAD_ENABLE, 1); 408 /* switch to vlan unaware mode */ 409 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 410 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 411 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 412 413 /* default vlan cfg: create mask based on enabled ports */ 414 port_mask = GENMASK(common->port_num, 0) & 415 ~common->disabled_ports_mask; 416 417 cpsw_ale_add_vlan(common->ale, 0, port_mask, 418 port_mask, port_mask, 419 port_mask & ~ALE_PORT_HOST); 420 421 if (common->is_emac_mode) 422 am65_cpsw_init_host_port_emac(common); 423 else 424 am65_cpsw_init_host_port_switch(common); 425 426 for (i = 0; i < common->rx_chns.descs_num; i++) { 427 skb = __netdev_alloc_skb_ip_align(NULL, 428 AM65_CPSW_MAX_PACKET_SIZE, 429 GFP_KERNEL); 430 if (!skb) { 431 dev_err(common->dev, "cannot allocate skb\n"); 432 return -ENOMEM; 433 } 434 435 ret = am65_cpsw_nuss_rx_push(common, skb); 436 if (ret < 0) { 437 dev_err(common->dev, 438 "cannot submit skb to channel rx, error %d\n", 439 ret); 440 kfree_skb(skb); 441 return ret; 442 } 443 kmemleak_not_leak(skb); 444 } 445 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 446 447 for (i = 0; i < common->tx_ch_num; i++) { 448 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 449 if (ret) 450 return ret; 451 napi_enable(&common->tx_chns[i].napi_tx); 452 } 453 454 napi_enable(&common->napi_rx); 455 if (common->rx_irq_disabled) { 456 common->rx_irq_disabled = false; 457 enable_irq(common->rx_chns.irq); 458 } 459 460 dev_dbg(common->dev, "cpsw_nuss started\n"); 461 return 0; 462 } 463 464 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 465 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 466 467 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 468 { 469 int i; 470 471 if (common->usage_count != 1) 472 return 0; 473 474 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 475 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 476 477 /* shutdown tx channels */ 478 atomic_set(&common->tdown_cnt, common->tx_ch_num); 479 /* ensure new tdown_cnt value is visible */ 480 smp_mb__after_atomic(); 481 reinit_completion(&common->tdown_complete); 482 483 for (i = 0; i < common->tx_ch_num; i++) 484 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 485 486 i = wait_for_completion_timeout(&common->tdown_complete, 487 msecs_to_jiffies(1000)); 488 if (!i) 489 dev_err(common->dev, "tx timeout\n"); 490 for (i = 0; i < common->tx_ch_num; i++) 491 napi_disable(&common->tx_chns[i].napi_tx); 492 493 for (i = 0; i < common->tx_ch_num; i++) { 494 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 495 &common->tx_chns[i], 496 am65_cpsw_nuss_tx_cleanup); 497 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 498 } 499 500 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 501 napi_disable(&common->napi_rx); 502 503 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 504 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 505 &common->rx_chns, 506 am65_cpsw_nuss_rx_cleanup, !!i); 507 508 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 509 510 cpsw_ale_stop(common->ale); 511 512 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 513 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 514 515 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 516 return 0; 517 } 518 519 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 520 { 521 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 522 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 523 int ret; 524 525 phylink_stop(port->slave.phylink); 526 527 netif_tx_stop_all_queues(ndev); 528 529 phylink_disconnect_phy(port->slave.phylink); 530 531 ret = am65_cpsw_nuss_common_stop(common); 532 if (ret) 533 return ret; 534 535 common->usage_count--; 536 pm_runtime_put(common->dev); 537 return 0; 538 } 539 540 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 541 { 542 struct am65_cpsw_port *port = arg; 543 544 if (!vdev) 545 return 0; 546 547 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 548 } 549 550 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 551 { 552 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 553 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 554 int ret, i; 555 556 ret = pm_runtime_resume_and_get(common->dev); 557 if (ret < 0) 558 return ret; 559 560 /* Notify the stack of the actual queue counts. */ 561 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 562 if (ret) { 563 dev_err(common->dev, "cannot set real number of tx queues\n"); 564 return ret; 565 } 566 567 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 568 if (ret) { 569 dev_err(common->dev, "cannot set real number of rx queues\n"); 570 return ret; 571 } 572 573 for (i = 0; i < common->tx_ch_num; i++) 574 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 575 576 ret = am65_cpsw_nuss_common_open(common, ndev->features); 577 if (ret) 578 return ret; 579 580 common->usage_count++; 581 582 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 583 584 if (common->is_emac_mode) 585 am65_cpsw_init_port_emac_ale(port); 586 else 587 am65_cpsw_init_port_switch_ale(port); 588 589 /* mac_sl should be configured via phy-link interface */ 590 am65_cpsw_sl_ctl_reset(port); 591 592 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, 593 port->slave.phy_if); 594 if (ret) 595 goto error_cleanup; 596 597 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 598 if (ret) 599 goto error_cleanup; 600 601 /* restore vlan configurations */ 602 vlan_for_each(ndev, cpsw_restore_vlans, port); 603 604 phylink_start(port->slave.phylink); 605 606 return 0; 607 608 error_cleanup: 609 am65_cpsw_nuss_ndo_slave_stop(ndev); 610 return ret; 611 } 612 613 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 614 { 615 struct am65_cpsw_rx_chn *rx_chn = data; 616 struct cppi5_host_desc_t *desc_rx; 617 struct sk_buff *skb; 618 dma_addr_t buf_dma; 619 u32 buf_dma_len; 620 void **swdata; 621 622 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 623 swdata = cppi5_hdesc_get_swdata(desc_rx); 624 skb = *swdata; 625 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 626 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 627 628 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 629 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 630 631 dev_kfree_skb_any(skb); 632 } 633 634 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 635 { 636 struct skb_shared_hwtstamps *ssh; 637 u64 ns; 638 639 ns = ((u64)psdata[1] << 32) | psdata[0]; 640 641 ssh = skb_hwtstamps(skb); 642 memset(ssh, 0, sizeof(*ssh)); 643 ssh->hwtstamp = ns_to_ktime(ns); 644 } 645 646 /* RX psdata[2] word format - checksum information */ 647 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 648 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 649 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 650 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 651 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 652 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 653 654 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 655 { 656 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 657 * csum information provides in psdata[2] word: 658 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 659 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 660 * bits - indicates IPv4/IPv6 packet 661 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 662 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 663 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 664 */ 665 skb_checksum_none_assert(skb); 666 667 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 668 return; 669 670 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 671 AM65_CPSW_RX_PSD_IPV4_VALID)) && 672 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 673 /* csum for fragmented packets is unsupported */ 674 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 675 skb->ip_summed = CHECKSUM_UNNECESSARY; 676 } 677 } 678 679 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 680 u32 flow_idx) 681 { 682 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 683 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 684 struct am65_cpsw_ndev_priv *ndev_priv; 685 struct am65_cpsw_ndev_stats *stats; 686 struct cppi5_host_desc_t *desc_rx; 687 struct device *dev = common->dev; 688 struct sk_buff *skb, *new_skb; 689 dma_addr_t desc_dma, buf_dma; 690 struct am65_cpsw_port *port; 691 struct net_device *ndev; 692 void **swdata; 693 u32 *psdata; 694 int ret = 0; 695 696 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 697 if (ret) { 698 if (ret != -ENODATA) 699 dev_err(dev, "RX: pop chn fail %d\n", ret); 700 return ret; 701 } 702 703 if (cppi5_desc_is_tdcm(desc_dma)) { 704 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 705 return 0; 706 } 707 708 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 709 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 710 __func__, flow_idx, &desc_dma); 711 712 swdata = cppi5_hdesc_get_swdata(desc_rx); 713 skb = *swdata; 714 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 715 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 716 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 717 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 718 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 719 port = am65_common_get_port(common, port_id); 720 ndev = port->ndev; 721 skb->dev = ndev; 722 723 psdata = cppi5_hdesc_get_psdata(desc_rx); 724 /* add RX timestamp */ 725 if (port->rx_ts_enabled) 726 am65_cpsw_nuss_rx_ts(skb, psdata); 727 csum_info = psdata[2]; 728 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 729 730 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 731 732 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 733 734 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 735 if (new_skb) { 736 ndev_priv = netdev_priv(ndev); 737 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 738 skb_put(skb, pkt_len); 739 skb->protocol = eth_type_trans(skb, ndev); 740 am65_cpsw_nuss_rx_csum(skb, csum_info); 741 napi_gro_receive(&common->napi_rx, skb); 742 743 stats = this_cpu_ptr(ndev_priv->stats); 744 745 u64_stats_update_begin(&stats->syncp); 746 stats->rx_packets++; 747 stats->rx_bytes += pkt_len; 748 u64_stats_update_end(&stats->syncp); 749 kmemleak_not_leak(new_skb); 750 } else { 751 ndev->stats.rx_dropped++; 752 new_skb = skb; 753 } 754 755 if (netif_dormant(ndev)) { 756 dev_kfree_skb_any(new_skb); 757 ndev->stats.rx_dropped++; 758 return 0; 759 } 760 761 ret = am65_cpsw_nuss_rx_push(common, new_skb); 762 if (WARN_ON(ret < 0)) { 763 dev_kfree_skb_any(new_skb); 764 ndev->stats.rx_errors++; 765 ndev->stats.rx_dropped++; 766 } 767 768 return ret; 769 } 770 771 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 772 { 773 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 774 int flow = AM65_CPSW_MAX_RX_FLOWS; 775 int cur_budget, ret; 776 int num_rx = 0; 777 778 /* process every flow */ 779 while (flow--) { 780 cur_budget = budget - num_rx; 781 782 while (cur_budget--) { 783 ret = am65_cpsw_nuss_rx_packets(common, flow); 784 if (ret) 785 break; 786 num_rx++; 787 } 788 789 if (num_rx >= budget) 790 break; 791 } 792 793 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 794 795 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 796 if (common->rx_irq_disabled) { 797 common->rx_irq_disabled = false; 798 enable_irq(common->rx_chns.irq); 799 } 800 } 801 802 return num_rx; 803 } 804 805 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 806 struct cppi5_host_desc_t *desc) 807 { 808 struct cppi5_host_desc_t *first_desc, *next_desc; 809 dma_addr_t buf_dma, next_desc_dma; 810 u32 buf_dma_len; 811 812 first_desc = desc; 813 next_desc = first_desc; 814 815 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 816 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 817 818 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 819 820 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 821 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 822 while (next_desc_dma) { 823 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 824 next_desc_dma); 825 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 826 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 827 828 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 829 DMA_TO_DEVICE); 830 831 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 832 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 833 834 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 835 } 836 837 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 838 } 839 840 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 841 { 842 struct am65_cpsw_tx_chn *tx_chn = data; 843 struct cppi5_host_desc_t *desc_tx; 844 struct sk_buff *skb; 845 void **swdata; 846 847 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 848 swdata = cppi5_hdesc_get_swdata(desc_tx); 849 skb = *(swdata); 850 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 851 852 dev_kfree_skb_any(skb); 853 } 854 855 static struct sk_buff * 856 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 857 dma_addr_t desc_dma) 858 { 859 struct am65_cpsw_ndev_priv *ndev_priv; 860 struct am65_cpsw_ndev_stats *stats; 861 struct cppi5_host_desc_t *desc_tx; 862 struct net_device *ndev; 863 struct sk_buff *skb; 864 void **swdata; 865 866 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 867 desc_dma); 868 swdata = cppi5_hdesc_get_swdata(desc_tx); 869 skb = *(swdata); 870 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 871 872 ndev = skb->dev; 873 874 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 875 876 ndev_priv = netdev_priv(ndev); 877 stats = this_cpu_ptr(ndev_priv->stats); 878 u64_stats_update_begin(&stats->syncp); 879 stats->tx_packets++; 880 stats->tx_bytes += skb->len; 881 u64_stats_update_end(&stats->syncp); 882 883 return skb; 884 } 885 886 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 887 struct netdev_queue *netif_txq) 888 { 889 if (netif_tx_queue_stopped(netif_txq)) { 890 /* Check whether the queue is stopped due to stalled 891 * tx dma, if the queue is stopped then wake the queue 892 * as we have free desc for tx 893 */ 894 __netif_tx_lock(netif_txq, smp_processor_id()); 895 if (netif_running(ndev) && 896 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 897 netif_tx_wake_queue(netif_txq); 898 899 __netif_tx_unlock(netif_txq); 900 } 901 } 902 903 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 904 int chn, unsigned int budget) 905 { 906 struct device *dev = common->dev; 907 struct am65_cpsw_tx_chn *tx_chn; 908 struct netdev_queue *netif_txq; 909 unsigned int total_bytes = 0; 910 struct net_device *ndev; 911 struct sk_buff *skb; 912 dma_addr_t desc_dma; 913 int res, num_tx = 0; 914 915 tx_chn = &common->tx_chns[chn]; 916 917 while (true) { 918 spin_lock(&tx_chn->lock); 919 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 920 spin_unlock(&tx_chn->lock); 921 if (res == -ENODATA) 922 break; 923 924 if (cppi5_desc_is_tdcm(desc_dma)) { 925 if (atomic_dec_and_test(&common->tdown_cnt)) 926 complete(&common->tdown_complete); 927 break; 928 } 929 930 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 931 total_bytes = skb->len; 932 ndev = skb->dev; 933 napi_consume_skb(skb, budget); 934 num_tx++; 935 936 netif_txq = netdev_get_tx_queue(ndev, chn); 937 938 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 939 940 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 941 } 942 943 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 944 945 return num_tx; 946 } 947 948 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 949 int chn, unsigned int budget) 950 { 951 struct device *dev = common->dev; 952 struct am65_cpsw_tx_chn *tx_chn; 953 struct netdev_queue *netif_txq; 954 unsigned int total_bytes = 0; 955 struct net_device *ndev; 956 struct sk_buff *skb; 957 dma_addr_t desc_dma; 958 int res, num_tx = 0; 959 960 tx_chn = &common->tx_chns[chn]; 961 962 while (true) { 963 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 964 if (res == -ENODATA) 965 break; 966 967 if (cppi5_desc_is_tdcm(desc_dma)) { 968 if (atomic_dec_and_test(&common->tdown_cnt)) 969 complete(&common->tdown_complete); 970 break; 971 } 972 973 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 974 975 ndev = skb->dev; 976 total_bytes += skb->len; 977 napi_consume_skb(skb, budget); 978 num_tx++; 979 } 980 981 if (!num_tx) 982 return 0; 983 984 netif_txq = netdev_get_tx_queue(ndev, chn); 985 986 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 987 988 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 989 990 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 991 992 return num_tx; 993 } 994 995 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 996 { 997 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 998 int num_tx; 999 1000 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1001 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1002 else 1003 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1004 1005 if (num_tx >= budget) 1006 return budget; 1007 1008 if (napi_complete_done(napi_tx, num_tx)) 1009 enable_irq(tx_chn->irq); 1010 1011 return 0; 1012 } 1013 1014 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1015 { 1016 struct am65_cpsw_common *common = dev_id; 1017 1018 common->rx_irq_disabled = true; 1019 disable_irq_nosync(irq); 1020 napi_schedule(&common->napi_rx); 1021 1022 return IRQ_HANDLED; 1023 } 1024 1025 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1026 { 1027 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1028 1029 disable_irq_nosync(irq); 1030 napi_schedule(&tx_chn->napi_tx); 1031 1032 return IRQ_HANDLED; 1033 } 1034 1035 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1036 struct net_device *ndev) 1037 { 1038 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1039 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1040 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1041 struct device *dev = common->dev; 1042 struct am65_cpsw_tx_chn *tx_chn; 1043 struct netdev_queue *netif_txq; 1044 dma_addr_t desc_dma, buf_dma; 1045 int ret, q_idx, i; 1046 void **swdata; 1047 u32 *psdata; 1048 u32 pkt_len; 1049 1050 /* padding enabled in hw */ 1051 pkt_len = skb_headlen(skb); 1052 1053 /* SKB TX timestamp */ 1054 if (port->tx_ts_enabled) 1055 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1056 1057 q_idx = skb_get_queue_mapping(skb); 1058 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1059 1060 tx_chn = &common->tx_chns[q_idx]; 1061 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1062 1063 /* Map the linear buffer */ 1064 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1065 DMA_TO_DEVICE); 1066 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1067 dev_err(dev, "Failed to map tx skb buffer\n"); 1068 ndev->stats.tx_errors++; 1069 goto err_free_skb; 1070 } 1071 1072 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1073 if (!first_desc) { 1074 dev_dbg(dev, "Failed to allocate descriptor\n"); 1075 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1076 DMA_TO_DEVICE); 1077 goto busy_stop_q; 1078 } 1079 1080 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1081 AM65_CPSW_NAV_PS_DATA_SIZE); 1082 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1083 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1084 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1085 1086 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1087 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1088 swdata = cppi5_hdesc_get_swdata(first_desc); 1089 *(swdata) = skb; 1090 psdata = cppi5_hdesc_get_psdata(first_desc); 1091 1092 /* HW csum offload if enabled */ 1093 psdata[2] = 0; 1094 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1095 unsigned int cs_start, cs_offset; 1096 1097 cs_start = skb_transport_offset(skb); 1098 cs_offset = cs_start + skb->csum_offset; 1099 /* HW numerates bytes starting from 1 */ 1100 psdata[2] = ((cs_offset + 1) << 24) | 1101 ((cs_start + 1) << 16) | (skb->len - cs_start); 1102 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1103 } 1104 1105 if (!skb_is_nonlinear(skb)) 1106 goto done_tx; 1107 1108 dev_dbg(dev, "fragmented SKB\n"); 1109 1110 /* Handle the case where skb is fragmented in pages */ 1111 cur_desc = first_desc; 1112 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1113 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1114 u32 frag_size = skb_frag_size(frag); 1115 1116 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1117 if (!next_desc) { 1118 dev_err(dev, "Failed to allocate descriptor\n"); 1119 goto busy_free_descs; 1120 } 1121 1122 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1123 DMA_TO_DEVICE); 1124 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1125 dev_err(dev, "Failed to map tx skb page\n"); 1126 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1127 ndev->stats.tx_errors++; 1128 goto err_free_descs; 1129 } 1130 1131 cppi5_hdesc_reset_hbdesc(next_desc); 1132 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1133 cppi5_hdesc_attach_buf(next_desc, 1134 buf_dma, frag_size, buf_dma, frag_size); 1135 1136 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1137 next_desc); 1138 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1139 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1140 1141 pkt_len += frag_size; 1142 cur_desc = next_desc; 1143 } 1144 WARN_ON(pkt_len != skb->len); 1145 1146 done_tx: 1147 skb_tx_timestamp(skb); 1148 1149 /* report bql before sending packet */ 1150 netdev_tx_sent_queue(netif_txq, pkt_len); 1151 1152 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1153 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1154 if (AM65_CPSW_IS_CPSW2G(common)) { 1155 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1156 } else { 1157 spin_lock_bh(&tx_chn->lock); 1158 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1159 spin_unlock_bh(&tx_chn->lock); 1160 } 1161 if (ret) { 1162 dev_err(dev, "can't push desc %d\n", ret); 1163 /* inform bql */ 1164 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1165 ndev->stats.tx_errors++; 1166 goto err_free_descs; 1167 } 1168 1169 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1170 netif_tx_stop_queue(netif_txq); 1171 /* Barrier, so that stop_queue visible to other cpus */ 1172 smp_mb__after_atomic(); 1173 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1174 1175 /* re-check for smp */ 1176 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1177 MAX_SKB_FRAGS) { 1178 netif_tx_wake_queue(netif_txq); 1179 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1180 } 1181 } 1182 1183 return NETDEV_TX_OK; 1184 1185 err_free_descs: 1186 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1187 err_free_skb: 1188 ndev->stats.tx_dropped++; 1189 dev_kfree_skb_any(skb); 1190 return NETDEV_TX_OK; 1191 1192 busy_free_descs: 1193 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1194 busy_stop_q: 1195 netif_tx_stop_queue(netif_txq); 1196 return NETDEV_TX_BUSY; 1197 } 1198 1199 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1200 void *addr) 1201 { 1202 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1203 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1204 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1205 int ret; 1206 1207 ret = eth_prepare_mac_addr_change(ndev, addr); 1208 if (ret < 0) 1209 return ret; 1210 1211 ret = pm_runtime_resume_and_get(common->dev); 1212 if (ret < 0) 1213 return ret; 1214 1215 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1216 HOST_PORT_NUM, 0, 0); 1217 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1218 HOST_PORT_NUM, ALE_SECURE, 0); 1219 1220 am65_cpsw_port_set_sl_mac(port, addr); 1221 eth_commit_mac_addr_change(ndev, sockaddr); 1222 1223 pm_runtime_put(common->dev); 1224 1225 return 0; 1226 } 1227 1228 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1229 struct ifreq *ifr) 1230 { 1231 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1232 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1233 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1234 struct hwtstamp_config cfg; 1235 1236 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1237 return -EOPNOTSUPP; 1238 1239 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1240 return -EFAULT; 1241 1242 /* TX HW timestamp */ 1243 switch (cfg.tx_type) { 1244 case HWTSTAMP_TX_OFF: 1245 case HWTSTAMP_TX_ON: 1246 break; 1247 default: 1248 return -ERANGE; 1249 } 1250 1251 switch (cfg.rx_filter) { 1252 case HWTSTAMP_FILTER_NONE: 1253 port->rx_ts_enabled = false; 1254 break; 1255 case HWTSTAMP_FILTER_ALL: 1256 case HWTSTAMP_FILTER_SOME: 1257 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1258 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1259 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1260 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1261 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1262 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1263 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1264 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1265 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1266 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1267 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1268 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1269 case HWTSTAMP_FILTER_NTP_ALL: 1270 port->rx_ts_enabled = true; 1271 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1272 break; 1273 default: 1274 return -ERANGE; 1275 } 1276 1277 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1278 1279 /* cfg TX timestamp */ 1280 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1281 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1282 1283 ts_vlan_ltype = ETH_P_8021Q; 1284 1285 ts_ctrl_ltype2 = ETH_P_1588 | 1286 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1287 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1288 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1289 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1290 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1291 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1292 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1293 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1294 1295 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1296 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1297 1298 if (port->tx_ts_enabled) 1299 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1300 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1301 1302 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1303 writel(ts_vlan_ltype, port->port_base + 1304 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1305 writel(ts_ctrl_ltype2, port->port_base + 1306 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1307 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1308 1309 /* en/dis RX timestamp */ 1310 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1311 1312 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1313 } 1314 1315 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1316 struct ifreq *ifr) 1317 { 1318 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1319 struct hwtstamp_config cfg; 1320 1321 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1322 return -EOPNOTSUPP; 1323 1324 cfg.flags = 0; 1325 cfg.tx_type = port->tx_ts_enabled ? 1326 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1327 cfg.rx_filter = port->rx_ts_enabled ? 1328 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1329 1330 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1331 } 1332 1333 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1334 struct ifreq *req, int cmd) 1335 { 1336 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1337 1338 if (!netif_running(ndev)) 1339 return -EINVAL; 1340 1341 switch (cmd) { 1342 case SIOCSHWTSTAMP: 1343 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1344 case SIOCGHWTSTAMP: 1345 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1346 } 1347 1348 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1349 } 1350 1351 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1352 struct rtnl_link_stats64 *stats) 1353 { 1354 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1355 unsigned int start; 1356 int cpu; 1357 1358 for_each_possible_cpu(cpu) { 1359 struct am65_cpsw_ndev_stats *cpu_stats; 1360 u64 rx_packets; 1361 u64 rx_bytes; 1362 u64 tx_packets; 1363 u64 tx_bytes; 1364 1365 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1366 do { 1367 start = u64_stats_fetch_begin_irq(&cpu_stats->syncp); 1368 rx_packets = cpu_stats->rx_packets; 1369 rx_bytes = cpu_stats->rx_bytes; 1370 tx_packets = cpu_stats->tx_packets; 1371 tx_bytes = cpu_stats->tx_bytes; 1372 } while (u64_stats_fetch_retry_irq(&cpu_stats->syncp, start)); 1373 1374 stats->rx_packets += rx_packets; 1375 stats->rx_bytes += rx_bytes; 1376 stats->tx_packets += tx_packets; 1377 stats->tx_bytes += tx_bytes; 1378 } 1379 1380 stats->rx_errors = dev->stats.rx_errors; 1381 stats->rx_dropped = dev->stats.rx_dropped; 1382 stats->tx_dropped = dev->stats.tx_dropped; 1383 } 1384 1385 static struct devlink_port *am65_cpsw_ndo_get_devlink_port(struct net_device *ndev) 1386 { 1387 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1388 1389 return &port->devlink_port; 1390 } 1391 1392 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1393 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1394 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1395 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1396 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1397 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1398 .ndo_validate_addr = eth_validate_addr, 1399 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1400 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1401 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1402 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1403 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1404 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1405 .ndo_get_devlink_port = am65_cpsw_ndo_get_devlink_port, 1406 }; 1407 1408 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1409 const struct phylink_link_state *state) 1410 { 1411 /* Currently not used */ 1412 } 1413 1414 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1415 phy_interface_t interface) 1416 { 1417 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1418 phylink_config); 1419 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1420 struct am65_cpsw_common *common = port->common; 1421 struct net_device *ndev = port->ndev; 1422 int tmo; 1423 1424 /* disable forwarding */ 1425 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1426 1427 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1428 1429 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1430 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1431 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1432 1433 cpsw_sl_ctl_reset(port->slave.mac_sl); 1434 1435 am65_cpsw_qos_link_down(ndev); 1436 netif_tx_stop_all_queues(ndev); 1437 } 1438 1439 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1440 unsigned int mode, phy_interface_t interface, int speed, 1441 int duplex, bool tx_pause, bool rx_pause) 1442 { 1443 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1444 phylink_config); 1445 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1446 struct am65_cpsw_common *common = port->common; 1447 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1448 struct net_device *ndev = port->ndev; 1449 1450 if (speed == SPEED_1000) 1451 mac_control |= CPSW_SL_CTL_GIG; 1452 if (speed == SPEED_10 && interface == PHY_INTERFACE_MODE_RGMII) 1453 /* Can be used with in band mode only */ 1454 mac_control |= CPSW_SL_CTL_EXT_EN; 1455 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1456 mac_control |= CPSW_SL_CTL_IFCTL_A; 1457 if (duplex) 1458 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1459 1460 /* rx_pause/tx_pause */ 1461 if (rx_pause) 1462 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1463 1464 if (tx_pause) 1465 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1466 1467 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1468 1469 /* enable forwarding */ 1470 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1471 1472 am65_cpsw_qos_link_up(ndev, speed); 1473 netif_tx_wake_all_queues(ndev); 1474 } 1475 1476 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1477 .validate = phylink_generic_validate, 1478 .mac_config = am65_cpsw_nuss_mac_config, 1479 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1480 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1481 }; 1482 1483 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1484 { 1485 struct am65_cpsw_common *common = port->common; 1486 1487 if (!port->disabled) 1488 return; 1489 1490 cpsw_ale_control_set(common->ale, port->port_id, 1491 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1492 1493 cpsw_sl_reset(port->slave.mac_sl, 100); 1494 cpsw_sl_ctl_reset(port->slave.mac_sl); 1495 } 1496 1497 static void am65_cpsw_nuss_free_tx_chns(void *data) 1498 { 1499 struct am65_cpsw_common *common = data; 1500 int i; 1501 1502 for (i = 0; i < common->tx_ch_num; i++) { 1503 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1504 1505 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1506 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1507 1508 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1509 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1510 1511 memset(tx_chn, 0, sizeof(*tx_chn)); 1512 } 1513 } 1514 1515 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1516 { 1517 struct device *dev = common->dev; 1518 int i; 1519 1520 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1521 1522 for (i = 0; i < common->tx_ch_num; i++) { 1523 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1524 1525 if (tx_chn->irq) 1526 devm_free_irq(dev, tx_chn->irq, tx_chn); 1527 1528 netif_napi_del(&tx_chn->napi_tx); 1529 1530 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1531 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1532 1533 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1534 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1535 1536 memset(tx_chn, 0, sizeof(*tx_chn)); 1537 } 1538 } 1539 1540 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1541 { 1542 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1543 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1544 struct device *dev = common->dev; 1545 struct k3_ring_cfg ring_cfg = { 1546 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1547 .mode = K3_RINGACC_RING_MODE_RING, 1548 .flags = 0 1549 }; 1550 u32 hdesc_size; 1551 int i, ret = 0; 1552 1553 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1554 AM65_CPSW_NAV_SW_DATA_SIZE); 1555 1556 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1557 tx_cfg.tx_cfg = ring_cfg; 1558 tx_cfg.txcq_cfg = ring_cfg; 1559 tx_cfg.tx_cfg.size = max_desc_num; 1560 tx_cfg.txcq_cfg.size = max_desc_num; 1561 1562 for (i = 0; i < common->tx_ch_num; i++) { 1563 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1564 1565 snprintf(tx_chn->tx_chn_name, 1566 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1567 1568 spin_lock_init(&tx_chn->lock); 1569 tx_chn->common = common; 1570 tx_chn->id = i; 1571 tx_chn->descs_num = max_desc_num; 1572 1573 tx_chn->tx_chn = 1574 k3_udma_glue_request_tx_chn(dev, 1575 tx_chn->tx_chn_name, 1576 &tx_cfg); 1577 if (IS_ERR(tx_chn->tx_chn)) { 1578 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1579 "Failed to request tx dma channel\n"); 1580 goto err; 1581 } 1582 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1583 1584 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1585 tx_chn->descs_num, 1586 hdesc_size, 1587 tx_chn->tx_chn_name); 1588 if (IS_ERR(tx_chn->desc_pool)) { 1589 ret = PTR_ERR(tx_chn->desc_pool); 1590 dev_err(dev, "Failed to create poll %d\n", ret); 1591 goto err; 1592 } 1593 1594 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1595 if (tx_chn->irq <= 0) { 1596 dev_err(dev, "Failed to get tx dma irq %d\n", 1597 tx_chn->irq); 1598 goto err; 1599 } 1600 1601 snprintf(tx_chn->tx_chn_name, 1602 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1603 dev_name(dev), tx_chn->id); 1604 } 1605 1606 err: 1607 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1608 if (i) { 1609 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1610 return i; 1611 } 1612 1613 return ret; 1614 } 1615 1616 static void am65_cpsw_nuss_free_rx_chns(void *data) 1617 { 1618 struct am65_cpsw_common *common = data; 1619 struct am65_cpsw_rx_chn *rx_chn; 1620 1621 rx_chn = &common->rx_chns; 1622 1623 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1624 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1625 1626 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1627 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1628 } 1629 1630 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1631 { 1632 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1633 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1634 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1635 struct device *dev = common->dev; 1636 u32 hdesc_size; 1637 u32 fdqring_id; 1638 int i, ret = 0; 1639 1640 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1641 AM65_CPSW_NAV_SW_DATA_SIZE); 1642 1643 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1644 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1645 rx_cfg.flow_id_base = common->rx_flow_id_base; 1646 1647 /* init all flows */ 1648 rx_chn->dev = dev; 1649 rx_chn->descs_num = max_desc_num; 1650 1651 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1652 if (IS_ERR(rx_chn->rx_chn)) { 1653 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1654 "Failed to request rx dma channel\n"); 1655 goto err; 1656 } 1657 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1658 1659 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1660 rx_chn->descs_num, 1661 hdesc_size, "rx"); 1662 if (IS_ERR(rx_chn->desc_pool)) { 1663 ret = PTR_ERR(rx_chn->desc_pool); 1664 dev_err(dev, "Failed to create rx poll %d\n", ret); 1665 goto err; 1666 } 1667 1668 common->rx_flow_id_base = 1669 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1670 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1671 1672 fdqring_id = K3_RINGACC_RING_ID_ANY; 1673 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1674 struct k3_ring_cfg rxring_cfg = { 1675 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1676 .mode = K3_RINGACC_RING_MODE_RING, 1677 .flags = 0, 1678 }; 1679 struct k3_ring_cfg fdqring_cfg = { 1680 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1681 .flags = K3_RINGACC_RING_SHARED, 1682 }; 1683 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1684 .rx_cfg = rxring_cfg, 1685 .rxfdq_cfg = fdqring_cfg, 1686 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1687 .src_tag_lo_sel = 1688 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1689 }; 1690 1691 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1692 rx_flow_cfg.rx_cfg.size = max_desc_num; 1693 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1694 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1695 1696 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1697 i, &rx_flow_cfg); 1698 if (ret) { 1699 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1700 goto err; 1701 } 1702 if (!i) 1703 fdqring_id = 1704 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1705 i); 1706 1707 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1708 1709 if (rx_chn->irq <= 0) { 1710 dev_err(dev, "Failed to get rx dma irq %d\n", 1711 rx_chn->irq); 1712 ret = -ENXIO; 1713 goto err; 1714 } 1715 } 1716 1717 err: 1718 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1719 if (i) { 1720 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1721 return i; 1722 } 1723 1724 return ret; 1725 } 1726 1727 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1728 { 1729 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1730 1731 host_p->common = common; 1732 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1733 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1734 1735 return 0; 1736 } 1737 1738 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1739 int slave, u8 *mac_addr) 1740 { 1741 u32 mac_lo, mac_hi, offset; 1742 struct regmap *syscon; 1743 int ret; 1744 1745 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1746 if (IS_ERR(syscon)) { 1747 if (PTR_ERR(syscon) == -ENODEV) 1748 return 0; 1749 return PTR_ERR(syscon); 1750 } 1751 1752 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1753 &offset); 1754 if (ret) 1755 return ret; 1756 1757 regmap_read(syscon, offset, &mac_lo); 1758 regmap_read(syscon, offset + 4, &mac_hi); 1759 1760 mac_addr[0] = (mac_hi >> 8) & 0xff; 1761 mac_addr[1] = mac_hi & 0xff; 1762 mac_addr[2] = (mac_lo >> 24) & 0xff; 1763 mac_addr[3] = (mac_lo >> 16) & 0xff; 1764 mac_addr[4] = (mac_lo >> 8) & 0xff; 1765 mac_addr[5] = mac_lo & 0xff; 1766 1767 return 0; 1768 } 1769 1770 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1771 { 1772 struct device *dev = common->dev; 1773 struct device_node *node; 1774 struct am65_cpts *cpts; 1775 void __iomem *reg_base; 1776 1777 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1778 return 0; 1779 1780 node = of_get_child_by_name(dev->of_node, "cpts"); 1781 if (!node) { 1782 dev_err(dev, "%s cpts not found\n", __func__); 1783 return -ENOENT; 1784 } 1785 1786 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1787 cpts = am65_cpts_create(dev, reg_base, node); 1788 if (IS_ERR(cpts)) { 1789 int ret = PTR_ERR(cpts); 1790 1791 if (ret == -EOPNOTSUPP) { 1792 dev_info(dev, "cpts disabled\n"); 1793 return 0; 1794 } 1795 1796 dev_err(dev, "cpts create err %d\n", ret); 1797 return ret; 1798 } 1799 common->cpts = cpts; 1800 /* Forbid PM runtime if CPTS is running. 1801 * K3 CPSWxG modules may completely lose context during ON->OFF 1802 * transitions depending on integration. 1803 * AM65x/J721E MCU CPSW2G: false 1804 * J721E MAIN_CPSW9G: true 1805 */ 1806 pm_runtime_forbid(dev); 1807 1808 return 0; 1809 } 1810 1811 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1812 { 1813 struct device_node *node, *port_np; 1814 struct device *dev = common->dev; 1815 int ret; 1816 1817 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1818 if (!node) 1819 return -ENOENT; 1820 1821 for_each_child_of_node(node, port_np) { 1822 struct am65_cpsw_port *port; 1823 u32 port_id; 1824 1825 /* it is not a slave port node, continue */ 1826 if (strcmp(port_np->name, "port")) 1827 continue; 1828 1829 ret = of_property_read_u32(port_np, "reg", &port_id); 1830 if (ret < 0) { 1831 dev_err(dev, "%pOF error reading port_id %d\n", 1832 port_np, ret); 1833 goto of_node_put; 1834 } 1835 1836 if (!port_id || port_id > common->port_num) { 1837 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1838 port_np, port_id, port_np->name); 1839 ret = -EINVAL; 1840 goto of_node_put; 1841 } 1842 1843 port = am65_common_get_port(common, port_id); 1844 port->port_id = port_id; 1845 port->common = common; 1846 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1847 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1848 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1849 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1850 port->name = of_get_property(port_np, "label", NULL); 1851 port->fetch_ram_base = 1852 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1853 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1854 1855 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1856 if (IS_ERR(port->slave.mac_sl)) { 1857 ret = PTR_ERR(port->slave.mac_sl); 1858 goto of_node_put; 1859 } 1860 1861 port->disabled = !of_device_is_available(port_np); 1862 if (port->disabled) { 1863 common->disabled_ports_mask |= BIT(port->port_id); 1864 continue; 1865 } 1866 1867 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1868 if (IS_ERR(port->slave.ifphy)) { 1869 ret = PTR_ERR(port->slave.ifphy); 1870 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1871 port_np, ret); 1872 goto of_node_put; 1873 } 1874 1875 port->slave.mac_only = 1876 of_property_read_bool(port_np, "ti,mac-only"); 1877 1878 /* get phy/link info */ 1879 port->slave.phy_node = port_np; 1880 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1881 if (ret) { 1882 dev_err(dev, "%pOF read phy-mode err %d\n", 1883 port_np, ret); 1884 goto of_node_put; 1885 } 1886 1887 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1888 if (ret) { 1889 am65_cpsw_am654_get_efuse_macid(port_np, 1890 port->port_id, 1891 port->slave.mac_addr); 1892 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1893 eth_random_addr(port->slave.mac_addr); 1894 dev_err(dev, "Use random MAC address\n"); 1895 } 1896 } 1897 } 1898 of_node_put(node); 1899 1900 /* is there at least one ext.port */ 1901 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1902 dev_err(dev, "No Ext. port are available\n"); 1903 return -ENODEV; 1904 } 1905 1906 return 0; 1907 1908 of_node_put: 1909 of_node_put(port_np); 1910 of_node_put(node); 1911 return ret; 1912 } 1913 1914 static void am65_cpsw_pcpu_stats_free(void *data) 1915 { 1916 struct am65_cpsw_ndev_stats __percpu *stats = data; 1917 1918 free_percpu(stats); 1919 } 1920 1921 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 1922 { 1923 struct am65_cpsw_port *port; 1924 int i; 1925 1926 for (i = 0; i < common->port_num; i++) { 1927 port = &common->ports[i]; 1928 if (port->slave.phylink) 1929 phylink_destroy(port->slave.phylink); 1930 } 1931 } 1932 1933 static int 1934 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 1935 { 1936 struct am65_cpsw_ndev_priv *ndev_priv; 1937 struct device *dev = common->dev; 1938 struct am65_cpsw_port *port; 1939 struct phylink *phylink; 1940 int ret; 1941 1942 port = &common->ports[port_idx]; 1943 1944 if (port->disabled) 1945 return 0; 1946 1947 /* alloc netdev */ 1948 port->ndev = devm_alloc_etherdev_mqs(common->dev, 1949 sizeof(struct am65_cpsw_ndev_priv), 1950 AM65_CPSW_MAX_TX_QUEUES, 1951 AM65_CPSW_MAX_RX_QUEUES); 1952 if (!port->ndev) { 1953 dev_err(dev, "error allocating slave net_device %u\n", 1954 port->port_id); 1955 return -ENOMEM; 1956 } 1957 1958 ndev_priv = netdev_priv(port->ndev); 1959 ndev_priv->port = port; 1960 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 1961 SET_NETDEV_DEV(port->ndev, dev); 1962 1963 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 1964 1965 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 1966 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 1967 port->ndev->hw_features = NETIF_F_SG | 1968 NETIF_F_RXCSUM | 1969 NETIF_F_HW_CSUM | 1970 NETIF_F_HW_TC; 1971 port->ndev->features = port->ndev->hw_features | 1972 NETIF_F_HW_VLAN_CTAG_FILTER; 1973 port->ndev->vlan_features |= NETIF_F_SG; 1974 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 1975 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 1976 1977 /* Configuring Phylink */ 1978 port->slave.phylink_config.dev = &port->ndev->dev; 1979 port->slave.phylink_config.type = PHYLINK_NETDEV; 1980 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 1981 1982 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 1983 1984 phylink = phylink_create(&port->slave.phylink_config, dev->fwnode, port->slave.phy_if, 1985 &am65_cpsw_phylink_mac_ops); 1986 if (IS_ERR(phylink)) 1987 return PTR_ERR(phylink); 1988 1989 port->slave.phylink = phylink; 1990 1991 /* Disable TX checksum offload by default due to HW bug */ 1992 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 1993 port->ndev->features &= ~NETIF_F_HW_CSUM; 1994 1995 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 1996 if (!ndev_priv->stats) 1997 return -ENOMEM; 1998 1999 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2000 ndev_priv->stats); 2001 if (ret) 2002 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2003 2004 if (!common->dma_ndev) 2005 common->dma_ndev = port->ndev; 2006 2007 return ret; 2008 } 2009 2010 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2011 { 2012 int ret; 2013 int i; 2014 2015 for (i = 0; i < common->port_num; i++) { 2016 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2017 if (ret) 2018 return ret; 2019 } 2020 2021 netif_napi_add(common->dma_ndev, &common->napi_rx, 2022 am65_cpsw_nuss_rx_poll, NAPI_POLL_WEIGHT); 2023 2024 return ret; 2025 } 2026 2027 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 2028 { 2029 struct device *dev = common->dev; 2030 int i, ret = 0; 2031 2032 for (i = 0; i < common->tx_ch_num; i++) { 2033 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 2034 2035 netif_tx_napi_add(common->dma_ndev, &tx_chn->napi_tx, 2036 am65_cpsw_nuss_tx_poll, NAPI_POLL_WEIGHT); 2037 2038 ret = devm_request_irq(dev, tx_chn->irq, 2039 am65_cpsw_nuss_tx_irq, 2040 IRQF_TRIGGER_HIGH, 2041 tx_chn->tx_chn_name, tx_chn); 2042 if (ret) { 2043 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 2044 tx_chn->id, tx_chn->irq, ret); 2045 goto err; 2046 } 2047 } 2048 2049 err: 2050 return ret; 2051 } 2052 2053 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2054 { 2055 struct am65_cpsw_port *port; 2056 int i; 2057 2058 for (i = 0; i < common->port_num; i++) { 2059 port = &common->ports[i]; 2060 if (port->ndev) 2061 unregister_netdev(port->ndev); 2062 } 2063 } 2064 2065 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2066 { 2067 int set_val = 0; 2068 int i; 2069 2070 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2071 set_val = 1; 2072 2073 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2074 2075 for (i = 1; i <= common->port_num; i++) { 2076 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2077 struct am65_cpsw_ndev_priv *priv; 2078 2079 if (!port->ndev) 2080 continue; 2081 2082 priv = am65_ndev_to_priv(port->ndev); 2083 priv->offload_fwd_mark = set_val; 2084 } 2085 } 2086 2087 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2088 { 2089 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2090 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2091 2092 return !common->is_emac_mode; 2093 } 2094 2095 return false; 2096 } 2097 2098 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2099 struct net_device *br_ndev, 2100 struct netlink_ext_ack *extack) 2101 { 2102 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2103 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2104 int err; 2105 2106 if (!common->br_members) { 2107 common->hw_bridge_dev = br_ndev; 2108 } else { 2109 /* This is adding the port to a second bridge, this is 2110 * unsupported 2111 */ 2112 if (common->hw_bridge_dev != br_ndev) 2113 return -EOPNOTSUPP; 2114 } 2115 2116 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2117 false, extack); 2118 if (err) 2119 return err; 2120 2121 common->br_members |= BIT(priv->port->port_id); 2122 2123 am65_cpsw_port_offload_fwd_mark_update(common); 2124 2125 return NOTIFY_DONE; 2126 } 2127 2128 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2129 { 2130 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2131 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2132 2133 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2134 2135 common->br_members &= ~BIT(priv->port->port_id); 2136 2137 am65_cpsw_port_offload_fwd_mark_update(common); 2138 2139 if (!common->br_members) 2140 common->hw_bridge_dev = NULL; 2141 } 2142 2143 /* netdev notifier */ 2144 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2145 unsigned long event, void *ptr) 2146 { 2147 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2148 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2149 struct netdev_notifier_changeupper_info *info; 2150 int ret = NOTIFY_DONE; 2151 2152 if (!am65_cpsw_port_dev_check(ndev)) 2153 return NOTIFY_DONE; 2154 2155 switch (event) { 2156 case NETDEV_CHANGEUPPER: 2157 info = ptr; 2158 2159 if (netif_is_bridge_master(info->upper_dev)) { 2160 if (info->linking) 2161 ret = am65_cpsw_netdevice_port_link(ndev, 2162 info->upper_dev, 2163 extack); 2164 else 2165 am65_cpsw_netdevice_port_unlink(ndev); 2166 } 2167 break; 2168 default: 2169 return NOTIFY_DONE; 2170 } 2171 2172 return notifier_from_errno(ret); 2173 } 2174 2175 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2176 { 2177 int ret = 0; 2178 2179 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2180 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2181 return 0; 2182 2183 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2184 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2185 if (ret) { 2186 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2187 return ret; 2188 } 2189 2190 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2191 if (ret) 2192 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2193 2194 return ret; 2195 } 2196 2197 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2198 { 2199 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2200 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2201 return; 2202 2203 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2204 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2205 } 2206 2207 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2208 2209 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2210 { 2211 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2212 ALE_MCAST_BLOCK_LEARN_FWD); 2213 } 2214 2215 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2216 { 2217 struct am65_cpsw_host *host = am65_common_get_host(common); 2218 2219 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2220 2221 am65_cpsw_init_stp_ale_entry(common); 2222 2223 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2224 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2225 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2226 } 2227 2228 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2229 { 2230 struct am65_cpsw_host *host = am65_common_get_host(common); 2231 2232 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2233 2234 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2235 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2236 2237 /* learning make no sense in multi-mac mode */ 2238 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2239 } 2240 2241 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2242 struct devlink_param_gset_ctx *ctx) 2243 { 2244 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2245 struct am65_cpsw_common *common = dl_priv->common; 2246 2247 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2248 2249 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2250 return -EOPNOTSUPP; 2251 2252 ctx->val.vbool = !common->is_emac_mode; 2253 2254 return 0; 2255 } 2256 2257 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2258 { 2259 struct am65_cpsw_slave_data *slave = &port->slave; 2260 struct am65_cpsw_common *common = port->common; 2261 u32 port_mask; 2262 2263 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2264 2265 if (slave->mac_only) 2266 /* enable mac-only mode on port */ 2267 cpsw_ale_control_set(common->ale, port->port_id, 2268 ALE_PORT_MACONLY, 1); 2269 2270 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2271 2272 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2273 2274 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2275 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2276 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2277 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2278 } 2279 2280 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2281 { 2282 struct am65_cpsw_slave_data *slave = &port->slave; 2283 struct am65_cpsw_common *cpsw = port->common; 2284 u32 port_mask; 2285 2286 cpsw_ale_control_set(cpsw->ale, port->port_id, 2287 ALE_PORT_NOLEARN, 0); 2288 2289 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2290 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2291 slave->port_vlan); 2292 2293 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2294 2295 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2296 port_mask, ALE_VLAN, slave->port_vlan, 2297 ALE_MCAST_FWD_2); 2298 2299 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2300 2301 cpsw_ale_control_set(cpsw->ale, port->port_id, 2302 ALE_PORT_MACONLY, 0); 2303 } 2304 2305 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2306 struct devlink_param_gset_ctx *ctx) 2307 { 2308 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2309 struct am65_cpsw_common *cpsw = dl_priv->common; 2310 bool switch_en = ctx->val.vbool; 2311 bool if_running = false; 2312 int i; 2313 2314 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2315 2316 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2317 return -EOPNOTSUPP; 2318 2319 if (switch_en == !cpsw->is_emac_mode) 2320 return 0; 2321 2322 if (!switch_en && cpsw->br_members) { 2323 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2324 return -EINVAL; 2325 } 2326 2327 rtnl_lock(); 2328 2329 cpsw->is_emac_mode = !switch_en; 2330 2331 for (i = 0; i < cpsw->port_num; i++) { 2332 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2333 2334 if (!sl_ndev || !netif_running(sl_ndev)) 2335 continue; 2336 2337 if_running = true; 2338 } 2339 2340 if (!if_running) { 2341 /* all ndevs are down */ 2342 for (i = 0; i < cpsw->port_num; i++) { 2343 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2344 struct am65_cpsw_slave_data *slave; 2345 2346 if (!sl_ndev) 2347 continue; 2348 2349 slave = am65_ndev_to_slave(sl_ndev); 2350 if (switch_en) 2351 slave->port_vlan = cpsw->default_vlan; 2352 else 2353 slave->port_vlan = 0; 2354 } 2355 2356 goto exit; 2357 } 2358 2359 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2360 /* clean up ALE table */ 2361 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2362 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2363 2364 if (switch_en) { 2365 dev_info(cpsw->dev, "Enable switch mode\n"); 2366 2367 am65_cpsw_init_host_port_switch(cpsw); 2368 2369 for (i = 0; i < cpsw->port_num; i++) { 2370 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2371 struct am65_cpsw_slave_data *slave; 2372 struct am65_cpsw_port *port; 2373 2374 if (!sl_ndev) 2375 continue; 2376 2377 port = am65_ndev_to_port(sl_ndev); 2378 slave = am65_ndev_to_slave(sl_ndev); 2379 slave->port_vlan = cpsw->default_vlan; 2380 2381 if (netif_running(sl_ndev)) 2382 am65_cpsw_init_port_switch_ale(port); 2383 } 2384 2385 } else { 2386 dev_info(cpsw->dev, "Disable switch mode\n"); 2387 2388 am65_cpsw_init_host_port_emac(cpsw); 2389 2390 for (i = 0; i < cpsw->port_num; i++) { 2391 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2392 struct am65_cpsw_port *port; 2393 2394 if (!sl_ndev) 2395 continue; 2396 2397 port = am65_ndev_to_port(sl_ndev); 2398 port->slave.port_vlan = 0; 2399 if (netif_running(sl_ndev)) 2400 am65_cpsw_init_port_emac_ale(port); 2401 } 2402 } 2403 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2404 exit: 2405 rtnl_unlock(); 2406 2407 return 0; 2408 } 2409 2410 static const struct devlink_param am65_cpsw_devlink_params[] = { 2411 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2412 DEVLINK_PARAM_TYPE_BOOL, 2413 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2414 am65_cpsw_dl_switch_mode_get, 2415 am65_cpsw_dl_switch_mode_set, NULL), 2416 }; 2417 2418 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2419 { 2420 struct devlink_port_attrs attrs = {}; 2421 struct am65_cpsw_devlink *dl_priv; 2422 struct device *dev = common->dev; 2423 struct devlink_port *dl_port; 2424 struct am65_cpsw_port *port; 2425 int ret = 0; 2426 int i; 2427 2428 common->devlink = 2429 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2430 if (!common->devlink) 2431 return -ENOMEM; 2432 2433 dl_priv = devlink_priv(common->devlink); 2434 dl_priv->common = common; 2435 2436 /* Provide devlink hook to switch mode when multiple external ports 2437 * are present NUSS switchdev driver is enabled. 2438 */ 2439 if (!AM65_CPSW_IS_CPSW2G(common) && 2440 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2441 ret = devlink_params_register(common->devlink, 2442 am65_cpsw_devlink_params, 2443 ARRAY_SIZE(am65_cpsw_devlink_params)); 2444 if (ret) { 2445 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2446 goto dl_unreg; 2447 } 2448 } 2449 2450 for (i = 1; i <= common->port_num; i++) { 2451 port = am65_common_get_port(common, i); 2452 dl_port = &port->devlink_port; 2453 2454 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2455 attrs.phys.port_number = port->port_id; 2456 attrs.switch_id.id_len = sizeof(resource_size_t); 2457 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2458 devlink_port_attrs_set(dl_port, &attrs); 2459 2460 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2461 if (ret) { 2462 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2463 port->port_id, ret); 2464 goto dl_port_unreg; 2465 } 2466 devlink_port_type_eth_set(dl_port, port->ndev); 2467 } 2468 devlink_register(common->devlink); 2469 return ret; 2470 2471 dl_port_unreg: 2472 for (i = i - 1; i >= 1; i--) { 2473 port = am65_common_get_port(common, i); 2474 dl_port = &port->devlink_port; 2475 2476 devlink_port_unregister(dl_port); 2477 } 2478 dl_unreg: 2479 devlink_free(common->devlink); 2480 return ret; 2481 } 2482 2483 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2484 { 2485 struct devlink_port *dl_port; 2486 struct am65_cpsw_port *port; 2487 int i; 2488 2489 devlink_unregister(common->devlink); 2490 2491 for (i = 1; i <= common->port_num; i++) { 2492 port = am65_common_get_port(common, i); 2493 dl_port = &port->devlink_port; 2494 2495 devlink_port_unregister(dl_port); 2496 } 2497 2498 if (!AM65_CPSW_IS_CPSW2G(common) && 2499 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2500 devlink_params_unregister(common->devlink, 2501 am65_cpsw_devlink_params, 2502 ARRAY_SIZE(am65_cpsw_devlink_params)); 2503 2504 devlink_free(common->devlink); 2505 } 2506 2507 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2508 { 2509 struct device *dev = common->dev; 2510 struct am65_cpsw_port *port; 2511 int ret = 0, i; 2512 2513 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 2514 if (ret) 2515 return ret; 2516 2517 ret = devm_request_irq(dev, common->rx_chns.irq, 2518 am65_cpsw_nuss_rx_irq, 2519 IRQF_TRIGGER_HIGH, dev_name(dev), common); 2520 if (ret) { 2521 dev_err(dev, "failure requesting rx irq %u, %d\n", 2522 common->rx_chns.irq, ret); 2523 return ret; 2524 } 2525 2526 for (i = 0; i < common->port_num; i++) { 2527 port = &common->ports[i]; 2528 2529 if (!port->ndev) 2530 continue; 2531 2532 ret = register_netdev(port->ndev); 2533 if (ret) { 2534 dev_err(dev, "error registering slave net device%i %d\n", 2535 i, ret); 2536 goto err_cleanup_ndev; 2537 } 2538 } 2539 2540 ret = am65_cpsw_register_notifiers(common); 2541 if (ret) 2542 goto err_cleanup_ndev; 2543 2544 ret = am65_cpsw_nuss_register_devlink(common); 2545 if (ret) 2546 goto clean_unregister_notifiers; 2547 2548 /* can't auto unregister ndev using devm_add_action() due to 2549 * devres release sequence in DD core for DMA 2550 */ 2551 2552 return 0; 2553 clean_unregister_notifiers: 2554 am65_cpsw_unregister_notifiers(common); 2555 err_cleanup_ndev: 2556 am65_cpsw_nuss_cleanup_ndev(common); 2557 2558 return ret; 2559 } 2560 2561 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2562 { 2563 int ret; 2564 2565 common->tx_ch_num = num_tx; 2566 ret = am65_cpsw_nuss_init_tx_chns(common); 2567 if (ret) 2568 return ret; 2569 2570 return am65_cpsw_nuss_ndev_add_tx_napi(common); 2571 } 2572 2573 struct am65_cpsw_soc_pdata { 2574 u32 quirks_dis; 2575 }; 2576 2577 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2578 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2579 }; 2580 2581 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2582 { .family = "AM65X", 2583 .revision = "SR2.0", 2584 .data = &am65x_soc_sr2_0 2585 }, 2586 {/* sentinel */} 2587 }; 2588 2589 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2590 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2591 .ale_dev_id = "am65x-cpsw2g", 2592 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2593 }; 2594 2595 static const struct am65_cpsw_pdata j721e_pdata = { 2596 .quirks = 0, 2597 .ale_dev_id = "am65x-cpsw2g", 2598 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2599 }; 2600 2601 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2602 .quirks = 0, 2603 .ale_dev_id = "am64-cpswxg", 2604 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2605 }; 2606 2607 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2608 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2609 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2610 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2611 { /* sentinel */ }, 2612 }; 2613 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2614 2615 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2616 { 2617 const struct soc_device_attribute *soc; 2618 2619 soc = soc_device_match(am65_cpsw_socinfo); 2620 if (soc && soc->data) { 2621 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2622 2623 /* disable quirks */ 2624 common->pdata.quirks &= ~socdata->quirks_dis; 2625 } 2626 } 2627 2628 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2629 { 2630 struct cpsw_ale_params ale_params = { 0 }; 2631 const struct of_device_id *of_id; 2632 struct device *dev = &pdev->dev; 2633 struct am65_cpsw_common *common; 2634 struct device_node *node; 2635 struct resource *res; 2636 struct clk *clk; 2637 u64 id_temp; 2638 int ret, i; 2639 2640 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2641 if (!common) 2642 return -ENOMEM; 2643 common->dev = dev; 2644 2645 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2646 if (!of_id) 2647 return -EINVAL; 2648 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2649 2650 am65_cpsw_nuss_apply_socinfo(common); 2651 2652 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2653 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2654 if (IS_ERR(common->ss_base)) 2655 return PTR_ERR(common->ss_base); 2656 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2657 /* Use device's physical base address as switch id */ 2658 id_temp = cpu_to_be64(res->start); 2659 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2660 2661 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2662 if (!node) 2663 return -ENOENT; 2664 common->port_num = of_get_child_count(node); 2665 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2666 return -ENOENT; 2667 of_node_put(node); 2668 2669 common->rx_flow_id_base = -1; 2670 init_completion(&common->tdown_complete); 2671 common->tx_ch_num = 1; 2672 common->pf_p0_rx_ptype_rrobin = false; 2673 common->default_vlan = 1; 2674 2675 common->ports = devm_kcalloc(dev, common->port_num, 2676 sizeof(*common->ports), 2677 GFP_KERNEL); 2678 if (!common->ports) 2679 return -ENOMEM; 2680 2681 clk = devm_clk_get(dev, "fck"); 2682 if (IS_ERR(clk)) 2683 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2684 common->bus_freq = clk_get_rate(clk); 2685 2686 pm_runtime_enable(dev); 2687 ret = pm_runtime_resume_and_get(dev); 2688 if (ret < 0) { 2689 pm_runtime_disable(dev); 2690 return ret; 2691 } 2692 2693 node = of_get_child_by_name(dev->of_node, "mdio"); 2694 if (!node) { 2695 dev_warn(dev, "MDIO node not found\n"); 2696 } else if (of_device_is_available(node)) { 2697 struct platform_device *mdio_pdev; 2698 2699 mdio_pdev = of_platform_device_create(node, NULL, dev); 2700 if (!mdio_pdev) { 2701 ret = -ENODEV; 2702 goto err_pm_clear; 2703 } 2704 2705 common->mdio_dev = &mdio_pdev->dev; 2706 } 2707 of_node_put(node); 2708 2709 am65_cpsw_nuss_get_ver(common); 2710 2711 /* init tx channels */ 2712 ret = am65_cpsw_nuss_init_tx_chns(common); 2713 if (ret) 2714 goto err_of_clear; 2715 ret = am65_cpsw_nuss_init_rx_chns(common); 2716 if (ret) 2717 goto err_of_clear; 2718 2719 ret = am65_cpsw_nuss_init_host_p(common); 2720 if (ret) 2721 goto err_of_clear; 2722 2723 ret = am65_cpsw_nuss_init_slave_ports(common); 2724 if (ret) 2725 goto err_of_clear; 2726 2727 /* init common data */ 2728 ale_params.dev = dev; 2729 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2730 ale_params.ale_ports = common->port_num + 1; 2731 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2732 ale_params.dev_id = common->pdata.ale_dev_id; 2733 ale_params.bus_freq = common->bus_freq; 2734 2735 common->ale = cpsw_ale_create(&ale_params); 2736 if (IS_ERR(common->ale)) { 2737 dev_err(dev, "error initializing ale engine\n"); 2738 ret = PTR_ERR(common->ale); 2739 goto err_of_clear; 2740 } 2741 2742 ret = am65_cpsw_init_cpts(common); 2743 if (ret) 2744 goto err_of_clear; 2745 2746 /* init ports */ 2747 for (i = 0; i < common->port_num; i++) 2748 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2749 2750 dev_set_drvdata(dev, common); 2751 2752 common->is_emac_mode = true; 2753 2754 ret = am65_cpsw_nuss_init_ndevs(common); 2755 if (ret) 2756 goto err_free_phylink; 2757 2758 ret = am65_cpsw_nuss_register_ndevs(common); 2759 if (ret) 2760 goto err_free_phylink; 2761 2762 pm_runtime_put(dev); 2763 return 0; 2764 2765 err_free_phylink: 2766 am65_cpsw_nuss_phylink_cleanup(common); 2767 err_of_clear: 2768 of_platform_device_destroy(common->mdio_dev, NULL); 2769 err_pm_clear: 2770 pm_runtime_put_sync(dev); 2771 pm_runtime_disable(dev); 2772 return ret; 2773 } 2774 2775 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2776 { 2777 struct device *dev = &pdev->dev; 2778 struct am65_cpsw_common *common; 2779 int ret; 2780 2781 common = dev_get_drvdata(dev); 2782 2783 ret = pm_runtime_resume_and_get(&pdev->dev); 2784 if (ret < 0) 2785 return ret; 2786 2787 am65_cpsw_nuss_phylink_cleanup(common); 2788 am65_cpsw_unregister_devlink(common); 2789 am65_cpsw_unregister_notifiers(common); 2790 2791 /* must unregister ndevs here because DD release_driver routine calls 2792 * dma_deconfigure(dev) before devres_release_all(dev) 2793 */ 2794 am65_cpsw_nuss_cleanup_ndev(common); 2795 2796 of_platform_device_destroy(common->mdio_dev, NULL); 2797 2798 pm_runtime_put_sync(&pdev->dev); 2799 pm_runtime_disable(&pdev->dev); 2800 return 0; 2801 } 2802 2803 static struct platform_driver am65_cpsw_nuss_driver = { 2804 .driver = { 2805 .name = AM65_CPSW_DRV_NAME, 2806 .of_match_table = am65_cpsw_nuss_of_mtable, 2807 }, 2808 .probe = am65_cpsw_nuss_probe, 2809 .remove = am65_cpsw_nuss_remove, 2810 }; 2811 2812 module_platform_driver(am65_cpsw_nuss_driver); 2813 2814 MODULE_LICENSE("GPL v2"); 2815 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2816 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2817