1 // SPDX-License-Identifier: GPL-2.0 2 /* Texas Instruments K3 AM65 Ethernet Switch SubSystem Driver 3 * 4 * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/etherdevice.h> 10 #include <linux/if_vlan.h> 11 #include <linux/interrupt.h> 12 #include <linux/irqdomain.h> 13 #include <linux/kernel.h> 14 #include <linux/kmemleak.h> 15 #include <linux/module.h> 16 #include <linux/netdevice.h> 17 #include <linux/net_tstamp.h> 18 #include <linux/of.h> 19 #include <linux/of_mdio.h> 20 #include <linux/of_net.h> 21 #include <linux/of_device.h> 22 #include <linux/phylink.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/rtnetlink.h> 28 #include <linux/mfd/syscon.h> 29 #include <linux/sys_soc.h> 30 #include <linux/dma/ti-cppi5.h> 31 #include <linux/dma/k3-udma-glue.h> 32 #include <net/switchdev.h> 33 34 #include "cpsw_ale.h" 35 #include "cpsw_sl.h" 36 #include "am65-cpsw-nuss.h" 37 #include "am65-cpsw-switchdev.h" 38 #include "k3-cppi-desc-pool.h" 39 #include "am65-cpts.h" 40 41 #define AM65_CPSW_SS_BASE 0x0 42 #define AM65_CPSW_SGMII_BASE 0x100 43 #define AM65_CPSW_XGMII_BASE 0x2100 44 #define AM65_CPSW_CPSW_NU_BASE 0x20000 45 #define AM65_CPSW_NU_PORTS_BASE 0x1000 46 #define AM65_CPSW_NU_FRAM_BASE 0x12000 47 #define AM65_CPSW_NU_STATS_BASE 0x1a000 48 #define AM65_CPSW_NU_ALE_BASE 0x1e000 49 #define AM65_CPSW_NU_CPTS_BASE 0x1d000 50 51 #define AM65_CPSW_NU_PORTS_OFFSET 0x1000 52 #define AM65_CPSW_NU_STATS_PORT_OFFSET 0x200 53 #define AM65_CPSW_NU_FRAM_PORT_OFFSET 0x200 54 55 #define AM65_CPSW_MAX_PORTS 8 56 57 #define AM65_CPSW_MIN_PACKET_SIZE VLAN_ETH_ZLEN 58 #define AM65_CPSW_MAX_PACKET_SIZE (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 59 60 #define AM65_CPSW_REG_CTL 0x004 61 #define AM65_CPSW_REG_STAT_PORT_EN 0x014 62 #define AM65_CPSW_REG_PTYPE 0x018 63 64 #define AM65_CPSW_P0_REG_CTL 0x004 65 #define AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET 0x008 66 67 #define AM65_CPSW_PORT_REG_PRI_CTL 0x01c 68 #define AM65_CPSW_PORT_REG_RX_PRI_MAP 0x020 69 #define AM65_CPSW_PORT_REG_RX_MAXLEN 0x024 70 71 #define AM65_CPSW_PORTN_REG_SA_L 0x308 72 #define AM65_CPSW_PORTN_REG_SA_H 0x30c 73 #define AM65_CPSW_PORTN_REG_TS_CTL 0x310 74 #define AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG 0x314 75 #define AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG 0x318 76 #define AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 0x31C 77 78 #define AM65_CPSW_SGMII_CONTROL_REG 0x010 79 #define AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE BIT(0) 80 81 #define AM65_CPSW_CTL_VLAN_AWARE BIT(1) 82 #define AM65_CPSW_CTL_P0_ENABLE BIT(2) 83 #define AM65_CPSW_CTL_P0_TX_CRC_REMOVE BIT(13) 84 #define AM65_CPSW_CTL_P0_RX_PAD BIT(14) 85 86 /* AM65_CPSW_P0_REG_CTL */ 87 #define AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN BIT(0) 88 89 /* AM65_CPSW_PORT_REG_PRI_CTL */ 90 #define AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN BIT(8) 91 92 /* AM65_CPSW_PN_TS_CTL register fields */ 93 #define AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN BIT(4) 94 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN BIT(5) 95 #define AM65_CPSW_PN_TS_CTL_TX_VLAN_LT2_EN BIT(6) 96 #define AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN BIT(7) 97 #define AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN BIT(10) 98 #define AM65_CPSW_PN_TS_CTL_TX_HOST_TS_EN BIT(11) 99 #define AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT 16 100 101 /* AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG register fields */ 102 #define AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT 16 103 104 /* AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2 */ 105 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 BIT(16) 106 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 BIT(17) 107 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 BIT(18) 108 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 BIT(19) 109 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 BIT(20) 110 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 BIT(21) 111 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 BIT(22) 112 #define AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO BIT(23) 113 114 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */ 115 #define AM65_CPSW_TS_EVENT_MSG_TYPE_BITS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 116 117 #define AM65_CPSW_TS_SEQ_ID_OFFSET (0x1e) 118 119 #define AM65_CPSW_TS_TX_ANX_ALL_EN \ 120 (AM65_CPSW_PN_TS_CTL_TX_ANX_D_EN | \ 121 AM65_CPSW_PN_TS_CTL_TX_ANX_E_EN | \ 122 AM65_CPSW_PN_TS_CTL_TX_ANX_F_EN) 123 124 #define AM65_CPSW_ALE_AGEOUT_DEFAULT 30 125 /* Number of TX/RX descriptors */ 126 #define AM65_CPSW_MAX_TX_DESC 500 127 #define AM65_CPSW_MAX_RX_DESC 500 128 129 #define AM65_CPSW_NAV_PS_DATA_SIZE 16 130 #define AM65_CPSW_NAV_SW_DATA_SIZE 16 131 132 #define AM65_CPSW_DEBUG (NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK | \ 133 NETIF_MSG_IFUP | NETIF_MSG_PROBE | NETIF_MSG_IFDOWN | \ 134 NETIF_MSG_RX_ERR | NETIF_MSG_TX_ERR) 135 136 static void am65_cpsw_port_set_sl_mac(struct am65_cpsw_port *slave, 137 const u8 *dev_addr) 138 { 139 u32 mac_hi = (dev_addr[0] << 0) | (dev_addr[1] << 8) | 140 (dev_addr[2] << 16) | (dev_addr[3] << 24); 141 u32 mac_lo = (dev_addr[4] << 0) | (dev_addr[5] << 8); 142 143 writel(mac_hi, slave->port_base + AM65_CPSW_PORTN_REG_SA_H); 144 writel(mac_lo, slave->port_base + AM65_CPSW_PORTN_REG_SA_L); 145 } 146 147 static void am65_cpsw_sl_ctl_reset(struct am65_cpsw_port *port) 148 { 149 cpsw_sl_reset(port->slave.mac_sl, 100); 150 /* Max length register has to be restored after MAC SL reset */ 151 writel(AM65_CPSW_MAX_PACKET_SIZE, 152 port->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 153 } 154 155 static void am65_cpsw_nuss_get_ver(struct am65_cpsw_common *common) 156 { 157 common->nuss_ver = readl(common->ss_base); 158 common->cpsw_ver = readl(common->cpsw_base); 159 dev_info(common->dev, 160 "initializing am65 cpsw nuss version 0x%08X, cpsw version 0x%08X Ports: %u quirks:%08x\n", 161 common->nuss_ver, 162 common->cpsw_ver, 163 common->port_num + 1, 164 common->pdata.quirks); 165 } 166 167 static int am65_cpsw_nuss_ndo_slave_add_vid(struct net_device *ndev, 168 __be16 proto, u16 vid) 169 { 170 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 171 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 172 u32 port_mask, unreg_mcast = 0; 173 int ret; 174 175 if (!common->is_emac_mode) 176 return 0; 177 178 if (!netif_running(ndev) || !vid) 179 return 0; 180 181 ret = pm_runtime_resume_and_get(common->dev); 182 if (ret < 0) 183 return ret; 184 185 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 186 if (!vid) 187 unreg_mcast = port_mask; 188 dev_info(common->dev, "Adding vlan %d to vlan filter\n", vid); 189 ret = cpsw_ale_vlan_add_modify(common->ale, vid, port_mask, 190 unreg_mcast, port_mask, 0); 191 192 pm_runtime_put(common->dev); 193 return ret; 194 } 195 196 static int am65_cpsw_nuss_ndo_slave_kill_vid(struct net_device *ndev, 197 __be16 proto, u16 vid) 198 { 199 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 200 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 201 int ret; 202 203 if (!common->is_emac_mode) 204 return 0; 205 206 if (!netif_running(ndev) || !vid) 207 return 0; 208 209 ret = pm_runtime_resume_and_get(common->dev); 210 if (ret < 0) 211 return ret; 212 213 dev_info(common->dev, "Removing vlan %d from vlan filter\n", vid); 214 ret = cpsw_ale_del_vlan(common->ale, vid, 215 BIT(port->port_id) | ALE_PORT_HOST); 216 217 pm_runtime_put(common->dev); 218 return ret; 219 } 220 221 static void am65_cpsw_slave_set_promisc(struct am65_cpsw_port *port, 222 bool promisc) 223 { 224 struct am65_cpsw_common *common = port->common; 225 226 if (promisc && !common->is_emac_mode) { 227 dev_dbg(common->dev, "promisc mode requested in switch mode"); 228 return; 229 } 230 231 if (promisc) { 232 /* Enable promiscuous mode */ 233 cpsw_ale_control_set(common->ale, port->port_id, 234 ALE_PORT_MACONLY_CAF, 1); 235 dev_dbg(common->dev, "promisc enabled\n"); 236 } else { 237 /* Disable promiscuous mode */ 238 cpsw_ale_control_set(common->ale, port->port_id, 239 ALE_PORT_MACONLY_CAF, 0); 240 dev_dbg(common->dev, "promisc disabled\n"); 241 } 242 } 243 244 static void am65_cpsw_nuss_ndo_slave_set_rx_mode(struct net_device *ndev) 245 { 246 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 247 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 248 u32 port_mask; 249 bool promisc; 250 251 promisc = !!(ndev->flags & IFF_PROMISC); 252 am65_cpsw_slave_set_promisc(port, promisc); 253 254 if (promisc) 255 return; 256 257 /* Restore allmulti on vlans if necessary */ 258 cpsw_ale_set_allmulti(common->ale, 259 ndev->flags & IFF_ALLMULTI, port->port_id); 260 261 port_mask = ALE_PORT_HOST; 262 /* Clear all mcast from ALE */ 263 cpsw_ale_flush_multicast(common->ale, port_mask, -1); 264 265 if (!netdev_mc_empty(ndev)) { 266 struct netdev_hw_addr *ha; 267 268 /* program multicast address list into ALE register */ 269 netdev_for_each_mc_addr(ha, ndev) { 270 cpsw_ale_add_mcast(common->ale, ha->addr, 271 port_mask, 0, 0, 0); 272 } 273 } 274 } 275 276 static void am65_cpsw_nuss_ndo_host_tx_timeout(struct net_device *ndev, 277 unsigned int txqueue) 278 { 279 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 280 struct am65_cpsw_tx_chn *tx_chn; 281 struct netdev_queue *netif_txq; 282 unsigned long trans_start; 283 284 netif_txq = netdev_get_tx_queue(ndev, txqueue); 285 tx_chn = &common->tx_chns[txqueue]; 286 trans_start = READ_ONCE(netif_txq->trans_start); 287 288 netdev_err(ndev, "txq:%d DRV_XOFF:%d tmo:%u dql_avail:%d free_desc:%zu\n", 289 txqueue, 290 netif_tx_queue_stopped(netif_txq), 291 jiffies_to_msecs(jiffies - trans_start), 292 dql_avail(&netif_txq->dql), 293 k3_cppi_desc_pool_avail(tx_chn->desc_pool)); 294 295 if (netif_tx_queue_stopped(netif_txq)) { 296 /* try recover if stopped by us */ 297 txq_trans_update(netif_txq); 298 netif_tx_wake_queue(netif_txq); 299 } 300 } 301 302 static int am65_cpsw_nuss_rx_push(struct am65_cpsw_common *common, 303 struct sk_buff *skb) 304 { 305 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 306 struct cppi5_host_desc_t *desc_rx; 307 struct device *dev = common->dev; 308 u32 pkt_len = skb_tailroom(skb); 309 dma_addr_t desc_dma; 310 dma_addr_t buf_dma; 311 void *swdata; 312 313 desc_rx = k3_cppi_desc_pool_alloc(rx_chn->desc_pool); 314 if (!desc_rx) { 315 dev_err(dev, "Failed to allocate RXFDQ descriptor\n"); 316 return -ENOMEM; 317 } 318 desc_dma = k3_cppi_desc_pool_virt2dma(rx_chn->desc_pool, desc_rx); 319 320 buf_dma = dma_map_single(rx_chn->dma_dev, skb->data, pkt_len, 321 DMA_FROM_DEVICE); 322 if (unlikely(dma_mapping_error(rx_chn->dma_dev, buf_dma))) { 323 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 324 dev_err(dev, "Failed to map rx skb buffer\n"); 325 return -EINVAL; 326 } 327 328 cppi5_hdesc_init(desc_rx, CPPI5_INFO0_HDESC_EPIB_PRESENT, 329 AM65_CPSW_NAV_PS_DATA_SIZE); 330 k3_udma_glue_rx_dma_to_cppi5_addr(rx_chn->rx_chn, &buf_dma); 331 cppi5_hdesc_attach_buf(desc_rx, buf_dma, skb_tailroom(skb), buf_dma, skb_tailroom(skb)); 332 swdata = cppi5_hdesc_get_swdata(desc_rx); 333 *((void **)swdata) = skb; 334 335 return k3_udma_glue_push_rx_chn(rx_chn->rx_chn, 0, desc_rx, desc_dma); 336 } 337 338 void am65_cpsw_nuss_set_p0_ptype(struct am65_cpsw_common *common) 339 { 340 struct am65_cpsw_host *host_p = am65_common_get_host(common); 341 u32 val, pri_map; 342 343 /* P0 set Receive Priority Type */ 344 val = readl(host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 345 346 if (common->pf_p0_rx_ptype_rrobin) { 347 val |= AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 348 /* Enet Ports fifos works in fixed priority mode only, so 349 * reset P0_Rx_Pri_Map so all packet will go in Enet fifo 0 350 */ 351 pri_map = 0x0; 352 } else { 353 val &= ~AM65_CPSW_PORT_REG_PRI_CTL_RX_PTYPE_RROBIN; 354 /* restore P0_Rx_Pri_Map */ 355 pri_map = 0x76543210; 356 } 357 358 writel(pri_map, host_p->port_base + AM65_CPSW_PORT_REG_RX_PRI_MAP); 359 writel(val, host_p->port_base + AM65_CPSW_PORT_REG_PRI_CTL); 360 } 361 362 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common); 363 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common); 364 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port); 365 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port); 366 367 static int am65_cpsw_nuss_common_open(struct am65_cpsw_common *common) 368 { 369 struct am65_cpsw_host *host_p = am65_common_get_host(common); 370 int port_idx, i, ret; 371 struct sk_buff *skb; 372 u32 val, port_mask; 373 374 if (common->usage_count) 375 return 0; 376 377 /* Control register */ 378 writel(AM65_CPSW_CTL_P0_ENABLE | AM65_CPSW_CTL_P0_TX_CRC_REMOVE | 379 AM65_CPSW_CTL_VLAN_AWARE | AM65_CPSW_CTL_P0_RX_PAD, 380 common->cpsw_base + AM65_CPSW_REG_CTL); 381 /* Max length register */ 382 writel(AM65_CPSW_MAX_PACKET_SIZE, 383 host_p->port_base + AM65_CPSW_PORT_REG_RX_MAXLEN); 384 /* set base flow_id */ 385 writel(common->rx_flow_id_base, 386 host_p->port_base + AM65_CPSW_PORT0_REG_FLOW_ID_OFFSET); 387 /* en tx crc offload */ 388 writel(AM65_CPSW_P0_REG_CTL_RX_CHECKSUM_EN, host_p->port_base + AM65_CPSW_P0_REG_CTL); 389 390 am65_cpsw_nuss_set_p0_ptype(common); 391 392 /* enable statistic */ 393 val = BIT(HOST_PORT_NUM); 394 for (port_idx = 0; port_idx < common->port_num; port_idx++) { 395 struct am65_cpsw_port *port = &common->ports[port_idx]; 396 397 if (!port->disabled) 398 val |= BIT(port->port_id); 399 } 400 writel(val, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 401 402 /* disable priority elevation */ 403 writel(0, common->cpsw_base + AM65_CPSW_REG_PTYPE); 404 405 cpsw_ale_start(common->ale); 406 407 /* limit to one RX flow only */ 408 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 409 ALE_DEFAULT_THREAD_ID, 0); 410 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 411 ALE_DEFAULT_THREAD_ENABLE, 1); 412 /* switch to vlan unaware mode */ 413 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_VLAN_AWARE, 1); 414 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 415 ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 416 417 /* default vlan cfg: create mask based on enabled ports */ 418 port_mask = GENMASK(common->port_num, 0) & 419 ~common->disabled_ports_mask; 420 421 cpsw_ale_add_vlan(common->ale, 0, port_mask, 422 port_mask, port_mask, 423 port_mask & ~ALE_PORT_HOST); 424 425 if (common->is_emac_mode) 426 am65_cpsw_init_host_port_emac(common); 427 else 428 am65_cpsw_init_host_port_switch(common); 429 430 for (i = 0; i < common->rx_chns.descs_num; i++) { 431 skb = __netdev_alloc_skb_ip_align(NULL, 432 AM65_CPSW_MAX_PACKET_SIZE, 433 GFP_KERNEL); 434 if (!skb) { 435 dev_err(common->dev, "cannot allocate skb\n"); 436 return -ENOMEM; 437 } 438 439 ret = am65_cpsw_nuss_rx_push(common, skb); 440 if (ret < 0) { 441 dev_err(common->dev, 442 "cannot submit skb to channel rx, error %d\n", 443 ret); 444 kfree_skb(skb); 445 return ret; 446 } 447 kmemleak_not_leak(skb); 448 } 449 k3_udma_glue_enable_rx_chn(common->rx_chns.rx_chn); 450 451 for (i = 0; i < common->tx_ch_num; i++) { 452 ret = k3_udma_glue_enable_tx_chn(common->tx_chns[i].tx_chn); 453 if (ret) 454 return ret; 455 napi_enable(&common->tx_chns[i].napi_tx); 456 } 457 458 napi_enable(&common->napi_rx); 459 if (common->rx_irq_disabled) { 460 common->rx_irq_disabled = false; 461 enable_irq(common->rx_chns.irq); 462 } 463 464 dev_dbg(common->dev, "cpsw_nuss started\n"); 465 return 0; 466 } 467 468 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma); 469 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma); 470 471 static int am65_cpsw_nuss_common_stop(struct am65_cpsw_common *common) 472 { 473 int i; 474 475 if (common->usage_count != 1) 476 return 0; 477 478 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, 479 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 480 481 /* shutdown tx channels */ 482 atomic_set(&common->tdown_cnt, common->tx_ch_num); 483 /* ensure new tdown_cnt value is visible */ 484 smp_mb__after_atomic(); 485 reinit_completion(&common->tdown_complete); 486 487 for (i = 0; i < common->tx_ch_num; i++) 488 k3_udma_glue_tdown_tx_chn(common->tx_chns[i].tx_chn, false); 489 490 i = wait_for_completion_timeout(&common->tdown_complete, 491 msecs_to_jiffies(1000)); 492 if (!i) 493 dev_err(common->dev, "tx timeout\n"); 494 for (i = 0; i < common->tx_ch_num; i++) 495 napi_disable(&common->tx_chns[i].napi_tx); 496 497 for (i = 0; i < common->tx_ch_num; i++) { 498 k3_udma_glue_reset_tx_chn(common->tx_chns[i].tx_chn, 499 &common->tx_chns[i], 500 am65_cpsw_nuss_tx_cleanup); 501 k3_udma_glue_disable_tx_chn(common->tx_chns[i].tx_chn); 502 } 503 504 k3_udma_glue_tdown_rx_chn(common->rx_chns.rx_chn, true); 505 napi_disable(&common->napi_rx); 506 507 for (i = 0; i < AM65_CPSW_MAX_RX_FLOWS; i++) 508 k3_udma_glue_reset_rx_chn(common->rx_chns.rx_chn, i, 509 &common->rx_chns, 510 am65_cpsw_nuss_rx_cleanup, !!i); 511 512 k3_udma_glue_disable_rx_chn(common->rx_chns.rx_chn); 513 514 cpsw_ale_stop(common->ale); 515 516 writel(0, common->cpsw_base + AM65_CPSW_REG_CTL); 517 writel(0, common->cpsw_base + AM65_CPSW_REG_STAT_PORT_EN); 518 519 dev_dbg(common->dev, "cpsw_nuss stopped\n"); 520 return 0; 521 } 522 523 static int am65_cpsw_nuss_ndo_slave_stop(struct net_device *ndev) 524 { 525 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 526 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 527 int ret; 528 529 phylink_stop(port->slave.phylink); 530 531 netif_tx_stop_all_queues(ndev); 532 533 phylink_disconnect_phy(port->slave.phylink); 534 535 ret = am65_cpsw_nuss_common_stop(common); 536 if (ret) 537 return ret; 538 539 common->usage_count--; 540 pm_runtime_put(common->dev); 541 return 0; 542 } 543 544 static int cpsw_restore_vlans(struct net_device *vdev, int vid, void *arg) 545 { 546 struct am65_cpsw_port *port = arg; 547 548 if (!vdev) 549 return 0; 550 551 return am65_cpsw_nuss_ndo_slave_add_vid(port->ndev, 0, vid); 552 } 553 554 static int am65_cpsw_nuss_ndo_slave_open(struct net_device *ndev) 555 { 556 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 557 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 558 int ret, i; 559 u32 reg; 560 561 ret = pm_runtime_resume_and_get(common->dev); 562 if (ret < 0) 563 return ret; 564 565 /* Idle MAC port */ 566 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 567 cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 568 cpsw_sl_ctl_reset(port->slave.mac_sl); 569 570 /* soft reset MAC */ 571 cpsw_sl_reg_write(port->slave.mac_sl, CPSW_SL_SOFT_RESET, 1); 572 mdelay(1); 573 reg = cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_SOFT_RESET); 574 if (reg) { 575 dev_err(common->dev, "soft RESET didn't complete\n"); 576 return -ETIMEDOUT; 577 } 578 579 /* Notify the stack of the actual queue counts. */ 580 ret = netif_set_real_num_tx_queues(ndev, common->tx_ch_num); 581 if (ret) { 582 dev_err(common->dev, "cannot set real number of tx queues\n"); 583 return ret; 584 } 585 586 ret = netif_set_real_num_rx_queues(ndev, AM65_CPSW_MAX_RX_QUEUES); 587 if (ret) { 588 dev_err(common->dev, "cannot set real number of rx queues\n"); 589 return ret; 590 } 591 592 for (i = 0; i < common->tx_ch_num; i++) 593 netdev_tx_reset_queue(netdev_get_tx_queue(ndev, i)); 594 595 ret = am65_cpsw_nuss_common_open(common); 596 if (ret) 597 return ret; 598 599 common->usage_count++; 600 601 am65_cpsw_port_set_sl_mac(port, ndev->dev_addr); 602 603 if (common->is_emac_mode) 604 am65_cpsw_init_port_emac_ale(port); 605 else 606 am65_cpsw_init_port_switch_ale(port); 607 608 /* mac_sl should be configured via phy-link interface */ 609 am65_cpsw_sl_ctl_reset(port); 610 611 ret = phylink_of_phy_connect(port->slave.phylink, port->slave.phy_node, 0); 612 if (ret) 613 goto error_cleanup; 614 615 /* restore vlan configurations */ 616 vlan_for_each(ndev, cpsw_restore_vlans, port); 617 618 phylink_start(port->slave.phylink); 619 620 return 0; 621 622 error_cleanup: 623 am65_cpsw_nuss_ndo_slave_stop(ndev); 624 return ret; 625 } 626 627 static void am65_cpsw_nuss_rx_cleanup(void *data, dma_addr_t desc_dma) 628 { 629 struct am65_cpsw_rx_chn *rx_chn = data; 630 struct cppi5_host_desc_t *desc_rx; 631 struct sk_buff *skb; 632 dma_addr_t buf_dma; 633 u32 buf_dma_len; 634 void **swdata; 635 636 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 637 swdata = cppi5_hdesc_get_swdata(desc_rx); 638 skb = *swdata; 639 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 640 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 641 642 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 643 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 644 645 dev_kfree_skb_any(skb); 646 } 647 648 static void am65_cpsw_nuss_rx_ts(struct sk_buff *skb, u32 *psdata) 649 { 650 struct skb_shared_hwtstamps *ssh; 651 u64 ns; 652 653 ns = ((u64)psdata[1] << 32) | psdata[0]; 654 655 ssh = skb_hwtstamps(skb); 656 memset(ssh, 0, sizeof(*ssh)); 657 ssh->hwtstamp = ns_to_ktime(ns); 658 } 659 660 /* RX psdata[2] word format - checksum information */ 661 #define AM65_CPSW_RX_PSD_CSUM_ADD GENMASK(15, 0) 662 #define AM65_CPSW_RX_PSD_CSUM_ERR BIT(16) 663 #define AM65_CPSW_RX_PSD_IS_FRAGMENT BIT(17) 664 #define AM65_CPSW_RX_PSD_IS_TCP BIT(18) 665 #define AM65_CPSW_RX_PSD_IPV6_VALID BIT(19) 666 #define AM65_CPSW_RX_PSD_IPV4_VALID BIT(20) 667 668 static void am65_cpsw_nuss_rx_csum(struct sk_buff *skb, u32 csum_info) 669 { 670 /* HW can verify IPv4/IPv6 TCP/UDP packets checksum 671 * csum information provides in psdata[2] word: 672 * AM65_CPSW_RX_PSD_CSUM_ERR bit - indicates csum error 673 * AM65_CPSW_RX_PSD_IPV6_VALID and AM65_CPSW_RX_PSD_IPV4_VALID 674 * bits - indicates IPv4/IPv6 packet 675 * AM65_CPSW_RX_PSD_IS_FRAGMENT bit - indicates fragmented packet 676 * AM65_CPSW_RX_PSD_CSUM_ADD has value 0xFFFF for non fragmented packets 677 * or csum value for fragmented packets if !AM65_CPSW_RX_PSD_CSUM_ERR 678 */ 679 skb_checksum_none_assert(skb); 680 681 if (unlikely(!(skb->dev->features & NETIF_F_RXCSUM))) 682 return; 683 684 if ((csum_info & (AM65_CPSW_RX_PSD_IPV6_VALID | 685 AM65_CPSW_RX_PSD_IPV4_VALID)) && 686 !(csum_info & AM65_CPSW_RX_PSD_CSUM_ERR)) { 687 /* csum for fragmented packets is unsupported */ 688 if (!(csum_info & AM65_CPSW_RX_PSD_IS_FRAGMENT)) 689 skb->ip_summed = CHECKSUM_UNNECESSARY; 690 } 691 } 692 693 static int am65_cpsw_nuss_rx_packets(struct am65_cpsw_common *common, 694 u32 flow_idx) 695 { 696 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 697 u32 buf_dma_len, pkt_len, port_id = 0, csum_info; 698 struct am65_cpsw_ndev_priv *ndev_priv; 699 struct am65_cpsw_ndev_stats *stats; 700 struct cppi5_host_desc_t *desc_rx; 701 struct device *dev = common->dev; 702 struct sk_buff *skb, *new_skb; 703 dma_addr_t desc_dma, buf_dma; 704 struct am65_cpsw_port *port; 705 struct net_device *ndev; 706 void **swdata; 707 u32 *psdata; 708 int ret = 0; 709 710 ret = k3_udma_glue_pop_rx_chn(rx_chn->rx_chn, flow_idx, &desc_dma); 711 if (ret) { 712 if (ret != -ENODATA) 713 dev_err(dev, "RX: pop chn fail %d\n", ret); 714 return ret; 715 } 716 717 if (cppi5_desc_is_tdcm(desc_dma)) { 718 dev_dbg(dev, "%s RX tdown flow: %u\n", __func__, flow_idx); 719 return 0; 720 } 721 722 desc_rx = k3_cppi_desc_pool_dma2virt(rx_chn->desc_pool, desc_dma); 723 dev_dbg(dev, "%s flow_idx: %u desc %pad\n", 724 __func__, flow_idx, &desc_dma); 725 726 swdata = cppi5_hdesc_get_swdata(desc_rx); 727 skb = *swdata; 728 cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len); 729 k3_udma_glue_rx_cppi5_to_dma_addr(rx_chn->rx_chn, &buf_dma); 730 pkt_len = cppi5_hdesc_get_pktlen(desc_rx); 731 cppi5_desc_get_tags_ids(&desc_rx->hdr, &port_id, NULL); 732 dev_dbg(dev, "%s rx port_id:%d\n", __func__, port_id); 733 port = am65_common_get_port(common, port_id); 734 ndev = port->ndev; 735 skb->dev = ndev; 736 737 psdata = cppi5_hdesc_get_psdata(desc_rx); 738 /* add RX timestamp */ 739 if (port->rx_ts_enabled) 740 am65_cpsw_nuss_rx_ts(skb, psdata); 741 csum_info = psdata[2]; 742 dev_dbg(dev, "%s rx csum_info:%#x\n", __func__, csum_info); 743 744 dma_unmap_single(rx_chn->dma_dev, buf_dma, buf_dma_len, DMA_FROM_DEVICE); 745 746 k3_cppi_desc_pool_free(rx_chn->desc_pool, desc_rx); 747 748 new_skb = netdev_alloc_skb_ip_align(ndev, AM65_CPSW_MAX_PACKET_SIZE); 749 if (new_skb) { 750 ndev_priv = netdev_priv(ndev); 751 am65_cpsw_nuss_set_offload_fwd_mark(skb, ndev_priv->offload_fwd_mark); 752 skb_put(skb, pkt_len); 753 skb->protocol = eth_type_trans(skb, ndev); 754 am65_cpsw_nuss_rx_csum(skb, csum_info); 755 napi_gro_receive(&common->napi_rx, skb); 756 757 stats = this_cpu_ptr(ndev_priv->stats); 758 759 u64_stats_update_begin(&stats->syncp); 760 stats->rx_packets++; 761 stats->rx_bytes += pkt_len; 762 u64_stats_update_end(&stats->syncp); 763 kmemleak_not_leak(new_skb); 764 } else { 765 ndev->stats.rx_dropped++; 766 new_skb = skb; 767 } 768 769 if (netif_dormant(ndev)) { 770 dev_kfree_skb_any(new_skb); 771 ndev->stats.rx_dropped++; 772 return 0; 773 } 774 775 ret = am65_cpsw_nuss_rx_push(common, new_skb); 776 if (WARN_ON(ret < 0)) { 777 dev_kfree_skb_any(new_skb); 778 ndev->stats.rx_errors++; 779 ndev->stats.rx_dropped++; 780 } 781 782 return ret; 783 } 784 785 static int am65_cpsw_nuss_rx_poll(struct napi_struct *napi_rx, int budget) 786 { 787 struct am65_cpsw_common *common = am65_cpsw_napi_to_common(napi_rx); 788 int flow = AM65_CPSW_MAX_RX_FLOWS; 789 int cur_budget, ret; 790 int num_rx = 0; 791 792 /* process every flow */ 793 while (flow--) { 794 cur_budget = budget - num_rx; 795 796 while (cur_budget--) { 797 ret = am65_cpsw_nuss_rx_packets(common, flow); 798 if (ret) 799 break; 800 num_rx++; 801 } 802 803 if (num_rx >= budget) 804 break; 805 } 806 807 dev_dbg(common->dev, "%s num_rx:%d %d\n", __func__, num_rx, budget); 808 809 if (num_rx < budget && napi_complete_done(napi_rx, num_rx)) { 810 if (common->rx_irq_disabled) { 811 common->rx_irq_disabled = false; 812 enable_irq(common->rx_chns.irq); 813 } 814 } 815 816 return num_rx; 817 } 818 819 static void am65_cpsw_nuss_xmit_free(struct am65_cpsw_tx_chn *tx_chn, 820 struct cppi5_host_desc_t *desc) 821 { 822 struct cppi5_host_desc_t *first_desc, *next_desc; 823 dma_addr_t buf_dma, next_desc_dma; 824 u32 buf_dma_len; 825 826 first_desc = desc; 827 next_desc = first_desc; 828 829 cppi5_hdesc_get_obuf(first_desc, &buf_dma, &buf_dma_len); 830 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 831 832 dma_unmap_single(tx_chn->dma_dev, buf_dma, buf_dma_len, DMA_TO_DEVICE); 833 834 next_desc_dma = cppi5_hdesc_get_next_hbdesc(first_desc); 835 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 836 while (next_desc_dma) { 837 next_desc = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 838 next_desc_dma); 839 cppi5_hdesc_get_obuf(next_desc, &buf_dma, &buf_dma_len); 840 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &buf_dma); 841 842 dma_unmap_page(tx_chn->dma_dev, buf_dma, buf_dma_len, 843 DMA_TO_DEVICE); 844 845 next_desc_dma = cppi5_hdesc_get_next_hbdesc(next_desc); 846 k3_udma_glue_tx_cppi5_to_dma_addr(tx_chn->tx_chn, &next_desc_dma); 847 848 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 849 } 850 851 k3_cppi_desc_pool_free(tx_chn->desc_pool, first_desc); 852 } 853 854 static void am65_cpsw_nuss_tx_cleanup(void *data, dma_addr_t desc_dma) 855 { 856 struct am65_cpsw_tx_chn *tx_chn = data; 857 struct cppi5_host_desc_t *desc_tx; 858 struct sk_buff *skb; 859 void **swdata; 860 861 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, desc_dma); 862 swdata = cppi5_hdesc_get_swdata(desc_tx); 863 skb = *(swdata); 864 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 865 866 dev_kfree_skb_any(skb); 867 } 868 869 static struct sk_buff * 870 am65_cpsw_nuss_tx_compl_packet(struct am65_cpsw_tx_chn *tx_chn, 871 dma_addr_t desc_dma) 872 { 873 struct am65_cpsw_ndev_priv *ndev_priv; 874 struct am65_cpsw_ndev_stats *stats; 875 struct cppi5_host_desc_t *desc_tx; 876 struct net_device *ndev; 877 struct sk_buff *skb; 878 void **swdata; 879 880 desc_tx = k3_cppi_desc_pool_dma2virt(tx_chn->desc_pool, 881 desc_dma); 882 swdata = cppi5_hdesc_get_swdata(desc_tx); 883 skb = *(swdata); 884 am65_cpsw_nuss_xmit_free(tx_chn, desc_tx); 885 886 ndev = skb->dev; 887 888 am65_cpts_tx_timestamp(tx_chn->common->cpts, skb); 889 890 ndev_priv = netdev_priv(ndev); 891 stats = this_cpu_ptr(ndev_priv->stats); 892 u64_stats_update_begin(&stats->syncp); 893 stats->tx_packets++; 894 stats->tx_bytes += skb->len; 895 u64_stats_update_end(&stats->syncp); 896 897 return skb; 898 } 899 900 static void am65_cpsw_nuss_tx_wake(struct am65_cpsw_tx_chn *tx_chn, struct net_device *ndev, 901 struct netdev_queue *netif_txq) 902 { 903 if (netif_tx_queue_stopped(netif_txq)) { 904 /* Check whether the queue is stopped due to stalled 905 * tx dma, if the queue is stopped then wake the queue 906 * as we have free desc for tx 907 */ 908 __netif_tx_lock(netif_txq, smp_processor_id()); 909 if (netif_running(ndev) && 910 (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= MAX_SKB_FRAGS)) 911 netif_tx_wake_queue(netif_txq); 912 913 __netif_tx_unlock(netif_txq); 914 } 915 } 916 917 static int am65_cpsw_nuss_tx_compl_packets(struct am65_cpsw_common *common, 918 int chn, unsigned int budget) 919 { 920 struct device *dev = common->dev; 921 struct am65_cpsw_tx_chn *tx_chn; 922 struct netdev_queue *netif_txq; 923 unsigned int total_bytes = 0; 924 struct net_device *ndev; 925 struct sk_buff *skb; 926 dma_addr_t desc_dma; 927 int res, num_tx = 0; 928 929 tx_chn = &common->tx_chns[chn]; 930 931 while (true) { 932 spin_lock(&tx_chn->lock); 933 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 934 spin_unlock(&tx_chn->lock); 935 if (res == -ENODATA) 936 break; 937 938 if (cppi5_desc_is_tdcm(desc_dma)) { 939 if (atomic_dec_and_test(&common->tdown_cnt)) 940 complete(&common->tdown_complete); 941 break; 942 } 943 944 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 945 total_bytes = skb->len; 946 ndev = skb->dev; 947 napi_consume_skb(skb, budget); 948 num_tx++; 949 950 netif_txq = netdev_get_tx_queue(ndev, chn); 951 952 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 953 954 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 955 } 956 957 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 958 959 return num_tx; 960 } 961 962 static int am65_cpsw_nuss_tx_compl_packets_2g(struct am65_cpsw_common *common, 963 int chn, unsigned int budget) 964 { 965 struct device *dev = common->dev; 966 struct am65_cpsw_tx_chn *tx_chn; 967 struct netdev_queue *netif_txq; 968 unsigned int total_bytes = 0; 969 struct net_device *ndev; 970 struct sk_buff *skb; 971 dma_addr_t desc_dma; 972 int res, num_tx = 0; 973 974 tx_chn = &common->tx_chns[chn]; 975 976 while (true) { 977 res = k3_udma_glue_pop_tx_chn(tx_chn->tx_chn, &desc_dma); 978 if (res == -ENODATA) 979 break; 980 981 if (cppi5_desc_is_tdcm(desc_dma)) { 982 if (atomic_dec_and_test(&common->tdown_cnt)) 983 complete(&common->tdown_complete); 984 break; 985 } 986 987 skb = am65_cpsw_nuss_tx_compl_packet(tx_chn, desc_dma); 988 989 ndev = skb->dev; 990 total_bytes += skb->len; 991 napi_consume_skb(skb, budget); 992 num_tx++; 993 } 994 995 if (!num_tx) 996 return 0; 997 998 netif_txq = netdev_get_tx_queue(ndev, chn); 999 1000 netdev_tx_completed_queue(netif_txq, num_tx, total_bytes); 1001 1002 am65_cpsw_nuss_tx_wake(tx_chn, ndev, netif_txq); 1003 1004 dev_dbg(dev, "%s:%u pkt:%d\n", __func__, chn, num_tx); 1005 1006 return num_tx; 1007 } 1008 1009 static int am65_cpsw_nuss_tx_poll(struct napi_struct *napi_tx, int budget) 1010 { 1011 struct am65_cpsw_tx_chn *tx_chn = am65_cpsw_napi_to_tx_chn(napi_tx); 1012 int num_tx; 1013 1014 if (AM65_CPSW_IS_CPSW2G(tx_chn->common)) 1015 num_tx = am65_cpsw_nuss_tx_compl_packets_2g(tx_chn->common, tx_chn->id, budget); 1016 else 1017 num_tx = am65_cpsw_nuss_tx_compl_packets(tx_chn->common, tx_chn->id, budget); 1018 1019 if (num_tx >= budget) 1020 return budget; 1021 1022 if (napi_complete_done(napi_tx, num_tx)) 1023 enable_irq(tx_chn->irq); 1024 1025 return 0; 1026 } 1027 1028 static irqreturn_t am65_cpsw_nuss_rx_irq(int irq, void *dev_id) 1029 { 1030 struct am65_cpsw_common *common = dev_id; 1031 1032 common->rx_irq_disabled = true; 1033 disable_irq_nosync(irq); 1034 napi_schedule(&common->napi_rx); 1035 1036 return IRQ_HANDLED; 1037 } 1038 1039 static irqreturn_t am65_cpsw_nuss_tx_irq(int irq, void *dev_id) 1040 { 1041 struct am65_cpsw_tx_chn *tx_chn = dev_id; 1042 1043 disable_irq_nosync(irq); 1044 napi_schedule(&tx_chn->napi_tx); 1045 1046 return IRQ_HANDLED; 1047 } 1048 1049 static netdev_tx_t am65_cpsw_nuss_ndo_slave_xmit(struct sk_buff *skb, 1050 struct net_device *ndev) 1051 { 1052 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1053 struct cppi5_host_desc_t *first_desc, *next_desc, *cur_desc; 1054 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1055 struct device *dev = common->dev; 1056 struct am65_cpsw_tx_chn *tx_chn; 1057 struct netdev_queue *netif_txq; 1058 dma_addr_t desc_dma, buf_dma; 1059 int ret, q_idx, i; 1060 void **swdata; 1061 u32 *psdata; 1062 u32 pkt_len; 1063 1064 /* padding enabled in hw */ 1065 pkt_len = skb_headlen(skb); 1066 1067 /* SKB TX timestamp */ 1068 if (port->tx_ts_enabled) 1069 am65_cpts_prep_tx_timestamp(common->cpts, skb); 1070 1071 q_idx = skb_get_queue_mapping(skb); 1072 dev_dbg(dev, "%s skb_queue:%d\n", __func__, q_idx); 1073 1074 tx_chn = &common->tx_chns[q_idx]; 1075 netif_txq = netdev_get_tx_queue(ndev, q_idx); 1076 1077 /* Map the linear buffer */ 1078 buf_dma = dma_map_single(tx_chn->dma_dev, skb->data, pkt_len, 1079 DMA_TO_DEVICE); 1080 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1081 dev_err(dev, "Failed to map tx skb buffer\n"); 1082 ndev->stats.tx_errors++; 1083 goto err_free_skb; 1084 } 1085 1086 first_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1087 if (!first_desc) { 1088 dev_dbg(dev, "Failed to allocate descriptor\n"); 1089 dma_unmap_single(tx_chn->dma_dev, buf_dma, pkt_len, 1090 DMA_TO_DEVICE); 1091 goto busy_stop_q; 1092 } 1093 1094 cppi5_hdesc_init(first_desc, CPPI5_INFO0_HDESC_EPIB_PRESENT, 1095 AM65_CPSW_NAV_PS_DATA_SIZE); 1096 cppi5_desc_set_pktids(&first_desc->hdr, 0, 0x3FFF); 1097 cppi5_hdesc_set_pkttype(first_desc, 0x7); 1098 cppi5_desc_set_tags_ids(&first_desc->hdr, 0, port->port_id); 1099 1100 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1101 cppi5_hdesc_attach_buf(first_desc, buf_dma, pkt_len, buf_dma, pkt_len); 1102 swdata = cppi5_hdesc_get_swdata(first_desc); 1103 *(swdata) = skb; 1104 psdata = cppi5_hdesc_get_psdata(first_desc); 1105 1106 /* HW csum offload if enabled */ 1107 psdata[2] = 0; 1108 if (likely(skb->ip_summed == CHECKSUM_PARTIAL)) { 1109 unsigned int cs_start, cs_offset; 1110 1111 cs_start = skb_transport_offset(skb); 1112 cs_offset = cs_start + skb->csum_offset; 1113 /* HW numerates bytes starting from 1 */ 1114 psdata[2] = ((cs_offset + 1) << 24) | 1115 ((cs_start + 1) << 16) | (skb->len - cs_start); 1116 dev_dbg(dev, "%s tx psdata:%#x\n", __func__, psdata[2]); 1117 } 1118 1119 if (!skb_is_nonlinear(skb)) 1120 goto done_tx; 1121 1122 dev_dbg(dev, "fragmented SKB\n"); 1123 1124 /* Handle the case where skb is fragmented in pages */ 1125 cur_desc = first_desc; 1126 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 1127 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1128 u32 frag_size = skb_frag_size(frag); 1129 1130 next_desc = k3_cppi_desc_pool_alloc(tx_chn->desc_pool); 1131 if (!next_desc) { 1132 dev_err(dev, "Failed to allocate descriptor\n"); 1133 goto busy_free_descs; 1134 } 1135 1136 buf_dma = skb_frag_dma_map(tx_chn->dma_dev, frag, 0, frag_size, 1137 DMA_TO_DEVICE); 1138 if (unlikely(dma_mapping_error(tx_chn->dma_dev, buf_dma))) { 1139 dev_err(dev, "Failed to map tx skb page\n"); 1140 k3_cppi_desc_pool_free(tx_chn->desc_pool, next_desc); 1141 ndev->stats.tx_errors++; 1142 goto err_free_descs; 1143 } 1144 1145 cppi5_hdesc_reset_hbdesc(next_desc); 1146 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &buf_dma); 1147 cppi5_hdesc_attach_buf(next_desc, 1148 buf_dma, frag_size, buf_dma, frag_size); 1149 1150 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, 1151 next_desc); 1152 k3_udma_glue_tx_dma_to_cppi5_addr(tx_chn->tx_chn, &desc_dma); 1153 cppi5_hdesc_link_hbdesc(cur_desc, desc_dma); 1154 1155 pkt_len += frag_size; 1156 cur_desc = next_desc; 1157 } 1158 WARN_ON(pkt_len != skb->len); 1159 1160 done_tx: 1161 skb_tx_timestamp(skb); 1162 1163 /* report bql before sending packet */ 1164 netdev_tx_sent_queue(netif_txq, pkt_len); 1165 1166 cppi5_hdesc_set_pktlen(first_desc, pkt_len); 1167 desc_dma = k3_cppi_desc_pool_virt2dma(tx_chn->desc_pool, first_desc); 1168 if (AM65_CPSW_IS_CPSW2G(common)) { 1169 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1170 } else { 1171 spin_lock_bh(&tx_chn->lock); 1172 ret = k3_udma_glue_push_tx_chn(tx_chn->tx_chn, first_desc, desc_dma); 1173 spin_unlock_bh(&tx_chn->lock); 1174 } 1175 if (ret) { 1176 dev_err(dev, "can't push desc %d\n", ret); 1177 /* inform bql */ 1178 netdev_tx_completed_queue(netif_txq, 1, pkt_len); 1179 ndev->stats.tx_errors++; 1180 goto err_free_descs; 1181 } 1182 1183 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) < MAX_SKB_FRAGS) { 1184 netif_tx_stop_queue(netif_txq); 1185 /* Barrier, so that stop_queue visible to other cpus */ 1186 smp_mb__after_atomic(); 1187 dev_dbg(dev, "netif_tx_stop_queue %d\n", q_idx); 1188 1189 /* re-check for smp */ 1190 if (k3_cppi_desc_pool_avail(tx_chn->desc_pool) >= 1191 MAX_SKB_FRAGS) { 1192 netif_tx_wake_queue(netif_txq); 1193 dev_dbg(dev, "netif_tx_wake_queue %d\n", q_idx); 1194 } 1195 } 1196 1197 return NETDEV_TX_OK; 1198 1199 err_free_descs: 1200 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1201 err_free_skb: 1202 ndev->stats.tx_dropped++; 1203 dev_kfree_skb_any(skb); 1204 return NETDEV_TX_OK; 1205 1206 busy_free_descs: 1207 am65_cpsw_nuss_xmit_free(tx_chn, first_desc); 1208 busy_stop_q: 1209 netif_tx_stop_queue(netif_txq); 1210 return NETDEV_TX_BUSY; 1211 } 1212 1213 static int am65_cpsw_nuss_ndo_slave_set_mac_address(struct net_device *ndev, 1214 void *addr) 1215 { 1216 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1217 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1218 struct sockaddr *sockaddr = (struct sockaddr *)addr; 1219 int ret; 1220 1221 ret = eth_prepare_mac_addr_change(ndev, addr); 1222 if (ret < 0) 1223 return ret; 1224 1225 ret = pm_runtime_resume_and_get(common->dev); 1226 if (ret < 0) 1227 return ret; 1228 1229 cpsw_ale_del_ucast(common->ale, ndev->dev_addr, 1230 HOST_PORT_NUM, 0, 0); 1231 cpsw_ale_add_ucast(common->ale, sockaddr->sa_data, 1232 HOST_PORT_NUM, ALE_SECURE, 0); 1233 1234 am65_cpsw_port_set_sl_mac(port, addr); 1235 eth_commit_mac_addr_change(ndev, sockaddr); 1236 1237 pm_runtime_put(common->dev); 1238 1239 return 0; 1240 } 1241 1242 static int am65_cpsw_nuss_hwtstamp_set(struct net_device *ndev, 1243 struct ifreq *ifr) 1244 { 1245 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 1246 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1247 u32 ts_ctrl, seq_id, ts_ctrl_ltype2, ts_vlan_ltype; 1248 struct hwtstamp_config cfg; 1249 1250 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1251 return -EOPNOTSUPP; 1252 1253 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg))) 1254 return -EFAULT; 1255 1256 /* TX HW timestamp */ 1257 switch (cfg.tx_type) { 1258 case HWTSTAMP_TX_OFF: 1259 case HWTSTAMP_TX_ON: 1260 break; 1261 default: 1262 return -ERANGE; 1263 } 1264 1265 switch (cfg.rx_filter) { 1266 case HWTSTAMP_FILTER_NONE: 1267 port->rx_ts_enabled = false; 1268 break; 1269 case HWTSTAMP_FILTER_ALL: 1270 case HWTSTAMP_FILTER_SOME: 1271 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 1272 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 1273 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 1274 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 1275 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 1276 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 1277 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 1278 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 1279 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 1280 case HWTSTAMP_FILTER_PTP_V2_EVENT: 1281 case HWTSTAMP_FILTER_PTP_V2_SYNC: 1282 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 1283 case HWTSTAMP_FILTER_NTP_ALL: 1284 port->rx_ts_enabled = true; 1285 cfg.rx_filter = HWTSTAMP_FILTER_ALL; 1286 break; 1287 default: 1288 return -ERANGE; 1289 } 1290 1291 port->tx_ts_enabled = (cfg.tx_type == HWTSTAMP_TX_ON); 1292 1293 /* cfg TX timestamp */ 1294 seq_id = (AM65_CPSW_TS_SEQ_ID_OFFSET << 1295 AM65_CPSW_PN_TS_SEQ_ID_OFFSET_SHIFT) | ETH_P_1588; 1296 1297 ts_vlan_ltype = ETH_P_8021Q; 1298 1299 ts_ctrl_ltype2 = ETH_P_1588 | 1300 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_107 | 1301 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_129 | 1302 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_130 | 1303 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_131 | 1304 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_132 | 1305 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_319 | 1306 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_320 | 1307 AM65_CPSW_PN_TS_CTL_LTYPE2_TS_TTL_NONZERO; 1308 1309 ts_ctrl = AM65_CPSW_TS_EVENT_MSG_TYPE_BITS << 1310 AM65_CPSW_PN_TS_CTL_MSG_TYPE_EN_SHIFT; 1311 1312 if (port->tx_ts_enabled) 1313 ts_ctrl |= AM65_CPSW_TS_TX_ANX_ALL_EN | 1314 AM65_CPSW_PN_TS_CTL_TX_VLAN_LT1_EN; 1315 1316 writel(seq_id, port->port_base + AM65_CPSW_PORTN_REG_TS_SEQ_LTYPE_REG); 1317 writel(ts_vlan_ltype, port->port_base + 1318 AM65_CPSW_PORTN_REG_TS_VLAN_LTYPE_REG); 1319 writel(ts_ctrl_ltype2, port->port_base + 1320 AM65_CPSW_PORTN_REG_TS_CTL_LTYPE2); 1321 writel(ts_ctrl, port->port_base + AM65_CPSW_PORTN_REG_TS_CTL); 1322 1323 /* en/dis RX timestamp */ 1324 am65_cpts_rx_enable(common->cpts, port->rx_ts_enabled); 1325 1326 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1327 } 1328 1329 static int am65_cpsw_nuss_hwtstamp_get(struct net_device *ndev, 1330 struct ifreq *ifr) 1331 { 1332 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1333 struct hwtstamp_config cfg; 1334 1335 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1336 return -EOPNOTSUPP; 1337 1338 cfg.flags = 0; 1339 cfg.tx_type = port->tx_ts_enabled ? 1340 HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF; 1341 cfg.rx_filter = port->rx_ts_enabled ? 1342 HWTSTAMP_FILTER_ALL : HWTSTAMP_FILTER_NONE; 1343 1344 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0; 1345 } 1346 1347 static int am65_cpsw_nuss_ndo_slave_ioctl(struct net_device *ndev, 1348 struct ifreq *req, int cmd) 1349 { 1350 struct am65_cpsw_port *port = am65_ndev_to_port(ndev); 1351 1352 if (!netif_running(ndev)) 1353 return -EINVAL; 1354 1355 switch (cmd) { 1356 case SIOCSHWTSTAMP: 1357 return am65_cpsw_nuss_hwtstamp_set(ndev, req); 1358 case SIOCGHWTSTAMP: 1359 return am65_cpsw_nuss_hwtstamp_get(ndev, req); 1360 } 1361 1362 return phylink_mii_ioctl(port->slave.phylink, req, cmd); 1363 } 1364 1365 static void am65_cpsw_nuss_ndo_get_stats(struct net_device *dev, 1366 struct rtnl_link_stats64 *stats) 1367 { 1368 struct am65_cpsw_ndev_priv *ndev_priv = netdev_priv(dev); 1369 unsigned int start; 1370 int cpu; 1371 1372 for_each_possible_cpu(cpu) { 1373 struct am65_cpsw_ndev_stats *cpu_stats; 1374 u64 rx_packets; 1375 u64 rx_bytes; 1376 u64 tx_packets; 1377 u64 tx_bytes; 1378 1379 cpu_stats = per_cpu_ptr(ndev_priv->stats, cpu); 1380 do { 1381 start = u64_stats_fetch_begin(&cpu_stats->syncp); 1382 rx_packets = cpu_stats->rx_packets; 1383 rx_bytes = cpu_stats->rx_bytes; 1384 tx_packets = cpu_stats->tx_packets; 1385 tx_bytes = cpu_stats->tx_bytes; 1386 } while (u64_stats_fetch_retry(&cpu_stats->syncp, start)); 1387 1388 stats->rx_packets += rx_packets; 1389 stats->rx_bytes += rx_bytes; 1390 stats->tx_packets += tx_packets; 1391 stats->tx_bytes += tx_bytes; 1392 } 1393 1394 stats->rx_errors = dev->stats.rx_errors; 1395 stats->rx_dropped = dev->stats.rx_dropped; 1396 stats->tx_dropped = dev->stats.tx_dropped; 1397 } 1398 1399 static const struct net_device_ops am65_cpsw_nuss_netdev_ops = { 1400 .ndo_open = am65_cpsw_nuss_ndo_slave_open, 1401 .ndo_stop = am65_cpsw_nuss_ndo_slave_stop, 1402 .ndo_start_xmit = am65_cpsw_nuss_ndo_slave_xmit, 1403 .ndo_set_rx_mode = am65_cpsw_nuss_ndo_slave_set_rx_mode, 1404 .ndo_get_stats64 = am65_cpsw_nuss_ndo_get_stats, 1405 .ndo_validate_addr = eth_validate_addr, 1406 .ndo_set_mac_address = am65_cpsw_nuss_ndo_slave_set_mac_address, 1407 .ndo_tx_timeout = am65_cpsw_nuss_ndo_host_tx_timeout, 1408 .ndo_vlan_rx_add_vid = am65_cpsw_nuss_ndo_slave_add_vid, 1409 .ndo_vlan_rx_kill_vid = am65_cpsw_nuss_ndo_slave_kill_vid, 1410 .ndo_eth_ioctl = am65_cpsw_nuss_ndo_slave_ioctl, 1411 .ndo_setup_tc = am65_cpsw_qos_ndo_setup_tc, 1412 }; 1413 1414 static void am65_cpsw_nuss_mac_config(struct phylink_config *config, unsigned int mode, 1415 const struct phylink_link_state *state) 1416 { 1417 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1418 phylink_config); 1419 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1420 struct am65_cpsw_common *common = port->common; 1421 1422 if (common->pdata.extra_modes & BIT(state->interface)) 1423 writel(AM65_CPSW_SGMII_CONTROL_MR_AN_ENABLE, 1424 port->sgmii_base + AM65_CPSW_SGMII_CONTROL_REG); 1425 } 1426 1427 static void am65_cpsw_nuss_mac_link_down(struct phylink_config *config, unsigned int mode, 1428 phy_interface_t interface) 1429 { 1430 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1431 phylink_config); 1432 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1433 struct am65_cpsw_common *common = port->common; 1434 struct net_device *ndev = port->ndev; 1435 int tmo; 1436 1437 /* disable forwarding */ 1438 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1439 1440 cpsw_sl_ctl_set(port->slave.mac_sl, CPSW_SL_CTL_CMD_IDLE); 1441 1442 tmo = cpsw_sl_wait_for_idle(port->slave.mac_sl, 100); 1443 dev_dbg(common->dev, "down msc_sl %08x tmo %d\n", 1444 cpsw_sl_reg_read(port->slave.mac_sl, CPSW_SL_MACSTATUS), tmo); 1445 1446 cpsw_sl_ctl_reset(port->slave.mac_sl); 1447 1448 am65_cpsw_qos_link_down(ndev); 1449 netif_tx_stop_all_queues(ndev); 1450 } 1451 1452 static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy_device *phy, 1453 unsigned int mode, phy_interface_t interface, int speed, 1454 int duplex, bool tx_pause, bool rx_pause) 1455 { 1456 struct am65_cpsw_slave_data *slave = container_of(config, struct am65_cpsw_slave_data, 1457 phylink_config); 1458 struct am65_cpsw_port *port = container_of(slave, struct am65_cpsw_port, slave); 1459 struct am65_cpsw_common *common = port->common; 1460 u32 mac_control = CPSW_SL_CTL_GMII_EN; 1461 struct net_device *ndev = port->ndev; 1462 1463 if (speed == SPEED_1000) 1464 mac_control |= CPSW_SL_CTL_GIG; 1465 if (speed == SPEED_10 && phy_interface_mode_is_rgmii(interface)) 1466 /* Can be used with in band mode only */ 1467 mac_control |= CPSW_SL_CTL_EXT_EN; 1468 if (speed == SPEED_100 && interface == PHY_INTERFACE_MODE_RMII) 1469 mac_control |= CPSW_SL_CTL_IFCTL_A; 1470 if (duplex) 1471 mac_control |= CPSW_SL_CTL_FULLDUPLEX; 1472 1473 /* rx_pause/tx_pause */ 1474 if (rx_pause) 1475 mac_control |= CPSW_SL_CTL_RX_FLOW_EN; 1476 1477 if (tx_pause) 1478 mac_control |= CPSW_SL_CTL_TX_FLOW_EN; 1479 1480 cpsw_sl_ctl_set(port->slave.mac_sl, mac_control); 1481 1482 /* enable forwarding */ 1483 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_STATE, ALE_PORT_STATE_FORWARD); 1484 1485 am65_cpsw_qos_link_up(ndev, speed); 1486 netif_tx_wake_all_queues(ndev); 1487 } 1488 1489 static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = { 1490 .mac_config = am65_cpsw_nuss_mac_config, 1491 .mac_link_down = am65_cpsw_nuss_mac_link_down, 1492 .mac_link_up = am65_cpsw_nuss_mac_link_up, 1493 }; 1494 1495 static void am65_cpsw_nuss_slave_disable_unused(struct am65_cpsw_port *port) 1496 { 1497 struct am65_cpsw_common *common = port->common; 1498 1499 if (!port->disabled) 1500 return; 1501 1502 cpsw_ale_control_set(common->ale, port->port_id, 1503 ALE_PORT_STATE, ALE_PORT_STATE_DISABLE); 1504 1505 cpsw_sl_reset(port->slave.mac_sl, 100); 1506 cpsw_sl_ctl_reset(port->slave.mac_sl); 1507 } 1508 1509 static void am65_cpsw_nuss_free_tx_chns(void *data) 1510 { 1511 struct am65_cpsw_common *common = data; 1512 int i; 1513 1514 for (i = 0; i < common->tx_ch_num; i++) { 1515 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1516 1517 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1518 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1519 1520 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1521 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1522 1523 memset(tx_chn, 0, sizeof(*tx_chn)); 1524 } 1525 } 1526 1527 void am65_cpsw_nuss_remove_tx_chns(struct am65_cpsw_common *common) 1528 { 1529 struct device *dev = common->dev; 1530 int i; 1531 1532 devm_remove_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1533 1534 for (i = 0; i < common->tx_ch_num; i++) { 1535 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1536 1537 if (tx_chn->irq) 1538 devm_free_irq(dev, tx_chn->irq, tx_chn); 1539 1540 netif_napi_del(&tx_chn->napi_tx); 1541 1542 if (!IS_ERR_OR_NULL(tx_chn->desc_pool)) 1543 k3_cppi_desc_pool_destroy(tx_chn->desc_pool); 1544 1545 if (!IS_ERR_OR_NULL(tx_chn->tx_chn)) 1546 k3_udma_glue_release_tx_chn(tx_chn->tx_chn); 1547 1548 memset(tx_chn, 0, sizeof(*tx_chn)); 1549 } 1550 } 1551 1552 static int am65_cpsw_nuss_ndev_add_tx_napi(struct am65_cpsw_common *common) 1553 { 1554 struct device *dev = common->dev; 1555 int i, ret = 0; 1556 1557 for (i = 0; i < common->tx_ch_num; i++) { 1558 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1559 1560 netif_napi_add_tx(common->dma_ndev, &tx_chn->napi_tx, 1561 am65_cpsw_nuss_tx_poll); 1562 1563 ret = devm_request_irq(dev, tx_chn->irq, 1564 am65_cpsw_nuss_tx_irq, 1565 IRQF_TRIGGER_HIGH, 1566 tx_chn->tx_chn_name, tx_chn); 1567 if (ret) { 1568 dev_err(dev, "failure requesting tx%u irq %u, %d\n", 1569 tx_chn->id, tx_chn->irq, ret); 1570 goto err; 1571 } 1572 } 1573 1574 err: 1575 return ret; 1576 } 1577 1578 static int am65_cpsw_nuss_init_tx_chns(struct am65_cpsw_common *common) 1579 { 1580 u32 max_desc_num = ALIGN(AM65_CPSW_MAX_TX_DESC, MAX_SKB_FRAGS); 1581 struct k3_udma_glue_tx_channel_cfg tx_cfg = { 0 }; 1582 struct device *dev = common->dev; 1583 struct k3_ring_cfg ring_cfg = { 1584 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1585 .mode = K3_RINGACC_RING_MODE_RING, 1586 .flags = 0 1587 }; 1588 u32 hdesc_size; 1589 int i, ret = 0; 1590 1591 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1592 AM65_CPSW_NAV_SW_DATA_SIZE); 1593 1594 tx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1595 tx_cfg.tx_cfg = ring_cfg; 1596 tx_cfg.txcq_cfg = ring_cfg; 1597 tx_cfg.tx_cfg.size = max_desc_num; 1598 tx_cfg.txcq_cfg.size = max_desc_num; 1599 1600 for (i = 0; i < common->tx_ch_num; i++) { 1601 struct am65_cpsw_tx_chn *tx_chn = &common->tx_chns[i]; 1602 1603 snprintf(tx_chn->tx_chn_name, 1604 sizeof(tx_chn->tx_chn_name), "tx%d", i); 1605 1606 spin_lock_init(&tx_chn->lock); 1607 tx_chn->common = common; 1608 tx_chn->id = i; 1609 tx_chn->descs_num = max_desc_num; 1610 1611 tx_chn->tx_chn = 1612 k3_udma_glue_request_tx_chn(dev, 1613 tx_chn->tx_chn_name, 1614 &tx_cfg); 1615 if (IS_ERR(tx_chn->tx_chn)) { 1616 ret = dev_err_probe(dev, PTR_ERR(tx_chn->tx_chn), 1617 "Failed to request tx dma channel\n"); 1618 goto err; 1619 } 1620 tx_chn->dma_dev = k3_udma_glue_tx_get_dma_device(tx_chn->tx_chn); 1621 1622 tx_chn->desc_pool = k3_cppi_desc_pool_create_name(tx_chn->dma_dev, 1623 tx_chn->descs_num, 1624 hdesc_size, 1625 tx_chn->tx_chn_name); 1626 if (IS_ERR(tx_chn->desc_pool)) { 1627 ret = PTR_ERR(tx_chn->desc_pool); 1628 dev_err(dev, "Failed to create poll %d\n", ret); 1629 goto err; 1630 } 1631 1632 tx_chn->irq = k3_udma_glue_tx_get_irq(tx_chn->tx_chn); 1633 if (tx_chn->irq <= 0) { 1634 dev_err(dev, "Failed to get tx dma irq %d\n", 1635 tx_chn->irq); 1636 goto err; 1637 } 1638 1639 snprintf(tx_chn->tx_chn_name, 1640 sizeof(tx_chn->tx_chn_name), "%s-tx%d", 1641 dev_name(dev), tx_chn->id); 1642 } 1643 1644 ret = am65_cpsw_nuss_ndev_add_tx_napi(common); 1645 if (ret) { 1646 dev_err(dev, "Failed to add tx NAPI %d\n", ret); 1647 goto err; 1648 } 1649 1650 err: 1651 i = devm_add_action(dev, am65_cpsw_nuss_free_tx_chns, common); 1652 if (i) { 1653 dev_err(dev, "Failed to add free_tx_chns action %d\n", i); 1654 return i; 1655 } 1656 1657 return ret; 1658 } 1659 1660 static void am65_cpsw_nuss_free_rx_chns(void *data) 1661 { 1662 struct am65_cpsw_common *common = data; 1663 struct am65_cpsw_rx_chn *rx_chn; 1664 1665 rx_chn = &common->rx_chns; 1666 1667 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1668 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1669 1670 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1671 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1672 } 1673 1674 static void am65_cpsw_nuss_remove_rx_chns(void *data) 1675 { 1676 struct am65_cpsw_common *common = data; 1677 struct am65_cpsw_rx_chn *rx_chn; 1678 struct device *dev = common->dev; 1679 1680 rx_chn = &common->rx_chns; 1681 devm_remove_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1682 1683 if (!(rx_chn->irq < 0)) 1684 devm_free_irq(dev, rx_chn->irq, common); 1685 1686 netif_napi_del(&common->napi_rx); 1687 1688 if (!IS_ERR_OR_NULL(rx_chn->desc_pool)) 1689 k3_cppi_desc_pool_destroy(rx_chn->desc_pool); 1690 1691 if (!IS_ERR_OR_NULL(rx_chn->rx_chn)) 1692 k3_udma_glue_release_rx_chn(rx_chn->rx_chn); 1693 1694 common->rx_flow_id_base = -1; 1695 } 1696 1697 static int am65_cpsw_nuss_init_rx_chns(struct am65_cpsw_common *common) 1698 { 1699 struct am65_cpsw_rx_chn *rx_chn = &common->rx_chns; 1700 struct k3_udma_glue_rx_channel_cfg rx_cfg = { 0 }; 1701 u32 max_desc_num = AM65_CPSW_MAX_RX_DESC; 1702 struct device *dev = common->dev; 1703 u32 hdesc_size; 1704 u32 fdqring_id; 1705 int i, ret = 0; 1706 1707 hdesc_size = cppi5_hdesc_calc_size(true, AM65_CPSW_NAV_PS_DATA_SIZE, 1708 AM65_CPSW_NAV_SW_DATA_SIZE); 1709 1710 rx_cfg.swdata_size = AM65_CPSW_NAV_SW_DATA_SIZE; 1711 rx_cfg.flow_id_num = AM65_CPSW_MAX_RX_FLOWS; 1712 rx_cfg.flow_id_base = common->rx_flow_id_base; 1713 1714 /* init all flows */ 1715 rx_chn->dev = dev; 1716 rx_chn->descs_num = max_desc_num; 1717 1718 rx_chn->rx_chn = k3_udma_glue_request_rx_chn(dev, "rx", &rx_cfg); 1719 if (IS_ERR(rx_chn->rx_chn)) { 1720 ret = dev_err_probe(dev, PTR_ERR(rx_chn->rx_chn), 1721 "Failed to request rx dma channel\n"); 1722 goto err; 1723 } 1724 rx_chn->dma_dev = k3_udma_glue_rx_get_dma_device(rx_chn->rx_chn); 1725 1726 rx_chn->desc_pool = k3_cppi_desc_pool_create_name(rx_chn->dma_dev, 1727 rx_chn->descs_num, 1728 hdesc_size, "rx"); 1729 if (IS_ERR(rx_chn->desc_pool)) { 1730 ret = PTR_ERR(rx_chn->desc_pool); 1731 dev_err(dev, "Failed to create rx poll %d\n", ret); 1732 goto err; 1733 } 1734 1735 common->rx_flow_id_base = 1736 k3_udma_glue_rx_get_flow_id_base(rx_chn->rx_chn); 1737 dev_info(dev, "set new flow-id-base %u\n", common->rx_flow_id_base); 1738 1739 fdqring_id = K3_RINGACC_RING_ID_ANY; 1740 for (i = 0; i < rx_cfg.flow_id_num; i++) { 1741 struct k3_ring_cfg rxring_cfg = { 1742 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1743 .mode = K3_RINGACC_RING_MODE_RING, 1744 .flags = 0, 1745 }; 1746 struct k3_ring_cfg fdqring_cfg = { 1747 .elm_size = K3_RINGACC_RING_ELSIZE_8, 1748 .flags = K3_RINGACC_RING_SHARED, 1749 }; 1750 struct k3_udma_glue_rx_flow_cfg rx_flow_cfg = { 1751 .rx_cfg = rxring_cfg, 1752 .rxfdq_cfg = fdqring_cfg, 1753 .ring_rxq_id = K3_RINGACC_RING_ID_ANY, 1754 .src_tag_lo_sel = 1755 K3_UDMA_GLUE_SRC_TAG_LO_USE_REMOTE_SRC_TAG, 1756 }; 1757 1758 rx_flow_cfg.ring_rxfdq0_id = fdqring_id; 1759 rx_flow_cfg.rx_cfg.size = max_desc_num; 1760 rx_flow_cfg.rxfdq_cfg.size = max_desc_num; 1761 rx_flow_cfg.rxfdq_cfg.mode = common->pdata.fdqring_mode; 1762 1763 ret = k3_udma_glue_rx_flow_init(rx_chn->rx_chn, 1764 i, &rx_flow_cfg); 1765 if (ret) { 1766 dev_err(dev, "Failed to init rx flow%d %d\n", i, ret); 1767 goto err; 1768 } 1769 if (!i) 1770 fdqring_id = 1771 k3_udma_glue_rx_flow_get_fdq_id(rx_chn->rx_chn, 1772 i); 1773 1774 rx_chn->irq = k3_udma_glue_rx_get_irq(rx_chn->rx_chn, i); 1775 1776 if (rx_chn->irq <= 0) { 1777 dev_err(dev, "Failed to get rx dma irq %d\n", 1778 rx_chn->irq); 1779 ret = -ENXIO; 1780 goto err; 1781 } 1782 } 1783 1784 netif_napi_add(common->dma_ndev, &common->napi_rx, 1785 am65_cpsw_nuss_rx_poll); 1786 1787 ret = devm_request_irq(dev, rx_chn->irq, 1788 am65_cpsw_nuss_rx_irq, 1789 IRQF_TRIGGER_HIGH, dev_name(dev), common); 1790 if (ret) { 1791 dev_err(dev, "failure requesting rx irq %u, %d\n", 1792 rx_chn->irq, ret); 1793 goto err; 1794 } 1795 1796 err: 1797 i = devm_add_action(dev, am65_cpsw_nuss_free_rx_chns, common); 1798 if (i) { 1799 dev_err(dev, "Failed to add free_rx_chns action %d\n", i); 1800 return i; 1801 } 1802 1803 return ret; 1804 } 1805 1806 static int am65_cpsw_nuss_init_host_p(struct am65_cpsw_common *common) 1807 { 1808 struct am65_cpsw_host *host_p = am65_common_get_host(common); 1809 1810 host_p->common = common; 1811 host_p->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE; 1812 host_p->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE; 1813 1814 return 0; 1815 } 1816 1817 static int am65_cpsw_am654_get_efuse_macid(struct device_node *of_node, 1818 int slave, u8 *mac_addr) 1819 { 1820 u32 mac_lo, mac_hi, offset; 1821 struct regmap *syscon; 1822 int ret; 1823 1824 syscon = syscon_regmap_lookup_by_phandle(of_node, "ti,syscon-efuse"); 1825 if (IS_ERR(syscon)) { 1826 if (PTR_ERR(syscon) == -ENODEV) 1827 return 0; 1828 return PTR_ERR(syscon); 1829 } 1830 1831 ret = of_property_read_u32_index(of_node, "ti,syscon-efuse", 1, 1832 &offset); 1833 if (ret) 1834 return ret; 1835 1836 regmap_read(syscon, offset, &mac_lo); 1837 regmap_read(syscon, offset + 4, &mac_hi); 1838 1839 mac_addr[0] = (mac_hi >> 8) & 0xff; 1840 mac_addr[1] = mac_hi & 0xff; 1841 mac_addr[2] = (mac_lo >> 24) & 0xff; 1842 mac_addr[3] = (mac_lo >> 16) & 0xff; 1843 mac_addr[4] = (mac_lo >> 8) & 0xff; 1844 mac_addr[5] = mac_lo & 0xff; 1845 1846 return 0; 1847 } 1848 1849 static int am65_cpsw_init_cpts(struct am65_cpsw_common *common) 1850 { 1851 struct device *dev = common->dev; 1852 struct device_node *node; 1853 struct am65_cpts *cpts; 1854 void __iomem *reg_base; 1855 1856 if (!IS_ENABLED(CONFIG_TI_K3_AM65_CPTS)) 1857 return 0; 1858 1859 node = of_get_child_by_name(dev->of_node, "cpts"); 1860 if (!node) { 1861 dev_err(dev, "%s cpts not found\n", __func__); 1862 return -ENOENT; 1863 } 1864 1865 reg_base = common->cpsw_base + AM65_CPSW_NU_CPTS_BASE; 1866 cpts = am65_cpts_create(dev, reg_base, node); 1867 if (IS_ERR(cpts)) { 1868 int ret = PTR_ERR(cpts); 1869 1870 of_node_put(node); 1871 if (ret == -EOPNOTSUPP) { 1872 dev_info(dev, "cpts disabled\n"); 1873 return 0; 1874 } 1875 1876 dev_err(dev, "cpts create err %d\n", ret); 1877 return ret; 1878 } 1879 common->cpts = cpts; 1880 /* Forbid PM runtime if CPTS is running. 1881 * K3 CPSWxG modules may completely lose context during ON->OFF 1882 * transitions depending on integration. 1883 * AM65x/J721E MCU CPSW2G: false 1884 * J721E MAIN_CPSW9G: true 1885 */ 1886 pm_runtime_forbid(dev); 1887 1888 return 0; 1889 } 1890 1891 static int am65_cpsw_nuss_init_slave_ports(struct am65_cpsw_common *common) 1892 { 1893 struct device_node *node, *port_np; 1894 struct device *dev = common->dev; 1895 int ret; 1896 1897 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 1898 if (!node) 1899 return -ENOENT; 1900 1901 for_each_child_of_node(node, port_np) { 1902 struct am65_cpsw_port *port; 1903 u32 port_id; 1904 1905 /* it is not a slave port node, continue */ 1906 if (strcmp(port_np->name, "port")) 1907 continue; 1908 1909 ret = of_property_read_u32(port_np, "reg", &port_id); 1910 if (ret < 0) { 1911 dev_err(dev, "%pOF error reading port_id %d\n", 1912 port_np, ret); 1913 goto of_node_put; 1914 } 1915 1916 if (!port_id || port_id > common->port_num) { 1917 dev_err(dev, "%pOF has invalid port_id %u %s\n", 1918 port_np, port_id, port_np->name); 1919 ret = -EINVAL; 1920 goto of_node_put; 1921 } 1922 1923 port = am65_common_get_port(common, port_id); 1924 port->port_id = port_id; 1925 port->common = common; 1926 port->port_base = common->cpsw_base + AM65_CPSW_NU_PORTS_BASE + 1927 AM65_CPSW_NU_PORTS_OFFSET * (port_id); 1928 if (common->pdata.extra_modes) 1929 port->sgmii_base = common->ss_base + AM65_CPSW_SGMII_BASE * (port_id); 1930 port->stat_base = common->cpsw_base + AM65_CPSW_NU_STATS_BASE + 1931 (AM65_CPSW_NU_STATS_PORT_OFFSET * port_id); 1932 port->name = of_get_property(port_np, "label", NULL); 1933 port->fetch_ram_base = 1934 common->cpsw_base + AM65_CPSW_NU_FRAM_BASE + 1935 (AM65_CPSW_NU_FRAM_PORT_OFFSET * (port_id - 1)); 1936 1937 port->slave.mac_sl = cpsw_sl_get("am65", dev, port->port_base); 1938 if (IS_ERR(port->slave.mac_sl)) { 1939 ret = PTR_ERR(port->slave.mac_sl); 1940 goto of_node_put; 1941 } 1942 1943 port->disabled = !of_device_is_available(port_np); 1944 if (port->disabled) { 1945 common->disabled_ports_mask |= BIT(port->port_id); 1946 continue; 1947 } 1948 1949 port->slave.ifphy = devm_of_phy_get(dev, port_np, NULL); 1950 if (IS_ERR(port->slave.ifphy)) { 1951 ret = PTR_ERR(port->slave.ifphy); 1952 dev_err(dev, "%pOF error retrieving port phy: %d\n", 1953 port_np, ret); 1954 goto of_node_put; 1955 } 1956 1957 port->slave.mac_only = 1958 of_property_read_bool(port_np, "ti,mac-only"); 1959 1960 /* get phy/link info */ 1961 port->slave.phy_node = port_np; 1962 ret = of_get_phy_mode(port_np, &port->slave.phy_if); 1963 if (ret) { 1964 dev_err(dev, "%pOF read phy-mode err %d\n", 1965 port_np, ret); 1966 goto of_node_put; 1967 } 1968 1969 ret = phy_set_mode_ext(port->slave.ifphy, PHY_MODE_ETHERNET, port->slave.phy_if); 1970 if (ret) 1971 goto of_node_put; 1972 1973 ret = of_get_mac_address(port_np, port->slave.mac_addr); 1974 if (ret) { 1975 am65_cpsw_am654_get_efuse_macid(port_np, 1976 port->port_id, 1977 port->slave.mac_addr); 1978 if (!is_valid_ether_addr(port->slave.mac_addr)) { 1979 eth_random_addr(port->slave.mac_addr); 1980 dev_err(dev, "Use random MAC address\n"); 1981 } 1982 } 1983 } 1984 of_node_put(node); 1985 1986 /* is there at least one ext.port */ 1987 if (!(~common->disabled_ports_mask & GENMASK(common->port_num, 1))) { 1988 dev_err(dev, "No Ext. port are available\n"); 1989 return -ENODEV; 1990 } 1991 1992 return 0; 1993 1994 of_node_put: 1995 of_node_put(port_np); 1996 of_node_put(node); 1997 return ret; 1998 } 1999 2000 static void am65_cpsw_pcpu_stats_free(void *data) 2001 { 2002 struct am65_cpsw_ndev_stats __percpu *stats = data; 2003 2004 free_percpu(stats); 2005 } 2006 2007 static void am65_cpsw_nuss_phylink_cleanup(struct am65_cpsw_common *common) 2008 { 2009 struct am65_cpsw_port *port; 2010 int i; 2011 2012 for (i = 0; i < common->port_num; i++) { 2013 port = &common->ports[i]; 2014 if (port->slave.phylink) 2015 phylink_destroy(port->slave.phylink); 2016 } 2017 } 2018 2019 static int 2020 am65_cpsw_nuss_init_port_ndev(struct am65_cpsw_common *common, u32 port_idx) 2021 { 2022 struct am65_cpsw_ndev_priv *ndev_priv; 2023 struct device *dev = common->dev; 2024 struct am65_cpsw_port *port; 2025 struct phylink *phylink; 2026 int ret; 2027 2028 port = &common->ports[port_idx]; 2029 2030 if (port->disabled) 2031 return 0; 2032 2033 /* alloc netdev */ 2034 port->ndev = devm_alloc_etherdev_mqs(common->dev, 2035 sizeof(struct am65_cpsw_ndev_priv), 2036 AM65_CPSW_MAX_TX_QUEUES, 2037 AM65_CPSW_MAX_RX_QUEUES); 2038 if (!port->ndev) { 2039 dev_err(dev, "error allocating slave net_device %u\n", 2040 port->port_id); 2041 return -ENOMEM; 2042 } 2043 2044 ndev_priv = netdev_priv(port->ndev); 2045 ndev_priv->port = port; 2046 ndev_priv->msg_enable = AM65_CPSW_DEBUG; 2047 SET_NETDEV_DEV(port->ndev, dev); 2048 2049 eth_hw_addr_set(port->ndev, port->slave.mac_addr); 2050 2051 port->ndev->min_mtu = AM65_CPSW_MIN_PACKET_SIZE; 2052 port->ndev->max_mtu = AM65_CPSW_MAX_PACKET_SIZE; 2053 port->ndev->hw_features = NETIF_F_SG | 2054 NETIF_F_RXCSUM | 2055 NETIF_F_HW_CSUM | 2056 NETIF_F_HW_TC; 2057 port->ndev->features = port->ndev->hw_features | 2058 NETIF_F_HW_VLAN_CTAG_FILTER; 2059 port->ndev->vlan_features |= NETIF_F_SG; 2060 port->ndev->netdev_ops = &am65_cpsw_nuss_netdev_ops; 2061 port->ndev->ethtool_ops = &am65_cpsw_ethtool_ops_slave; 2062 2063 /* Configuring Phylink */ 2064 port->slave.phylink_config.dev = &port->ndev->dev; 2065 port->slave.phylink_config.type = PHYLINK_NETDEV; 2066 port->slave.phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | MAC_1000FD; 2067 port->slave.phylink_config.mac_managed_pm = true; /* MAC does PM */ 2068 2069 if (phy_interface_mode_is_rgmii(port->slave.phy_if)) { 2070 phy_interface_set_rgmii(port->slave.phylink_config.supported_interfaces); 2071 } else if (port->slave.phy_if == PHY_INTERFACE_MODE_RMII) { 2072 __set_bit(PHY_INTERFACE_MODE_RMII, 2073 port->slave.phylink_config.supported_interfaces); 2074 } else if (common->pdata.extra_modes & BIT(port->slave.phy_if)) { 2075 __set_bit(PHY_INTERFACE_MODE_QSGMII, 2076 port->slave.phylink_config.supported_interfaces); 2077 } else { 2078 dev_err(dev, "selected phy-mode is not supported\n"); 2079 return -EOPNOTSUPP; 2080 } 2081 2082 phylink = phylink_create(&port->slave.phylink_config, 2083 of_node_to_fwnode(port->slave.phy_node), 2084 port->slave.phy_if, 2085 &am65_cpsw_phylink_mac_ops); 2086 if (IS_ERR(phylink)) 2087 return PTR_ERR(phylink); 2088 2089 port->slave.phylink = phylink; 2090 2091 /* Disable TX checksum offload by default due to HW bug */ 2092 if (common->pdata.quirks & AM65_CPSW_QUIRK_I2027_NO_TX_CSUM) 2093 port->ndev->features &= ~NETIF_F_HW_CSUM; 2094 2095 ndev_priv->stats = netdev_alloc_pcpu_stats(struct am65_cpsw_ndev_stats); 2096 if (!ndev_priv->stats) 2097 return -ENOMEM; 2098 2099 ret = devm_add_action_or_reset(dev, am65_cpsw_pcpu_stats_free, 2100 ndev_priv->stats); 2101 if (ret) 2102 dev_err(dev, "failed to add percpu stat free action %d\n", ret); 2103 2104 if (!common->dma_ndev) 2105 common->dma_ndev = port->ndev; 2106 2107 return ret; 2108 } 2109 2110 static int am65_cpsw_nuss_init_ndevs(struct am65_cpsw_common *common) 2111 { 2112 int ret; 2113 int i; 2114 2115 for (i = 0; i < common->port_num; i++) { 2116 ret = am65_cpsw_nuss_init_port_ndev(common, i); 2117 if (ret) 2118 return ret; 2119 } 2120 2121 return ret; 2122 } 2123 2124 static void am65_cpsw_nuss_cleanup_ndev(struct am65_cpsw_common *common) 2125 { 2126 struct am65_cpsw_port *port; 2127 int i; 2128 2129 for (i = 0; i < common->port_num; i++) { 2130 port = &common->ports[i]; 2131 if (port->ndev && port->ndev->reg_state == NETREG_REGISTERED) 2132 unregister_netdev(port->ndev); 2133 } 2134 } 2135 2136 static void am65_cpsw_port_offload_fwd_mark_update(struct am65_cpsw_common *common) 2137 { 2138 int set_val = 0; 2139 int i; 2140 2141 if (common->br_members == (GENMASK(common->port_num, 1) & ~common->disabled_ports_mask)) 2142 set_val = 1; 2143 2144 dev_dbg(common->dev, "set offload_fwd_mark %d\n", set_val); 2145 2146 for (i = 1; i <= common->port_num; i++) { 2147 struct am65_cpsw_port *port = am65_common_get_port(common, i); 2148 struct am65_cpsw_ndev_priv *priv; 2149 2150 if (!port->ndev) 2151 continue; 2152 2153 priv = am65_ndev_to_priv(port->ndev); 2154 priv->offload_fwd_mark = set_val; 2155 } 2156 } 2157 2158 bool am65_cpsw_port_dev_check(const struct net_device *ndev) 2159 { 2160 if (ndev->netdev_ops == &am65_cpsw_nuss_netdev_ops) { 2161 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2162 2163 return !common->is_emac_mode; 2164 } 2165 2166 return false; 2167 } 2168 2169 static int am65_cpsw_netdevice_port_link(struct net_device *ndev, 2170 struct net_device *br_ndev, 2171 struct netlink_ext_ack *extack) 2172 { 2173 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2174 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2175 int err; 2176 2177 if (!common->br_members) { 2178 common->hw_bridge_dev = br_ndev; 2179 } else { 2180 /* This is adding the port to a second bridge, this is 2181 * unsupported 2182 */ 2183 if (common->hw_bridge_dev != br_ndev) 2184 return -EOPNOTSUPP; 2185 } 2186 2187 err = switchdev_bridge_port_offload(ndev, ndev, NULL, NULL, NULL, 2188 false, extack); 2189 if (err) 2190 return err; 2191 2192 common->br_members |= BIT(priv->port->port_id); 2193 2194 am65_cpsw_port_offload_fwd_mark_update(common); 2195 2196 return NOTIFY_DONE; 2197 } 2198 2199 static void am65_cpsw_netdevice_port_unlink(struct net_device *ndev) 2200 { 2201 struct am65_cpsw_common *common = am65_ndev_to_common(ndev); 2202 struct am65_cpsw_ndev_priv *priv = am65_ndev_to_priv(ndev); 2203 2204 switchdev_bridge_port_unoffload(ndev, NULL, NULL, NULL); 2205 2206 common->br_members &= ~BIT(priv->port->port_id); 2207 2208 am65_cpsw_port_offload_fwd_mark_update(common); 2209 2210 if (!common->br_members) 2211 common->hw_bridge_dev = NULL; 2212 } 2213 2214 /* netdev notifier */ 2215 static int am65_cpsw_netdevice_event(struct notifier_block *unused, 2216 unsigned long event, void *ptr) 2217 { 2218 struct netlink_ext_ack *extack = netdev_notifier_info_to_extack(ptr); 2219 struct net_device *ndev = netdev_notifier_info_to_dev(ptr); 2220 struct netdev_notifier_changeupper_info *info; 2221 int ret = NOTIFY_DONE; 2222 2223 if (!am65_cpsw_port_dev_check(ndev)) 2224 return NOTIFY_DONE; 2225 2226 switch (event) { 2227 case NETDEV_CHANGEUPPER: 2228 info = ptr; 2229 2230 if (netif_is_bridge_master(info->upper_dev)) { 2231 if (info->linking) 2232 ret = am65_cpsw_netdevice_port_link(ndev, 2233 info->upper_dev, 2234 extack); 2235 else 2236 am65_cpsw_netdevice_port_unlink(ndev); 2237 } 2238 break; 2239 default: 2240 return NOTIFY_DONE; 2241 } 2242 2243 return notifier_from_errno(ret); 2244 } 2245 2246 static int am65_cpsw_register_notifiers(struct am65_cpsw_common *cpsw) 2247 { 2248 int ret = 0; 2249 2250 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2251 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2252 return 0; 2253 2254 cpsw->am65_cpsw_netdevice_nb.notifier_call = &am65_cpsw_netdevice_event; 2255 ret = register_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2256 if (ret) { 2257 dev_err(cpsw->dev, "can't register netdevice notifier\n"); 2258 return ret; 2259 } 2260 2261 ret = am65_cpsw_switchdev_register_notifiers(cpsw); 2262 if (ret) 2263 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2264 2265 return ret; 2266 } 2267 2268 static void am65_cpsw_unregister_notifiers(struct am65_cpsw_common *cpsw) 2269 { 2270 if (AM65_CPSW_IS_CPSW2G(cpsw) || 2271 !IS_REACHABLE(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2272 return; 2273 2274 am65_cpsw_switchdev_unregister_notifiers(cpsw); 2275 unregister_netdevice_notifier(&cpsw->am65_cpsw_netdevice_nb); 2276 } 2277 2278 static const struct devlink_ops am65_cpsw_devlink_ops = {}; 2279 2280 static void am65_cpsw_init_stp_ale_entry(struct am65_cpsw_common *cpsw) 2281 { 2282 cpsw_ale_add_mcast(cpsw->ale, eth_stp_addr, ALE_PORT_HOST, ALE_SUPER, 0, 2283 ALE_MCAST_BLOCK_LEARN_FWD); 2284 } 2285 2286 static void am65_cpsw_init_host_port_switch(struct am65_cpsw_common *common) 2287 { 2288 struct am65_cpsw_host *host = am65_common_get_host(common); 2289 2290 writel(common->default_vlan, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2291 2292 am65_cpsw_init_stp_ale_entry(common); 2293 2294 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 1); 2295 dev_dbg(common->dev, "Set P0_UNI_FLOOD\n"); 2296 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 0); 2297 } 2298 2299 static void am65_cpsw_init_host_port_emac(struct am65_cpsw_common *common) 2300 { 2301 struct am65_cpsw_host *host = am65_common_get_host(common); 2302 2303 writel(0, host->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2304 2305 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_P0_UNI_FLOOD, 0); 2306 dev_dbg(common->dev, "unset P0_UNI_FLOOD\n"); 2307 2308 /* learning make no sense in multi-mac mode */ 2309 cpsw_ale_control_set(common->ale, HOST_PORT_NUM, ALE_PORT_NOLEARN, 1); 2310 } 2311 2312 static int am65_cpsw_dl_switch_mode_get(struct devlink *dl, u32 id, 2313 struct devlink_param_gset_ctx *ctx) 2314 { 2315 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2316 struct am65_cpsw_common *common = dl_priv->common; 2317 2318 dev_dbg(common->dev, "%s id:%u\n", __func__, id); 2319 2320 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2321 return -EOPNOTSUPP; 2322 2323 ctx->val.vbool = !common->is_emac_mode; 2324 2325 return 0; 2326 } 2327 2328 static void am65_cpsw_init_port_emac_ale(struct am65_cpsw_port *port) 2329 { 2330 struct am65_cpsw_slave_data *slave = &port->slave; 2331 struct am65_cpsw_common *common = port->common; 2332 u32 port_mask; 2333 2334 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2335 2336 if (slave->mac_only) 2337 /* enable mac-only mode on port */ 2338 cpsw_ale_control_set(common->ale, port->port_id, 2339 ALE_PORT_MACONLY, 1); 2340 2341 cpsw_ale_control_set(common->ale, port->port_id, ALE_PORT_NOLEARN, 1); 2342 2343 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2344 2345 cpsw_ale_add_ucast(common->ale, port->ndev->dev_addr, 2346 HOST_PORT_NUM, ALE_SECURE, slave->port_vlan); 2347 cpsw_ale_add_mcast(common->ale, port->ndev->broadcast, 2348 port_mask, ALE_VLAN, slave->port_vlan, ALE_MCAST_FWD_2); 2349 } 2350 2351 static void am65_cpsw_init_port_switch_ale(struct am65_cpsw_port *port) 2352 { 2353 struct am65_cpsw_slave_data *slave = &port->slave; 2354 struct am65_cpsw_common *cpsw = port->common; 2355 u32 port_mask; 2356 2357 cpsw_ale_control_set(cpsw->ale, port->port_id, 2358 ALE_PORT_NOLEARN, 0); 2359 2360 cpsw_ale_add_ucast(cpsw->ale, port->ndev->dev_addr, 2361 HOST_PORT_NUM, ALE_SECURE | ALE_BLOCKED | ALE_VLAN, 2362 slave->port_vlan); 2363 2364 port_mask = BIT(port->port_id) | ALE_PORT_HOST; 2365 2366 cpsw_ale_add_mcast(cpsw->ale, port->ndev->broadcast, 2367 port_mask, ALE_VLAN, slave->port_vlan, 2368 ALE_MCAST_FWD_2); 2369 2370 writel(slave->port_vlan, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2371 2372 cpsw_ale_control_set(cpsw->ale, port->port_id, 2373 ALE_PORT_MACONLY, 0); 2374 } 2375 2376 static int am65_cpsw_dl_switch_mode_set(struct devlink *dl, u32 id, 2377 struct devlink_param_gset_ctx *ctx) 2378 { 2379 struct am65_cpsw_devlink *dl_priv = devlink_priv(dl); 2380 struct am65_cpsw_common *cpsw = dl_priv->common; 2381 bool switch_en = ctx->val.vbool; 2382 bool if_running = false; 2383 int i; 2384 2385 dev_dbg(cpsw->dev, "%s id:%u\n", __func__, id); 2386 2387 if (id != AM65_CPSW_DL_PARAM_SWITCH_MODE) 2388 return -EOPNOTSUPP; 2389 2390 if (switch_en == !cpsw->is_emac_mode) 2391 return 0; 2392 2393 if (!switch_en && cpsw->br_members) { 2394 dev_err(cpsw->dev, "Remove ports from bridge before disabling switch mode\n"); 2395 return -EINVAL; 2396 } 2397 2398 rtnl_lock(); 2399 2400 cpsw->is_emac_mode = !switch_en; 2401 2402 for (i = 0; i < cpsw->port_num; i++) { 2403 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2404 2405 if (!sl_ndev || !netif_running(sl_ndev)) 2406 continue; 2407 2408 if_running = true; 2409 } 2410 2411 if (!if_running) { 2412 /* all ndevs are down */ 2413 for (i = 0; i < cpsw->port_num; i++) { 2414 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2415 struct am65_cpsw_slave_data *slave; 2416 2417 if (!sl_ndev) 2418 continue; 2419 2420 slave = am65_ndev_to_slave(sl_ndev); 2421 if (switch_en) 2422 slave->port_vlan = cpsw->default_vlan; 2423 else 2424 slave->port_vlan = 0; 2425 } 2426 2427 goto exit; 2428 } 2429 2430 cpsw_ale_control_set(cpsw->ale, 0, ALE_BYPASS, 1); 2431 /* clean up ALE table */ 2432 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_CLEAR, 1); 2433 cpsw_ale_control_get(cpsw->ale, HOST_PORT_NUM, ALE_AGEOUT); 2434 2435 if (switch_en) { 2436 dev_info(cpsw->dev, "Enable switch mode\n"); 2437 2438 am65_cpsw_init_host_port_switch(cpsw); 2439 2440 for (i = 0; i < cpsw->port_num; i++) { 2441 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2442 struct am65_cpsw_slave_data *slave; 2443 struct am65_cpsw_port *port; 2444 2445 if (!sl_ndev) 2446 continue; 2447 2448 port = am65_ndev_to_port(sl_ndev); 2449 slave = am65_ndev_to_slave(sl_ndev); 2450 slave->port_vlan = cpsw->default_vlan; 2451 2452 if (netif_running(sl_ndev)) 2453 am65_cpsw_init_port_switch_ale(port); 2454 } 2455 2456 } else { 2457 dev_info(cpsw->dev, "Disable switch mode\n"); 2458 2459 am65_cpsw_init_host_port_emac(cpsw); 2460 2461 for (i = 0; i < cpsw->port_num; i++) { 2462 struct net_device *sl_ndev = cpsw->ports[i].ndev; 2463 struct am65_cpsw_port *port; 2464 2465 if (!sl_ndev) 2466 continue; 2467 2468 port = am65_ndev_to_port(sl_ndev); 2469 port->slave.port_vlan = 0; 2470 if (netif_running(sl_ndev)) 2471 am65_cpsw_init_port_emac_ale(port); 2472 } 2473 } 2474 cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_BYPASS, 0); 2475 exit: 2476 rtnl_unlock(); 2477 2478 return 0; 2479 } 2480 2481 static const struct devlink_param am65_cpsw_devlink_params[] = { 2482 DEVLINK_PARAM_DRIVER(AM65_CPSW_DL_PARAM_SWITCH_MODE, "switch_mode", 2483 DEVLINK_PARAM_TYPE_BOOL, 2484 BIT(DEVLINK_PARAM_CMODE_RUNTIME), 2485 am65_cpsw_dl_switch_mode_get, 2486 am65_cpsw_dl_switch_mode_set, NULL), 2487 }; 2488 2489 static int am65_cpsw_nuss_register_devlink(struct am65_cpsw_common *common) 2490 { 2491 struct devlink_port_attrs attrs = {}; 2492 struct am65_cpsw_devlink *dl_priv; 2493 struct device *dev = common->dev; 2494 struct devlink_port *dl_port; 2495 struct am65_cpsw_port *port; 2496 int ret = 0; 2497 int i; 2498 2499 common->devlink = 2500 devlink_alloc(&am65_cpsw_devlink_ops, sizeof(*dl_priv), dev); 2501 if (!common->devlink) 2502 return -ENOMEM; 2503 2504 dl_priv = devlink_priv(common->devlink); 2505 dl_priv->common = common; 2506 2507 /* Provide devlink hook to switch mode when multiple external ports 2508 * are present NUSS switchdev driver is enabled. 2509 */ 2510 if (!AM65_CPSW_IS_CPSW2G(common) && 2511 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) { 2512 ret = devlink_params_register(common->devlink, 2513 am65_cpsw_devlink_params, 2514 ARRAY_SIZE(am65_cpsw_devlink_params)); 2515 if (ret) { 2516 dev_err(dev, "devlink params reg fail ret:%d\n", ret); 2517 goto dl_unreg; 2518 } 2519 } 2520 2521 for (i = 1; i <= common->port_num; i++) { 2522 port = am65_common_get_port(common, i); 2523 dl_port = &port->devlink_port; 2524 2525 if (port->ndev) 2526 attrs.flavour = DEVLINK_PORT_FLAVOUR_PHYSICAL; 2527 else 2528 attrs.flavour = DEVLINK_PORT_FLAVOUR_UNUSED; 2529 attrs.phys.port_number = port->port_id; 2530 attrs.switch_id.id_len = sizeof(resource_size_t); 2531 memcpy(attrs.switch_id.id, common->switch_id, attrs.switch_id.id_len); 2532 devlink_port_attrs_set(dl_port, &attrs); 2533 2534 ret = devlink_port_register(common->devlink, dl_port, port->port_id); 2535 if (ret) { 2536 dev_err(dev, "devlink_port reg fail for port %d, ret:%d\n", 2537 port->port_id, ret); 2538 goto dl_port_unreg; 2539 } 2540 } 2541 devlink_register(common->devlink); 2542 return ret; 2543 2544 dl_port_unreg: 2545 for (i = i - 1; i >= 1; i--) { 2546 port = am65_common_get_port(common, i); 2547 dl_port = &port->devlink_port; 2548 2549 devlink_port_unregister(dl_port); 2550 } 2551 dl_unreg: 2552 devlink_free(common->devlink); 2553 return ret; 2554 } 2555 2556 static void am65_cpsw_unregister_devlink(struct am65_cpsw_common *common) 2557 { 2558 struct devlink_port *dl_port; 2559 struct am65_cpsw_port *port; 2560 int i; 2561 2562 devlink_unregister(common->devlink); 2563 2564 for (i = 1; i <= common->port_num; i++) { 2565 port = am65_common_get_port(common, i); 2566 dl_port = &port->devlink_port; 2567 2568 devlink_port_unregister(dl_port); 2569 } 2570 2571 if (!AM65_CPSW_IS_CPSW2G(common) && 2572 IS_ENABLED(CONFIG_TI_K3_AM65_CPSW_SWITCHDEV)) 2573 devlink_params_unregister(common->devlink, 2574 am65_cpsw_devlink_params, 2575 ARRAY_SIZE(am65_cpsw_devlink_params)); 2576 2577 devlink_free(common->devlink); 2578 } 2579 2580 static int am65_cpsw_nuss_register_ndevs(struct am65_cpsw_common *common) 2581 { 2582 struct device *dev = common->dev; 2583 struct am65_cpsw_port *port; 2584 int ret = 0, i; 2585 2586 /* init tx channels */ 2587 ret = am65_cpsw_nuss_init_tx_chns(common); 2588 if (ret) 2589 return ret; 2590 ret = am65_cpsw_nuss_init_rx_chns(common); 2591 if (ret) 2592 return ret; 2593 2594 ret = am65_cpsw_nuss_register_devlink(common); 2595 if (ret) 2596 return ret; 2597 2598 for (i = 0; i < common->port_num; i++) { 2599 port = &common->ports[i]; 2600 2601 if (!port->ndev) 2602 continue; 2603 2604 SET_NETDEV_DEVLINK_PORT(port->ndev, &port->devlink_port); 2605 2606 ret = register_netdev(port->ndev); 2607 if (ret) { 2608 dev_err(dev, "error registering slave net device%i %d\n", 2609 i, ret); 2610 goto err_cleanup_ndev; 2611 } 2612 } 2613 2614 ret = am65_cpsw_register_notifiers(common); 2615 if (ret) 2616 goto err_cleanup_ndev; 2617 2618 /* can't auto unregister ndev using devm_add_action() due to 2619 * devres release sequence in DD core for DMA 2620 */ 2621 2622 return 0; 2623 2624 err_cleanup_ndev: 2625 am65_cpsw_nuss_cleanup_ndev(common); 2626 am65_cpsw_unregister_devlink(common); 2627 2628 return ret; 2629 } 2630 2631 int am65_cpsw_nuss_update_tx_chns(struct am65_cpsw_common *common, int num_tx) 2632 { 2633 int ret; 2634 2635 common->tx_ch_num = num_tx; 2636 ret = am65_cpsw_nuss_init_tx_chns(common); 2637 2638 return ret; 2639 } 2640 2641 struct am65_cpsw_soc_pdata { 2642 u32 quirks_dis; 2643 }; 2644 2645 static const struct am65_cpsw_soc_pdata am65x_soc_sr2_0 = { 2646 .quirks_dis = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2647 }; 2648 2649 static const struct soc_device_attribute am65_cpsw_socinfo[] = { 2650 { .family = "AM65X", 2651 .revision = "SR2.0", 2652 .data = &am65x_soc_sr2_0 2653 }, 2654 {/* sentinel */} 2655 }; 2656 2657 static const struct am65_cpsw_pdata am65x_sr1_0 = { 2658 .quirks = AM65_CPSW_QUIRK_I2027_NO_TX_CSUM, 2659 .ale_dev_id = "am65x-cpsw2g", 2660 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2661 }; 2662 2663 static const struct am65_cpsw_pdata j721e_pdata = { 2664 .quirks = 0, 2665 .ale_dev_id = "am65x-cpsw2g", 2666 .fdqring_mode = K3_RINGACC_RING_MODE_MESSAGE, 2667 }; 2668 2669 static const struct am65_cpsw_pdata am64x_cpswxg_pdata = { 2670 .quirks = 0, 2671 .ale_dev_id = "am64-cpswxg", 2672 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2673 }; 2674 2675 static const struct am65_cpsw_pdata j7200_cpswxg_pdata = { 2676 .quirks = 0, 2677 .ale_dev_id = "am64-cpswxg", 2678 .fdqring_mode = K3_RINGACC_RING_MODE_RING, 2679 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII), 2680 }; 2681 2682 static const struct of_device_id am65_cpsw_nuss_of_mtable[] = { 2683 { .compatible = "ti,am654-cpsw-nuss", .data = &am65x_sr1_0}, 2684 { .compatible = "ti,j721e-cpsw-nuss", .data = &j721e_pdata}, 2685 { .compatible = "ti,am642-cpsw-nuss", .data = &am64x_cpswxg_pdata}, 2686 { .compatible = "ti,j7200-cpswxg-nuss", .data = &j7200_cpswxg_pdata}, 2687 { /* sentinel */ }, 2688 }; 2689 MODULE_DEVICE_TABLE(of, am65_cpsw_nuss_of_mtable); 2690 2691 static void am65_cpsw_nuss_apply_socinfo(struct am65_cpsw_common *common) 2692 { 2693 const struct soc_device_attribute *soc; 2694 2695 soc = soc_device_match(am65_cpsw_socinfo); 2696 if (soc && soc->data) { 2697 const struct am65_cpsw_soc_pdata *socdata = soc->data; 2698 2699 /* disable quirks */ 2700 common->pdata.quirks &= ~socdata->quirks_dis; 2701 } 2702 } 2703 2704 static int am65_cpsw_nuss_probe(struct platform_device *pdev) 2705 { 2706 struct cpsw_ale_params ale_params = { 0 }; 2707 const struct of_device_id *of_id; 2708 struct device *dev = &pdev->dev; 2709 struct am65_cpsw_common *common; 2710 struct device_node *node; 2711 struct resource *res; 2712 struct clk *clk; 2713 u64 id_temp; 2714 int ret, i; 2715 int ale_entries; 2716 2717 common = devm_kzalloc(dev, sizeof(struct am65_cpsw_common), GFP_KERNEL); 2718 if (!common) 2719 return -ENOMEM; 2720 common->dev = dev; 2721 2722 of_id = of_match_device(am65_cpsw_nuss_of_mtable, dev); 2723 if (!of_id) 2724 return -EINVAL; 2725 common->pdata = *(const struct am65_cpsw_pdata *)of_id->data; 2726 2727 am65_cpsw_nuss_apply_socinfo(common); 2728 2729 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cpsw_nuss"); 2730 common->ss_base = devm_ioremap_resource(&pdev->dev, res); 2731 if (IS_ERR(common->ss_base)) 2732 return PTR_ERR(common->ss_base); 2733 common->cpsw_base = common->ss_base + AM65_CPSW_CPSW_NU_BASE; 2734 /* Use device's physical base address as switch id */ 2735 id_temp = cpu_to_be64(res->start); 2736 memcpy(common->switch_id, &id_temp, sizeof(res->start)); 2737 2738 node = of_get_child_by_name(dev->of_node, "ethernet-ports"); 2739 if (!node) 2740 return -ENOENT; 2741 common->port_num = of_get_child_count(node); 2742 of_node_put(node); 2743 if (common->port_num < 1 || common->port_num > AM65_CPSW_MAX_PORTS) 2744 return -ENOENT; 2745 2746 common->rx_flow_id_base = -1; 2747 init_completion(&common->tdown_complete); 2748 common->tx_ch_num = 1; 2749 common->pf_p0_rx_ptype_rrobin = false; 2750 common->default_vlan = 1; 2751 2752 common->ports = devm_kcalloc(dev, common->port_num, 2753 sizeof(*common->ports), 2754 GFP_KERNEL); 2755 if (!common->ports) 2756 return -ENOMEM; 2757 2758 clk = devm_clk_get(dev, "fck"); 2759 if (IS_ERR(clk)) 2760 return dev_err_probe(dev, PTR_ERR(clk), "getting fck clock\n"); 2761 common->bus_freq = clk_get_rate(clk); 2762 2763 pm_runtime_enable(dev); 2764 ret = pm_runtime_resume_and_get(dev); 2765 if (ret < 0) { 2766 pm_runtime_disable(dev); 2767 return ret; 2768 } 2769 2770 node = of_get_child_by_name(dev->of_node, "mdio"); 2771 if (!node) { 2772 dev_warn(dev, "MDIO node not found\n"); 2773 } else if (of_device_is_available(node)) { 2774 struct platform_device *mdio_pdev; 2775 2776 mdio_pdev = of_platform_device_create(node, NULL, dev); 2777 if (!mdio_pdev) { 2778 ret = -ENODEV; 2779 goto err_pm_clear; 2780 } 2781 2782 common->mdio_dev = &mdio_pdev->dev; 2783 } 2784 of_node_put(node); 2785 2786 am65_cpsw_nuss_get_ver(common); 2787 2788 ret = am65_cpsw_nuss_init_host_p(common); 2789 if (ret) 2790 goto err_of_clear; 2791 2792 ret = am65_cpsw_nuss_init_slave_ports(common); 2793 if (ret) 2794 goto err_of_clear; 2795 2796 /* init common data */ 2797 ale_params.dev = dev; 2798 ale_params.ale_ageout = AM65_CPSW_ALE_AGEOUT_DEFAULT; 2799 ale_params.ale_ports = common->port_num + 1; 2800 ale_params.ale_regs = common->cpsw_base + AM65_CPSW_NU_ALE_BASE; 2801 ale_params.dev_id = common->pdata.ale_dev_id; 2802 ale_params.bus_freq = common->bus_freq; 2803 2804 common->ale = cpsw_ale_create(&ale_params); 2805 if (IS_ERR(common->ale)) { 2806 dev_err(dev, "error initializing ale engine\n"); 2807 ret = PTR_ERR(common->ale); 2808 goto err_of_clear; 2809 } 2810 2811 ale_entries = common->ale->params.ale_entries; 2812 common->ale_context = devm_kzalloc(dev, 2813 ale_entries * ALE_ENTRY_WORDS * sizeof(u32), 2814 GFP_KERNEL); 2815 ret = am65_cpsw_init_cpts(common); 2816 if (ret) 2817 goto err_of_clear; 2818 2819 /* init ports */ 2820 for (i = 0; i < common->port_num; i++) 2821 am65_cpsw_nuss_slave_disable_unused(&common->ports[i]); 2822 2823 dev_set_drvdata(dev, common); 2824 2825 common->is_emac_mode = true; 2826 2827 ret = am65_cpsw_nuss_init_ndevs(common); 2828 if (ret) 2829 goto err_free_phylink; 2830 2831 ret = am65_cpsw_nuss_register_ndevs(common); 2832 if (ret) 2833 goto err_free_phylink; 2834 2835 pm_runtime_put(dev); 2836 return 0; 2837 2838 err_free_phylink: 2839 am65_cpsw_nuss_phylink_cleanup(common); 2840 err_of_clear: 2841 of_platform_device_destroy(common->mdio_dev, NULL); 2842 err_pm_clear: 2843 pm_runtime_put_sync(dev); 2844 pm_runtime_disable(dev); 2845 return ret; 2846 } 2847 2848 static int am65_cpsw_nuss_remove(struct platform_device *pdev) 2849 { 2850 struct device *dev = &pdev->dev; 2851 struct am65_cpsw_common *common; 2852 int ret; 2853 2854 common = dev_get_drvdata(dev); 2855 2856 ret = pm_runtime_resume_and_get(&pdev->dev); 2857 if (ret < 0) 2858 return ret; 2859 2860 am65_cpsw_unregister_devlink(common); 2861 am65_cpsw_unregister_notifiers(common); 2862 2863 /* must unregister ndevs here because DD release_driver routine calls 2864 * dma_deconfigure(dev) before devres_release_all(dev) 2865 */ 2866 am65_cpsw_nuss_cleanup_ndev(common); 2867 am65_cpsw_nuss_phylink_cleanup(common); 2868 2869 of_platform_device_destroy(common->mdio_dev, NULL); 2870 2871 pm_runtime_put_sync(&pdev->dev); 2872 pm_runtime_disable(&pdev->dev); 2873 return 0; 2874 } 2875 2876 #ifdef CONFIG_PM_SLEEP 2877 static int am65_cpsw_nuss_suspend(struct device *dev) 2878 { 2879 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2880 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2881 struct am65_cpsw_port *port; 2882 struct net_device *ndev; 2883 int i, ret; 2884 2885 cpsw_ale_dump(common->ale, common->ale_context); 2886 host_p->vid_context = readl(host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2887 for (i = 0; i < common->port_num; i++) { 2888 port = &common->ports[i]; 2889 ndev = port->ndev; 2890 2891 if (!ndev) 2892 continue; 2893 2894 port->vid_context = readl(port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2895 netif_device_detach(ndev); 2896 if (netif_running(ndev)) { 2897 rtnl_lock(); 2898 ret = am65_cpsw_nuss_ndo_slave_stop(ndev); 2899 rtnl_unlock(); 2900 if (ret < 0) { 2901 netdev_err(ndev, "failed to stop: %d", ret); 2902 return ret; 2903 } 2904 } 2905 } 2906 2907 am65_cpts_suspend(common->cpts); 2908 2909 am65_cpsw_nuss_remove_rx_chns(common); 2910 am65_cpsw_nuss_remove_tx_chns(common); 2911 2912 return 0; 2913 } 2914 2915 static int am65_cpsw_nuss_resume(struct device *dev) 2916 { 2917 struct am65_cpsw_common *common = dev_get_drvdata(dev); 2918 struct am65_cpsw_port *port; 2919 struct net_device *ndev; 2920 int i, ret; 2921 struct am65_cpsw_host *host_p = am65_common_get_host(common); 2922 2923 ret = am65_cpsw_nuss_init_tx_chns(common); 2924 if (ret) 2925 return ret; 2926 ret = am65_cpsw_nuss_init_rx_chns(common); 2927 if (ret) 2928 return ret; 2929 2930 /* If RX IRQ was disabled before suspend, keep it disabled */ 2931 if (common->rx_irq_disabled) 2932 disable_irq(common->rx_chns.irq); 2933 2934 am65_cpts_resume(common->cpts); 2935 2936 for (i = 0; i < common->port_num; i++) { 2937 port = &common->ports[i]; 2938 ndev = port->ndev; 2939 2940 if (!ndev) 2941 continue; 2942 2943 if (netif_running(ndev)) { 2944 rtnl_lock(); 2945 ret = am65_cpsw_nuss_ndo_slave_open(ndev); 2946 rtnl_unlock(); 2947 if (ret < 0) { 2948 netdev_err(ndev, "failed to start: %d", ret); 2949 return ret; 2950 } 2951 } 2952 2953 netif_device_attach(ndev); 2954 writel(port->vid_context, port->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2955 } 2956 2957 writel(host_p->vid_context, host_p->port_base + AM65_CPSW_PORT_VLAN_REG_OFFSET); 2958 cpsw_ale_restore(common->ale, common->ale_context); 2959 2960 return 0; 2961 } 2962 #endif /* CONFIG_PM_SLEEP */ 2963 2964 static const struct dev_pm_ops am65_cpsw_nuss_dev_pm_ops = { 2965 SET_SYSTEM_SLEEP_PM_OPS(am65_cpsw_nuss_suspend, am65_cpsw_nuss_resume) 2966 }; 2967 2968 static struct platform_driver am65_cpsw_nuss_driver = { 2969 .driver = { 2970 .name = AM65_CPSW_DRV_NAME, 2971 .of_match_table = am65_cpsw_nuss_of_mtable, 2972 .pm = &am65_cpsw_nuss_dev_pm_ops, 2973 }, 2974 .probe = am65_cpsw_nuss_probe, 2975 .remove = am65_cpsw_nuss_remove, 2976 }; 2977 2978 module_platform_driver(am65_cpsw_nuss_driver); 2979 2980 MODULE_LICENSE("GPL v2"); 2981 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>"); 2982 MODULE_DESCRIPTION("TI AM65 CPSW Ethernet driver"); 2983