1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) Tehuti Networks Ltd. */ 3 4 #ifndef _TN40_REGS_H_ 5 #define _TN40_REGS_H_ 6 7 /* Register region size */ 8 #define TN40_REGS_SIZE 0x10000 9 10 /* Registers from 0x0000-0x00fc were remapped to 0x4000-0x40fc */ 11 #define TN40_REG_TXD_CFG1_0 0x4000 12 #define TN40_REG_TXD_CFG1_1 0x4004 13 #define TN40_REG_TXD_CFG1_2 0x4008 14 #define TN40_REG_TXD_CFG1_3 0x400C 15 16 #define TN40_REG_RXF_CFG1_0 0x4010 17 #define TN40_REG_RXF_CFG1_1 0x4014 18 #define TN40_REG_RXF_CFG1_2 0x4018 19 #define TN40_REG_RXF_CFG1_3 0x401C 20 21 #define TN40_REG_RXD_CFG1_0 0x4020 22 #define TN40_REG_RXD_CFG1_1 0x4024 23 #define TN40_REG_RXD_CFG1_2 0x4028 24 #define TN40_REG_RXD_CFG1_3 0x402C 25 26 #define TN40_REG_TXF_CFG1_0 0x4030 27 #define TN40_REG_TXF_CFG1_1 0x4034 28 #define TN40_REG_TXF_CFG1_2 0x4038 29 #define TN40_REG_TXF_CFG1_3 0x403C 30 31 #define TN40_REG_TXD_CFG0_0 0x4040 32 #define TN40_REG_TXD_CFG0_1 0x4044 33 #define TN40_REG_TXD_CFG0_2 0x4048 34 #define TN40_REG_TXD_CFG0_3 0x404C 35 36 #define TN40_REG_RXF_CFG0_0 0x4050 37 #define TN40_REG_RXF_CFG0_1 0x4054 38 #define TN40_REG_RXF_CFG0_2 0x4058 39 #define TN40_REG_RXF_CFG0_3 0x405C 40 41 #define TN40_REG_RXD_CFG0_0 0x4060 42 #define TN40_REG_RXD_CFG0_1 0x4064 43 #define TN40_REG_RXD_CFG0_2 0x4068 44 #define TN40_REG_RXD_CFG0_3 0x406C 45 46 #define TN40_REG_TXF_CFG0_0 0x4070 47 #define TN40_REG_TXF_CFG0_1 0x4074 48 #define TN40_REG_TXF_CFG0_2 0x4078 49 #define TN40_REG_TXF_CFG0_3 0x407C 50 51 #define TN40_REG_TXD_WPTR_0 0x4080 52 #define TN40_REG_TXD_WPTR_1 0x4084 53 #define TN40_REG_TXD_WPTR_2 0x4088 54 #define TN40_REG_TXD_WPTR_3 0x408C 55 56 #define TN40_REG_RXF_WPTR_0 0x4090 57 #define TN40_REG_RXF_WPTR_1 0x4094 58 #define TN40_REG_RXF_WPTR_2 0x4098 59 #define TN40_REG_RXF_WPTR_3 0x409C 60 61 #define TN40_REG_RXD_WPTR_0 0x40A0 62 #define TN40_REG_RXD_WPTR_1 0x40A4 63 #define TN40_REG_RXD_WPTR_2 0x40A8 64 #define TN40_REG_RXD_WPTR_3 0x40AC 65 66 #define TN40_REG_TXF_WPTR_0 0x40B0 67 #define TN40_REG_TXF_WPTR_1 0x40B4 68 #define TN40_REG_TXF_WPTR_2 0x40B8 69 #define TN40_REG_TXF_WPTR_3 0x40BC 70 71 #define TN40_REG_TXD_RPTR_0 0x40C0 72 #define TN40_REG_TXD_RPTR_1 0x40C4 73 #define TN40_REG_TXD_RPTR_2 0x40C8 74 #define TN40_REG_TXD_RPTR_3 0x40CC 75 76 #define TN40_REG_RXF_RPTR_0 0x40D0 77 #define TN40_REG_RXF_RPTR_1 0x40D4 78 #define TN40_REG_RXF_RPTR_2 0x40D8 79 #define TN40_REG_RXF_RPTR_3 0x40DC 80 81 #define TN40_REG_RXD_RPTR_0 0x40E0 82 #define TN40_REG_RXD_RPTR_1 0x40E4 83 #define TN40_REG_RXD_RPTR_2 0x40E8 84 #define TN40_REG_RXD_RPTR_3 0x40EC 85 86 #define TN40_REG_TXF_RPTR_0 0x40F0 87 #define TN40_REG_TXF_RPTR_1 0x40F4 88 #define TN40_REG_TXF_RPTR_2 0x40F8 89 #define TN40_REG_TXF_RPTR_3 0x40FC 90 91 /* Hardware versioning */ 92 #define TN40_FPGA_VER 0x5030 93 94 /* Registers from 0x0100-0x0150 were remapped to 0x5100-0x5150 */ 95 #define TN40_REG_ISR TN40_REG_ISR0 96 #define TN40_REG_ISR0 0x5100 97 98 #define TN40_REG_IMR TN40_REG_IMR0 99 #define TN40_REG_IMR0 0x5110 100 101 #define TN40_REG_RDINTCM0 0x5120 102 #define TN40_REG_RDINTCM2 0x5128 103 104 #define TN40_REG_TDINTCM0 0x5130 105 106 #define TN40_REG_ISR_MSK0 0x5140 107 108 #define TN40_REG_INIT_SEMAPHORE 0x5170 109 #define TN40_REG_INIT_STATUS 0x5180 110 111 #define TN40_REG_MAC_LNK_STAT 0x0200 112 #define TN40_MAC_LINK_STAT 0x0004 /* Link state */ 113 114 #define TN40_REG_BLNK_LED 0x0210 115 116 #define TN40_REG_GMAC_RXF_A 0x1240 117 118 #define TN40_REG_UNC_MAC0_A 0x1250 119 #define TN40_REG_UNC_MAC1_A 0x1260 120 #define TN40_REG_UNC_MAC2_A 0x1270 121 122 #define TN40_REG_VLAN_0 0x1800 123 124 #define TN40_REG_MAX_FRAME_A 0x12C0 125 126 #define TN40_REG_RX_MAC_MCST0 0x1A80 127 #define TN40_REG_RX_MAC_MCST1 0x1A84 128 #define TN40_MAC_MCST_NUM 15 129 #define TN40_REG_RX_MCST_HASH0 0x1A00 130 #define TN40_MAC_MCST_HASH_NUM 8 131 132 #define TN40_REG_VPC 0x2300 133 #define TN40_REG_VIC 0x2320 134 #define TN40_REG_VGLB 0x2340 135 136 #define TN40_REG_CLKPLL 0x5000 137 138 /* MDIO interface */ 139 140 #define TN40_REG_MDIO_CMD_STAT 0x6030 141 #define TN40_REG_MDIO_CMD 0x6034 142 #define TN40_REG_MDIO_DATA 0x6038 143 #define TN40_REG_MDIO_ADDR 0x603C 144 #define TN40_GET_MDIO_BUSY(x) FIELD_GET(GENMASK(0, 0), (x)) 145 #define TN40_GET_MDIO_RD_ERR(x) FIELD_GET(GENMASK(1, 1), (x)) 146 147 #define TN40_REG_REVISION 0x6000 148 #define TN40_REG_SCRATCH 0x6004 149 #define TN40_REG_CTRLST 0x6008 150 #define TN40_REG_MAC_ADDR_0 0x600C 151 #define TN40_REG_MAC_ADDR_1 0x6010 152 #define TN40_REG_FRM_LENGTH 0x6014 153 #define TN40_REG_PAUSE_QUANT 0x6054 154 #define TN40_REG_RX_FIFO_SECTION 0x601C 155 #define TN40_REG_TX_FIFO_SECTION 0x6020 156 #define TN40_REG_RX_FULLNESS 0x6024 157 #define TN40_REG_TX_FULLNESS 0x6028 158 #define TN40_REG_HASHTABLE 0x602C 159 160 #define TN40_REG_RST_PORT 0x7000 161 #define TN40_REG_DIS_PORT 0x7010 162 #define TN40_REG_RST_QU 0x7020 163 #define TN40_REG_DIS_QU 0x7030 164 165 #define TN40_REG_CTRLST_TX_ENA 0x0001 166 #define TN40_REG_CTRLST_RX_ENA 0x0002 167 #define TN40_REG_CTRLST_PRM_ENA 0x0010 168 #define TN40_REG_CTRLST_PAD_ENA 0x0020 169 170 #define TN40_REG_CTRLST_BASE (TN40_REG_CTRLST_PAD_ENA | REG_CTRLST_PRM_ENA) 171 172 /* TXD TXF RXF RXD CONFIG 0x0000 --- 0x007c */ 173 #define TN40_TX_RX_CFG1_BASE 0xffffffff /*0-31 */ 174 #define TN40_TX_RX_CFG0_BASE 0xfffff000 /*31:12 */ 175 #define TN40_TX_RX_CFG0_RSVD 0x00000ffc /*11:2 */ 176 #define TN40_TX_RX_CFG0_SIZE 0x00000003 /*1:0 */ 177 178 /* TXD TXF RXF RXD WRITE 0x0080 --- 0x00BC */ 179 #define TN40_TXF_WPTR_WR_PTR 0x00007ff8 /*14:3 */ 180 181 /* TXD TXF RXF RXD READ 0x00CO --- 0x00FC */ 182 #define TN40_TXF_RPTR_RD_PTR 0x00007ff8 /*14:3 */ 183 184 /* The last 4 bits are dropped size is rounded to 16 */ 185 #define TN40_TXF_WPTR_MASK 0x7ff0 186 187 /* regISR 0x0100 */ 188 /* regIMR 0x0110 */ 189 #define TN40_IMR_INPROG 0x80000000 /*31 */ 190 #define TN40_IR_LNKCHG1 0x10000000 /*28 */ 191 #define TN40_IR_LNKCHG0 0x08000000 /*27 */ 192 #define TN40_IR_GPIO 0x04000000 /*26 */ 193 #define TN40_IR_RFRSH 0x02000000 /*25 */ 194 #define TN40_IR_RSVD 0x01000000 /*24 */ 195 #define TN40_IR_SWI 0x00800000 /*23 */ 196 #define TN40_IR_RX_FREE_3 0x00400000 /*22 */ 197 #define TN40_IR_RX_FREE_2 0x00200000 /*21 */ 198 #define TN40_IR_RX_FREE_1 0x00100000 /*20 */ 199 #define TN40_IR_RX_FREE_0 0x00080000 /*19 */ 200 #define TN40_IR_TX_FREE_3 0x00040000 /*18 */ 201 #define TN40_IR_TX_FREE_2 0x00020000 /*17 */ 202 #define TN40_IR_TX_FREE_1 0x00010000 /*16 */ 203 #define TN40_IR_TX_FREE_0 0x00008000 /*15 */ 204 #define TN40_IR_RX_DESC_3 0x00004000 /*14 */ 205 #define TN40_IR_RX_DESC_2 0x00002000 /*13 */ 206 #define TN40_IR_RX_DESC_1 0x00001000 /*12 */ 207 #define TN40_IR_RX_DESC_0 0x00000800 /*11 */ 208 #define TN40_IR_PSE 0x00000400 /*10 */ 209 #define TN40_IR_TMR3 0x00000200 /* 9 */ 210 #define TN40_IR_TMR2 0x00000100 /* 8 */ 211 #define TN40_IR_TMR1 0x00000080 /* 7 */ 212 #define TN40_IR_TMR0 0x00000040 /* 6 */ 213 #define TN40_IR_VNT 0x00000020 /* 5 */ 214 #define TN40_IR_RxFL 0x00000010 /* 4 */ 215 #define TN40_IR_SDPERR 0x00000008 /* 3 */ 216 #define TN40_IR_TR 0x00000004 /* 2 */ 217 #define TN40_IR_PCIE_LINK 0x00000002 /* 1 */ 218 #define TN40_IR_PCIE_TOUT 0x00000001 /* 0 */ 219 220 #define TN40_IR_EXTRA \ 221 (TN40_IR_RX_FREE_0 | TN40_IR_LNKCHG0 | TN40_IR_LNKCHG1 |\ 222 TN40_IR_PSE | TN40_IR_TMR0 | TN40_IR_PCIE_LINK | \ 223 TN40_IR_PCIE_TOUT) 224 225 #define TN40_GMAC_RX_FILTER_OSEN 0x1000 /* shared OS enable */ 226 #define TN40_GMAC_RX_FILTER_TXFC 0x0400 /* Tx flow control */ 227 #define TN40_GMAC_RX_FILTER_RSV0 0x0200 /* reserved */ 228 #define TN40_GMAC_RX_FILTER_FDA 0x0100 /* filter out direct address */ 229 #define TN40_GMAC_RX_FILTER_AOF 0x0080 /* accept over run */ 230 #define TN40_GMAC_RX_FILTER_ACF 0x0040 /* accept control frames */ 231 #define TN40_GMAC_RX_FILTER_ARUNT 0x0020 /* accept under run */ 232 #define TN40_GMAC_RX_FILTER_ACRC 0x0010 /* accept crc error */ 233 #define TN40_GMAC_RX_FILTER_AM 0x0008 /* accept multicast */ 234 #define TN40_GMAC_RX_FILTER_AB 0x0004 /* accept broadcast */ 235 #define TN40_GMAC_RX_FILTER_PRM 0x0001 /* [0:1] promiscuous mode */ 236 237 #define TN40_MAX_FRAME_AB_VAL 0x3fff /* 13:0 */ 238 239 #define TN40_CLKPLL_PLLLKD 0x0200 /* 9 */ 240 #define TN40_CLKPLL_RSTEND 0x0100 /* 8 */ 241 #define TN40_CLKPLL_SFTRST 0x0001 /* 0 */ 242 243 #define TN40_CLKPLL_LKD (TN40_CLKPLL_PLLLKD | TN40_CLKPLL_RSTEND) 244 245 #endif 246