1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* Copyright (c) Tehuti Networks Ltd. */ 3 4 #ifndef _TN40_H_ 5 #define _TN40_H_ 6 7 #include <linux/property.h> 8 #include "tn40_regs.h" 9 10 #define TN40_DRV_NAME "tn40xx" 11 12 #define PCI_DEVICE_ID_TEHUTI_TN9510 0x4025 13 14 #define TN40_MDIO_SPEED_1MHZ (1) 15 #define TN40_MDIO_SPEED_6MHZ (6) 16 17 /* netdev tx queue len for Luxor. The default value is 1000. 18 * ifconfig eth1 txqueuelen 3000 - to change it at runtime. 19 */ 20 #define TN40_NDEV_TXQ_LEN 1000 21 22 #define TN40_FIFO_SIZE 4096 23 #define TN40_FIFO_EXTRA_SPACE 1024 24 25 #define TN40_TXF_DESC_SZ 16 26 #define TN40_MAX_TX_LEVEL (priv->txd_fifo0.m.memsz - 16) 27 #define TN40_MIN_TX_LEVEL 256 28 #define TN40_NO_UPD_PACKETS 40 29 #define TN40_MAX_MTU BIT(14) 30 31 #define TN40_PCK_TH_MULT 128 32 #define TN40_INT_COAL_MULT 2 33 34 #define TN40_INT_REG_VAL(coal, coal_rc, rxf_th, pck_th) ( \ 35 FIELD_PREP(GENMASK(14, 0), (coal)) | \ 36 FIELD_PREP(BIT(15), (coal_rc)) | \ 37 FIELD_PREP(GENMASK(19, 16), (rxf_th)) | \ 38 FIELD_PREP(GENMASK(31, 20), (pck_th)) \ 39 ) 40 41 struct tn40_fifo { 42 dma_addr_t da; /* Physical address of fifo (used by HW) */ 43 char *va; /* Virtual address of fifo (used by SW) */ 44 u32 rptr, wptr; 45 /* Cached values of RPTR and WPTR registers, 46 * they're 32 bits on both 32 and 64 archs. 47 */ 48 u16 reg_cfg0; 49 u16 reg_cfg1; 50 u16 reg_rptr; 51 u16 reg_wptr; 52 u16 memsz; /* Memory size allocated for fifo */ 53 u16 size_mask; 54 u16 pktsz; /* Skb packet size to allocate */ 55 u16 rcvno; /* Number of buffers that come from this RXF */ 56 }; 57 58 struct tn40_txf_fifo { 59 struct tn40_fifo m; /* The minimal set of variables used by all fifos */ 60 }; 61 62 struct tn40_txd_fifo { 63 struct tn40_fifo m; /* The minimal set of variables used by all fifos */ 64 }; 65 66 struct tn40_rxf_fifo { 67 struct tn40_fifo m; /* The minimal set of variables used by all fifos */ 68 }; 69 70 struct tn40_rxd_fifo { 71 struct tn40_fifo m; /* The minimal set of variables used by all fifos */ 72 }; 73 74 struct tn40_rx_map { 75 struct page *page; 76 }; 77 78 struct tn40_rxdb { 79 unsigned int *stack; 80 struct tn40_rx_map *elems; 81 unsigned int nelem; 82 unsigned int top; 83 }; 84 85 union tn40_tx_dma_addr { 86 dma_addr_t dma; 87 struct sk_buff *skb; 88 }; 89 90 /* Entry in the db. 91 * if len == 0 addr is dma 92 * if len != 0 addr is skb 93 */ 94 struct tn40_tx_map { 95 union tn40_tx_dma_addr addr; 96 int len; 97 }; 98 99 /* tx database - implemented as circular fifo buffer */ 100 struct tn40_txdb { 101 struct tn40_tx_map *start; /* Points to the first element */ 102 struct tn40_tx_map *end; /* Points just AFTER the last element */ 103 struct tn40_tx_map *rptr; /* Points to the next element to read */ 104 struct tn40_tx_map *wptr; /* Points to the next element to write */ 105 int size; /* Number of elements in the db */ 106 }; 107 108 #define NODE_PROP(_NAME, _PROP) ( \ 109 (const struct software_node) { \ 110 .name = _NAME, \ 111 .properties = _PROP, \ 112 }) 113 114 #define NODE_PAR_PROP(_NAME, _PAR, _PROP) ( \ 115 (const struct software_node) { \ 116 .name = _NAME, \ 117 .parent = _PAR, \ 118 .properties = _PROP, \ 119 }) 120 121 enum tn40_swnodes { 122 SWNODE_MDIO, 123 SWNODE_PHY, 124 SWNODE_MAX 125 }; 126 127 struct tn40_nodes { 128 char phy_name[32]; 129 char mdio_name[32]; 130 struct property_entry phy_props[3]; 131 struct software_node swnodes[SWNODE_MAX]; 132 const struct software_node *group[SWNODE_MAX + 1]; 133 }; 134 135 struct tn40_priv { 136 struct net_device *ndev; 137 struct pci_dev *pdev; 138 139 struct tn40_nodes nodes; 140 141 struct napi_struct napi; 142 /* RX FIFOs: 1 for data (full) descs, and 2 for free descs */ 143 struct tn40_rxd_fifo rxd_fifo0; 144 struct tn40_rxf_fifo rxf_fifo0; 145 struct tn40_rxdb *rxdb0; /* Rx dbs to store skb pointers */ 146 struct page_pool *page_pool; 147 148 /* Tx FIFOs: 1 for data desc, 1 for empty (acks) desc */ 149 struct tn40_txd_fifo txd_fifo0; 150 struct tn40_txf_fifo txf_fifo0; 151 struct tn40_txdb txdb; 152 int tx_level; 153 int tx_update_mark; 154 int tx_noupd; 155 156 int stats_flag; 157 struct rtnl_link_stats64 stats; 158 u64 alloc_fail; 159 struct u64_stats_sync syncp; 160 161 u8 txd_size; 162 u8 txf_size; 163 u8 rxd_size; 164 u8 rxf_size; 165 u32 rdintcm; 166 u32 tdintcm; 167 168 u32 isr_mask; 169 170 void __iomem *regs; 171 172 /* SHORT_PKT_FIX */ 173 u32 b0_len; 174 dma_addr_t b0_dma; /* Physical address of buffer */ 175 char *b0_va; /* Virtual address of buffer */ 176 177 struct mii_bus *mdio; 178 struct phy_device *phydev; 179 struct phylink *phylink; 180 struct phylink_config phylink_config; 181 }; 182 183 /* RX FREE descriptor - 64bit */ 184 struct tn40_rxf_desc { 185 __le32 info; /* Buffer Count + Info - described below */ 186 __le32 va_lo; /* VAdr[31:0] */ 187 __le32 va_hi; /* VAdr[63:32] */ 188 __le32 pa_lo; /* PAdr[31:0] */ 189 __le32 pa_hi; /* PAdr[63:32] */ 190 __le32 len; /* Buffer Length */ 191 }; 192 193 #define TN40_GET_RXD_BC(x) FIELD_GET(GENMASK(4, 0), (x)) 194 #define TN40_GET_RXD_ERR(x) FIELD_GET(GENMASK(26, 21), (x)) 195 #define TN40_GET_RXD_PKT_ID(x) FIELD_GET(GENMASK(30, 28), (x)) 196 #define TN40_GET_RXD_VTAG(x) FIELD_GET(BIT(31), (x)) 197 #define TN40_GET_RXD_VLAN_TCI(x) FIELD_GET(GENMASK(15, 0), (x)) 198 199 struct tn40_rxd_desc { 200 __le32 rxd_val1; 201 __le16 len; 202 __le16 rxd_vlan; 203 __le32 va_lo; 204 __le32 va_hi; 205 __le32 rss_lo; 206 __le32 rss_hash; 207 }; 208 209 #define TN40_MAX_PBL (19) 210 /* PBL describes each virtual buffer to be transmitted from the host. */ 211 struct tn40_pbl { 212 __le32 pa_lo; 213 __le32 pa_hi; 214 __le32 len; 215 }; 216 217 /* First word for TXD descriptor. It means: type = 3 for regular Tx packet, 218 * hw_csum = 7 for IP+UDP+TCP HW checksums. 219 */ 220 #define TN40_TXD_W1_VAL(bc, checksum, vtag, lgsnd, vlan_id) ( \ 221 GENMASK(17, 16) | \ 222 FIELD_PREP(GENMASK(4, 0), (bc)) | \ 223 FIELD_PREP(GENMASK(7, 5), (checksum)) | \ 224 FIELD_PREP(BIT(8), (vtag)) | \ 225 FIELD_PREP(GENMASK(12, 9), (lgsnd)) | \ 226 FIELD_PREP(GENMASK(15, 13), \ 227 FIELD_GET(GENMASK(15, 13), (vlan_id))) | \ 228 FIELD_PREP(GENMASK(31, 20), \ 229 FIELD_GET(GENMASK(11, 0), (vlan_id))) \ 230 ) 231 232 struct tn40_txd_desc { 233 __le32 txd_val1; 234 __le16 mss; 235 __le16 length; 236 __le32 va_lo; 237 __le32 va_hi; 238 struct tn40_pbl pbl[]; /* Fragments */ 239 }; 240 241 struct tn40_txf_desc { 242 u32 status; 243 u32 va_lo; /* VAdr[31:0] */ 244 u32 va_hi; /* VAdr[63:32] */ 245 u32 pad; 246 }; 247 248 static inline u32 tn40_read_reg(struct tn40_priv *priv, u32 reg) 249 { 250 return readl(priv->regs + reg); 251 } 252 253 static inline void tn40_write_reg(struct tn40_priv *priv, u32 reg, u32 val) 254 { 255 writel(val, priv->regs + reg); 256 } 257 258 int tn40_set_link_speed(struct tn40_priv *priv, u32 speed); 259 260 void tn40_swnodes_cleanup(struct tn40_priv *priv); 261 int tn40_mdiobus_init(struct tn40_priv *priv); 262 263 int tn40_phy_register(struct tn40_priv *priv); 264 void tn40_phy_unregister(struct tn40_priv *priv); 265 266 #endif /* _TN40XX_H */ 267