1 // SPDX-License-Identifier: GPL-2.0+ 2 /* Copyright (c) Tehuti Networks Ltd. */ 3 4 #include <linux/bitfield.h> 5 #include <linux/ethtool.h> 6 #include <linux/firmware.h> 7 #include <linux/if_vlan.h> 8 #include <linux/iopoll.h> 9 #include <linux/netdevice.h> 10 #include <linux/pci.h> 11 #include <linux/phylink.h> 12 #include <linux/vmalloc.h> 13 #include <net/page_pool/helpers.h> 14 15 #include "tn40.h" 16 17 #define TN40_SHORT_PACKET_SIZE 60 18 #define TN40_FIRMWARE_NAME "tehuti/bdx.bin" 19 20 static void tn40_enable_interrupts(struct tn40_priv *priv) 21 { 22 tn40_write_reg(priv, TN40_REG_IMR, priv->isr_mask); 23 } 24 25 static void tn40_disable_interrupts(struct tn40_priv *priv) 26 { 27 tn40_write_reg(priv, TN40_REG_IMR, 0); 28 } 29 30 static int tn40_fifo_alloc(struct tn40_priv *priv, struct tn40_fifo *f, 31 int fsz_type, 32 u16 reg_cfg0, u16 reg_cfg1, 33 u16 reg_rptr, u16 reg_wptr) 34 { 35 u16 memsz = TN40_FIFO_SIZE * (1 << fsz_type); 36 u64 cfg_base; 37 38 memset(f, 0, sizeof(struct tn40_fifo)); 39 /* 1K extra space is allocated at the end of the fifo to simplify 40 * processing of descriptors that wraps around fifo's end. 41 */ 42 f->va = dma_alloc_coherent(&priv->pdev->dev, 43 memsz + TN40_FIFO_EXTRA_SPACE, &f->da, 44 GFP_KERNEL); 45 if (!f->va) 46 return -ENOMEM; 47 48 f->reg_cfg0 = reg_cfg0; 49 f->reg_cfg1 = reg_cfg1; 50 f->reg_rptr = reg_rptr; 51 f->reg_wptr = reg_wptr; 52 f->rptr = 0; 53 f->wptr = 0; 54 f->memsz = memsz; 55 f->size_mask = memsz - 1; 56 cfg_base = lower_32_bits((f->da & TN40_TX_RX_CFG0_BASE) | fsz_type); 57 tn40_write_reg(priv, reg_cfg0, cfg_base); 58 tn40_write_reg(priv, reg_cfg1, upper_32_bits(f->da)); 59 return 0; 60 } 61 62 static void tn40_fifo_free(struct tn40_priv *priv, struct tn40_fifo *f) 63 { 64 dma_free_coherent(&priv->pdev->dev, 65 f->memsz + TN40_FIFO_EXTRA_SPACE, f->va, f->da); 66 } 67 68 static struct tn40_rxdb *tn40_rxdb_alloc(int nelem) 69 { 70 size_t size = sizeof(struct tn40_rxdb) + (nelem * sizeof(int)) + 71 (nelem * sizeof(struct tn40_rx_map)); 72 struct tn40_rxdb *db; 73 int i; 74 75 db = vzalloc(size); 76 if (db) { 77 db->stack = (int *)(db + 1); 78 db->elems = (void *)(db->stack + nelem); 79 db->nelem = nelem; 80 db->top = nelem; 81 /* make the first alloc close to db struct */ 82 for (i = 0; i < nelem; i++) 83 db->stack[i] = nelem - i - 1; 84 } 85 return db; 86 } 87 88 static void tn40_rxdb_free(struct tn40_rxdb *db) 89 { 90 vfree(db); 91 } 92 93 static int tn40_rxdb_alloc_elem(struct tn40_rxdb *db) 94 { 95 return db->stack[--db->top]; 96 } 97 98 static void *tn40_rxdb_addr_elem(struct tn40_rxdb *db, unsigned int n) 99 { 100 return db->elems + n; 101 } 102 103 static int tn40_rxdb_available(struct tn40_rxdb *db) 104 { 105 return db->top; 106 } 107 108 static void tn40_rxdb_free_elem(struct tn40_rxdb *db, unsigned int n) 109 { 110 db->stack[db->top++] = n; 111 } 112 113 /** 114 * tn40_create_rx_ring - Initialize RX all related HW and SW resources 115 * @priv: NIC private structure 116 * 117 * create_rx_ring creates rxf and rxd fifos, updates the relevant HW registers, 118 * preallocates skbs for rx. It assumes that Rx is disabled in HW funcs are 119 * grouped for better cache usage 120 * 121 * RxD fifo is smaller then RxF fifo by design. Upon high load, RxD will be 122 * filled and packets will be dropped by the NIC without getting into the host 123 * or generating interrupts. In this situation the host has no chance of 124 * processing all the packets. Dropping packets by the NIC is cheaper, since it 125 * takes 0 CPU cycles. 126 * 127 * Return: 0 on success and negative value on error. 128 */ 129 static int tn40_create_rx_ring(struct tn40_priv *priv) 130 { 131 struct page_pool_params pp = { 132 .dev = &priv->pdev->dev, 133 .napi = &priv->napi, 134 .dma_dir = DMA_FROM_DEVICE, 135 .netdev = priv->ndev, 136 .flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV, 137 .max_len = PAGE_SIZE, 138 }; 139 int ret, pkt_size, nr; 140 141 priv->page_pool = page_pool_create(&pp); 142 if (IS_ERR(priv->page_pool)) 143 return PTR_ERR(priv->page_pool); 144 145 ret = tn40_fifo_alloc(priv, &priv->rxd_fifo0.m, priv->rxd_size, 146 TN40_REG_RXD_CFG0_0, TN40_REG_RXD_CFG1_0, 147 TN40_REG_RXD_RPTR_0, TN40_REG_RXD_WPTR_0); 148 if (ret) 149 goto err_destroy_page_pool; 150 151 ret = tn40_fifo_alloc(priv, &priv->rxf_fifo0.m, priv->rxf_size, 152 TN40_REG_RXF_CFG0_0, TN40_REG_RXF_CFG1_0, 153 TN40_REG_RXF_RPTR_0, TN40_REG_RXF_WPTR_0); 154 if (ret) 155 goto err_free_rxd; 156 157 pkt_size = priv->ndev->mtu + VLAN_ETH_HLEN; 158 priv->rxf_fifo0.m.pktsz = pkt_size; 159 nr = priv->rxf_fifo0.m.memsz / sizeof(struct tn40_rxf_desc); 160 priv->rxdb0 = tn40_rxdb_alloc(nr); 161 if (!priv->rxdb0) { 162 ret = -ENOMEM; 163 goto err_free_rxf; 164 } 165 return 0; 166 err_free_rxf: 167 tn40_fifo_free(priv, &priv->rxf_fifo0.m); 168 err_free_rxd: 169 tn40_fifo_free(priv, &priv->rxd_fifo0.m); 170 err_destroy_page_pool: 171 page_pool_destroy(priv->page_pool); 172 return ret; 173 } 174 175 static void tn40_rx_free_buffers(struct tn40_priv *priv) 176 { 177 struct tn40_rxdb *db = priv->rxdb0; 178 struct tn40_rx_map *dm; 179 u16 i; 180 181 netdev_dbg(priv->ndev, "total =%d free =%d busy =%d\n", db->nelem, 182 tn40_rxdb_available(db), 183 db->nelem - tn40_rxdb_available(db)); 184 185 for (i = 0; i < db->nelem; i++) { 186 dm = tn40_rxdb_addr_elem(db, i); 187 if (dm->page) 188 page_pool_put_full_page(priv->page_pool, dm->page, 189 false); 190 } 191 } 192 193 static void tn40_destroy_rx_ring(struct tn40_priv *priv) 194 { 195 if (priv->rxdb0) { 196 tn40_rx_free_buffers(priv); 197 tn40_rxdb_free(priv->rxdb0); 198 priv->rxdb0 = NULL; 199 } 200 tn40_fifo_free(priv, &priv->rxf_fifo0.m); 201 tn40_fifo_free(priv, &priv->rxd_fifo0.m); 202 page_pool_destroy(priv->page_pool); 203 } 204 205 static void tn40_set_rx_desc(struct tn40_priv *priv, int idx, u64 dma) 206 { 207 struct tn40_rxf_fifo *f = &priv->rxf_fifo0; 208 struct tn40_rxf_desc *rxfd; 209 int delta; 210 211 rxfd = (struct tn40_rxf_desc *)(f->m.va + f->m.wptr); 212 rxfd->info = cpu_to_le32(0x10003); /* INFO =1 BC =3 */ 213 rxfd->va_lo = cpu_to_le32(idx); 214 rxfd->pa_lo = cpu_to_le32(lower_32_bits(dma)); 215 rxfd->pa_hi = cpu_to_le32(upper_32_bits(dma)); 216 rxfd->len = cpu_to_le32(f->m.pktsz); 217 f->m.wptr += sizeof(struct tn40_rxf_desc); 218 delta = f->m.wptr - f->m.memsz; 219 if (unlikely(delta >= 0)) { 220 f->m.wptr = delta; 221 if (delta > 0) { 222 memcpy(f->m.va, f->m.va + f->m.memsz, delta); 223 netdev_dbg(priv->ndev, 224 "wrapped rxd descriptor\n"); 225 } 226 } 227 } 228 229 /** 230 * tn40_rx_alloc_buffers - Fill rxf fifo with buffers. 231 * 232 * @priv: NIC's private structure 233 * 234 * rx_alloc_buffers allocates buffers via the page pool API, builds rxf descs 235 * and pushes them (rxf descr) into the rxf fifo. The pages are stored in rxdb. 236 * To calculate the free space, we uses the cached values of RPTR and WPTR 237 * when needed. This function also updates RPTR and WPTR. 238 */ 239 static void tn40_rx_alloc_buffers(struct tn40_priv *priv) 240 { 241 struct tn40_rxf_fifo *f = &priv->rxf_fifo0; 242 struct tn40_rxdb *db = priv->rxdb0; 243 struct tn40_rx_map *dm; 244 struct page *page; 245 int dno, i, idx; 246 247 dno = tn40_rxdb_available(db) - 1; 248 for (i = dno; i > 0; i--) { 249 page = page_pool_dev_alloc_pages(priv->page_pool); 250 if (!page) 251 break; 252 253 idx = tn40_rxdb_alloc_elem(db); 254 tn40_set_rx_desc(priv, idx, page_pool_get_dma_addr(page)); 255 dm = tn40_rxdb_addr_elem(db, idx); 256 dm->page = page; 257 } 258 if (i != dno) 259 tn40_write_reg(priv, f->m.reg_wptr, 260 f->m.wptr & TN40_TXF_WPTR_WR_PTR); 261 netdev_dbg(priv->ndev, "write_reg 0x%04x f->m.reg_wptr 0x%x\n", 262 f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); 263 netdev_dbg(priv->ndev, "read_reg 0x%04x f->m.reg_rptr=0x%x\n", 264 f->m.reg_rptr, tn40_read_reg(priv, f->m.reg_rptr)); 265 netdev_dbg(priv->ndev, "write_reg 0x%04x f->m.reg_wptr=0x%x\n", 266 f->m.reg_wptr, tn40_read_reg(priv, f->m.reg_wptr)); 267 } 268 269 static void tn40_recycle_rx_buffer(struct tn40_priv *priv, 270 struct tn40_rxd_desc *rxdd) 271 { 272 struct tn40_rxf_fifo *f = &priv->rxf_fifo0; 273 struct tn40_rx_map *dm; 274 int idx; 275 276 idx = le32_to_cpu(rxdd->va_lo); 277 dm = tn40_rxdb_addr_elem(priv->rxdb0, idx); 278 tn40_set_rx_desc(priv, idx, page_pool_get_dma_addr(dm->page)); 279 280 tn40_write_reg(priv, f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); 281 } 282 283 static int tn40_rx_receive(struct tn40_priv *priv, int budget) 284 { 285 struct tn40_rxd_fifo *f = &priv->rxd_fifo0; 286 u32 rxd_val1, rxd_err, pkt_id; 287 int tmp_len, size, done = 0; 288 struct tn40_rxdb *db = NULL; 289 struct tn40_rxd_desc *rxdd; 290 struct tn40_rx_map *dm; 291 struct sk_buff *skb; 292 u16 len, rxd_vlan; 293 int idx; 294 295 f->m.wptr = tn40_read_reg(priv, f->m.reg_wptr) & TN40_TXF_WPTR_WR_PTR; 296 size = f->m.wptr - f->m.rptr; 297 if (size < 0) 298 size += f->m.memsz; /* Size is negative :-) */ 299 300 while (size > 0) { 301 rxdd = (struct tn40_rxd_desc *)(f->m.va + f->m.rptr); 302 db = priv->rxdb0; 303 304 /* We have a chicken and egg problem here. If the 305 * descriptor is wrapped we first need to copy the tail 306 * of the descriptor to the end of the buffer before 307 * extracting values from the descriptor. However in 308 * order to know if the descriptor is wrapped we need to 309 * obtain the length of the descriptor from (the 310 * wrapped) descriptor. Luckily the length is the first 311 * word of the descriptor. Descriptor lengths are 312 * multiples of 8 bytes so in case of a wrapped 313 * descriptor the first 8 bytes guaranteed to appear 314 * before the end of the buffer. We first obtain the 315 * length, we then copy the rest of the descriptor if 316 * needed and then extract the rest of the values from 317 * the descriptor. 318 * 319 * Do not change the order of operations as it will 320 * break the code!!! 321 */ 322 rxd_val1 = le32_to_cpu(rxdd->rxd_val1); 323 tmp_len = TN40_GET_RXD_BC(rxd_val1) << 3; 324 pkt_id = TN40_GET_RXD_PKT_ID(rxd_val1); 325 size -= tmp_len; 326 /* CHECK FOR A PARTIALLY ARRIVED DESCRIPTOR */ 327 if (size < 0) { 328 netdev_dbg(priv->ndev, 329 "%s partially arrived desc tmp_len %d\n", 330 __func__, tmp_len); 331 break; 332 } 333 /* make sure that the descriptor fully is arrived 334 * before reading the rest of the descriptor. 335 */ 336 rmb(); 337 338 /* A special treatment is given to non-contiguous 339 * descriptors that start near the end, wraps around 340 * and continue at the beginning. The second part is 341 * copied right after the first, and then descriptor 342 * is interpreted as normal. The fifo has an extra 343 * space to allow such operations. 344 */ 345 346 /* HAVE WE REACHED THE END OF THE QUEUE? */ 347 f->m.rptr += tmp_len; 348 tmp_len = f->m.rptr - f->m.memsz; 349 if (unlikely(tmp_len >= 0)) { 350 f->m.rptr = tmp_len; 351 if (tmp_len > 0) { 352 /* COPY PARTIAL DESCRIPTOR 353 * TO THE END OF THE QUEUE 354 */ 355 netdev_dbg(priv->ndev, 356 "wrapped desc rptr=%d tmp_len=%d\n", 357 f->m.rptr, tmp_len); 358 memcpy(f->m.va + f->m.memsz, f->m.va, tmp_len); 359 } 360 } 361 idx = le32_to_cpu(rxdd->va_lo); 362 dm = tn40_rxdb_addr_elem(db, idx); 363 prefetch(dm); 364 365 len = le16_to_cpu(rxdd->len); 366 rxd_vlan = le16_to_cpu(rxdd->rxd_vlan); 367 /* CHECK FOR ERRORS */ 368 rxd_err = TN40_GET_RXD_ERR(rxd_val1); 369 if (unlikely(rxd_err)) { 370 u64_stats_update_begin(&priv->syncp); 371 priv->stats.rx_errors++; 372 u64_stats_update_end(&priv->syncp); 373 tn40_recycle_rx_buffer(priv, rxdd); 374 continue; 375 } 376 377 skb = napi_build_skb(page_address(dm->page), PAGE_SIZE); 378 if (!skb) { 379 u64_stats_update_begin(&priv->syncp); 380 priv->stats.rx_dropped++; 381 u64_stats_update_end(&priv->syncp); 382 tn40_recycle_rx_buffer(priv, rxdd); 383 break; 384 } 385 skb_mark_for_recycle(skb); 386 skb_put(skb, len); 387 skb->protocol = eth_type_trans(skb, priv->ndev); 388 skb->ip_summed = 389 (pkt_id == 0) ? CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 390 if (TN40_GET_RXD_VTAG(rxd_val1)) 391 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 392 TN40_GET_RXD_VLAN_TCI(rxd_vlan)); 393 394 dm->page = NULL; 395 tn40_rxdb_free_elem(db, idx); 396 397 napi_gro_receive(&priv->napi, skb); 398 399 u64_stats_update_begin(&priv->syncp); 400 priv->stats.rx_bytes += len; 401 u64_stats_update_end(&priv->syncp); 402 403 if (unlikely(++done >= budget)) 404 break; 405 } 406 u64_stats_update_begin(&priv->syncp); 407 priv->stats.rx_packets += done; 408 u64_stats_update_end(&priv->syncp); 409 /* FIXME: Do something to minimize pci accesses */ 410 tn40_write_reg(priv, f->m.reg_rptr, f->m.rptr & TN40_TXF_WPTR_WR_PTR); 411 tn40_rx_alloc_buffers(priv); 412 return done; 413 } 414 415 /* TX HW/SW interaction overview 416 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 417 * There are 2 types of TX communication channels between driver and NIC. 418 * 1) TX Free Fifo - TXF - Holds ack descriptors for sent packets. 419 * 2) TX Data Fifo - TXD - Holds descriptors of full buffers. 420 * 421 * Currently the NIC supports TSO, checksumming and gather DMA 422 * UFO and IP fragmentation is on the way. 423 * 424 * RX SW Data Structures 425 * ~~~~~~~~~~~~~~~~~~~~~ 426 * TXDB is used to keep track of all skbs owned by SW and their DMA addresses. 427 * For TX case, ownership lasts from getting the packet via hard_xmit and 428 * until the HW acknowledges sending the packet by TXF descriptors. 429 * TXDB is implemented as a cyclic buffer. 430 * 431 * FIFO objects keep info about the fifo's size and location, relevant HW 432 * registers, usage and skb db. Each RXD and RXF fifo has their own fifo 433 * structure. Implemented as simple struct. 434 * 435 * TX SW Execution Flow 436 * ~~~~~~~~~~~~~~~~~~~~ 437 * OS calls the driver's hard_xmit method with a packet to send. The driver 438 * creates DMA mappings, builds TXD descriptors and kicks the HW by updating 439 * TXD WPTR. 440 * 441 * When a packet is sent, The HW write a TXF descriptor and the SW 442 * frees the original skb. To prevent TXD fifo overflow without 443 * reading HW registers every time, the SW deploys "tx level" 444 * technique. Upon startup, the tx level is initialized to TXD fifo 445 * length. For every sent packet, the SW gets its TXD descriptor size 446 * (from a pre-calculated array) and subtracts it from tx level. The 447 * size is also stored in txdb. When a TXF ack arrives, the SW fetched 448 * the size of the original TXD descriptor from the txdb and adds it 449 * to the tx level. When the Tx level drops below some predefined 450 * threshold, the driver stops the TX queue. When the TX level rises 451 * above that level, the tx queue is enabled again. 452 * 453 * This technique avoids excessive reading of RPTR and WPTR registers. 454 * As our benchmarks shows, it adds 1.5 Gbit/sec to NIC's throughput. 455 */ 456 static void tn40_do_tx_db_ptr_next(struct tn40_txdb *db, 457 struct tn40_tx_map **pptr) 458 { 459 ++*pptr; 460 if (unlikely(*pptr == db->end)) 461 *pptr = db->start; 462 } 463 464 static void tn40_tx_db_inc_rptr(struct tn40_txdb *db) 465 { 466 tn40_do_tx_db_ptr_next(db, &db->rptr); 467 } 468 469 static void tn40_tx_db_inc_wptr(struct tn40_txdb *db) 470 { 471 tn40_do_tx_db_ptr_next(db, &db->wptr); 472 } 473 474 static int tn40_tx_db_init(struct tn40_txdb *d, int sz_type) 475 { 476 int memsz = TN40_FIFO_SIZE * (1 << (sz_type + 1)); 477 478 d->start = vzalloc(memsz); 479 if (!d->start) 480 return -ENOMEM; 481 /* In order to differentiate between an empty db state and a full db 482 * state at least one element should always be empty in order to 483 * avoid rptr == wptr, which means that the db is empty. 484 */ 485 d->size = memsz / sizeof(struct tn40_tx_map) - 1; 486 d->end = d->start + d->size + 1; /* just after last element */ 487 488 /* All dbs are created empty */ 489 d->rptr = d->start; 490 d->wptr = d->start; 491 return 0; 492 } 493 494 static void tn40_tx_db_close(struct tn40_txdb *d) 495 { 496 if (d->start) { 497 vfree(d->start); 498 d->start = NULL; 499 } 500 } 501 502 /* Sizes of tx desc (including padding if needed) as function of the SKB's 503 * frag number 504 * 7 - is number of lwords in txd with one phys buffer 505 * 3 - is number of lwords used for every additional phys buffer 506 * for (i = 0; i < TN40_MAX_PBL; i++) { 507 * lwords = 7 + (i * 3); 508 * if (lwords & 1) 509 * lwords++; pad it with 1 lword 510 * tn40_txd_sizes[i].bytes = lwords << 2; 511 * tn40_txd_sizes[i].qwords = lwords >> 1; 512 * } 513 */ 514 static struct { 515 u16 bytes; 516 u16 qwords; /* qword = 64 bit */ 517 } tn40_txd_sizes[] = { 518 {0x20, 0x04}, 519 {0x28, 0x05}, 520 {0x38, 0x07}, 521 {0x40, 0x08}, 522 {0x50, 0x0a}, 523 {0x58, 0x0b}, 524 {0x68, 0x0d}, 525 {0x70, 0x0e}, 526 {0x80, 0x10}, 527 {0x88, 0x11}, 528 {0x98, 0x13}, 529 {0xa0, 0x14}, 530 {0xb0, 0x16}, 531 {0xb8, 0x17}, 532 {0xc8, 0x19}, 533 {0xd0, 0x1a}, 534 {0xe0, 0x1c}, 535 {0xe8, 0x1d}, 536 {0xf8, 0x1f}, 537 }; 538 539 static void tn40_pbl_set(struct tn40_pbl *pbl, dma_addr_t dma, int len) 540 { 541 pbl->len = cpu_to_le32(len); 542 pbl->pa_lo = cpu_to_le32(lower_32_bits(dma)); 543 pbl->pa_hi = cpu_to_le32(upper_32_bits(dma)); 544 } 545 546 static void tn40_txdb_set(struct tn40_txdb *db, dma_addr_t dma, int len) 547 { 548 db->wptr->len = len; 549 db->wptr->addr.dma = dma; 550 } 551 552 struct tn40_mapping_info { 553 dma_addr_t dma; 554 size_t size; 555 }; 556 557 /** 558 * tn40_tx_map_skb - create and store DMA mappings for skb's data blocks 559 * @priv: NIC private structure 560 * @skb: socket buffer to map 561 * @txdd: pointer to tx descriptor to be updated 562 * @pkt_len: pointer to unsigned long value 563 * 564 * This function creates DMA mappings for skb's data blocks and writes them to 565 * PBL of a new tx descriptor. It also stores them in the tx db, so they could 566 * be unmapped after the data has been sent. It is the responsibility of the 567 * caller to make sure that there is enough space in the txdb. The last 568 * element holds a pointer to skb itself and is marked with a zero length. 569 * 570 * Return: 0 on success and negative value on error. 571 */ 572 static int tn40_tx_map_skb(struct tn40_priv *priv, struct sk_buff *skb, 573 struct tn40_txd_desc *txdd, unsigned int *pkt_len) 574 { 575 struct tn40_mapping_info info[TN40_MAX_PBL]; 576 int nr_frags = skb_shinfo(skb)->nr_frags; 577 struct tn40_pbl *pbl = &txdd->pbl[0]; 578 struct tn40_txdb *db = &priv->txdb; 579 unsigned int size; 580 int i, len, ret; 581 dma_addr_t dma; 582 583 netdev_dbg(priv->ndev, "TX skb %p skbLen %d dataLen %d frags %d\n", skb, 584 skb->len, skb->data_len, nr_frags); 585 if (nr_frags > TN40_MAX_PBL - 1) { 586 ret = skb_linearize(skb); 587 if (ret) 588 return ret; 589 nr_frags = skb_shinfo(skb)->nr_frags; 590 } 591 /* initial skb */ 592 len = skb->len - skb->data_len; 593 dma = dma_map_single(&priv->pdev->dev, skb->data, len, 594 DMA_TO_DEVICE); 595 ret = dma_mapping_error(&priv->pdev->dev, dma); 596 if (ret) 597 return ret; 598 599 tn40_txdb_set(db, dma, len); 600 tn40_pbl_set(pbl++, db->wptr->addr.dma, db->wptr->len); 601 *pkt_len = db->wptr->len; 602 603 for (i = 0; i < nr_frags; i++) { 604 skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 605 606 size = skb_frag_size(frag); 607 dma = skb_frag_dma_map(&priv->pdev->dev, frag, 0, 608 size, DMA_TO_DEVICE); 609 610 ret = dma_mapping_error(&priv->pdev->dev, dma); 611 if (ret) 612 goto mapping_error; 613 info[i].dma = dma; 614 info[i].size = size; 615 } 616 617 for (i = 0; i < nr_frags; i++) { 618 tn40_tx_db_inc_wptr(db); 619 tn40_txdb_set(db, info[i].dma, info[i].size); 620 tn40_pbl_set(pbl++, db->wptr->addr.dma, db->wptr->len); 621 *pkt_len += db->wptr->len; 622 } 623 624 /* SHORT_PKT_FIX */ 625 if (skb->len < TN40_SHORT_PACKET_SIZE) 626 ++nr_frags; 627 628 /* Add skb clean up info. */ 629 tn40_tx_db_inc_wptr(db); 630 db->wptr->len = -tn40_txd_sizes[nr_frags].bytes; 631 db->wptr->addr.skb = skb; 632 tn40_tx_db_inc_wptr(db); 633 634 return 0; 635 mapping_error: 636 dma_unmap_page(&priv->pdev->dev, db->wptr->addr.dma, db->wptr->len, 637 DMA_TO_DEVICE); 638 for (; i > 0; i--) 639 dma_unmap_page(&priv->pdev->dev, info[i - 1].dma, 640 info[i - 1].size, DMA_TO_DEVICE); 641 return -ENOMEM; 642 } 643 644 static int tn40_create_tx_ring(struct tn40_priv *priv) 645 { 646 int ret; 647 648 ret = tn40_fifo_alloc(priv, &priv->txd_fifo0.m, priv->txd_size, 649 TN40_REG_TXD_CFG0_0, TN40_REG_TXD_CFG1_0, 650 TN40_REG_TXD_RPTR_0, TN40_REG_TXD_WPTR_0); 651 if (ret) 652 return ret; 653 654 ret = tn40_fifo_alloc(priv, &priv->txf_fifo0.m, priv->txf_size, 655 TN40_REG_TXF_CFG0_0, TN40_REG_TXF_CFG1_0, 656 TN40_REG_TXF_RPTR_0, TN40_REG_TXF_WPTR_0); 657 if (ret) 658 goto err_free_txd; 659 660 /* The TX db has to keep mappings for all packets sent (on 661 * TxD) and not yet reclaimed (on TxF). 662 */ 663 ret = tn40_tx_db_init(&priv->txdb, max(priv->txd_size, priv->txf_size)); 664 if (ret) 665 goto err_free_txf; 666 667 /* SHORT_PKT_FIX */ 668 priv->b0_len = 64; 669 priv->b0_va = dma_alloc_coherent(&priv->pdev->dev, priv->b0_len, 670 &priv->b0_dma, GFP_KERNEL); 671 if (!priv->b0_va) 672 goto err_free_db; 673 674 priv->tx_level = TN40_MAX_TX_LEVEL; 675 priv->tx_update_mark = priv->tx_level - 1024; 676 return 0; 677 err_free_db: 678 tn40_tx_db_close(&priv->txdb); 679 err_free_txf: 680 tn40_fifo_free(priv, &priv->txf_fifo0.m); 681 err_free_txd: 682 tn40_fifo_free(priv, &priv->txd_fifo0.m); 683 return -ENOMEM; 684 } 685 686 /** 687 * tn40_tx_space - Calculate the available space in the TX fifo. 688 * @priv: NIC private structure 689 * 690 * Return: available space in TX fifo in bytes 691 */ 692 static int tn40_tx_space(struct tn40_priv *priv) 693 { 694 struct tn40_txd_fifo *f = &priv->txd_fifo0; 695 int fsize; 696 697 f->m.rptr = tn40_read_reg(priv, f->m.reg_rptr) & TN40_TXF_WPTR_WR_PTR; 698 fsize = f->m.rptr - f->m.wptr; 699 if (fsize <= 0) 700 fsize = f->m.memsz + fsize; 701 return fsize; 702 } 703 704 #define TN40_TXD_FULL_CHECKSUM 7 705 706 static netdev_tx_t tn40_start_xmit(struct sk_buff *skb, struct net_device *ndev) 707 { 708 struct tn40_priv *priv = netdev_priv(ndev); 709 struct tn40_txd_fifo *f = &priv->txd_fifo0; 710 int txd_checksum = TN40_TXD_FULL_CHECKSUM; 711 struct tn40_txd_desc *txdd; 712 int nr_frags, len, err; 713 unsigned int pkt_len; 714 int txd_vlan_id = 0; 715 int txd_lgsnd = 0; 716 int txd_vtag = 0; 717 int txd_mss = 0; 718 719 /* Build tx descriptor */ 720 txdd = (struct tn40_txd_desc *)(f->m.va + f->m.wptr); 721 err = tn40_tx_map_skb(priv, skb, txdd, &pkt_len); 722 if (err) { 723 u64_stats_update_begin(&priv->syncp); 724 priv->stats.tx_dropped++; 725 u64_stats_update_end(&priv->syncp); 726 dev_kfree_skb(skb); 727 return NETDEV_TX_OK; 728 } 729 nr_frags = skb_shinfo(skb)->nr_frags; 730 if (unlikely(skb->ip_summed != CHECKSUM_PARTIAL)) 731 txd_checksum = 0; 732 733 if (skb_shinfo(skb)->gso_size) { 734 txd_mss = skb_shinfo(skb)->gso_size; 735 txd_lgsnd = 1; 736 netdev_dbg(priv->ndev, "skb %p pkt len %d gso size = %d\n", skb, 737 pkt_len, txd_mss); 738 } 739 if (skb_vlan_tag_present(skb)) { 740 /* Don't cut VLAN ID to 12 bits */ 741 txd_vlan_id = skb_vlan_tag_get(skb); 742 txd_vtag = 1; 743 } 744 txdd->va_hi = 0; 745 txdd->va_lo = 0; 746 txdd->length = cpu_to_le16(pkt_len); 747 txdd->mss = cpu_to_le16(txd_mss); 748 txdd->txd_val1 = 749 cpu_to_le32(TN40_TXD_W1_VAL 750 (tn40_txd_sizes[nr_frags].qwords, txd_checksum, 751 txd_vtag, txd_lgsnd, txd_vlan_id)); 752 netdev_dbg(priv->ndev, "=== w1 qwords[%d] %d =====\n", nr_frags, 753 tn40_txd_sizes[nr_frags].qwords); 754 netdev_dbg(priv->ndev, "=== TxD desc =====================\n"); 755 netdev_dbg(priv->ndev, "=== w1: 0x%x ================\n", 756 txdd->txd_val1); 757 netdev_dbg(priv->ndev, "=== w2: mss 0x%x len 0x%x\n", txdd->mss, 758 txdd->length); 759 /* SHORT_PKT_FIX */ 760 if (pkt_len < TN40_SHORT_PACKET_SIZE) { 761 struct tn40_pbl *pbl = &txdd->pbl[++nr_frags]; 762 763 txdd->length = cpu_to_le16(TN40_SHORT_PACKET_SIZE); 764 txdd->txd_val1 = 765 cpu_to_le32(TN40_TXD_W1_VAL 766 (tn40_txd_sizes[nr_frags].qwords, 767 txd_checksum, txd_vtag, txd_lgsnd, 768 txd_vlan_id)); 769 pbl->len = cpu_to_le32(TN40_SHORT_PACKET_SIZE - pkt_len); 770 pbl->pa_lo = cpu_to_le32(lower_32_bits(priv->b0_dma)); 771 pbl->pa_hi = cpu_to_le32(upper_32_bits(priv->b0_dma)); 772 netdev_dbg(priv->ndev, "=== SHORT_PKT_FIX ==============\n"); 773 netdev_dbg(priv->ndev, "=== nr_frags : %d ==============\n", 774 nr_frags); 775 } 776 777 /* Increment TXD write pointer. In case of fifo wrapping copy 778 * reminder of the descriptor to the beginning. 779 */ 780 f->m.wptr += tn40_txd_sizes[nr_frags].bytes; 781 len = f->m.wptr - f->m.memsz; 782 if (unlikely(len >= 0)) { 783 f->m.wptr = len; 784 if (len > 0) 785 memcpy(f->m.va, f->m.va + f->m.memsz, len); 786 } 787 /* Force memory writes to complete before letting the HW know 788 * there are new descriptors to fetch. 789 */ 790 wmb(); 791 792 priv->tx_level -= tn40_txd_sizes[nr_frags].bytes; 793 if (priv->tx_level > priv->tx_update_mark) { 794 tn40_write_reg(priv, f->m.reg_wptr, 795 f->m.wptr & TN40_TXF_WPTR_WR_PTR); 796 } else { 797 if (priv->tx_noupd++ > TN40_NO_UPD_PACKETS) { 798 priv->tx_noupd = 0; 799 tn40_write_reg(priv, f->m.reg_wptr, 800 f->m.wptr & TN40_TXF_WPTR_WR_PTR); 801 } 802 } 803 804 u64_stats_update_begin(&priv->syncp); 805 priv->stats.tx_packets++; 806 priv->stats.tx_bytes += pkt_len; 807 u64_stats_update_end(&priv->syncp); 808 if (priv->tx_level < TN40_MIN_TX_LEVEL) { 809 netdev_dbg(priv->ndev, "TX Q STOP level %d\n", priv->tx_level); 810 netif_stop_queue(ndev); 811 } 812 813 return NETDEV_TX_OK; 814 } 815 816 static void tn40_tx_cleanup(struct tn40_priv *priv) 817 { 818 struct tn40_txf_fifo *f = &priv->txf_fifo0; 819 struct tn40_txdb *db = &priv->txdb; 820 int tx_level = 0; 821 822 f->m.wptr = tn40_read_reg(priv, f->m.reg_wptr) & TN40_TXF_WPTR_MASK; 823 824 netif_tx_lock(priv->ndev); 825 while (f->m.wptr != f->m.rptr) { 826 f->m.rptr += TN40_TXF_DESC_SZ; 827 f->m.rptr &= f->m.size_mask; 828 /* Unmap all fragments */ 829 /* First has to come tx_maps containing DMA */ 830 do { 831 dma_addr_t addr = db->rptr->addr.dma; 832 size_t size = db->rptr->len; 833 834 netif_tx_unlock(priv->ndev); 835 dma_unmap_page(&priv->pdev->dev, addr, 836 size, DMA_TO_DEVICE); 837 netif_tx_lock(priv->ndev); 838 tn40_tx_db_inc_rptr(db); 839 } while (db->rptr->len > 0); 840 tx_level -= db->rptr->len; /* '-' Because the len is negative */ 841 842 /* Now should come skb pointer - free it */ 843 dev_kfree_skb_any(db->rptr->addr.skb); 844 netdev_dbg(priv->ndev, "dev_kfree_skb_any %p %d\n", 845 db->rptr->addr.skb, -db->rptr->len); 846 tn40_tx_db_inc_rptr(db); 847 } 848 849 /* Let the HW know which TXF descriptors were cleaned */ 850 tn40_write_reg(priv, f->m.reg_rptr, f->m.rptr & TN40_TXF_WPTR_WR_PTR); 851 852 /* We reclaimed resources, so in case the Q is stopped by xmit 853 * callback, we resume the transmission and use tx_lock to 854 * synchronize with xmit. 855 */ 856 priv->tx_level += tx_level; 857 if (priv->tx_noupd) { 858 priv->tx_noupd = 0; 859 tn40_write_reg(priv, priv->txd_fifo0.m.reg_wptr, 860 priv->txd_fifo0.m.wptr & TN40_TXF_WPTR_WR_PTR); 861 } 862 if (unlikely(netif_queue_stopped(priv->ndev) && 863 netif_carrier_ok(priv->ndev) && 864 (priv->tx_level >= TN40_MAX_TX_LEVEL / 2))) { 865 netdev_dbg(priv->ndev, "TX Q WAKE level %d\n", priv->tx_level); 866 netif_wake_queue(priv->ndev); 867 } 868 netif_tx_unlock(priv->ndev); 869 } 870 871 static void tn40_tx_free_skbs(struct tn40_priv *priv) 872 { 873 struct tn40_txdb *db = &priv->txdb; 874 875 while (db->rptr != db->wptr) { 876 if (likely(db->rptr->len)) 877 dma_unmap_page(&priv->pdev->dev, db->rptr->addr.dma, 878 db->rptr->len, DMA_TO_DEVICE); 879 else 880 dev_kfree_skb(db->rptr->addr.skb); 881 tn40_tx_db_inc_rptr(db); 882 } 883 } 884 885 static void tn40_destroy_tx_ring(struct tn40_priv *priv) 886 { 887 tn40_tx_free_skbs(priv); 888 tn40_fifo_free(priv, &priv->txd_fifo0.m); 889 tn40_fifo_free(priv, &priv->txf_fifo0.m); 890 tn40_tx_db_close(&priv->txdb); 891 /* SHORT_PKT_FIX */ 892 if (priv->b0_len) { 893 dma_free_coherent(&priv->pdev->dev, priv->b0_len, priv->b0_va, 894 priv->b0_dma); 895 priv->b0_len = 0; 896 } 897 } 898 899 /** 900 * tn40_tx_push_desc - Push a descriptor to TxD fifo. 901 * 902 * @priv: NIC private structure 903 * @data: desc's data 904 * @size: desc's size 905 * 906 * This function pushes desc to TxD fifo and overlaps it if needed. 907 * 908 * This function does not check for available space, nor does it check 909 * that the data size is smaller than the fifo size. Checking for 910 * space is the responsibility of the caller. 911 */ 912 static void tn40_tx_push_desc(struct tn40_priv *priv, void *data, int size) 913 { 914 struct tn40_txd_fifo *f = &priv->txd_fifo0; 915 int i = f->m.memsz - f->m.wptr; 916 917 if (size == 0) 918 return; 919 920 if (i > size) { 921 memcpy(f->m.va + f->m.wptr, data, size); 922 f->m.wptr += size; 923 } else { 924 memcpy(f->m.va + f->m.wptr, data, i); 925 f->m.wptr = size - i; 926 memcpy(f->m.va, data + i, f->m.wptr); 927 } 928 tn40_write_reg(priv, f->m.reg_wptr, f->m.wptr & TN40_TXF_WPTR_WR_PTR); 929 } 930 931 /** 932 * tn40_tx_push_desc_safe - push descriptor to TxD fifo in a safe way. 933 * 934 * @priv: NIC private structure 935 * @data: descriptor data 936 * @size: descriptor size 937 * 938 * This function does check for available space and, if necessary, 939 * waits for the NIC to read existing data before writing new data. 940 */ 941 static void tn40_tx_push_desc_safe(struct tn40_priv *priv, void *data, int size) 942 { 943 int timer = 0; 944 945 while (size > 0) { 946 /* We subtract 8 because when the fifo is full rptr == 947 * wptr, which also means that fifo is empty, we can 948 * understand the difference, but could the HW do the 949 * same ??? 950 */ 951 int avail = tn40_tx_space(priv) - 8; 952 953 if (avail <= 0) { 954 if (timer++ > 300) /* Prevent endless loop */ 955 break; 956 /* Give the HW a chance to clean the fifo */ 957 usleep_range(50, 60); 958 continue; 959 } 960 avail = min(avail, size); 961 netdev_dbg(priv->ndev, 962 "about to push %d bytes starting %p size %d\n", 963 avail, data, size); 964 tn40_tx_push_desc(priv, data, avail); 965 size -= avail; 966 data += avail; 967 } 968 } 969 970 int tn40_set_link_speed(struct tn40_priv *priv, u32 speed) 971 { 972 u32 val; 973 int i; 974 975 netdev_dbg(priv->ndev, "speed %d\n", speed); 976 switch (speed) { 977 case SPEED_10000: 978 case SPEED_5000: 979 case SPEED_2500: 980 netdev_dbg(priv->ndev, "link_speed %d\n", speed); 981 982 tn40_write_reg(priv, 0x1010, 0x217); /*ETHSD.REFCLK_CONF */ 983 tn40_write_reg(priv, 0x104c, 0x4c); /*ETHSD.L0_RX_PCNT */ 984 tn40_write_reg(priv, 0x1050, 0x4c); /*ETHSD.L1_RX_PCNT */ 985 tn40_write_reg(priv, 0x1054, 0x4c); /*ETHSD.L2_RX_PCNT */ 986 tn40_write_reg(priv, 0x1058, 0x4c); /*ETHSD.L3_RX_PCNT */ 987 tn40_write_reg(priv, 0x102c, 0x434); /*ETHSD.L0_TX_PCNT */ 988 tn40_write_reg(priv, 0x1030, 0x434); /*ETHSD.L1_TX_PCNT */ 989 tn40_write_reg(priv, 0x1034, 0x434); /*ETHSD.L2_TX_PCNT */ 990 tn40_write_reg(priv, 0x1038, 0x434); /*ETHSD.L3_TX_PCNT */ 991 tn40_write_reg(priv, 0x6300, 0x0400); /*MAC.PCS_CTRL */ 992 993 tn40_write_reg(priv, 0x1018, 0x00); /*Mike2 */ 994 udelay(5); 995 tn40_write_reg(priv, 0x1018, 0x04); /*Mike2 */ 996 udelay(5); 997 tn40_write_reg(priv, 0x1018, 0x06); /*Mike2 */ 998 udelay(5); 999 /*MikeFix1 */ 1000 /*L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 */ 1001 tn40_write_reg(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */ 1002 tn40_write_reg(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */ 1003 tn40_write_reg(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */ 1004 tn40_write_reg(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */ 1005 tn40_write_reg(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT */ 1006 for (i = 1000; i; i--) { 1007 usleep_range(50, 60); 1008 /*ETHSD.INIT_STAT */ 1009 val = tn40_read_reg(priv, 0x1014); 1010 if (val & (1 << 9)) { 1011 /*ETHSD.INIT_STAT */ 1012 tn40_write_reg(priv, 0x1014, 0x3); 1013 /*ETHSD.INIT_STAT */ 1014 val = tn40_read_reg(priv, 0x1014); 1015 1016 break; 1017 } 1018 } 1019 if (!i) 1020 netdev_err(priv->ndev, "MAC init timeout!\n"); 1021 1022 tn40_write_reg(priv, 0x6350, 0x0); /*MAC.PCS_IF_MODE */ 1023 tn40_write_reg(priv, TN40_REG_CTRLST, 0xC13); /*0x93//0x13 */ 1024 tn40_write_reg(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */ 1025 usleep_range(2000, 2100); 1026 1027 tn40_write_reg(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */ 1028 break; 1029 1030 case SPEED_1000: 1031 case SPEED_100: 1032 tn40_write_reg(priv, 0x1010, 0x613); /*ETHSD.REFCLK_CONF */ 1033 tn40_write_reg(priv, 0x104c, 0x4d); /*ETHSD.L0_RX_PCNT */ 1034 tn40_write_reg(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */ 1035 tn40_write_reg(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */ 1036 tn40_write_reg(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */ 1037 tn40_write_reg(priv, 0x102c, 0x35); /*ETHSD.L0_TX_PCNT */ 1038 tn40_write_reg(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */ 1039 tn40_write_reg(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */ 1040 tn40_write_reg(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */ 1041 tn40_write_reg(priv, 0x6300, 0x01140); /*MAC.PCS_CTRL */ 1042 1043 tn40_write_reg(priv, 0x1014, 0x043); /*ETHSD.INIT_STAT */ 1044 for (i = 1000; i; i--) { 1045 usleep_range(50, 60); 1046 val = tn40_read_reg(priv, 0x1014); /*ETHSD.INIT_STAT */ 1047 if (val & (1 << 9)) { 1048 /*ETHSD.INIT_STAT */ 1049 tn40_write_reg(priv, 0x1014, 0x3); 1050 /*ETHSD.INIT_STAT */ 1051 val = tn40_read_reg(priv, 0x1014); 1052 1053 break; 1054 } 1055 } 1056 if (!i) 1057 netdev_err(priv->ndev, "MAC init timeout!\n"); 1058 1059 tn40_write_reg(priv, 0x6350, 0x2b); /*MAC.PCS_IF_MODE 1g */ 1060 tn40_write_reg(priv, 0x6310, 0x9801); /*MAC.PCS_DEV_AB */ 1061 1062 tn40_write_reg(priv, 0x6314, 0x1); /*MAC.PCS_PART_AB */ 1063 tn40_write_reg(priv, 0x6348, 0xc8); /*MAC.PCS_LINK_LO */ 1064 tn40_write_reg(priv, 0x634c, 0xc8); /*MAC.PCS_LINK_HI */ 1065 usleep_range(50, 60); 1066 tn40_write_reg(priv, TN40_REG_CTRLST, 0xC13); /*0x93//0x13 */ 1067 tn40_write_reg(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */ 1068 usleep_range(2000, 2100); 1069 1070 tn40_write_reg(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */ 1071 tn40_write_reg(priv, 0x6300, 0x1140); /*MAC.PCS_CTRL */ 1072 break; 1073 1074 case 0: /* Link down */ 1075 tn40_write_reg(priv, 0x104c, 0x0); /*ETHSD.L0_RX_PCNT */ 1076 tn40_write_reg(priv, 0x1050, 0x0); /*ETHSD.L1_RX_PCNT */ 1077 tn40_write_reg(priv, 0x1054, 0x0); /*ETHSD.L2_RX_PCNT */ 1078 tn40_write_reg(priv, 0x1058, 0x0); /*ETHSD.L3_RX_PCNT */ 1079 tn40_write_reg(priv, 0x102c, 0x0); /*ETHSD.L0_TX_PCNT */ 1080 tn40_write_reg(priv, 0x1030, 0x0); /*ETHSD.L1_TX_PCNT */ 1081 tn40_write_reg(priv, 0x1034, 0x0); /*ETHSD.L2_TX_PCNT */ 1082 tn40_write_reg(priv, 0x1038, 0x0); /*ETHSD.L3_TX_PCNT */ 1083 1084 tn40_write_reg(priv, TN40_REG_CTRLST, 0x800); 1085 tn40_write_reg(priv, 0x111c, 0x7ff); /*MAC.MAC_RST_CNT */ 1086 usleep_range(2000, 2100); 1087 1088 tn40_write_reg(priv, 0x111c, 0x0); /*MAC.MAC_RST_CNT */ 1089 break; 1090 1091 default: 1092 netdev_err(priv->ndev, 1093 "Link speed was not identified yet (%d)\n", speed); 1094 speed = 0; 1095 break; 1096 } 1097 return speed; 1098 } 1099 1100 static void tn40_link_changed(struct tn40_priv *priv) 1101 { 1102 u32 link = tn40_read_reg(priv, 1103 TN40_REG_MAC_LNK_STAT) & TN40_MAC_LINK_STAT; 1104 1105 netdev_dbg(priv->ndev, "link changed %u\n", link); 1106 } 1107 1108 static void tn40_isr_extra(struct tn40_priv *priv, u32 isr) 1109 { 1110 if (isr & (TN40_IR_LNKCHG0 | TN40_IR_LNKCHG1 | TN40_IR_TMR0)) { 1111 netdev_dbg(priv->ndev, "isr = 0x%x\n", isr); 1112 tn40_link_changed(priv); 1113 } 1114 } 1115 1116 static irqreturn_t tn40_isr_napi(int irq, void *dev) 1117 { 1118 struct tn40_priv *priv = netdev_priv((struct net_device *)dev); 1119 u32 isr; 1120 1121 isr = tn40_read_reg(priv, TN40_REG_ISR_MSK0); 1122 1123 if (unlikely(!isr)) { 1124 tn40_enable_interrupts(priv); 1125 return IRQ_NONE; /* Not our interrupt */ 1126 } 1127 1128 if (isr & TN40_IR_EXTRA) 1129 tn40_isr_extra(priv, isr); 1130 1131 if (isr & (TN40_IR_RX_DESC_0 | TN40_IR_TX_FREE_0 | TN40_IR_TMR1)) { 1132 if (likely(napi_schedule_prep(&priv->napi))) { 1133 __napi_schedule(&priv->napi); 1134 return IRQ_HANDLED; 1135 } 1136 /* We get here if an interrupt has slept into the 1137 * small time window between these lines in 1138 * tn40_poll: tn40_enable_interrupts(priv); return 0; 1139 * 1140 * Currently interrupts are disabled (since we read 1141 * the ISR register) and we have failed to register 1142 * the next poll. So we read the regs to trigger the 1143 * chip and allow further interrupts. 1144 */ 1145 tn40_read_reg(priv, TN40_REG_TXF_WPTR_0); 1146 tn40_read_reg(priv, TN40_REG_RXD_WPTR_0); 1147 } 1148 1149 tn40_enable_interrupts(priv); 1150 return IRQ_HANDLED; 1151 } 1152 1153 static int tn40_poll(struct napi_struct *napi, int budget) 1154 { 1155 struct tn40_priv *priv = container_of(napi, struct tn40_priv, napi); 1156 int work_done; 1157 1158 tn40_tx_cleanup(priv); 1159 1160 if (!budget) 1161 return 0; 1162 1163 work_done = tn40_rx_receive(priv, budget); 1164 if (work_done == budget) 1165 return budget; 1166 1167 if (napi_complete_done(napi, work_done)) 1168 tn40_enable_interrupts(priv); 1169 return work_done; 1170 } 1171 1172 static int tn40_fw_load(struct tn40_priv *priv) 1173 { 1174 const struct firmware *fw = NULL; 1175 int master, ret; 1176 u32 val; 1177 1178 ret = request_firmware(&fw, TN40_FIRMWARE_NAME, &priv->pdev->dev); 1179 if (ret) 1180 return ret; 1181 1182 master = tn40_read_reg(priv, TN40_REG_INIT_SEMAPHORE); 1183 if (!tn40_read_reg(priv, TN40_REG_INIT_STATUS) && master) { 1184 netdev_dbg(priv->ndev, "Loading FW...\n"); 1185 tn40_tx_push_desc_safe(priv, (void *)fw->data, fw->size); 1186 msleep(100); 1187 } 1188 ret = read_poll_timeout(tn40_read_reg, val, val, 2000, 400000, false, 1189 priv, TN40_REG_INIT_STATUS); 1190 if (master) 1191 tn40_write_reg(priv, TN40_REG_INIT_SEMAPHORE, 1); 1192 1193 if (ret) { 1194 netdev_err(priv->ndev, "firmware loading failed\n"); 1195 netdev_dbg(priv->ndev, "VPC: 0x%x VIC: 0x%x STATUS: 0x%xd\n", 1196 tn40_read_reg(priv, TN40_REG_VPC), 1197 tn40_read_reg(priv, TN40_REG_VIC), 1198 tn40_read_reg(priv, TN40_REG_INIT_STATUS)); 1199 ret = -EIO; 1200 } else { 1201 netdev_dbg(priv->ndev, "firmware loading success\n"); 1202 } 1203 release_firmware(fw); 1204 return ret; 1205 } 1206 1207 static void tn40_restore_mac(struct net_device *ndev, struct tn40_priv *priv) 1208 { 1209 u32 val; 1210 1211 netdev_dbg(priv->ndev, "mac0 =%x mac1 =%x mac2 =%x\n", 1212 tn40_read_reg(priv, TN40_REG_UNC_MAC0_A), 1213 tn40_read_reg(priv, TN40_REG_UNC_MAC1_A), 1214 tn40_read_reg(priv, TN40_REG_UNC_MAC2_A)); 1215 1216 val = (ndev->dev_addr[0] << 8) | (ndev->dev_addr[1]); 1217 tn40_write_reg(priv, TN40_REG_UNC_MAC2_A, val); 1218 val = (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]); 1219 tn40_write_reg(priv, TN40_REG_UNC_MAC1_A, val); 1220 val = (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]); 1221 tn40_write_reg(priv, TN40_REG_UNC_MAC0_A, val); 1222 1223 /* More then IP MAC address */ 1224 tn40_write_reg(priv, TN40_REG_MAC_ADDR_0, 1225 (ndev->dev_addr[3] << 24) | (ndev->dev_addr[2] << 16) | 1226 (ndev->dev_addr[1] << 8) | (ndev->dev_addr[0])); 1227 tn40_write_reg(priv, TN40_REG_MAC_ADDR_1, 1228 (ndev->dev_addr[5] << 8) | (ndev->dev_addr[4])); 1229 1230 netdev_dbg(priv->ndev, "mac0 =%x mac1 =%x mac2 =%x\n", 1231 tn40_read_reg(priv, TN40_REG_UNC_MAC0_A), 1232 tn40_read_reg(priv, TN40_REG_UNC_MAC1_A), 1233 tn40_read_reg(priv, TN40_REG_UNC_MAC2_A)); 1234 } 1235 1236 static void tn40_hw_start(struct tn40_priv *priv) 1237 { 1238 tn40_write_reg(priv, TN40_REG_FRM_LENGTH, 0X3FE0); 1239 tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, 0X10fd); 1240 /*MikeFix1 */ 1241 /*L0: 0x103c , L1: 0x1040 , L2: 0x1044 , L3: 0x1048 =0x81644 */ 1242 tn40_write_reg(priv, 0x103c, 0x81644); /*ETHSD.L0_TX_DCNT */ 1243 tn40_write_reg(priv, 0x1040, 0x81644); /*ETHSD.L1_TX_DCNT */ 1244 tn40_write_reg(priv, 0x1044, 0x81644); /*ETHSD.L2_TX_DCNT */ 1245 tn40_write_reg(priv, 0x1048, 0x81644); /*ETHSD.L3_TX_DCNT */ 1246 tn40_write_reg(priv, TN40_REG_RX_FIFO_SECTION, 0x10); 1247 tn40_write_reg(priv, TN40_REG_TX_FIFO_SECTION, 0xE00010); 1248 tn40_write_reg(priv, TN40_REG_RX_FULLNESS, 0); 1249 tn40_write_reg(priv, TN40_REG_TX_FULLNESS, 0); 1250 1251 tn40_write_reg(priv, TN40_REG_VGLB, 0); 1252 tn40_write_reg(priv, TN40_REG_MAX_FRAME_A, 1253 priv->rxf_fifo0.m.pktsz & TN40_MAX_FRAME_AB_VAL); 1254 tn40_write_reg(priv, TN40_REG_RDINTCM0, priv->rdintcm); 1255 tn40_write_reg(priv, TN40_REG_RDINTCM2, 0); 1256 1257 /* old val = 0x300064 */ 1258 tn40_write_reg(priv, TN40_REG_TDINTCM0, priv->tdintcm); 1259 1260 /* Enable timer interrupt once in 2 secs. */ 1261 tn40_restore_mac(priv->ndev, priv); 1262 1263 /* Pause frame */ 1264 tn40_write_reg(priv, 0x12E0, 0x28); 1265 tn40_write_reg(priv, TN40_REG_PAUSE_QUANT, 0xFFFF); 1266 tn40_write_reg(priv, 0x6064, 0xF); 1267 1268 tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, 1269 TN40_GMAC_RX_FILTER_OSEN | TN40_GMAC_RX_FILTER_TXFC | 1270 TN40_GMAC_RX_FILTER_AM | TN40_GMAC_RX_FILTER_AB); 1271 1272 tn40_enable_interrupts(priv); 1273 } 1274 1275 static int tn40_hw_reset(struct tn40_priv *priv) 1276 { 1277 u32 val; 1278 1279 /* Reset sequences: read, write 1, read, write 0 */ 1280 val = tn40_read_reg(priv, TN40_REG_CLKPLL); 1281 tn40_write_reg(priv, TN40_REG_CLKPLL, (val | TN40_CLKPLL_SFTRST) + 0x8); 1282 usleep_range(50, 60); 1283 val = tn40_read_reg(priv, TN40_REG_CLKPLL); 1284 tn40_write_reg(priv, TN40_REG_CLKPLL, val & ~TN40_CLKPLL_SFTRST); 1285 1286 /* Check that the PLLs are locked and reset ended */ 1287 val = read_poll_timeout(tn40_read_reg, val, 1288 (val & TN40_CLKPLL_LKD) == TN40_CLKPLL_LKD, 1289 10000, 700000, false, priv, TN40_REG_CLKPLL); 1290 if (val) 1291 return -EIO; 1292 1293 usleep_range(50, 60); 1294 /* Do any PCI-E read transaction */ 1295 tn40_read_reg(priv, TN40_REG_RXD_CFG0_0); 1296 return 0; 1297 } 1298 1299 static void tn40_sw_reset(struct tn40_priv *priv) 1300 { 1301 int i, ret; 1302 u32 val; 1303 1304 /* 1. load MAC (obsolete) */ 1305 /* 2. disable Rx (and Tx) */ 1306 tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, 0); 1307 msleep(100); 1308 /* 3. Disable port */ 1309 tn40_write_reg(priv, TN40_REG_DIS_PORT, 1); 1310 /* 4. Disable queue */ 1311 tn40_write_reg(priv, TN40_REG_DIS_QU, 1); 1312 /* 5. Wait until hw is disabled */ 1313 ret = read_poll_timeout(tn40_read_reg, val, val & 1, 10000, 500000, 1314 false, priv, TN40_REG_RST_PORT); 1315 if (ret) 1316 netdev_err(priv->ndev, "SW reset timeout. continuing anyway\n"); 1317 1318 /* 6. Disable interrupts */ 1319 tn40_write_reg(priv, TN40_REG_RDINTCM0, 0); 1320 tn40_write_reg(priv, TN40_REG_TDINTCM0, 0); 1321 tn40_write_reg(priv, TN40_REG_IMR, 0); 1322 tn40_read_reg(priv, TN40_REG_ISR); 1323 1324 /* 7. Reset queue */ 1325 tn40_write_reg(priv, TN40_REG_RST_QU, 1); 1326 /* 8. Reset port */ 1327 tn40_write_reg(priv, TN40_REG_RST_PORT, 1); 1328 /* 9. Zero all read and write pointers */ 1329 for (i = TN40_REG_TXD_WPTR_0; i <= TN40_REG_TXF_RPTR_3; i += 0x10) 1330 tn40_write_reg(priv, i, 0); 1331 /* 10. Unset port disable */ 1332 tn40_write_reg(priv, TN40_REG_DIS_PORT, 0); 1333 /* 11. Unset queue disable */ 1334 tn40_write_reg(priv, TN40_REG_DIS_QU, 0); 1335 /* 12. Unset queue reset */ 1336 tn40_write_reg(priv, TN40_REG_RST_QU, 0); 1337 /* 13. Unset port reset */ 1338 tn40_write_reg(priv, TN40_REG_RST_PORT, 0); 1339 /* 14. Enable Rx */ 1340 /* Skipped. will be done later */ 1341 } 1342 1343 static int tn40_start(struct tn40_priv *priv) 1344 { 1345 int ret; 1346 1347 ret = tn40_create_tx_ring(priv); 1348 if (ret) { 1349 netdev_err(priv->ndev, "failed to tx init %d\n", ret); 1350 return ret; 1351 } 1352 1353 ret = tn40_create_rx_ring(priv); 1354 if (ret) { 1355 netdev_err(priv->ndev, "failed to rx init %d\n", ret); 1356 goto err_tx_ring; 1357 } 1358 1359 tn40_rx_alloc_buffers(priv); 1360 if (tn40_rxdb_available(priv->rxdb0) != 1) { 1361 ret = -ENOMEM; 1362 netdev_err(priv->ndev, "failed to allocate rx buffers\n"); 1363 goto err_rx_ring; 1364 } 1365 1366 ret = request_irq(priv->pdev->irq, &tn40_isr_napi, IRQF_SHARED, 1367 priv->ndev->name, priv->ndev); 1368 if (ret) { 1369 netdev_err(priv->ndev, "failed to request irq %d\n", ret); 1370 goto err_rx_ring; 1371 } 1372 1373 tn40_hw_start(priv); 1374 return 0; 1375 err_rx_ring: 1376 tn40_destroy_rx_ring(priv); 1377 err_tx_ring: 1378 tn40_destroy_tx_ring(priv); 1379 return ret; 1380 } 1381 1382 static void tn40_stop(struct tn40_priv *priv) 1383 { 1384 tn40_disable_interrupts(priv); 1385 free_irq(priv->pdev->irq, priv->ndev); 1386 tn40_sw_reset(priv); 1387 tn40_destroy_tx_ring(priv); 1388 tn40_destroy_rx_ring(priv); 1389 } 1390 1391 static int tn40_close(struct net_device *ndev) 1392 { 1393 struct tn40_priv *priv = netdev_priv(ndev); 1394 1395 phylink_stop(priv->phylink); 1396 phylink_disconnect_phy(priv->phylink); 1397 1398 napi_disable(&priv->napi); 1399 netif_napi_del(&priv->napi); 1400 tn40_stop(priv); 1401 return 0; 1402 } 1403 1404 static int tn40_open(struct net_device *dev) 1405 { 1406 struct tn40_priv *priv = netdev_priv(dev); 1407 int ret; 1408 1409 ret = phylink_connect_phy(priv->phylink, priv->phydev); 1410 if (ret) { 1411 netdev_err(dev, "failed to connect to phy %d\n", ret); 1412 return ret; 1413 } 1414 tn40_sw_reset(priv); 1415 ret = tn40_start(priv); 1416 if (ret) { 1417 phylink_disconnect_phy(priv->phylink); 1418 netdev_err(dev, "failed to start %d\n", ret); 1419 return ret; 1420 } 1421 napi_enable(&priv->napi); 1422 phylink_start(priv->phylink); 1423 netif_start_queue(priv->ndev); 1424 return 0; 1425 } 1426 1427 static void __tn40_vlan_rx_vid(struct net_device *ndev, uint16_t vid, 1428 int enable) 1429 { 1430 struct tn40_priv *priv = netdev_priv(ndev); 1431 u32 reg, bit, val; 1432 1433 netdev_dbg(priv->ndev, "vid =%d value =%d\n", (int)vid, enable); 1434 reg = TN40_REG_VLAN_0 + (vid / 32) * 4; 1435 bit = 1 << vid % 32; 1436 val = tn40_read_reg(priv, reg); 1437 netdev_dbg(priv->ndev, "reg =%x, val =%x, bit =%d\n", reg, val, bit); 1438 if (enable) 1439 val |= bit; 1440 else 1441 val &= ~bit; 1442 netdev_dbg(priv->ndev, "new val %x\n", val); 1443 tn40_write_reg(priv, reg, val); 1444 } 1445 1446 static int tn40_vlan_rx_add_vid(struct net_device *ndev, 1447 __always_unused __be16 proto, u16 vid) 1448 { 1449 __tn40_vlan_rx_vid(ndev, vid, 1); 1450 return 0; 1451 } 1452 1453 static int tn40_vlan_rx_kill_vid(struct net_device *ndev, 1454 __always_unused __be16 proto, u16 vid) 1455 { 1456 __tn40_vlan_rx_vid(ndev, vid, 0); 1457 return 0; 1458 } 1459 1460 static void tn40_setmulti(struct net_device *ndev) 1461 { 1462 u32 rxf_val = TN40_GMAC_RX_FILTER_AM | TN40_GMAC_RX_FILTER_AB | 1463 TN40_GMAC_RX_FILTER_OSEN | TN40_GMAC_RX_FILTER_TXFC; 1464 struct tn40_priv *priv = netdev_priv(ndev); 1465 int i; 1466 1467 /* IMF - imperfect (hash) rx multicast filter */ 1468 /* PMF - perfect rx multicast filter */ 1469 1470 /* FIXME: RXE(OFF) */ 1471 if (ndev->flags & IFF_PROMISC) { 1472 rxf_val |= TN40_GMAC_RX_FILTER_PRM; 1473 } else if (ndev->flags & IFF_ALLMULTI) { 1474 /* set IMF to accept all multicast frames */ 1475 for (i = 0; i < TN40_MAC_MCST_HASH_NUM; i++) 1476 tn40_write_reg(priv, 1477 TN40_REG_RX_MCST_HASH0 + i * 4, ~0); 1478 } else if (netdev_mc_count(ndev)) { 1479 struct netdev_hw_addr *mclist; 1480 u32 reg, val; 1481 u8 hash; 1482 1483 /* Set IMF to deny all multicast frames */ 1484 for (i = 0; i < TN40_MAC_MCST_HASH_NUM; i++) 1485 tn40_write_reg(priv, 1486 TN40_REG_RX_MCST_HASH0 + i * 4, 0); 1487 1488 /* Set PMF to deny all multicast frames */ 1489 for (i = 0; i < TN40_MAC_MCST_NUM; i++) { 1490 tn40_write_reg(priv, 1491 TN40_REG_RX_MAC_MCST0 + i * 8, 0); 1492 tn40_write_reg(priv, 1493 TN40_REG_RX_MAC_MCST1 + i * 8, 0); 1494 } 1495 /* Use PMF to accept first MAC_MCST_NUM (15) addresses */ 1496 1497 /* TBD: Sort the addresses and write them in ascending 1498 * order into RX_MAC_MCST regs. we skip this phase now 1499 * and accept ALL multicast frames through IMF. Accept 1500 * the rest of addresses throw IMF. 1501 */ 1502 netdev_for_each_mc_addr(mclist, ndev) { 1503 hash = 0; 1504 for (i = 0; i < ETH_ALEN; i++) 1505 hash ^= mclist->addr[i]; 1506 1507 reg = TN40_REG_RX_MCST_HASH0 + ((hash >> 5) << 2); 1508 val = tn40_read_reg(priv, reg); 1509 val |= (1 << (hash % 32)); 1510 tn40_write_reg(priv, reg, val); 1511 } 1512 } else { 1513 rxf_val |= TN40_GMAC_RX_FILTER_AB; 1514 } 1515 tn40_write_reg(priv, TN40_REG_GMAC_RXF_A, rxf_val); 1516 /* Enable RX */ 1517 /* FIXME: RXE(ON) */ 1518 } 1519 1520 static int tn40_set_mac(struct net_device *ndev, void *p) 1521 { 1522 struct tn40_priv *priv = netdev_priv(ndev); 1523 struct sockaddr *addr = p; 1524 1525 eth_hw_addr_set(ndev, addr->sa_data); 1526 tn40_restore_mac(ndev, priv); 1527 return 0; 1528 } 1529 1530 static void tn40_mac_init(struct tn40_priv *priv) 1531 { 1532 u8 addr[ETH_ALEN]; 1533 u64 val; 1534 1535 val = (u64)tn40_read_reg(priv, TN40_REG_UNC_MAC0_A); 1536 val |= (u64)tn40_read_reg(priv, TN40_REG_UNC_MAC1_A) << 16; 1537 val |= (u64)tn40_read_reg(priv, TN40_REG_UNC_MAC2_A) << 32; 1538 1539 u64_to_ether_addr(val, addr); 1540 eth_hw_addr_set(priv->ndev, addr); 1541 } 1542 1543 static void tn40_get_stats(struct net_device *ndev, 1544 struct rtnl_link_stats64 *stats) 1545 { 1546 struct tn40_priv *priv = netdev_priv(ndev); 1547 unsigned int start; 1548 1549 do { 1550 start = u64_stats_fetch_begin(&priv->syncp); 1551 stats->tx_packets = priv->stats.tx_packets; 1552 stats->tx_bytes = priv->stats.tx_bytes; 1553 stats->tx_dropped = priv->stats.tx_dropped; 1554 1555 stats->rx_packets = priv->stats.rx_packets; 1556 stats->rx_bytes = priv->stats.rx_bytes; 1557 stats->rx_dropped = priv->stats.rx_dropped; 1558 stats->rx_errors = priv->stats.rx_errors; 1559 } while (u64_stats_fetch_retry(&priv->syncp, start)); 1560 } 1561 1562 static const struct net_device_ops tn40_netdev_ops = { 1563 .ndo_open = tn40_open, 1564 .ndo_stop = tn40_close, 1565 .ndo_start_xmit = tn40_start_xmit, 1566 .ndo_validate_addr = eth_validate_addr, 1567 .ndo_set_rx_mode = tn40_setmulti, 1568 .ndo_get_stats64 = tn40_get_stats, 1569 .ndo_set_mac_address = tn40_set_mac, 1570 .ndo_vlan_rx_add_vid = tn40_vlan_rx_add_vid, 1571 .ndo_vlan_rx_kill_vid = tn40_vlan_rx_kill_vid, 1572 }; 1573 1574 static int tn40_priv_init(struct tn40_priv *priv) 1575 { 1576 int ret; 1577 1578 tn40_set_link_speed(priv, 0); 1579 1580 /* Set GPIO[9:0] to output 0 */ 1581 tn40_write_reg(priv, 0x51E0, 0x30010006); /* GPIO_OE_ WR CMD */ 1582 tn40_write_reg(priv, 0x51F0, 0x0); /* GPIO_OE_ DATA */ 1583 tn40_write_reg(priv, TN40_REG_MDIO_CMD_STAT, 0x3ec8); 1584 1585 /* we use tx descriptors to load a firmware. */ 1586 ret = tn40_create_tx_ring(priv); 1587 if (ret) 1588 return ret; 1589 ret = tn40_fw_load(priv); 1590 tn40_destroy_tx_ring(priv); 1591 return ret; 1592 } 1593 1594 static struct net_device *tn40_netdev_alloc(struct pci_dev *pdev) 1595 { 1596 struct net_device *ndev; 1597 1598 ndev = devm_alloc_etherdev(&pdev->dev, sizeof(struct tn40_priv)); 1599 if (!ndev) 1600 return NULL; 1601 ndev->netdev_ops = &tn40_netdev_ops; 1602 ndev->tx_queue_len = TN40_NDEV_TXQ_LEN; 1603 ndev->mem_start = pci_resource_start(pdev, 0); 1604 ndev->mem_end = pci_resource_end(pdev, 0); 1605 ndev->min_mtu = ETH_ZLEN; 1606 ndev->max_mtu = TN40_MAX_MTU; 1607 1608 ndev->features = NETIF_F_IP_CSUM | 1609 NETIF_F_SG | 1610 NETIF_F_FRAGLIST | 1611 NETIF_F_TSO | NETIF_F_GRO | 1612 NETIF_F_RXCSUM | 1613 NETIF_F_RXHASH | 1614 NETIF_F_HW_VLAN_CTAG_TX | 1615 NETIF_F_HW_VLAN_CTAG_RX | 1616 NETIF_F_HW_VLAN_CTAG_FILTER; 1617 ndev->vlan_features = NETIF_F_IP_CSUM | 1618 NETIF_F_SG | 1619 NETIF_F_TSO | NETIF_F_GRO | NETIF_F_RXHASH; 1620 1621 if (dma_get_mask(&pdev->dev) == DMA_BIT_MASK(64)) { 1622 ndev->features |= NETIF_F_HIGHDMA; 1623 ndev->vlan_features |= NETIF_F_HIGHDMA; 1624 } 1625 ndev->hw_features |= ndev->features; 1626 1627 SET_NETDEV_DEV(ndev, &pdev->dev); 1628 netif_stop_queue(ndev); 1629 return ndev; 1630 } 1631 1632 static int tn40_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 1633 { 1634 struct net_device *ndev; 1635 struct tn40_priv *priv; 1636 unsigned int nvec = 1; 1637 void __iomem *regs; 1638 int ret; 1639 1640 ret = pci_enable_device(pdev); 1641 if (ret) 1642 return ret; 1643 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1644 if (ret) { 1645 dev_err(&pdev->dev, "failed to set DMA mask.\n"); 1646 goto err_disable_device; 1647 } 1648 1649 ret = pci_request_regions(pdev, TN40_DRV_NAME); 1650 if (ret) { 1651 dev_err(&pdev->dev, "failed to request PCI regions.\n"); 1652 goto err_disable_device; 1653 } 1654 1655 pci_set_master(pdev); 1656 1657 regs = pci_iomap(pdev, 0, TN40_REGS_SIZE); 1658 if (!regs) { 1659 ret = -EIO; 1660 dev_err(&pdev->dev, "failed to map PCI bar.\n"); 1661 goto err_free_regions; 1662 } 1663 1664 ndev = tn40_netdev_alloc(pdev); 1665 if (!ndev) { 1666 ret = -ENOMEM; 1667 dev_err(&pdev->dev, "failed to allocate netdev.\n"); 1668 goto err_iounmap; 1669 } 1670 1671 priv = netdev_priv(ndev); 1672 pci_set_drvdata(pdev, priv); 1673 netif_napi_add(ndev, &priv->napi, tn40_poll); 1674 1675 priv->regs = regs; 1676 priv->pdev = pdev; 1677 priv->ndev = ndev; 1678 /* Initialize fifo sizes. */ 1679 priv->txd_size = 3; 1680 priv->txf_size = 3; 1681 priv->rxd_size = 3; 1682 priv->rxf_size = 3; 1683 /* Initialize the initial coalescing registers. */ 1684 priv->rdintcm = TN40_INT_REG_VAL(0x20, 1, 4, 12); 1685 priv->tdintcm = TN40_INT_REG_VAL(0x20, 1, 0, 12); 1686 1687 ret = tn40_hw_reset(priv); 1688 if (ret) { 1689 dev_err(&pdev->dev, "failed to reset HW.\n"); 1690 goto err_unset_drvdata; 1691 } 1692 1693 ret = pci_alloc_irq_vectors(pdev, 1, nvec, PCI_IRQ_MSI); 1694 if (ret < 0) { 1695 dev_err(&pdev->dev, "failed to allocate irq.\n"); 1696 goto err_unset_drvdata; 1697 } 1698 1699 ret = tn40_mdiobus_init(priv); 1700 if (ret) { 1701 dev_err(&pdev->dev, "failed to initialize mdio bus.\n"); 1702 goto err_free_irq; 1703 } 1704 1705 priv->stats_flag = 1706 ((tn40_read_reg(priv, TN40_FPGA_VER) & 0xFFF) != 308); 1707 u64_stats_init(&priv->syncp); 1708 1709 priv->isr_mask = TN40_IR_RX_FREE_0 | TN40_IR_LNKCHG0 | TN40_IR_PSE | 1710 TN40_IR_TMR0 | TN40_IR_RX_DESC_0 | TN40_IR_TX_FREE_0 | 1711 TN40_IR_TMR1; 1712 1713 tn40_mac_init(priv); 1714 ret = tn40_phy_register(priv); 1715 if (ret) { 1716 dev_err(&pdev->dev, "failed to set up PHY.\n"); 1717 goto err_free_irq; 1718 } 1719 1720 ret = tn40_priv_init(priv); 1721 if (ret) { 1722 dev_err(&pdev->dev, "failed to initialize tn40_priv.\n"); 1723 goto err_unregister_phydev; 1724 } 1725 1726 ret = register_netdev(ndev); 1727 if (ret) { 1728 dev_err(&pdev->dev, "failed to register netdev.\n"); 1729 goto err_unregister_phydev; 1730 } 1731 return 0; 1732 err_unregister_phydev: 1733 tn40_phy_unregister(priv); 1734 err_free_irq: 1735 pci_free_irq_vectors(pdev); 1736 err_unset_drvdata: 1737 pci_set_drvdata(pdev, NULL); 1738 err_iounmap: 1739 iounmap(regs); 1740 err_free_regions: 1741 pci_release_regions(pdev); 1742 err_disable_device: 1743 pci_disable_device(pdev); 1744 return ret; 1745 } 1746 1747 static void tn40_remove(struct pci_dev *pdev) 1748 { 1749 struct tn40_priv *priv = pci_get_drvdata(pdev); 1750 struct net_device *ndev = priv->ndev; 1751 1752 unregister_netdev(ndev); 1753 1754 tn40_phy_unregister(priv); 1755 pci_free_irq_vectors(priv->pdev); 1756 pci_set_drvdata(pdev, NULL); 1757 iounmap(priv->regs); 1758 pci_release_regions(pdev); 1759 pci_disable_device(pdev); 1760 } 1761 1762 static const struct pci_device_id tn40_id_table[] = { 1763 { PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022, 1764 PCI_VENDOR_ID_TEHUTI, 0x3015) }, 1765 { PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022, 1766 PCI_VENDOR_ID_DLINK, 0x4d00) }, 1767 { PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022, 1768 PCI_VENDOR_ID_ASUSTEK, 0x8709) }, 1769 { PCI_DEVICE_SUB(PCI_VENDOR_ID_TEHUTI, 0x4022, 1770 PCI_VENDOR_ID_EDIMAX, 0x8103) }, 1771 { } 1772 }; 1773 1774 static struct pci_driver tn40_driver = { 1775 .name = TN40_DRV_NAME, 1776 .id_table = tn40_id_table, 1777 .probe = tn40_probe, 1778 .remove = tn40_remove, 1779 }; 1780 1781 module_pci_driver(tn40_driver); 1782 1783 MODULE_DEVICE_TABLE(pci, tn40_id_table); 1784 MODULE_LICENSE("GPL"); 1785 MODULE_FIRMWARE(TN40_FIRMWARE_NAME); 1786 MODULE_DESCRIPTION("Tehuti Network TN40xx Driver"); 1787