1 /* Synopsys DesignWare Core Enterprise Ethernet (XLGMAC) Driver 2 * 3 * Copyright (c) 2017 Synopsys, Inc. (www.synopsys.com) 4 * 5 * This program is dual-licensed; you may select either version 2 of 6 * the GNU General Public License ("GPL") or BSD license ("BSD"). 7 * 8 * This Synopsys DWC XLGMAC software driver and associated documentation 9 * (hereinafter the "Software") is an unsupported proprietary work of 10 * Synopsys, Inc. unless otherwise expressly agreed to in writing between 11 * Synopsys and you. The Software IS NOT an item of Licensed Software or a 12 * Licensed Product under any End User Software License Agreement or 13 * Agreement for Licensed Products with Synopsys or any supplement thereto. 14 * Synopsys is a registered trademark of Synopsys, Inc. Other names included 15 * in the SOFTWARE may be the trademarks of their respective owners. 16 */ 17 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 21 #include "dwc-xlgmac.h" 22 #include "dwc-xlgmac-reg.h" 23 24 static int debug = -1; 25 module_param(debug, int, 0644); 26 MODULE_LICENSE("GPL"); 27 MODULE_PARM_DESC(debug, "DWC ethernet debug level (0=none,...,16=all)"); 28 static const u32 default_msg_level = (NETIF_MSG_LINK | NETIF_MSG_IFDOWN | 29 NETIF_MSG_IFUP); 30 31 static unsigned char dev_addr[6] = {0, 0x55, 0x7b, 0xb5, 0x7d, 0xf7}; 32 33 static void xlgmac_read_mac_addr(struct xlgmac_pdata *pdata) 34 { 35 struct net_device *netdev = pdata->netdev; 36 37 /* Currently it uses a static mac address for test */ 38 memcpy(pdata->mac_addr, dev_addr, netdev->addr_len); 39 } 40 41 static void xlgmac_default_config(struct xlgmac_pdata *pdata) 42 { 43 pdata->tx_osp_mode = DMA_OSP_ENABLE; 44 pdata->tx_sf_mode = MTL_TSF_ENABLE; 45 pdata->rx_sf_mode = MTL_RSF_DISABLE; 46 pdata->pblx8 = DMA_PBL_X8_ENABLE; 47 pdata->tx_pbl = DMA_PBL_32; 48 pdata->rx_pbl = DMA_PBL_32; 49 pdata->tx_threshold = MTL_TX_THRESHOLD_128; 50 pdata->rx_threshold = MTL_RX_THRESHOLD_128; 51 pdata->tx_pause = 1; 52 pdata->rx_pause = 1; 53 pdata->phy_speed = SPEED_25000; 54 pdata->sysclk_rate = XLGMAC_SYSCLOCK; 55 56 strlcpy(pdata->drv_name, XLGMAC_DRV_NAME, sizeof(pdata->drv_name)); 57 strlcpy(pdata->drv_ver, XLGMAC_DRV_VERSION, sizeof(pdata->drv_ver)); 58 } 59 60 static void xlgmac_init_all_ops(struct xlgmac_pdata *pdata) 61 { 62 xlgmac_init_desc_ops(&pdata->desc_ops); 63 xlgmac_init_hw_ops(&pdata->hw_ops); 64 } 65 66 static int xlgmac_init(struct xlgmac_pdata *pdata) 67 { 68 struct xlgmac_hw_ops *hw_ops = &pdata->hw_ops; 69 struct net_device *netdev = pdata->netdev; 70 unsigned int i; 71 int ret; 72 73 /* Set default configuration data */ 74 xlgmac_default_config(pdata); 75 76 /* Set irq, base_addr, MAC address, */ 77 netdev->irq = pdata->dev_irq; 78 netdev->base_addr = (unsigned long)pdata->mac_regs; 79 xlgmac_read_mac_addr(pdata); 80 memcpy(netdev->dev_addr, pdata->mac_addr, netdev->addr_len); 81 82 /* Set all the function pointers */ 83 xlgmac_init_all_ops(pdata); 84 85 /* Issue software reset to device */ 86 hw_ops->exit(pdata); 87 88 /* Populate the hardware features */ 89 xlgmac_get_all_hw_features(pdata); 90 xlgmac_print_all_hw_features(pdata); 91 92 /* TODO: Set the PHY mode to XLGMII */ 93 94 /* Set the DMA mask */ 95 ret = dma_set_mask_and_coherent(pdata->dev, 96 DMA_BIT_MASK(pdata->hw_feat.dma_width)); 97 if (ret) { 98 dev_err(pdata->dev, "dma_set_mask_and_coherent failed\n"); 99 return ret; 100 } 101 102 /* Channel and ring params initializtion 103 * pdata->channel_count; 104 * pdata->tx_ring_count; 105 * pdata->rx_ring_count; 106 * pdata->tx_desc_count; 107 * pdata->rx_desc_count; 108 */ 109 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_TX_DESC_CNT); 110 pdata->tx_desc_count = XLGMAC_TX_DESC_CNT; 111 if (pdata->tx_desc_count & (pdata->tx_desc_count - 1)) { 112 dev_err(pdata->dev, "tx descriptor count (%d) is not valid\n", 113 pdata->tx_desc_count); 114 ret = -EINVAL; 115 return ret; 116 } 117 BUILD_BUG_ON_NOT_POWER_OF_2(XLGMAC_RX_DESC_CNT); 118 pdata->rx_desc_count = XLGMAC_RX_DESC_CNT; 119 if (pdata->rx_desc_count & (pdata->rx_desc_count - 1)) { 120 dev_err(pdata->dev, "rx descriptor count (%d) is not valid\n", 121 pdata->rx_desc_count); 122 ret = -EINVAL; 123 return ret; 124 } 125 126 pdata->tx_ring_count = min_t(unsigned int, num_online_cpus(), 127 pdata->hw_feat.tx_ch_cnt); 128 pdata->tx_ring_count = min_t(unsigned int, pdata->tx_ring_count, 129 pdata->hw_feat.tx_q_cnt); 130 pdata->tx_q_count = pdata->tx_ring_count; 131 ret = netif_set_real_num_tx_queues(netdev, pdata->tx_q_count); 132 if (ret) { 133 dev_err(pdata->dev, "error setting real tx queue count\n"); 134 return ret; 135 } 136 137 pdata->rx_ring_count = min_t(unsigned int, 138 netif_get_num_default_rss_queues(), 139 pdata->hw_feat.rx_ch_cnt); 140 pdata->rx_ring_count = min_t(unsigned int, pdata->rx_ring_count, 141 pdata->hw_feat.rx_q_cnt); 142 pdata->rx_q_count = pdata->rx_ring_count; 143 ret = netif_set_real_num_rx_queues(netdev, pdata->rx_q_count); 144 if (ret) { 145 dev_err(pdata->dev, "error setting real rx queue count\n"); 146 return ret; 147 } 148 149 pdata->channel_count = 150 max_t(unsigned int, pdata->tx_ring_count, pdata->rx_ring_count); 151 152 /* Initialize RSS hash key and lookup table */ 153 netdev_rss_key_fill(pdata->rss_key, sizeof(pdata->rss_key)); 154 155 for (i = 0; i < XLGMAC_RSS_MAX_TABLE_SIZE; i++) 156 pdata->rss_table[i] = XLGMAC_SET_REG_BITS( 157 pdata->rss_table[i], 158 MAC_RSSDR_DMCH_POS, 159 MAC_RSSDR_DMCH_LEN, 160 i % pdata->rx_ring_count); 161 162 pdata->rss_options = XLGMAC_SET_REG_BITS( 163 pdata->rss_options, 164 MAC_RSSCR_IP2TE_POS, 165 MAC_RSSCR_IP2TE_LEN, 1); 166 pdata->rss_options = XLGMAC_SET_REG_BITS( 167 pdata->rss_options, 168 MAC_RSSCR_TCP4TE_POS, 169 MAC_RSSCR_TCP4TE_LEN, 1); 170 pdata->rss_options = XLGMAC_SET_REG_BITS( 171 pdata->rss_options, 172 MAC_RSSCR_UDP4TE_POS, 173 MAC_RSSCR_UDP4TE_LEN, 1); 174 175 /* Set device operations */ 176 netdev->netdev_ops = xlgmac_get_netdev_ops(); 177 178 /* Set device features */ 179 if (pdata->hw_feat.tso) { 180 netdev->hw_features = NETIF_F_TSO; 181 netdev->hw_features |= NETIF_F_TSO6; 182 netdev->hw_features |= NETIF_F_SG; 183 netdev->hw_features |= NETIF_F_IP_CSUM; 184 netdev->hw_features |= NETIF_F_IPV6_CSUM; 185 } else if (pdata->hw_feat.tx_coe) { 186 netdev->hw_features = NETIF_F_IP_CSUM; 187 netdev->hw_features |= NETIF_F_IPV6_CSUM; 188 } 189 190 if (pdata->hw_feat.rx_coe) { 191 netdev->hw_features |= NETIF_F_RXCSUM; 192 netdev->hw_features |= NETIF_F_GRO; 193 } 194 195 if (pdata->hw_feat.rss) 196 netdev->hw_features |= NETIF_F_RXHASH; 197 198 netdev->vlan_features |= netdev->hw_features; 199 200 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX; 201 if (pdata->hw_feat.sa_vlan_ins) 202 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX; 203 if (pdata->hw_feat.vlhash) 204 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER; 205 206 netdev->features |= netdev->hw_features; 207 pdata->netdev_features = netdev->features; 208 209 netdev->priv_flags |= IFF_UNICAST_FLT; 210 211 /* Use default watchdog timeout */ 212 netdev->watchdog_timeo = 0; 213 214 /* Tx coalesce parameters initialization */ 215 pdata->tx_usecs = XLGMAC_INIT_DMA_TX_USECS; 216 pdata->tx_frames = XLGMAC_INIT_DMA_TX_FRAMES; 217 218 /* Rx coalesce parameters initialization */ 219 pdata->rx_riwt = hw_ops->usec_to_riwt(pdata, XLGMAC_INIT_DMA_RX_USECS); 220 pdata->rx_usecs = XLGMAC_INIT_DMA_RX_USECS; 221 pdata->rx_frames = XLGMAC_INIT_DMA_RX_FRAMES; 222 223 return 0; 224 } 225 226 int xlgmac_drv_probe(struct device *dev, struct xlgmac_resources *res) 227 { 228 struct xlgmac_pdata *pdata; 229 struct net_device *netdev; 230 int ret; 231 232 netdev = alloc_etherdev_mq(sizeof(struct xlgmac_pdata), 233 XLGMAC_MAX_DMA_CHANNELS); 234 235 if (!netdev) { 236 dev_err(dev, "alloc_etherdev failed\n"); 237 return -ENOMEM; 238 } 239 240 SET_NETDEV_DEV(netdev, dev); 241 dev_set_drvdata(dev, netdev); 242 pdata = netdev_priv(netdev); 243 pdata->dev = dev; 244 pdata->netdev = netdev; 245 246 pdata->dev_irq = res->irq; 247 pdata->mac_regs = res->addr; 248 249 mutex_init(&pdata->rss_mutex); 250 pdata->msg_enable = netif_msg_init(debug, default_msg_level); 251 252 ret = xlgmac_init(pdata); 253 if (ret) { 254 dev_err(dev, "xlgmac init failed\n"); 255 goto err_free_netdev; 256 } 257 258 ret = register_netdev(netdev); 259 if (ret) { 260 dev_err(dev, "net device registration failed\n"); 261 goto err_free_netdev; 262 } 263 264 return 0; 265 266 err_free_netdev: 267 free_netdev(netdev); 268 269 return ret; 270 } 271 272 int xlgmac_drv_remove(struct device *dev) 273 { 274 struct net_device *netdev = dev_get_drvdata(dev); 275 276 unregister_netdev(netdev); 277 free_netdev(netdev); 278 279 return 0; 280 } 281 282 void xlgmac_dump_tx_desc(struct xlgmac_pdata *pdata, 283 struct xlgmac_ring *ring, 284 unsigned int idx, 285 unsigned int count, 286 unsigned int flag) 287 { 288 struct xlgmac_desc_data *desc_data; 289 struct xlgmac_dma_desc *dma_desc; 290 291 while (count--) { 292 desc_data = XLGMAC_GET_DESC_DATA(ring, idx); 293 dma_desc = desc_data->dma_desc; 294 295 netdev_dbg(pdata->netdev, "TX: dma_desc=%p, dma_desc_addr=%pad\n", 296 desc_data->dma_desc, &desc_data->dma_desc_addr); 297 netdev_dbg(pdata->netdev, 298 "TX_NORMAL_DESC[%d %s] = %08x:%08x:%08x:%08x\n", idx, 299 (flag == 1) ? "QUEUED FOR TX" : "TX BY DEVICE", 300 le32_to_cpu(dma_desc->desc0), 301 le32_to_cpu(dma_desc->desc1), 302 le32_to_cpu(dma_desc->desc2), 303 le32_to_cpu(dma_desc->desc3)); 304 305 idx++; 306 } 307 } 308 309 void xlgmac_dump_rx_desc(struct xlgmac_pdata *pdata, 310 struct xlgmac_ring *ring, 311 unsigned int idx) 312 { 313 struct xlgmac_desc_data *desc_data; 314 struct xlgmac_dma_desc *dma_desc; 315 316 desc_data = XLGMAC_GET_DESC_DATA(ring, idx); 317 dma_desc = desc_data->dma_desc; 318 319 netdev_dbg(pdata->netdev, "RX: dma_desc=%p, dma_desc_addr=%pad\n", 320 desc_data->dma_desc, &desc_data->dma_desc_addr); 321 netdev_dbg(pdata->netdev, 322 "RX_NORMAL_DESC[%d RX BY DEVICE] = %08x:%08x:%08x:%08x\n", 323 idx, 324 le32_to_cpu(dma_desc->desc0), 325 le32_to_cpu(dma_desc->desc1), 326 le32_to_cpu(dma_desc->desc2), 327 le32_to_cpu(dma_desc->desc3)); 328 } 329 330 void xlgmac_print_pkt(struct net_device *netdev, 331 struct sk_buff *skb, bool tx_rx) 332 { 333 struct ethhdr *eth = (struct ethhdr *)skb->data; 334 unsigned char *buf = skb->data; 335 unsigned char buffer[128]; 336 unsigned int i, j; 337 338 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 339 340 netdev_dbg(netdev, "%s packet of %d bytes\n", 341 (tx_rx ? "TX" : "RX"), skb->len); 342 343 netdev_dbg(netdev, "Dst MAC addr: %pM\n", eth->h_dest); 344 netdev_dbg(netdev, "Src MAC addr: %pM\n", eth->h_source); 345 netdev_dbg(netdev, "Protocol: %#06hx\n", ntohs(eth->h_proto)); 346 347 for (i = 0, j = 0; i < skb->len;) { 348 j += snprintf(buffer + j, sizeof(buffer) - j, "%02hhx", 349 buf[i++]); 350 351 if ((i % 32) == 0) { 352 netdev_dbg(netdev, " %#06x: %s\n", i - 32, buffer); 353 j = 0; 354 } else if ((i % 16) == 0) { 355 buffer[j++] = ' '; 356 buffer[j++] = ' '; 357 } else if ((i % 4) == 0) { 358 buffer[j++] = ' '; 359 } 360 } 361 if (i % 32) 362 netdev_dbg(netdev, " %#06x: %s\n", i - (i % 32), buffer); 363 364 netdev_dbg(netdev, "\n************** SKB dump ****************\n"); 365 } 366 367 void xlgmac_get_all_hw_features(struct xlgmac_pdata *pdata) 368 { 369 struct xlgmac_hw_features *hw_feat = &pdata->hw_feat; 370 unsigned int mac_hfr0, mac_hfr1, mac_hfr2; 371 372 mac_hfr0 = readl(pdata->mac_regs + MAC_HWF0R); 373 mac_hfr1 = readl(pdata->mac_regs + MAC_HWF1R); 374 mac_hfr2 = readl(pdata->mac_regs + MAC_HWF2R); 375 376 memset(hw_feat, 0, sizeof(*hw_feat)); 377 378 hw_feat->version = readl(pdata->mac_regs + MAC_VR); 379 380 /* Hardware feature register 0 */ 381 hw_feat->phyifsel = XLGMAC_GET_REG_BITS(mac_hfr0, 382 MAC_HWF0R_PHYIFSEL_POS, 383 MAC_HWF0R_PHYIFSEL_LEN); 384 hw_feat->vlhash = XLGMAC_GET_REG_BITS(mac_hfr0, 385 MAC_HWF0R_VLHASH_POS, 386 MAC_HWF0R_VLHASH_LEN); 387 hw_feat->sma = XLGMAC_GET_REG_BITS(mac_hfr0, 388 MAC_HWF0R_SMASEL_POS, 389 MAC_HWF0R_SMASEL_LEN); 390 hw_feat->rwk = XLGMAC_GET_REG_BITS(mac_hfr0, 391 MAC_HWF0R_RWKSEL_POS, 392 MAC_HWF0R_RWKSEL_LEN); 393 hw_feat->mgk = XLGMAC_GET_REG_BITS(mac_hfr0, 394 MAC_HWF0R_MGKSEL_POS, 395 MAC_HWF0R_MGKSEL_LEN); 396 hw_feat->mmc = XLGMAC_GET_REG_BITS(mac_hfr0, 397 MAC_HWF0R_MMCSEL_POS, 398 MAC_HWF0R_MMCSEL_LEN); 399 hw_feat->aoe = XLGMAC_GET_REG_BITS(mac_hfr0, 400 MAC_HWF0R_ARPOFFSEL_POS, 401 MAC_HWF0R_ARPOFFSEL_LEN); 402 hw_feat->ts = XLGMAC_GET_REG_BITS(mac_hfr0, 403 MAC_HWF0R_TSSEL_POS, 404 MAC_HWF0R_TSSEL_LEN); 405 hw_feat->eee = XLGMAC_GET_REG_BITS(mac_hfr0, 406 MAC_HWF0R_EEESEL_POS, 407 MAC_HWF0R_EEESEL_LEN); 408 hw_feat->tx_coe = XLGMAC_GET_REG_BITS(mac_hfr0, 409 MAC_HWF0R_TXCOESEL_POS, 410 MAC_HWF0R_TXCOESEL_LEN); 411 hw_feat->rx_coe = XLGMAC_GET_REG_BITS(mac_hfr0, 412 MAC_HWF0R_RXCOESEL_POS, 413 MAC_HWF0R_RXCOESEL_LEN); 414 hw_feat->addn_mac = XLGMAC_GET_REG_BITS(mac_hfr0, 415 MAC_HWF0R_ADDMACADRSEL_POS, 416 MAC_HWF0R_ADDMACADRSEL_LEN); 417 hw_feat->ts_src = XLGMAC_GET_REG_BITS(mac_hfr0, 418 MAC_HWF0R_TSSTSSEL_POS, 419 MAC_HWF0R_TSSTSSEL_LEN); 420 hw_feat->sa_vlan_ins = XLGMAC_GET_REG_BITS(mac_hfr0, 421 MAC_HWF0R_SAVLANINS_POS, 422 MAC_HWF0R_SAVLANINS_LEN); 423 424 /* Hardware feature register 1 */ 425 hw_feat->rx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1, 426 MAC_HWF1R_RXFIFOSIZE_POS, 427 MAC_HWF1R_RXFIFOSIZE_LEN); 428 hw_feat->tx_fifo_size = XLGMAC_GET_REG_BITS(mac_hfr1, 429 MAC_HWF1R_TXFIFOSIZE_POS, 430 MAC_HWF1R_TXFIFOSIZE_LEN); 431 hw_feat->adv_ts_hi = XLGMAC_GET_REG_BITS(mac_hfr1, 432 MAC_HWF1R_ADVTHWORD_POS, 433 MAC_HWF1R_ADVTHWORD_LEN); 434 hw_feat->dma_width = XLGMAC_GET_REG_BITS(mac_hfr1, 435 MAC_HWF1R_ADDR64_POS, 436 MAC_HWF1R_ADDR64_LEN); 437 hw_feat->dcb = XLGMAC_GET_REG_BITS(mac_hfr1, 438 MAC_HWF1R_DCBEN_POS, 439 MAC_HWF1R_DCBEN_LEN); 440 hw_feat->sph = XLGMAC_GET_REG_BITS(mac_hfr1, 441 MAC_HWF1R_SPHEN_POS, 442 MAC_HWF1R_SPHEN_LEN); 443 hw_feat->tso = XLGMAC_GET_REG_BITS(mac_hfr1, 444 MAC_HWF1R_TSOEN_POS, 445 MAC_HWF1R_TSOEN_LEN); 446 hw_feat->dma_debug = XLGMAC_GET_REG_BITS(mac_hfr1, 447 MAC_HWF1R_DBGMEMA_POS, 448 MAC_HWF1R_DBGMEMA_LEN); 449 hw_feat->rss = XLGMAC_GET_REG_BITS(mac_hfr1, 450 MAC_HWF1R_RSSEN_POS, 451 MAC_HWF1R_RSSEN_LEN); 452 hw_feat->tc_cnt = XLGMAC_GET_REG_BITS(mac_hfr1, 453 MAC_HWF1R_NUMTC_POS, 454 MAC_HWF1R_NUMTC_LEN); 455 hw_feat->hash_table_size = XLGMAC_GET_REG_BITS(mac_hfr1, 456 MAC_HWF1R_HASHTBLSZ_POS, 457 MAC_HWF1R_HASHTBLSZ_LEN); 458 hw_feat->l3l4_filter_num = XLGMAC_GET_REG_BITS(mac_hfr1, 459 MAC_HWF1R_L3L4FNUM_POS, 460 MAC_HWF1R_L3L4FNUM_LEN); 461 462 /* Hardware feature register 2 */ 463 hw_feat->rx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 464 MAC_HWF2R_RXQCNT_POS, 465 MAC_HWF2R_RXQCNT_LEN); 466 hw_feat->tx_q_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 467 MAC_HWF2R_TXQCNT_POS, 468 MAC_HWF2R_TXQCNT_LEN); 469 hw_feat->rx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 470 MAC_HWF2R_RXCHCNT_POS, 471 MAC_HWF2R_RXCHCNT_LEN); 472 hw_feat->tx_ch_cnt = XLGMAC_GET_REG_BITS(mac_hfr2, 473 MAC_HWF2R_TXCHCNT_POS, 474 MAC_HWF2R_TXCHCNT_LEN); 475 hw_feat->pps_out_num = XLGMAC_GET_REG_BITS(mac_hfr2, 476 MAC_HWF2R_PPSOUTNUM_POS, 477 MAC_HWF2R_PPSOUTNUM_LEN); 478 hw_feat->aux_snap_num = XLGMAC_GET_REG_BITS(mac_hfr2, 479 MAC_HWF2R_AUXSNAPNUM_POS, 480 MAC_HWF2R_AUXSNAPNUM_LEN); 481 482 /* Translate the Hash Table size into actual number */ 483 switch (hw_feat->hash_table_size) { 484 case 0: 485 break; 486 case 1: 487 hw_feat->hash_table_size = 64; 488 break; 489 case 2: 490 hw_feat->hash_table_size = 128; 491 break; 492 case 3: 493 hw_feat->hash_table_size = 256; 494 break; 495 } 496 497 /* Translate the address width setting into actual number */ 498 switch (hw_feat->dma_width) { 499 case 0: 500 hw_feat->dma_width = 32; 501 break; 502 case 1: 503 hw_feat->dma_width = 40; 504 break; 505 case 2: 506 hw_feat->dma_width = 48; 507 break; 508 default: 509 hw_feat->dma_width = 32; 510 } 511 512 /* The Queue, Channel and TC counts are zero based so increment them 513 * to get the actual number 514 */ 515 hw_feat->rx_q_cnt++; 516 hw_feat->tx_q_cnt++; 517 hw_feat->rx_ch_cnt++; 518 hw_feat->tx_ch_cnt++; 519 hw_feat->tc_cnt++; 520 } 521 522 void xlgmac_print_all_hw_features(struct xlgmac_pdata *pdata) 523 { 524 char *str = NULL; 525 526 XLGMAC_PR("\n"); 527 XLGMAC_PR("=====================================================\n"); 528 XLGMAC_PR("\n"); 529 XLGMAC_PR("HW support following features\n"); 530 XLGMAC_PR("\n"); 531 /* HW Feature Register0 */ 532 XLGMAC_PR("VLAN Hash Filter Selected : %s\n", 533 pdata->hw_feat.vlhash ? "YES" : "NO"); 534 XLGMAC_PR("SMA (MDIO) Interface : %s\n", 535 pdata->hw_feat.sma ? "YES" : "NO"); 536 XLGMAC_PR("PMT Remote Wake-up Packet Enable : %s\n", 537 pdata->hw_feat.rwk ? "YES" : "NO"); 538 XLGMAC_PR("PMT Magic Packet Enable : %s\n", 539 pdata->hw_feat.mgk ? "YES" : "NO"); 540 XLGMAC_PR("RMON/MMC Module Enable : %s\n", 541 pdata->hw_feat.mmc ? "YES" : "NO"); 542 XLGMAC_PR("ARP Offload Enabled : %s\n", 543 pdata->hw_feat.aoe ? "YES" : "NO"); 544 XLGMAC_PR("IEEE 1588-2008 Timestamp Enabled : %s\n", 545 pdata->hw_feat.ts ? "YES" : "NO"); 546 XLGMAC_PR("Energy Efficient Ethernet Enabled : %s\n", 547 pdata->hw_feat.eee ? "YES" : "NO"); 548 XLGMAC_PR("Transmit Checksum Offload Enabled : %s\n", 549 pdata->hw_feat.tx_coe ? "YES" : "NO"); 550 XLGMAC_PR("Receive Checksum Offload Enabled : %s\n", 551 pdata->hw_feat.rx_coe ? "YES" : "NO"); 552 XLGMAC_PR("Additional MAC Addresses 1-31 Selected : %s\n", 553 pdata->hw_feat.addn_mac ? "YES" : "NO"); 554 555 switch (pdata->hw_feat.ts_src) { 556 case 0: 557 str = "RESERVED"; 558 break; 559 case 1: 560 str = "INTERNAL"; 561 break; 562 case 2: 563 str = "EXTERNAL"; 564 break; 565 case 3: 566 str = "BOTH"; 567 break; 568 } 569 XLGMAC_PR("Timestamp System Time Source : %s\n", str); 570 571 XLGMAC_PR("Source Address or VLAN Insertion Enable : %s\n", 572 pdata->hw_feat.sa_vlan_ins ? "YES" : "NO"); 573 574 /* HW Feature Register1 */ 575 switch (pdata->hw_feat.rx_fifo_size) { 576 case 0: 577 str = "128 bytes"; 578 break; 579 case 1: 580 str = "256 bytes"; 581 break; 582 case 2: 583 str = "512 bytes"; 584 break; 585 case 3: 586 str = "1 KBytes"; 587 break; 588 case 4: 589 str = "2 KBytes"; 590 break; 591 case 5: 592 str = "4 KBytes"; 593 break; 594 case 6: 595 str = "8 KBytes"; 596 break; 597 case 7: 598 str = "16 KBytes"; 599 break; 600 case 8: 601 str = "32 kBytes"; 602 break; 603 case 9: 604 str = "64 KBytes"; 605 break; 606 case 10: 607 str = "128 KBytes"; 608 break; 609 case 11: 610 str = "256 KBytes"; 611 break; 612 default: 613 str = "RESERVED"; 614 } 615 XLGMAC_PR("MTL Receive FIFO Size : %s\n", str); 616 617 switch (pdata->hw_feat.tx_fifo_size) { 618 case 0: 619 str = "128 bytes"; 620 break; 621 case 1: 622 str = "256 bytes"; 623 break; 624 case 2: 625 str = "512 bytes"; 626 break; 627 case 3: 628 str = "1 KBytes"; 629 break; 630 case 4: 631 str = "2 KBytes"; 632 break; 633 case 5: 634 str = "4 KBytes"; 635 break; 636 case 6: 637 str = "8 KBytes"; 638 break; 639 case 7: 640 str = "16 KBytes"; 641 break; 642 case 8: 643 str = "32 kBytes"; 644 break; 645 case 9: 646 str = "64 KBytes"; 647 break; 648 case 10: 649 str = "128 KBytes"; 650 break; 651 case 11: 652 str = "256 KBytes"; 653 break; 654 default: 655 str = "RESERVED"; 656 } 657 XLGMAC_PR("MTL Transmit FIFO Size : %s\n", str); 658 659 XLGMAC_PR("IEEE 1588 High Word Register Enable : %s\n", 660 pdata->hw_feat.adv_ts_hi ? "YES" : "NO"); 661 XLGMAC_PR("Address width : %u\n", 662 pdata->hw_feat.dma_width); 663 XLGMAC_PR("DCB Feature Enable : %s\n", 664 pdata->hw_feat.dcb ? "YES" : "NO"); 665 XLGMAC_PR("Split Header Feature Enable : %s\n", 666 pdata->hw_feat.sph ? "YES" : "NO"); 667 XLGMAC_PR("TCP Segmentation Offload Enable : %s\n", 668 pdata->hw_feat.tso ? "YES" : "NO"); 669 XLGMAC_PR("DMA Debug Registers Enabled : %s\n", 670 pdata->hw_feat.dma_debug ? "YES" : "NO"); 671 XLGMAC_PR("RSS Feature Enabled : %s\n", 672 pdata->hw_feat.rss ? "YES" : "NO"); 673 XLGMAC_PR("Number of Traffic classes : %u\n", 674 (pdata->hw_feat.tc_cnt)); 675 XLGMAC_PR("Hash Table Size : %u\n", 676 pdata->hw_feat.hash_table_size); 677 XLGMAC_PR("Total number of L3 or L4 Filters : %u\n", 678 pdata->hw_feat.l3l4_filter_num); 679 680 /* HW Feature Register2 */ 681 XLGMAC_PR("Number of MTL Receive Queues : %u\n", 682 pdata->hw_feat.rx_q_cnt); 683 XLGMAC_PR("Number of MTL Transmit Queues : %u\n", 684 pdata->hw_feat.tx_q_cnt); 685 XLGMAC_PR("Number of DMA Receive Channels : %u\n", 686 pdata->hw_feat.rx_ch_cnt); 687 XLGMAC_PR("Number of DMA Transmit Channels : %u\n", 688 pdata->hw_feat.tx_ch_cnt); 689 690 switch (pdata->hw_feat.pps_out_num) { 691 case 0: 692 str = "No PPS output"; 693 break; 694 case 1: 695 str = "1 PPS output"; 696 break; 697 case 2: 698 str = "2 PPS output"; 699 break; 700 case 3: 701 str = "3 PPS output"; 702 break; 703 case 4: 704 str = "4 PPS output"; 705 break; 706 default: 707 str = "RESERVED"; 708 } 709 XLGMAC_PR("Number of PPS Outputs : %s\n", str); 710 711 switch (pdata->hw_feat.aux_snap_num) { 712 case 0: 713 str = "No auxiliary input"; 714 break; 715 case 1: 716 str = "1 auxiliary input"; 717 break; 718 case 2: 719 str = "2 auxiliary input"; 720 break; 721 case 3: 722 str = "3 auxiliary input"; 723 break; 724 case 4: 725 str = "4 auxiliary input"; 726 break; 727 default: 728 str = "RESERVED"; 729 } 730 XLGMAC_PR("Number of Auxiliary Snapshot Inputs : %s", str); 731 732 XLGMAC_PR("\n"); 733 XLGMAC_PR("=====================================================\n"); 734 XLGMAC_PR("\n"); 735 } 736