1 /* niu.c: Neptune ethernet driver. 2 * 3 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net) 4 */ 5 6 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 7 8 #include <linux/module.h> 9 #include <linux/init.h> 10 #include <linux/interrupt.h> 11 #include <linux/pci.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/netdevice.h> 14 #include <linux/ethtool.h> 15 #include <linux/etherdevice.h> 16 #include <linux/platform_device.h> 17 #include <linux/delay.h> 18 #include <linux/bitops.h> 19 #include <linux/mii.h> 20 #include <linux/if.h> 21 #include <linux/if_ether.h> 22 #include <linux/if_vlan.h> 23 #include <linux/ip.h> 24 #include <linux/in.h> 25 #include <linux/ipv6.h> 26 #include <linux/log2.h> 27 #include <linux/jiffies.h> 28 #include <linux/crc32.h> 29 #include <linux/list.h> 30 #include <linux/slab.h> 31 32 #include <linux/io.h> 33 #include <linux/of_device.h> 34 35 #include "niu.h" 36 37 #define DRV_MODULE_NAME "niu" 38 #define DRV_MODULE_VERSION "1.1" 39 #define DRV_MODULE_RELDATE "Apr 22, 2010" 40 41 static char version[] __devinitdata = 42 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 43 44 MODULE_AUTHOR("David S. Miller (davem@davemloft.net)"); 45 MODULE_DESCRIPTION("NIU ethernet driver"); 46 MODULE_LICENSE("GPL"); 47 MODULE_VERSION(DRV_MODULE_VERSION); 48 49 #ifndef readq 50 static u64 readq(void __iomem *reg) 51 { 52 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); 53 } 54 55 static void writeq(u64 val, void __iomem *reg) 56 { 57 writel(val & 0xffffffff, reg); 58 writel(val >> 32, reg + 0x4UL); 59 } 60 #endif 61 62 static DEFINE_PCI_DEVICE_TABLE(niu_pci_tbl) = { 63 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, 64 {} 65 }; 66 67 MODULE_DEVICE_TABLE(pci, niu_pci_tbl); 68 69 #define NIU_TX_TIMEOUT (5 * HZ) 70 71 #define nr64(reg) readq(np->regs + (reg)) 72 #define nw64(reg, val) writeq((val), np->regs + (reg)) 73 74 #define nr64_mac(reg) readq(np->mac_regs + (reg)) 75 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) 76 77 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) 78 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) 79 80 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) 81 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) 82 83 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) 84 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) 85 86 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 87 88 static int niu_debug; 89 static int debug = -1; 90 module_param(debug, int, 0); 91 MODULE_PARM_DESC(debug, "NIU debug level"); 92 93 #define niu_lock_parent(np, flags) \ 94 spin_lock_irqsave(&np->parent->lock, flags) 95 #define niu_unlock_parent(np, flags) \ 96 spin_unlock_irqrestore(&np->parent->lock, flags) 97 98 static int serdes_init_10g_serdes(struct niu *np); 99 100 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, 101 u64 bits, int limit, int delay) 102 { 103 while (--limit >= 0) { 104 u64 val = nr64_mac(reg); 105 106 if (!(val & bits)) 107 break; 108 udelay(delay); 109 } 110 if (limit < 0) 111 return -ENODEV; 112 return 0; 113 } 114 115 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, 116 u64 bits, int limit, int delay, 117 const char *reg_name) 118 { 119 int err; 120 121 nw64_mac(reg, bits); 122 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); 123 if (err) 124 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 125 (unsigned long long)bits, reg_name, 126 (unsigned long long)nr64_mac(reg)); 127 return err; 128 } 129 130 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 131 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 132 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 133 }) 134 135 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, 136 u64 bits, int limit, int delay) 137 { 138 while (--limit >= 0) { 139 u64 val = nr64_ipp(reg); 140 141 if (!(val & bits)) 142 break; 143 udelay(delay); 144 } 145 if (limit < 0) 146 return -ENODEV; 147 return 0; 148 } 149 150 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, 151 u64 bits, int limit, int delay, 152 const char *reg_name) 153 { 154 int err; 155 u64 val; 156 157 val = nr64_ipp(reg); 158 val |= bits; 159 nw64_ipp(reg, val); 160 161 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); 162 if (err) 163 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 164 (unsigned long long)bits, reg_name, 165 (unsigned long long)nr64_ipp(reg)); 166 return err; 167 } 168 169 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 170 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 171 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 172 }) 173 174 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, 175 u64 bits, int limit, int delay) 176 { 177 while (--limit >= 0) { 178 u64 val = nr64(reg); 179 180 if (!(val & bits)) 181 break; 182 udelay(delay); 183 } 184 if (limit < 0) 185 return -ENODEV; 186 return 0; 187 } 188 189 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ 190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 191 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ 192 }) 193 194 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, 195 u64 bits, int limit, int delay, 196 const char *reg_name) 197 { 198 int err; 199 200 nw64(reg, bits); 201 err = __niu_wait_bits_clear(np, reg, bits, limit, delay); 202 if (err) 203 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 204 (unsigned long long)bits, reg_name, 205 (unsigned long long)nr64(reg)); 206 return err; 207 } 208 209 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 211 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 212 }) 213 214 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) 215 { 216 u64 val = (u64) lp->timer; 217 218 if (on) 219 val |= LDG_IMGMT_ARM; 220 221 nw64(LDG_IMGMT(lp->ldg_num), val); 222 } 223 224 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) 225 { 226 unsigned long mask_reg, bits; 227 u64 val; 228 229 if (ldn < 0 || ldn > LDN_MAX) 230 return -EINVAL; 231 232 if (ldn < 64) { 233 mask_reg = LD_IM0(ldn); 234 bits = LD_IM0_MASK; 235 } else { 236 mask_reg = LD_IM1(ldn - 64); 237 bits = LD_IM1_MASK; 238 } 239 240 val = nr64(mask_reg); 241 if (on) 242 val &= ~bits; 243 else 244 val |= bits; 245 nw64(mask_reg, val); 246 247 return 0; 248 } 249 250 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) 251 { 252 struct niu_parent *parent = np->parent; 253 int i; 254 255 for (i = 0; i <= LDN_MAX; i++) { 256 int err; 257 258 if (parent->ldg_map[i] != lp->ldg_num) 259 continue; 260 261 err = niu_ldn_irq_enable(np, i, on); 262 if (err) 263 return err; 264 } 265 return 0; 266 } 267 268 static int niu_enable_interrupts(struct niu *np, int on) 269 { 270 int i; 271 272 for (i = 0; i < np->num_ldg; i++) { 273 struct niu_ldg *lp = &np->ldg[i]; 274 int err; 275 276 err = niu_enable_ldn_in_ldg(np, lp, on); 277 if (err) 278 return err; 279 } 280 for (i = 0; i < np->num_ldg; i++) 281 niu_ldg_rearm(np, &np->ldg[i], on); 282 283 return 0; 284 } 285 286 static u32 phy_encode(u32 type, int port) 287 { 288 return type << (port * 2); 289 } 290 291 static u32 phy_decode(u32 val, int port) 292 { 293 return (val >> (port * 2)) & PORT_TYPE_MASK; 294 } 295 296 static int mdio_wait(struct niu *np) 297 { 298 int limit = 1000; 299 u64 val; 300 301 while (--limit > 0) { 302 val = nr64(MIF_FRAME_OUTPUT); 303 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) 304 return val & MIF_FRAME_OUTPUT_DATA; 305 306 udelay(10); 307 } 308 309 return -ENODEV; 310 } 311 312 static int mdio_read(struct niu *np, int port, int dev, int reg) 313 { 314 int err; 315 316 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 317 err = mdio_wait(np); 318 if (err < 0) 319 return err; 320 321 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); 322 return mdio_wait(np); 323 } 324 325 static int mdio_write(struct niu *np, int port, int dev, int reg, int data) 326 { 327 int err; 328 329 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 330 err = mdio_wait(np); 331 if (err < 0) 332 return err; 333 334 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); 335 err = mdio_wait(np); 336 if (err < 0) 337 return err; 338 339 return 0; 340 } 341 342 static int mii_read(struct niu *np, int port, int reg) 343 { 344 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); 345 return mdio_wait(np); 346 } 347 348 static int mii_write(struct niu *np, int port, int reg, int data) 349 { 350 int err; 351 352 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); 353 err = mdio_wait(np); 354 if (err < 0) 355 return err; 356 357 return 0; 358 } 359 360 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) 361 { 362 int err; 363 364 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 365 ESR2_TI_PLL_TX_CFG_L(channel), 366 val & 0xffff); 367 if (!err) 368 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 369 ESR2_TI_PLL_TX_CFG_H(channel), 370 val >> 16); 371 return err; 372 } 373 374 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) 375 { 376 int err; 377 378 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 379 ESR2_TI_PLL_RX_CFG_L(channel), 380 val & 0xffff); 381 if (!err) 382 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 383 ESR2_TI_PLL_RX_CFG_H(channel), 384 val >> 16); 385 return err; 386 } 387 388 /* Mode is always 10G fiber. */ 389 static int serdes_init_niu_10g_fiber(struct niu *np) 390 { 391 struct niu_link_config *lp = &np->link_config; 392 u32 tx_cfg, rx_cfg; 393 unsigned long i; 394 395 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 396 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 397 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 398 PLL_RX_CFG_EQ_LP_ADAPTIVE); 399 400 if (lp->loopback_mode == LOOPBACK_PHY) { 401 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 402 403 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 404 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 405 406 tx_cfg |= PLL_TX_CFG_ENTEST; 407 rx_cfg |= PLL_RX_CFG_ENTEST; 408 } 409 410 /* Initialize all 4 lanes of the SERDES. */ 411 for (i = 0; i < 4; i++) { 412 int err = esr2_set_tx_cfg(np, i, tx_cfg); 413 if (err) 414 return err; 415 } 416 417 for (i = 0; i < 4; i++) { 418 int err = esr2_set_rx_cfg(np, i, rx_cfg); 419 if (err) 420 return err; 421 } 422 423 return 0; 424 } 425 426 static int serdes_init_niu_1g_serdes(struct niu *np) 427 { 428 struct niu_link_config *lp = &np->link_config; 429 u16 pll_cfg, pll_sts; 430 int max_retry = 100; 431 u64 uninitialized_var(sig), mask, val; 432 u32 tx_cfg, rx_cfg; 433 unsigned long i; 434 int err; 435 436 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV | 437 PLL_TX_CFG_RATE_HALF); 438 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 439 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 440 PLL_RX_CFG_RATE_HALF); 441 442 if (np->port == 0) 443 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE; 444 445 if (lp->loopback_mode == LOOPBACK_PHY) { 446 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 447 448 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 449 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 450 451 tx_cfg |= PLL_TX_CFG_ENTEST; 452 rx_cfg |= PLL_RX_CFG_ENTEST; 453 } 454 455 /* Initialize PLL for 1G */ 456 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X); 457 458 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 459 ESR2_TI_PLL_CFG_L, pll_cfg); 460 if (err) { 461 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 462 np->port, __func__); 463 return err; 464 } 465 466 pll_sts = PLL_CFG_ENPLL; 467 468 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 469 ESR2_TI_PLL_STS_L, pll_sts); 470 if (err) { 471 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 472 np->port, __func__); 473 return err; 474 } 475 476 udelay(200); 477 478 /* Initialize all 4 lanes of the SERDES. */ 479 for (i = 0; i < 4; i++) { 480 err = esr2_set_tx_cfg(np, i, tx_cfg); 481 if (err) 482 return err; 483 } 484 485 for (i = 0; i < 4; i++) { 486 err = esr2_set_rx_cfg(np, i, rx_cfg); 487 if (err) 488 return err; 489 } 490 491 switch (np->port) { 492 case 0: 493 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 494 mask = val; 495 break; 496 497 case 1: 498 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 499 mask = val; 500 break; 501 502 default: 503 return -EINVAL; 504 } 505 506 while (max_retry--) { 507 sig = nr64(ESR_INT_SIGNALS); 508 if ((sig & mask) == val) 509 break; 510 511 mdelay(500); 512 } 513 514 if ((sig & mask) != val) { 515 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 516 np->port, (int)(sig & mask), (int)val); 517 return -ENODEV; 518 } 519 520 return 0; 521 } 522 523 static int serdes_init_niu_10g_serdes(struct niu *np) 524 { 525 struct niu_link_config *lp = &np->link_config; 526 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; 527 int max_retry = 100; 528 u64 uninitialized_var(sig), mask, val; 529 unsigned long i; 530 int err; 531 532 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 533 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 534 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 535 PLL_RX_CFG_EQ_LP_ADAPTIVE); 536 537 if (lp->loopback_mode == LOOPBACK_PHY) { 538 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 539 540 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 541 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 542 543 tx_cfg |= PLL_TX_CFG_ENTEST; 544 rx_cfg |= PLL_RX_CFG_ENTEST; 545 } 546 547 /* Initialize PLL for 10G */ 548 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X); 549 550 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 551 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff); 552 if (err) { 553 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 554 np->port, __func__); 555 return err; 556 } 557 558 pll_sts = PLL_CFG_ENPLL; 559 560 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 561 ESR2_TI_PLL_STS_L, pll_sts & 0xffff); 562 if (err) { 563 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 564 np->port, __func__); 565 return err; 566 } 567 568 udelay(200); 569 570 /* Initialize all 4 lanes of the SERDES. */ 571 for (i = 0; i < 4; i++) { 572 err = esr2_set_tx_cfg(np, i, tx_cfg); 573 if (err) 574 return err; 575 } 576 577 for (i = 0; i < 4; i++) { 578 err = esr2_set_rx_cfg(np, i, rx_cfg); 579 if (err) 580 return err; 581 } 582 583 /* check if serdes is ready */ 584 585 switch (np->port) { 586 case 0: 587 mask = ESR_INT_SIGNALS_P0_BITS; 588 val = (ESR_INT_SRDY0_P0 | 589 ESR_INT_DET0_P0 | 590 ESR_INT_XSRDY_P0 | 591 ESR_INT_XDP_P0_CH3 | 592 ESR_INT_XDP_P0_CH2 | 593 ESR_INT_XDP_P0_CH1 | 594 ESR_INT_XDP_P0_CH0); 595 break; 596 597 case 1: 598 mask = ESR_INT_SIGNALS_P1_BITS; 599 val = (ESR_INT_SRDY0_P1 | 600 ESR_INT_DET0_P1 | 601 ESR_INT_XSRDY_P1 | 602 ESR_INT_XDP_P1_CH3 | 603 ESR_INT_XDP_P1_CH2 | 604 ESR_INT_XDP_P1_CH1 | 605 ESR_INT_XDP_P1_CH0); 606 break; 607 608 default: 609 return -EINVAL; 610 } 611 612 while (max_retry--) { 613 sig = nr64(ESR_INT_SIGNALS); 614 if ((sig & mask) == val) 615 break; 616 617 mdelay(500); 618 } 619 620 if ((sig & mask) != val) { 621 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n", 622 np->port, (int)(sig & mask), (int)val); 623 624 /* 10G failed, try initializing at 1G */ 625 err = serdes_init_niu_1g_serdes(np); 626 if (!err) { 627 np->flags &= ~NIU_FLAGS_10G; 628 np->mac_xcvr = MAC_XCVR_PCS; 629 } else { 630 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 631 np->port); 632 return -ENODEV; 633 } 634 } 635 return 0; 636 } 637 638 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) 639 { 640 int err; 641 642 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); 643 if (err >= 0) { 644 *val = (err & 0xffff); 645 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 646 ESR_RXTX_CTRL_H(chan)); 647 if (err >= 0) 648 *val |= ((err & 0xffff) << 16); 649 err = 0; 650 } 651 return err; 652 } 653 654 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) 655 { 656 int err; 657 658 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 659 ESR_GLUE_CTRL0_L(chan)); 660 if (err >= 0) { 661 *val = (err & 0xffff); 662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 663 ESR_GLUE_CTRL0_H(chan)); 664 if (err >= 0) { 665 *val |= ((err & 0xffff) << 16); 666 err = 0; 667 } 668 } 669 return err; 670 } 671 672 static int esr_read_reset(struct niu *np, u32 *val) 673 { 674 int err; 675 676 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 677 ESR_RXTX_RESET_CTRL_L); 678 if (err >= 0) { 679 *val = (err & 0xffff); 680 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 681 ESR_RXTX_RESET_CTRL_H); 682 if (err >= 0) { 683 *val |= ((err & 0xffff) << 16); 684 err = 0; 685 } 686 } 687 return err; 688 } 689 690 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) 691 { 692 int err; 693 694 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 695 ESR_RXTX_CTRL_L(chan), val & 0xffff); 696 if (!err) 697 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 698 ESR_RXTX_CTRL_H(chan), (val >> 16)); 699 return err; 700 } 701 702 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) 703 { 704 int err; 705 706 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 707 ESR_GLUE_CTRL0_L(chan), val & 0xffff); 708 if (!err) 709 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 710 ESR_GLUE_CTRL0_H(chan), (val >> 16)); 711 return err; 712 } 713 714 static int esr_reset(struct niu *np) 715 { 716 u32 uninitialized_var(reset); 717 int err; 718 719 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 720 ESR_RXTX_RESET_CTRL_L, 0x0000); 721 if (err) 722 return err; 723 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 724 ESR_RXTX_RESET_CTRL_H, 0xffff); 725 if (err) 726 return err; 727 udelay(200); 728 729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 730 ESR_RXTX_RESET_CTRL_L, 0xffff); 731 if (err) 732 return err; 733 udelay(200); 734 735 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 736 ESR_RXTX_RESET_CTRL_H, 0x0000); 737 if (err) 738 return err; 739 udelay(200); 740 741 err = esr_read_reset(np, &reset); 742 if (err) 743 return err; 744 if (reset != 0) { 745 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n", 746 np->port, reset); 747 return -ENODEV; 748 } 749 750 return 0; 751 } 752 753 static int serdes_init_10g(struct niu *np) 754 { 755 struct niu_link_config *lp = &np->link_config; 756 unsigned long ctrl_reg, test_cfg_reg, i; 757 u64 ctrl_val, test_cfg_val, sig, mask, val; 758 int err; 759 760 switch (np->port) { 761 case 0: 762 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 763 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 764 break; 765 case 1: 766 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 767 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 768 break; 769 770 default: 771 return -EINVAL; 772 } 773 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 774 ENET_SERDES_CTRL_SDET_1 | 775 ENET_SERDES_CTRL_SDET_2 | 776 ENET_SERDES_CTRL_SDET_3 | 777 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 778 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 779 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 780 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 781 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 782 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 783 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 784 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 785 test_cfg_val = 0; 786 787 if (lp->loopback_mode == LOOPBACK_PHY) { 788 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 789 ENET_SERDES_TEST_MD_0_SHIFT) | 790 (ENET_TEST_MD_PAD_LOOPBACK << 791 ENET_SERDES_TEST_MD_1_SHIFT) | 792 (ENET_TEST_MD_PAD_LOOPBACK << 793 ENET_SERDES_TEST_MD_2_SHIFT) | 794 (ENET_TEST_MD_PAD_LOOPBACK << 795 ENET_SERDES_TEST_MD_3_SHIFT)); 796 } 797 798 nw64(ctrl_reg, ctrl_val); 799 nw64(test_cfg_reg, test_cfg_val); 800 801 /* Initialize all 4 lanes of the SERDES. */ 802 for (i = 0; i < 4; i++) { 803 u32 rxtx_ctrl, glue0; 804 805 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 806 if (err) 807 return err; 808 err = esr_read_glue0(np, i, &glue0); 809 if (err) 810 return err; 811 812 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 813 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 814 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 815 816 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 817 ESR_GLUE_CTRL0_THCNT | 818 ESR_GLUE_CTRL0_BLTIME); 819 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 820 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 821 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 822 (BLTIME_300_CYCLES << 823 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 824 825 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 826 if (err) 827 return err; 828 err = esr_write_glue0(np, i, glue0); 829 if (err) 830 return err; 831 } 832 833 err = esr_reset(np); 834 if (err) 835 return err; 836 837 sig = nr64(ESR_INT_SIGNALS); 838 switch (np->port) { 839 case 0: 840 mask = ESR_INT_SIGNALS_P0_BITS; 841 val = (ESR_INT_SRDY0_P0 | 842 ESR_INT_DET0_P0 | 843 ESR_INT_XSRDY_P0 | 844 ESR_INT_XDP_P0_CH3 | 845 ESR_INT_XDP_P0_CH2 | 846 ESR_INT_XDP_P0_CH1 | 847 ESR_INT_XDP_P0_CH0); 848 break; 849 850 case 1: 851 mask = ESR_INT_SIGNALS_P1_BITS; 852 val = (ESR_INT_SRDY0_P1 | 853 ESR_INT_DET0_P1 | 854 ESR_INT_XSRDY_P1 | 855 ESR_INT_XDP_P1_CH3 | 856 ESR_INT_XDP_P1_CH2 | 857 ESR_INT_XDP_P1_CH1 | 858 ESR_INT_XDP_P1_CH0); 859 break; 860 861 default: 862 return -EINVAL; 863 } 864 865 if ((sig & mask) != val) { 866 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 867 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 868 return 0; 869 } 870 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 871 np->port, (int)(sig & mask), (int)val); 872 return -ENODEV; 873 } 874 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) 875 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 876 return 0; 877 } 878 879 static int serdes_init_1g(struct niu *np) 880 { 881 u64 val; 882 883 val = nr64(ENET_SERDES_1_PLL_CFG); 884 val &= ~ENET_SERDES_PLL_FBDIV2; 885 switch (np->port) { 886 case 0: 887 val |= ENET_SERDES_PLL_HRATE0; 888 break; 889 case 1: 890 val |= ENET_SERDES_PLL_HRATE1; 891 break; 892 case 2: 893 val |= ENET_SERDES_PLL_HRATE2; 894 break; 895 case 3: 896 val |= ENET_SERDES_PLL_HRATE3; 897 break; 898 default: 899 return -EINVAL; 900 } 901 nw64(ENET_SERDES_1_PLL_CFG, val); 902 903 return 0; 904 } 905 906 static int serdes_init_1g_serdes(struct niu *np) 907 { 908 struct niu_link_config *lp = &np->link_config; 909 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 910 u64 ctrl_val, test_cfg_val, sig, mask, val; 911 int err; 912 u64 reset_val, val_rd; 913 914 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | 915 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 | 916 ENET_SERDES_PLL_FBDIV0; 917 switch (np->port) { 918 case 0: 919 reset_val = ENET_SERDES_RESET_0; 920 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 921 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 922 pll_cfg = ENET_SERDES_0_PLL_CFG; 923 break; 924 case 1: 925 reset_val = ENET_SERDES_RESET_1; 926 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 927 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 928 pll_cfg = ENET_SERDES_1_PLL_CFG; 929 break; 930 931 default: 932 return -EINVAL; 933 } 934 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 935 ENET_SERDES_CTRL_SDET_1 | 936 ENET_SERDES_CTRL_SDET_2 | 937 ENET_SERDES_CTRL_SDET_3 | 938 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 939 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 940 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 941 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 942 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 943 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 944 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 945 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 946 test_cfg_val = 0; 947 948 if (lp->loopback_mode == LOOPBACK_PHY) { 949 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 950 ENET_SERDES_TEST_MD_0_SHIFT) | 951 (ENET_TEST_MD_PAD_LOOPBACK << 952 ENET_SERDES_TEST_MD_1_SHIFT) | 953 (ENET_TEST_MD_PAD_LOOPBACK << 954 ENET_SERDES_TEST_MD_2_SHIFT) | 955 (ENET_TEST_MD_PAD_LOOPBACK << 956 ENET_SERDES_TEST_MD_3_SHIFT)); 957 } 958 959 nw64(ENET_SERDES_RESET, reset_val); 960 mdelay(20); 961 val_rd = nr64(ENET_SERDES_RESET); 962 val_rd &= ~reset_val; 963 nw64(pll_cfg, val); 964 nw64(ctrl_reg, ctrl_val); 965 nw64(test_cfg_reg, test_cfg_val); 966 nw64(ENET_SERDES_RESET, val_rd); 967 mdelay(2000); 968 969 /* Initialize all 4 lanes of the SERDES. */ 970 for (i = 0; i < 4; i++) { 971 u32 rxtx_ctrl, glue0; 972 973 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 974 if (err) 975 return err; 976 err = esr_read_glue0(np, i, &glue0); 977 if (err) 978 return err; 979 980 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 981 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 982 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 983 984 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 985 ESR_GLUE_CTRL0_THCNT | 986 ESR_GLUE_CTRL0_BLTIME); 987 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 988 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 989 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 990 (BLTIME_300_CYCLES << 991 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 992 993 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 994 if (err) 995 return err; 996 err = esr_write_glue0(np, i, glue0); 997 if (err) 998 return err; 999 } 1000 1001 1002 sig = nr64(ESR_INT_SIGNALS); 1003 switch (np->port) { 1004 case 0: 1005 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 1006 mask = val; 1007 break; 1008 1009 case 1: 1010 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 1011 mask = val; 1012 break; 1013 1014 default: 1015 return -EINVAL; 1016 } 1017 1018 if ((sig & mask) != val) { 1019 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 1020 np->port, (int)(sig & mask), (int)val); 1021 return -ENODEV; 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int link_status_1g_serdes(struct niu *np, int *link_up_p) 1028 { 1029 struct niu_link_config *lp = &np->link_config; 1030 int link_up; 1031 u64 val; 1032 u16 current_speed; 1033 unsigned long flags; 1034 u8 current_duplex; 1035 1036 link_up = 0; 1037 current_speed = SPEED_INVALID; 1038 current_duplex = DUPLEX_INVALID; 1039 1040 spin_lock_irqsave(&np->lock, flags); 1041 1042 val = nr64_pcs(PCS_MII_STAT); 1043 1044 if (val & PCS_MII_STAT_LINK_STATUS) { 1045 link_up = 1; 1046 current_speed = SPEED_1000; 1047 current_duplex = DUPLEX_FULL; 1048 } 1049 1050 lp->active_speed = current_speed; 1051 lp->active_duplex = current_duplex; 1052 spin_unlock_irqrestore(&np->lock, flags); 1053 1054 *link_up_p = link_up; 1055 return 0; 1056 } 1057 1058 static int link_status_10g_serdes(struct niu *np, int *link_up_p) 1059 { 1060 unsigned long flags; 1061 struct niu_link_config *lp = &np->link_config; 1062 int link_up = 0; 1063 int link_ok = 1; 1064 u64 val, val2; 1065 u16 current_speed; 1066 u8 current_duplex; 1067 1068 if (!(np->flags & NIU_FLAGS_10G)) 1069 return link_status_1g_serdes(np, link_up_p); 1070 1071 current_speed = SPEED_INVALID; 1072 current_duplex = DUPLEX_INVALID; 1073 spin_lock_irqsave(&np->lock, flags); 1074 1075 val = nr64_xpcs(XPCS_STATUS(0)); 1076 val2 = nr64_mac(XMAC_INTER2); 1077 if (val2 & 0x01000000) 1078 link_ok = 0; 1079 1080 if ((val & 0x1000ULL) && link_ok) { 1081 link_up = 1; 1082 current_speed = SPEED_10000; 1083 current_duplex = DUPLEX_FULL; 1084 } 1085 lp->active_speed = current_speed; 1086 lp->active_duplex = current_duplex; 1087 spin_unlock_irqrestore(&np->lock, flags); 1088 *link_up_p = link_up; 1089 return 0; 1090 } 1091 1092 static int link_status_mii(struct niu *np, int *link_up_p) 1093 { 1094 struct niu_link_config *lp = &np->link_config; 1095 int err; 1096 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus; 1097 int supported, advertising, active_speed, active_duplex; 1098 1099 err = mii_read(np, np->phy_addr, MII_BMCR); 1100 if (unlikely(err < 0)) 1101 return err; 1102 bmcr = err; 1103 1104 err = mii_read(np, np->phy_addr, MII_BMSR); 1105 if (unlikely(err < 0)) 1106 return err; 1107 bmsr = err; 1108 1109 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1110 if (unlikely(err < 0)) 1111 return err; 1112 advert = err; 1113 1114 err = mii_read(np, np->phy_addr, MII_LPA); 1115 if (unlikely(err < 0)) 1116 return err; 1117 lpa = err; 1118 1119 if (likely(bmsr & BMSR_ESTATEN)) { 1120 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1121 if (unlikely(err < 0)) 1122 return err; 1123 estatus = err; 1124 1125 err = mii_read(np, np->phy_addr, MII_CTRL1000); 1126 if (unlikely(err < 0)) 1127 return err; 1128 ctrl1000 = err; 1129 1130 err = mii_read(np, np->phy_addr, MII_STAT1000); 1131 if (unlikely(err < 0)) 1132 return err; 1133 stat1000 = err; 1134 } else 1135 estatus = ctrl1000 = stat1000 = 0; 1136 1137 supported = 0; 1138 if (bmsr & BMSR_ANEGCAPABLE) 1139 supported |= SUPPORTED_Autoneg; 1140 if (bmsr & BMSR_10HALF) 1141 supported |= SUPPORTED_10baseT_Half; 1142 if (bmsr & BMSR_10FULL) 1143 supported |= SUPPORTED_10baseT_Full; 1144 if (bmsr & BMSR_100HALF) 1145 supported |= SUPPORTED_100baseT_Half; 1146 if (bmsr & BMSR_100FULL) 1147 supported |= SUPPORTED_100baseT_Full; 1148 if (estatus & ESTATUS_1000_THALF) 1149 supported |= SUPPORTED_1000baseT_Half; 1150 if (estatus & ESTATUS_1000_TFULL) 1151 supported |= SUPPORTED_1000baseT_Full; 1152 lp->supported = supported; 1153 1154 advertising = 0; 1155 if (advert & ADVERTISE_10HALF) 1156 advertising |= ADVERTISED_10baseT_Half; 1157 if (advert & ADVERTISE_10FULL) 1158 advertising |= ADVERTISED_10baseT_Full; 1159 if (advert & ADVERTISE_100HALF) 1160 advertising |= ADVERTISED_100baseT_Half; 1161 if (advert & ADVERTISE_100FULL) 1162 advertising |= ADVERTISED_100baseT_Full; 1163 if (ctrl1000 & ADVERTISE_1000HALF) 1164 advertising |= ADVERTISED_1000baseT_Half; 1165 if (ctrl1000 & ADVERTISE_1000FULL) 1166 advertising |= ADVERTISED_1000baseT_Full; 1167 1168 if (bmcr & BMCR_ANENABLE) { 1169 int neg, neg1000; 1170 1171 lp->active_autoneg = 1; 1172 advertising |= ADVERTISED_Autoneg; 1173 1174 neg = advert & lpa; 1175 neg1000 = (ctrl1000 << 2) & stat1000; 1176 1177 if (neg1000 & (LPA_1000FULL | LPA_1000HALF)) 1178 active_speed = SPEED_1000; 1179 else if (neg & LPA_100) 1180 active_speed = SPEED_100; 1181 else if (neg & (LPA_10HALF | LPA_10FULL)) 1182 active_speed = SPEED_10; 1183 else 1184 active_speed = SPEED_INVALID; 1185 1186 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX)) 1187 active_duplex = DUPLEX_FULL; 1188 else if (active_speed != SPEED_INVALID) 1189 active_duplex = DUPLEX_HALF; 1190 else 1191 active_duplex = DUPLEX_INVALID; 1192 } else { 1193 lp->active_autoneg = 0; 1194 1195 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100)) 1196 active_speed = SPEED_1000; 1197 else if (bmcr & BMCR_SPEED100) 1198 active_speed = SPEED_100; 1199 else 1200 active_speed = SPEED_10; 1201 1202 if (bmcr & BMCR_FULLDPLX) 1203 active_duplex = DUPLEX_FULL; 1204 else 1205 active_duplex = DUPLEX_HALF; 1206 } 1207 1208 lp->active_advertising = advertising; 1209 lp->active_speed = active_speed; 1210 lp->active_duplex = active_duplex; 1211 *link_up_p = !!(bmsr & BMSR_LSTATUS); 1212 1213 return 0; 1214 } 1215 1216 static int link_status_1g_rgmii(struct niu *np, int *link_up_p) 1217 { 1218 struct niu_link_config *lp = &np->link_config; 1219 u16 current_speed, bmsr; 1220 unsigned long flags; 1221 u8 current_duplex; 1222 int err, link_up; 1223 1224 link_up = 0; 1225 current_speed = SPEED_INVALID; 1226 current_duplex = DUPLEX_INVALID; 1227 1228 spin_lock_irqsave(&np->lock, flags); 1229 1230 err = -EINVAL; 1231 1232 err = mii_read(np, np->phy_addr, MII_BMSR); 1233 if (err < 0) 1234 goto out; 1235 1236 bmsr = err; 1237 if (bmsr & BMSR_LSTATUS) { 1238 u16 adv, lpa; 1239 1240 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1241 if (err < 0) 1242 goto out; 1243 adv = err; 1244 1245 err = mii_read(np, np->phy_addr, MII_LPA); 1246 if (err < 0) 1247 goto out; 1248 lpa = err; 1249 1250 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1251 if (err < 0) 1252 goto out; 1253 link_up = 1; 1254 current_speed = SPEED_1000; 1255 current_duplex = DUPLEX_FULL; 1256 1257 } 1258 lp->active_speed = current_speed; 1259 lp->active_duplex = current_duplex; 1260 err = 0; 1261 1262 out: 1263 spin_unlock_irqrestore(&np->lock, flags); 1264 1265 *link_up_p = link_up; 1266 return err; 1267 } 1268 1269 static int link_status_1g(struct niu *np, int *link_up_p) 1270 { 1271 struct niu_link_config *lp = &np->link_config; 1272 unsigned long flags; 1273 int err; 1274 1275 spin_lock_irqsave(&np->lock, flags); 1276 1277 err = link_status_mii(np, link_up_p); 1278 lp->supported |= SUPPORTED_TP; 1279 lp->active_advertising |= ADVERTISED_TP; 1280 1281 spin_unlock_irqrestore(&np->lock, flags); 1282 return err; 1283 } 1284 1285 static int bcm8704_reset(struct niu *np) 1286 { 1287 int err, limit; 1288 1289 err = mdio_read(np, np->phy_addr, 1290 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1291 if (err < 0 || err == 0xffff) 1292 return err; 1293 err |= BMCR_RESET; 1294 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1295 MII_BMCR, err); 1296 if (err) 1297 return err; 1298 1299 limit = 1000; 1300 while (--limit >= 0) { 1301 err = mdio_read(np, np->phy_addr, 1302 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1303 if (err < 0) 1304 return err; 1305 if (!(err & BMCR_RESET)) 1306 break; 1307 } 1308 if (limit < 0) { 1309 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n", 1310 np->port, (err & 0xffff)); 1311 return -ENODEV; 1312 } 1313 return 0; 1314 } 1315 1316 /* When written, certain PHY registers need to be read back twice 1317 * in order for the bits to settle properly. 1318 */ 1319 static int bcm8704_user_dev3_readback(struct niu *np, int reg) 1320 { 1321 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1322 if (err < 0) 1323 return err; 1324 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1325 if (err < 0) 1326 return err; 1327 return 0; 1328 } 1329 1330 static int bcm8706_init_user_dev3(struct niu *np) 1331 { 1332 int err; 1333 1334 1335 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1336 BCM8704_USER_OPT_DIGITAL_CTRL); 1337 if (err < 0) 1338 return err; 1339 err &= ~USER_ODIG_CTRL_GPIOS; 1340 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1341 err |= USER_ODIG_CTRL_RESV2; 1342 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1343 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1344 if (err) 1345 return err; 1346 1347 mdelay(1000); 1348 1349 return 0; 1350 } 1351 1352 static int bcm8704_init_user_dev3(struct niu *np) 1353 { 1354 int err; 1355 1356 err = mdio_write(np, np->phy_addr, 1357 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, 1358 (USER_CONTROL_OPTXRST_LVL | 1359 USER_CONTROL_OPBIASFLT_LVL | 1360 USER_CONTROL_OBTMPFLT_LVL | 1361 USER_CONTROL_OPPRFLT_LVL | 1362 USER_CONTROL_OPTXFLT_LVL | 1363 USER_CONTROL_OPRXLOS_LVL | 1364 USER_CONTROL_OPRXFLT_LVL | 1365 USER_CONTROL_OPTXON_LVL | 1366 (0x3f << USER_CONTROL_RES1_SHIFT))); 1367 if (err) 1368 return err; 1369 1370 err = mdio_write(np, np->phy_addr, 1371 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, 1372 (USER_PMD_TX_CTL_XFP_CLKEN | 1373 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | 1374 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | 1375 USER_PMD_TX_CTL_TSCK_LPWREN)); 1376 if (err) 1377 return err; 1378 1379 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); 1380 if (err) 1381 return err; 1382 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); 1383 if (err) 1384 return err; 1385 1386 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1387 BCM8704_USER_OPT_DIGITAL_CTRL); 1388 if (err < 0) 1389 return err; 1390 err &= ~USER_ODIG_CTRL_GPIOS; 1391 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1392 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1393 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1394 if (err) 1395 return err; 1396 1397 mdelay(1000); 1398 1399 return 0; 1400 } 1401 1402 static int mrvl88x2011_act_led(struct niu *np, int val) 1403 { 1404 int err; 1405 1406 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1407 MRVL88X2011_LED_8_TO_11_CTL); 1408 if (err < 0) 1409 return err; 1410 1411 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); 1412 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); 1413 1414 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1415 MRVL88X2011_LED_8_TO_11_CTL, err); 1416 } 1417 1418 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) 1419 { 1420 int err; 1421 1422 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1423 MRVL88X2011_LED_BLINK_CTL); 1424 if (err >= 0) { 1425 err &= ~MRVL88X2011_LED_BLKRATE_MASK; 1426 err |= (rate << 4); 1427 1428 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1429 MRVL88X2011_LED_BLINK_CTL, err); 1430 } 1431 1432 return err; 1433 } 1434 1435 static int xcvr_init_10g_mrvl88x2011(struct niu *np) 1436 { 1437 int err; 1438 1439 /* Set LED functions */ 1440 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); 1441 if (err) 1442 return err; 1443 1444 /* led activity */ 1445 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); 1446 if (err) 1447 return err; 1448 1449 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1450 MRVL88X2011_GENERAL_CTL); 1451 if (err < 0) 1452 return err; 1453 1454 err |= MRVL88X2011_ENA_XFPREFCLK; 1455 1456 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1457 MRVL88X2011_GENERAL_CTL, err); 1458 if (err < 0) 1459 return err; 1460 1461 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1462 MRVL88X2011_PMA_PMD_CTL_1); 1463 if (err < 0) 1464 return err; 1465 1466 if (np->link_config.loopback_mode == LOOPBACK_MAC) 1467 err |= MRVL88X2011_LOOPBACK; 1468 else 1469 err &= ~MRVL88X2011_LOOPBACK; 1470 1471 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1472 MRVL88X2011_PMA_PMD_CTL_1, err); 1473 if (err < 0) 1474 return err; 1475 1476 /* Enable PMD */ 1477 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1478 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); 1479 } 1480 1481 1482 static int xcvr_diag_bcm870x(struct niu *np) 1483 { 1484 u16 analog_stat0, tx_alarm_status; 1485 int err = 0; 1486 1487 #if 1 1488 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1489 MII_STAT1000); 1490 if (err < 0) 1491 return err; 1492 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err); 1493 1494 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); 1495 if (err < 0) 1496 return err; 1497 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err); 1498 1499 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1500 MII_NWAYTEST); 1501 if (err < 0) 1502 return err; 1503 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err); 1504 #endif 1505 1506 /* XXX dig this out it might not be so useful XXX */ 1507 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1508 BCM8704_USER_ANALOG_STATUS0); 1509 if (err < 0) 1510 return err; 1511 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1512 BCM8704_USER_ANALOG_STATUS0); 1513 if (err < 0) 1514 return err; 1515 analog_stat0 = err; 1516 1517 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1518 BCM8704_USER_TX_ALARM_STATUS); 1519 if (err < 0) 1520 return err; 1521 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1522 BCM8704_USER_TX_ALARM_STATUS); 1523 if (err < 0) 1524 return err; 1525 tx_alarm_status = err; 1526 1527 if (analog_stat0 != 0x03fc) { 1528 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { 1529 pr_info("Port %u cable not connected or bad cable\n", 1530 np->port); 1531 } else if (analog_stat0 == 0x639c) { 1532 pr_info("Port %u optical module is bad or missing\n", 1533 np->port); 1534 } 1535 } 1536 1537 return 0; 1538 } 1539 1540 static int xcvr_10g_set_lb_bcm870x(struct niu *np) 1541 { 1542 struct niu_link_config *lp = &np->link_config; 1543 int err; 1544 1545 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1546 MII_BMCR); 1547 if (err < 0) 1548 return err; 1549 1550 err &= ~BMCR_LOOPBACK; 1551 1552 if (lp->loopback_mode == LOOPBACK_MAC) 1553 err |= BMCR_LOOPBACK; 1554 1555 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1556 MII_BMCR, err); 1557 if (err) 1558 return err; 1559 1560 return 0; 1561 } 1562 1563 static int xcvr_init_10g_bcm8706(struct niu *np) 1564 { 1565 int err = 0; 1566 u64 val; 1567 1568 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) && 1569 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0) 1570 return err; 1571 1572 val = nr64_mac(XMAC_CONFIG); 1573 val &= ~XMAC_CONFIG_LED_POLARITY; 1574 val |= XMAC_CONFIG_FORCE_LED_ON; 1575 nw64_mac(XMAC_CONFIG, val); 1576 1577 val = nr64(MIF_CONFIG); 1578 val |= MIF_CONFIG_INDIRECT_MODE; 1579 nw64(MIF_CONFIG, val); 1580 1581 err = bcm8704_reset(np); 1582 if (err) 1583 return err; 1584 1585 err = xcvr_10g_set_lb_bcm870x(np); 1586 if (err) 1587 return err; 1588 1589 err = bcm8706_init_user_dev3(np); 1590 if (err) 1591 return err; 1592 1593 err = xcvr_diag_bcm870x(np); 1594 if (err) 1595 return err; 1596 1597 return 0; 1598 } 1599 1600 static int xcvr_init_10g_bcm8704(struct niu *np) 1601 { 1602 int err; 1603 1604 err = bcm8704_reset(np); 1605 if (err) 1606 return err; 1607 1608 err = bcm8704_init_user_dev3(np); 1609 if (err) 1610 return err; 1611 1612 err = xcvr_10g_set_lb_bcm870x(np); 1613 if (err) 1614 return err; 1615 1616 err = xcvr_diag_bcm870x(np); 1617 if (err) 1618 return err; 1619 1620 return 0; 1621 } 1622 1623 static int xcvr_init_10g(struct niu *np) 1624 { 1625 int phy_id, err; 1626 u64 val; 1627 1628 val = nr64_mac(XMAC_CONFIG); 1629 val &= ~XMAC_CONFIG_LED_POLARITY; 1630 val |= XMAC_CONFIG_FORCE_LED_ON; 1631 nw64_mac(XMAC_CONFIG, val); 1632 1633 /* XXX shared resource, lock parent XXX */ 1634 val = nr64(MIF_CONFIG); 1635 val |= MIF_CONFIG_INDIRECT_MODE; 1636 nw64(MIF_CONFIG, val); 1637 1638 phy_id = phy_decode(np->parent->port_phy, np->port); 1639 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 1640 1641 /* handle different phy types */ 1642 switch (phy_id & NIU_PHY_ID_MASK) { 1643 case NIU_PHY_ID_MRVL88X2011: 1644 err = xcvr_init_10g_mrvl88x2011(np); 1645 break; 1646 1647 default: /* bcom 8704 */ 1648 err = xcvr_init_10g_bcm8704(np); 1649 break; 1650 } 1651 1652 return err; 1653 } 1654 1655 static int mii_reset(struct niu *np) 1656 { 1657 int limit, err; 1658 1659 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); 1660 if (err) 1661 return err; 1662 1663 limit = 1000; 1664 while (--limit >= 0) { 1665 udelay(500); 1666 err = mii_read(np, np->phy_addr, MII_BMCR); 1667 if (err < 0) 1668 return err; 1669 if (!(err & BMCR_RESET)) 1670 break; 1671 } 1672 if (limit < 0) { 1673 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n", 1674 np->port, err); 1675 return -ENODEV; 1676 } 1677 1678 return 0; 1679 } 1680 1681 static int xcvr_init_1g_rgmii(struct niu *np) 1682 { 1683 int err; 1684 u64 val; 1685 u16 bmcr, bmsr, estat; 1686 1687 val = nr64(MIF_CONFIG); 1688 val &= ~MIF_CONFIG_INDIRECT_MODE; 1689 nw64(MIF_CONFIG, val); 1690 1691 err = mii_reset(np); 1692 if (err) 1693 return err; 1694 1695 err = mii_read(np, np->phy_addr, MII_BMSR); 1696 if (err < 0) 1697 return err; 1698 bmsr = err; 1699 1700 estat = 0; 1701 if (bmsr & BMSR_ESTATEN) { 1702 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1703 if (err < 0) 1704 return err; 1705 estat = err; 1706 } 1707 1708 bmcr = 0; 1709 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1710 if (err) 1711 return err; 1712 1713 if (bmsr & BMSR_ESTATEN) { 1714 u16 ctrl1000 = 0; 1715 1716 if (estat & ESTATUS_1000_TFULL) 1717 ctrl1000 |= ADVERTISE_1000FULL; 1718 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); 1719 if (err) 1720 return err; 1721 } 1722 1723 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX); 1724 1725 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1726 if (err) 1727 return err; 1728 1729 err = mii_read(np, np->phy_addr, MII_BMCR); 1730 if (err < 0) 1731 return err; 1732 bmcr = mii_read(np, np->phy_addr, MII_BMCR); 1733 1734 err = mii_read(np, np->phy_addr, MII_BMSR); 1735 if (err < 0) 1736 return err; 1737 1738 return 0; 1739 } 1740 1741 static int mii_init_common(struct niu *np) 1742 { 1743 struct niu_link_config *lp = &np->link_config; 1744 u16 bmcr, bmsr, adv, estat; 1745 int err; 1746 1747 err = mii_reset(np); 1748 if (err) 1749 return err; 1750 1751 err = mii_read(np, np->phy_addr, MII_BMSR); 1752 if (err < 0) 1753 return err; 1754 bmsr = err; 1755 1756 estat = 0; 1757 if (bmsr & BMSR_ESTATEN) { 1758 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1759 if (err < 0) 1760 return err; 1761 estat = err; 1762 } 1763 1764 bmcr = 0; 1765 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1766 if (err) 1767 return err; 1768 1769 if (lp->loopback_mode == LOOPBACK_MAC) { 1770 bmcr |= BMCR_LOOPBACK; 1771 if (lp->active_speed == SPEED_1000) 1772 bmcr |= BMCR_SPEED1000; 1773 if (lp->active_duplex == DUPLEX_FULL) 1774 bmcr |= BMCR_FULLDPLX; 1775 } 1776 1777 if (lp->loopback_mode == LOOPBACK_PHY) { 1778 u16 aux; 1779 1780 aux = (BCM5464R_AUX_CTL_EXT_LB | 1781 BCM5464R_AUX_CTL_WRITE_1); 1782 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); 1783 if (err) 1784 return err; 1785 } 1786 1787 if (lp->autoneg) { 1788 u16 ctrl1000; 1789 1790 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; 1791 if ((bmsr & BMSR_10HALF) && 1792 (lp->advertising & ADVERTISED_10baseT_Half)) 1793 adv |= ADVERTISE_10HALF; 1794 if ((bmsr & BMSR_10FULL) && 1795 (lp->advertising & ADVERTISED_10baseT_Full)) 1796 adv |= ADVERTISE_10FULL; 1797 if ((bmsr & BMSR_100HALF) && 1798 (lp->advertising & ADVERTISED_100baseT_Half)) 1799 adv |= ADVERTISE_100HALF; 1800 if ((bmsr & BMSR_100FULL) && 1801 (lp->advertising & ADVERTISED_100baseT_Full)) 1802 adv |= ADVERTISE_100FULL; 1803 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); 1804 if (err) 1805 return err; 1806 1807 if (likely(bmsr & BMSR_ESTATEN)) { 1808 ctrl1000 = 0; 1809 if ((estat & ESTATUS_1000_THALF) && 1810 (lp->advertising & ADVERTISED_1000baseT_Half)) 1811 ctrl1000 |= ADVERTISE_1000HALF; 1812 if ((estat & ESTATUS_1000_TFULL) && 1813 (lp->advertising & ADVERTISED_1000baseT_Full)) 1814 ctrl1000 |= ADVERTISE_1000FULL; 1815 err = mii_write(np, np->phy_addr, 1816 MII_CTRL1000, ctrl1000); 1817 if (err) 1818 return err; 1819 } 1820 1821 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 1822 } else { 1823 /* !lp->autoneg */ 1824 int fulldpx; 1825 1826 if (lp->duplex == DUPLEX_FULL) { 1827 bmcr |= BMCR_FULLDPLX; 1828 fulldpx = 1; 1829 } else if (lp->duplex == DUPLEX_HALF) 1830 fulldpx = 0; 1831 else 1832 return -EINVAL; 1833 1834 if (lp->speed == SPEED_1000) { 1835 /* if X-full requested while not supported, or 1836 X-half requested while not supported... */ 1837 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) || 1838 (!fulldpx && !(estat & ESTATUS_1000_THALF))) 1839 return -EINVAL; 1840 bmcr |= BMCR_SPEED1000; 1841 } else if (lp->speed == SPEED_100) { 1842 if ((fulldpx && !(bmsr & BMSR_100FULL)) || 1843 (!fulldpx && !(bmsr & BMSR_100HALF))) 1844 return -EINVAL; 1845 bmcr |= BMCR_SPEED100; 1846 } else if (lp->speed == SPEED_10) { 1847 if ((fulldpx && !(bmsr & BMSR_10FULL)) || 1848 (!fulldpx && !(bmsr & BMSR_10HALF))) 1849 return -EINVAL; 1850 } else 1851 return -EINVAL; 1852 } 1853 1854 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1855 if (err) 1856 return err; 1857 1858 #if 0 1859 err = mii_read(np, np->phy_addr, MII_BMCR); 1860 if (err < 0) 1861 return err; 1862 bmcr = err; 1863 1864 err = mii_read(np, np->phy_addr, MII_BMSR); 1865 if (err < 0) 1866 return err; 1867 bmsr = err; 1868 1869 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n", 1870 np->port, bmcr, bmsr); 1871 #endif 1872 1873 return 0; 1874 } 1875 1876 static int xcvr_init_1g(struct niu *np) 1877 { 1878 u64 val; 1879 1880 /* XXX shared resource, lock parent XXX */ 1881 val = nr64(MIF_CONFIG); 1882 val &= ~MIF_CONFIG_INDIRECT_MODE; 1883 nw64(MIF_CONFIG, val); 1884 1885 return mii_init_common(np); 1886 } 1887 1888 static int niu_xcvr_init(struct niu *np) 1889 { 1890 const struct niu_phy_ops *ops = np->phy_ops; 1891 int err; 1892 1893 err = 0; 1894 if (ops->xcvr_init) 1895 err = ops->xcvr_init(np); 1896 1897 return err; 1898 } 1899 1900 static int niu_serdes_init(struct niu *np) 1901 { 1902 const struct niu_phy_ops *ops = np->phy_ops; 1903 int err; 1904 1905 err = 0; 1906 if (ops->serdes_init) 1907 err = ops->serdes_init(np); 1908 1909 return err; 1910 } 1911 1912 static void niu_init_xif(struct niu *); 1913 static void niu_handle_led(struct niu *, int status); 1914 1915 static int niu_link_status_common(struct niu *np, int link_up) 1916 { 1917 struct niu_link_config *lp = &np->link_config; 1918 struct net_device *dev = np->dev; 1919 unsigned long flags; 1920 1921 if (!netif_carrier_ok(dev) && link_up) { 1922 netif_info(np, link, dev, "Link is up at %s, %s duplex\n", 1923 lp->active_speed == SPEED_10000 ? "10Gb/sec" : 1924 lp->active_speed == SPEED_1000 ? "1Gb/sec" : 1925 lp->active_speed == SPEED_100 ? "100Mbit/sec" : 1926 "10Mbit/sec", 1927 lp->active_duplex == DUPLEX_FULL ? "full" : "half"); 1928 1929 spin_lock_irqsave(&np->lock, flags); 1930 niu_init_xif(np); 1931 niu_handle_led(np, 1); 1932 spin_unlock_irqrestore(&np->lock, flags); 1933 1934 netif_carrier_on(dev); 1935 } else if (netif_carrier_ok(dev) && !link_up) { 1936 netif_warn(np, link, dev, "Link is down\n"); 1937 spin_lock_irqsave(&np->lock, flags); 1938 niu_handle_led(np, 0); 1939 spin_unlock_irqrestore(&np->lock, flags); 1940 netif_carrier_off(dev); 1941 } 1942 1943 return 0; 1944 } 1945 1946 static int link_status_10g_mrvl(struct niu *np, int *link_up_p) 1947 { 1948 int err, link_up, pma_status, pcs_status; 1949 1950 link_up = 0; 1951 1952 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1953 MRVL88X2011_10G_PMD_STATUS_2); 1954 if (err < 0) 1955 goto out; 1956 1957 /* Check PMA/PMD Register: 1.0001.2 == 1 */ 1958 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1959 MRVL88X2011_PMA_PMD_STATUS_1); 1960 if (err < 0) 1961 goto out; 1962 1963 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1964 1965 /* Check PMC Register : 3.0001.2 == 1: read twice */ 1966 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1967 MRVL88X2011_PMA_PMD_STATUS_1); 1968 if (err < 0) 1969 goto out; 1970 1971 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1972 MRVL88X2011_PMA_PMD_STATUS_1); 1973 if (err < 0) 1974 goto out; 1975 1976 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1977 1978 /* Check XGXS Register : 4.0018.[0-3,12] */ 1979 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, 1980 MRVL88X2011_10G_XGXS_LANE_STAT); 1981 if (err < 0) 1982 goto out; 1983 1984 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | 1985 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | 1986 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | 1987 0x800)) 1988 link_up = (pma_status && pcs_status) ? 1 : 0; 1989 1990 np->link_config.active_speed = SPEED_10000; 1991 np->link_config.active_duplex = DUPLEX_FULL; 1992 err = 0; 1993 out: 1994 mrvl88x2011_act_led(np, (link_up ? 1995 MRVL88X2011_LED_CTL_PCS_ACT : 1996 MRVL88X2011_LED_CTL_OFF)); 1997 1998 *link_up_p = link_up; 1999 return err; 2000 } 2001 2002 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p) 2003 { 2004 int err, link_up; 2005 link_up = 0; 2006 2007 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 2008 BCM8704_PMD_RCV_SIGDET); 2009 if (err < 0 || err == 0xffff) 2010 goto out; 2011 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2012 err = 0; 2013 goto out; 2014 } 2015 2016 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2017 BCM8704_PCS_10G_R_STATUS); 2018 if (err < 0) 2019 goto out; 2020 2021 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2022 err = 0; 2023 goto out; 2024 } 2025 2026 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2027 BCM8704_PHYXS_XGXS_LANE_STAT); 2028 if (err < 0) 2029 goto out; 2030 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2031 PHYXS_XGXS_LANE_STAT_MAGIC | 2032 PHYXS_XGXS_LANE_STAT_PATTEST | 2033 PHYXS_XGXS_LANE_STAT_LANE3 | 2034 PHYXS_XGXS_LANE_STAT_LANE2 | 2035 PHYXS_XGXS_LANE_STAT_LANE1 | 2036 PHYXS_XGXS_LANE_STAT_LANE0)) { 2037 err = 0; 2038 np->link_config.active_speed = SPEED_INVALID; 2039 np->link_config.active_duplex = DUPLEX_INVALID; 2040 goto out; 2041 } 2042 2043 link_up = 1; 2044 np->link_config.active_speed = SPEED_10000; 2045 np->link_config.active_duplex = DUPLEX_FULL; 2046 err = 0; 2047 2048 out: 2049 *link_up_p = link_up; 2050 return err; 2051 } 2052 2053 static int link_status_10g_bcom(struct niu *np, int *link_up_p) 2054 { 2055 int err, link_up; 2056 2057 link_up = 0; 2058 2059 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 2060 BCM8704_PMD_RCV_SIGDET); 2061 if (err < 0) 2062 goto out; 2063 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2064 err = 0; 2065 goto out; 2066 } 2067 2068 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2069 BCM8704_PCS_10G_R_STATUS); 2070 if (err < 0) 2071 goto out; 2072 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2073 err = 0; 2074 goto out; 2075 } 2076 2077 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2078 BCM8704_PHYXS_XGXS_LANE_STAT); 2079 if (err < 0) 2080 goto out; 2081 2082 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2083 PHYXS_XGXS_LANE_STAT_MAGIC | 2084 PHYXS_XGXS_LANE_STAT_LANE3 | 2085 PHYXS_XGXS_LANE_STAT_LANE2 | 2086 PHYXS_XGXS_LANE_STAT_LANE1 | 2087 PHYXS_XGXS_LANE_STAT_LANE0)) { 2088 err = 0; 2089 goto out; 2090 } 2091 2092 link_up = 1; 2093 np->link_config.active_speed = SPEED_10000; 2094 np->link_config.active_duplex = DUPLEX_FULL; 2095 err = 0; 2096 2097 out: 2098 *link_up_p = link_up; 2099 return err; 2100 } 2101 2102 static int link_status_10g(struct niu *np, int *link_up_p) 2103 { 2104 unsigned long flags; 2105 int err = -EINVAL; 2106 2107 spin_lock_irqsave(&np->lock, flags); 2108 2109 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2110 int phy_id; 2111 2112 phy_id = phy_decode(np->parent->port_phy, np->port); 2113 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 2114 2115 /* handle different phy types */ 2116 switch (phy_id & NIU_PHY_ID_MASK) { 2117 case NIU_PHY_ID_MRVL88X2011: 2118 err = link_status_10g_mrvl(np, link_up_p); 2119 break; 2120 2121 default: /* bcom 8704 */ 2122 err = link_status_10g_bcom(np, link_up_p); 2123 break; 2124 } 2125 } 2126 2127 spin_unlock_irqrestore(&np->lock, flags); 2128 2129 return err; 2130 } 2131 2132 static int niu_10g_phy_present(struct niu *np) 2133 { 2134 u64 sig, mask, val; 2135 2136 sig = nr64(ESR_INT_SIGNALS); 2137 switch (np->port) { 2138 case 0: 2139 mask = ESR_INT_SIGNALS_P0_BITS; 2140 val = (ESR_INT_SRDY0_P0 | 2141 ESR_INT_DET0_P0 | 2142 ESR_INT_XSRDY_P0 | 2143 ESR_INT_XDP_P0_CH3 | 2144 ESR_INT_XDP_P0_CH2 | 2145 ESR_INT_XDP_P0_CH1 | 2146 ESR_INT_XDP_P0_CH0); 2147 break; 2148 2149 case 1: 2150 mask = ESR_INT_SIGNALS_P1_BITS; 2151 val = (ESR_INT_SRDY0_P1 | 2152 ESR_INT_DET0_P1 | 2153 ESR_INT_XSRDY_P1 | 2154 ESR_INT_XDP_P1_CH3 | 2155 ESR_INT_XDP_P1_CH2 | 2156 ESR_INT_XDP_P1_CH1 | 2157 ESR_INT_XDP_P1_CH0); 2158 break; 2159 2160 default: 2161 return 0; 2162 } 2163 2164 if ((sig & mask) != val) 2165 return 0; 2166 return 1; 2167 } 2168 2169 static int link_status_10g_hotplug(struct niu *np, int *link_up_p) 2170 { 2171 unsigned long flags; 2172 int err = 0; 2173 int phy_present; 2174 int phy_present_prev; 2175 2176 spin_lock_irqsave(&np->lock, flags); 2177 2178 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2179 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ? 2180 1 : 0; 2181 phy_present = niu_10g_phy_present(np); 2182 if (phy_present != phy_present_prev) { 2183 /* state change */ 2184 if (phy_present) { 2185 /* A NEM was just plugged in */ 2186 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2187 if (np->phy_ops->xcvr_init) 2188 err = np->phy_ops->xcvr_init(np); 2189 if (err) { 2190 err = mdio_read(np, np->phy_addr, 2191 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 2192 if (err == 0xffff) { 2193 /* No mdio, back-to-back XAUI */ 2194 goto out; 2195 } 2196 /* debounce */ 2197 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2198 } 2199 } else { 2200 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2201 *link_up_p = 0; 2202 netif_warn(np, link, np->dev, 2203 "Hotplug PHY Removed\n"); 2204 } 2205 } 2206 out: 2207 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) { 2208 err = link_status_10g_bcm8706(np, link_up_p); 2209 if (err == 0xffff) { 2210 /* No mdio, back-to-back XAUI: it is C10NEM */ 2211 *link_up_p = 1; 2212 np->link_config.active_speed = SPEED_10000; 2213 np->link_config.active_duplex = DUPLEX_FULL; 2214 } 2215 } 2216 } 2217 2218 spin_unlock_irqrestore(&np->lock, flags); 2219 2220 return 0; 2221 } 2222 2223 static int niu_link_status(struct niu *np, int *link_up_p) 2224 { 2225 const struct niu_phy_ops *ops = np->phy_ops; 2226 int err; 2227 2228 err = 0; 2229 if (ops->link_status) 2230 err = ops->link_status(np, link_up_p); 2231 2232 return err; 2233 } 2234 2235 static void niu_timer(unsigned long __opaque) 2236 { 2237 struct niu *np = (struct niu *) __opaque; 2238 unsigned long off; 2239 int err, link_up; 2240 2241 err = niu_link_status(np, &link_up); 2242 if (!err) 2243 niu_link_status_common(np, link_up); 2244 2245 if (netif_carrier_ok(np->dev)) 2246 off = 5 * HZ; 2247 else 2248 off = 1 * HZ; 2249 np->timer.expires = jiffies + off; 2250 2251 add_timer(&np->timer); 2252 } 2253 2254 static const struct niu_phy_ops phy_ops_10g_serdes = { 2255 .serdes_init = serdes_init_10g_serdes, 2256 .link_status = link_status_10g_serdes, 2257 }; 2258 2259 static const struct niu_phy_ops phy_ops_10g_serdes_niu = { 2260 .serdes_init = serdes_init_niu_10g_serdes, 2261 .link_status = link_status_10g_serdes, 2262 }; 2263 2264 static const struct niu_phy_ops phy_ops_1g_serdes_niu = { 2265 .serdes_init = serdes_init_niu_1g_serdes, 2266 .link_status = link_status_1g_serdes, 2267 }; 2268 2269 static const struct niu_phy_ops phy_ops_1g_rgmii = { 2270 .xcvr_init = xcvr_init_1g_rgmii, 2271 .link_status = link_status_1g_rgmii, 2272 }; 2273 2274 static const struct niu_phy_ops phy_ops_10g_fiber_niu = { 2275 .serdes_init = serdes_init_niu_10g_fiber, 2276 .xcvr_init = xcvr_init_10g, 2277 .link_status = link_status_10g, 2278 }; 2279 2280 static const struct niu_phy_ops phy_ops_10g_fiber = { 2281 .serdes_init = serdes_init_10g, 2282 .xcvr_init = xcvr_init_10g, 2283 .link_status = link_status_10g, 2284 }; 2285 2286 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = { 2287 .serdes_init = serdes_init_10g, 2288 .xcvr_init = xcvr_init_10g_bcm8706, 2289 .link_status = link_status_10g_hotplug, 2290 }; 2291 2292 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = { 2293 .serdes_init = serdes_init_niu_10g_fiber, 2294 .xcvr_init = xcvr_init_10g_bcm8706, 2295 .link_status = link_status_10g_hotplug, 2296 }; 2297 2298 static const struct niu_phy_ops phy_ops_10g_copper = { 2299 .serdes_init = serdes_init_10g, 2300 .link_status = link_status_10g, /* XXX */ 2301 }; 2302 2303 static const struct niu_phy_ops phy_ops_1g_fiber = { 2304 .serdes_init = serdes_init_1g, 2305 .xcvr_init = xcvr_init_1g, 2306 .link_status = link_status_1g, 2307 }; 2308 2309 static const struct niu_phy_ops phy_ops_1g_copper = { 2310 .xcvr_init = xcvr_init_1g, 2311 .link_status = link_status_1g, 2312 }; 2313 2314 struct niu_phy_template { 2315 const struct niu_phy_ops *ops; 2316 u32 phy_addr_base; 2317 }; 2318 2319 static const struct niu_phy_template phy_template_niu_10g_fiber = { 2320 .ops = &phy_ops_10g_fiber_niu, 2321 .phy_addr_base = 16, 2322 }; 2323 2324 static const struct niu_phy_template phy_template_niu_10g_serdes = { 2325 .ops = &phy_ops_10g_serdes_niu, 2326 .phy_addr_base = 0, 2327 }; 2328 2329 static const struct niu_phy_template phy_template_niu_1g_serdes = { 2330 .ops = &phy_ops_1g_serdes_niu, 2331 .phy_addr_base = 0, 2332 }; 2333 2334 static const struct niu_phy_template phy_template_10g_fiber = { 2335 .ops = &phy_ops_10g_fiber, 2336 .phy_addr_base = 8, 2337 }; 2338 2339 static const struct niu_phy_template phy_template_10g_fiber_hotplug = { 2340 .ops = &phy_ops_10g_fiber_hotplug, 2341 .phy_addr_base = 8, 2342 }; 2343 2344 static const struct niu_phy_template phy_template_niu_10g_hotplug = { 2345 .ops = &phy_ops_niu_10g_hotplug, 2346 .phy_addr_base = 8, 2347 }; 2348 2349 static const struct niu_phy_template phy_template_10g_copper = { 2350 .ops = &phy_ops_10g_copper, 2351 .phy_addr_base = 10, 2352 }; 2353 2354 static const struct niu_phy_template phy_template_1g_fiber = { 2355 .ops = &phy_ops_1g_fiber, 2356 .phy_addr_base = 0, 2357 }; 2358 2359 static const struct niu_phy_template phy_template_1g_copper = { 2360 .ops = &phy_ops_1g_copper, 2361 .phy_addr_base = 0, 2362 }; 2363 2364 static const struct niu_phy_template phy_template_1g_rgmii = { 2365 .ops = &phy_ops_1g_rgmii, 2366 .phy_addr_base = 0, 2367 }; 2368 2369 static const struct niu_phy_template phy_template_10g_serdes = { 2370 .ops = &phy_ops_10g_serdes, 2371 .phy_addr_base = 0, 2372 }; 2373 2374 static int niu_atca_port_num[4] = { 2375 0, 0, 11, 10 2376 }; 2377 2378 static int serdes_init_10g_serdes(struct niu *np) 2379 { 2380 struct niu_link_config *lp = &np->link_config; 2381 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 2382 u64 ctrl_val, test_cfg_val, sig, mask, val; 2383 2384 switch (np->port) { 2385 case 0: 2386 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 2387 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 2388 pll_cfg = ENET_SERDES_0_PLL_CFG; 2389 break; 2390 case 1: 2391 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 2392 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 2393 pll_cfg = ENET_SERDES_1_PLL_CFG; 2394 break; 2395 2396 default: 2397 return -EINVAL; 2398 } 2399 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 2400 ENET_SERDES_CTRL_SDET_1 | 2401 ENET_SERDES_CTRL_SDET_2 | 2402 ENET_SERDES_CTRL_SDET_3 | 2403 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 2404 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 2405 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 2406 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 2407 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 2408 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 2409 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 2410 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 2411 test_cfg_val = 0; 2412 2413 if (lp->loopback_mode == LOOPBACK_PHY) { 2414 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 2415 ENET_SERDES_TEST_MD_0_SHIFT) | 2416 (ENET_TEST_MD_PAD_LOOPBACK << 2417 ENET_SERDES_TEST_MD_1_SHIFT) | 2418 (ENET_TEST_MD_PAD_LOOPBACK << 2419 ENET_SERDES_TEST_MD_2_SHIFT) | 2420 (ENET_TEST_MD_PAD_LOOPBACK << 2421 ENET_SERDES_TEST_MD_3_SHIFT)); 2422 } 2423 2424 esr_reset(np); 2425 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2); 2426 nw64(ctrl_reg, ctrl_val); 2427 nw64(test_cfg_reg, test_cfg_val); 2428 2429 /* Initialize all 4 lanes of the SERDES. */ 2430 for (i = 0; i < 4; i++) { 2431 u32 rxtx_ctrl, glue0; 2432 int err; 2433 2434 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 2435 if (err) 2436 return err; 2437 err = esr_read_glue0(np, i, &glue0); 2438 if (err) 2439 return err; 2440 2441 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 2442 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 2443 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 2444 2445 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 2446 ESR_GLUE_CTRL0_THCNT | 2447 ESR_GLUE_CTRL0_BLTIME); 2448 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 2449 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 2450 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 2451 (BLTIME_300_CYCLES << 2452 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 2453 2454 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 2455 if (err) 2456 return err; 2457 err = esr_write_glue0(np, i, glue0); 2458 if (err) 2459 return err; 2460 } 2461 2462 2463 sig = nr64(ESR_INT_SIGNALS); 2464 switch (np->port) { 2465 case 0: 2466 mask = ESR_INT_SIGNALS_P0_BITS; 2467 val = (ESR_INT_SRDY0_P0 | 2468 ESR_INT_DET0_P0 | 2469 ESR_INT_XSRDY_P0 | 2470 ESR_INT_XDP_P0_CH3 | 2471 ESR_INT_XDP_P0_CH2 | 2472 ESR_INT_XDP_P0_CH1 | 2473 ESR_INT_XDP_P0_CH0); 2474 break; 2475 2476 case 1: 2477 mask = ESR_INT_SIGNALS_P1_BITS; 2478 val = (ESR_INT_SRDY0_P1 | 2479 ESR_INT_DET0_P1 | 2480 ESR_INT_XSRDY_P1 | 2481 ESR_INT_XDP_P1_CH3 | 2482 ESR_INT_XDP_P1_CH2 | 2483 ESR_INT_XDP_P1_CH1 | 2484 ESR_INT_XDP_P1_CH0); 2485 break; 2486 2487 default: 2488 return -EINVAL; 2489 } 2490 2491 if ((sig & mask) != val) { 2492 int err; 2493 err = serdes_init_1g_serdes(np); 2494 if (!err) { 2495 np->flags &= ~NIU_FLAGS_10G; 2496 np->mac_xcvr = MAC_XCVR_PCS; 2497 } else { 2498 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 2499 np->port); 2500 return -ENODEV; 2501 } 2502 } 2503 2504 return 0; 2505 } 2506 2507 static int niu_determine_phy_disposition(struct niu *np) 2508 { 2509 struct niu_parent *parent = np->parent; 2510 u8 plat_type = parent->plat_type; 2511 const struct niu_phy_template *tp; 2512 u32 phy_addr_off = 0; 2513 2514 if (plat_type == PLAT_TYPE_NIU) { 2515 switch (np->flags & 2516 (NIU_FLAGS_10G | 2517 NIU_FLAGS_FIBER | 2518 NIU_FLAGS_XCVR_SERDES)) { 2519 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2520 /* 10G Serdes */ 2521 tp = &phy_template_niu_10g_serdes; 2522 break; 2523 case NIU_FLAGS_XCVR_SERDES: 2524 /* 1G Serdes */ 2525 tp = &phy_template_niu_1g_serdes; 2526 break; 2527 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2528 /* 10G Fiber */ 2529 default: 2530 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2531 tp = &phy_template_niu_10g_hotplug; 2532 if (np->port == 0) 2533 phy_addr_off = 8; 2534 if (np->port == 1) 2535 phy_addr_off = 12; 2536 } else { 2537 tp = &phy_template_niu_10g_fiber; 2538 phy_addr_off += np->port; 2539 } 2540 break; 2541 } 2542 } else { 2543 switch (np->flags & 2544 (NIU_FLAGS_10G | 2545 NIU_FLAGS_FIBER | 2546 NIU_FLAGS_XCVR_SERDES)) { 2547 case 0: 2548 /* 1G copper */ 2549 tp = &phy_template_1g_copper; 2550 if (plat_type == PLAT_TYPE_VF_P0) 2551 phy_addr_off = 10; 2552 else if (plat_type == PLAT_TYPE_VF_P1) 2553 phy_addr_off = 26; 2554 2555 phy_addr_off += (np->port ^ 0x3); 2556 break; 2557 2558 case NIU_FLAGS_10G: 2559 /* 10G copper */ 2560 tp = &phy_template_10g_copper; 2561 break; 2562 2563 case NIU_FLAGS_FIBER: 2564 /* 1G fiber */ 2565 tp = &phy_template_1g_fiber; 2566 break; 2567 2568 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2569 /* 10G fiber */ 2570 tp = &phy_template_10g_fiber; 2571 if (plat_type == PLAT_TYPE_VF_P0 || 2572 plat_type == PLAT_TYPE_VF_P1) 2573 phy_addr_off = 8; 2574 phy_addr_off += np->port; 2575 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2576 tp = &phy_template_10g_fiber_hotplug; 2577 if (np->port == 0) 2578 phy_addr_off = 8; 2579 if (np->port == 1) 2580 phy_addr_off = 12; 2581 } 2582 break; 2583 2584 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2585 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 2586 case NIU_FLAGS_XCVR_SERDES: 2587 switch(np->port) { 2588 case 0: 2589 case 1: 2590 tp = &phy_template_10g_serdes; 2591 break; 2592 case 2: 2593 case 3: 2594 tp = &phy_template_1g_rgmii; 2595 break; 2596 default: 2597 return -EINVAL; 2598 break; 2599 } 2600 phy_addr_off = niu_atca_port_num[np->port]; 2601 break; 2602 2603 default: 2604 return -EINVAL; 2605 } 2606 } 2607 2608 np->phy_ops = tp->ops; 2609 np->phy_addr = tp->phy_addr_base + phy_addr_off; 2610 2611 return 0; 2612 } 2613 2614 static int niu_init_link(struct niu *np) 2615 { 2616 struct niu_parent *parent = np->parent; 2617 int err, ignore; 2618 2619 if (parent->plat_type == PLAT_TYPE_NIU) { 2620 err = niu_xcvr_init(np); 2621 if (err) 2622 return err; 2623 msleep(200); 2624 } 2625 err = niu_serdes_init(np); 2626 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2627 return err; 2628 msleep(200); 2629 err = niu_xcvr_init(np); 2630 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2631 niu_link_status(np, &ignore); 2632 return 0; 2633 } 2634 2635 static void niu_set_primary_mac(struct niu *np, unsigned char *addr) 2636 { 2637 u16 reg0 = addr[4] << 8 | addr[5]; 2638 u16 reg1 = addr[2] << 8 | addr[3]; 2639 u16 reg2 = addr[0] << 8 | addr[1]; 2640 2641 if (np->flags & NIU_FLAGS_XMAC) { 2642 nw64_mac(XMAC_ADDR0, reg0); 2643 nw64_mac(XMAC_ADDR1, reg1); 2644 nw64_mac(XMAC_ADDR2, reg2); 2645 } else { 2646 nw64_mac(BMAC_ADDR0, reg0); 2647 nw64_mac(BMAC_ADDR1, reg1); 2648 nw64_mac(BMAC_ADDR2, reg2); 2649 } 2650 } 2651 2652 static int niu_num_alt_addr(struct niu *np) 2653 { 2654 if (np->flags & NIU_FLAGS_XMAC) 2655 return XMAC_NUM_ALT_ADDR; 2656 else 2657 return BMAC_NUM_ALT_ADDR; 2658 } 2659 2660 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr) 2661 { 2662 u16 reg0 = addr[4] << 8 | addr[5]; 2663 u16 reg1 = addr[2] << 8 | addr[3]; 2664 u16 reg2 = addr[0] << 8 | addr[1]; 2665 2666 if (index >= niu_num_alt_addr(np)) 2667 return -EINVAL; 2668 2669 if (np->flags & NIU_FLAGS_XMAC) { 2670 nw64_mac(XMAC_ALT_ADDR0(index), reg0); 2671 nw64_mac(XMAC_ALT_ADDR1(index), reg1); 2672 nw64_mac(XMAC_ALT_ADDR2(index), reg2); 2673 } else { 2674 nw64_mac(BMAC_ALT_ADDR0(index), reg0); 2675 nw64_mac(BMAC_ALT_ADDR1(index), reg1); 2676 nw64_mac(BMAC_ALT_ADDR2(index), reg2); 2677 } 2678 2679 return 0; 2680 } 2681 2682 static int niu_enable_alt_mac(struct niu *np, int index, int on) 2683 { 2684 unsigned long reg; 2685 u64 val, mask; 2686 2687 if (index >= niu_num_alt_addr(np)) 2688 return -EINVAL; 2689 2690 if (np->flags & NIU_FLAGS_XMAC) { 2691 reg = XMAC_ADDR_CMPEN; 2692 mask = 1 << index; 2693 } else { 2694 reg = BMAC_ADDR_CMPEN; 2695 mask = 1 << (index + 1); 2696 } 2697 2698 val = nr64_mac(reg); 2699 if (on) 2700 val |= mask; 2701 else 2702 val &= ~mask; 2703 nw64_mac(reg, val); 2704 2705 return 0; 2706 } 2707 2708 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, 2709 int num, int mac_pref) 2710 { 2711 u64 val = nr64_mac(reg); 2712 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); 2713 val |= num; 2714 if (mac_pref) 2715 val |= HOST_INFO_MPR; 2716 nw64_mac(reg, val); 2717 } 2718 2719 static int __set_rdc_table_num(struct niu *np, 2720 int xmac_index, int bmac_index, 2721 int rdc_table_num, int mac_pref) 2722 { 2723 unsigned long reg; 2724 2725 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN) 2726 return -EINVAL; 2727 if (np->flags & NIU_FLAGS_XMAC) 2728 reg = XMAC_HOST_INFO(xmac_index); 2729 else 2730 reg = BMAC_HOST_INFO(bmac_index); 2731 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); 2732 return 0; 2733 } 2734 2735 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num, 2736 int mac_pref) 2737 { 2738 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref); 2739 } 2740 2741 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num, 2742 int mac_pref) 2743 { 2744 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref); 2745 } 2746 2747 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx, 2748 int table_num, int mac_pref) 2749 { 2750 if (idx >= niu_num_alt_addr(np)) 2751 return -EINVAL; 2752 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref); 2753 } 2754 2755 static u64 vlan_entry_set_parity(u64 reg_val) 2756 { 2757 u64 port01_mask; 2758 u64 port23_mask; 2759 2760 port01_mask = 0x00ff; 2761 port23_mask = 0xff00; 2762 2763 if (hweight64(reg_val & port01_mask) & 1) 2764 reg_val |= ENET_VLAN_TBL_PARITY0; 2765 else 2766 reg_val &= ~ENET_VLAN_TBL_PARITY0; 2767 2768 if (hweight64(reg_val & port23_mask) & 1) 2769 reg_val |= ENET_VLAN_TBL_PARITY1; 2770 else 2771 reg_val &= ~ENET_VLAN_TBL_PARITY1; 2772 2773 return reg_val; 2774 } 2775 2776 static void vlan_tbl_write(struct niu *np, unsigned long index, 2777 int port, int vpr, int rdc_table) 2778 { 2779 u64 reg_val = nr64(ENET_VLAN_TBL(index)); 2780 2781 reg_val &= ~((ENET_VLAN_TBL_VPR | 2782 ENET_VLAN_TBL_VLANRDCTBLN) << 2783 ENET_VLAN_TBL_SHIFT(port)); 2784 if (vpr) 2785 reg_val |= (ENET_VLAN_TBL_VPR << 2786 ENET_VLAN_TBL_SHIFT(port)); 2787 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); 2788 2789 reg_val = vlan_entry_set_parity(reg_val); 2790 2791 nw64(ENET_VLAN_TBL(index), reg_val); 2792 } 2793 2794 static void vlan_tbl_clear(struct niu *np) 2795 { 2796 int i; 2797 2798 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) 2799 nw64(ENET_VLAN_TBL(i), 0); 2800 } 2801 2802 static int tcam_wait_bit(struct niu *np, u64 bit) 2803 { 2804 int limit = 1000; 2805 2806 while (--limit > 0) { 2807 if (nr64(TCAM_CTL) & bit) 2808 break; 2809 udelay(1); 2810 } 2811 if (limit <= 0) 2812 return -ENODEV; 2813 2814 return 0; 2815 } 2816 2817 static int tcam_flush(struct niu *np, int index) 2818 { 2819 nw64(TCAM_KEY_0, 0x00); 2820 nw64(TCAM_KEY_MASK_0, 0xff); 2821 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2822 2823 return tcam_wait_bit(np, TCAM_CTL_STAT); 2824 } 2825 2826 #if 0 2827 static int tcam_read(struct niu *np, int index, 2828 u64 *key, u64 *mask) 2829 { 2830 int err; 2831 2832 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index)); 2833 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2834 if (!err) { 2835 key[0] = nr64(TCAM_KEY_0); 2836 key[1] = nr64(TCAM_KEY_1); 2837 key[2] = nr64(TCAM_KEY_2); 2838 key[3] = nr64(TCAM_KEY_3); 2839 mask[0] = nr64(TCAM_KEY_MASK_0); 2840 mask[1] = nr64(TCAM_KEY_MASK_1); 2841 mask[2] = nr64(TCAM_KEY_MASK_2); 2842 mask[3] = nr64(TCAM_KEY_MASK_3); 2843 } 2844 return err; 2845 } 2846 #endif 2847 2848 static int tcam_write(struct niu *np, int index, 2849 u64 *key, u64 *mask) 2850 { 2851 nw64(TCAM_KEY_0, key[0]); 2852 nw64(TCAM_KEY_1, key[1]); 2853 nw64(TCAM_KEY_2, key[2]); 2854 nw64(TCAM_KEY_3, key[3]); 2855 nw64(TCAM_KEY_MASK_0, mask[0]); 2856 nw64(TCAM_KEY_MASK_1, mask[1]); 2857 nw64(TCAM_KEY_MASK_2, mask[2]); 2858 nw64(TCAM_KEY_MASK_3, mask[3]); 2859 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2860 2861 return tcam_wait_bit(np, TCAM_CTL_STAT); 2862 } 2863 2864 #if 0 2865 static int tcam_assoc_read(struct niu *np, int index, u64 *data) 2866 { 2867 int err; 2868 2869 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index)); 2870 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2871 if (!err) 2872 *data = nr64(TCAM_KEY_1); 2873 2874 return err; 2875 } 2876 #endif 2877 2878 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data) 2879 { 2880 nw64(TCAM_KEY_1, assoc_data); 2881 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); 2882 2883 return tcam_wait_bit(np, TCAM_CTL_STAT); 2884 } 2885 2886 static void tcam_enable(struct niu *np, int on) 2887 { 2888 u64 val = nr64(FFLP_CFG_1); 2889 2890 if (on) 2891 val &= ~FFLP_CFG_1_TCAM_DIS; 2892 else 2893 val |= FFLP_CFG_1_TCAM_DIS; 2894 nw64(FFLP_CFG_1, val); 2895 } 2896 2897 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio) 2898 { 2899 u64 val = nr64(FFLP_CFG_1); 2900 2901 val &= ~(FFLP_CFG_1_FFLPINITDONE | 2902 FFLP_CFG_1_CAMLAT | 2903 FFLP_CFG_1_CAMRATIO); 2904 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); 2905 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); 2906 nw64(FFLP_CFG_1, val); 2907 2908 val = nr64(FFLP_CFG_1); 2909 val |= FFLP_CFG_1_FFLPINITDONE; 2910 nw64(FFLP_CFG_1, val); 2911 } 2912 2913 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class, 2914 int on) 2915 { 2916 unsigned long reg; 2917 u64 val; 2918 2919 if (class < CLASS_CODE_ETHERTYPE1 || 2920 class > CLASS_CODE_ETHERTYPE2) 2921 return -EINVAL; 2922 2923 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2924 val = nr64(reg); 2925 if (on) 2926 val |= L2_CLS_VLD; 2927 else 2928 val &= ~L2_CLS_VLD; 2929 nw64(reg, val); 2930 2931 return 0; 2932 } 2933 2934 #if 0 2935 static int tcam_user_eth_class_set(struct niu *np, unsigned long class, 2936 u64 ether_type) 2937 { 2938 unsigned long reg; 2939 u64 val; 2940 2941 if (class < CLASS_CODE_ETHERTYPE1 || 2942 class > CLASS_CODE_ETHERTYPE2 || 2943 (ether_type & ~(u64)0xffff) != 0) 2944 return -EINVAL; 2945 2946 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2947 val = nr64(reg); 2948 val &= ~L2_CLS_ETYPE; 2949 val |= (ether_type << L2_CLS_ETYPE_SHIFT); 2950 nw64(reg, val); 2951 2952 return 0; 2953 } 2954 #endif 2955 2956 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class, 2957 int on) 2958 { 2959 unsigned long reg; 2960 u64 val; 2961 2962 if (class < CLASS_CODE_USER_PROG1 || 2963 class > CLASS_CODE_USER_PROG4) 2964 return -EINVAL; 2965 2966 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2967 val = nr64(reg); 2968 if (on) 2969 val |= L3_CLS_VALID; 2970 else 2971 val &= ~L3_CLS_VALID; 2972 nw64(reg, val); 2973 2974 return 0; 2975 } 2976 2977 static int tcam_user_ip_class_set(struct niu *np, unsigned long class, 2978 int ipv6, u64 protocol_id, 2979 u64 tos_mask, u64 tos_val) 2980 { 2981 unsigned long reg; 2982 u64 val; 2983 2984 if (class < CLASS_CODE_USER_PROG1 || 2985 class > CLASS_CODE_USER_PROG4 || 2986 (protocol_id & ~(u64)0xff) != 0 || 2987 (tos_mask & ~(u64)0xff) != 0 || 2988 (tos_val & ~(u64)0xff) != 0) 2989 return -EINVAL; 2990 2991 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2992 val = nr64(reg); 2993 val &= ~(L3_CLS_IPVER | L3_CLS_PID | 2994 L3_CLS_TOSMASK | L3_CLS_TOS); 2995 if (ipv6) 2996 val |= L3_CLS_IPVER; 2997 val |= (protocol_id << L3_CLS_PID_SHIFT); 2998 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); 2999 val |= (tos_val << L3_CLS_TOS_SHIFT); 3000 nw64(reg, val); 3001 3002 return 0; 3003 } 3004 3005 static int tcam_early_init(struct niu *np) 3006 { 3007 unsigned long i; 3008 int err; 3009 3010 tcam_enable(np, 0); 3011 tcam_set_lat_and_ratio(np, 3012 DEFAULT_TCAM_LATENCY, 3013 DEFAULT_TCAM_ACCESS_RATIO); 3014 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) { 3015 err = tcam_user_eth_class_enable(np, i, 0); 3016 if (err) 3017 return err; 3018 } 3019 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) { 3020 err = tcam_user_ip_class_enable(np, i, 0); 3021 if (err) 3022 return err; 3023 } 3024 3025 return 0; 3026 } 3027 3028 static int tcam_flush_all(struct niu *np) 3029 { 3030 unsigned long i; 3031 3032 for (i = 0; i < np->parent->tcam_num_entries; i++) { 3033 int err = tcam_flush(np, i); 3034 if (err) 3035 return err; 3036 } 3037 return 0; 3038 } 3039 3040 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries) 3041 { 3042 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0); 3043 } 3044 3045 #if 0 3046 static int hash_read(struct niu *np, unsigned long partition, 3047 unsigned long index, unsigned long num_entries, 3048 u64 *data) 3049 { 3050 u64 val = hash_addr_regval(index, num_entries); 3051 unsigned long i; 3052 3053 if (partition >= FCRAM_NUM_PARTITIONS || 3054 index + num_entries > FCRAM_SIZE) 3055 return -EINVAL; 3056 3057 nw64(HASH_TBL_ADDR(partition), val); 3058 for (i = 0; i < num_entries; i++) 3059 data[i] = nr64(HASH_TBL_DATA(partition)); 3060 3061 return 0; 3062 } 3063 #endif 3064 3065 static int hash_write(struct niu *np, unsigned long partition, 3066 unsigned long index, unsigned long num_entries, 3067 u64 *data) 3068 { 3069 u64 val = hash_addr_regval(index, num_entries); 3070 unsigned long i; 3071 3072 if (partition >= FCRAM_NUM_PARTITIONS || 3073 index + (num_entries * 8) > FCRAM_SIZE) 3074 return -EINVAL; 3075 3076 nw64(HASH_TBL_ADDR(partition), val); 3077 for (i = 0; i < num_entries; i++) 3078 nw64(HASH_TBL_DATA(partition), data[i]); 3079 3080 return 0; 3081 } 3082 3083 static void fflp_reset(struct niu *np) 3084 { 3085 u64 val; 3086 3087 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); 3088 udelay(10); 3089 nw64(FFLP_CFG_1, 0); 3090 3091 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; 3092 nw64(FFLP_CFG_1, val); 3093 } 3094 3095 static void fflp_set_timings(struct niu *np) 3096 { 3097 u64 val = nr64(FFLP_CFG_1); 3098 3099 val &= ~FFLP_CFG_1_FFLPINITDONE; 3100 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); 3101 nw64(FFLP_CFG_1, val); 3102 3103 val = nr64(FFLP_CFG_1); 3104 val |= FFLP_CFG_1_FFLPINITDONE; 3105 nw64(FFLP_CFG_1, val); 3106 3107 val = nr64(FCRAM_REF_TMR); 3108 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); 3109 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); 3110 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); 3111 nw64(FCRAM_REF_TMR, val); 3112 } 3113 3114 static int fflp_set_partition(struct niu *np, u64 partition, 3115 u64 mask, u64 base, int enable) 3116 { 3117 unsigned long reg; 3118 u64 val; 3119 3120 if (partition >= FCRAM_NUM_PARTITIONS || 3121 (mask & ~(u64)0x1f) != 0 || 3122 (base & ~(u64)0x1f) != 0) 3123 return -EINVAL; 3124 3125 reg = FLW_PRT_SEL(partition); 3126 3127 val = nr64(reg); 3128 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); 3129 val |= (mask << FLW_PRT_SEL_MASK_SHIFT); 3130 val |= (base << FLW_PRT_SEL_BASE_SHIFT); 3131 if (enable) 3132 val |= FLW_PRT_SEL_EXT; 3133 nw64(reg, val); 3134 3135 return 0; 3136 } 3137 3138 static int fflp_disable_all_partitions(struct niu *np) 3139 { 3140 unsigned long i; 3141 3142 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) { 3143 int err = fflp_set_partition(np, 0, 0, 0, 0); 3144 if (err) 3145 return err; 3146 } 3147 return 0; 3148 } 3149 3150 static void fflp_llcsnap_enable(struct niu *np, int on) 3151 { 3152 u64 val = nr64(FFLP_CFG_1); 3153 3154 if (on) 3155 val |= FFLP_CFG_1_LLCSNAP; 3156 else 3157 val &= ~FFLP_CFG_1_LLCSNAP; 3158 nw64(FFLP_CFG_1, val); 3159 } 3160 3161 static void fflp_errors_enable(struct niu *np, int on) 3162 { 3163 u64 val = nr64(FFLP_CFG_1); 3164 3165 if (on) 3166 val &= ~FFLP_CFG_1_ERRORDIS; 3167 else 3168 val |= FFLP_CFG_1_ERRORDIS; 3169 nw64(FFLP_CFG_1, val); 3170 } 3171 3172 static int fflp_hash_clear(struct niu *np) 3173 { 3174 struct fcram_hash_ipv4 ent; 3175 unsigned long i; 3176 3177 /* IPV4 hash entry with valid bit clear, rest is don't care. */ 3178 memset(&ent, 0, sizeof(ent)); 3179 ent.header = HASH_HEADER_EXT; 3180 3181 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) { 3182 int err = hash_write(np, 0, i, 1, (u64 *) &ent); 3183 if (err) 3184 return err; 3185 } 3186 return 0; 3187 } 3188 3189 static int fflp_early_init(struct niu *np) 3190 { 3191 struct niu_parent *parent; 3192 unsigned long flags; 3193 int err; 3194 3195 niu_lock_parent(np, flags); 3196 3197 parent = np->parent; 3198 err = 0; 3199 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) { 3200 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3201 fflp_reset(np); 3202 fflp_set_timings(np); 3203 err = fflp_disable_all_partitions(np); 3204 if (err) { 3205 netif_printk(np, probe, KERN_DEBUG, np->dev, 3206 "fflp_disable_all_partitions failed, err=%d\n", 3207 err); 3208 goto out; 3209 } 3210 } 3211 3212 err = tcam_early_init(np); 3213 if (err) { 3214 netif_printk(np, probe, KERN_DEBUG, np->dev, 3215 "tcam_early_init failed, err=%d\n", err); 3216 goto out; 3217 } 3218 fflp_llcsnap_enable(np, 1); 3219 fflp_errors_enable(np, 0); 3220 nw64(H1POLY, 0); 3221 nw64(H2POLY, 0); 3222 3223 err = tcam_flush_all(np); 3224 if (err) { 3225 netif_printk(np, probe, KERN_DEBUG, np->dev, 3226 "tcam_flush_all failed, err=%d\n", err); 3227 goto out; 3228 } 3229 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3230 err = fflp_hash_clear(np); 3231 if (err) { 3232 netif_printk(np, probe, KERN_DEBUG, np->dev, 3233 "fflp_hash_clear failed, err=%d\n", 3234 err); 3235 goto out; 3236 } 3237 } 3238 3239 vlan_tbl_clear(np); 3240 3241 parent->flags |= PARENT_FLGS_CLS_HWINIT; 3242 } 3243 out: 3244 niu_unlock_parent(np, flags); 3245 return err; 3246 } 3247 3248 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key) 3249 { 3250 if (class_code < CLASS_CODE_USER_PROG1 || 3251 class_code > CLASS_CODE_SCTP_IPV6) 3252 return -EINVAL; 3253 3254 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3255 return 0; 3256 } 3257 3258 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key) 3259 { 3260 if (class_code < CLASS_CODE_USER_PROG1 || 3261 class_code > CLASS_CODE_SCTP_IPV6) 3262 return -EINVAL; 3263 3264 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3265 return 0; 3266 } 3267 3268 /* Entries for the ports are interleaved in the TCAM */ 3269 static u16 tcam_get_index(struct niu *np, u16 idx) 3270 { 3271 /* One entry reserved for IP fragment rule */ 3272 if (idx >= (np->clas.tcam_sz - 1)) 3273 idx = 0; 3274 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports); 3275 } 3276 3277 static u16 tcam_get_size(struct niu *np) 3278 { 3279 /* One entry reserved for IP fragment rule */ 3280 return np->clas.tcam_sz - 1; 3281 } 3282 3283 static u16 tcam_get_valid_entry_cnt(struct niu *np) 3284 { 3285 /* One entry reserved for IP fragment rule */ 3286 return np->clas.tcam_valid_entries - 1; 3287 } 3288 3289 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page, 3290 u32 offset, u32 size, u32 truesize) 3291 { 3292 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size); 3293 3294 skb->len += size; 3295 skb->data_len += size; 3296 skb->truesize += truesize; 3297 } 3298 3299 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a) 3300 { 3301 a >>= PAGE_SHIFT; 3302 a ^= (a >> ilog2(MAX_RBR_RING_SIZE)); 3303 3304 return a & (MAX_RBR_RING_SIZE - 1); 3305 } 3306 3307 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr, 3308 struct page ***link) 3309 { 3310 unsigned int h = niu_hash_rxaddr(rp, addr); 3311 struct page *p, **pp; 3312 3313 addr &= PAGE_MASK; 3314 pp = &rp->rxhash[h]; 3315 for (; (p = *pp) != NULL; pp = (struct page **) &p->mapping) { 3316 if (p->index == addr) { 3317 *link = pp; 3318 goto found; 3319 } 3320 } 3321 BUG(); 3322 3323 found: 3324 return p; 3325 } 3326 3327 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) 3328 { 3329 unsigned int h = niu_hash_rxaddr(rp, base); 3330 3331 page->index = base; 3332 page->mapping = (struct address_space *) rp->rxhash[h]; 3333 rp->rxhash[h] = page; 3334 } 3335 3336 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp, 3337 gfp_t mask, int start_index) 3338 { 3339 struct page *page; 3340 u64 addr; 3341 int i; 3342 3343 page = alloc_page(mask); 3344 if (!page) 3345 return -ENOMEM; 3346 3347 addr = np->ops->map_page(np->device, page, 0, 3348 PAGE_SIZE, DMA_FROM_DEVICE); 3349 3350 niu_hash_page(rp, page, addr); 3351 if (rp->rbr_blocks_per_page > 1) 3352 atomic_add(rp->rbr_blocks_per_page - 1, 3353 &compound_head(page)->_count); 3354 3355 for (i = 0; i < rp->rbr_blocks_per_page; i++) { 3356 __le32 *rbr = &rp->rbr[start_index + i]; 3357 3358 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT); 3359 addr += rp->rbr_block_size; 3360 } 3361 3362 return 0; 3363 } 3364 3365 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3366 { 3367 int index = rp->rbr_index; 3368 3369 rp->rbr_pending++; 3370 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) { 3371 int err = niu_rbr_add_page(np, rp, mask, index); 3372 3373 if (unlikely(err)) { 3374 rp->rbr_pending--; 3375 return; 3376 } 3377 3378 rp->rbr_index += rp->rbr_blocks_per_page; 3379 BUG_ON(rp->rbr_index > rp->rbr_table_size); 3380 if (rp->rbr_index == rp->rbr_table_size) 3381 rp->rbr_index = 0; 3382 3383 if (rp->rbr_pending >= rp->rbr_kick_thresh) { 3384 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); 3385 rp->rbr_pending = 0; 3386 } 3387 } 3388 } 3389 3390 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp) 3391 { 3392 unsigned int index = rp->rcr_index; 3393 int num_rcr = 0; 3394 3395 rp->rx_dropped++; 3396 while (1) { 3397 struct page *page, **link; 3398 u64 addr, val; 3399 u32 rcr_size; 3400 3401 num_rcr++; 3402 3403 val = le64_to_cpup(&rp->rcr[index]); 3404 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3405 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3406 page = niu_find_rxpage(rp, addr, &link); 3407 3408 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3409 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3410 if ((page->index + PAGE_SIZE) - rcr_size == addr) { 3411 *link = (struct page *) page->mapping; 3412 np->ops->unmap_page(np->device, page->index, 3413 PAGE_SIZE, DMA_FROM_DEVICE); 3414 page->index = 0; 3415 page->mapping = NULL; 3416 __free_page(page); 3417 rp->rbr_refill_pending++; 3418 } 3419 3420 index = NEXT_RCR(rp, index); 3421 if (!(val & RCR_ENTRY_MULTI)) 3422 break; 3423 3424 } 3425 rp->rcr_index = index; 3426 3427 return num_rcr; 3428 } 3429 3430 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np, 3431 struct rx_ring_info *rp) 3432 { 3433 unsigned int index = rp->rcr_index; 3434 struct rx_pkt_hdr1 *rh; 3435 struct sk_buff *skb; 3436 int len, num_rcr; 3437 3438 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE); 3439 if (unlikely(!skb)) 3440 return niu_rx_pkt_ignore(np, rp); 3441 3442 num_rcr = 0; 3443 while (1) { 3444 struct page *page, **link; 3445 u32 rcr_size, append_size; 3446 u64 addr, val, off; 3447 3448 num_rcr++; 3449 3450 val = le64_to_cpup(&rp->rcr[index]); 3451 3452 len = (val & RCR_ENTRY_L2_LEN) >> 3453 RCR_ENTRY_L2_LEN_SHIFT; 3454 len -= ETH_FCS_LEN; 3455 3456 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3457 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3458 page = niu_find_rxpage(rp, addr, &link); 3459 3460 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3461 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3462 3463 off = addr & ~PAGE_MASK; 3464 append_size = rcr_size; 3465 if (num_rcr == 1) { 3466 int ptype; 3467 3468 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); 3469 if ((ptype == RCR_PKT_TYPE_TCP || 3470 ptype == RCR_PKT_TYPE_UDP) && 3471 !(val & (RCR_ENTRY_NOPORT | 3472 RCR_ENTRY_ERROR))) 3473 skb->ip_summed = CHECKSUM_UNNECESSARY; 3474 else 3475 skb_checksum_none_assert(skb); 3476 } else if (!(val & RCR_ENTRY_MULTI)) 3477 append_size = len - skb->len; 3478 3479 niu_rx_skb_append(skb, page, off, append_size, rcr_size); 3480 if ((page->index + rp->rbr_block_size) - rcr_size == addr) { 3481 *link = (struct page *) page->mapping; 3482 np->ops->unmap_page(np->device, page->index, 3483 PAGE_SIZE, DMA_FROM_DEVICE); 3484 page->index = 0; 3485 page->mapping = NULL; 3486 rp->rbr_refill_pending++; 3487 } else 3488 get_page(page); 3489 3490 index = NEXT_RCR(rp, index); 3491 if (!(val & RCR_ENTRY_MULTI)) 3492 break; 3493 3494 } 3495 rp->rcr_index = index; 3496 3497 len += sizeof(*rh); 3498 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN); 3499 __pskb_pull_tail(skb, len); 3500 3501 rh = (struct rx_pkt_hdr1 *) skb->data; 3502 if (np->dev->features & NETIF_F_RXHASH) 3503 skb->rxhash = ((u32)rh->hashval2_0 << 24 | 3504 (u32)rh->hashval2_1 << 16 | 3505 (u32)rh->hashval1_1 << 8 | 3506 (u32)rh->hashval1_2 << 0); 3507 skb_pull(skb, sizeof(*rh)); 3508 3509 rp->rx_packets++; 3510 rp->rx_bytes += skb->len; 3511 3512 skb->protocol = eth_type_trans(skb, np->dev); 3513 skb_record_rx_queue(skb, rp->rx_channel); 3514 napi_gro_receive(napi, skb); 3515 3516 return num_rcr; 3517 } 3518 3519 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3520 { 3521 int blocks_per_page = rp->rbr_blocks_per_page; 3522 int err, index = rp->rbr_index; 3523 3524 err = 0; 3525 while (index < (rp->rbr_table_size - blocks_per_page)) { 3526 err = niu_rbr_add_page(np, rp, mask, index); 3527 if (err) 3528 break; 3529 3530 index += blocks_per_page; 3531 } 3532 3533 rp->rbr_index = index; 3534 return err; 3535 } 3536 3537 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp) 3538 { 3539 int i; 3540 3541 for (i = 0; i < MAX_RBR_RING_SIZE; i++) { 3542 struct page *page; 3543 3544 page = rp->rxhash[i]; 3545 while (page) { 3546 struct page *next = (struct page *) page->mapping; 3547 u64 base = page->index; 3548 3549 np->ops->unmap_page(np->device, base, PAGE_SIZE, 3550 DMA_FROM_DEVICE); 3551 page->index = 0; 3552 page->mapping = NULL; 3553 3554 __free_page(page); 3555 3556 page = next; 3557 } 3558 } 3559 3560 for (i = 0; i < rp->rbr_table_size; i++) 3561 rp->rbr[i] = cpu_to_le32(0); 3562 rp->rbr_index = 0; 3563 } 3564 3565 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx) 3566 { 3567 struct tx_buff_info *tb = &rp->tx_buffs[idx]; 3568 struct sk_buff *skb = tb->skb; 3569 struct tx_pkt_hdr *tp; 3570 u64 tx_flags; 3571 int i, len; 3572 3573 tp = (struct tx_pkt_hdr *) skb->data; 3574 tx_flags = le64_to_cpup(&tp->flags); 3575 3576 rp->tx_packets++; 3577 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) - 3578 ((tx_flags & TXHDR_PAD) / 2)); 3579 3580 len = skb_headlen(skb); 3581 np->ops->unmap_single(np->device, tb->mapping, 3582 len, DMA_TO_DEVICE); 3583 3584 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK) 3585 rp->mark_pending--; 3586 3587 tb->skb = NULL; 3588 do { 3589 idx = NEXT_TX(rp, idx); 3590 len -= MAX_TX_DESC_LEN; 3591 } while (len > 0); 3592 3593 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 3594 tb = &rp->tx_buffs[idx]; 3595 BUG_ON(tb->skb != NULL); 3596 np->ops->unmap_page(np->device, tb->mapping, 3597 skb_frag_size(&skb_shinfo(skb)->frags[i]), 3598 DMA_TO_DEVICE); 3599 idx = NEXT_TX(rp, idx); 3600 } 3601 3602 dev_kfree_skb(skb); 3603 3604 return idx; 3605 } 3606 3607 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4) 3608 3609 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) 3610 { 3611 struct netdev_queue *txq; 3612 u16 pkt_cnt, tmp; 3613 int cons, index; 3614 u64 cs; 3615 3616 index = (rp - np->tx_rings); 3617 txq = netdev_get_tx_queue(np->dev, index); 3618 3619 cs = rp->tx_cs; 3620 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) 3621 goto out; 3622 3623 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT; 3624 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) & 3625 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT); 3626 3627 rp->last_pkt_cnt = tmp; 3628 3629 cons = rp->cons; 3630 3631 netif_printk(np, tx_done, KERN_DEBUG, np->dev, 3632 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons); 3633 3634 while (pkt_cnt--) 3635 cons = release_tx_packet(np, rp, cons); 3636 3637 rp->cons = cons; 3638 smp_mb(); 3639 3640 out: 3641 if (unlikely(netif_tx_queue_stopped(txq) && 3642 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { 3643 __netif_tx_lock(txq, smp_processor_id()); 3644 if (netif_tx_queue_stopped(txq) && 3645 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) 3646 netif_tx_wake_queue(txq); 3647 __netif_tx_unlock(txq); 3648 } 3649 } 3650 3651 static inline void niu_sync_rx_discard_stats(struct niu *np, 3652 struct rx_ring_info *rp, 3653 const int limit) 3654 { 3655 /* This elaborate scheme is needed for reading the RX discard 3656 * counters, as they are only 16-bit and can overflow quickly, 3657 * and because the overflow indication bit is not usable as 3658 * the counter value does not wrap, but remains at max value 3659 * 0xFFFF. 3660 * 3661 * In theory and in practice counters can be lost in between 3662 * reading nr64() and clearing the counter nw64(). For this 3663 * reason, the number of counter clearings nw64() is 3664 * limited/reduced though the limit parameter. 3665 */ 3666 int rx_channel = rp->rx_channel; 3667 u32 misc, wred; 3668 3669 /* RXMISC (Receive Miscellaneous Discard Count), covers the 3670 * following discard events: IPP (Input Port Process), 3671 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive 3672 * Block Ring) prefetch buffer is empty. 3673 */ 3674 misc = nr64(RXMISC(rx_channel)); 3675 if (unlikely((misc & RXMISC_COUNT) > limit)) { 3676 nw64(RXMISC(rx_channel), 0); 3677 rp->rx_errors += misc & RXMISC_COUNT; 3678 3679 if (unlikely(misc & RXMISC_OFLOW)) 3680 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n", 3681 rx_channel); 3682 3683 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3684 "rx-%d: MISC drop=%u over=%u\n", 3685 rx_channel, misc, misc-limit); 3686 } 3687 3688 /* WRED (Weighted Random Early Discard) by hardware */ 3689 wred = nr64(RED_DIS_CNT(rx_channel)); 3690 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) { 3691 nw64(RED_DIS_CNT(rx_channel), 0); 3692 rp->rx_dropped += wred & RED_DIS_CNT_COUNT; 3693 3694 if (unlikely(wred & RED_DIS_CNT_OFLOW)) 3695 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel); 3696 3697 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3698 "rx-%d: WRED drop=%u over=%u\n", 3699 rx_channel, wred, wred-limit); 3700 } 3701 } 3702 3703 static int niu_rx_work(struct napi_struct *napi, struct niu *np, 3704 struct rx_ring_info *rp, int budget) 3705 { 3706 int qlen, rcr_done = 0, work_done = 0; 3707 struct rxdma_mailbox *mbox = rp->mbox; 3708 u64 stat; 3709 3710 #if 1 3711 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3712 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN; 3713 #else 3714 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 3715 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN); 3716 #endif 3717 mbox->rx_dma_ctl_stat = 0; 3718 mbox->rcrstat_a = 0; 3719 3720 netif_printk(np, rx_status, KERN_DEBUG, np->dev, 3721 "%s(chan[%d]), stat[%llx] qlen=%d\n", 3722 __func__, rp->rx_channel, (unsigned long long)stat, qlen); 3723 3724 rcr_done = work_done = 0; 3725 qlen = min(qlen, budget); 3726 while (work_done < qlen) { 3727 rcr_done += niu_process_rx_pkt(napi, np, rp); 3728 work_done++; 3729 } 3730 3731 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) { 3732 unsigned int i; 3733 3734 for (i = 0; i < rp->rbr_refill_pending; i++) 3735 niu_rbr_refill(np, rp, GFP_ATOMIC); 3736 rp->rbr_refill_pending = 0; 3737 } 3738 3739 stat = (RX_DMA_CTL_STAT_MEX | 3740 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) | 3741 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT)); 3742 3743 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); 3744 3745 /* Only sync discards stats when qlen indicate potential for drops */ 3746 if (qlen > 10) 3747 niu_sync_rx_discard_stats(np, rp, 0x7FFF); 3748 3749 return work_done; 3750 } 3751 3752 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget) 3753 { 3754 u64 v0 = lp->v0; 3755 u32 tx_vec = (v0 >> 32); 3756 u32 rx_vec = (v0 & 0xffffffff); 3757 int i, work_done = 0; 3758 3759 netif_printk(np, intr, KERN_DEBUG, np->dev, 3760 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0); 3761 3762 for (i = 0; i < np->num_tx_rings; i++) { 3763 struct tx_ring_info *rp = &np->tx_rings[i]; 3764 if (tx_vec & (1 << rp->tx_channel)) 3765 niu_tx_work(np, rp); 3766 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); 3767 } 3768 3769 for (i = 0; i < np->num_rx_rings; i++) { 3770 struct rx_ring_info *rp = &np->rx_rings[i]; 3771 3772 if (rx_vec & (1 << rp->rx_channel)) { 3773 int this_work_done; 3774 3775 this_work_done = niu_rx_work(&lp->napi, np, rp, 3776 budget); 3777 3778 budget -= this_work_done; 3779 work_done += this_work_done; 3780 } 3781 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); 3782 } 3783 3784 return work_done; 3785 } 3786 3787 static int niu_poll(struct napi_struct *napi, int budget) 3788 { 3789 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi); 3790 struct niu *np = lp->np; 3791 int work_done; 3792 3793 work_done = niu_poll_core(np, lp, budget); 3794 3795 if (work_done < budget) { 3796 napi_complete(napi); 3797 niu_ldg_rearm(np, lp, 1); 3798 } 3799 return work_done; 3800 } 3801 3802 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp, 3803 u64 stat) 3804 { 3805 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel); 3806 3807 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT) 3808 pr_cont("RBR_TMOUT "); 3809 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR) 3810 pr_cont("RSP_CNT "); 3811 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS) 3812 pr_cont("BYTE_EN_BUS "); 3813 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR) 3814 pr_cont("RSP_DAT "); 3815 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR) 3816 pr_cont("RCR_ACK "); 3817 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR) 3818 pr_cont("RCR_SHA_PAR "); 3819 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR) 3820 pr_cont("RBR_PRE_PAR "); 3821 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR) 3822 pr_cont("CONFIG "); 3823 if (stat & RX_DMA_CTL_STAT_RCRINCON) 3824 pr_cont("RCRINCON "); 3825 if (stat & RX_DMA_CTL_STAT_RCRFULL) 3826 pr_cont("RCRFULL "); 3827 if (stat & RX_DMA_CTL_STAT_RBRFULL) 3828 pr_cont("RBRFULL "); 3829 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE) 3830 pr_cont("RBRLOGPAGE "); 3831 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE) 3832 pr_cont("CFIGLOGPAGE "); 3833 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR) 3834 pr_cont("DC_FIDO "); 3835 3836 pr_cont(")\n"); 3837 } 3838 3839 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp) 3840 { 3841 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3842 int err = 0; 3843 3844 3845 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL | 3846 RX_DMA_CTL_STAT_PORT_FATAL)) 3847 err = -EINVAL; 3848 3849 if (err) { 3850 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n", 3851 rp->rx_channel, 3852 (unsigned long long) stat); 3853 3854 niu_log_rxchan_errors(np, rp, stat); 3855 } 3856 3857 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 3858 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS); 3859 3860 return err; 3861 } 3862 3863 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp, 3864 u64 cs) 3865 { 3866 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel); 3867 3868 if (cs & TX_CS_MBOX_ERR) 3869 pr_cont("MBOX "); 3870 if (cs & TX_CS_PKT_SIZE_ERR) 3871 pr_cont("PKT_SIZE "); 3872 if (cs & TX_CS_TX_RING_OFLOW) 3873 pr_cont("TX_RING_OFLOW "); 3874 if (cs & TX_CS_PREF_BUF_PAR_ERR) 3875 pr_cont("PREF_BUF_PAR "); 3876 if (cs & TX_CS_NACK_PREF) 3877 pr_cont("NACK_PREF "); 3878 if (cs & TX_CS_NACK_PKT_RD) 3879 pr_cont("NACK_PKT_RD "); 3880 if (cs & TX_CS_CONF_PART_ERR) 3881 pr_cont("CONF_PART "); 3882 if (cs & TX_CS_PKT_PRT_ERR) 3883 pr_cont("PKT_PTR "); 3884 3885 pr_cont(")\n"); 3886 } 3887 3888 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp) 3889 { 3890 u64 cs, logh, logl; 3891 3892 cs = nr64(TX_CS(rp->tx_channel)); 3893 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel)); 3894 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel)); 3895 3896 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n", 3897 rp->tx_channel, 3898 (unsigned long long)cs, 3899 (unsigned long long)logh, 3900 (unsigned long long)logl); 3901 3902 niu_log_txchan_errors(np, rp, cs); 3903 3904 return -ENODEV; 3905 } 3906 3907 static int niu_mif_interrupt(struct niu *np) 3908 { 3909 u64 mif_status = nr64(MIF_STATUS); 3910 int phy_mdint = 0; 3911 3912 if (np->flags & NIU_FLAGS_XMAC) { 3913 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS); 3914 3915 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT) 3916 phy_mdint = 1; 3917 } 3918 3919 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n", 3920 (unsigned long long)mif_status, phy_mdint); 3921 3922 return -ENODEV; 3923 } 3924 3925 static void niu_xmac_interrupt(struct niu *np) 3926 { 3927 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 3928 u64 val; 3929 3930 val = nr64_mac(XTXMAC_STATUS); 3931 if (val & XTXMAC_STATUS_FRAME_CNT_EXP) 3932 mp->tx_frames += TXMAC_FRM_CNT_COUNT; 3933 if (val & XTXMAC_STATUS_BYTE_CNT_EXP) 3934 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT; 3935 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) 3936 mp->tx_fifo_errors++; 3937 if (val & XTXMAC_STATUS_TXMAC_OFLOW) 3938 mp->tx_overflow_errors++; 3939 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) 3940 mp->tx_max_pkt_size_errors++; 3941 if (val & XTXMAC_STATUS_TXMAC_UFLOW) 3942 mp->tx_underflow_errors++; 3943 3944 val = nr64_mac(XRXMAC_STATUS); 3945 if (val & XRXMAC_STATUS_LCL_FLT_STATUS) 3946 mp->rx_local_faults++; 3947 if (val & XRXMAC_STATUS_RFLT_DET) 3948 mp->rx_remote_faults++; 3949 if (val & XRXMAC_STATUS_LFLT_CNT_EXP) 3950 mp->rx_link_faults += LINK_FAULT_CNT_COUNT; 3951 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) 3952 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT; 3953 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) 3954 mp->rx_frags += RXMAC_FRAG_CNT_COUNT; 3955 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) 3956 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT; 3957 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) 3958 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; 3959 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) 3960 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; 3961 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) 3962 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT; 3963 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) 3964 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT; 3965 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) 3966 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT; 3967 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) 3968 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT; 3969 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) 3970 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT; 3971 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) 3972 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT; 3973 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) 3974 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT; 3975 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP) 3976 mp->rx_octets += RXMAC_BT_CNT_COUNT; 3977 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) 3978 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT; 3979 if (val & XRXMAC_STATUS_LENERR_CNT_EXP) 3980 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT; 3981 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) 3982 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT; 3983 if (val & XRXMAC_STATUS_RXUFLOW) 3984 mp->rx_underflows++; 3985 if (val & XRXMAC_STATUS_RXOFLOW) 3986 mp->rx_overflows++; 3987 3988 val = nr64_mac(XMAC_FC_STAT); 3989 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) 3990 mp->pause_off_state++; 3991 if (val & XMAC_FC_STAT_TX_MAC_PAUSE) 3992 mp->pause_on_state++; 3993 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) 3994 mp->pause_received++; 3995 } 3996 3997 static void niu_bmac_interrupt(struct niu *np) 3998 { 3999 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 4000 u64 val; 4001 4002 val = nr64_mac(BTXMAC_STATUS); 4003 if (val & BTXMAC_STATUS_UNDERRUN) 4004 mp->tx_underflow_errors++; 4005 if (val & BTXMAC_STATUS_MAX_PKT_ERR) 4006 mp->tx_max_pkt_size_errors++; 4007 if (val & BTXMAC_STATUS_BYTE_CNT_EXP) 4008 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT; 4009 if (val & BTXMAC_STATUS_FRAME_CNT_EXP) 4010 mp->tx_frames += BTXMAC_FRM_CNT_COUNT; 4011 4012 val = nr64_mac(BRXMAC_STATUS); 4013 if (val & BRXMAC_STATUS_OVERFLOW) 4014 mp->rx_overflows++; 4015 if (val & BRXMAC_STATUS_FRAME_CNT_EXP) 4016 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT; 4017 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) 4018 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4019 if (val & BRXMAC_STATUS_CRC_ERR_EXP) 4020 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4021 if (val & BRXMAC_STATUS_LEN_ERR_EXP) 4022 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT; 4023 4024 val = nr64_mac(BMAC_CTRL_STATUS); 4025 if (val & BMAC_CTRL_STATUS_NOPAUSE) 4026 mp->pause_off_state++; 4027 if (val & BMAC_CTRL_STATUS_PAUSE) 4028 mp->pause_on_state++; 4029 if (val & BMAC_CTRL_STATUS_PAUSE_RECV) 4030 mp->pause_received++; 4031 } 4032 4033 static int niu_mac_interrupt(struct niu *np) 4034 { 4035 if (np->flags & NIU_FLAGS_XMAC) 4036 niu_xmac_interrupt(np); 4037 else 4038 niu_bmac_interrupt(np); 4039 4040 return 0; 4041 } 4042 4043 static void niu_log_device_error(struct niu *np, u64 stat) 4044 { 4045 netdev_err(np->dev, "Core device errors ( "); 4046 4047 if (stat & SYS_ERR_MASK_META2) 4048 pr_cont("META2 "); 4049 if (stat & SYS_ERR_MASK_META1) 4050 pr_cont("META1 "); 4051 if (stat & SYS_ERR_MASK_PEU) 4052 pr_cont("PEU "); 4053 if (stat & SYS_ERR_MASK_TXC) 4054 pr_cont("TXC "); 4055 if (stat & SYS_ERR_MASK_RDMC) 4056 pr_cont("RDMC "); 4057 if (stat & SYS_ERR_MASK_TDMC) 4058 pr_cont("TDMC "); 4059 if (stat & SYS_ERR_MASK_ZCP) 4060 pr_cont("ZCP "); 4061 if (stat & SYS_ERR_MASK_FFLP) 4062 pr_cont("FFLP "); 4063 if (stat & SYS_ERR_MASK_IPP) 4064 pr_cont("IPP "); 4065 if (stat & SYS_ERR_MASK_MAC) 4066 pr_cont("MAC "); 4067 if (stat & SYS_ERR_MASK_SMX) 4068 pr_cont("SMX "); 4069 4070 pr_cont(")\n"); 4071 } 4072 4073 static int niu_device_error(struct niu *np) 4074 { 4075 u64 stat = nr64(SYS_ERR_STAT); 4076 4077 netdev_err(np->dev, "Core device error, stat[%llx]\n", 4078 (unsigned long long)stat); 4079 4080 niu_log_device_error(np, stat); 4081 4082 return -ENODEV; 4083 } 4084 4085 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp, 4086 u64 v0, u64 v1, u64 v2) 4087 { 4088 4089 int i, err = 0; 4090 4091 lp->v0 = v0; 4092 lp->v1 = v1; 4093 lp->v2 = v2; 4094 4095 if (v1 & 0x00000000ffffffffULL) { 4096 u32 rx_vec = (v1 & 0xffffffff); 4097 4098 for (i = 0; i < np->num_rx_rings; i++) { 4099 struct rx_ring_info *rp = &np->rx_rings[i]; 4100 4101 if (rx_vec & (1 << rp->rx_channel)) { 4102 int r = niu_rx_error(np, rp); 4103 if (r) { 4104 err = r; 4105 } else { 4106 if (!v0) 4107 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 4108 RX_DMA_CTL_STAT_MEX); 4109 } 4110 } 4111 } 4112 } 4113 if (v1 & 0x7fffffff00000000ULL) { 4114 u32 tx_vec = (v1 >> 32) & 0x7fffffff; 4115 4116 for (i = 0; i < np->num_tx_rings; i++) { 4117 struct tx_ring_info *rp = &np->tx_rings[i]; 4118 4119 if (tx_vec & (1 << rp->tx_channel)) { 4120 int r = niu_tx_error(np, rp); 4121 if (r) 4122 err = r; 4123 } 4124 } 4125 } 4126 if ((v0 | v1) & 0x8000000000000000ULL) { 4127 int r = niu_mif_interrupt(np); 4128 if (r) 4129 err = r; 4130 } 4131 if (v2) { 4132 if (v2 & 0x01ef) { 4133 int r = niu_mac_interrupt(np); 4134 if (r) 4135 err = r; 4136 } 4137 if (v2 & 0x0210) { 4138 int r = niu_device_error(np); 4139 if (r) 4140 err = r; 4141 } 4142 } 4143 4144 if (err) 4145 niu_enable_interrupts(np, 0); 4146 4147 return err; 4148 } 4149 4150 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp, 4151 int ldn) 4152 { 4153 struct rxdma_mailbox *mbox = rp->mbox; 4154 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 4155 4156 stat_write = (RX_DMA_CTL_STAT_RCRTHRES | 4157 RX_DMA_CTL_STAT_RCRTO); 4158 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); 4159 4160 netif_printk(np, intr, KERN_DEBUG, np->dev, 4161 "%s() stat[%llx]\n", __func__, (unsigned long long)stat); 4162 } 4163 4164 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp, 4165 int ldn) 4166 { 4167 rp->tx_cs = nr64(TX_CS(rp->tx_channel)); 4168 4169 netif_printk(np, intr, KERN_DEBUG, np->dev, 4170 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs); 4171 } 4172 4173 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0) 4174 { 4175 struct niu_parent *parent = np->parent; 4176 u32 rx_vec, tx_vec; 4177 int i; 4178 4179 tx_vec = (v0 >> 32); 4180 rx_vec = (v0 & 0xffffffff); 4181 4182 for (i = 0; i < np->num_rx_rings; i++) { 4183 struct rx_ring_info *rp = &np->rx_rings[i]; 4184 int ldn = LDN_RXDMA(rp->rx_channel); 4185 4186 if (parent->ldg_map[ldn] != ldg) 4187 continue; 4188 4189 nw64(LD_IM0(ldn), LD_IM0_MASK); 4190 if (rx_vec & (1 << rp->rx_channel)) 4191 niu_rxchan_intr(np, rp, ldn); 4192 } 4193 4194 for (i = 0; i < np->num_tx_rings; i++) { 4195 struct tx_ring_info *rp = &np->tx_rings[i]; 4196 int ldn = LDN_TXDMA(rp->tx_channel); 4197 4198 if (parent->ldg_map[ldn] != ldg) 4199 continue; 4200 4201 nw64(LD_IM0(ldn), LD_IM0_MASK); 4202 if (tx_vec & (1 << rp->tx_channel)) 4203 niu_txchan_intr(np, rp, ldn); 4204 } 4205 } 4206 4207 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp, 4208 u64 v0, u64 v1, u64 v2) 4209 { 4210 if (likely(napi_schedule_prep(&lp->napi))) { 4211 lp->v0 = v0; 4212 lp->v1 = v1; 4213 lp->v2 = v2; 4214 __niu_fastpath_interrupt(np, lp->ldg_num, v0); 4215 __napi_schedule(&lp->napi); 4216 } 4217 } 4218 4219 static irqreturn_t niu_interrupt(int irq, void *dev_id) 4220 { 4221 struct niu_ldg *lp = dev_id; 4222 struct niu *np = lp->np; 4223 int ldg = lp->ldg_num; 4224 unsigned long flags; 4225 u64 v0, v1, v2; 4226 4227 if (netif_msg_intr(np)) 4228 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)", 4229 __func__, lp, ldg); 4230 4231 spin_lock_irqsave(&np->lock, flags); 4232 4233 v0 = nr64(LDSV0(ldg)); 4234 v1 = nr64(LDSV1(ldg)); 4235 v2 = nr64(LDSV2(ldg)); 4236 4237 if (netif_msg_intr(np)) 4238 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n", 4239 (unsigned long long) v0, 4240 (unsigned long long) v1, 4241 (unsigned long long) v2); 4242 4243 if (unlikely(!v0 && !v1 && !v2)) { 4244 spin_unlock_irqrestore(&np->lock, flags); 4245 return IRQ_NONE; 4246 } 4247 4248 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) { 4249 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2); 4250 if (err) 4251 goto out; 4252 } 4253 if (likely(v0 & ~((u64)1 << LDN_MIF))) 4254 niu_schedule_napi(np, lp, v0, v1, v2); 4255 else 4256 niu_ldg_rearm(np, lp, 1); 4257 out: 4258 spin_unlock_irqrestore(&np->lock, flags); 4259 4260 return IRQ_HANDLED; 4261 } 4262 4263 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp) 4264 { 4265 if (rp->mbox) { 4266 np->ops->free_coherent(np->device, 4267 sizeof(struct rxdma_mailbox), 4268 rp->mbox, rp->mbox_dma); 4269 rp->mbox = NULL; 4270 } 4271 if (rp->rcr) { 4272 np->ops->free_coherent(np->device, 4273 MAX_RCR_RING_SIZE * sizeof(__le64), 4274 rp->rcr, rp->rcr_dma); 4275 rp->rcr = NULL; 4276 rp->rcr_table_size = 0; 4277 rp->rcr_index = 0; 4278 } 4279 if (rp->rbr) { 4280 niu_rbr_free(np, rp); 4281 4282 np->ops->free_coherent(np->device, 4283 MAX_RBR_RING_SIZE * sizeof(__le32), 4284 rp->rbr, rp->rbr_dma); 4285 rp->rbr = NULL; 4286 rp->rbr_table_size = 0; 4287 rp->rbr_index = 0; 4288 } 4289 kfree(rp->rxhash); 4290 rp->rxhash = NULL; 4291 } 4292 4293 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp) 4294 { 4295 if (rp->mbox) { 4296 np->ops->free_coherent(np->device, 4297 sizeof(struct txdma_mailbox), 4298 rp->mbox, rp->mbox_dma); 4299 rp->mbox = NULL; 4300 } 4301 if (rp->descr) { 4302 int i; 4303 4304 for (i = 0; i < MAX_TX_RING_SIZE; i++) { 4305 if (rp->tx_buffs[i].skb) 4306 (void) release_tx_packet(np, rp, i); 4307 } 4308 4309 np->ops->free_coherent(np->device, 4310 MAX_TX_RING_SIZE * sizeof(__le64), 4311 rp->descr, rp->descr_dma); 4312 rp->descr = NULL; 4313 rp->pending = 0; 4314 rp->prod = 0; 4315 rp->cons = 0; 4316 rp->wrap_bit = 0; 4317 } 4318 } 4319 4320 static void niu_free_channels(struct niu *np) 4321 { 4322 int i; 4323 4324 if (np->rx_rings) { 4325 for (i = 0; i < np->num_rx_rings; i++) { 4326 struct rx_ring_info *rp = &np->rx_rings[i]; 4327 4328 niu_free_rx_ring_info(np, rp); 4329 } 4330 kfree(np->rx_rings); 4331 np->rx_rings = NULL; 4332 np->num_rx_rings = 0; 4333 } 4334 4335 if (np->tx_rings) { 4336 for (i = 0; i < np->num_tx_rings; i++) { 4337 struct tx_ring_info *rp = &np->tx_rings[i]; 4338 4339 niu_free_tx_ring_info(np, rp); 4340 } 4341 kfree(np->tx_rings); 4342 np->tx_rings = NULL; 4343 np->num_tx_rings = 0; 4344 } 4345 } 4346 4347 static int niu_alloc_rx_ring_info(struct niu *np, 4348 struct rx_ring_info *rp) 4349 { 4350 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64); 4351 4352 rp->rxhash = kzalloc(MAX_RBR_RING_SIZE * sizeof(struct page *), 4353 GFP_KERNEL); 4354 if (!rp->rxhash) 4355 return -ENOMEM; 4356 4357 rp->mbox = np->ops->alloc_coherent(np->device, 4358 sizeof(struct rxdma_mailbox), 4359 &rp->mbox_dma, GFP_KERNEL); 4360 if (!rp->mbox) 4361 return -ENOMEM; 4362 if ((unsigned long)rp->mbox & (64UL - 1)) { 4363 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n", 4364 rp->mbox); 4365 return -EINVAL; 4366 } 4367 4368 rp->rcr = np->ops->alloc_coherent(np->device, 4369 MAX_RCR_RING_SIZE * sizeof(__le64), 4370 &rp->rcr_dma, GFP_KERNEL); 4371 if (!rp->rcr) 4372 return -ENOMEM; 4373 if ((unsigned long)rp->rcr & (64UL - 1)) { 4374 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n", 4375 rp->rcr); 4376 return -EINVAL; 4377 } 4378 rp->rcr_table_size = MAX_RCR_RING_SIZE; 4379 rp->rcr_index = 0; 4380 4381 rp->rbr = np->ops->alloc_coherent(np->device, 4382 MAX_RBR_RING_SIZE * sizeof(__le32), 4383 &rp->rbr_dma, GFP_KERNEL); 4384 if (!rp->rbr) 4385 return -ENOMEM; 4386 if ((unsigned long)rp->rbr & (64UL - 1)) { 4387 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n", 4388 rp->rbr); 4389 return -EINVAL; 4390 } 4391 rp->rbr_table_size = MAX_RBR_RING_SIZE; 4392 rp->rbr_index = 0; 4393 rp->rbr_pending = 0; 4394 4395 return 0; 4396 } 4397 4398 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp) 4399 { 4400 int mtu = np->dev->mtu; 4401 4402 /* These values are recommended by the HW designers for fair 4403 * utilization of DRR amongst the rings. 4404 */ 4405 rp->max_burst = mtu + 32; 4406 if (rp->max_burst > 4096) 4407 rp->max_burst = 4096; 4408 } 4409 4410 static int niu_alloc_tx_ring_info(struct niu *np, 4411 struct tx_ring_info *rp) 4412 { 4413 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64); 4414 4415 rp->mbox = np->ops->alloc_coherent(np->device, 4416 sizeof(struct txdma_mailbox), 4417 &rp->mbox_dma, GFP_KERNEL); 4418 if (!rp->mbox) 4419 return -ENOMEM; 4420 if ((unsigned long)rp->mbox & (64UL - 1)) { 4421 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n", 4422 rp->mbox); 4423 return -EINVAL; 4424 } 4425 4426 rp->descr = np->ops->alloc_coherent(np->device, 4427 MAX_TX_RING_SIZE * sizeof(__le64), 4428 &rp->descr_dma, GFP_KERNEL); 4429 if (!rp->descr) 4430 return -ENOMEM; 4431 if ((unsigned long)rp->descr & (64UL - 1)) { 4432 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n", 4433 rp->descr); 4434 return -EINVAL; 4435 } 4436 4437 rp->pending = MAX_TX_RING_SIZE; 4438 rp->prod = 0; 4439 rp->cons = 0; 4440 rp->wrap_bit = 0; 4441 4442 /* XXX make these configurable... XXX */ 4443 rp->mark_freq = rp->pending / 4; 4444 4445 niu_set_max_burst(np, rp); 4446 4447 return 0; 4448 } 4449 4450 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp) 4451 { 4452 u16 bss; 4453 4454 bss = min(PAGE_SHIFT, 15); 4455 4456 rp->rbr_block_size = 1 << bss; 4457 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss); 4458 4459 rp->rbr_sizes[0] = 256; 4460 rp->rbr_sizes[1] = 1024; 4461 if (np->dev->mtu > ETH_DATA_LEN) { 4462 switch (PAGE_SIZE) { 4463 case 4 * 1024: 4464 rp->rbr_sizes[2] = 4096; 4465 break; 4466 4467 default: 4468 rp->rbr_sizes[2] = 8192; 4469 break; 4470 } 4471 } else { 4472 rp->rbr_sizes[2] = 2048; 4473 } 4474 rp->rbr_sizes[3] = rp->rbr_block_size; 4475 } 4476 4477 static int niu_alloc_channels(struct niu *np) 4478 { 4479 struct niu_parent *parent = np->parent; 4480 int first_rx_channel, first_tx_channel; 4481 int num_rx_rings, num_tx_rings; 4482 struct rx_ring_info *rx_rings; 4483 struct tx_ring_info *tx_rings; 4484 int i, port, err; 4485 4486 port = np->port; 4487 first_rx_channel = first_tx_channel = 0; 4488 for (i = 0; i < port; i++) { 4489 first_rx_channel += parent->rxchan_per_port[i]; 4490 first_tx_channel += parent->txchan_per_port[i]; 4491 } 4492 4493 num_rx_rings = parent->rxchan_per_port[port]; 4494 num_tx_rings = parent->txchan_per_port[port]; 4495 4496 rx_rings = kcalloc(num_rx_rings, sizeof(struct rx_ring_info), 4497 GFP_KERNEL); 4498 err = -ENOMEM; 4499 if (!rx_rings) 4500 goto out_err; 4501 4502 np->num_rx_rings = num_rx_rings; 4503 smp_wmb(); 4504 np->rx_rings = rx_rings; 4505 4506 netif_set_real_num_rx_queues(np->dev, num_rx_rings); 4507 4508 for (i = 0; i < np->num_rx_rings; i++) { 4509 struct rx_ring_info *rp = &np->rx_rings[i]; 4510 4511 rp->np = np; 4512 rp->rx_channel = first_rx_channel + i; 4513 4514 err = niu_alloc_rx_ring_info(np, rp); 4515 if (err) 4516 goto out_err; 4517 4518 niu_size_rbr(np, rp); 4519 4520 /* XXX better defaults, configurable, etc... XXX */ 4521 rp->nonsyn_window = 64; 4522 rp->nonsyn_threshold = rp->rcr_table_size - 64; 4523 rp->syn_window = 64; 4524 rp->syn_threshold = rp->rcr_table_size - 64; 4525 rp->rcr_pkt_threshold = 16; 4526 rp->rcr_timeout = 8; 4527 rp->rbr_kick_thresh = RBR_REFILL_MIN; 4528 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page) 4529 rp->rbr_kick_thresh = rp->rbr_blocks_per_page; 4530 4531 err = niu_rbr_fill(np, rp, GFP_KERNEL); 4532 if (err) 4533 return err; 4534 } 4535 4536 tx_rings = kcalloc(num_tx_rings, sizeof(struct tx_ring_info), 4537 GFP_KERNEL); 4538 err = -ENOMEM; 4539 if (!tx_rings) 4540 goto out_err; 4541 4542 np->num_tx_rings = num_tx_rings; 4543 smp_wmb(); 4544 np->tx_rings = tx_rings; 4545 4546 netif_set_real_num_tx_queues(np->dev, num_tx_rings); 4547 4548 for (i = 0; i < np->num_tx_rings; i++) { 4549 struct tx_ring_info *rp = &np->tx_rings[i]; 4550 4551 rp->np = np; 4552 rp->tx_channel = first_tx_channel + i; 4553 4554 err = niu_alloc_tx_ring_info(np, rp); 4555 if (err) 4556 goto out_err; 4557 } 4558 4559 return 0; 4560 4561 out_err: 4562 niu_free_channels(np); 4563 return err; 4564 } 4565 4566 static int niu_tx_cs_sng_poll(struct niu *np, int channel) 4567 { 4568 int limit = 1000; 4569 4570 while (--limit > 0) { 4571 u64 val = nr64(TX_CS(channel)); 4572 if (val & TX_CS_SNG_STATE) 4573 return 0; 4574 } 4575 return -ENODEV; 4576 } 4577 4578 static int niu_tx_channel_stop(struct niu *np, int channel) 4579 { 4580 u64 val = nr64(TX_CS(channel)); 4581 4582 val |= TX_CS_STOP_N_GO; 4583 nw64(TX_CS(channel), val); 4584 4585 return niu_tx_cs_sng_poll(np, channel); 4586 } 4587 4588 static int niu_tx_cs_reset_poll(struct niu *np, int channel) 4589 { 4590 int limit = 1000; 4591 4592 while (--limit > 0) { 4593 u64 val = nr64(TX_CS(channel)); 4594 if (!(val & TX_CS_RST)) 4595 return 0; 4596 } 4597 return -ENODEV; 4598 } 4599 4600 static int niu_tx_channel_reset(struct niu *np, int channel) 4601 { 4602 u64 val = nr64(TX_CS(channel)); 4603 int err; 4604 4605 val |= TX_CS_RST; 4606 nw64(TX_CS(channel), val); 4607 4608 err = niu_tx_cs_reset_poll(np, channel); 4609 if (!err) 4610 nw64(TX_RING_KICK(channel), 0); 4611 4612 return err; 4613 } 4614 4615 static int niu_tx_channel_lpage_init(struct niu *np, int channel) 4616 { 4617 u64 val; 4618 4619 nw64(TX_LOG_MASK1(channel), 0); 4620 nw64(TX_LOG_VAL1(channel), 0); 4621 nw64(TX_LOG_MASK2(channel), 0); 4622 nw64(TX_LOG_VAL2(channel), 0); 4623 nw64(TX_LOG_PAGE_RELO1(channel), 0); 4624 nw64(TX_LOG_PAGE_RELO2(channel), 0); 4625 nw64(TX_LOG_PAGE_HDL(channel), 0); 4626 4627 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; 4628 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); 4629 nw64(TX_LOG_PAGE_VLD(channel), val); 4630 4631 /* XXX TXDMA 32bit mode? XXX */ 4632 4633 return 0; 4634 } 4635 4636 static void niu_txc_enable_port(struct niu *np, int on) 4637 { 4638 unsigned long flags; 4639 u64 val, mask; 4640 4641 niu_lock_parent(np, flags); 4642 val = nr64(TXC_CONTROL); 4643 mask = (u64)1 << np->port; 4644 if (on) { 4645 val |= TXC_CONTROL_ENABLE | mask; 4646 } else { 4647 val &= ~mask; 4648 if ((val & ~TXC_CONTROL_ENABLE) == 0) 4649 val &= ~TXC_CONTROL_ENABLE; 4650 } 4651 nw64(TXC_CONTROL, val); 4652 niu_unlock_parent(np, flags); 4653 } 4654 4655 static void niu_txc_set_imask(struct niu *np, u64 imask) 4656 { 4657 unsigned long flags; 4658 u64 val; 4659 4660 niu_lock_parent(np, flags); 4661 val = nr64(TXC_INT_MASK); 4662 val &= ~TXC_INT_MASK_VAL(np->port); 4663 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); 4664 niu_unlock_parent(np, flags); 4665 } 4666 4667 static void niu_txc_port_dma_enable(struct niu *np, int on) 4668 { 4669 u64 val = 0; 4670 4671 if (on) { 4672 int i; 4673 4674 for (i = 0; i < np->num_tx_rings; i++) 4675 val |= (1 << np->tx_rings[i].tx_channel); 4676 } 4677 nw64(TXC_PORT_DMA(np->port), val); 4678 } 4679 4680 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 4681 { 4682 int err, channel = rp->tx_channel; 4683 u64 val, ring_len; 4684 4685 err = niu_tx_channel_stop(np, channel); 4686 if (err) 4687 return err; 4688 4689 err = niu_tx_channel_reset(np, channel); 4690 if (err) 4691 return err; 4692 4693 err = niu_tx_channel_lpage_init(np, channel); 4694 if (err) 4695 return err; 4696 4697 nw64(TXC_DMA_MAX(channel), rp->max_burst); 4698 nw64(TX_ENT_MSK(channel), 0); 4699 4700 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE | 4701 TX_RNG_CFIG_STADDR)) { 4702 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n", 4703 channel, (unsigned long long)rp->descr_dma); 4704 return -EINVAL; 4705 } 4706 4707 /* The length field in TX_RNG_CFIG is measured in 64-byte 4708 * blocks. rp->pending is the number of TX descriptors in 4709 * our ring, 8 bytes each, thus we divide by 8 bytes more 4710 * to get the proper value the chip wants. 4711 */ 4712 ring_len = (rp->pending / 8); 4713 4714 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | 4715 rp->descr_dma); 4716 nw64(TX_RNG_CFIG(channel), val); 4717 4718 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) || 4719 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) { 4720 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n", 4721 channel, (unsigned long long)rp->mbox_dma); 4722 return -EINVAL; 4723 } 4724 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); 4725 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); 4726 4727 nw64(TX_CS(channel), 0); 4728 4729 rp->last_pkt_cnt = 0; 4730 4731 return 0; 4732 } 4733 4734 static void niu_init_rdc_groups(struct niu *np) 4735 { 4736 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port]; 4737 int i, first_table_num = tp->first_table_num; 4738 4739 for (i = 0; i < tp->num_tables; i++) { 4740 struct rdc_table *tbl = &tp->tables[i]; 4741 int this_table = first_table_num + i; 4742 int slot; 4743 4744 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) 4745 nw64(RDC_TBL(this_table, slot), 4746 tbl->rxdma_channel[slot]); 4747 } 4748 4749 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); 4750 } 4751 4752 static void niu_init_drr_weight(struct niu *np) 4753 { 4754 int type = phy_decode(np->parent->port_phy, np->port); 4755 u64 val; 4756 4757 switch (type) { 4758 case PORT_TYPE_10G: 4759 val = PT_DRR_WEIGHT_DEFAULT_10G; 4760 break; 4761 4762 case PORT_TYPE_1G: 4763 default: 4764 val = PT_DRR_WEIGHT_DEFAULT_1G; 4765 break; 4766 } 4767 nw64(PT_DRR_WT(np->port), val); 4768 } 4769 4770 static int niu_init_hostinfo(struct niu *np) 4771 { 4772 struct niu_parent *parent = np->parent; 4773 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 4774 int i, err, num_alt = niu_num_alt_addr(np); 4775 int first_rdc_table = tp->first_table_num; 4776 4777 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 4778 if (err) 4779 return err; 4780 4781 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 4782 if (err) 4783 return err; 4784 4785 for (i = 0; i < num_alt; i++) { 4786 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1); 4787 if (err) 4788 return err; 4789 } 4790 4791 return 0; 4792 } 4793 4794 static int niu_rx_channel_reset(struct niu *np, int channel) 4795 { 4796 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel), 4797 RXDMA_CFIG1_RST, 1000, 10, 4798 "RXDMA_CFIG1"); 4799 } 4800 4801 static int niu_rx_channel_lpage_init(struct niu *np, int channel) 4802 { 4803 u64 val; 4804 4805 nw64(RX_LOG_MASK1(channel), 0); 4806 nw64(RX_LOG_VAL1(channel), 0); 4807 nw64(RX_LOG_MASK2(channel), 0); 4808 nw64(RX_LOG_VAL2(channel), 0); 4809 nw64(RX_LOG_PAGE_RELO1(channel), 0); 4810 nw64(RX_LOG_PAGE_RELO2(channel), 0); 4811 nw64(RX_LOG_PAGE_HDL(channel), 0); 4812 4813 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; 4814 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); 4815 nw64(RX_LOG_PAGE_VLD(channel), val); 4816 4817 return 0; 4818 } 4819 4820 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp) 4821 { 4822 u64 val; 4823 4824 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | 4825 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) | 4826 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) | 4827 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT)); 4828 nw64(RDC_RED_PARA(rp->rx_channel), val); 4829 } 4830 4831 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret) 4832 { 4833 u64 val = 0; 4834 4835 *ret = 0; 4836 switch (rp->rbr_block_size) { 4837 case 4 * 1024: 4838 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); 4839 break; 4840 case 8 * 1024: 4841 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); 4842 break; 4843 case 16 * 1024: 4844 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); 4845 break; 4846 case 32 * 1024: 4847 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); 4848 break; 4849 default: 4850 return -EINVAL; 4851 } 4852 val |= RBR_CFIG_B_VLD2; 4853 switch (rp->rbr_sizes[2]) { 4854 case 2 * 1024: 4855 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); 4856 break; 4857 case 4 * 1024: 4858 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); 4859 break; 4860 case 8 * 1024: 4861 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); 4862 break; 4863 case 16 * 1024: 4864 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); 4865 break; 4866 4867 default: 4868 return -EINVAL; 4869 } 4870 val |= RBR_CFIG_B_VLD1; 4871 switch (rp->rbr_sizes[1]) { 4872 case 1 * 1024: 4873 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); 4874 break; 4875 case 2 * 1024: 4876 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); 4877 break; 4878 case 4 * 1024: 4879 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); 4880 break; 4881 case 8 * 1024: 4882 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); 4883 break; 4884 4885 default: 4886 return -EINVAL; 4887 } 4888 val |= RBR_CFIG_B_VLD0; 4889 switch (rp->rbr_sizes[0]) { 4890 case 256: 4891 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); 4892 break; 4893 case 512: 4894 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); 4895 break; 4896 case 1 * 1024: 4897 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); 4898 break; 4899 case 2 * 1024: 4900 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); 4901 break; 4902 4903 default: 4904 return -EINVAL; 4905 } 4906 4907 *ret = val; 4908 return 0; 4909 } 4910 4911 static int niu_enable_rx_channel(struct niu *np, int channel, int on) 4912 { 4913 u64 val = nr64(RXDMA_CFIG1(channel)); 4914 int limit; 4915 4916 if (on) 4917 val |= RXDMA_CFIG1_EN; 4918 else 4919 val &= ~RXDMA_CFIG1_EN; 4920 nw64(RXDMA_CFIG1(channel), val); 4921 4922 limit = 1000; 4923 while (--limit > 0) { 4924 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST) 4925 break; 4926 udelay(10); 4927 } 4928 if (limit <= 0) 4929 return -ENODEV; 4930 return 0; 4931 } 4932 4933 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 4934 { 4935 int err, channel = rp->rx_channel; 4936 u64 val; 4937 4938 err = niu_rx_channel_reset(np, channel); 4939 if (err) 4940 return err; 4941 4942 err = niu_rx_channel_lpage_init(np, channel); 4943 if (err) 4944 return err; 4945 4946 niu_rx_channel_wred_init(np, rp); 4947 4948 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); 4949 nw64(RX_DMA_CTL_STAT(channel), 4950 (RX_DMA_CTL_STAT_MEX | 4951 RX_DMA_CTL_STAT_RCRTHRES | 4952 RX_DMA_CTL_STAT_RCRTO | 4953 RX_DMA_CTL_STAT_RBR_EMPTY)); 4954 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); 4955 nw64(RXDMA_CFIG2(channel), 4956 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) | 4957 RXDMA_CFIG2_FULL_HDR)); 4958 nw64(RBR_CFIG_A(channel), 4959 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) | 4960 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR))); 4961 err = niu_compute_rbr_cfig_b(rp, &val); 4962 if (err) 4963 return err; 4964 nw64(RBR_CFIG_B(channel), val); 4965 nw64(RCRCFIG_A(channel), 4966 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) | 4967 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR))); 4968 nw64(RCRCFIG_B(channel), 4969 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) | 4970 RCRCFIG_B_ENTOUT | 4971 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT)); 4972 4973 err = niu_enable_rx_channel(np, channel, 1); 4974 if (err) 4975 return err; 4976 4977 nw64(RBR_KICK(channel), rp->rbr_index); 4978 4979 val = nr64(RX_DMA_CTL_STAT(channel)); 4980 val |= RX_DMA_CTL_STAT_RBR_EMPTY; 4981 nw64(RX_DMA_CTL_STAT(channel), val); 4982 4983 return 0; 4984 } 4985 4986 static int niu_init_rx_channels(struct niu *np) 4987 { 4988 unsigned long flags; 4989 u64 seed = jiffies_64; 4990 int err, i; 4991 4992 niu_lock_parent(np, flags); 4993 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); 4994 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); 4995 niu_unlock_parent(np, flags); 4996 4997 /* XXX RXDMA 32bit mode? XXX */ 4998 4999 niu_init_rdc_groups(np); 5000 niu_init_drr_weight(np); 5001 5002 err = niu_init_hostinfo(np); 5003 if (err) 5004 return err; 5005 5006 for (i = 0; i < np->num_rx_rings; i++) { 5007 struct rx_ring_info *rp = &np->rx_rings[i]; 5008 5009 err = niu_init_one_rx_channel(np, rp); 5010 if (err) 5011 return err; 5012 } 5013 5014 return 0; 5015 } 5016 5017 static int niu_set_ip_frag_rule(struct niu *np) 5018 { 5019 struct niu_parent *parent = np->parent; 5020 struct niu_classifier *cp = &np->clas; 5021 struct niu_tcam_entry *tp; 5022 int index, err; 5023 5024 index = cp->tcam_top; 5025 tp = &parent->tcam[index]; 5026 5027 /* Note that the noport bit is the same in both ipv4 and 5028 * ipv6 format TCAM entries. 5029 */ 5030 memset(tp, 0, sizeof(*tp)); 5031 tp->key[1] = TCAM_V4KEY1_NOPORT; 5032 tp->key_mask[1] = TCAM_V4KEY1_NOPORT; 5033 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 5034 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT)); 5035 err = tcam_write(np, index, tp->key, tp->key_mask); 5036 if (err) 5037 return err; 5038 err = tcam_assoc_write(np, index, tp->assoc_data); 5039 if (err) 5040 return err; 5041 tp->valid = 1; 5042 cp->tcam_valid_entries++; 5043 5044 return 0; 5045 } 5046 5047 static int niu_init_classifier_hw(struct niu *np) 5048 { 5049 struct niu_parent *parent = np->parent; 5050 struct niu_classifier *cp = &np->clas; 5051 int i, err; 5052 5053 nw64(H1POLY, cp->h1_init); 5054 nw64(H2POLY, cp->h2_init); 5055 5056 err = niu_init_hostinfo(np); 5057 if (err) 5058 return err; 5059 5060 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) { 5061 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i]; 5062 5063 vlan_tbl_write(np, i, np->port, 5064 vp->vlan_pref, vp->rdc_num); 5065 } 5066 5067 for (i = 0; i < cp->num_alt_mac_mappings; i++) { 5068 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i]; 5069 5070 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num, 5071 ap->rdc_num, ap->mac_pref); 5072 if (err) 5073 return err; 5074 } 5075 5076 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 5077 int index = i - CLASS_CODE_USER_PROG1; 5078 5079 err = niu_set_tcam_key(np, i, parent->tcam_key[index]); 5080 if (err) 5081 return err; 5082 err = niu_set_flow_key(np, i, parent->flow_key[index]); 5083 if (err) 5084 return err; 5085 } 5086 5087 err = niu_set_ip_frag_rule(np); 5088 if (err) 5089 return err; 5090 5091 tcam_enable(np, 1); 5092 5093 return 0; 5094 } 5095 5096 static int niu_zcp_write(struct niu *np, int index, u64 *data) 5097 { 5098 nw64(ZCP_RAM_DATA0, data[0]); 5099 nw64(ZCP_RAM_DATA1, data[1]); 5100 nw64(ZCP_RAM_DATA2, data[2]); 5101 nw64(ZCP_RAM_DATA3, data[3]); 5102 nw64(ZCP_RAM_DATA4, data[4]); 5103 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); 5104 nw64(ZCP_RAM_ACC, 5105 (ZCP_RAM_ACC_WRITE | 5106 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5107 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5108 5109 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5110 1000, 100); 5111 } 5112 5113 static int niu_zcp_read(struct niu *np, int index, u64 *data) 5114 { 5115 int err; 5116 5117 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5118 1000, 100); 5119 if (err) { 5120 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n", 5121 (unsigned long long)nr64(ZCP_RAM_ACC)); 5122 return err; 5123 } 5124 5125 nw64(ZCP_RAM_ACC, 5126 (ZCP_RAM_ACC_READ | 5127 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5128 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5129 5130 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5131 1000, 100); 5132 if (err) { 5133 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n", 5134 (unsigned long long)nr64(ZCP_RAM_ACC)); 5135 return err; 5136 } 5137 5138 data[0] = nr64(ZCP_RAM_DATA0); 5139 data[1] = nr64(ZCP_RAM_DATA1); 5140 data[2] = nr64(ZCP_RAM_DATA2); 5141 data[3] = nr64(ZCP_RAM_DATA3); 5142 data[4] = nr64(ZCP_RAM_DATA4); 5143 5144 return 0; 5145 } 5146 5147 static void niu_zcp_cfifo_reset(struct niu *np) 5148 { 5149 u64 val = nr64(RESET_CFIFO); 5150 5151 val |= RESET_CFIFO_RST(np->port); 5152 nw64(RESET_CFIFO, val); 5153 udelay(10); 5154 5155 val &= ~RESET_CFIFO_RST(np->port); 5156 nw64(RESET_CFIFO, val); 5157 } 5158 5159 static int niu_init_zcp(struct niu *np) 5160 { 5161 u64 data[5], rbuf[5]; 5162 int i, max, err; 5163 5164 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5165 if (np->port == 0 || np->port == 1) 5166 max = ATLAS_P0_P1_CFIFO_ENTRIES; 5167 else 5168 max = ATLAS_P2_P3_CFIFO_ENTRIES; 5169 } else 5170 max = NIU_CFIFO_ENTRIES; 5171 5172 data[0] = 0; 5173 data[1] = 0; 5174 data[2] = 0; 5175 data[3] = 0; 5176 data[4] = 0; 5177 5178 for (i = 0; i < max; i++) { 5179 err = niu_zcp_write(np, i, data); 5180 if (err) 5181 return err; 5182 err = niu_zcp_read(np, i, rbuf); 5183 if (err) 5184 return err; 5185 } 5186 5187 niu_zcp_cfifo_reset(np); 5188 nw64(CFIFO_ECC(np->port), 0); 5189 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); 5190 (void) nr64(ZCP_INT_STAT); 5191 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); 5192 5193 return 0; 5194 } 5195 5196 static void niu_ipp_write(struct niu *np, int index, u64 *data) 5197 { 5198 u64 val = nr64_ipp(IPP_CFIG); 5199 5200 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); 5201 nw64_ipp(IPP_DFIFO_WR_PTR, index); 5202 nw64_ipp(IPP_DFIFO_WR0, data[0]); 5203 nw64_ipp(IPP_DFIFO_WR1, data[1]); 5204 nw64_ipp(IPP_DFIFO_WR2, data[2]); 5205 nw64_ipp(IPP_DFIFO_WR3, data[3]); 5206 nw64_ipp(IPP_DFIFO_WR4, data[4]); 5207 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); 5208 } 5209 5210 static void niu_ipp_read(struct niu *np, int index, u64 *data) 5211 { 5212 nw64_ipp(IPP_DFIFO_RD_PTR, index); 5213 data[0] = nr64_ipp(IPP_DFIFO_RD0); 5214 data[1] = nr64_ipp(IPP_DFIFO_RD1); 5215 data[2] = nr64_ipp(IPP_DFIFO_RD2); 5216 data[3] = nr64_ipp(IPP_DFIFO_RD3); 5217 data[4] = nr64_ipp(IPP_DFIFO_RD4); 5218 } 5219 5220 static int niu_ipp_reset(struct niu *np) 5221 { 5222 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST, 5223 1000, 100, "IPP_CFIG"); 5224 } 5225 5226 static int niu_init_ipp(struct niu *np) 5227 { 5228 u64 data[5], rbuf[5], val; 5229 int i, max, err; 5230 5231 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5232 if (np->port == 0 || np->port == 1) 5233 max = ATLAS_P0_P1_DFIFO_ENTRIES; 5234 else 5235 max = ATLAS_P2_P3_DFIFO_ENTRIES; 5236 } else 5237 max = NIU_DFIFO_ENTRIES; 5238 5239 data[0] = 0; 5240 data[1] = 0; 5241 data[2] = 0; 5242 data[3] = 0; 5243 data[4] = 0; 5244 5245 for (i = 0; i < max; i++) { 5246 niu_ipp_write(np, i, data); 5247 niu_ipp_read(np, i, rbuf); 5248 } 5249 5250 (void) nr64_ipp(IPP_INT_STAT); 5251 (void) nr64_ipp(IPP_INT_STAT); 5252 5253 err = niu_ipp_reset(np); 5254 if (err) 5255 return err; 5256 5257 (void) nr64_ipp(IPP_PKT_DIS); 5258 (void) nr64_ipp(IPP_BAD_CS_CNT); 5259 (void) nr64_ipp(IPP_ECC); 5260 5261 (void) nr64_ipp(IPP_INT_STAT); 5262 5263 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL); 5264 5265 val = nr64_ipp(IPP_CFIG); 5266 val &= ~IPP_CFIG_IP_MAX_PKT; 5267 val |= (IPP_CFIG_IPP_ENABLE | 5268 IPP_CFIG_DFIFO_ECC_EN | 5269 IPP_CFIG_DROP_BAD_CRC | 5270 IPP_CFIG_CKSUM_EN | 5271 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT)); 5272 nw64_ipp(IPP_CFIG, val); 5273 5274 return 0; 5275 } 5276 5277 static void niu_handle_led(struct niu *np, int status) 5278 { 5279 u64 val; 5280 val = nr64_mac(XMAC_CONFIG); 5281 5282 if ((np->flags & NIU_FLAGS_10G) != 0 && 5283 (np->flags & NIU_FLAGS_FIBER) != 0) { 5284 if (status) { 5285 val |= XMAC_CONFIG_LED_POLARITY; 5286 val &= ~XMAC_CONFIG_FORCE_LED_ON; 5287 } else { 5288 val |= XMAC_CONFIG_FORCE_LED_ON; 5289 val &= ~XMAC_CONFIG_LED_POLARITY; 5290 } 5291 } 5292 5293 nw64_mac(XMAC_CONFIG, val); 5294 } 5295 5296 static void niu_init_xif_xmac(struct niu *np) 5297 { 5298 struct niu_link_config *lp = &np->link_config; 5299 u64 val; 5300 5301 if (np->flags & NIU_FLAGS_XCVR_SERDES) { 5302 val = nr64(MIF_CONFIG); 5303 val |= MIF_CONFIG_ATCA_GE; 5304 nw64(MIF_CONFIG, val); 5305 } 5306 5307 val = nr64_mac(XMAC_CONFIG); 5308 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5309 5310 val |= XMAC_CONFIG_TX_OUTPUT_EN; 5311 5312 if (lp->loopback_mode == LOOPBACK_MAC) { 5313 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5314 val |= XMAC_CONFIG_LOOPBACK; 5315 } else { 5316 val &= ~XMAC_CONFIG_LOOPBACK; 5317 } 5318 5319 if (np->flags & NIU_FLAGS_10G) { 5320 val &= ~XMAC_CONFIG_LFS_DISABLE; 5321 } else { 5322 val |= XMAC_CONFIG_LFS_DISABLE; 5323 if (!(np->flags & NIU_FLAGS_FIBER) && 5324 !(np->flags & NIU_FLAGS_XCVR_SERDES)) 5325 val |= XMAC_CONFIG_1G_PCS_BYPASS; 5326 else 5327 val &= ~XMAC_CONFIG_1G_PCS_BYPASS; 5328 } 5329 5330 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5331 5332 if (lp->active_speed == SPEED_100) 5333 val |= XMAC_CONFIG_SEL_CLK_25MHZ; 5334 else 5335 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; 5336 5337 nw64_mac(XMAC_CONFIG, val); 5338 5339 val = nr64_mac(XMAC_CONFIG); 5340 val &= ~XMAC_CONFIG_MODE_MASK; 5341 if (np->flags & NIU_FLAGS_10G) { 5342 val |= XMAC_CONFIG_MODE_XGMII; 5343 } else { 5344 if (lp->active_speed == SPEED_1000) 5345 val |= XMAC_CONFIG_MODE_GMII; 5346 else 5347 val |= XMAC_CONFIG_MODE_MII; 5348 } 5349 5350 nw64_mac(XMAC_CONFIG, val); 5351 } 5352 5353 static void niu_init_xif_bmac(struct niu *np) 5354 { 5355 struct niu_link_config *lp = &np->link_config; 5356 u64 val; 5357 5358 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; 5359 5360 if (lp->loopback_mode == LOOPBACK_MAC) 5361 val |= BMAC_XIF_CONFIG_MII_LOOPBACK; 5362 else 5363 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; 5364 5365 if (lp->active_speed == SPEED_1000) 5366 val |= BMAC_XIF_CONFIG_GMII_MODE; 5367 else 5368 val &= ~BMAC_XIF_CONFIG_GMII_MODE; 5369 5370 val &= ~(BMAC_XIF_CONFIG_LINK_LED | 5371 BMAC_XIF_CONFIG_LED_POLARITY); 5372 5373 if (!(np->flags & NIU_FLAGS_10G) && 5374 !(np->flags & NIU_FLAGS_FIBER) && 5375 lp->active_speed == SPEED_100) 5376 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; 5377 else 5378 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; 5379 5380 nw64_mac(BMAC_XIF_CONFIG, val); 5381 } 5382 5383 static void niu_init_xif(struct niu *np) 5384 { 5385 if (np->flags & NIU_FLAGS_XMAC) 5386 niu_init_xif_xmac(np); 5387 else 5388 niu_init_xif_bmac(np); 5389 } 5390 5391 static void niu_pcs_mii_reset(struct niu *np) 5392 { 5393 int limit = 1000; 5394 u64 val = nr64_pcs(PCS_MII_CTL); 5395 val |= PCS_MII_CTL_RST; 5396 nw64_pcs(PCS_MII_CTL, val); 5397 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) { 5398 udelay(100); 5399 val = nr64_pcs(PCS_MII_CTL); 5400 } 5401 } 5402 5403 static void niu_xpcs_reset(struct niu *np) 5404 { 5405 int limit = 1000; 5406 u64 val = nr64_xpcs(XPCS_CONTROL1); 5407 val |= XPCS_CONTROL1_RESET; 5408 nw64_xpcs(XPCS_CONTROL1, val); 5409 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) { 5410 udelay(100); 5411 val = nr64_xpcs(XPCS_CONTROL1); 5412 } 5413 } 5414 5415 static int niu_init_pcs(struct niu *np) 5416 { 5417 struct niu_link_config *lp = &np->link_config; 5418 u64 val; 5419 5420 switch (np->flags & (NIU_FLAGS_10G | 5421 NIU_FLAGS_FIBER | 5422 NIU_FLAGS_XCVR_SERDES)) { 5423 case NIU_FLAGS_FIBER: 5424 /* 1G fiber */ 5425 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5426 nw64_pcs(PCS_DPATH_MODE, 0); 5427 niu_pcs_mii_reset(np); 5428 break; 5429 5430 case NIU_FLAGS_10G: 5431 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 5432 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 5433 /* 10G SERDES */ 5434 if (!(np->flags & NIU_FLAGS_XMAC)) 5435 return -EINVAL; 5436 5437 /* 10G copper or fiber */ 5438 val = nr64_mac(XMAC_CONFIG); 5439 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5440 nw64_mac(XMAC_CONFIG, val); 5441 5442 niu_xpcs_reset(np); 5443 5444 val = nr64_xpcs(XPCS_CONTROL1); 5445 if (lp->loopback_mode == LOOPBACK_PHY) 5446 val |= XPCS_CONTROL1_LOOPBACK; 5447 else 5448 val &= ~XPCS_CONTROL1_LOOPBACK; 5449 nw64_xpcs(XPCS_CONTROL1, val); 5450 5451 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0); 5452 (void) nr64_xpcs(XPCS_SYMERR_CNT01); 5453 (void) nr64_xpcs(XPCS_SYMERR_CNT23); 5454 break; 5455 5456 5457 case NIU_FLAGS_XCVR_SERDES: 5458 /* 1G SERDES */ 5459 niu_pcs_mii_reset(np); 5460 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5461 nw64_pcs(PCS_DPATH_MODE, 0); 5462 break; 5463 5464 case 0: 5465 /* 1G copper */ 5466 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 5467 /* 1G RGMII FIBER */ 5468 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII); 5469 niu_pcs_mii_reset(np); 5470 break; 5471 5472 default: 5473 return -EINVAL; 5474 } 5475 5476 return 0; 5477 } 5478 5479 static int niu_reset_tx_xmac(struct niu *np) 5480 { 5481 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST, 5482 (XTXMAC_SW_RST_REG_RS | 5483 XTXMAC_SW_RST_SOFT_RST), 5484 1000, 100, "XTXMAC_SW_RST"); 5485 } 5486 5487 static int niu_reset_tx_bmac(struct niu *np) 5488 { 5489 int limit; 5490 5491 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET); 5492 limit = 1000; 5493 while (--limit >= 0) { 5494 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET)) 5495 break; 5496 udelay(100); 5497 } 5498 if (limit < 0) { 5499 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n", 5500 np->port, 5501 (unsigned long long) nr64_mac(BTXMAC_SW_RST)); 5502 return -ENODEV; 5503 } 5504 5505 return 0; 5506 } 5507 5508 static int niu_reset_tx_mac(struct niu *np) 5509 { 5510 if (np->flags & NIU_FLAGS_XMAC) 5511 return niu_reset_tx_xmac(np); 5512 else 5513 return niu_reset_tx_bmac(np); 5514 } 5515 5516 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max) 5517 { 5518 u64 val; 5519 5520 val = nr64_mac(XMAC_MIN); 5521 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | 5522 XMAC_MIN_RX_MIN_PKT_SIZE); 5523 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); 5524 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); 5525 nw64_mac(XMAC_MIN, val); 5526 5527 nw64_mac(XMAC_MAX, max); 5528 5529 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0); 5530 5531 val = nr64_mac(XMAC_IPG); 5532 if (np->flags & NIU_FLAGS_10G) { 5533 val &= ~XMAC_IPG_IPG_XGMII; 5534 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); 5535 } else { 5536 val &= ~XMAC_IPG_IPG_MII_GMII; 5537 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); 5538 } 5539 nw64_mac(XMAC_IPG, val); 5540 5541 val = nr64_mac(XMAC_CONFIG); 5542 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | 5543 XMAC_CONFIG_STRETCH_MODE | 5544 XMAC_CONFIG_VAR_MIN_IPG_EN | 5545 XMAC_CONFIG_TX_ENABLE); 5546 nw64_mac(XMAC_CONFIG, val); 5547 5548 nw64_mac(TXMAC_FRM_CNT, 0); 5549 nw64_mac(TXMAC_BYTE_CNT, 0); 5550 } 5551 5552 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max) 5553 { 5554 u64 val; 5555 5556 nw64_mac(BMAC_MIN_FRAME, min); 5557 nw64_mac(BMAC_MAX_FRAME, max); 5558 5559 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0); 5560 nw64_mac(BMAC_CTRL_TYPE, 0x8808); 5561 nw64_mac(BMAC_PREAMBLE_SIZE, 7); 5562 5563 val = nr64_mac(BTXMAC_CONFIG); 5564 val &= ~(BTXMAC_CONFIG_FCS_DISABLE | 5565 BTXMAC_CONFIG_ENABLE); 5566 nw64_mac(BTXMAC_CONFIG, val); 5567 } 5568 5569 static void niu_init_tx_mac(struct niu *np) 5570 { 5571 u64 min, max; 5572 5573 min = 64; 5574 if (np->dev->mtu > ETH_DATA_LEN) 5575 max = 9216; 5576 else 5577 max = 1522; 5578 5579 /* The XMAC_MIN register only accepts values for TX min which 5580 * have the low 3 bits cleared. 5581 */ 5582 BUG_ON(min & 0x7); 5583 5584 if (np->flags & NIU_FLAGS_XMAC) 5585 niu_init_tx_xmac(np, min, max); 5586 else 5587 niu_init_tx_bmac(np, min, max); 5588 } 5589 5590 static int niu_reset_rx_xmac(struct niu *np) 5591 { 5592 int limit; 5593 5594 nw64_mac(XRXMAC_SW_RST, 5595 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST); 5596 limit = 1000; 5597 while (--limit >= 0) { 5598 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS | 5599 XRXMAC_SW_RST_SOFT_RST))) 5600 break; 5601 udelay(100); 5602 } 5603 if (limit < 0) { 5604 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n", 5605 np->port, 5606 (unsigned long long) nr64_mac(XRXMAC_SW_RST)); 5607 return -ENODEV; 5608 } 5609 5610 return 0; 5611 } 5612 5613 static int niu_reset_rx_bmac(struct niu *np) 5614 { 5615 int limit; 5616 5617 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET); 5618 limit = 1000; 5619 while (--limit >= 0) { 5620 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET)) 5621 break; 5622 udelay(100); 5623 } 5624 if (limit < 0) { 5625 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n", 5626 np->port, 5627 (unsigned long long) nr64_mac(BRXMAC_SW_RST)); 5628 return -ENODEV; 5629 } 5630 5631 return 0; 5632 } 5633 5634 static int niu_reset_rx_mac(struct niu *np) 5635 { 5636 if (np->flags & NIU_FLAGS_XMAC) 5637 return niu_reset_rx_xmac(np); 5638 else 5639 return niu_reset_rx_bmac(np); 5640 } 5641 5642 static void niu_init_rx_xmac(struct niu *np) 5643 { 5644 struct niu_parent *parent = np->parent; 5645 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5646 int first_rdc_table = tp->first_table_num; 5647 unsigned long i; 5648 u64 val; 5649 5650 nw64_mac(XMAC_ADD_FILT0, 0); 5651 nw64_mac(XMAC_ADD_FILT1, 0); 5652 nw64_mac(XMAC_ADD_FILT2, 0); 5653 nw64_mac(XMAC_ADD_FILT12_MASK, 0); 5654 nw64_mac(XMAC_ADD_FILT00_MASK, 0); 5655 for (i = 0; i < MAC_NUM_HASH; i++) 5656 nw64_mac(XMAC_HASH_TBL(i), 0); 5657 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0); 5658 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5659 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5660 5661 val = nr64_mac(XMAC_CONFIG); 5662 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | 5663 XMAC_CONFIG_PROMISCUOUS | 5664 XMAC_CONFIG_PROMISC_GROUP | 5665 XMAC_CONFIG_ERR_CHK_DIS | 5666 XMAC_CONFIG_RX_CRC_CHK_DIS | 5667 XMAC_CONFIG_RESERVED_MULTICAST | 5668 XMAC_CONFIG_RX_CODEV_CHK_DIS | 5669 XMAC_CONFIG_ADDR_FILTER_EN | 5670 XMAC_CONFIG_RCV_PAUSE_ENABLE | 5671 XMAC_CONFIG_STRIP_CRC | 5672 XMAC_CONFIG_PASS_FLOW_CTRL | 5673 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN); 5674 val |= (XMAC_CONFIG_HASH_FILTER_EN); 5675 nw64_mac(XMAC_CONFIG, val); 5676 5677 nw64_mac(RXMAC_BT_CNT, 0); 5678 nw64_mac(RXMAC_BC_FRM_CNT, 0); 5679 nw64_mac(RXMAC_MC_FRM_CNT, 0); 5680 nw64_mac(RXMAC_FRAG_CNT, 0); 5681 nw64_mac(RXMAC_HIST_CNT1, 0); 5682 nw64_mac(RXMAC_HIST_CNT2, 0); 5683 nw64_mac(RXMAC_HIST_CNT3, 0); 5684 nw64_mac(RXMAC_HIST_CNT4, 0); 5685 nw64_mac(RXMAC_HIST_CNT5, 0); 5686 nw64_mac(RXMAC_HIST_CNT6, 0); 5687 nw64_mac(RXMAC_HIST_CNT7, 0); 5688 nw64_mac(RXMAC_MPSZER_CNT, 0); 5689 nw64_mac(RXMAC_CRC_ER_CNT, 0); 5690 nw64_mac(RXMAC_CD_VIO_CNT, 0); 5691 nw64_mac(LINK_FAULT_CNT, 0); 5692 } 5693 5694 static void niu_init_rx_bmac(struct niu *np) 5695 { 5696 struct niu_parent *parent = np->parent; 5697 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5698 int first_rdc_table = tp->first_table_num; 5699 unsigned long i; 5700 u64 val; 5701 5702 nw64_mac(BMAC_ADD_FILT0, 0); 5703 nw64_mac(BMAC_ADD_FILT1, 0); 5704 nw64_mac(BMAC_ADD_FILT2, 0); 5705 nw64_mac(BMAC_ADD_FILT12_MASK, 0); 5706 nw64_mac(BMAC_ADD_FILT00_MASK, 0); 5707 for (i = 0; i < MAC_NUM_HASH; i++) 5708 nw64_mac(BMAC_HASH_TBL(i), 0); 5709 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5710 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5711 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0); 5712 5713 val = nr64_mac(BRXMAC_CONFIG); 5714 val &= ~(BRXMAC_CONFIG_ENABLE | 5715 BRXMAC_CONFIG_STRIP_PAD | 5716 BRXMAC_CONFIG_STRIP_FCS | 5717 BRXMAC_CONFIG_PROMISC | 5718 BRXMAC_CONFIG_PROMISC_GRP | 5719 BRXMAC_CONFIG_ADDR_FILT_EN | 5720 BRXMAC_CONFIG_DISCARD_DIS); 5721 val |= (BRXMAC_CONFIG_HASH_FILT_EN); 5722 nw64_mac(BRXMAC_CONFIG, val); 5723 5724 val = nr64_mac(BMAC_ADDR_CMPEN); 5725 val |= BMAC_ADDR_CMPEN_EN0; 5726 nw64_mac(BMAC_ADDR_CMPEN, val); 5727 } 5728 5729 static void niu_init_rx_mac(struct niu *np) 5730 { 5731 niu_set_primary_mac(np, np->dev->dev_addr); 5732 5733 if (np->flags & NIU_FLAGS_XMAC) 5734 niu_init_rx_xmac(np); 5735 else 5736 niu_init_rx_bmac(np); 5737 } 5738 5739 static void niu_enable_tx_xmac(struct niu *np, int on) 5740 { 5741 u64 val = nr64_mac(XMAC_CONFIG); 5742 5743 if (on) 5744 val |= XMAC_CONFIG_TX_ENABLE; 5745 else 5746 val &= ~XMAC_CONFIG_TX_ENABLE; 5747 nw64_mac(XMAC_CONFIG, val); 5748 } 5749 5750 static void niu_enable_tx_bmac(struct niu *np, int on) 5751 { 5752 u64 val = nr64_mac(BTXMAC_CONFIG); 5753 5754 if (on) 5755 val |= BTXMAC_CONFIG_ENABLE; 5756 else 5757 val &= ~BTXMAC_CONFIG_ENABLE; 5758 nw64_mac(BTXMAC_CONFIG, val); 5759 } 5760 5761 static void niu_enable_tx_mac(struct niu *np, int on) 5762 { 5763 if (np->flags & NIU_FLAGS_XMAC) 5764 niu_enable_tx_xmac(np, on); 5765 else 5766 niu_enable_tx_bmac(np, on); 5767 } 5768 5769 static void niu_enable_rx_xmac(struct niu *np, int on) 5770 { 5771 u64 val = nr64_mac(XMAC_CONFIG); 5772 5773 val &= ~(XMAC_CONFIG_HASH_FILTER_EN | 5774 XMAC_CONFIG_PROMISCUOUS); 5775 5776 if (np->flags & NIU_FLAGS_MCAST) 5777 val |= XMAC_CONFIG_HASH_FILTER_EN; 5778 if (np->flags & NIU_FLAGS_PROMISC) 5779 val |= XMAC_CONFIG_PROMISCUOUS; 5780 5781 if (on) 5782 val |= XMAC_CONFIG_RX_MAC_ENABLE; 5783 else 5784 val &= ~XMAC_CONFIG_RX_MAC_ENABLE; 5785 nw64_mac(XMAC_CONFIG, val); 5786 } 5787 5788 static void niu_enable_rx_bmac(struct niu *np, int on) 5789 { 5790 u64 val = nr64_mac(BRXMAC_CONFIG); 5791 5792 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | 5793 BRXMAC_CONFIG_PROMISC); 5794 5795 if (np->flags & NIU_FLAGS_MCAST) 5796 val |= BRXMAC_CONFIG_HASH_FILT_EN; 5797 if (np->flags & NIU_FLAGS_PROMISC) 5798 val |= BRXMAC_CONFIG_PROMISC; 5799 5800 if (on) 5801 val |= BRXMAC_CONFIG_ENABLE; 5802 else 5803 val &= ~BRXMAC_CONFIG_ENABLE; 5804 nw64_mac(BRXMAC_CONFIG, val); 5805 } 5806 5807 static void niu_enable_rx_mac(struct niu *np, int on) 5808 { 5809 if (np->flags & NIU_FLAGS_XMAC) 5810 niu_enable_rx_xmac(np, on); 5811 else 5812 niu_enable_rx_bmac(np, on); 5813 } 5814 5815 static int niu_init_mac(struct niu *np) 5816 { 5817 int err; 5818 5819 niu_init_xif(np); 5820 err = niu_init_pcs(np); 5821 if (err) 5822 return err; 5823 5824 err = niu_reset_tx_mac(np); 5825 if (err) 5826 return err; 5827 niu_init_tx_mac(np); 5828 err = niu_reset_rx_mac(np); 5829 if (err) 5830 return err; 5831 niu_init_rx_mac(np); 5832 5833 /* This looks hookey but the RX MAC reset we just did will 5834 * undo some of the state we setup in niu_init_tx_mac() so we 5835 * have to call it again. In particular, the RX MAC reset will 5836 * set the XMAC_MAX register back to it's default value. 5837 */ 5838 niu_init_tx_mac(np); 5839 niu_enable_tx_mac(np, 1); 5840 5841 niu_enable_rx_mac(np, 1); 5842 5843 return 0; 5844 } 5845 5846 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5847 { 5848 (void) niu_tx_channel_stop(np, rp->tx_channel); 5849 } 5850 5851 static void niu_stop_tx_channels(struct niu *np) 5852 { 5853 int i; 5854 5855 for (i = 0; i < np->num_tx_rings; i++) { 5856 struct tx_ring_info *rp = &np->tx_rings[i]; 5857 5858 niu_stop_one_tx_channel(np, rp); 5859 } 5860 } 5861 5862 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5863 { 5864 (void) niu_tx_channel_reset(np, rp->tx_channel); 5865 } 5866 5867 static void niu_reset_tx_channels(struct niu *np) 5868 { 5869 int i; 5870 5871 for (i = 0; i < np->num_tx_rings; i++) { 5872 struct tx_ring_info *rp = &np->tx_rings[i]; 5873 5874 niu_reset_one_tx_channel(np, rp); 5875 } 5876 } 5877 5878 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5879 { 5880 (void) niu_enable_rx_channel(np, rp->rx_channel, 0); 5881 } 5882 5883 static void niu_stop_rx_channels(struct niu *np) 5884 { 5885 int i; 5886 5887 for (i = 0; i < np->num_rx_rings; i++) { 5888 struct rx_ring_info *rp = &np->rx_rings[i]; 5889 5890 niu_stop_one_rx_channel(np, rp); 5891 } 5892 } 5893 5894 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5895 { 5896 int channel = rp->rx_channel; 5897 5898 (void) niu_rx_channel_reset(np, channel); 5899 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); 5900 nw64(RX_DMA_CTL_STAT(channel), 0); 5901 (void) niu_enable_rx_channel(np, channel, 0); 5902 } 5903 5904 static void niu_reset_rx_channels(struct niu *np) 5905 { 5906 int i; 5907 5908 for (i = 0; i < np->num_rx_rings; i++) { 5909 struct rx_ring_info *rp = &np->rx_rings[i]; 5910 5911 niu_reset_one_rx_channel(np, rp); 5912 } 5913 } 5914 5915 static void niu_disable_ipp(struct niu *np) 5916 { 5917 u64 rd, wr, val; 5918 int limit; 5919 5920 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5921 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5922 limit = 100; 5923 while (--limit >= 0 && (rd != wr)) { 5924 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5925 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5926 } 5927 if (limit < 0 && 5928 (rd != 0 && wr != 1)) { 5929 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n", 5930 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR), 5931 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR)); 5932 } 5933 5934 val = nr64_ipp(IPP_CFIG); 5935 val &= ~(IPP_CFIG_IPP_ENABLE | 5936 IPP_CFIG_DFIFO_ECC_EN | 5937 IPP_CFIG_DROP_BAD_CRC | 5938 IPP_CFIG_CKSUM_EN); 5939 nw64_ipp(IPP_CFIG, val); 5940 5941 (void) niu_ipp_reset(np); 5942 } 5943 5944 static int niu_init_hw(struct niu *np) 5945 { 5946 int i, err; 5947 5948 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n"); 5949 niu_txc_enable_port(np, 1); 5950 niu_txc_port_dma_enable(np, 1); 5951 niu_txc_set_imask(np, 0); 5952 5953 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n"); 5954 for (i = 0; i < np->num_tx_rings; i++) { 5955 struct tx_ring_info *rp = &np->tx_rings[i]; 5956 5957 err = niu_init_one_tx_channel(np, rp); 5958 if (err) 5959 return err; 5960 } 5961 5962 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n"); 5963 err = niu_init_rx_channels(np); 5964 if (err) 5965 goto out_uninit_tx_channels; 5966 5967 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n"); 5968 err = niu_init_classifier_hw(np); 5969 if (err) 5970 goto out_uninit_rx_channels; 5971 5972 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n"); 5973 err = niu_init_zcp(np); 5974 if (err) 5975 goto out_uninit_rx_channels; 5976 5977 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n"); 5978 err = niu_init_ipp(np); 5979 if (err) 5980 goto out_uninit_rx_channels; 5981 5982 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n"); 5983 err = niu_init_mac(np); 5984 if (err) 5985 goto out_uninit_ipp; 5986 5987 return 0; 5988 5989 out_uninit_ipp: 5990 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n"); 5991 niu_disable_ipp(np); 5992 5993 out_uninit_rx_channels: 5994 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n"); 5995 niu_stop_rx_channels(np); 5996 niu_reset_rx_channels(np); 5997 5998 out_uninit_tx_channels: 5999 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n"); 6000 niu_stop_tx_channels(np); 6001 niu_reset_tx_channels(np); 6002 6003 return err; 6004 } 6005 6006 static void niu_stop_hw(struct niu *np) 6007 { 6008 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n"); 6009 niu_enable_interrupts(np, 0); 6010 6011 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n"); 6012 niu_enable_rx_mac(np, 0); 6013 6014 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n"); 6015 niu_disable_ipp(np); 6016 6017 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n"); 6018 niu_stop_tx_channels(np); 6019 6020 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n"); 6021 niu_stop_rx_channels(np); 6022 6023 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n"); 6024 niu_reset_tx_channels(np); 6025 6026 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n"); 6027 niu_reset_rx_channels(np); 6028 } 6029 6030 static void niu_set_irq_name(struct niu *np) 6031 { 6032 int port = np->port; 6033 int i, j = 1; 6034 6035 sprintf(np->irq_name[0], "%s:MAC", np->dev->name); 6036 6037 if (port == 0) { 6038 sprintf(np->irq_name[1], "%s:MIF", np->dev->name); 6039 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name); 6040 j = 3; 6041 } 6042 6043 for (i = 0; i < np->num_ldg - j; i++) { 6044 if (i < np->num_rx_rings) 6045 sprintf(np->irq_name[i+j], "%s-rx-%d", 6046 np->dev->name, i); 6047 else if (i < np->num_tx_rings + np->num_rx_rings) 6048 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name, 6049 i - np->num_rx_rings); 6050 } 6051 } 6052 6053 static int niu_request_irq(struct niu *np) 6054 { 6055 int i, j, err; 6056 6057 niu_set_irq_name(np); 6058 6059 err = 0; 6060 for (i = 0; i < np->num_ldg; i++) { 6061 struct niu_ldg *lp = &np->ldg[i]; 6062 6063 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED, 6064 np->irq_name[i], lp); 6065 if (err) 6066 goto out_free_irqs; 6067 6068 } 6069 6070 return 0; 6071 6072 out_free_irqs: 6073 for (j = 0; j < i; j++) { 6074 struct niu_ldg *lp = &np->ldg[j]; 6075 6076 free_irq(lp->irq, lp); 6077 } 6078 return err; 6079 } 6080 6081 static void niu_free_irq(struct niu *np) 6082 { 6083 int i; 6084 6085 for (i = 0; i < np->num_ldg; i++) { 6086 struct niu_ldg *lp = &np->ldg[i]; 6087 6088 free_irq(lp->irq, lp); 6089 } 6090 } 6091 6092 static void niu_enable_napi(struct niu *np) 6093 { 6094 int i; 6095 6096 for (i = 0; i < np->num_ldg; i++) 6097 napi_enable(&np->ldg[i].napi); 6098 } 6099 6100 static void niu_disable_napi(struct niu *np) 6101 { 6102 int i; 6103 6104 for (i = 0; i < np->num_ldg; i++) 6105 napi_disable(&np->ldg[i].napi); 6106 } 6107 6108 static int niu_open(struct net_device *dev) 6109 { 6110 struct niu *np = netdev_priv(dev); 6111 int err; 6112 6113 netif_carrier_off(dev); 6114 6115 err = niu_alloc_channels(np); 6116 if (err) 6117 goto out_err; 6118 6119 err = niu_enable_interrupts(np, 0); 6120 if (err) 6121 goto out_free_channels; 6122 6123 err = niu_request_irq(np); 6124 if (err) 6125 goto out_free_channels; 6126 6127 niu_enable_napi(np); 6128 6129 spin_lock_irq(&np->lock); 6130 6131 err = niu_init_hw(np); 6132 if (!err) { 6133 init_timer(&np->timer); 6134 np->timer.expires = jiffies + HZ; 6135 np->timer.data = (unsigned long) np; 6136 np->timer.function = niu_timer; 6137 6138 err = niu_enable_interrupts(np, 1); 6139 if (err) 6140 niu_stop_hw(np); 6141 } 6142 6143 spin_unlock_irq(&np->lock); 6144 6145 if (err) { 6146 niu_disable_napi(np); 6147 goto out_free_irq; 6148 } 6149 6150 netif_tx_start_all_queues(dev); 6151 6152 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6153 netif_carrier_on(dev); 6154 6155 add_timer(&np->timer); 6156 6157 return 0; 6158 6159 out_free_irq: 6160 niu_free_irq(np); 6161 6162 out_free_channels: 6163 niu_free_channels(np); 6164 6165 out_err: 6166 return err; 6167 } 6168 6169 static void niu_full_shutdown(struct niu *np, struct net_device *dev) 6170 { 6171 cancel_work_sync(&np->reset_task); 6172 6173 niu_disable_napi(np); 6174 netif_tx_stop_all_queues(dev); 6175 6176 del_timer_sync(&np->timer); 6177 6178 spin_lock_irq(&np->lock); 6179 6180 niu_stop_hw(np); 6181 6182 spin_unlock_irq(&np->lock); 6183 } 6184 6185 static int niu_close(struct net_device *dev) 6186 { 6187 struct niu *np = netdev_priv(dev); 6188 6189 niu_full_shutdown(np, dev); 6190 6191 niu_free_irq(np); 6192 6193 niu_free_channels(np); 6194 6195 niu_handle_led(np, 0); 6196 6197 return 0; 6198 } 6199 6200 static void niu_sync_xmac_stats(struct niu *np) 6201 { 6202 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 6203 6204 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT); 6205 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT); 6206 6207 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT); 6208 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT); 6209 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT); 6210 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT); 6211 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT); 6212 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1); 6213 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2); 6214 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3); 6215 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4); 6216 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5); 6217 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6); 6218 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7); 6219 mp->rx_octets += nr64_mac(RXMAC_BT_CNT); 6220 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT); 6221 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT); 6222 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT); 6223 } 6224 6225 static void niu_sync_bmac_stats(struct niu *np) 6226 { 6227 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 6228 6229 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT); 6230 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT); 6231 6232 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT); 6233 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6234 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6235 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT); 6236 } 6237 6238 static void niu_sync_mac_stats(struct niu *np) 6239 { 6240 if (np->flags & NIU_FLAGS_XMAC) 6241 niu_sync_xmac_stats(np); 6242 else 6243 niu_sync_bmac_stats(np); 6244 } 6245 6246 static void niu_get_rx_stats(struct niu *np, 6247 struct rtnl_link_stats64 *stats) 6248 { 6249 u64 pkts, dropped, errors, bytes; 6250 struct rx_ring_info *rx_rings; 6251 int i; 6252 6253 pkts = dropped = errors = bytes = 0; 6254 6255 rx_rings = ACCESS_ONCE(np->rx_rings); 6256 if (!rx_rings) 6257 goto no_rings; 6258 6259 for (i = 0; i < np->num_rx_rings; i++) { 6260 struct rx_ring_info *rp = &rx_rings[i]; 6261 6262 niu_sync_rx_discard_stats(np, rp, 0); 6263 6264 pkts += rp->rx_packets; 6265 bytes += rp->rx_bytes; 6266 dropped += rp->rx_dropped; 6267 errors += rp->rx_errors; 6268 } 6269 6270 no_rings: 6271 stats->rx_packets = pkts; 6272 stats->rx_bytes = bytes; 6273 stats->rx_dropped = dropped; 6274 stats->rx_errors = errors; 6275 } 6276 6277 static void niu_get_tx_stats(struct niu *np, 6278 struct rtnl_link_stats64 *stats) 6279 { 6280 u64 pkts, errors, bytes; 6281 struct tx_ring_info *tx_rings; 6282 int i; 6283 6284 pkts = errors = bytes = 0; 6285 6286 tx_rings = ACCESS_ONCE(np->tx_rings); 6287 if (!tx_rings) 6288 goto no_rings; 6289 6290 for (i = 0; i < np->num_tx_rings; i++) { 6291 struct tx_ring_info *rp = &tx_rings[i]; 6292 6293 pkts += rp->tx_packets; 6294 bytes += rp->tx_bytes; 6295 errors += rp->tx_errors; 6296 } 6297 6298 no_rings: 6299 stats->tx_packets = pkts; 6300 stats->tx_bytes = bytes; 6301 stats->tx_errors = errors; 6302 } 6303 6304 static struct rtnl_link_stats64 *niu_get_stats(struct net_device *dev, 6305 struct rtnl_link_stats64 *stats) 6306 { 6307 struct niu *np = netdev_priv(dev); 6308 6309 if (netif_running(dev)) { 6310 niu_get_rx_stats(np, stats); 6311 niu_get_tx_stats(np, stats); 6312 } 6313 6314 return stats; 6315 } 6316 6317 static void niu_load_hash_xmac(struct niu *np, u16 *hash) 6318 { 6319 int i; 6320 6321 for (i = 0; i < 16; i++) 6322 nw64_mac(XMAC_HASH_TBL(i), hash[i]); 6323 } 6324 6325 static void niu_load_hash_bmac(struct niu *np, u16 *hash) 6326 { 6327 int i; 6328 6329 for (i = 0; i < 16; i++) 6330 nw64_mac(BMAC_HASH_TBL(i), hash[i]); 6331 } 6332 6333 static void niu_load_hash(struct niu *np, u16 *hash) 6334 { 6335 if (np->flags & NIU_FLAGS_XMAC) 6336 niu_load_hash_xmac(np, hash); 6337 else 6338 niu_load_hash_bmac(np, hash); 6339 } 6340 6341 static void niu_set_rx_mode(struct net_device *dev) 6342 { 6343 struct niu *np = netdev_priv(dev); 6344 int i, alt_cnt, err; 6345 struct netdev_hw_addr *ha; 6346 unsigned long flags; 6347 u16 hash[16] = { 0, }; 6348 6349 spin_lock_irqsave(&np->lock, flags); 6350 niu_enable_rx_mac(np, 0); 6351 6352 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC); 6353 if (dev->flags & IFF_PROMISC) 6354 np->flags |= NIU_FLAGS_PROMISC; 6355 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev))) 6356 np->flags |= NIU_FLAGS_MCAST; 6357 6358 alt_cnt = netdev_uc_count(dev); 6359 if (alt_cnt > niu_num_alt_addr(np)) { 6360 alt_cnt = 0; 6361 np->flags |= NIU_FLAGS_PROMISC; 6362 } 6363 6364 if (alt_cnt) { 6365 int index = 0; 6366 6367 netdev_for_each_uc_addr(ha, dev) { 6368 err = niu_set_alt_mac(np, index, ha->addr); 6369 if (err) 6370 netdev_warn(dev, "Error %d adding alt mac %d\n", 6371 err, index); 6372 err = niu_enable_alt_mac(np, index, 1); 6373 if (err) 6374 netdev_warn(dev, "Error %d enabling alt mac %d\n", 6375 err, index); 6376 6377 index++; 6378 } 6379 } else { 6380 int alt_start; 6381 if (np->flags & NIU_FLAGS_XMAC) 6382 alt_start = 0; 6383 else 6384 alt_start = 1; 6385 for (i = alt_start; i < niu_num_alt_addr(np); i++) { 6386 err = niu_enable_alt_mac(np, i, 0); 6387 if (err) 6388 netdev_warn(dev, "Error %d disabling alt mac %d\n", 6389 err, i); 6390 } 6391 } 6392 if (dev->flags & IFF_ALLMULTI) { 6393 for (i = 0; i < 16; i++) 6394 hash[i] = 0xffff; 6395 } else if (!netdev_mc_empty(dev)) { 6396 netdev_for_each_mc_addr(ha, dev) { 6397 u32 crc = ether_crc_le(ETH_ALEN, ha->addr); 6398 6399 crc >>= 24; 6400 hash[crc >> 4] |= (1 << (15 - (crc & 0xf))); 6401 } 6402 } 6403 6404 if (np->flags & NIU_FLAGS_MCAST) 6405 niu_load_hash(np, hash); 6406 6407 niu_enable_rx_mac(np, 1); 6408 spin_unlock_irqrestore(&np->lock, flags); 6409 } 6410 6411 static int niu_set_mac_addr(struct net_device *dev, void *p) 6412 { 6413 struct niu *np = netdev_priv(dev); 6414 struct sockaddr *addr = p; 6415 unsigned long flags; 6416 6417 if (!is_valid_ether_addr(addr->sa_data)) 6418 return -EINVAL; 6419 6420 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN); 6421 6422 if (!netif_running(dev)) 6423 return 0; 6424 6425 spin_lock_irqsave(&np->lock, flags); 6426 niu_enable_rx_mac(np, 0); 6427 niu_set_primary_mac(np, dev->dev_addr); 6428 niu_enable_rx_mac(np, 1); 6429 spin_unlock_irqrestore(&np->lock, flags); 6430 6431 return 0; 6432 } 6433 6434 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 6435 { 6436 return -EOPNOTSUPP; 6437 } 6438 6439 static void niu_netif_stop(struct niu *np) 6440 { 6441 np->dev->trans_start = jiffies; /* prevent tx timeout */ 6442 6443 niu_disable_napi(np); 6444 6445 netif_tx_disable(np->dev); 6446 } 6447 6448 static void niu_netif_start(struct niu *np) 6449 { 6450 /* NOTE: unconditional netif_wake_queue is only appropriate 6451 * so long as all callers are assured to have free tx slots 6452 * (such as after niu_init_hw). 6453 */ 6454 netif_tx_wake_all_queues(np->dev); 6455 6456 niu_enable_napi(np); 6457 6458 niu_enable_interrupts(np, 1); 6459 } 6460 6461 static void niu_reset_buffers(struct niu *np) 6462 { 6463 int i, j, k, err; 6464 6465 if (np->rx_rings) { 6466 for (i = 0; i < np->num_rx_rings; i++) { 6467 struct rx_ring_info *rp = &np->rx_rings[i]; 6468 6469 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) { 6470 struct page *page; 6471 6472 page = rp->rxhash[j]; 6473 while (page) { 6474 struct page *next = 6475 (struct page *) page->mapping; 6476 u64 base = page->index; 6477 base = base >> RBR_DESCR_ADDR_SHIFT; 6478 rp->rbr[k++] = cpu_to_le32(base); 6479 page = next; 6480 } 6481 } 6482 for (; k < MAX_RBR_RING_SIZE; k++) { 6483 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k); 6484 if (unlikely(err)) 6485 break; 6486 } 6487 6488 rp->rbr_index = rp->rbr_table_size - 1; 6489 rp->rcr_index = 0; 6490 rp->rbr_pending = 0; 6491 rp->rbr_refill_pending = 0; 6492 } 6493 } 6494 if (np->tx_rings) { 6495 for (i = 0; i < np->num_tx_rings; i++) { 6496 struct tx_ring_info *rp = &np->tx_rings[i]; 6497 6498 for (j = 0; j < MAX_TX_RING_SIZE; j++) { 6499 if (rp->tx_buffs[j].skb) 6500 (void) release_tx_packet(np, rp, j); 6501 } 6502 6503 rp->pending = MAX_TX_RING_SIZE; 6504 rp->prod = 0; 6505 rp->cons = 0; 6506 rp->wrap_bit = 0; 6507 } 6508 } 6509 } 6510 6511 static void niu_reset_task(struct work_struct *work) 6512 { 6513 struct niu *np = container_of(work, struct niu, reset_task); 6514 unsigned long flags; 6515 int err; 6516 6517 spin_lock_irqsave(&np->lock, flags); 6518 if (!netif_running(np->dev)) { 6519 spin_unlock_irqrestore(&np->lock, flags); 6520 return; 6521 } 6522 6523 spin_unlock_irqrestore(&np->lock, flags); 6524 6525 del_timer_sync(&np->timer); 6526 6527 niu_netif_stop(np); 6528 6529 spin_lock_irqsave(&np->lock, flags); 6530 6531 niu_stop_hw(np); 6532 6533 spin_unlock_irqrestore(&np->lock, flags); 6534 6535 niu_reset_buffers(np); 6536 6537 spin_lock_irqsave(&np->lock, flags); 6538 6539 err = niu_init_hw(np); 6540 if (!err) { 6541 np->timer.expires = jiffies + HZ; 6542 add_timer(&np->timer); 6543 niu_netif_start(np); 6544 } 6545 6546 spin_unlock_irqrestore(&np->lock, flags); 6547 } 6548 6549 static void niu_tx_timeout(struct net_device *dev) 6550 { 6551 struct niu *np = netdev_priv(dev); 6552 6553 dev_err(np->device, "%s: Transmit timed out, resetting\n", 6554 dev->name); 6555 6556 schedule_work(&np->reset_task); 6557 } 6558 6559 static void niu_set_txd(struct tx_ring_info *rp, int index, 6560 u64 mapping, u64 len, u64 mark, 6561 u64 n_frags) 6562 { 6563 __le64 *desc = &rp->descr[index]; 6564 6565 *desc = cpu_to_le64(mark | 6566 (n_frags << TX_DESC_NUM_PTR_SHIFT) | 6567 (len << TX_DESC_TR_LEN_SHIFT) | 6568 (mapping & TX_DESC_SAD)); 6569 } 6570 6571 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr, 6572 u64 pad_bytes, u64 len) 6573 { 6574 u16 eth_proto, eth_proto_inner; 6575 u64 csum_bits, l3off, ihl, ret; 6576 u8 ip_proto; 6577 int ipv6; 6578 6579 eth_proto = be16_to_cpu(ehdr->h_proto); 6580 eth_proto_inner = eth_proto; 6581 if (eth_proto == ETH_P_8021Q) { 6582 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr; 6583 __be16 val = vp->h_vlan_encapsulated_proto; 6584 6585 eth_proto_inner = be16_to_cpu(val); 6586 } 6587 6588 ipv6 = ihl = 0; 6589 switch (skb->protocol) { 6590 case cpu_to_be16(ETH_P_IP): 6591 ip_proto = ip_hdr(skb)->protocol; 6592 ihl = ip_hdr(skb)->ihl; 6593 break; 6594 case cpu_to_be16(ETH_P_IPV6): 6595 ip_proto = ipv6_hdr(skb)->nexthdr; 6596 ihl = (40 >> 2); 6597 ipv6 = 1; 6598 break; 6599 default: 6600 ip_proto = ihl = 0; 6601 break; 6602 } 6603 6604 csum_bits = TXHDR_CSUM_NONE; 6605 if (skb->ip_summed == CHECKSUM_PARTIAL) { 6606 u64 start, stuff; 6607 6608 csum_bits = (ip_proto == IPPROTO_TCP ? 6609 TXHDR_CSUM_TCP : 6610 (ip_proto == IPPROTO_UDP ? 6611 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP)); 6612 6613 start = skb_checksum_start_offset(skb) - 6614 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6615 stuff = start + skb->csum_offset; 6616 6617 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT; 6618 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT; 6619 } 6620 6621 l3off = skb_network_offset(skb) - 6622 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6623 6624 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) | 6625 (len << TXHDR_LEN_SHIFT) | 6626 ((l3off / 2) << TXHDR_L3START_SHIFT) | 6627 (ihl << TXHDR_IHL_SHIFT) | 6628 ((eth_proto_inner < 1536) ? TXHDR_LLC : 0) | 6629 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) | 6630 (ipv6 ? TXHDR_IP_VER : 0) | 6631 csum_bits); 6632 6633 return ret; 6634 } 6635 6636 static netdev_tx_t niu_start_xmit(struct sk_buff *skb, 6637 struct net_device *dev) 6638 { 6639 struct niu *np = netdev_priv(dev); 6640 unsigned long align, headroom; 6641 struct netdev_queue *txq; 6642 struct tx_ring_info *rp; 6643 struct tx_pkt_hdr *tp; 6644 unsigned int len, nfg; 6645 struct ethhdr *ehdr; 6646 int prod, i, tlen; 6647 u64 mapping, mrk; 6648 6649 i = skb_get_queue_mapping(skb); 6650 rp = &np->tx_rings[i]; 6651 txq = netdev_get_tx_queue(dev, i); 6652 6653 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { 6654 netif_tx_stop_queue(txq); 6655 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name); 6656 rp->tx_errors++; 6657 return NETDEV_TX_BUSY; 6658 } 6659 6660 if (skb->len < ETH_ZLEN) { 6661 unsigned int pad_bytes = ETH_ZLEN - skb->len; 6662 6663 if (skb_pad(skb, pad_bytes)) 6664 goto out; 6665 skb_put(skb, pad_bytes); 6666 } 6667 6668 len = sizeof(struct tx_pkt_hdr) + 15; 6669 if (skb_headroom(skb) < len) { 6670 struct sk_buff *skb_new; 6671 6672 skb_new = skb_realloc_headroom(skb, len); 6673 if (!skb_new) { 6674 rp->tx_errors++; 6675 goto out_drop; 6676 } 6677 kfree_skb(skb); 6678 skb = skb_new; 6679 } else 6680 skb_orphan(skb); 6681 6682 align = ((unsigned long) skb->data & (16 - 1)); 6683 headroom = align + sizeof(struct tx_pkt_hdr); 6684 6685 ehdr = (struct ethhdr *) skb->data; 6686 tp = (struct tx_pkt_hdr *) skb_push(skb, headroom); 6687 6688 len = skb->len - sizeof(struct tx_pkt_hdr); 6689 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len)); 6690 tp->resv = 0; 6691 6692 len = skb_headlen(skb); 6693 mapping = np->ops->map_single(np->device, skb->data, 6694 len, DMA_TO_DEVICE); 6695 6696 prod = rp->prod; 6697 6698 rp->tx_buffs[prod].skb = skb; 6699 rp->tx_buffs[prod].mapping = mapping; 6700 6701 mrk = TX_DESC_SOP; 6702 if (++rp->mark_counter == rp->mark_freq) { 6703 rp->mark_counter = 0; 6704 mrk |= TX_DESC_MARK; 6705 rp->mark_pending++; 6706 } 6707 6708 tlen = len; 6709 nfg = skb_shinfo(skb)->nr_frags; 6710 while (tlen > 0) { 6711 tlen -= MAX_TX_DESC_LEN; 6712 nfg++; 6713 } 6714 6715 while (len > 0) { 6716 unsigned int this_len = len; 6717 6718 if (this_len > MAX_TX_DESC_LEN) 6719 this_len = MAX_TX_DESC_LEN; 6720 6721 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg); 6722 mrk = nfg = 0; 6723 6724 prod = NEXT_TX(rp, prod); 6725 mapping += this_len; 6726 len -= this_len; 6727 } 6728 6729 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 6730 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 6731 6732 len = skb_frag_size(frag); 6733 mapping = np->ops->map_page(np->device, skb_frag_page(frag), 6734 frag->page_offset, len, 6735 DMA_TO_DEVICE); 6736 6737 rp->tx_buffs[prod].skb = NULL; 6738 rp->tx_buffs[prod].mapping = mapping; 6739 6740 niu_set_txd(rp, prod, mapping, len, 0, 0); 6741 6742 prod = NEXT_TX(rp, prod); 6743 } 6744 6745 if (prod < rp->prod) 6746 rp->wrap_bit ^= TX_RING_KICK_WRAP; 6747 rp->prod = prod; 6748 6749 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); 6750 6751 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { 6752 netif_tx_stop_queue(txq); 6753 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) 6754 netif_tx_wake_queue(txq); 6755 } 6756 6757 out: 6758 return NETDEV_TX_OK; 6759 6760 out_drop: 6761 rp->tx_errors++; 6762 kfree_skb(skb); 6763 goto out; 6764 } 6765 6766 static int niu_change_mtu(struct net_device *dev, int new_mtu) 6767 { 6768 struct niu *np = netdev_priv(dev); 6769 int err, orig_jumbo, new_jumbo; 6770 6771 if (new_mtu < 68 || new_mtu > NIU_MAX_MTU) 6772 return -EINVAL; 6773 6774 orig_jumbo = (dev->mtu > ETH_DATA_LEN); 6775 new_jumbo = (new_mtu > ETH_DATA_LEN); 6776 6777 dev->mtu = new_mtu; 6778 6779 if (!netif_running(dev) || 6780 (orig_jumbo == new_jumbo)) 6781 return 0; 6782 6783 niu_full_shutdown(np, dev); 6784 6785 niu_free_channels(np); 6786 6787 niu_enable_napi(np); 6788 6789 err = niu_alloc_channels(np); 6790 if (err) 6791 return err; 6792 6793 spin_lock_irq(&np->lock); 6794 6795 err = niu_init_hw(np); 6796 if (!err) { 6797 init_timer(&np->timer); 6798 np->timer.expires = jiffies + HZ; 6799 np->timer.data = (unsigned long) np; 6800 np->timer.function = niu_timer; 6801 6802 err = niu_enable_interrupts(np, 1); 6803 if (err) 6804 niu_stop_hw(np); 6805 } 6806 6807 spin_unlock_irq(&np->lock); 6808 6809 if (!err) { 6810 netif_tx_start_all_queues(dev); 6811 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6812 netif_carrier_on(dev); 6813 6814 add_timer(&np->timer); 6815 } 6816 6817 return err; 6818 } 6819 6820 static void niu_get_drvinfo(struct net_device *dev, 6821 struct ethtool_drvinfo *info) 6822 { 6823 struct niu *np = netdev_priv(dev); 6824 struct niu_vpd *vpd = &np->vpd; 6825 6826 strcpy(info->driver, DRV_MODULE_NAME); 6827 strcpy(info->version, DRV_MODULE_VERSION); 6828 sprintf(info->fw_version, "%d.%d", 6829 vpd->fcode_major, vpd->fcode_minor); 6830 if (np->parent->plat_type != PLAT_TYPE_NIU) 6831 strcpy(info->bus_info, pci_name(np->pdev)); 6832 } 6833 6834 static int niu_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6835 { 6836 struct niu *np = netdev_priv(dev); 6837 struct niu_link_config *lp; 6838 6839 lp = &np->link_config; 6840 6841 memset(cmd, 0, sizeof(*cmd)); 6842 cmd->phy_address = np->phy_addr; 6843 cmd->supported = lp->supported; 6844 cmd->advertising = lp->active_advertising; 6845 cmd->autoneg = lp->active_autoneg; 6846 ethtool_cmd_speed_set(cmd, lp->active_speed); 6847 cmd->duplex = lp->active_duplex; 6848 cmd->port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP; 6849 cmd->transceiver = (np->flags & NIU_FLAGS_XCVR_SERDES) ? 6850 XCVR_EXTERNAL : XCVR_INTERNAL; 6851 6852 return 0; 6853 } 6854 6855 static int niu_set_settings(struct net_device *dev, struct ethtool_cmd *cmd) 6856 { 6857 struct niu *np = netdev_priv(dev); 6858 struct niu_link_config *lp = &np->link_config; 6859 6860 lp->advertising = cmd->advertising; 6861 lp->speed = ethtool_cmd_speed(cmd); 6862 lp->duplex = cmd->duplex; 6863 lp->autoneg = cmd->autoneg; 6864 return niu_init_link(np); 6865 } 6866 6867 static u32 niu_get_msglevel(struct net_device *dev) 6868 { 6869 struct niu *np = netdev_priv(dev); 6870 return np->msg_enable; 6871 } 6872 6873 static void niu_set_msglevel(struct net_device *dev, u32 value) 6874 { 6875 struct niu *np = netdev_priv(dev); 6876 np->msg_enable = value; 6877 } 6878 6879 static int niu_nway_reset(struct net_device *dev) 6880 { 6881 struct niu *np = netdev_priv(dev); 6882 6883 if (np->link_config.autoneg) 6884 return niu_init_link(np); 6885 6886 return 0; 6887 } 6888 6889 static int niu_get_eeprom_len(struct net_device *dev) 6890 { 6891 struct niu *np = netdev_priv(dev); 6892 6893 return np->eeprom_len; 6894 } 6895 6896 static int niu_get_eeprom(struct net_device *dev, 6897 struct ethtool_eeprom *eeprom, u8 *data) 6898 { 6899 struct niu *np = netdev_priv(dev); 6900 u32 offset, len, val; 6901 6902 offset = eeprom->offset; 6903 len = eeprom->len; 6904 6905 if (offset + len < offset) 6906 return -EINVAL; 6907 if (offset >= np->eeprom_len) 6908 return -EINVAL; 6909 if (offset + len > np->eeprom_len) 6910 len = eeprom->len = np->eeprom_len - offset; 6911 6912 if (offset & 3) { 6913 u32 b_offset, b_count; 6914 6915 b_offset = offset & 3; 6916 b_count = 4 - b_offset; 6917 if (b_count > len) 6918 b_count = len; 6919 6920 val = nr64(ESPC_NCR((offset - b_offset) / 4)); 6921 memcpy(data, ((char *)&val) + b_offset, b_count); 6922 data += b_count; 6923 len -= b_count; 6924 offset += b_count; 6925 } 6926 while (len >= 4) { 6927 val = nr64(ESPC_NCR(offset / 4)); 6928 memcpy(data, &val, 4); 6929 data += 4; 6930 len -= 4; 6931 offset += 4; 6932 } 6933 if (len) { 6934 val = nr64(ESPC_NCR(offset / 4)); 6935 memcpy(data, &val, len); 6936 } 6937 return 0; 6938 } 6939 6940 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid) 6941 { 6942 switch (flow_type) { 6943 case TCP_V4_FLOW: 6944 case TCP_V6_FLOW: 6945 *pid = IPPROTO_TCP; 6946 break; 6947 case UDP_V4_FLOW: 6948 case UDP_V6_FLOW: 6949 *pid = IPPROTO_UDP; 6950 break; 6951 case SCTP_V4_FLOW: 6952 case SCTP_V6_FLOW: 6953 *pid = IPPROTO_SCTP; 6954 break; 6955 case AH_V4_FLOW: 6956 case AH_V6_FLOW: 6957 *pid = IPPROTO_AH; 6958 break; 6959 case ESP_V4_FLOW: 6960 case ESP_V6_FLOW: 6961 *pid = IPPROTO_ESP; 6962 break; 6963 default: 6964 *pid = 0; 6965 break; 6966 } 6967 } 6968 6969 static int niu_class_to_ethflow(u64 class, int *flow_type) 6970 { 6971 switch (class) { 6972 case CLASS_CODE_TCP_IPV4: 6973 *flow_type = TCP_V4_FLOW; 6974 break; 6975 case CLASS_CODE_UDP_IPV4: 6976 *flow_type = UDP_V4_FLOW; 6977 break; 6978 case CLASS_CODE_AH_ESP_IPV4: 6979 *flow_type = AH_V4_FLOW; 6980 break; 6981 case CLASS_CODE_SCTP_IPV4: 6982 *flow_type = SCTP_V4_FLOW; 6983 break; 6984 case CLASS_CODE_TCP_IPV6: 6985 *flow_type = TCP_V6_FLOW; 6986 break; 6987 case CLASS_CODE_UDP_IPV6: 6988 *flow_type = UDP_V6_FLOW; 6989 break; 6990 case CLASS_CODE_AH_ESP_IPV6: 6991 *flow_type = AH_V6_FLOW; 6992 break; 6993 case CLASS_CODE_SCTP_IPV6: 6994 *flow_type = SCTP_V6_FLOW; 6995 break; 6996 case CLASS_CODE_USER_PROG1: 6997 case CLASS_CODE_USER_PROG2: 6998 case CLASS_CODE_USER_PROG3: 6999 case CLASS_CODE_USER_PROG4: 7000 *flow_type = IP_USER_FLOW; 7001 break; 7002 default: 7003 return 0; 7004 } 7005 7006 return 1; 7007 } 7008 7009 static int niu_ethflow_to_class(int flow_type, u64 *class) 7010 { 7011 switch (flow_type) { 7012 case TCP_V4_FLOW: 7013 *class = CLASS_CODE_TCP_IPV4; 7014 break; 7015 case UDP_V4_FLOW: 7016 *class = CLASS_CODE_UDP_IPV4; 7017 break; 7018 case AH_ESP_V4_FLOW: 7019 case AH_V4_FLOW: 7020 case ESP_V4_FLOW: 7021 *class = CLASS_CODE_AH_ESP_IPV4; 7022 break; 7023 case SCTP_V4_FLOW: 7024 *class = CLASS_CODE_SCTP_IPV4; 7025 break; 7026 case TCP_V6_FLOW: 7027 *class = CLASS_CODE_TCP_IPV6; 7028 break; 7029 case UDP_V6_FLOW: 7030 *class = CLASS_CODE_UDP_IPV6; 7031 break; 7032 case AH_ESP_V6_FLOW: 7033 case AH_V6_FLOW: 7034 case ESP_V6_FLOW: 7035 *class = CLASS_CODE_AH_ESP_IPV6; 7036 break; 7037 case SCTP_V6_FLOW: 7038 *class = CLASS_CODE_SCTP_IPV6; 7039 break; 7040 default: 7041 return 0; 7042 } 7043 7044 return 1; 7045 } 7046 7047 static u64 niu_flowkey_to_ethflow(u64 flow_key) 7048 { 7049 u64 ethflow = 0; 7050 7051 if (flow_key & FLOW_KEY_L2DA) 7052 ethflow |= RXH_L2DA; 7053 if (flow_key & FLOW_KEY_VLAN) 7054 ethflow |= RXH_VLAN; 7055 if (flow_key & FLOW_KEY_IPSA) 7056 ethflow |= RXH_IP_SRC; 7057 if (flow_key & FLOW_KEY_IPDA) 7058 ethflow |= RXH_IP_DST; 7059 if (flow_key & FLOW_KEY_PROTO) 7060 ethflow |= RXH_L3_PROTO; 7061 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT)) 7062 ethflow |= RXH_L4_B_0_1; 7063 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT)) 7064 ethflow |= RXH_L4_B_2_3; 7065 7066 return ethflow; 7067 7068 } 7069 7070 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key) 7071 { 7072 u64 key = 0; 7073 7074 if (ethflow & RXH_L2DA) 7075 key |= FLOW_KEY_L2DA; 7076 if (ethflow & RXH_VLAN) 7077 key |= FLOW_KEY_VLAN; 7078 if (ethflow & RXH_IP_SRC) 7079 key |= FLOW_KEY_IPSA; 7080 if (ethflow & RXH_IP_DST) 7081 key |= FLOW_KEY_IPDA; 7082 if (ethflow & RXH_L3_PROTO) 7083 key |= FLOW_KEY_PROTO; 7084 if (ethflow & RXH_L4_B_0_1) 7085 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT); 7086 if (ethflow & RXH_L4_B_2_3) 7087 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT); 7088 7089 *flow_key = key; 7090 7091 return 1; 7092 7093 } 7094 7095 static int niu_get_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) 7096 { 7097 u64 class; 7098 7099 nfc->data = 0; 7100 7101 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7102 return -EINVAL; 7103 7104 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7105 TCAM_KEY_DISC) 7106 nfc->data = RXH_DISCARD; 7107 else 7108 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class - 7109 CLASS_CODE_USER_PROG1]); 7110 return 0; 7111 } 7112 7113 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp, 7114 struct ethtool_rx_flow_spec *fsp) 7115 { 7116 u32 tmp; 7117 u16 prt; 7118 7119 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7120 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7121 7122 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7123 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7124 7125 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7126 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7127 7128 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7129 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7130 7131 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >> 7132 TCAM_V4KEY2_TOS_SHIFT; 7133 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >> 7134 TCAM_V4KEY2_TOS_SHIFT; 7135 7136 switch (fsp->flow_type) { 7137 case TCP_V4_FLOW: 7138 case UDP_V4_FLOW: 7139 case SCTP_V4_FLOW: 7140 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7141 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7142 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7143 7144 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7145 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7146 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7147 7148 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7149 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7150 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7151 7152 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7153 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7154 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7155 break; 7156 case AH_V4_FLOW: 7157 case ESP_V4_FLOW: 7158 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7159 TCAM_V4KEY2_PORT_SPI_SHIFT; 7160 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7161 7162 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7163 TCAM_V4KEY2_PORT_SPI_SHIFT; 7164 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7165 break; 7166 case IP_USER_FLOW: 7167 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7168 TCAM_V4KEY2_PORT_SPI_SHIFT; 7169 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7170 7171 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7172 TCAM_V4KEY2_PORT_SPI_SHIFT; 7173 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7174 7175 fsp->h_u.usr_ip4_spec.proto = 7176 (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7177 TCAM_V4KEY2_PROTO_SHIFT; 7178 fsp->m_u.usr_ip4_spec.proto = 7179 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >> 7180 TCAM_V4KEY2_PROTO_SHIFT; 7181 7182 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 7183 break; 7184 default: 7185 break; 7186 } 7187 } 7188 7189 static int niu_get_ethtool_tcam_entry(struct niu *np, 7190 struct ethtool_rxnfc *nfc) 7191 { 7192 struct niu_parent *parent = np->parent; 7193 struct niu_tcam_entry *tp; 7194 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7195 u16 idx; 7196 u64 class; 7197 int ret = 0; 7198 7199 idx = tcam_get_index(np, (u16)nfc->fs.location); 7200 7201 tp = &parent->tcam[idx]; 7202 if (!tp->valid) { 7203 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n", 7204 parent->index, (u16)nfc->fs.location, idx); 7205 return -EINVAL; 7206 } 7207 7208 /* fill the flow spec entry */ 7209 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7210 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7211 ret = niu_class_to_ethflow(class, &fsp->flow_type); 7212 7213 if (ret < 0) { 7214 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n", 7215 parent->index); 7216 ret = -EINVAL; 7217 goto out; 7218 } 7219 7220 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) { 7221 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7222 TCAM_V4KEY2_PROTO_SHIFT; 7223 if (proto == IPPROTO_ESP) { 7224 if (fsp->flow_type == AH_V4_FLOW) 7225 fsp->flow_type = ESP_V4_FLOW; 7226 else 7227 fsp->flow_type = ESP_V6_FLOW; 7228 } 7229 } 7230 7231 switch (fsp->flow_type) { 7232 case TCP_V4_FLOW: 7233 case UDP_V4_FLOW: 7234 case SCTP_V4_FLOW: 7235 case AH_V4_FLOW: 7236 case ESP_V4_FLOW: 7237 niu_get_ip4fs_from_tcam_key(tp, fsp); 7238 break; 7239 case TCP_V6_FLOW: 7240 case UDP_V6_FLOW: 7241 case SCTP_V6_FLOW: 7242 case AH_V6_FLOW: 7243 case ESP_V6_FLOW: 7244 /* Not yet implemented */ 7245 ret = -EINVAL; 7246 break; 7247 case IP_USER_FLOW: 7248 niu_get_ip4fs_from_tcam_key(tp, fsp); 7249 break; 7250 default: 7251 ret = -EINVAL; 7252 break; 7253 } 7254 7255 if (ret < 0) 7256 goto out; 7257 7258 if (tp->assoc_data & TCAM_ASSOCDATA_DISC) 7259 fsp->ring_cookie = RX_CLS_FLOW_DISC; 7260 else 7261 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >> 7262 TCAM_ASSOCDATA_OFFSET_SHIFT; 7263 7264 /* put the tcam size here */ 7265 nfc->data = tcam_get_size(np); 7266 out: 7267 return ret; 7268 } 7269 7270 static int niu_get_ethtool_tcam_all(struct niu *np, 7271 struct ethtool_rxnfc *nfc, 7272 u32 *rule_locs) 7273 { 7274 struct niu_parent *parent = np->parent; 7275 struct niu_tcam_entry *tp; 7276 int i, idx, cnt; 7277 unsigned long flags; 7278 int ret = 0; 7279 7280 /* put the tcam size here */ 7281 nfc->data = tcam_get_size(np); 7282 7283 niu_lock_parent(np, flags); 7284 for (cnt = 0, i = 0; i < nfc->data; i++) { 7285 idx = tcam_get_index(np, i); 7286 tp = &parent->tcam[idx]; 7287 if (!tp->valid) 7288 continue; 7289 if (cnt == nfc->rule_cnt) { 7290 ret = -EMSGSIZE; 7291 break; 7292 } 7293 rule_locs[cnt] = i; 7294 cnt++; 7295 } 7296 niu_unlock_parent(np, flags); 7297 7298 nfc->rule_cnt = cnt; 7299 7300 return ret; 7301 } 7302 7303 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 7304 u32 *rule_locs) 7305 { 7306 struct niu *np = netdev_priv(dev); 7307 int ret = 0; 7308 7309 switch (cmd->cmd) { 7310 case ETHTOOL_GRXFH: 7311 ret = niu_get_hash_opts(np, cmd); 7312 break; 7313 case ETHTOOL_GRXRINGS: 7314 cmd->data = np->num_rx_rings; 7315 break; 7316 case ETHTOOL_GRXCLSRLCNT: 7317 cmd->rule_cnt = tcam_get_valid_entry_cnt(np); 7318 break; 7319 case ETHTOOL_GRXCLSRULE: 7320 ret = niu_get_ethtool_tcam_entry(np, cmd); 7321 break; 7322 case ETHTOOL_GRXCLSRLALL: 7323 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs); 7324 break; 7325 default: 7326 ret = -EINVAL; 7327 break; 7328 } 7329 7330 return ret; 7331 } 7332 7333 static int niu_set_hash_opts(struct niu *np, struct ethtool_rxnfc *nfc) 7334 { 7335 u64 class; 7336 u64 flow_key = 0; 7337 unsigned long flags; 7338 7339 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7340 return -EINVAL; 7341 7342 if (class < CLASS_CODE_USER_PROG1 || 7343 class > CLASS_CODE_SCTP_IPV6) 7344 return -EINVAL; 7345 7346 if (nfc->data & RXH_DISCARD) { 7347 niu_lock_parent(np, flags); 7348 flow_key = np->parent->tcam_key[class - 7349 CLASS_CODE_USER_PROG1]; 7350 flow_key |= TCAM_KEY_DISC; 7351 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7352 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7353 niu_unlock_parent(np, flags); 7354 return 0; 7355 } else { 7356 /* Discard was set before, but is not set now */ 7357 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7358 TCAM_KEY_DISC) { 7359 niu_lock_parent(np, flags); 7360 flow_key = np->parent->tcam_key[class - 7361 CLASS_CODE_USER_PROG1]; 7362 flow_key &= ~TCAM_KEY_DISC; 7363 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), 7364 flow_key); 7365 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = 7366 flow_key; 7367 niu_unlock_parent(np, flags); 7368 } 7369 } 7370 7371 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key)) 7372 return -EINVAL; 7373 7374 niu_lock_parent(np, flags); 7375 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7376 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7377 niu_unlock_parent(np, flags); 7378 7379 return 0; 7380 } 7381 7382 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp, 7383 struct niu_tcam_entry *tp, 7384 int l2_rdc_tab, u64 class) 7385 { 7386 u8 pid = 0; 7387 u32 sip, dip, sipm, dipm, spi, spim; 7388 u16 sport, dport, spm, dpm; 7389 7390 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src); 7391 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src); 7392 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst); 7393 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst); 7394 7395 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT; 7396 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE; 7397 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT; 7398 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM; 7399 7400 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT; 7401 tp->key[3] |= dip; 7402 7403 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT; 7404 tp->key_mask[3] |= dipm; 7405 7406 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos << 7407 TCAM_V4KEY2_TOS_SHIFT); 7408 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos << 7409 TCAM_V4KEY2_TOS_SHIFT); 7410 switch (fsp->flow_type) { 7411 case TCP_V4_FLOW: 7412 case UDP_V4_FLOW: 7413 case SCTP_V4_FLOW: 7414 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc); 7415 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc); 7416 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst); 7417 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst); 7418 7419 tp->key[2] |= (((u64)sport << 16) | dport); 7420 tp->key_mask[2] |= (((u64)spm << 16) | dpm); 7421 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7422 break; 7423 case AH_V4_FLOW: 7424 case ESP_V4_FLOW: 7425 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi); 7426 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi); 7427 7428 tp->key[2] |= spi; 7429 tp->key_mask[2] |= spim; 7430 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7431 break; 7432 case IP_USER_FLOW: 7433 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes); 7434 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes); 7435 7436 tp->key[2] |= spi; 7437 tp->key_mask[2] |= spim; 7438 pid = fsp->h_u.usr_ip4_spec.proto; 7439 break; 7440 default: 7441 break; 7442 } 7443 7444 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT); 7445 if (pid) { 7446 tp->key_mask[2] |= TCAM_V4KEY2_PROTO; 7447 } 7448 } 7449 7450 static int niu_add_ethtool_tcam_entry(struct niu *np, 7451 struct ethtool_rxnfc *nfc) 7452 { 7453 struct niu_parent *parent = np->parent; 7454 struct niu_tcam_entry *tp; 7455 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7456 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port]; 7457 int l2_rdc_table = rdc_table->first_table_num; 7458 u16 idx; 7459 u64 class; 7460 unsigned long flags; 7461 int err, ret; 7462 7463 ret = 0; 7464 7465 idx = nfc->fs.location; 7466 if (idx >= tcam_get_size(np)) 7467 return -EINVAL; 7468 7469 if (fsp->flow_type == IP_USER_FLOW) { 7470 int i; 7471 int add_usr_cls = 0; 7472 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec; 7473 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec; 7474 7475 if (uspec->ip_ver != ETH_RX_NFC_IP4) 7476 return -EINVAL; 7477 7478 niu_lock_parent(np, flags); 7479 7480 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7481 if (parent->l3_cls[i]) { 7482 if (uspec->proto == parent->l3_cls_pid[i]) { 7483 class = parent->l3_cls[i]; 7484 parent->l3_cls_refcnt[i]++; 7485 add_usr_cls = 1; 7486 break; 7487 } 7488 } else { 7489 /* Program new user IP class */ 7490 switch (i) { 7491 case 0: 7492 class = CLASS_CODE_USER_PROG1; 7493 break; 7494 case 1: 7495 class = CLASS_CODE_USER_PROG2; 7496 break; 7497 case 2: 7498 class = CLASS_CODE_USER_PROG3; 7499 break; 7500 case 3: 7501 class = CLASS_CODE_USER_PROG4; 7502 break; 7503 default: 7504 break; 7505 } 7506 ret = tcam_user_ip_class_set(np, class, 0, 7507 uspec->proto, 7508 uspec->tos, 7509 umask->tos); 7510 if (ret) 7511 goto out; 7512 7513 ret = tcam_user_ip_class_enable(np, class, 1); 7514 if (ret) 7515 goto out; 7516 parent->l3_cls[i] = class; 7517 parent->l3_cls_pid[i] = uspec->proto; 7518 parent->l3_cls_refcnt[i]++; 7519 add_usr_cls = 1; 7520 break; 7521 } 7522 } 7523 if (!add_usr_cls) { 7524 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n", 7525 parent->index, __func__, uspec->proto); 7526 ret = -EINVAL; 7527 goto out; 7528 } 7529 niu_unlock_parent(np, flags); 7530 } else { 7531 if (!niu_ethflow_to_class(fsp->flow_type, &class)) { 7532 return -EINVAL; 7533 } 7534 } 7535 7536 niu_lock_parent(np, flags); 7537 7538 idx = tcam_get_index(np, idx); 7539 tp = &parent->tcam[idx]; 7540 7541 memset(tp, 0, sizeof(*tp)); 7542 7543 /* fill in the tcam key and mask */ 7544 switch (fsp->flow_type) { 7545 case TCP_V4_FLOW: 7546 case UDP_V4_FLOW: 7547 case SCTP_V4_FLOW: 7548 case AH_V4_FLOW: 7549 case ESP_V4_FLOW: 7550 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7551 break; 7552 case TCP_V6_FLOW: 7553 case UDP_V6_FLOW: 7554 case SCTP_V6_FLOW: 7555 case AH_V6_FLOW: 7556 case ESP_V6_FLOW: 7557 /* Not yet implemented */ 7558 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n", 7559 parent->index, __func__, fsp->flow_type); 7560 ret = -EINVAL; 7561 goto out; 7562 case IP_USER_FLOW: 7563 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7564 break; 7565 default: 7566 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n", 7567 parent->index, __func__, fsp->flow_type); 7568 ret = -EINVAL; 7569 goto out; 7570 } 7571 7572 /* fill in the assoc data */ 7573 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 7574 tp->assoc_data = TCAM_ASSOCDATA_DISC; 7575 } else { 7576 if (fsp->ring_cookie >= np->num_rx_rings) { 7577 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n", 7578 parent->index, __func__, 7579 (long long)fsp->ring_cookie); 7580 ret = -EINVAL; 7581 goto out; 7582 } 7583 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 7584 (fsp->ring_cookie << 7585 TCAM_ASSOCDATA_OFFSET_SHIFT)); 7586 } 7587 7588 err = tcam_write(np, idx, tp->key, tp->key_mask); 7589 if (err) { 7590 ret = -EINVAL; 7591 goto out; 7592 } 7593 err = tcam_assoc_write(np, idx, tp->assoc_data); 7594 if (err) { 7595 ret = -EINVAL; 7596 goto out; 7597 } 7598 7599 /* validate the entry */ 7600 tp->valid = 1; 7601 np->clas.tcam_valid_entries++; 7602 out: 7603 niu_unlock_parent(np, flags); 7604 7605 return ret; 7606 } 7607 7608 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc) 7609 { 7610 struct niu_parent *parent = np->parent; 7611 struct niu_tcam_entry *tp; 7612 u16 idx; 7613 unsigned long flags; 7614 u64 class; 7615 int ret = 0; 7616 7617 if (loc >= tcam_get_size(np)) 7618 return -EINVAL; 7619 7620 niu_lock_parent(np, flags); 7621 7622 idx = tcam_get_index(np, loc); 7623 tp = &parent->tcam[idx]; 7624 7625 /* if the entry is of a user defined class, then update*/ 7626 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7627 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7628 7629 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) { 7630 int i; 7631 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7632 if (parent->l3_cls[i] == class) { 7633 parent->l3_cls_refcnt[i]--; 7634 if (!parent->l3_cls_refcnt[i]) { 7635 /* disable class */ 7636 ret = tcam_user_ip_class_enable(np, 7637 class, 7638 0); 7639 if (ret) 7640 goto out; 7641 parent->l3_cls[i] = 0; 7642 parent->l3_cls_pid[i] = 0; 7643 } 7644 break; 7645 } 7646 } 7647 if (i == NIU_L3_PROG_CLS) { 7648 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n", 7649 parent->index, __func__, 7650 (unsigned long long)class); 7651 ret = -EINVAL; 7652 goto out; 7653 } 7654 } 7655 7656 ret = tcam_flush(np, idx); 7657 if (ret) 7658 goto out; 7659 7660 /* invalidate the entry */ 7661 tp->valid = 0; 7662 np->clas.tcam_valid_entries--; 7663 out: 7664 niu_unlock_parent(np, flags); 7665 7666 return ret; 7667 } 7668 7669 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 7670 { 7671 struct niu *np = netdev_priv(dev); 7672 int ret = 0; 7673 7674 switch (cmd->cmd) { 7675 case ETHTOOL_SRXFH: 7676 ret = niu_set_hash_opts(np, cmd); 7677 break; 7678 case ETHTOOL_SRXCLSRLINS: 7679 ret = niu_add_ethtool_tcam_entry(np, cmd); 7680 break; 7681 case ETHTOOL_SRXCLSRLDEL: 7682 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location); 7683 break; 7684 default: 7685 ret = -EINVAL; 7686 break; 7687 } 7688 7689 return ret; 7690 } 7691 7692 static const struct { 7693 const char string[ETH_GSTRING_LEN]; 7694 } niu_xmac_stat_keys[] = { 7695 { "tx_frames" }, 7696 { "tx_bytes" }, 7697 { "tx_fifo_errors" }, 7698 { "tx_overflow_errors" }, 7699 { "tx_max_pkt_size_errors" }, 7700 { "tx_underflow_errors" }, 7701 { "rx_local_faults" }, 7702 { "rx_remote_faults" }, 7703 { "rx_link_faults" }, 7704 { "rx_align_errors" }, 7705 { "rx_frags" }, 7706 { "rx_mcasts" }, 7707 { "rx_bcasts" }, 7708 { "rx_hist_cnt1" }, 7709 { "rx_hist_cnt2" }, 7710 { "rx_hist_cnt3" }, 7711 { "rx_hist_cnt4" }, 7712 { "rx_hist_cnt5" }, 7713 { "rx_hist_cnt6" }, 7714 { "rx_hist_cnt7" }, 7715 { "rx_octets" }, 7716 { "rx_code_violations" }, 7717 { "rx_len_errors" }, 7718 { "rx_crc_errors" }, 7719 { "rx_underflows" }, 7720 { "rx_overflows" }, 7721 { "pause_off_state" }, 7722 { "pause_on_state" }, 7723 { "pause_received" }, 7724 }; 7725 7726 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys) 7727 7728 static const struct { 7729 const char string[ETH_GSTRING_LEN]; 7730 } niu_bmac_stat_keys[] = { 7731 { "tx_underflow_errors" }, 7732 { "tx_max_pkt_size_errors" }, 7733 { "tx_bytes" }, 7734 { "tx_frames" }, 7735 { "rx_overflows" }, 7736 { "rx_frames" }, 7737 { "rx_align_errors" }, 7738 { "rx_crc_errors" }, 7739 { "rx_len_errors" }, 7740 { "pause_off_state" }, 7741 { "pause_on_state" }, 7742 { "pause_received" }, 7743 }; 7744 7745 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys) 7746 7747 static const struct { 7748 const char string[ETH_GSTRING_LEN]; 7749 } niu_rxchan_stat_keys[] = { 7750 { "rx_channel" }, 7751 { "rx_packets" }, 7752 { "rx_bytes" }, 7753 { "rx_dropped" }, 7754 { "rx_errors" }, 7755 }; 7756 7757 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys) 7758 7759 static const struct { 7760 const char string[ETH_GSTRING_LEN]; 7761 } niu_txchan_stat_keys[] = { 7762 { "tx_channel" }, 7763 { "tx_packets" }, 7764 { "tx_bytes" }, 7765 { "tx_errors" }, 7766 }; 7767 7768 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys) 7769 7770 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data) 7771 { 7772 struct niu *np = netdev_priv(dev); 7773 int i; 7774 7775 if (stringset != ETH_SS_STATS) 7776 return; 7777 7778 if (np->flags & NIU_FLAGS_XMAC) { 7779 memcpy(data, niu_xmac_stat_keys, 7780 sizeof(niu_xmac_stat_keys)); 7781 data += sizeof(niu_xmac_stat_keys); 7782 } else { 7783 memcpy(data, niu_bmac_stat_keys, 7784 sizeof(niu_bmac_stat_keys)); 7785 data += sizeof(niu_bmac_stat_keys); 7786 } 7787 for (i = 0; i < np->num_rx_rings; i++) { 7788 memcpy(data, niu_rxchan_stat_keys, 7789 sizeof(niu_rxchan_stat_keys)); 7790 data += sizeof(niu_rxchan_stat_keys); 7791 } 7792 for (i = 0; i < np->num_tx_rings; i++) { 7793 memcpy(data, niu_txchan_stat_keys, 7794 sizeof(niu_txchan_stat_keys)); 7795 data += sizeof(niu_txchan_stat_keys); 7796 } 7797 } 7798 7799 static int niu_get_sset_count(struct net_device *dev, int stringset) 7800 { 7801 struct niu *np = netdev_priv(dev); 7802 7803 if (stringset != ETH_SS_STATS) 7804 return -EINVAL; 7805 7806 return (np->flags & NIU_FLAGS_XMAC ? 7807 NUM_XMAC_STAT_KEYS : 7808 NUM_BMAC_STAT_KEYS) + 7809 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) + 7810 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS); 7811 } 7812 7813 static void niu_get_ethtool_stats(struct net_device *dev, 7814 struct ethtool_stats *stats, u64 *data) 7815 { 7816 struct niu *np = netdev_priv(dev); 7817 int i; 7818 7819 niu_sync_mac_stats(np); 7820 if (np->flags & NIU_FLAGS_XMAC) { 7821 memcpy(data, &np->mac_stats.xmac, 7822 sizeof(struct niu_xmac_stats)); 7823 data += (sizeof(struct niu_xmac_stats) / sizeof(u64)); 7824 } else { 7825 memcpy(data, &np->mac_stats.bmac, 7826 sizeof(struct niu_bmac_stats)); 7827 data += (sizeof(struct niu_bmac_stats) / sizeof(u64)); 7828 } 7829 for (i = 0; i < np->num_rx_rings; i++) { 7830 struct rx_ring_info *rp = &np->rx_rings[i]; 7831 7832 niu_sync_rx_discard_stats(np, rp, 0); 7833 7834 data[0] = rp->rx_channel; 7835 data[1] = rp->rx_packets; 7836 data[2] = rp->rx_bytes; 7837 data[3] = rp->rx_dropped; 7838 data[4] = rp->rx_errors; 7839 data += 5; 7840 } 7841 for (i = 0; i < np->num_tx_rings; i++) { 7842 struct tx_ring_info *rp = &np->tx_rings[i]; 7843 7844 data[0] = rp->tx_channel; 7845 data[1] = rp->tx_packets; 7846 data[2] = rp->tx_bytes; 7847 data[3] = rp->tx_errors; 7848 data += 4; 7849 } 7850 } 7851 7852 static u64 niu_led_state_save(struct niu *np) 7853 { 7854 if (np->flags & NIU_FLAGS_XMAC) 7855 return nr64_mac(XMAC_CONFIG); 7856 else 7857 return nr64_mac(BMAC_XIF_CONFIG); 7858 } 7859 7860 static void niu_led_state_restore(struct niu *np, u64 val) 7861 { 7862 if (np->flags & NIU_FLAGS_XMAC) 7863 nw64_mac(XMAC_CONFIG, val); 7864 else 7865 nw64_mac(BMAC_XIF_CONFIG, val); 7866 } 7867 7868 static void niu_force_led(struct niu *np, int on) 7869 { 7870 u64 val, reg, bit; 7871 7872 if (np->flags & NIU_FLAGS_XMAC) { 7873 reg = XMAC_CONFIG; 7874 bit = XMAC_CONFIG_FORCE_LED_ON; 7875 } else { 7876 reg = BMAC_XIF_CONFIG; 7877 bit = BMAC_XIF_CONFIG_LINK_LED; 7878 } 7879 7880 val = nr64_mac(reg); 7881 if (on) 7882 val |= bit; 7883 else 7884 val &= ~bit; 7885 nw64_mac(reg, val); 7886 } 7887 7888 static int niu_set_phys_id(struct net_device *dev, 7889 enum ethtool_phys_id_state state) 7890 7891 { 7892 struct niu *np = netdev_priv(dev); 7893 7894 if (!netif_running(dev)) 7895 return -EAGAIN; 7896 7897 switch (state) { 7898 case ETHTOOL_ID_ACTIVE: 7899 np->orig_led_state = niu_led_state_save(np); 7900 return 1; /* cycle on/off once per second */ 7901 7902 case ETHTOOL_ID_ON: 7903 niu_force_led(np, 1); 7904 break; 7905 7906 case ETHTOOL_ID_OFF: 7907 niu_force_led(np, 0); 7908 break; 7909 7910 case ETHTOOL_ID_INACTIVE: 7911 niu_led_state_restore(np, np->orig_led_state); 7912 } 7913 7914 return 0; 7915 } 7916 7917 static const struct ethtool_ops niu_ethtool_ops = { 7918 .get_drvinfo = niu_get_drvinfo, 7919 .get_link = ethtool_op_get_link, 7920 .get_msglevel = niu_get_msglevel, 7921 .set_msglevel = niu_set_msglevel, 7922 .nway_reset = niu_nway_reset, 7923 .get_eeprom_len = niu_get_eeprom_len, 7924 .get_eeprom = niu_get_eeprom, 7925 .get_settings = niu_get_settings, 7926 .set_settings = niu_set_settings, 7927 .get_strings = niu_get_strings, 7928 .get_sset_count = niu_get_sset_count, 7929 .get_ethtool_stats = niu_get_ethtool_stats, 7930 .set_phys_id = niu_set_phys_id, 7931 .get_rxnfc = niu_get_nfc, 7932 .set_rxnfc = niu_set_nfc, 7933 }; 7934 7935 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, 7936 int ldg, int ldn) 7937 { 7938 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) 7939 return -EINVAL; 7940 if (ldn < 0 || ldn > LDN_MAX) 7941 return -EINVAL; 7942 7943 parent->ldg_map[ldn] = ldg; 7944 7945 if (np->parent->plat_type == PLAT_TYPE_NIU) { 7946 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by 7947 * the firmware, and we're not supposed to change them. 7948 * Validate the mapping, because if it's wrong we probably 7949 * won't get any interrupts and that's painful to debug. 7950 */ 7951 if (nr64(LDG_NUM(ldn)) != ldg) { 7952 dev_err(np->device, "Port %u, mis-matched LDG assignment for ldn %d, should be %d is %llu\n", 7953 np->port, ldn, ldg, 7954 (unsigned long long) nr64(LDG_NUM(ldn))); 7955 return -EINVAL; 7956 } 7957 } else 7958 nw64(LDG_NUM(ldn), ldg); 7959 7960 return 0; 7961 } 7962 7963 static int niu_set_ldg_timer_res(struct niu *np, int res) 7964 { 7965 if (res < 0 || res > LDG_TIMER_RES_VAL) 7966 return -EINVAL; 7967 7968 7969 nw64(LDG_TIMER_RES, res); 7970 7971 return 0; 7972 } 7973 7974 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector) 7975 { 7976 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) || 7977 (func < 0 || func > 3) || 7978 (vector < 0 || vector > 0x1f)) 7979 return -EINVAL; 7980 7981 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); 7982 7983 return 0; 7984 } 7985 7986 static int __devinit niu_pci_eeprom_read(struct niu *np, u32 addr) 7987 { 7988 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START | 7989 (addr << ESPC_PIO_STAT_ADDR_SHIFT)); 7990 int limit; 7991 7992 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT)) 7993 return -EINVAL; 7994 7995 frame = frame_base; 7996 nw64(ESPC_PIO_STAT, frame); 7997 limit = 64; 7998 do { 7999 udelay(5); 8000 frame = nr64(ESPC_PIO_STAT); 8001 if (frame & ESPC_PIO_STAT_READ_END) 8002 break; 8003 } while (limit--); 8004 if (!(frame & ESPC_PIO_STAT_READ_END)) { 8005 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 8006 (unsigned long long) frame); 8007 return -ENODEV; 8008 } 8009 8010 frame = frame_base; 8011 nw64(ESPC_PIO_STAT, frame); 8012 limit = 64; 8013 do { 8014 udelay(5); 8015 frame = nr64(ESPC_PIO_STAT); 8016 if (frame & ESPC_PIO_STAT_READ_END) 8017 break; 8018 } while (limit--); 8019 if (!(frame & ESPC_PIO_STAT_READ_END)) { 8020 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 8021 (unsigned long long) frame); 8022 return -ENODEV; 8023 } 8024 8025 frame = nr64(ESPC_PIO_STAT); 8026 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT; 8027 } 8028 8029 static int __devinit niu_pci_eeprom_read16(struct niu *np, u32 off) 8030 { 8031 int err = niu_pci_eeprom_read(np, off); 8032 u16 val; 8033 8034 if (err < 0) 8035 return err; 8036 val = (err << 8); 8037 err = niu_pci_eeprom_read(np, off + 1); 8038 if (err < 0) 8039 return err; 8040 val |= (err & 0xff); 8041 8042 return val; 8043 } 8044 8045 static int __devinit niu_pci_eeprom_read16_swp(struct niu *np, u32 off) 8046 { 8047 int err = niu_pci_eeprom_read(np, off); 8048 u16 val; 8049 8050 if (err < 0) 8051 return err; 8052 8053 val = (err & 0xff); 8054 err = niu_pci_eeprom_read(np, off + 1); 8055 if (err < 0) 8056 return err; 8057 8058 val |= (err & 0xff) << 8; 8059 8060 return val; 8061 } 8062 8063 static int __devinit niu_pci_vpd_get_propname(struct niu *np, 8064 u32 off, 8065 char *namebuf, 8066 int namebuf_len) 8067 { 8068 int i; 8069 8070 for (i = 0; i < namebuf_len; i++) { 8071 int err = niu_pci_eeprom_read(np, off + i); 8072 if (err < 0) 8073 return err; 8074 *namebuf++ = err; 8075 if (!err) 8076 break; 8077 } 8078 if (i >= namebuf_len) 8079 return -EINVAL; 8080 8081 return i + 1; 8082 } 8083 8084 static void __devinit niu_vpd_parse_version(struct niu *np) 8085 { 8086 struct niu_vpd *vpd = &np->vpd; 8087 int len = strlen(vpd->version) + 1; 8088 const char *s = vpd->version; 8089 int i; 8090 8091 for (i = 0; i < len - 5; i++) { 8092 if (!strncmp(s + i, "FCode ", 6)) 8093 break; 8094 } 8095 if (i >= len - 5) 8096 return; 8097 8098 s += i + 5; 8099 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor); 8100 8101 netif_printk(np, probe, KERN_DEBUG, np->dev, 8102 "VPD_SCAN: FCODE major(%d) minor(%d)\n", 8103 vpd->fcode_major, vpd->fcode_minor); 8104 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR || 8105 (vpd->fcode_major == NIU_VPD_MIN_MAJOR && 8106 vpd->fcode_minor >= NIU_VPD_MIN_MINOR)) 8107 np->flags |= NIU_FLAGS_VPD_VALID; 8108 } 8109 8110 /* ESPC_PIO_EN_ENABLE must be set */ 8111 static int __devinit niu_pci_vpd_scan_props(struct niu *np, 8112 u32 start, u32 end) 8113 { 8114 unsigned int found_mask = 0; 8115 #define FOUND_MASK_MODEL 0x00000001 8116 #define FOUND_MASK_BMODEL 0x00000002 8117 #define FOUND_MASK_VERS 0x00000004 8118 #define FOUND_MASK_MAC 0x00000008 8119 #define FOUND_MASK_NMAC 0x00000010 8120 #define FOUND_MASK_PHY 0x00000020 8121 #define FOUND_MASK_ALL 0x0000003f 8122 8123 netif_printk(np, probe, KERN_DEBUG, np->dev, 8124 "VPD_SCAN: start[%x] end[%x]\n", start, end); 8125 while (start < end) { 8126 int len, err, prop_len; 8127 char namebuf[64]; 8128 u8 *prop_buf; 8129 int max_len; 8130 8131 if (found_mask == FOUND_MASK_ALL) { 8132 niu_vpd_parse_version(np); 8133 return 1; 8134 } 8135 8136 err = niu_pci_eeprom_read(np, start + 2); 8137 if (err < 0) 8138 return err; 8139 len = err; 8140 start += 3; 8141 8142 prop_len = niu_pci_eeprom_read(np, start + 4); 8143 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64); 8144 if (err < 0) 8145 return err; 8146 8147 prop_buf = NULL; 8148 max_len = 0; 8149 if (!strcmp(namebuf, "model")) { 8150 prop_buf = np->vpd.model; 8151 max_len = NIU_VPD_MODEL_MAX; 8152 found_mask |= FOUND_MASK_MODEL; 8153 } else if (!strcmp(namebuf, "board-model")) { 8154 prop_buf = np->vpd.board_model; 8155 max_len = NIU_VPD_BD_MODEL_MAX; 8156 found_mask |= FOUND_MASK_BMODEL; 8157 } else if (!strcmp(namebuf, "version")) { 8158 prop_buf = np->vpd.version; 8159 max_len = NIU_VPD_VERSION_MAX; 8160 found_mask |= FOUND_MASK_VERS; 8161 } else if (!strcmp(namebuf, "local-mac-address")) { 8162 prop_buf = np->vpd.local_mac; 8163 max_len = ETH_ALEN; 8164 found_mask |= FOUND_MASK_MAC; 8165 } else if (!strcmp(namebuf, "num-mac-addresses")) { 8166 prop_buf = &np->vpd.mac_num; 8167 max_len = 1; 8168 found_mask |= FOUND_MASK_NMAC; 8169 } else if (!strcmp(namebuf, "phy-type")) { 8170 prop_buf = np->vpd.phy_type; 8171 max_len = NIU_VPD_PHY_TYPE_MAX; 8172 found_mask |= FOUND_MASK_PHY; 8173 } 8174 8175 if (max_len && prop_len > max_len) { 8176 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len); 8177 return -EINVAL; 8178 } 8179 8180 if (prop_buf) { 8181 u32 off = start + 5 + err; 8182 int i; 8183 8184 netif_printk(np, probe, KERN_DEBUG, np->dev, 8185 "VPD_SCAN: Reading in property [%s] len[%d]\n", 8186 namebuf, prop_len); 8187 for (i = 0; i < prop_len; i++) 8188 *prop_buf++ = niu_pci_eeprom_read(np, off + i); 8189 } 8190 8191 start += len; 8192 } 8193 8194 return 0; 8195 } 8196 8197 /* ESPC_PIO_EN_ENABLE must be set */ 8198 static void __devinit niu_pci_vpd_fetch(struct niu *np, u32 start) 8199 { 8200 u32 offset; 8201 int err; 8202 8203 err = niu_pci_eeprom_read16_swp(np, start + 1); 8204 if (err < 0) 8205 return; 8206 8207 offset = err + 3; 8208 8209 while (start + offset < ESPC_EEPROM_SIZE) { 8210 u32 here = start + offset; 8211 u32 end; 8212 8213 err = niu_pci_eeprom_read(np, here); 8214 if (err != 0x90) 8215 return; 8216 8217 err = niu_pci_eeprom_read16_swp(np, here + 1); 8218 if (err < 0) 8219 return; 8220 8221 here = start + offset + 3; 8222 end = start + offset + err; 8223 8224 offset += err; 8225 8226 err = niu_pci_vpd_scan_props(np, here, end); 8227 if (err < 0 || err == 1) 8228 return; 8229 } 8230 } 8231 8232 /* ESPC_PIO_EN_ENABLE must be set */ 8233 static u32 __devinit niu_pci_vpd_offset(struct niu *np) 8234 { 8235 u32 start = 0, end = ESPC_EEPROM_SIZE, ret; 8236 int err; 8237 8238 while (start < end) { 8239 ret = start; 8240 8241 /* ROM header signature? */ 8242 err = niu_pci_eeprom_read16(np, start + 0); 8243 if (err != 0x55aa) 8244 return 0; 8245 8246 /* Apply offset to PCI data structure. */ 8247 err = niu_pci_eeprom_read16(np, start + 23); 8248 if (err < 0) 8249 return 0; 8250 start += err; 8251 8252 /* Check for "PCIR" signature. */ 8253 err = niu_pci_eeprom_read16(np, start + 0); 8254 if (err != 0x5043) 8255 return 0; 8256 err = niu_pci_eeprom_read16(np, start + 2); 8257 if (err != 0x4952) 8258 return 0; 8259 8260 /* Check for OBP image type. */ 8261 err = niu_pci_eeprom_read(np, start + 20); 8262 if (err < 0) 8263 return 0; 8264 if (err != 0x01) { 8265 err = niu_pci_eeprom_read(np, ret + 2); 8266 if (err < 0) 8267 return 0; 8268 8269 start = ret + (err * 512); 8270 continue; 8271 } 8272 8273 err = niu_pci_eeprom_read16_swp(np, start + 8); 8274 if (err < 0) 8275 return err; 8276 ret += err; 8277 8278 err = niu_pci_eeprom_read(np, ret + 0); 8279 if (err != 0x82) 8280 return 0; 8281 8282 return ret; 8283 } 8284 8285 return 0; 8286 } 8287 8288 static int __devinit niu_phy_type_prop_decode(struct niu *np, 8289 const char *phy_prop) 8290 { 8291 if (!strcmp(phy_prop, "mif")) { 8292 /* 1G copper, MII */ 8293 np->flags &= ~(NIU_FLAGS_FIBER | 8294 NIU_FLAGS_10G); 8295 np->mac_xcvr = MAC_XCVR_MII; 8296 } else if (!strcmp(phy_prop, "xgf")) { 8297 /* 10G fiber, XPCS */ 8298 np->flags |= (NIU_FLAGS_10G | 8299 NIU_FLAGS_FIBER); 8300 np->mac_xcvr = MAC_XCVR_XPCS; 8301 } else if (!strcmp(phy_prop, "pcs")) { 8302 /* 1G fiber, PCS */ 8303 np->flags &= ~NIU_FLAGS_10G; 8304 np->flags |= NIU_FLAGS_FIBER; 8305 np->mac_xcvr = MAC_XCVR_PCS; 8306 } else if (!strcmp(phy_prop, "xgc")) { 8307 /* 10G copper, XPCS */ 8308 np->flags |= NIU_FLAGS_10G; 8309 np->flags &= ~NIU_FLAGS_FIBER; 8310 np->mac_xcvr = MAC_XCVR_XPCS; 8311 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) { 8312 /* 10G Serdes or 1G Serdes, default to 10G */ 8313 np->flags |= NIU_FLAGS_10G; 8314 np->flags &= ~NIU_FLAGS_FIBER; 8315 np->flags |= NIU_FLAGS_XCVR_SERDES; 8316 np->mac_xcvr = MAC_XCVR_XPCS; 8317 } else { 8318 return -EINVAL; 8319 } 8320 return 0; 8321 } 8322 8323 static int niu_pci_vpd_get_nports(struct niu *np) 8324 { 8325 int ports = 0; 8326 8327 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) || 8328 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) || 8329 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) || 8330 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) || 8331 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) { 8332 ports = 4; 8333 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) || 8334 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) || 8335 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) || 8336 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) { 8337 ports = 2; 8338 } 8339 8340 return ports; 8341 } 8342 8343 static void __devinit niu_pci_vpd_validate(struct niu *np) 8344 { 8345 struct net_device *dev = np->dev; 8346 struct niu_vpd *vpd = &np->vpd; 8347 u8 val8; 8348 8349 if (!is_valid_ether_addr(&vpd->local_mac[0])) { 8350 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n"); 8351 8352 np->flags &= ~NIU_FLAGS_VPD_VALID; 8353 return; 8354 } 8355 8356 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8357 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8358 np->flags |= NIU_FLAGS_10G; 8359 np->flags &= ~NIU_FLAGS_FIBER; 8360 np->flags |= NIU_FLAGS_XCVR_SERDES; 8361 np->mac_xcvr = MAC_XCVR_PCS; 8362 if (np->port > 1) { 8363 np->flags |= NIU_FLAGS_FIBER; 8364 np->flags &= ~NIU_FLAGS_10G; 8365 } 8366 if (np->flags & NIU_FLAGS_10G) 8367 np->mac_xcvr = MAC_XCVR_XPCS; 8368 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8369 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 8370 NIU_FLAGS_HOTPLUG_PHY); 8371 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 8372 dev_err(np->device, "Illegal phy string [%s]\n", 8373 np->vpd.phy_type); 8374 dev_err(np->device, "Falling back to SPROM\n"); 8375 np->flags &= ~NIU_FLAGS_VPD_VALID; 8376 return; 8377 } 8378 8379 memcpy(dev->perm_addr, vpd->local_mac, ETH_ALEN); 8380 8381 val8 = dev->perm_addr[5]; 8382 dev->perm_addr[5] += np->port; 8383 if (dev->perm_addr[5] < val8) 8384 dev->perm_addr[4]++; 8385 8386 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); 8387 } 8388 8389 static int __devinit niu_pci_probe_sprom(struct niu *np) 8390 { 8391 struct net_device *dev = np->dev; 8392 int len, i; 8393 u64 val, sum; 8394 u8 val8; 8395 8396 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); 8397 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; 8398 len = val / 4; 8399 8400 np->eeprom_len = len; 8401 8402 netif_printk(np, probe, KERN_DEBUG, np->dev, 8403 "SPROM: Image size %llu\n", (unsigned long long)val); 8404 8405 sum = 0; 8406 for (i = 0; i < len; i++) { 8407 val = nr64(ESPC_NCR(i)); 8408 sum += (val >> 0) & 0xff; 8409 sum += (val >> 8) & 0xff; 8410 sum += (val >> 16) & 0xff; 8411 sum += (val >> 24) & 0xff; 8412 } 8413 netif_printk(np, probe, KERN_DEBUG, np->dev, 8414 "SPROM: Checksum %x\n", (int)(sum & 0xff)); 8415 if ((sum & 0xff) != 0xab) { 8416 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff)); 8417 return -EINVAL; 8418 } 8419 8420 val = nr64(ESPC_PHY_TYPE); 8421 switch (np->port) { 8422 case 0: 8423 val8 = (val & ESPC_PHY_TYPE_PORT0) >> 8424 ESPC_PHY_TYPE_PORT0_SHIFT; 8425 break; 8426 case 1: 8427 val8 = (val & ESPC_PHY_TYPE_PORT1) >> 8428 ESPC_PHY_TYPE_PORT1_SHIFT; 8429 break; 8430 case 2: 8431 val8 = (val & ESPC_PHY_TYPE_PORT2) >> 8432 ESPC_PHY_TYPE_PORT2_SHIFT; 8433 break; 8434 case 3: 8435 val8 = (val & ESPC_PHY_TYPE_PORT3) >> 8436 ESPC_PHY_TYPE_PORT3_SHIFT; 8437 break; 8438 default: 8439 dev_err(np->device, "Bogus port number %u\n", 8440 np->port); 8441 return -EINVAL; 8442 } 8443 netif_printk(np, probe, KERN_DEBUG, np->dev, 8444 "SPROM: PHY type %x\n", val8); 8445 8446 switch (val8) { 8447 case ESPC_PHY_TYPE_1G_COPPER: 8448 /* 1G copper, MII */ 8449 np->flags &= ~(NIU_FLAGS_FIBER | 8450 NIU_FLAGS_10G); 8451 np->mac_xcvr = MAC_XCVR_MII; 8452 break; 8453 8454 case ESPC_PHY_TYPE_1G_FIBER: 8455 /* 1G fiber, PCS */ 8456 np->flags &= ~NIU_FLAGS_10G; 8457 np->flags |= NIU_FLAGS_FIBER; 8458 np->mac_xcvr = MAC_XCVR_PCS; 8459 break; 8460 8461 case ESPC_PHY_TYPE_10G_COPPER: 8462 /* 10G copper, XPCS */ 8463 np->flags |= NIU_FLAGS_10G; 8464 np->flags &= ~NIU_FLAGS_FIBER; 8465 np->mac_xcvr = MAC_XCVR_XPCS; 8466 break; 8467 8468 case ESPC_PHY_TYPE_10G_FIBER: 8469 /* 10G fiber, XPCS */ 8470 np->flags |= (NIU_FLAGS_10G | 8471 NIU_FLAGS_FIBER); 8472 np->mac_xcvr = MAC_XCVR_XPCS; 8473 break; 8474 8475 default: 8476 dev_err(np->device, "Bogus SPROM phy type %u\n", val8); 8477 return -EINVAL; 8478 } 8479 8480 val = nr64(ESPC_MAC_ADDR0); 8481 netif_printk(np, probe, KERN_DEBUG, np->dev, 8482 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val); 8483 dev->perm_addr[0] = (val >> 0) & 0xff; 8484 dev->perm_addr[1] = (val >> 8) & 0xff; 8485 dev->perm_addr[2] = (val >> 16) & 0xff; 8486 dev->perm_addr[3] = (val >> 24) & 0xff; 8487 8488 val = nr64(ESPC_MAC_ADDR1); 8489 netif_printk(np, probe, KERN_DEBUG, np->dev, 8490 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val); 8491 dev->perm_addr[4] = (val >> 0) & 0xff; 8492 dev->perm_addr[5] = (val >> 8) & 0xff; 8493 8494 if (!is_valid_ether_addr(&dev->perm_addr[0])) { 8495 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n", 8496 dev->perm_addr); 8497 return -EINVAL; 8498 } 8499 8500 val8 = dev->perm_addr[5]; 8501 dev->perm_addr[5] += np->port; 8502 if (dev->perm_addr[5] < val8) 8503 dev->perm_addr[4]++; 8504 8505 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); 8506 8507 val = nr64(ESPC_MOD_STR_LEN); 8508 netif_printk(np, probe, KERN_DEBUG, np->dev, 8509 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8510 if (val >= 8 * 4) 8511 return -EINVAL; 8512 8513 for (i = 0; i < val; i += 4) { 8514 u64 tmp = nr64(ESPC_NCR(5 + (i / 4))); 8515 8516 np->vpd.model[i + 3] = (tmp >> 0) & 0xff; 8517 np->vpd.model[i + 2] = (tmp >> 8) & 0xff; 8518 np->vpd.model[i + 1] = (tmp >> 16) & 0xff; 8519 np->vpd.model[i + 0] = (tmp >> 24) & 0xff; 8520 } 8521 np->vpd.model[val] = '\0'; 8522 8523 val = nr64(ESPC_BD_MOD_STR_LEN); 8524 netif_printk(np, probe, KERN_DEBUG, np->dev, 8525 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8526 if (val >= 4 * 4) 8527 return -EINVAL; 8528 8529 for (i = 0; i < val; i += 4) { 8530 u64 tmp = nr64(ESPC_NCR(14 + (i / 4))); 8531 8532 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff; 8533 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff; 8534 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff; 8535 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff; 8536 } 8537 np->vpd.board_model[val] = '\0'; 8538 8539 np->vpd.mac_num = 8540 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL; 8541 netif_printk(np, probe, KERN_DEBUG, np->dev, 8542 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num); 8543 8544 return 0; 8545 } 8546 8547 static int __devinit niu_get_and_validate_port(struct niu *np) 8548 { 8549 struct niu_parent *parent = np->parent; 8550 8551 if (np->port <= 1) 8552 np->flags |= NIU_FLAGS_XMAC; 8553 8554 if (!parent->num_ports) { 8555 if (parent->plat_type == PLAT_TYPE_NIU) { 8556 parent->num_ports = 2; 8557 } else { 8558 parent->num_ports = niu_pci_vpd_get_nports(np); 8559 if (!parent->num_ports) { 8560 /* Fall back to SPROM as last resort. 8561 * This will fail on most cards. 8562 */ 8563 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) & 8564 ESPC_NUM_PORTS_MACS_VAL; 8565 8566 /* All of the current probing methods fail on 8567 * Maramba on-board parts. 8568 */ 8569 if (!parent->num_ports) 8570 parent->num_ports = 4; 8571 } 8572 } 8573 } 8574 8575 if (np->port >= parent->num_ports) 8576 return -ENODEV; 8577 8578 return 0; 8579 } 8580 8581 static int __devinit phy_record(struct niu_parent *parent, 8582 struct phy_probe_info *p, 8583 int dev_id_1, int dev_id_2, u8 phy_port, 8584 int type) 8585 { 8586 u32 id = (dev_id_1 << 16) | dev_id_2; 8587 u8 idx; 8588 8589 if (dev_id_1 < 0 || dev_id_2 < 0) 8590 return 0; 8591 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) { 8592 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) && 8593 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011) && 8594 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8706)) 8595 return 0; 8596 } else { 8597 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R) 8598 return 0; 8599 } 8600 8601 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n", 8602 parent->index, id, 8603 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" : 8604 type == PHY_TYPE_PCS ? "PCS" : "MII", 8605 phy_port); 8606 8607 if (p->cur[type] >= NIU_MAX_PORTS) { 8608 pr_err("Too many PHY ports\n"); 8609 return -EINVAL; 8610 } 8611 idx = p->cur[type]; 8612 p->phy_id[type][idx] = id; 8613 p->phy_port[type][idx] = phy_port; 8614 p->cur[type] = idx + 1; 8615 return 0; 8616 } 8617 8618 static int __devinit port_has_10g(struct phy_probe_info *p, int port) 8619 { 8620 int i; 8621 8622 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) { 8623 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port) 8624 return 1; 8625 } 8626 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) { 8627 if (p->phy_port[PHY_TYPE_PCS][i] == port) 8628 return 1; 8629 } 8630 8631 return 0; 8632 } 8633 8634 static int __devinit count_10g_ports(struct phy_probe_info *p, int *lowest) 8635 { 8636 int port, cnt; 8637 8638 cnt = 0; 8639 *lowest = 32; 8640 for (port = 8; port < 32; port++) { 8641 if (port_has_10g(p, port)) { 8642 if (!cnt) 8643 *lowest = port; 8644 cnt++; 8645 } 8646 } 8647 8648 return cnt; 8649 } 8650 8651 static int __devinit count_1g_ports(struct phy_probe_info *p, int *lowest) 8652 { 8653 *lowest = 32; 8654 if (p->cur[PHY_TYPE_MII]) 8655 *lowest = p->phy_port[PHY_TYPE_MII][0]; 8656 8657 return p->cur[PHY_TYPE_MII]; 8658 } 8659 8660 static void __devinit niu_n2_divide_channels(struct niu_parent *parent) 8661 { 8662 int num_ports = parent->num_ports; 8663 int i; 8664 8665 for (i = 0; i < num_ports; i++) { 8666 parent->rxchan_per_port[i] = (16 / num_ports); 8667 parent->txchan_per_port[i] = (16 / num_ports); 8668 8669 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8670 parent->index, i, 8671 parent->rxchan_per_port[i], 8672 parent->txchan_per_port[i]); 8673 } 8674 } 8675 8676 static void __devinit niu_divide_channels(struct niu_parent *parent, 8677 int num_10g, int num_1g) 8678 { 8679 int num_ports = parent->num_ports; 8680 int rx_chans_per_10g, rx_chans_per_1g; 8681 int tx_chans_per_10g, tx_chans_per_1g; 8682 int i, tot_rx, tot_tx; 8683 8684 if (!num_10g || !num_1g) { 8685 rx_chans_per_10g = rx_chans_per_1g = 8686 (NIU_NUM_RXCHAN / num_ports); 8687 tx_chans_per_10g = tx_chans_per_1g = 8688 (NIU_NUM_TXCHAN / num_ports); 8689 } else { 8690 rx_chans_per_1g = NIU_NUM_RXCHAN / 8; 8691 rx_chans_per_10g = (NIU_NUM_RXCHAN - 8692 (rx_chans_per_1g * num_1g)) / 8693 num_10g; 8694 8695 tx_chans_per_1g = NIU_NUM_TXCHAN / 6; 8696 tx_chans_per_10g = (NIU_NUM_TXCHAN - 8697 (tx_chans_per_1g * num_1g)) / 8698 num_10g; 8699 } 8700 8701 tot_rx = tot_tx = 0; 8702 for (i = 0; i < num_ports; i++) { 8703 int type = phy_decode(parent->port_phy, i); 8704 8705 if (type == PORT_TYPE_10G) { 8706 parent->rxchan_per_port[i] = rx_chans_per_10g; 8707 parent->txchan_per_port[i] = tx_chans_per_10g; 8708 } else { 8709 parent->rxchan_per_port[i] = rx_chans_per_1g; 8710 parent->txchan_per_port[i] = tx_chans_per_1g; 8711 } 8712 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8713 parent->index, i, 8714 parent->rxchan_per_port[i], 8715 parent->txchan_per_port[i]); 8716 tot_rx += parent->rxchan_per_port[i]; 8717 tot_tx += parent->txchan_per_port[i]; 8718 } 8719 8720 if (tot_rx > NIU_NUM_RXCHAN) { 8721 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n", 8722 parent->index, tot_rx); 8723 for (i = 0; i < num_ports; i++) 8724 parent->rxchan_per_port[i] = 1; 8725 } 8726 if (tot_tx > NIU_NUM_TXCHAN) { 8727 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n", 8728 parent->index, tot_tx); 8729 for (i = 0; i < num_ports; i++) 8730 parent->txchan_per_port[i] = 1; 8731 } 8732 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) { 8733 pr_warning("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n", 8734 parent->index, tot_rx, tot_tx); 8735 } 8736 } 8737 8738 static void __devinit niu_divide_rdc_groups(struct niu_parent *parent, 8739 int num_10g, int num_1g) 8740 { 8741 int i, num_ports = parent->num_ports; 8742 int rdc_group, rdc_groups_per_port; 8743 int rdc_channel_base; 8744 8745 rdc_group = 0; 8746 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports; 8747 8748 rdc_channel_base = 0; 8749 8750 for (i = 0; i < num_ports; i++) { 8751 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i]; 8752 int grp, num_channels = parent->rxchan_per_port[i]; 8753 int this_channel_offset; 8754 8755 tp->first_table_num = rdc_group; 8756 tp->num_tables = rdc_groups_per_port; 8757 this_channel_offset = 0; 8758 for (grp = 0; grp < tp->num_tables; grp++) { 8759 struct rdc_table *rt = &tp->tables[grp]; 8760 int slot; 8761 8762 pr_info("niu%d: Port %d RDC tbl(%d) [ ", 8763 parent->index, i, tp->first_table_num + grp); 8764 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) { 8765 rt->rxdma_channel[slot] = 8766 rdc_channel_base + this_channel_offset; 8767 8768 pr_cont("%d ", rt->rxdma_channel[slot]); 8769 8770 if (++this_channel_offset == num_channels) 8771 this_channel_offset = 0; 8772 } 8773 pr_cont("]\n"); 8774 } 8775 8776 parent->rdc_default[i] = rdc_channel_base; 8777 8778 rdc_channel_base += num_channels; 8779 rdc_group += rdc_groups_per_port; 8780 } 8781 } 8782 8783 static int __devinit fill_phy_probe_info(struct niu *np, 8784 struct niu_parent *parent, 8785 struct phy_probe_info *info) 8786 { 8787 unsigned long flags; 8788 int port, err; 8789 8790 memset(info, 0, sizeof(*info)); 8791 8792 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */ 8793 niu_lock_parent(np, flags); 8794 err = 0; 8795 for (port = 8; port < 32; port++) { 8796 int dev_id_1, dev_id_2; 8797 8798 dev_id_1 = mdio_read(np, port, 8799 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1); 8800 dev_id_2 = mdio_read(np, port, 8801 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2); 8802 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8803 PHY_TYPE_PMA_PMD); 8804 if (err) 8805 break; 8806 dev_id_1 = mdio_read(np, port, 8807 NIU_PCS_DEV_ADDR, MII_PHYSID1); 8808 dev_id_2 = mdio_read(np, port, 8809 NIU_PCS_DEV_ADDR, MII_PHYSID2); 8810 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8811 PHY_TYPE_PCS); 8812 if (err) 8813 break; 8814 dev_id_1 = mii_read(np, port, MII_PHYSID1); 8815 dev_id_2 = mii_read(np, port, MII_PHYSID2); 8816 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8817 PHY_TYPE_MII); 8818 if (err) 8819 break; 8820 } 8821 niu_unlock_parent(np, flags); 8822 8823 return err; 8824 } 8825 8826 static int __devinit walk_phys(struct niu *np, struct niu_parent *parent) 8827 { 8828 struct phy_probe_info *info = &parent->phy_probe_info; 8829 int lowest_10g, lowest_1g; 8830 int num_10g, num_1g; 8831 u32 val; 8832 int err; 8833 8834 num_10g = num_1g = 0; 8835 8836 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8837 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8838 num_10g = 0; 8839 num_1g = 2; 8840 parent->plat_type = PLAT_TYPE_ATCA_CP3220; 8841 parent->num_ports = 4; 8842 val = (phy_encode(PORT_TYPE_1G, 0) | 8843 phy_encode(PORT_TYPE_1G, 1) | 8844 phy_encode(PORT_TYPE_1G, 2) | 8845 phy_encode(PORT_TYPE_1G, 3)); 8846 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8847 num_10g = 2; 8848 num_1g = 0; 8849 parent->num_ports = 2; 8850 val = (phy_encode(PORT_TYPE_10G, 0) | 8851 phy_encode(PORT_TYPE_10G, 1)); 8852 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) && 8853 (parent->plat_type == PLAT_TYPE_NIU)) { 8854 /* this is the Monza case */ 8855 if (np->flags & NIU_FLAGS_10G) { 8856 val = (phy_encode(PORT_TYPE_10G, 0) | 8857 phy_encode(PORT_TYPE_10G, 1)); 8858 } else { 8859 val = (phy_encode(PORT_TYPE_1G, 0) | 8860 phy_encode(PORT_TYPE_1G, 1)); 8861 } 8862 } else { 8863 err = fill_phy_probe_info(np, parent, info); 8864 if (err) 8865 return err; 8866 8867 num_10g = count_10g_ports(info, &lowest_10g); 8868 num_1g = count_1g_ports(info, &lowest_1g); 8869 8870 switch ((num_10g << 4) | num_1g) { 8871 case 0x24: 8872 if (lowest_1g == 10) 8873 parent->plat_type = PLAT_TYPE_VF_P0; 8874 else if (lowest_1g == 26) 8875 parent->plat_type = PLAT_TYPE_VF_P1; 8876 else 8877 goto unknown_vg_1g_port; 8878 8879 /* fallthru */ 8880 case 0x22: 8881 val = (phy_encode(PORT_TYPE_10G, 0) | 8882 phy_encode(PORT_TYPE_10G, 1) | 8883 phy_encode(PORT_TYPE_1G, 2) | 8884 phy_encode(PORT_TYPE_1G, 3)); 8885 break; 8886 8887 case 0x20: 8888 val = (phy_encode(PORT_TYPE_10G, 0) | 8889 phy_encode(PORT_TYPE_10G, 1)); 8890 break; 8891 8892 case 0x10: 8893 val = phy_encode(PORT_TYPE_10G, np->port); 8894 break; 8895 8896 case 0x14: 8897 if (lowest_1g == 10) 8898 parent->plat_type = PLAT_TYPE_VF_P0; 8899 else if (lowest_1g == 26) 8900 parent->plat_type = PLAT_TYPE_VF_P1; 8901 else 8902 goto unknown_vg_1g_port; 8903 8904 /* fallthru */ 8905 case 0x13: 8906 if ((lowest_10g & 0x7) == 0) 8907 val = (phy_encode(PORT_TYPE_10G, 0) | 8908 phy_encode(PORT_TYPE_1G, 1) | 8909 phy_encode(PORT_TYPE_1G, 2) | 8910 phy_encode(PORT_TYPE_1G, 3)); 8911 else 8912 val = (phy_encode(PORT_TYPE_1G, 0) | 8913 phy_encode(PORT_TYPE_10G, 1) | 8914 phy_encode(PORT_TYPE_1G, 2) | 8915 phy_encode(PORT_TYPE_1G, 3)); 8916 break; 8917 8918 case 0x04: 8919 if (lowest_1g == 10) 8920 parent->plat_type = PLAT_TYPE_VF_P0; 8921 else if (lowest_1g == 26) 8922 parent->plat_type = PLAT_TYPE_VF_P1; 8923 else 8924 goto unknown_vg_1g_port; 8925 8926 val = (phy_encode(PORT_TYPE_1G, 0) | 8927 phy_encode(PORT_TYPE_1G, 1) | 8928 phy_encode(PORT_TYPE_1G, 2) | 8929 phy_encode(PORT_TYPE_1G, 3)); 8930 break; 8931 8932 default: 8933 pr_err("Unsupported port config 10G[%d] 1G[%d]\n", 8934 num_10g, num_1g); 8935 return -EINVAL; 8936 } 8937 } 8938 8939 parent->port_phy = val; 8940 8941 if (parent->plat_type == PLAT_TYPE_NIU) 8942 niu_n2_divide_channels(parent); 8943 else 8944 niu_divide_channels(parent, num_10g, num_1g); 8945 8946 niu_divide_rdc_groups(parent, num_10g, num_1g); 8947 8948 return 0; 8949 8950 unknown_vg_1g_port: 8951 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g); 8952 return -EINVAL; 8953 } 8954 8955 static int __devinit niu_probe_ports(struct niu *np) 8956 { 8957 struct niu_parent *parent = np->parent; 8958 int err, i; 8959 8960 if (parent->port_phy == PORT_PHY_UNKNOWN) { 8961 err = walk_phys(np, parent); 8962 if (err) 8963 return err; 8964 8965 niu_set_ldg_timer_res(np, 2); 8966 for (i = 0; i <= LDN_MAX; i++) 8967 niu_ldn_irq_enable(np, i, 0); 8968 } 8969 8970 if (parent->port_phy == PORT_PHY_INVALID) 8971 return -EINVAL; 8972 8973 return 0; 8974 } 8975 8976 static int __devinit niu_classifier_swstate_init(struct niu *np) 8977 { 8978 struct niu_classifier *cp = &np->clas; 8979 8980 cp->tcam_top = (u16) np->port; 8981 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports; 8982 cp->h1_init = 0xffffffff; 8983 cp->h2_init = 0xffff; 8984 8985 return fflp_early_init(np); 8986 } 8987 8988 static void __devinit niu_link_config_init(struct niu *np) 8989 { 8990 struct niu_link_config *lp = &np->link_config; 8991 8992 lp->advertising = (ADVERTISED_10baseT_Half | 8993 ADVERTISED_10baseT_Full | 8994 ADVERTISED_100baseT_Half | 8995 ADVERTISED_100baseT_Full | 8996 ADVERTISED_1000baseT_Half | 8997 ADVERTISED_1000baseT_Full | 8998 ADVERTISED_10000baseT_Full | 8999 ADVERTISED_Autoneg); 9000 lp->speed = lp->active_speed = SPEED_INVALID; 9001 lp->duplex = DUPLEX_FULL; 9002 lp->active_duplex = DUPLEX_INVALID; 9003 lp->autoneg = 1; 9004 #if 0 9005 lp->loopback_mode = LOOPBACK_MAC; 9006 lp->active_speed = SPEED_10000; 9007 lp->active_duplex = DUPLEX_FULL; 9008 #else 9009 lp->loopback_mode = LOOPBACK_DISABLED; 9010 #endif 9011 } 9012 9013 static int __devinit niu_init_mac_ipp_pcs_base(struct niu *np) 9014 { 9015 switch (np->port) { 9016 case 0: 9017 np->mac_regs = np->regs + XMAC_PORT0_OFF; 9018 np->ipp_off = 0x00000; 9019 np->pcs_off = 0x04000; 9020 np->xpcs_off = 0x02000; 9021 break; 9022 9023 case 1: 9024 np->mac_regs = np->regs + XMAC_PORT1_OFF; 9025 np->ipp_off = 0x08000; 9026 np->pcs_off = 0x0a000; 9027 np->xpcs_off = 0x08000; 9028 break; 9029 9030 case 2: 9031 np->mac_regs = np->regs + BMAC_PORT2_OFF; 9032 np->ipp_off = 0x04000; 9033 np->pcs_off = 0x0e000; 9034 np->xpcs_off = ~0UL; 9035 break; 9036 9037 case 3: 9038 np->mac_regs = np->regs + BMAC_PORT3_OFF; 9039 np->ipp_off = 0x0c000; 9040 np->pcs_off = 0x12000; 9041 np->xpcs_off = ~0UL; 9042 break; 9043 9044 default: 9045 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port); 9046 return -EINVAL; 9047 } 9048 9049 return 0; 9050 } 9051 9052 static void __devinit niu_try_msix(struct niu *np, u8 *ldg_num_map) 9053 { 9054 struct msix_entry msi_vec[NIU_NUM_LDG]; 9055 struct niu_parent *parent = np->parent; 9056 struct pci_dev *pdev = np->pdev; 9057 int i, num_irqs, err; 9058 u8 first_ldg; 9059 9060 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port; 9061 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++) 9062 ldg_num_map[i] = first_ldg + i; 9063 9064 num_irqs = (parent->rxchan_per_port[np->port] + 9065 parent->txchan_per_port[np->port] + 9066 (np->port == 0 ? 3 : 1)); 9067 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports)); 9068 9069 retry: 9070 for (i = 0; i < num_irqs; i++) { 9071 msi_vec[i].vector = 0; 9072 msi_vec[i].entry = i; 9073 } 9074 9075 err = pci_enable_msix(pdev, msi_vec, num_irqs); 9076 if (err < 0) { 9077 np->flags &= ~NIU_FLAGS_MSIX; 9078 return; 9079 } 9080 if (err > 0) { 9081 num_irqs = err; 9082 goto retry; 9083 } 9084 9085 np->flags |= NIU_FLAGS_MSIX; 9086 for (i = 0; i < num_irqs; i++) 9087 np->ldg[i].irq = msi_vec[i].vector; 9088 np->num_ldg = num_irqs; 9089 } 9090 9091 static int __devinit niu_n2_irq_init(struct niu *np, u8 *ldg_num_map) 9092 { 9093 #ifdef CONFIG_SPARC64 9094 struct platform_device *op = np->op; 9095 const u32 *int_prop; 9096 int i; 9097 9098 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL); 9099 if (!int_prop) 9100 return -ENODEV; 9101 9102 for (i = 0; i < op->archdata.num_irqs; i++) { 9103 ldg_num_map[i] = int_prop[i]; 9104 np->ldg[i].irq = op->archdata.irqs[i]; 9105 } 9106 9107 np->num_ldg = op->archdata.num_irqs; 9108 9109 return 0; 9110 #else 9111 return -EINVAL; 9112 #endif 9113 } 9114 9115 static int __devinit niu_ldg_init(struct niu *np) 9116 { 9117 struct niu_parent *parent = np->parent; 9118 u8 ldg_num_map[NIU_NUM_LDG]; 9119 int first_chan, num_chan; 9120 int i, err, ldg_rotor; 9121 u8 port; 9122 9123 np->num_ldg = 1; 9124 np->ldg[0].irq = np->dev->irq; 9125 if (parent->plat_type == PLAT_TYPE_NIU) { 9126 err = niu_n2_irq_init(np, ldg_num_map); 9127 if (err) 9128 return err; 9129 } else 9130 niu_try_msix(np, ldg_num_map); 9131 9132 port = np->port; 9133 for (i = 0; i < np->num_ldg; i++) { 9134 struct niu_ldg *lp = &np->ldg[i]; 9135 9136 netif_napi_add(np->dev, &lp->napi, niu_poll, 64); 9137 9138 lp->np = np; 9139 lp->ldg_num = ldg_num_map[i]; 9140 lp->timer = 2; /* XXX */ 9141 9142 /* On N2 NIU the firmware has setup the SID mappings so they go 9143 * to the correct values that will route the LDG to the proper 9144 * interrupt in the NCU interrupt table. 9145 */ 9146 if (np->parent->plat_type != PLAT_TYPE_NIU) { 9147 err = niu_set_ldg_sid(np, lp->ldg_num, port, i); 9148 if (err) 9149 return err; 9150 } 9151 } 9152 9153 /* We adopt the LDG assignment ordering used by the N2 NIU 9154 * 'interrupt' properties because that simplifies a lot of 9155 * things. This ordering is: 9156 * 9157 * MAC 9158 * MIF (if port zero) 9159 * SYSERR (if port zero) 9160 * RX channels 9161 * TX channels 9162 */ 9163 9164 ldg_rotor = 0; 9165 9166 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor], 9167 LDN_MAC(port)); 9168 if (err) 9169 return err; 9170 9171 ldg_rotor++; 9172 if (ldg_rotor == np->num_ldg) 9173 ldg_rotor = 0; 9174 9175 if (port == 0) { 9176 err = niu_ldg_assign_ldn(np, parent, 9177 ldg_num_map[ldg_rotor], 9178 LDN_MIF); 9179 if (err) 9180 return err; 9181 9182 ldg_rotor++; 9183 if (ldg_rotor == np->num_ldg) 9184 ldg_rotor = 0; 9185 9186 err = niu_ldg_assign_ldn(np, parent, 9187 ldg_num_map[ldg_rotor], 9188 LDN_DEVICE_ERROR); 9189 if (err) 9190 return err; 9191 9192 ldg_rotor++; 9193 if (ldg_rotor == np->num_ldg) 9194 ldg_rotor = 0; 9195 9196 } 9197 9198 first_chan = 0; 9199 for (i = 0; i < port; i++) 9200 first_chan += parent->rxchan_per_port[i]; 9201 num_chan = parent->rxchan_per_port[port]; 9202 9203 for (i = first_chan; i < (first_chan + num_chan); i++) { 9204 err = niu_ldg_assign_ldn(np, parent, 9205 ldg_num_map[ldg_rotor], 9206 LDN_RXDMA(i)); 9207 if (err) 9208 return err; 9209 ldg_rotor++; 9210 if (ldg_rotor == np->num_ldg) 9211 ldg_rotor = 0; 9212 } 9213 9214 first_chan = 0; 9215 for (i = 0; i < port; i++) 9216 first_chan += parent->txchan_per_port[i]; 9217 num_chan = parent->txchan_per_port[port]; 9218 for (i = first_chan; i < (first_chan + num_chan); i++) { 9219 err = niu_ldg_assign_ldn(np, parent, 9220 ldg_num_map[ldg_rotor], 9221 LDN_TXDMA(i)); 9222 if (err) 9223 return err; 9224 ldg_rotor++; 9225 if (ldg_rotor == np->num_ldg) 9226 ldg_rotor = 0; 9227 } 9228 9229 return 0; 9230 } 9231 9232 static void __devexit niu_ldg_free(struct niu *np) 9233 { 9234 if (np->flags & NIU_FLAGS_MSIX) 9235 pci_disable_msix(np->pdev); 9236 } 9237 9238 static int __devinit niu_get_of_props(struct niu *np) 9239 { 9240 #ifdef CONFIG_SPARC64 9241 struct net_device *dev = np->dev; 9242 struct device_node *dp; 9243 const char *phy_type; 9244 const u8 *mac_addr; 9245 const char *model; 9246 int prop_len; 9247 9248 if (np->parent->plat_type == PLAT_TYPE_NIU) 9249 dp = np->op->dev.of_node; 9250 else 9251 dp = pci_device_to_OF_node(np->pdev); 9252 9253 phy_type = of_get_property(dp, "phy-type", &prop_len); 9254 if (!phy_type) { 9255 netdev_err(dev, "%s: OF node lacks phy-type property\n", 9256 dp->full_name); 9257 return -EINVAL; 9258 } 9259 9260 if (!strcmp(phy_type, "none")) 9261 return -ENODEV; 9262 9263 strcpy(np->vpd.phy_type, phy_type); 9264 9265 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 9266 netdev_err(dev, "%s: Illegal phy string [%s]\n", 9267 dp->full_name, np->vpd.phy_type); 9268 return -EINVAL; 9269 } 9270 9271 mac_addr = of_get_property(dp, "local-mac-address", &prop_len); 9272 if (!mac_addr) { 9273 netdev_err(dev, "%s: OF node lacks local-mac-address property\n", 9274 dp->full_name); 9275 return -EINVAL; 9276 } 9277 if (prop_len != dev->addr_len) { 9278 netdev_err(dev, "%s: OF MAC address prop len (%d) is wrong\n", 9279 dp->full_name, prop_len); 9280 } 9281 memcpy(dev->perm_addr, mac_addr, dev->addr_len); 9282 if (!is_valid_ether_addr(&dev->perm_addr[0])) { 9283 netdev_err(dev, "%s: OF MAC address is invalid\n", 9284 dp->full_name); 9285 netdev_err(dev, "%s: [ %pM ]\n", dp->full_name, dev->perm_addr); 9286 return -EINVAL; 9287 } 9288 9289 memcpy(dev->dev_addr, dev->perm_addr, dev->addr_len); 9290 9291 model = of_get_property(dp, "model", &prop_len); 9292 9293 if (model) 9294 strcpy(np->vpd.model, model); 9295 9296 if (of_find_property(dp, "hot-swappable-phy", &prop_len)) { 9297 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 9298 NIU_FLAGS_HOTPLUG_PHY); 9299 } 9300 9301 return 0; 9302 #else 9303 return -EINVAL; 9304 #endif 9305 } 9306 9307 static int __devinit niu_get_invariants(struct niu *np) 9308 { 9309 int err, have_props; 9310 u32 offset; 9311 9312 err = niu_get_of_props(np); 9313 if (err == -ENODEV) 9314 return err; 9315 9316 have_props = !err; 9317 9318 err = niu_init_mac_ipp_pcs_base(np); 9319 if (err) 9320 return err; 9321 9322 if (have_props) { 9323 err = niu_get_and_validate_port(np); 9324 if (err) 9325 return err; 9326 9327 } else { 9328 if (np->parent->plat_type == PLAT_TYPE_NIU) 9329 return -EINVAL; 9330 9331 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); 9332 offset = niu_pci_vpd_offset(np); 9333 netif_printk(np, probe, KERN_DEBUG, np->dev, 9334 "%s() VPD offset [%08x]\n", __func__, offset); 9335 if (offset) 9336 niu_pci_vpd_fetch(np, offset); 9337 nw64(ESPC_PIO_EN, 0); 9338 9339 if (np->flags & NIU_FLAGS_VPD_VALID) { 9340 niu_pci_vpd_validate(np); 9341 err = niu_get_and_validate_port(np); 9342 if (err) 9343 return err; 9344 } 9345 9346 if (!(np->flags & NIU_FLAGS_VPD_VALID)) { 9347 err = niu_get_and_validate_port(np); 9348 if (err) 9349 return err; 9350 err = niu_pci_probe_sprom(np); 9351 if (err) 9352 return err; 9353 } 9354 } 9355 9356 err = niu_probe_ports(np); 9357 if (err) 9358 return err; 9359 9360 niu_ldg_init(np); 9361 9362 niu_classifier_swstate_init(np); 9363 niu_link_config_init(np); 9364 9365 err = niu_determine_phy_disposition(np); 9366 if (!err) 9367 err = niu_init_link(np); 9368 9369 return err; 9370 } 9371 9372 static LIST_HEAD(niu_parent_list); 9373 static DEFINE_MUTEX(niu_parent_lock); 9374 static int niu_parent_index; 9375 9376 static ssize_t show_port_phy(struct device *dev, 9377 struct device_attribute *attr, char *buf) 9378 { 9379 struct platform_device *plat_dev = to_platform_device(dev); 9380 struct niu_parent *p = plat_dev->dev.platform_data; 9381 u32 port_phy = p->port_phy; 9382 char *orig_buf = buf; 9383 int i; 9384 9385 if (port_phy == PORT_PHY_UNKNOWN || 9386 port_phy == PORT_PHY_INVALID) 9387 return 0; 9388 9389 for (i = 0; i < p->num_ports; i++) { 9390 const char *type_str; 9391 int type; 9392 9393 type = phy_decode(port_phy, i); 9394 if (type == PORT_TYPE_10G) 9395 type_str = "10G"; 9396 else 9397 type_str = "1G"; 9398 buf += sprintf(buf, 9399 (i == 0) ? "%s" : " %s", 9400 type_str); 9401 } 9402 buf += sprintf(buf, "\n"); 9403 return buf - orig_buf; 9404 } 9405 9406 static ssize_t show_plat_type(struct device *dev, 9407 struct device_attribute *attr, char *buf) 9408 { 9409 struct platform_device *plat_dev = to_platform_device(dev); 9410 struct niu_parent *p = plat_dev->dev.platform_data; 9411 const char *type_str; 9412 9413 switch (p->plat_type) { 9414 case PLAT_TYPE_ATLAS: 9415 type_str = "atlas"; 9416 break; 9417 case PLAT_TYPE_NIU: 9418 type_str = "niu"; 9419 break; 9420 case PLAT_TYPE_VF_P0: 9421 type_str = "vf_p0"; 9422 break; 9423 case PLAT_TYPE_VF_P1: 9424 type_str = "vf_p1"; 9425 break; 9426 default: 9427 type_str = "unknown"; 9428 break; 9429 } 9430 9431 return sprintf(buf, "%s\n", type_str); 9432 } 9433 9434 static ssize_t __show_chan_per_port(struct device *dev, 9435 struct device_attribute *attr, char *buf, 9436 int rx) 9437 { 9438 struct platform_device *plat_dev = to_platform_device(dev); 9439 struct niu_parent *p = plat_dev->dev.platform_data; 9440 char *orig_buf = buf; 9441 u8 *arr; 9442 int i; 9443 9444 arr = (rx ? p->rxchan_per_port : p->txchan_per_port); 9445 9446 for (i = 0; i < p->num_ports; i++) { 9447 buf += sprintf(buf, 9448 (i == 0) ? "%d" : " %d", 9449 arr[i]); 9450 } 9451 buf += sprintf(buf, "\n"); 9452 9453 return buf - orig_buf; 9454 } 9455 9456 static ssize_t show_rxchan_per_port(struct device *dev, 9457 struct device_attribute *attr, char *buf) 9458 { 9459 return __show_chan_per_port(dev, attr, buf, 1); 9460 } 9461 9462 static ssize_t show_txchan_per_port(struct device *dev, 9463 struct device_attribute *attr, char *buf) 9464 { 9465 return __show_chan_per_port(dev, attr, buf, 1); 9466 } 9467 9468 static ssize_t show_num_ports(struct device *dev, 9469 struct device_attribute *attr, char *buf) 9470 { 9471 struct platform_device *plat_dev = to_platform_device(dev); 9472 struct niu_parent *p = plat_dev->dev.platform_data; 9473 9474 return sprintf(buf, "%d\n", p->num_ports); 9475 } 9476 9477 static struct device_attribute niu_parent_attributes[] = { 9478 __ATTR(port_phy, S_IRUGO, show_port_phy, NULL), 9479 __ATTR(plat_type, S_IRUGO, show_plat_type, NULL), 9480 __ATTR(rxchan_per_port, S_IRUGO, show_rxchan_per_port, NULL), 9481 __ATTR(txchan_per_port, S_IRUGO, show_txchan_per_port, NULL), 9482 __ATTR(num_ports, S_IRUGO, show_num_ports, NULL), 9483 {} 9484 }; 9485 9486 static struct niu_parent * __devinit niu_new_parent(struct niu *np, 9487 union niu_parent_id *id, 9488 u8 ptype) 9489 { 9490 struct platform_device *plat_dev; 9491 struct niu_parent *p; 9492 int i; 9493 9494 plat_dev = platform_device_register_simple("niu-board", niu_parent_index, 9495 NULL, 0); 9496 if (IS_ERR(plat_dev)) 9497 return NULL; 9498 9499 for (i = 0; attr_name(niu_parent_attributes[i]); i++) { 9500 int err = device_create_file(&plat_dev->dev, 9501 &niu_parent_attributes[i]); 9502 if (err) 9503 goto fail_unregister; 9504 } 9505 9506 p = kzalloc(sizeof(*p), GFP_KERNEL); 9507 if (!p) 9508 goto fail_unregister; 9509 9510 p->index = niu_parent_index++; 9511 9512 plat_dev->dev.platform_data = p; 9513 p->plat_dev = plat_dev; 9514 9515 memcpy(&p->id, id, sizeof(*id)); 9516 p->plat_type = ptype; 9517 INIT_LIST_HEAD(&p->list); 9518 atomic_set(&p->refcnt, 0); 9519 list_add(&p->list, &niu_parent_list); 9520 spin_lock_init(&p->lock); 9521 9522 p->rxdma_clock_divider = 7500; 9523 9524 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES; 9525 if (p->plat_type == PLAT_TYPE_NIU) 9526 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES; 9527 9528 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 9529 int index = i - CLASS_CODE_USER_PROG1; 9530 9531 p->tcam_key[index] = TCAM_KEY_TSEL; 9532 p->flow_key[index] = (FLOW_KEY_IPSA | 9533 FLOW_KEY_IPDA | 9534 FLOW_KEY_PROTO | 9535 (FLOW_KEY_L4_BYTE12 << 9536 FLOW_KEY_L4_0_SHIFT) | 9537 (FLOW_KEY_L4_BYTE12 << 9538 FLOW_KEY_L4_1_SHIFT)); 9539 } 9540 9541 for (i = 0; i < LDN_MAX + 1; i++) 9542 p->ldg_map[i] = LDG_INVALID; 9543 9544 return p; 9545 9546 fail_unregister: 9547 platform_device_unregister(plat_dev); 9548 return NULL; 9549 } 9550 9551 static struct niu_parent * __devinit niu_get_parent(struct niu *np, 9552 union niu_parent_id *id, 9553 u8 ptype) 9554 { 9555 struct niu_parent *p, *tmp; 9556 int port = np->port; 9557 9558 mutex_lock(&niu_parent_lock); 9559 p = NULL; 9560 list_for_each_entry(tmp, &niu_parent_list, list) { 9561 if (!memcmp(id, &tmp->id, sizeof(*id))) { 9562 p = tmp; 9563 break; 9564 } 9565 } 9566 if (!p) 9567 p = niu_new_parent(np, id, ptype); 9568 9569 if (p) { 9570 char port_name[6]; 9571 int err; 9572 9573 sprintf(port_name, "port%d", port); 9574 err = sysfs_create_link(&p->plat_dev->dev.kobj, 9575 &np->device->kobj, 9576 port_name); 9577 if (!err) { 9578 p->ports[port] = np; 9579 atomic_inc(&p->refcnt); 9580 } 9581 } 9582 mutex_unlock(&niu_parent_lock); 9583 9584 return p; 9585 } 9586 9587 static void niu_put_parent(struct niu *np) 9588 { 9589 struct niu_parent *p = np->parent; 9590 u8 port = np->port; 9591 char port_name[6]; 9592 9593 BUG_ON(!p || p->ports[port] != np); 9594 9595 netif_printk(np, probe, KERN_DEBUG, np->dev, 9596 "%s() port[%u]\n", __func__, port); 9597 9598 sprintf(port_name, "port%d", port); 9599 9600 mutex_lock(&niu_parent_lock); 9601 9602 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name); 9603 9604 p->ports[port] = NULL; 9605 np->parent = NULL; 9606 9607 if (atomic_dec_and_test(&p->refcnt)) { 9608 list_del(&p->list); 9609 platform_device_unregister(p->plat_dev); 9610 } 9611 9612 mutex_unlock(&niu_parent_lock); 9613 } 9614 9615 static void *niu_pci_alloc_coherent(struct device *dev, size_t size, 9616 u64 *handle, gfp_t flag) 9617 { 9618 dma_addr_t dh; 9619 void *ret; 9620 9621 ret = dma_alloc_coherent(dev, size, &dh, flag); 9622 if (ret) 9623 *handle = dh; 9624 return ret; 9625 } 9626 9627 static void niu_pci_free_coherent(struct device *dev, size_t size, 9628 void *cpu_addr, u64 handle) 9629 { 9630 dma_free_coherent(dev, size, cpu_addr, handle); 9631 } 9632 9633 static u64 niu_pci_map_page(struct device *dev, struct page *page, 9634 unsigned long offset, size_t size, 9635 enum dma_data_direction direction) 9636 { 9637 return dma_map_page(dev, page, offset, size, direction); 9638 } 9639 9640 static void niu_pci_unmap_page(struct device *dev, u64 dma_address, 9641 size_t size, enum dma_data_direction direction) 9642 { 9643 dma_unmap_page(dev, dma_address, size, direction); 9644 } 9645 9646 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr, 9647 size_t size, 9648 enum dma_data_direction direction) 9649 { 9650 return dma_map_single(dev, cpu_addr, size, direction); 9651 } 9652 9653 static void niu_pci_unmap_single(struct device *dev, u64 dma_address, 9654 size_t size, 9655 enum dma_data_direction direction) 9656 { 9657 dma_unmap_single(dev, dma_address, size, direction); 9658 } 9659 9660 static const struct niu_ops niu_pci_ops = { 9661 .alloc_coherent = niu_pci_alloc_coherent, 9662 .free_coherent = niu_pci_free_coherent, 9663 .map_page = niu_pci_map_page, 9664 .unmap_page = niu_pci_unmap_page, 9665 .map_single = niu_pci_map_single, 9666 .unmap_single = niu_pci_unmap_single, 9667 }; 9668 9669 static void __devinit niu_driver_version(void) 9670 { 9671 static int niu_version_printed; 9672 9673 if (niu_version_printed++ == 0) 9674 pr_info("%s", version); 9675 } 9676 9677 static struct net_device * __devinit niu_alloc_and_init( 9678 struct device *gen_dev, struct pci_dev *pdev, 9679 struct platform_device *op, const struct niu_ops *ops, 9680 u8 port) 9681 { 9682 struct net_device *dev; 9683 struct niu *np; 9684 9685 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN); 9686 if (!dev) { 9687 dev_err(gen_dev, "Etherdev alloc failed, aborting\n"); 9688 return NULL; 9689 } 9690 9691 SET_NETDEV_DEV(dev, gen_dev); 9692 9693 np = netdev_priv(dev); 9694 np->dev = dev; 9695 np->pdev = pdev; 9696 np->op = op; 9697 np->device = gen_dev; 9698 np->ops = ops; 9699 9700 np->msg_enable = niu_debug; 9701 9702 spin_lock_init(&np->lock); 9703 INIT_WORK(&np->reset_task, niu_reset_task); 9704 9705 np->port = port; 9706 9707 return dev; 9708 } 9709 9710 static const struct net_device_ops niu_netdev_ops = { 9711 .ndo_open = niu_open, 9712 .ndo_stop = niu_close, 9713 .ndo_start_xmit = niu_start_xmit, 9714 .ndo_get_stats64 = niu_get_stats, 9715 .ndo_set_rx_mode = niu_set_rx_mode, 9716 .ndo_validate_addr = eth_validate_addr, 9717 .ndo_set_mac_address = niu_set_mac_addr, 9718 .ndo_do_ioctl = niu_ioctl, 9719 .ndo_tx_timeout = niu_tx_timeout, 9720 .ndo_change_mtu = niu_change_mtu, 9721 }; 9722 9723 static void __devinit niu_assign_netdev_ops(struct net_device *dev) 9724 { 9725 dev->netdev_ops = &niu_netdev_ops; 9726 dev->ethtool_ops = &niu_ethtool_ops; 9727 dev->watchdog_timeo = NIU_TX_TIMEOUT; 9728 } 9729 9730 static void __devinit niu_device_announce(struct niu *np) 9731 { 9732 struct net_device *dev = np->dev; 9733 9734 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr); 9735 9736 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) { 9737 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9738 dev->name, 9739 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9740 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9741 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"), 9742 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9743 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9744 np->vpd.phy_type); 9745 } else { 9746 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9747 dev->name, 9748 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9749 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9750 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : 9751 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" : 9752 "COPPER")), 9753 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9754 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9755 np->vpd.phy_type); 9756 } 9757 } 9758 9759 static void __devinit niu_set_basic_features(struct net_device *dev) 9760 { 9761 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH; 9762 dev->features |= dev->hw_features | NETIF_F_RXCSUM; 9763 } 9764 9765 static int __devinit niu_pci_init_one(struct pci_dev *pdev, 9766 const struct pci_device_id *ent) 9767 { 9768 union niu_parent_id parent_id; 9769 struct net_device *dev; 9770 struct niu *np; 9771 int err, pos; 9772 u64 dma_mask; 9773 u16 val16; 9774 9775 niu_driver_version(); 9776 9777 err = pci_enable_device(pdev); 9778 if (err) { 9779 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 9780 return err; 9781 } 9782 9783 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || 9784 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 9785 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n"); 9786 err = -ENODEV; 9787 goto err_out_disable_pdev; 9788 } 9789 9790 err = pci_request_regions(pdev, DRV_MODULE_NAME); 9791 if (err) { 9792 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 9793 goto err_out_disable_pdev; 9794 } 9795 9796 pos = pci_pcie_cap(pdev); 9797 if (pos <= 0) { 9798 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n"); 9799 goto err_out_free_res; 9800 } 9801 9802 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL, 9803 &niu_pci_ops, PCI_FUNC(pdev->devfn)); 9804 if (!dev) { 9805 err = -ENOMEM; 9806 goto err_out_free_res; 9807 } 9808 np = netdev_priv(dev); 9809 9810 memset(&parent_id, 0, sizeof(parent_id)); 9811 parent_id.pci.domain = pci_domain_nr(pdev->bus); 9812 parent_id.pci.bus = pdev->bus->number; 9813 parent_id.pci.device = PCI_SLOT(pdev->devfn); 9814 9815 np->parent = niu_get_parent(np, &parent_id, 9816 PLAT_TYPE_ATLAS); 9817 if (!np->parent) { 9818 err = -ENOMEM; 9819 goto err_out_free_dev; 9820 } 9821 9822 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16); 9823 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN; 9824 val16 |= (PCI_EXP_DEVCTL_CERE | 9825 PCI_EXP_DEVCTL_NFERE | 9826 PCI_EXP_DEVCTL_FERE | 9827 PCI_EXP_DEVCTL_URRE | 9828 PCI_EXP_DEVCTL_RELAX_EN); 9829 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16); 9830 9831 dma_mask = DMA_BIT_MASK(44); 9832 err = pci_set_dma_mask(pdev, dma_mask); 9833 if (!err) { 9834 dev->features |= NETIF_F_HIGHDMA; 9835 err = pci_set_consistent_dma_mask(pdev, dma_mask); 9836 if (err) { 9837 dev_err(&pdev->dev, "Unable to obtain 44 bit DMA for consistent allocations, aborting\n"); 9838 goto err_out_release_parent; 9839 } 9840 } 9841 if (err || dma_mask == DMA_BIT_MASK(32)) { 9842 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); 9843 if (err) { 9844 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 9845 goto err_out_release_parent; 9846 } 9847 } 9848 9849 niu_set_basic_features(dev); 9850 9851 dev->priv_flags |= IFF_UNICAST_FLT; 9852 9853 np->regs = pci_ioremap_bar(pdev, 0); 9854 if (!np->regs) { 9855 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 9856 err = -ENOMEM; 9857 goto err_out_release_parent; 9858 } 9859 9860 pci_set_master(pdev); 9861 pci_save_state(pdev); 9862 9863 dev->irq = pdev->irq; 9864 9865 niu_assign_netdev_ops(dev); 9866 9867 err = niu_get_invariants(np); 9868 if (err) { 9869 if (err != -ENODEV) 9870 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n"); 9871 goto err_out_iounmap; 9872 } 9873 9874 err = register_netdev(dev); 9875 if (err) { 9876 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); 9877 goto err_out_iounmap; 9878 } 9879 9880 pci_set_drvdata(pdev, dev); 9881 9882 niu_device_announce(np); 9883 9884 return 0; 9885 9886 err_out_iounmap: 9887 if (np->regs) { 9888 iounmap(np->regs); 9889 np->regs = NULL; 9890 } 9891 9892 err_out_release_parent: 9893 niu_put_parent(np); 9894 9895 err_out_free_dev: 9896 free_netdev(dev); 9897 9898 err_out_free_res: 9899 pci_release_regions(pdev); 9900 9901 err_out_disable_pdev: 9902 pci_disable_device(pdev); 9903 pci_set_drvdata(pdev, NULL); 9904 9905 return err; 9906 } 9907 9908 static void __devexit niu_pci_remove_one(struct pci_dev *pdev) 9909 { 9910 struct net_device *dev = pci_get_drvdata(pdev); 9911 9912 if (dev) { 9913 struct niu *np = netdev_priv(dev); 9914 9915 unregister_netdev(dev); 9916 if (np->regs) { 9917 iounmap(np->regs); 9918 np->regs = NULL; 9919 } 9920 9921 niu_ldg_free(np); 9922 9923 niu_put_parent(np); 9924 9925 free_netdev(dev); 9926 pci_release_regions(pdev); 9927 pci_disable_device(pdev); 9928 pci_set_drvdata(pdev, NULL); 9929 } 9930 } 9931 9932 static int niu_suspend(struct pci_dev *pdev, pm_message_t state) 9933 { 9934 struct net_device *dev = pci_get_drvdata(pdev); 9935 struct niu *np = netdev_priv(dev); 9936 unsigned long flags; 9937 9938 if (!netif_running(dev)) 9939 return 0; 9940 9941 flush_work_sync(&np->reset_task); 9942 niu_netif_stop(np); 9943 9944 del_timer_sync(&np->timer); 9945 9946 spin_lock_irqsave(&np->lock, flags); 9947 niu_enable_interrupts(np, 0); 9948 spin_unlock_irqrestore(&np->lock, flags); 9949 9950 netif_device_detach(dev); 9951 9952 spin_lock_irqsave(&np->lock, flags); 9953 niu_stop_hw(np); 9954 spin_unlock_irqrestore(&np->lock, flags); 9955 9956 pci_save_state(pdev); 9957 9958 return 0; 9959 } 9960 9961 static int niu_resume(struct pci_dev *pdev) 9962 { 9963 struct net_device *dev = pci_get_drvdata(pdev); 9964 struct niu *np = netdev_priv(dev); 9965 unsigned long flags; 9966 int err; 9967 9968 if (!netif_running(dev)) 9969 return 0; 9970 9971 pci_restore_state(pdev); 9972 9973 netif_device_attach(dev); 9974 9975 spin_lock_irqsave(&np->lock, flags); 9976 9977 err = niu_init_hw(np); 9978 if (!err) { 9979 np->timer.expires = jiffies + HZ; 9980 add_timer(&np->timer); 9981 niu_netif_start(np); 9982 } 9983 9984 spin_unlock_irqrestore(&np->lock, flags); 9985 9986 return err; 9987 } 9988 9989 static struct pci_driver niu_pci_driver = { 9990 .name = DRV_MODULE_NAME, 9991 .id_table = niu_pci_tbl, 9992 .probe = niu_pci_init_one, 9993 .remove = __devexit_p(niu_pci_remove_one), 9994 .suspend = niu_suspend, 9995 .resume = niu_resume, 9996 }; 9997 9998 #ifdef CONFIG_SPARC64 9999 static void *niu_phys_alloc_coherent(struct device *dev, size_t size, 10000 u64 *dma_addr, gfp_t flag) 10001 { 10002 unsigned long order = get_order(size); 10003 unsigned long page = __get_free_pages(flag, order); 10004 10005 if (page == 0UL) 10006 return NULL; 10007 memset((char *)page, 0, PAGE_SIZE << order); 10008 *dma_addr = __pa(page); 10009 10010 return (void *) page; 10011 } 10012 10013 static void niu_phys_free_coherent(struct device *dev, size_t size, 10014 void *cpu_addr, u64 handle) 10015 { 10016 unsigned long order = get_order(size); 10017 10018 free_pages((unsigned long) cpu_addr, order); 10019 } 10020 10021 static u64 niu_phys_map_page(struct device *dev, struct page *page, 10022 unsigned long offset, size_t size, 10023 enum dma_data_direction direction) 10024 { 10025 return page_to_phys(page) + offset; 10026 } 10027 10028 static void niu_phys_unmap_page(struct device *dev, u64 dma_address, 10029 size_t size, enum dma_data_direction direction) 10030 { 10031 /* Nothing to do. */ 10032 } 10033 10034 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr, 10035 size_t size, 10036 enum dma_data_direction direction) 10037 { 10038 return __pa(cpu_addr); 10039 } 10040 10041 static void niu_phys_unmap_single(struct device *dev, u64 dma_address, 10042 size_t size, 10043 enum dma_data_direction direction) 10044 { 10045 /* Nothing to do. */ 10046 } 10047 10048 static const struct niu_ops niu_phys_ops = { 10049 .alloc_coherent = niu_phys_alloc_coherent, 10050 .free_coherent = niu_phys_free_coherent, 10051 .map_page = niu_phys_map_page, 10052 .unmap_page = niu_phys_unmap_page, 10053 .map_single = niu_phys_map_single, 10054 .unmap_single = niu_phys_unmap_single, 10055 }; 10056 10057 static int __devinit niu_of_probe(struct platform_device *op) 10058 { 10059 union niu_parent_id parent_id; 10060 struct net_device *dev; 10061 struct niu *np; 10062 const u32 *reg; 10063 int err; 10064 10065 niu_driver_version(); 10066 10067 reg = of_get_property(op->dev.of_node, "reg", NULL); 10068 if (!reg) { 10069 dev_err(&op->dev, "%s: No 'reg' property, aborting\n", 10070 op->dev.of_node->full_name); 10071 return -ENODEV; 10072 } 10073 10074 dev = niu_alloc_and_init(&op->dev, NULL, op, 10075 &niu_phys_ops, reg[0] & 0x1); 10076 if (!dev) { 10077 err = -ENOMEM; 10078 goto err_out; 10079 } 10080 np = netdev_priv(dev); 10081 10082 memset(&parent_id, 0, sizeof(parent_id)); 10083 parent_id.of = of_get_parent(op->dev.of_node); 10084 10085 np->parent = niu_get_parent(np, &parent_id, 10086 PLAT_TYPE_NIU); 10087 if (!np->parent) { 10088 err = -ENOMEM; 10089 goto err_out_free_dev; 10090 } 10091 10092 niu_set_basic_features(dev); 10093 10094 np->regs = of_ioremap(&op->resource[1], 0, 10095 resource_size(&op->resource[1]), 10096 "niu regs"); 10097 if (!np->regs) { 10098 dev_err(&op->dev, "Cannot map device registers, aborting\n"); 10099 err = -ENOMEM; 10100 goto err_out_release_parent; 10101 } 10102 10103 np->vir_regs_1 = of_ioremap(&op->resource[2], 0, 10104 resource_size(&op->resource[2]), 10105 "niu vregs-1"); 10106 if (!np->vir_regs_1) { 10107 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n"); 10108 err = -ENOMEM; 10109 goto err_out_iounmap; 10110 } 10111 10112 np->vir_regs_2 = of_ioremap(&op->resource[3], 0, 10113 resource_size(&op->resource[3]), 10114 "niu vregs-2"); 10115 if (!np->vir_regs_2) { 10116 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n"); 10117 err = -ENOMEM; 10118 goto err_out_iounmap; 10119 } 10120 10121 niu_assign_netdev_ops(dev); 10122 10123 err = niu_get_invariants(np); 10124 if (err) { 10125 if (err != -ENODEV) 10126 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n"); 10127 goto err_out_iounmap; 10128 } 10129 10130 err = register_netdev(dev); 10131 if (err) { 10132 dev_err(&op->dev, "Cannot register net device, aborting\n"); 10133 goto err_out_iounmap; 10134 } 10135 10136 dev_set_drvdata(&op->dev, dev); 10137 10138 niu_device_announce(np); 10139 10140 return 0; 10141 10142 err_out_iounmap: 10143 if (np->vir_regs_1) { 10144 of_iounmap(&op->resource[2], np->vir_regs_1, 10145 resource_size(&op->resource[2])); 10146 np->vir_regs_1 = NULL; 10147 } 10148 10149 if (np->vir_regs_2) { 10150 of_iounmap(&op->resource[3], np->vir_regs_2, 10151 resource_size(&op->resource[3])); 10152 np->vir_regs_2 = NULL; 10153 } 10154 10155 if (np->regs) { 10156 of_iounmap(&op->resource[1], np->regs, 10157 resource_size(&op->resource[1])); 10158 np->regs = NULL; 10159 } 10160 10161 err_out_release_parent: 10162 niu_put_parent(np); 10163 10164 err_out_free_dev: 10165 free_netdev(dev); 10166 10167 err_out: 10168 return err; 10169 } 10170 10171 static int __devexit niu_of_remove(struct platform_device *op) 10172 { 10173 struct net_device *dev = dev_get_drvdata(&op->dev); 10174 10175 if (dev) { 10176 struct niu *np = netdev_priv(dev); 10177 10178 unregister_netdev(dev); 10179 10180 if (np->vir_regs_1) { 10181 of_iounmap(&op->resource[2], np->vir_regs_1, 10182 resource_size(&op->resource[2])); 10183 np->vir_regs_1 = NULL; 10184 } 10185 10186 if (np->vir_regs_2) { 10187 of_iounmap(&op->resource[3], np->vir_regs_2, 10188 resource_size(&op->resource[3])); 10189 np->vir_regs_2 = NULL; 10190 } 10191 10192 if (np->regs) { 10193 of_iounmap(&op->resource[1], np->regs, 10194 resource_size(&op->resource[1])); 10195 np->regs = NULL; 10196 } 10197 10198 niu_ldg_free(np); 10199 10200 niu_put_parent(np); 10201 10202 free_netdev(dev); 10203 dev_set_drvdata(&op->dev, NULL); 10204 } 10205 return 0; 10206 } 10207 10208 static const struct of_device_id niu_match[] = { 10209 { 10210 .name = "network", 10211 .compatible = "SUNW,niusl", 10212 }, 10213 {}, 10214 }; 10215 MODULE_DEVICE_TABLE(of, niu_match); 10216 10217 static struct platform_driver niu_of_driver = { 10218 .driver = { 10219 .name = "niu", 10220 .owner = THIS_MODULE, 10221 .of_match_table = niu_match, 10222 }, 10223 .probe = niu_of_probe, 10224 .remove = __devexit_p(niu_of_remove), 10225 }; 10226 10227 #endif /* CONFIG_SPARC64 */ 10228 10229 static int __init niu_init(void) 10230 { 10231 int err = 0; 10232 10233 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024); 10234 10235 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT); 10236 10237 #ifdef CONFIG_SPARC64 10238 err = platform_driver_register(&niu_of_driver); 10239 #endif 10240 10241 if (!err) { 10242 err = pci_register_driver(&niu_pci_driver); 10243 #ifdef CONFIG_SPARC64 10244 if (err) 10245 platform_driver_unregister(&niu_of_driver); 10246 #endif 10247 } 10248 10249 return err; 10250 } 10251 10252 static void __exit niu_exit(void) 10253 { 10254 pci_unregister_driver(&niu_pci_driver); 10255 #ifdef CONFIG_SPARC64 10256 platform_driver_unregister(&niu_of_driver); 10257 #endif 10258 } 10259 10260 module_init(niu_init); 10261 module_exit(niu_exit); 10262