1 // SPDX-License-Identifier: GPL-2.0 2 /* niu.c: Neptune ethernet driver. 3 * 4 * Copyright (C) 2007, 2008 David S. Miller (davem@davemloft.net) 5 */ 6 7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 8 9 #include <linux/module.h> 10 #include <linux/init.h> 11 #include <linux/interrupt.h> 12 #include <linux/pci.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/netdevice.h> 15 #include <linux/ethtool.h> 16 #include <linux/etherdevice.h> 17 #include <linux/platform_device.h> 18 #include <linux/delay.h> 19 #include <linux/bitops.h> 20 #include <linux/mii.h> 21 #include <linux/if.h> 22 #include <linux/if_ether.h> 23 #include <linux/if_vlan.h> 24 #include <linux/ip.h> 25 #include <linux/in.h> 26 #include <linux/ipv6.h> 27 #include <linux/log2.h> 28 #include <linux/jiffies.h> 29 #include <linux/crc32.h> 30 #include <linux/list.h> 31 #include <linux/slab.h> 32 33 #include <linux/io.h> 34 #include <linux/of.h> 35 36 #include "niu.h" 37 38 /* This driver wants to store a link to a "next page" within the 39 * page struct itself by overloading the content of the "mapping" 40 * member. This is not expected by the page API, but does currently 41 * work. However, the randstruct plugin gets very bothered by this 42 * case because "mapping" (struct address_space) is randomized, so 43 * casts to/from it trigger warnings. Hide this by way of a union, 44 * to create a typed alias of "mapping", since that's how it is 45 * actually being used here. 46 */ 47 union niu_page { 48 struct page page; 49 struct { 50 unsigned long __flags; /* unused alias of "flags" */ 51 struct list_head __lru; /* unused alias of "lru" */ 52 struct page *next; /* alias of "mapping" */ 53 }; 54 }; 55 #define niu_next_page(p) container_of(p, union niu_page, page)->next 56 57 #define DRV_MODULE_NAME "niu" 58 #define DRV_MODULE_VERSION "1.1" 59 #define DRV_MODULE_RELDATE "Apr 22, 2010" 60 61 static char version[] = 62 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 63 64 MODULE_AUTHOR("David S. Miller <davem@davemloft.net>"); 65 MODULE_DESCRIPTION("NIU ethernet driver"); 66 MODULE_LICENSE("GPL"); 67 MODULE_VERSION(DRV_MODULE_VERSION); 68 69 #ifndef readq 70 static u64 readq(void __iomem *reg) 71 { 72 return ((u64) readl(reg)) | (((u64) readl(reg + 4UL)) << 32); 73 } 74 75 static void writeq(u64 val, void __iomem *reg) 76 { 77 writel(val & 0xffffffff, reg); 78 writel(val >> 32, reg + 0x4UL); 79 } 80 #endif 81 82 static const struct pci_device_id niu_pci_tbl[] = { 83 {PCI_DEVICE(PCI_VENDOR_ID_SUN, 0xabcd)}, 84 {} 85 }; 86 87 MODULE_DEVICE_TABLE(pci, niu_pci_tbl); 88 89 #define NIU_TX_TIMEOUT (5 * HZ) 90 91 #define nr64(reg) readq(np->regs + (reg)) 92 #define nw64(reg, val) writeq((val), np->regs + (reg)) 93 94 #define nr64_mac(reg) readq(np->mac_regs + (reg)) 95 #define nw64_mac(reg, val) writeq((val), np->mac_regs + (reg)) 96 97 #define nr64_ipp(reg) readq(np->regs + np->ipp_off + (reg)) 98 #define nw64_ipp(reg, val) writeq((val), np->regs + np->ipp_off + (reg)) 99 100 #define nr64_pcs(reg) readq(np->regs + np->pcs_off + (reg)) 101 #define nw64_pcs(reg, val) writeq((val), np->regs + np->pcs_off + (reg)) 102 103 #define nr64_xpcs(reg) readq(np->regs + np->xpcs_off + (reg)) 104 #define nw64_xpcs(reg, val) writeq((val), np->regs + np->xpcs_off + (reg)) 105 106 #define NIU_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK) 107 108 static int niu_debug; 109 static int debug = -1; 110 module_param(debug, int, 0); 111 MODULE_PARM_DESC(debug, "NIU debug level"); 112 113 #define niu_lock_parent(np, flags) \ 114 spin_lock_irqsave(&np->parent->lock, flags) 115 #define niu_unlock_parent(np, flags) \ 116 spin_unlock_irqrestore(&np->parent->lock, flags) 117 118 static int serdes_init_10g_serdes(struct niu *np); 119 120 static int __niu_wait_bits_clear_mac(struct niu *np, unsigned long reg, 121 u64 bits, int limit, int delay) 122 { 123 while (--limit >= 0) { 124 u64 val = nr64_mac(reg); 125 126 if (!(val & bits)) 127 break; 128 udelay(delay); 129 } 130 if (limit < 0) 131 return -ENODEV; 132 return 0; 133 } 134 135 static int __niu_set_and_wait_clear_mac(struct niu *np, unsigned long reg, 136 u64 bits, int limit, int delay, 137 const char *reg_name) 138 { 139 int err; 140 141 nw64_mac(reg, bits); 142 err = __niu_wait_bits_clear_mac(np, reg, bits, limit, delay); 143 if (err) 144 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 145 (unsigned long long)bits, reg_name, 146 (unsigned long long)nr64_mac(reg)); 147 return err; 148 } 149 150 #define niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 151 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 152 __niu_set_and_wait_clear_mac(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 153 }) 154 155 static int __niu_wait_bits_clear_ipp(struct niu *np, unsigned long reg, 156 u64 bits, int limit, int delay) 157 { 158 while (--limit >= 0) { 159 u64 val = nr64_ipp(reg); 160 161 if (!(val & bits)) 162 break; 163 udelay(delay); 164 } 165 if (limit < 0) 166 return -ENODEV; 167 return 0; 168 } 169 170 static int __niu_set_and_wait_clear_ipp(struct niu *np, unsigned long reg, 171 u64 bits, int limit, int delay, 172 const char *reg_name) 173 { 174 int err; 175 u64 val; 176 177 val = nr64_ipp(reg); 178 val |= bits; 179 nw64_ipp(reg, val); 180 181 err = __niu_wait_bits_clear_ipp(np, reg, bits, limit, delay); 182 if (err) 183 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 184 (unsigned long long)bits, reg_name, 185 (unsigned long long)nr64_ipp(reg)); 186 return err; 187 } 188 189 #define niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 190 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 191 __niu_set_and_wait_clear_ipp(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 192 }) 193 194 static int __niu_wait_bits_clear(struct niu *np, unsigned long reg, 195 u64 bits, int limit, int delay) 196 { 197 while (--limit >= 0) { 198 u64 val = nr64(reg); 199 200 if (!(val & bits)) 201 break; 202 udelay(delay); 203 } 204 if (limit < 0) 205 return -ENODEV; 206 return 0; 207 } 208 209 #define niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY) \ 210 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 211 __niu_wait_bits_clear(NP, REG, BITS, LIMIT, DELAY); \ 212 }) 213 214 static int __niu_set_and_wait_clear(struct niu *np, unsigned long reg, 215 u64 bits, int limit, int delay, 216 const char *reg_name) 217 { 218 int err; 219 220 nw64(reg, bits); 221 err = __niu_wait_bits_clear(np, reg, bits, limit, delay); 222 if (err) 223 netdev_err(np->dev, "bits (%llx) of register %s would not clear, val[%llx]\n", 224 (unsigned long long)bits, reg_name, 225 (unsigned long long)nr64(reg)); 226 return err; 227 } 228 229 #define niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME) \ 230 ({ BUILD_BUG_ON(LIMIT <= 0 || DELAY < 0); \ 231 __niu_set_and_wait_clear(NP, REG, BITS, LIMIT, DELAY, REG_NAME); \ 232 }) 233 234 static void niu_ldg_rearm(struct niu *np, struct niu_ldg *lp, int on) 235 { 236 u64 val = (u64) lp->timer; 237 238 if (on) 239 val |= LDG_IMGMT_ARM; 240 241 nw64(LDG_IMGMT(lp->ldg_num), val); 242 } 243 244 static int niu_ldn_irq_enable(struct niu *np, int ldn, int on) 245 { 246 unsigned long mask_reg, bits; 247 u64 val; 248 249 if (ldn < 0 || ldn > LDN_MAX) 250 return -EINVAL; 251 252 if (ldn < 64) { 253 mask_reg = LD_IM0(ldn); 254 bits = LD_IM0_MASK; 255 } else { 256 mask_reg = LD_IM1(ldn - 64); 257 bits = LD_IM1_MASK; 258 } 259 260 val = nr64(mask_reg); 261 if (on) 262 val &= ~bits; 263 else 264 val |= bits; 265 nw64(mask_reg, val); 266 267 return 0; 268 } 269 270 static int niu_enable_ldn_in_ldg(struct niu *np, struct niu_ldg *lp, int on) 271 { 272 struct niu_parent *parent = np->parent; 273 int i; 274 275 for (i = 0; i <= LDN_MAX; i++) { 276 int err; 277 278 if (parent->ldg_map[i] != lp->ldg_num) 279 continue; 280 281 err = niu_ldn_irq_enable(np, i, on); 282 if (err) 283 return err; 284 } 285 return 0; 286 } 287 288 static int niu_enable_interrupts(struct niu *np, int on) 289 { 290 int i; 291 292 for (i = 0; i < np->num_ldg; i++) { 293 struct niu_ldg *lp = &np->ldg[i]; 294 int err; 295 296 err = niu_enable_ldn_in_ldg(np, lp, on); 297 if (err) 298 return err; 299 } 300 for (i = 0; i < np->num_ldg; i++) 301 niu_ldg_rearm(np, &np->ldg[i], on); 302 303 return 0; 304 } 305 306 static u32 phy_encode(u32 type, int port) 307 { 308 return type << (port * 2); 309 } 310 311 static u32 phy_decode(u32 val, int port) 312 { 313 return (val >> (port * 2)) & PORT_TYPE_MASK; 314 } 315 316 static int mdio_wait(struct niu *np) 317 { 318 int limit = 1000; 319 u64 val; 320 321 while (--limit > 0) { 322 val = nr64(MIF_FRAME_OUTPUT); 323 if ((val >> MIF_FRAME_OUTPUT_TA_SHIFT) & 0x1) 324 return val & MIF_FRAME_OUTPUT_DATA; 325 326 udelay(10); 327 } 328 329 return -ENODEV; 330 } 331 332 static int mdio_read(struct niu *np, int port, int dev, int reg) 333 { 334 int err; 335 336 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 337 err = mdio_wait(np); 338 if (err < 0) 339 return err; 340 341 nw64(MIF_FRAME_OUTPUT, MDIO_READ_OP(port, dev)); 342 return mdio_wait(np); 343 } 344 345 static int mdio_write(struct niu *np, int port, int dev, int reg, int data) 346 { 347 int err; 348 349 nw64(MIF_FRAME_OUTPUT, MDIO_ADDR_OP(port, dev, reg)); 350 err = mdio_wait(np); 351 if (err < 0) 352 return err; 353 354 nw64(MIF_FRAME_OUTPUT, MDIO_WRITE_OP(port, dev, data)); 355 err = mdio_wait(np); 356 if (err < 0) 357 return err; 358 359 return 0; 360 } 361 362 static int mii_read(struct niu *np, int port, int reg) 363 { 364 nw64(MIF_FRAME_OUTPUT, MII_READ_OP(port, reg)); 365 return mdio_wait(np); 366 } 367 368 static int mii_write(struct niu *np, int port, int reg, int data) 369 { 370 int err; 371 372 nw64(MIF_FRAME_OUTPUT, MII_WRITE_OP(port, reg, data)); 373 err = mdio_wait(np); 374 if (err < 0) 375 return err; 376 377 return 0; 378 } 379 380 static int esr2_set_tx_cfg(struct niu *np, unsigned long channel, u32 val) 381 { 382 int err; 383 384 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 385 ESR2_TI_PLL_TX_CFG_L(channel), 386 val & 0xffff); 387 if (!err) 388 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 389 ESR2_TI_PLL_TX_CFG_H(channel), 390 val >> 16); 391 return err; 392 } 393 394 static int esr2_set_rx_cfg(struct niu *np, unsigned long channel, u32 val) 395 { 396 int err; 397 398 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 399 ESR2_TI_PLL_RX_CFG_L(channel), 400 val & 0xffff); 401 if (!err) 402 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 403 ESR2_TI_PLL_RX_CFG_H(channel), 404 val >> 16); 405 return err; 406 } 407 408 /* Mode is always 10G fiber. */ 409 static int serdes_init_niu_10g_fiber(struct niu *np) 410 { 411 struct niu_link_config *lp = &np->link_config; 412 u32 tx_cfg, rx_cfg; 413 unsigned long i; 414 415 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 416 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 417 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 418 PLL_RX_CFG_EQ_LP_ADAPTIVE); 419 420 if (lp->loopback_mode == LOOPBACK_PHY) { 421 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 422 423 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 424 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 425 426 tx_cfg |= PLL_TX_CFG_ENTEST; 427 rx_cfg |= PLL_RX_CFG_ENTEST; 428 } 429 430 /* Initialize all 4 lanes of the SERDES. */ 431 for (i = 0; i < 4; i++) { 432 int err = esr2_set_tx_cfg(np, i, tx_cfg); 433 if (err) 434 return err; 435 } 436 437 for (i = 0; i < 4; i++) { 438 int err = esr2_set_rx_cfg(np, i, rx_cfg); 439 if (err) 440 return err; 441 } 442 443 return 0; 444 } 445 446 static int serdes_init_niu_1g_serdes(struct niu *np) 447 { 448 struct niu_link_config *lp = &np->link_config; 449 u16 pll_cfg, pll_sts; 450 int max_retry = 100; 451 u64 sig, mask, val; 452 u32 tx_cfg, rx_cfg; 453 unsigned long i; 454 int err; 455 456 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV | 457 PLL_TX_CFG_RATE_HALF); 458 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 459 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 460 PLL_RX_CFG_RATE_HALF); 461 462 if (np->port == 0) 463 rx_cfg |= PLL_RX_CFG_EQ_LP_ADAPTIVE; 464 465 if (lp->loopback_mode == LOOPBACK_PHY) { 466 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 467 468 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 469 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 470 471 tx_cfg |= PLL_TX_CFG_ENTEST; 472 rx_cfg |= PLL_RX_CFG_ENTEST; 473 } 474 475 /* Initialize PLL for 1G */ 476 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_8X); 477 478 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 479 ESR2_TI_PLL_CFG_L, pll_cfg); 480 if (err) { 481 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 482 np->port, __func__); 483 return err; 484 } 485 486 pll_sts = PLL_CFG_ENPLL; 487 488 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 489 ESR2_TI_PLL_STS_L, pll_sts); 490 if (err) { 491 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 492 np->port, __func__); 493 return err; 494 } 495 496 udelay(200); 497 498 /* Initialize all 4 lanes of the SERDES. */ 499 for (i = 0; i < 4; i++) { 500 err = esr2_set_tx_cfg(np, i, tx_cfg); 501 if (err) 502 return err; 503 } 504 505 for (i = 0; i < 4; i++) { 506 err = esr2_set_rx_cfg(np, i, rx_cfg); 507 if (err) 508 return err; 509 } 510 511 switch (np->port) { 512 case 0: 513 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 514 mask = val; 515 break; 516 517 case 1: 518 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 519 mask = val; 520 break; 521 522 default: 523 return -EINVAL; 524 } 525 526 while (max_retry--) { 527 sig = nr64(ESR_INT_SIGNALS); 528 if ((sig & mask) == val) 529 break; 530 531 mdelay(500); 532 } 533 534 if ((sig & mask) != val) { 535 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 536 np->port, (int)(sig & mask), (int)val); 537 return -ENODEV; 538 } 539 540 return 0; 541 } 542 543 static int serdes_init_niu_10g_serdes(struct niu *np) 544 { 545 struct niu_link_config *lp = &np->link_config; 546 u32 tx_cfg, rx_cfg, pll_cfg, pll_sts; 547 int max_retry = 100; 548 u64 sig, mask, val; 549 unsigned long i; 550 int err; 551 552 tx_cfg = (PLL_TX_CFG_ENTX | PLL_TX_CFG_SWING_1375MV); 553 rx_cfg = (PLL_RX_CFG_ENRX | PLL_RX_CFG_TERM_0P8VDDT | 554 PLL_RX_CFG_ALIGN_ENA | PLL_RX_CFG_LOS_LTHRESH | 555 PLL_RX_CFG_EQ_LP_ADAPTIVE); 556 557 if (lp->loopback_mode == LOOPBACK_PHY) { 558 u16 test_cfg = PLL_TEST_CFG_LOOPBACK_CML_DIS; 559 560 mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 561 ESR2_TI_PLL_TEST_CFG_L, test_cfg); 562 563 tx_cfg |= PLL_TX_CFG_ENTEST; 564 rx_cfg |= PLL_RX_CFG_ENTEST; 565 } 566 567 /* Initialize PLL for 10G */ 568 pll_cfg = (PLL_CFG_ENPLL | PLL_CFG_MPY_10X); 569 570 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 571 ESR2_TI_PLL_CFG_L, pll_cfg & 0xffff); 572 if (err) { 573 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_CFG_L failed\n", 574 np->port, __func__); 575 return err; 576 } 577 578 pll_sts = PLL_CFG_ENPLL; 579 580 err = mdio_write(np, np->port, NIU_ESR2_DEV_ADDR, 581 ESR2_TI_PLL_STS_L, pll_sts & 0xffff); 582 if (err) { 583 netdev_err(np->dev, "NIU Port %d %s() mdio write to ESR2_TI_PLL_STS_L failed\n", 584 np->port, __func__); 585 return err; 586 } 587 588 udelay(200); 589 590 /* Initialize all 4 lanes of the SERDES. */ 591 for (i = 0; i < 4; i++) { 592 err = esr2_set_tx_cfg(np, i, tx_cfg); 593 if (err) 594 return err; 595 } 596 597 for (i = 0; i < 4; i++) { 598 err = esr2_set_rx_cfg(np, i, rx_cfg); 599 if (err) 600 return err; 601 } 602 603 /* check if serdes is ready */ 604 605 switch (np->port) { 606 case 0: 607 mask = ESR_INT_SIGNALS_P0_BITS; 608 val = (ESR_INT_SRDY0_P0 | 609 ESR_INT_DET0_P0 | 610 ESR_INT_XSRDY_P0 | 611 ESR_INT_XDP_P0_CH3 | 612 ESR_INT_XDP_P0_CH2 | 613 ESR_INT_XDP_P0_CH1 | 614 ESR_INT_XDP_P0_CH0); 615 break; 616 617 case 1: 618 mask = ESR_INT_SIGNALS_P1_BITS; 619 val = (ESR_INT_SRDY0_P1 | 620 ESR_INT_DET0_P1 | 621 ESR_INT_XSRDY_P1 | 622 ESR_INT_XDP_P1_CH3 | 623 ESR_INT_XDP_P1_CH2 | 624 ESR_INT_XDP_P1_CH1 | 625 ESR_INT_XDP_P1_CH0); 626 break; 627 628 default: 629 return -EINVAL; 630 } 631 632 while (max_retry--) { 633 sig = nr64(ESR_INT_SIGNALS); 634 if ((sig & mask) == val) 635 break; 636 637 mdelay(500); 638 } 639 640 if ((sig & mask) != val) { 641 pr_info("NIU Port %u signal bits [%08x] are not [%08x] for 10G...trying 1G\n", 642 np->port, (int)(sig & mask), (int)val); 643 644 /* 10G failed, try initializing at 1G */ 645 err = serdes_init_niu_1g_serdes(np); 646 if (!err) { 647 np->flags &= ~NIU_FLAGS_10G; 648 np->mac_xcvr = MAC_XCVR_PCS; 649 } else { 650 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 651 np->port); 652 return -ENODEV; 653 } 654 } 655 return 0; 656 } 657 658 static int esr_read_rxtx_ctrl(struct niu *np, unsigned long chan, u32 *val) 659 { 660 int err; 661 662 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, ESR_RXTX_CTRL_L(chan)); 663 if (err >= 0) { 664 *val = (err & 0xffff); 665 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 666 ESR_RXTX_CTRL_H(chan)); 667 if (err >= 0) 668 *val |= ((err & 0xffff) << 16); 669 err = 0; 670 } 671 return err; 672 } 673 674 static int esr_read_glue0(struct niu *np, unsigned long chan, u32 *val) 675 { 676 int err; 677 678 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 679 ESR_GLUE_CTRL0_L(chan)); 680 if (err >= 0) { 681 *val = (err & 0xffff); 682 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 683 ESR_GLUE_CTRL0_H(chan)); 684 if (err >= 0) { 685 *val |= ((err & 0xffff) << 16); 686 err = 0; 687 } 688 } 689 return err; 690 } 691 692 static int esr_read_reset(struct niu *np, u32 *val) 693 { 694 int err; 695 696 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 697 ESR_RXTX_RESET_CTRL_L); 698 if (err >= 0) { 699 *val = (err & 0xffff); 700 err = mdio_read(np, np->port, NIU_ESR_DEV_ADDR, 701 ESR_RXTX_RESET_CTRL_H); 702 if (err >= 0) { 703 *val |= ((err & 0xffff) << 16); 704 err = 0; 705 } 706 } 707 return err; 708 } 709 710 static int esr_write_rxtx_ctrl(struct niu *np, unsigned long chan, u32 val) 711 { 712 int err; 713 714 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 715 ESR_RXTX_CTRL_L(chan), val & 0xffff); 716 if (!err) 717 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 718 ESR_RXTX_CTRL_H(chan), (val >> 16)); 719 return err; 720 } 721 722 static int esr_write_glue0(struct niu *np, unsigned long chan, u32 val) 723 { 724 int err; 725 726 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 727 ESR_GLUE_CTRL0_L(chan), val & 0xffff); 728 if (!err) 729 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 730 ESR_GLUE_CTRL0_H(chan), (val >> 16)); 731 return err; 732 } 733 734 static int esr_reset(struct niu *np) 735 { 736 u32 reset; 737 int err; 738 739 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 740 ESR_RXTX_RESET_CTRL_L, 0x0000); 741 if (err) 742 return err; 743 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 744 ESR_RXTX_RESET_CTRL_H, 0xffff); 745 if (err) 746 return err; 747 udelay(200); 748 749 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 750 ESR_RXTX_RESET_CTRL_L, 0xffff); 751 if (err) 752 return err; 753 udelay(200); 754 755 err = mdio_write(np, np->port, NIU_ESR_DEV_ADDR, 756 ESR_RXTX_RESET_CTRL_H, 0x0000); 757 if (err) 758 return err; 759 udelay(200); 760 761 err = esr_read_reset(np, &reset); 762 if (err) 763 return err; 764 if (reset != 0) { 765 netdev_err(np->dev, "Port %u ESR_RESET did not clear [%08x]\n", 766 np->port, reset); 767 return -ENODEV; 768 } 769 770 return 0; 771 } 772 773 static int serdes_init_10g(struct niu *np) 774 { 775 struct niu_link_config *lp = &np->link_config; 776 unsigned long ctrl_reg, test_cfg_reg, i; 777 u64 ctrl_val, test_cfg_val, sig, mask, val; 778 int err; 779 780 switch (np->port) { 781 case 0: 782 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 783 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 784 break; 785 case 1: 786 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 787 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 788 break; 789 790 default: 791 return -EINVAL; 792 } 793 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 794 ENET_SERDES_CTRL_SDET_1 | 795 ENET_SERDES_CTRL_SDET_2 | 796 ENET_SERDES_CTRL_SDET_3 | 797 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 798 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 799 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 800 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 801 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 802 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 803 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 804 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 805 test_cfg_val = 0; 806 807 if (lp->loopback_mode == LOOPBACK_PHY) { 808 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 809 ENET_SERDES_TEST_MD_0_SHIFT) | 810 (ENET_TEST_MD_PAD_LOOPBACK << 811 ENET_SERDES_TEST_MD_1_SHIFT) | 812 (ENET_TEST_MD_PAD_LOOPBACK << 813 ENET_SERDES_TEST_MD_2_SHIFT) | 814 (ENET_TEST_MD_PAD_LOOPBACK << 815 ENET_SERDES_TEST_MD_3_SHIFT)); 816 } 817 818 nw64(ctrl_reg, ctrl_val); 819 nw64(test_cfg_reg, test_cfg_val); 820 821 /* Initialize all 4 lanes of the SERDES. */ 822 for (i = 0; i < 4; i++) { 823 u32 rxtx_ctrl, glue0; 824 825 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 826 if (err) 827 return err; 828 err = esr_read_glue0(np, i, &glue0); 829 if (err) 830 return err; 831 832 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 833 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 834 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 835 836 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 837 ESR_GLUE_CTRL0_THCNT | 838 ESR_GLUE_CTRL0_BLTIME); 839 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 840 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 841 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 842 (BLTIME_300_CYCLES << 843 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 844 845 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 846 if (err) 847 return err; 848 err = esr_write_glue0(np, i, glue0); 849 if (err) 850 return err; 851 } 852 853 err = esr_reset(np); 854 if (err) 855 return err; 856 857 sig = nr64(ESR_INT_SIGNALS); 858 switch (np->port) { 859 case 0: 860 mask = ESR_INT_SIGNALS_P0_BITS; 861 val = (ESR_INT_SRDY0_P0 | 862 ESR_INT_DET0_P0 | 863 ESR_INT_XSRDY_P0 | 864 ESR_INT_XDP_P0_CH3 | 865 ESR_INT_XDP_P0_CH2 | 866 ESR_INT_XDP_P0_CH1 | 867 ESR_INT_XDP_P0_CH0); 868 break; 869 870 case 1: 871 mask = ESR_INT_SIGNALS_P1_BITS; 872 val = (ESR_INT_SRDY0_P1 | 873 ESR_INT_DET0_P1 | 874 ESR_INT_XSRDY_P1 | 875 ESR_INT_XDP_P1_CH3 | 876 ESR_INT_XDP_P1_CH2 | 877 ESR_INT_XDP_P1_CH1 | 878 ESR_INT_XDP_P1_CH0); 879 break; 880 881 default: 882 return -EINVAL; 883 } 884 885 if ((sig & mask) != val) { 886 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 887 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 888 return 0; 889 } 890 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 891 np->port, (int)(sig & mask), (int)val); 892 return -ENODEV; 893 } 894 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) 895 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 896 return 0; 897 } 898 899 static int serdes_init_1g(struct niu *np) 900 { 901 u64 val; 902 903 val = nr64(ENET_SERDES_1_PLL_CFG); 904 val &= ~ENET_SERDES_PLL_FBDIV2; 905 switch (np->port) { 906 case 0: 907 val |= ENET_SERDES_PLL_HRATE0; 908 break; 909 case 1: 910 val |= ENET_SERDES_PLL_HRATE1; 911 break; 912 case 2: 913 val |= ENET_SERDES_PLL_HRATE2; 914 break; 915 case 3: 916 val |= ENET_SERDES_PLL_HRATE3; 917 break; 918 default: 919 return -EINVAL; 920 } 921 nw64(ENET_SERDES_1_PLL_CFG, val); 922 923 return 0; 924 } 925 926 static int serdes_init_1g_serdes(struct niu *np) 927 { 928 struct niu_link_config *lp = &np->link_config; 929 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 930 u64 ctrl_val, test_cfg_val, sig, mask, val; 931 int err; 932 u64 reset_val, val_rd; 933 934 val = ENET_SERDES_PLL_HRATE0 | ENET_SERDES_PLL_HRATE1 | 935 ENET_SERDES_PLL_HRATE2 | ENET_SERDES_PLL_HRATE3 | 936 ENET_SERDES_PLL_FBDIV0; 937 switch (np->port) { 938 case 0: 939 reset_val = ENET_SERDES_RESET_0; 940 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 941 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 942 pll_cfg = ENET_SERDES_0_PLL_CFG; 943 break; 944 case 1: 945 reset_val = ENET_SERDES_RESET_1; 946 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 947 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 948 pll_cfg = ENET_SERDES_1_PLL_CFG; 949 break; 950 951 default: 952 return -EINVAL; 953 } 954 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 955 ENET_SERDES_CTRL_SDET_1 | 956 ENET_SERDES_CTRL_SDET_2 | 957 ENET_SERDES_CTRL_SDET_3 | 958 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 959 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 960 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 961 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 962 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 963 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 964 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 965 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 966 test_cfg_val = 0; 967 968 if (lp->loopback_mode == LOOPBACK_PHY) { 969 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 970 ENET_SERDES_TEST_MD_0_SHIFT) | 971 (ENET_TEST_MD_PAD_LOOPBACK << 972 ENET_SERDES_TEST_MD_1_SHIFT) | 973 (ENET_TEST_MD_PAD_LOOPBACK << 974 ENET_SERDES_TEST_MD_2_SHIFT) | 975 (ENET_TEST_MD_PAD_LOOPBACK << 976 ENET_SERDES_TEST_MD_3_SHIFT)); 977 } 978 979 nw64(ENET_SERDES_RESET, reset_val); 980 mdelay(20); 981 val_rd = nr64(ENET_SERDES_RESET); 982 val_rd &= ~reset_val; 983 nw64(pll_cfg, val); 984 nw64(ctrl_reg, ctrl_val); 985 nw64(test_cfg_reg, test_cfg_val); 986 nw64(ENET_SERDES_RESET, val_rd); 987 mdelay(2000); 988 989 /* Initialize all 4 lanes of the SERDES. */ 990 for (i = 0; i < 4; i++) { 991 u32 rxtx_ctrl, glue0; 992 993 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 994 if (err) 995 return err; 996 err = esr_read_glue0(np, i, &glue0); 997 if (err) 998 return err; 999 1000 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 1001 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 1002 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 1003 1004 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 1005 ESR_GLUE_CTRL0_THCNT | 1006 ESR_GLUE_CTRL0_BLTIME); 1007 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 1008 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 1009 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 1010 (BLTIME_300_CYCLES << 1011 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 1012 1013 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 1014 if (err) 1015 return err; 1016 err = esr_write_glue0(np, i, glue0); 1017 if (err) 1018 return err; 1019 } 1020 1021 1022 sig = nr64(ESR_INT_SIGNALS); 1023 switch (np->port) { 1024 case 0: 1025 val = (ESR_INT_SRDY0_P0 | ESR_INT_DET0_P0); 1026 mask = val; 1027 break; 1028 1029 case 1: 1030 val = (ESR_INT_SRDY0_P1 | ESR_INT_DET0_P1); 1031 mask = val; 1032 break; 1033 1034 default: 1035 return -EINVAL; 1036 } 1037 1038 if ((sig & mask) != val) { 1039 netdev_err(np->dev, "Port %u signal bits [%08x] are not [%08x]\n", 1040 np->port, (int)(sig & mask), (int)val); 1041 return -ENODEV; 1042 } 1043 1044 return 0; 1045 } 1046 1047 static int link_status_1g_serdes(struct niu *np, int *link_up_p) 1048 { 1049 struct niu_link_config *lp = &np->link_config; 1050 int link_up; 1051 u64 val; 1052 u16 current_speed; 1053 unsigned long flags; 1054 u8 current_duplex; 1055 1056 link_up = 0; 1057 current_speed = SPEED_INVALID; 1058 current_duplex = DUPLEX_INVALID; 1059 1060 spin_lock_irqsave(&np->lock, flags); 1061 1062 val = nr64_pcs(PCS_MII_STAT); 1063 1064 if (val & PCS_MII_STAT_LINK_STATUS) { 1065 link_up = 1; 1066 current_speed = SPEED_1000; 1067 current_duplex = DUPLEX_FULL; 1068 } 1069 1070 lp->active_speed = current_speed; 1071 lp->active_duplex = current_duplex; 1072 spin_unlock_irqrestore(&np->lock, flags); 1073 1074 *link_up_p = link_up; 1075 return 0; 1076 } 1077 1078 static int link_status_10g_serdes(struct niu *np, int *link_up_p) 1079 { 1080 unsigned long flags; 1081 struct niu_link_config *lp = &np->link_config; 1082 int link_up = 0; 1083 int link_ok = 1; 1084 u64 val, val2; 1085 u16 current_speed; 1086 u8 current_duplex; 1087 1088 if (!(np->flags & NIU_FLAGS_10G)) 1089 return link_status_1g_serdes(np, link_up_p); 1090 1091 current_speed = SPEED_INVALID; 1092 current_duplex = DUPLEX_INVALID; 1093 spin_lock_irqsave(&np->lock, flags); 1094 1095 val = nr64_xpcs(XPCS_STATUS(0)); 1096 val2 = nr64_mac(XMAC_INTER2); 1097 if (val2 & 0x01000000) 1098 link_ok = 0; 1099 1100 if ((val & 0x1000ULL) && link_ok) { 1101 link_up = 1; 1102 current_speed = SPEED_10000; 1103 current_duplex = DUPLEX_FULL; 1104 } 1105 lp->active_speed = current_speed; 1106 lp->active_duplex = current_duplex; 1107 spin_unlock_irqrestore(&np->lock, flags); 1108 *link_up_p = link_up; 1109 return 0; 1110 } 1111 1112 static int link_status_mii(struct niu *np, int *link_up_p) 1113 { 1114 struct niu_link_config *lp = &np->link_config; 1115 int err; 1116 int bmsr, advert, ctrl1000, stat1000, lpa, bmcr, estatus; 1117 int supported, advertising, active_speed, active_duplex; 1118 1119 err = mii_read(np, np->phy_addr, MII_BMCR); 1120 if (unlikely(err < 0)) 1121 return err; 1122 bmcr = err; 1123 1124 err = mii_read(np, np->phy_addr, MII_BMSR); 1125 if (unlikely(err < 0)) 1126 return err; 1127 bmsr = err; 1128 1129 err = mii_read(np, np->phy_addr, MII_ADVERTISE); 1130 if (unlikely(err < 0)) 1131 return err; 1132 advert = err; 1133 1134 err = mii_read(np, np->phy_addr, MII_LPA); 1135 if (unlikely(err < 0)) 1136 return err; 1137 lpa = err; 1138 1139 if (likely(bmsr & BMSR_ESTATEN)) { 1140 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1141 if (unlikely(err < 0)) 1142 return err; 1143 estatus = err; 1144 1145 err = mii_read(np, np->phy_addr, MII_CTRL1000); 1146 if (unlikely(err < 0)) 1147 return err; 1148 ctrl1000 = err; 1149 1150 err = mii_read(np, np->phy_addr, MII_STAT1000); 1151 if (unlikely(err < 0)) 1152 return err; 1153 stat1000 = err; 1154 } else 1155 estatus = ctrl1000 = stat1000 = 0; 1156 1157 supported = 0; 1158 if (bmsr & BMSR_ANEGCAPABLE) 1159 supported |= SUPPORTED_Autoneg; 1160 if (bmsr & BMSR_10HALF) 1161 supported |= SUPPORTED_10baseT_Half; 1162 if (bmsr & BMSR_10FULL) 1163 supported |= SUPPORTED_10baseT_Full; 1164 if (bmsr & BMSR_100HALF) 1165 supported |= SUPPORTED_100baseT_Half; 1166 if (bmsr & BMSR_100FULL) 1167 supported |= SUPPORTED_100baseT_Full; 1168 if (estatus & ESTATUS_1000_THALF) 1169 supported |= SUPPORTED_1000baseT_Half; 1170 if (estatus & ESTATUS_1000_TFULL) 1171 supported |= SUPPORTED_1000baseT_Full; 1172 lp->supported = supported; 1173 1174 advertising = mii_adv_to_ethtool_adv_t(advert); 1175 advertising |= mii_ctrl1000_to_ethtool_adv_t(ctrl1000); 1176 1177 if (bmcr & BMCR_ANENABLE) { 1178 int neg, neg1000; 1179 1180 lp->active_autoneg = 1; 1181 advertising |= ADVERTISED_Autoneg; 1182 1183 neg = advert & lpa; 1184 neg1000 = (ctrl1000 << 2) & stat1000; 1185 1186 if (neg1000 & (LPA_1000FULL | LPA_1000HALF)) 1187 active_speed = SPEED_1000; 1188 else if (neg & LPA_100) 1189 active_speed = SPEED_100; 1190 else if (neg & (LPA_10HALF | LPA_10FULL)) 1191 active_speed = SPEED_10; 1192 else 1193 active_speed = SPEED_INVALID; 1194 1195 if ((neg1000 & LPA_1000FULL) || (neg & LPA_DUPLEX)) 1196 active_duplex = DUPLEX_FULL; 1197 else if (active_speed != SPEED_INVALID) 1198 active_duplex = DUPLEX_HALF; 1199 else 1200 active_duplex = DUPLEX_INVALID; 1201 } else { 1202 lp->active_autoneg = 0; 1203 1204 if ((bmcr & BMCR_SPEED1000) && !(bmcr & BMCR_SPEED100)) 1205 active_speed = SPEED_1000; 1206 else if (bmcr & BMCR_SPEED100) 1207 active_speed = SPEED_100; 1208 else 1209 active_speed = SPEED_10; 1210 1211 if (bmcr & BMCR_FULLDPLX) 1212 active_duplex = DUPLEX_FULL; 1213 else 1214 active_duplex = DUPLEX_HALF; 1215 } 1216 1217 lp->active_advertising = advertising; 1218 lp->active_speed = active_speed; 1219 lp->active_duplex = active_duplex; 1220 *link_up_p = !!(bmsr & BMSR_LSTATUS); 1221 1222 return 0; 1223 } 1224 1225 static int link_status_1g_rgmii(struct niu *np, int *link_up_p) 1226 { 1227 struct niu_link_config *lp = &np->link_config; 1228 u16 current_speed, bmsr; 1229 unsigned long flags; 1230 u8 current_duplex; 1231 int err, link_up; 1232 1233 link_up = 0; 1234 current_speed = SPEED_INVALID; 1235 current_duplex = DUPLEX_INVALID; 1236 1237 spin_lock_irqsave(&np->lock, flags); 1238 1239 err = mii_read(np, np->phy_addr, MII_BMSR); 1240 if (err < 0) 1241 goto out; 1242 1243 bmsr = err; 1244 if (bmsr & BMSR_LSTATUS) { 1245 link_up = 1; 1246 current_speed = SPEED_1000; 1247 current_duplex = DUPLEX_FULL; 1248 } 1249 lp->active_speed = current_speed; 1250 lp->active_duplex = current_duplex; 1251 err = 0; 1252 1253 out: 1254 spin_unlock_irqrestore(&np->lock, flags); 1255 1256 *link_up_p = link_up; 1257 return err; 1258 } 1259 1260 static int link_status_1g(struct niu *np, int *link_up_p) 1261 { 1262 struct niu_link_config *lp = &np->link_config; 1263 unsigned long flags; 1264 int err; 1265 1266 spin_lock_irqsave(&np->lock, flags); 1267 1268 err = link_status_mii(np, link_up_p); 1269 lp->supported |= SUPPORTED_TP; 1270 lp->active_advertising |= ADVERTISED_TP; 1271 1272 spin_unlock_irqrestore(&np->lock, flags); 1273 return err; 1274 } 1275 1276 static int bcm8704_reset(struct niu *np) 1277 { 1278 int err, limit; 1279 1280 err = mdio_read(np, np->phy_addr, 1281 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1282 if (err < 0 || err == 0xffff) 1283 return err; 1284 err |= BMCR_RESET; 1285 err = mdio_write(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1286 MII_BMCR, err); 1287 if (err) 1288 return err; 1289 1290 limit = 1000; 1291 while (--limit >= 0) { 1292 err = mdio_read(np, np->phy_addr, 1293 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 1294 if (err < 0) 1295 return err; 1296 if (!(err & BMCR_RESET)) 1297 break; 1298 } 1299 if (limit < 0) { 1300 netdev_err(np->dev, "Port %u PHY will not reset (bmcr=%04x)\n", 1301 np->port, (err & 0xffff)); 1302 return -ENODEV; 1303 } 1304 return 0; 1305 } 1306 1307 /* When written, certain PHY registers need to be read back twice 1308 * in order for the bits to settle properly. 1309 */ 1310 static int bcm8704_user_dev3_readback(struct niu *np, int reg) 1311 { 1312 int err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1313 if (err < 0) 1314 return err; 1315 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, reg); 1316 if (err < 0) 1317 return err; 1318 return 0; 1319 } 1320 1321 static int bcm8706_init_user_dev3(struct niu *np) 1322 { 1323 int err; 1324 1325 1326 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1327 BCM8704_USER_OPT_DIGITAL_CTRL); 1328 if (err < 0) 1329 return err; 1330 err &= ~USER_ODIG_CTRL_GPIOS; 1331 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1332 err |= USER_ODIG_CTRL_RESV2; 1333 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1334 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1335 if (err) 1336 return err; 1337 1338 mdelay(1000); 1339 1340 return 0; 1341 } 1342 1343 static int bcm8704_init_user_dev3(struct niu *np) 1344 { 1345 int err; 1346 1347 err = mdio_write(np, np->phy_addr, 1348 BCM8704_USER_DEV3_ADDR, BCM8704_USER_CONTROL, 1349 (USER_CONTROL_OPTXRST_LVL | 1350 USER_CONTROL_OPBIASFLT_LVL | 1351 USER_CONTROL_OBTMPFLT_LVL | 1352 USER_CONTROL_OPPRFLT_LVL | 1353 USER_CONTROL_OPTXFLT_LVL | 1354 USER_CONTROL_OPRXLOS_LVL | 1355 USER_CONTROL_OPRXFLT_LVL | 1356 USER_CONTROL_OPTXON_LVL | 1357 (0x3f << USER_CONTROL_RES1_SHIFT))); 1358 if (err) 1359 return err; 1360 1361 err = mdio_write(np, np->phy_addr, 1362 BCM8704_USER_DEV3_ADDR, BCM8704_USER_PMD_TX_CONTROL, 1363 (USER_PMD_TX_CTL_XFP_CLKEN | 1364 (1 << USER_PMD_TX_CTL_TX_DAC_TXD_SH) | 1365 (2 << USER_PMD_TX_CTL_TX_DAC_TXCK_SH) | 1366 USER_PMD_TX_CTL_TSCK_LPWREN)); 1367 if (err) 1368 return err; 1369 1370 err = bcm8704_user_dev3_readback(np, BCM8704_USER_CONTROL); 1371 if (err) 1372 return err; 1373 err = bcm8704_user_dev3_readback(np, BCM8704_USER_PMD_TX_CONTROL); 1374 if (err) 1375 return err; 1376 1377 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1378 BCM8704_USER_OPT_DIGITAL_CTRL); 1379 if (err < 0) 1380 return err; 1381 err &= ~USER_ODIG_CTRL_GPIOS; 1382 err |= (0x3 << USER_ODIG_CTRL_GPIOS_SHIFT); 1383 err = mdio_write(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1384 BCM8704_USER_OPT_DIGITAL_CTRL, err); 1385 if (err) 1386 return err; 1387 1388 mdelay(1000); 1389 1390 return 0; 1391 } 1392 1393 static int mrvl88x2011_act_led(struct niu *np, int val) 1394 { 1395 int err; 1396 1397 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1398 MRVL88X2011_LED_8_TO_11_CTL); 1399 if (err < 0) 1400 return err; 1401 1402 err &= ~MRVL88X2011_LED(MRVL88X2011_LED_ACT,MRVL88X2011_LED_CTL_MASK); 1403 err |= MRVL88X2011_LED(MRVL88X2011_LED_ACT,val); 1404 1405 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1406 MRVL88X2011_LED_8_TO_11_CTL, err); 1407 } 1408 1409 static int mrvl88x2011_led_blink_rate(struct niu *np, int rate) 1410 { 1411 int err; 1412 1413 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1414 MRVL88X2011_LED_BLINK_CTL); 1415 if (err >= 0) { 1416 err &= ~MRVL88X2011_LED_BLKRATE_MASK; 1417 err |= (rate << 4); 1418 1419 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV2_ADDR, 1420 MRVL88X2011_LED_BLINK_CTL, err); 1421 } 1422 1423 return err; 1424 } 1425 1426 static int xcvr_init_10g_mrvl88x2011(struct niu *np) 1427 { 1428 int err; 1429 1430 /* Set LED functions */ 1431 err = mrvl88x2011_led_blink_rate(np, MRVL88X2011_LED_BLKRATE_134MS); 1432 if (err) 1433 return err; 1434 1435 /* led activity */ 1436 err = mrvl88x2011_act_led(np, MRVL88X2011_LED_CTL_OFF); 1437 if (err) 1438 return err; 1439 1440 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1441 MRVL88X2011_GENERAL_CTL); 1442 if (err < 0) 1443 return err; 1444 1445 err |= MRVL88X2011_ENA_XFPREFCLK; 1446 1447 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1448 MRVL88X2011_GENERAL_CTL, err); 1449 if (err < 0) 1450 return err; 1451 1452 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1453 MRVL88X2011_PMA_PMD_CTL_1); 1454 if (err < 0) 1455 return err; 1456 1457 if (np->link_config.loopback_mode == LOOPBACK_MAC) 1458 err |= MRVL88X2011_LOOPBACK; 1459 else 1460 err &= ~MRVL88X2011_LOOPBACK; 1461 1462 err = mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1463 MRVL88X2011_PMA_PMD_CTL_1, err); 1464 if (err < 0) 1465 return err; 1466 1467 /* Enable PMD */ 1468 return mdio_write(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1469 MRVL88X2011_10G_PMD_TX_DIS, MRVL88X2011_ENA_PMDTX); 1470 } 1471 1472 1473 static int xcvr_diag_bcm870x(struct niu *np) 1474 { 1475 u16 analog_stat0, tx_alarm_status; 1476 int err = 0; 1477 1478 #if 1 1479 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1480 MII_STAT1000); 1481 if (err < 0) 1482 return err; 1483 pr_info("Port %u PMA_PMD(MII_STAT1000) [%04x]\n", np->port, err); 1484 1485 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 0x20); 1486 if (err < 0) 1487 return err; 1488 pr_info("Port %u USER_DEV3(0x20) [%04x]\n", np->port, err); 1489 1490 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 1491 MII_NWAYTEST); 1492 if (err < 0) 1493 return err; 1494 pr_info("Port %u PHYXS(MII_NWAYTEST) [%04x]\n", np->port, err); 1495 #endif 1496 1497 /* XXX dig this out it might not be so useful XXX */ 1498 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1499 BCM8704_USER_ANALOG_STATUS0); 1500 if (err < 0) 1501 return err; 1502 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1503 BCM8704_USER_ANALOG_STATUS0); 1504 if (err < 0) 1505 return err; 1506 analog_stat0 = err; 1507 1508 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1509 BCM8704_USER_TX_ALARM_STATUS); 1510 if (err < 0) 1511 return err; 1512 err = mdio_read(np, np->phy_addr, BCM8704_USER_DEV3_ADDR, 1513 BCM8704_USER_TX_ALARM_STATUS); 1514 if (err < 0) 1515 return err; 1516 tx_alarm_status = err; 1517 1518 if (analog_stat0 != 0x03fc) { 1519 if ((analog_stat0 == 0x43bc) && (tx_alarm_status != 0)) { 1520 pr_info("Port %u cable not connected or bad cable\n", 1521 np->port); 1522 } else if (analog_stat0 == 0x639c) { 1523 pr_info("Port %u optical module is bad or missing\n", 1524 np->port); 1525 } 1526 } 1527 1528 return 0; 1529 } 1530 1531 static int xcvr_10g_set_lb_bcm870x(struct niu *np) 1532 { 1533 struct niu_link_config *lp = &np->link_config; 1534 int err; 1535 1536 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1537 MII_BMCR); 1538 if (err < 0) 1539 return err; 1540 1541 err &= ~BMCR_LOOPBACK; 1542 1543 if (lp->loopback_mode == LOOPBACK_MAC) 1544 err |= BMCR_LOOPBACK; 1545 1546 err = mdio_write(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 1547 MII_BMCR, err); 1548 if (err) 1549 return err; 1550 1551 return 0; 1552 } 1553 1554 static int xcvr_init_10g_bcm8706(struct niu *np) 1555 { 1556 int err = 0; 1557 u64 val; 1558 1559 if ((np->flags & NIU_FLAGS_HOTPLUG_PHY) && 1560 (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) == 0) 1561 return err; 1562 1563 val = nr64_mac(XMAC_CONFIG); 1564 val &= ~XMAC_CONFIG_LED_POLARITY; 1565 val |= XMAC_CONFIG_FORCE_LED_ON; 1566 nw64_mac(XMAC_CONFIG, val); 1567 1568 val = nr64(MIF_CONFIG); 1569 val |= MIF_CONFIG_INDIRECT_MODE; 1570 nw64(MIF_CONFIG, val); 1571 1572 err = bcm8704_reset(np); 1573 if (err) 1574 return err; 1575 1576 err = xcvr_10g_set_lb_bcm870x(np); 1577 if (err) 1578 return err; 1579 1580 err = bcm8706_init_user_dev3(np); 1581 if (err) 1582 return err; 1583 1584 err = xcvr_diag_bcm870x(np); 1585 if (err) 1586 return err; 1587 1588 return 0; 1589 } 1590 1591 static int xcvr_init_10g_bcm8704(struct niu *np) 1592 { 1593 int err; 1594 1595 err = bcm8704_reset(np); 1596 if (err) 1597 return err; 1598 1599 err = bcm8704_init_user_dev3(np); 1600 if (err) 1601 return err; 1602 1603 err = xcvr_10g_set_lb_bcm870x(np); 1604 if (err) 1605 return err; 1606 1607 err = xcvr_diag_bcm870x(np); 1608 if (err) 1609 return err; 1610 1611 return 0; 1612 } 1613 1614 static int xcvr_init_10g(struct niu *np) 1615 { 1616 int phy_id, err; 1617 u64 val; 1618 1619 val = nr64_mac(XMAC_CONFIG); 1620 val &= ~XMAC_CONFIG_LED_POLARITY; 1621 val |= XMAC_CONFIG_FORCE_LED_ON; 1622 nw64_mac(XMAC_CONFIG, val); 1623 1624 /* XXX shared resource, lock parent XXX */ 1625 val = nr64(MIF_CONFIG); 1626 val |= MIF_CONFIG_INDIRECT_MODE; 1627 nw64(MIF_CONFIG, val); 1628 1629 phy_id = phy_decode(np->parent->port_phy, np->port); 1630 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 1631 1632 /* handle different phy types */ 1633 switch (phy_id & NIU_PHY_ID_MASK) { 1634 case NIU_PHY_ID_MRVL88X2011: 1635 err = xcvr_init_10g_mrvl88x2011(np); 1636 break; 1637 1638 default: /* bcom 8704 */ 1639 err = xcvr_init_10g_bcm8704(np); 1640 break; 1641 } 1642 1643 return err; 1644 } 1645 1646 static int mii_reset(struct niu *np) 1647 { 1648 int limit, err; 1649 1650 err = mii_write(np, np->phy_addr, MII_BMCR, BMCR_RESET); 1651 if (err) 1652 return err; 1653 1654 limit = 1000; 1655 while (--limit >= 0) { 1656 udelay(500); 1657 err = mii_read(np, np->phy_addr, MII_BMCR); 1658 if (err < 0) 1659 return err; 1660 if (!(err & BMCR_RESET)) 1661 break; 1662 } 1663 if (limit < 0) { 1664 netdev_err(np->dev, "Port %u MII would not reset, bmcr[%04x]\n", 1665 np->port, err); 1666 return -ENODEV; 1667 } 1668 1669 return 0; 1670 } 1671 1672 static int xcvr_init_1g_rgmii(struct niu *np) 1673 { 1674 int err; 1675 u64 val; 1676 u16 bmcr, bmsr, estat; 1677 1678 val = nr64(MIF_CONFIG); 1679 val &= ~MIF_CONFIG_INDIRECT_MODE; 1680 nw64(MIF_CONFIG, val); 1681 1682 err = mii_reset(np); 1683 if (err) 1684 return err; 1685 1686 err = mii_read(np, np->phy_addr, MII_BMSR); 1687 if (err < 0) 1688 return err; 1689 bmsr = err; 1690 1691 estat = 0; 1692 if (bmsr & BMSR_ESTATEN) { 1693 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1694 if (err < 0) 1695 return err; 1696 estat = err; 1697 } 1698 1699 bmcr = 0; 1700 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1701 if (err) 1702 return err; 1703 1704 if (bmsr & BMSR_ESTATEN) { 1705 u16 ctrl1000 = 0; 1706 1707 if (estat & ESTATUS_1000_TFULL) 1708 ctrl1000 |= ADVERTISE_1000FULL; 1709 err = mii_write(np, np->phy_addr, MII_CTRL1000, ctrl1000); 1710 if (err) 1711 return err; 1712 } 1713 1714 bmcr = (BMCR_SPEED1000 | BMCR_FULLDPLX); 1715 1716 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1717 if (err) 1718 return err; 1719 1720 err = mii_read(np, np->phy_addr, MII_BMCR); 1721 if (err < 0) 1722 return err; 1723 bmcr = mii_read(np, np->phy_addr, MII_BMCR); 1724 1725 err = mii_read(np, np->phy_addr, MII_BMSR); 1726 if (err < 0) 1727 return err; 1728 1729 return 0; 1730 } 1731 1732 static int mii_init_common(struct niu *np) 1733 { 1734 struct niu_link_config *lp = &np->link_config; 1735 u16 bmcr, bmsr, adv, estat; 1736 int err; 1737 1738 err = mii_reset(np); 1739 if (err) 1740 return err; 1741 1742 err = mii_read(np, np->phy_addr, MII_BMSR); 1743 if (err < 0) 1744 return err; 1745 bmsr = err; 1746 1747 estat = 0; 1748 if (bmsr & BMSR_ESTATEN) { 1749 err = mii_read(np, np->phy_addr, MII_ESTATUS); 1750 if (err < 0) 1751 return err; 1752 estat = err; 1753 } 1754 1755 bmcr = 0; 1756 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1757 if (err) 1758 return err; 1759 1760 if (lp->loopback_mode == LOOPBACK_MAC) { 1761 bmcr |= BMCR_LOOPBACK; 1762 if (lp->active_speed == SPEED_1000) 1763 bmcr |= BMCR_SPEED1000; 1764 if (lp->active_duplex == DUPLEX_FULL) 1765 bmcr |= BMCR_FULLDPLX; 1766 } 1767 1768 if (lp->loopback_mode == LOOPBACK_PHY) { 1769 u16 aux; 1770 1771 aux = (BCM5464R_AUX_CTL_EXT_LB | 1772 BCM5464R_AUX_CTL_WRITE_1); 1773 err = mii_write(np, np->phy_addr, BCM5464R_AUX_CTL, aux); 1774 if (err) 1775 return err; 1776 } 1777 1778 if (lp->autoneg) { 1779 u16 ctrl1000; 1780 1781 adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP; 1782 if ((bmsr & BMSR_10HALF) && 1783 (lp->advertising & ADVERTISED_10baseT_Half)) 1784 adv |= ADVERTISE_10HALF; 1785 if ((bmsr & BMSR_10FULL) && 1786 (lp->advertising & ADVERTISED_10baseT_Full)) 1787 adv |= ADVERTISE_10FULL; 1788 if ((bmsr & BMSR_100HALF) && 1789 (lp->advertising & ADVERTISED_100baseT_Half)) 1790 adv |= ADVERTISE_100HALF; 1791 if ((bmsr & BMSR_100FULL) && 1792 (lp->advertising & ADVERTISED_100baseT_Full)) 1793 adv |= ADVERTISE_100FULL; 1794 err = mii_write(np, np->phy_addr, MII_ADVERTISE, adv); 1795 if (err) 1796 return err; 1797 1798 if (likely(bmsr & BMSR_ESTATEN)) { 1799 ctrl1000 = 0; 1800 if ((estat & ESTATUS_1000_THALF) && 1801 (lp->advertising & ADVERTISED_1000baseT_Half)) 1802 ctrl1000 |= ADVERTISE_1000HALF; 1803 if ((estat & ESTATUS_1000_TFULL) && 1804 (lp->advertising & ADVERTISED_1000baseT_Full)) 1805 ctrl1000 |= ADVERTISE_1000FULL; 1806 err = mii_write(np, np->phy_addr, 1807 MII_CTRL1000, ctrl1000); 1808 if (err) 1809 return err; 1810 } 1811 1812 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 1813 } else { 1814 /* !lp->autoneg */ 1815 int fulldpx; 1816 1817 if (lp->duplex == DUPLEX_FULL) { 1818 bmcr |= BMCR_FULLDPLX; 1819 fulldpx = 1; 1820 } else if (lp->duplex == DUPLEX_HALF) 1821 fulldpx = 0; 1822 else 1823 return -EINVAL; 1824 1825 if (lp->speed == SPEED_1000) { 1826 /* if X-full requested while not supported, or 1827 X-half requested while not supported... */ 1828 if ((fulldpx && !(estat & ESTATUS_1000_TFULL)) || 1829 (!fulldpx && !(estat & ESTATUS_1000_THALF))) 1830 return -EINVAL; 1831 bmcr |= BMCR_SPEED1000; 1832 } else if (lp->speed == SPEED_100) { 1833 if ((fulldpx && !(bmsr & BMSR_100FULL)) || 1834 (!fulldpx && !(bmsr & BMSR_100HALF))) 1835 return -EINVAL; 1836 bmcr |= BMCR_SPEED100; 1837 } else if (lp->speed == SPEED_10) { 1838 if ((fulldpx && !(bmsr & BMSR_10FULL)) || 1839 (!fulldpx && !(bmsr & BMSR_10HALF))) 1840 return -EINVAL; 1841 } else 1842 return -EINVAL; 1843 } 1844 1845 err = mii_write(np, np->phy_addr, MII_BMCR, bmcr); 1846 if (err) 1847 return err; 1848 1849 #if 0 1850 err = mii_read(np, np->phy_addr, MII_BMCR); 1851 if (err < 0) 1852 return err; 1853 bmcr = err; 1854 1855 err = mii_read(np, np->phy_addr, MII_BMSR); 1856 if (err < 0) 1857 return err; 1858 bmsr = err; 1859 1860 pr_info("Port %u after MII init bmcr[%04x] bmsr[%04x]\n", 1861 np->port, bmcr, bmsr); 1862 #endif 1863 1864 return 0; 1865 } 1866 1867 static int xcvr_init_1g(struct niu *np) 1868 { 1869 u64 val; 1870 1871 /* XXX shared resource, lock parent XXX */ 1872 val = nr64(MIF_CONFIG); 1873 val &= ~MIF_CONFIG_INDIRECT_MODE; 1874 nw64(MIF_CONFIG, val); 1875 1876 return mii_init_common(np); 1877 } 1878 1879 static int niu_xcvr_init(struct niu *np) 1880 { 1881 const struct niu_phy_ops *ops = np->phy_ops; 1882 int err; 1883 1884 err = 0; 1885 if (ops->xcvr_init) 1886 err = ops->xcvr_init(np); 1887 1888 return err; 1889 } 1890 1891 static int niu_serdes_init(struct niu *np) 1892 { 1893 const struct niu_phy_ops *ops = np->phy_ops; 1894 int err; 1895 1896 err = 0; 1897 if (ops->serdes_init) 1898 err = ops->serdes_init(np); 1899 1900 return err; 1901 } 1902 1903 static void niu_init_xif(struct niu *); 1904 static void niu_handle_led(struct niu *, int status); 1905 1906 static int niu_link_status_common(struct niu *np, int link_up) 1907 { 1908 struct niu_link_config *lp = &np->link_config; 1909 struct net_device *dev = np->dev; 1910 unsigned long flags; 1911 1912 if (!netif_carrier_ok(dev) && link_up) { 1913 netif_info(np, link, dev, "Link is up at %s, %s duplex\n", 1914 lp->active_speed == SPEED_10000 ? "10Gb/sec" : 1915 lp->active_speed == SPEED_1000 ? "1Gb/sec" : 1916 lp->active_speed == SPEED_100 ? "100Mbit/sec" : 1917 "10Mbit/sec", 1918 lp->active_duplex == DUPLEX_FULL ? "full" : "half"); 1919 1920 spin_lock_irqsave(&np->lock, flags); 1921 niu_init_xif(np); 1922 niu_handle_led(np, 1); 1923 spin_unlock_irqrestore(&np->lock, flags); 1924 1925 netif_carrier_on(dev); 1926 } else if (netif_carrier_ok(dev) && !link_up) { 1927 netif_warn(np, link, dev, "Link is down\n"); 1928 spin_lock_irqsave(&np->lock, flags); 1929 niu_handle_led(np, 0); 1930 spin_unlock_irqrestore(&np->lock, flags); 1931 netif_carrier_off(dev); 1932 } 1933 1934 return 0; 1935 } 1936 1937 static int link_status_10g_mrvl(struct niu *np, int *link_up_p) 1938 { 1939 int err, link_up, pma_status, pcs_status; 1940 1941 link_up = 0; 1942 1943 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1944 MRVL88X2011_10G_PMD_STATUS_2); 1945 if (err < 0) 1946 goto out; 1947 1948 /* Check PMA/PMD Register: 1.0001.2 == 1 */ 1949 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV1_ADDR, 1950 MRVL88X2011_PMA_PMD_STATUS_1); 1951 if (err < 0) 1952 goto out; 1953 1954 pma_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1955 1956 /* Check PMC Register : 3.0001.2 == 1: read twice */ 1957 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1958 MRVL88X2011_PMA_PMD_STATUS_1); 1959 if (err < 0) 1960 goto out; 1961 1962 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV3_ADDR, 1963 MRVL88X2011_PMA_PMD_STATUS_1); 1964 if (err < 0) 1965 goto out; 1966 1967 pcs_status = ((err & MRVL88X2011_LNK_STATUS_OK) ? 1 : 0); 1968 1969 /* Check XGXS Register : 4.0018.[0-3,12] */ 1970 err = mdio_read(np, np->phy_addr, MRVL88X2011_USER_DEV4_ADDR, 1971 MRVL88X2011_10G_XGXS_LANE_STAT); 1972 if (err < 0) 1973 goto out; 1974 1975 if (err == (PHYXS_XGXS_LANE_STAT_ALINGED | PHYXS_XGXS_LANE_STAT_LANE3 | 1976 PHYXS_XGXS_LANE_STAT_LANE2 | PHYXS_XGXS_LANE_STAT_LANE1 | 1977 PHYXS_XGXS_LANE_STAT_LANE0 | PHYXS_XGXS_LANE_STAT_MAGIC | 1978 0x800)) 1979 link_up = (pma_status && pcs_status) ? 1 : 0; 1980 1981 np->link_config.active_speed = SPEED_10000; 1982 np->link_config.active_duplex = DUPLEX_FULL; 1983 err = 0; 1984 out: 1985 mrvl88x2011_act_led(np, (link_up ? 1986 MRVL88X2011_LED_CTL_PCS_ACT : 1987 MRVL88X2011_LED_CTL_OFF)); 1988 1989 *link_up_p = link_up; 1990 return err; 1991 } 1992 1993 static int link_status_10g_bcm8706(struct niu *np, int *link_up_p) 1994 { 1995 int err, link_up; 1996 link_up = 0; 1997 1998 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 1999 BCM8704_PMD_RCV_SIGDET); 2000 if (err < 0 || err == 0xffff) 2001 goto out; 2002 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2003 err = 0; 2004 goto out; 2005 } 2006 2007 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2008 BCM8704_PCS_10G_R_STATUS); 2009 if (err < 0) 2010 goto out; 2011 2012 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2013 err = 0; 2014 goto out; 2015 } 2016 2017 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2018 BCM8704_PHYXS_XGXS_LANE_STAT); 2019 if (err < 0) 2020 goto out; 2021 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2022 PHYXS_XGXS_LANE_STAT_MAGIC | 2023 PHYXS_XGXS_LANE_STAT_PATTEST | 2024 PHYXS_XGXS_LANE_STAT_LANE3 | 2025 PHYXS_XGXS_LANE_STAT_LANE2 | 2026 PHYXS_XGXS_LANE_STAT_LANE1 | 2027 PHYXS_XGXS_LANE_STAT_LANE0)) { 2028 err = 0; 2029 np->link_config.active_speed = SPEED_INVALID; 2030 np->link_config.active_duplex = DUPLEX_INVALID; 2031 goto out; 2032 } 2033 2034 link_up = 1; 2035 np->link_config.active_speed = SPEED_10000; 2036 np->link_config.active_duplex = DUPLEX_FULL; 2037 err = 0; 2038 2039 out: 2040 *link_up_p = link_up; 2041 return err; 2042 } 2043 2044 static int link_status_10g_bcom(struct niu *np, int *link_up_p) 2045 { 2046 int err, link_up; 2047 2048 link_up = 0; 2049 2050 err = mdio_read(np, np->phy_addr, BCM8704_PMA_PMD_DEV_ADDR, 2051 BCM8704_PMD_RCV_SIGDET); 2052 if (err < 0) 2053 goto out; 2054 if (!(err & PMD_RCV_SIGDET_GLOBAL)) { 2055 err = 0; 2056 goto out; 2057 } 2058 2059 err = mdio_read(np, np->phy_addr, BCM8704_PCS_DEV_ADDR, 2060 BCM8704_PCS_10G_R_STATUS); 2061 if (err < 0) 2062 goto out; 2063 if (!(err & PCS_10G_R_STATUS_BLK_LOCK)) { 2064 err = 0; 2065 goto out; 2066 } 2067 2068 err = mdio_read(np, np->phy_addr, BCM8704_PHYXS_DEV_ADDR, 2069 BCM8704_PHYXS_XGXS_LANE_STAT); 2070 if (err < 0) 2071 goto out; 2072 2073 if (err != (PHYXS_XGXS_LANE_STAT_ALINGED | 2074 PHYXS_XGXS_LANE_STAT_MAGIC | 2075 PHYXS_XGXS_LANE_STAT_LANE3 | 2076 PHYXS_XGXS_LANE_STAT_LANE2 | 2077 PHYXS_XGXS_LANE_STAT_LANE1 | 2078 PHYXS_XGXS_LANE_STAT_LANE0)) { 2079 err = 0; 2080 goto out; 2081 } 2082 2083 link_up = 1; 2084 np->link_config.active_speed = SPEED_10000; 2085 np->link_config.active_duplex = DUPLEX_FULL; 2086 err = 0; 2087 2088 out: 2089 *link_up_p = link_up; 2090 return err; 2091 } 2092 2093 static int link_status_10g(struct niu *np, int *link_up_p) 2094 { 2095 unsigned long flags; 2096 int err = -EINVAL; 2097 2098 spin_lock_irqsave(&np->lock, flags); 2099 2100 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2101 int phy_id; 2102 2103 phy_id = phy_decode(np->parent->port_phy, np->port); 2104 phy_id = np->parent->phy_probe_info.phy_id[phy_id][np->port]; 2105 2106 /* handle different phy types */ 2107 switch (phy_id & NIU_PHY_ID_MASK) { 2108 case NIU_PHY_ID_MRVL88X2011: 2109 err = link_status_10g_mrvl(np, link_up_p); 2110 break; 2111 2112 default: /* bcom 8704 */ 2113 err = link_status_10g_bcom(np, link_up_p); 2114 break; 2115 } 2116 } 2117 2118 spin_unlock_irqrestore(&np->lock, flags); 2119 2120 return err; 2121 } 2122 2123 static int niu_10g_phy_present(struct niu *np) 2124 { 2125 u64 sig, mask, val; 2126 2127 sig = nr64(ESR_INT_SIGNALS); 2128 switch (np->port) { 2129 case 0: 2130 mask = ESR_INT_SIGNALS_P0_BITS; 2131 val = (ESR_INT_SRDY0_P0 | 2132 ESR_INT_DET0_P0 | 2133 ESR_INT_XSRDY_P0 | 2134 ESR_INT_XDP_P0_CH3 | 2135 ESR_INT_XDP_P0_CH2 | 2136 ESR_INT_XDP_P0_CH1 | 2137 ESR_INT_XDP_P0_CH0); 2138 break; 2139 2140 case 1: 2141 mask = ESR_INT_SIGNALS_P1_BITS; 2142 val = (ESR_INT_SRDY0_P1 | 2143 ESR_INT_DET0_P1 | 2144 ESR_INT_XSRDY_P1 | 2145 ESR_INT_XDP_P1_CH3 | 2146 ESR_INT_XDP_P1_CH2 | 2147 ESR_INT_XDP_P1_CH1 | 2148 ESR_INT_XDP_P1_CH0); 2149 break; 2150 2151 default: 2152 return 0; 2153 } 2154 2155 if ((sig & mask) != val) 2156 return 0; 2157 return 1; 2158 } 2159 2160 static int link_status_10g_hotplug(struct niu *np, int *link_up_p) 2161 { 2162 unsigned long flags; 2163 int err = 0; 2164 int phy_present; 2165 int phy_present_prev; 2166 2167 spin_lock_irqsave(&np->lock, flags); 2168 2169 if (np->link_config.loopback_mode == LOOPBACK_DISABLED) { 2170 phy_present_prev = (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) ? 2171 1 : 0; 2172 phy_present = niu_10g_phy_present(np); 2173 if (phy_present != phy_present_prev) { 2174 /* state change */ 2175 if (phy_present) { 2176 /* A NEM was just plugged in */ 2177 np->flags |= NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2178 if (np->phy_ops->xcvr_init) 2179 err = np->phy_ops->xcvr_init(np); 2180 if (err) { 2181 err = mdio_read(np, np->phy_addr, 2182 BCM8704_PHYXS_DEV_ADDR, MII_BMCR); 2183 if (err == 0xffff) { 2184 /* No mdio, back-to-back XAUI */ 2185 goto out; 2186 } 2187 /* debounce */ 2188 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2189 } 2190 } else { 2191 np->flags &= ~NIU_FLAGS_HOTPLUG_PHY_PRESENT; 2192 *link_up_p = 0; 2193 netif_warn(np, link, np->dev, 2194 "Hotplug PHY Removed\n"); 2195 } 2196 } 2197 out: 2198 if (np->flags & NIU_FLAGS_HOTPLUG_PHY_PRESENT) { 2199 err = link_status_10g_bcm8706(np, link_up_p); 2200 if (err == 0xffff) { 2201 /* No mdio, back-to-back XAUI: it is C10NEM */ 2202 *link_up_p = 1; 2203 np->link_config.active_speed = SPEED_10000; 2204 np->link_config.active_duplex = DUPLEX_FULL; 2205 } 2206 } 2207 } 2208 2209 spin_unlock_irqrestore(&np->lock, flags); 2210 2211 return 0; 2212 } 2213 2214 static int niu_link_status(struct niu *np, int *link_up_p) 2215 { 2216 const struct niu_phy_ops *ops = np->phy_ops; 2217 int err; 2218 2219 err = 0; 2220 if (ops->link_status) 2221 err = ops->link_status(np, link_up_p); 2222 2223 return err; 2224 } 2225 2226 static void niu_timer(struct timer_list *t) 2227 { 2228 struct niu *np = timer_container_of(np, t, timer); 2229 unsigned long off; 2230 int err, link_up; 2231 2232 err = niu_link_status(np, &link_up); 2233 if (!err) 2234 niu_link_status_common(np, link_up); 2235 2236 if (netif_carrier_ok(np->dev)) 2237 off = 5 * HZ; 2238 else 2239 off = 1 * HZ; 2240 np->timer.expires = jiffies + off; 2241 2242 add_timer(&np->timer); 2243 } 2244 2245 static const struct niu_phy_ops phy_ops_10g_serdes = { 2246 .serdes_init = serdes_init_10g_serdes, 2247 .link_status = link_status_10g_serdes, 2248 }; 2249 2250 static const struct niu_phy_ops phy_ops_10g_serdes_niu = { 2251 .serdes_init = serdes_init_niu_10g_serdes, 2252 .link_status = link_status_10g_serdes, 2253 }; 2254 2255 static const struct niu_phy_ops phy_ops_1g_serdes_niu = { 2256 .serdes_init = serdes_init_niu_1g_serdes, 2257 .link_status = link_status_1g_serdes, 2258 }; 2259 2260 static const struct niu_phy_ops phy_ops_1g_rgmii = { 2261 .xcvr_init = xcvr_init_1g_rgmii, 2262 .link_status = link_status_1g_rgmii, 2263 }; 2264 2265 static const struct niu_phy_ops phy_ops_10g_fiber_niu = { 2266 .serdes_init = serdes_init_niu_10g_fiber, 2267 .xcvr_init = xcvr_init_10g, 2268 .link_status = link_status_10g, 2269 }; 2270 2271 static const struct niu_phy_ops phy_ops_10g_fiber = { 2272 .serdes_init = serdes_init_10g, 2273 .xcvr_init = xcvr_init_10g, 2274 .link_status = link_status_10g, 2275 }; 2276 2277 static const struct niu_phy_ops phy_ops_10g_fiber_hotplug = { 2278 .serdes_init = serdes_init_10g, 2279 .xcvr_init = xcvr_init_10g_bcm8706, 2280 .link_status = link_status_10g_hotplug, 2281 }; 2282 2283 static const struct niu_phy_ops phy_ops_niu_10g_hotplug = { 2284 .serdes_init = serdes_init_niu_10g_fiber, 2285 .xcvr_init = xcvr_init_10g_bcm8706, 2286 .link_status = link_status_10g_hotplug, 2287 }; 2288 2289 static const struct niu_phy_ops phy_ops_10g_copper = { 2290 .serdes_init = serdes_init_10g, 2291 .link_status = link_status_10g, /* XXX */ 2292 }; 2293 2294 static const struct niu_phy_ops phy_ops_1g_fiber = { 2295 .serdes_init = serdes_init_1g, 2296 .xcvr_init = xcvr_init_1g, 2297 .link_status = link_status_1g, 2298 }; 2299 2300 static const struct niu_phy_ops phy_ops_1g_copper = { 2301 .xcvr_init = xcvr_init_1g, 2302 .link_status = link_status_1g, 2303 }; 2304 2305 struct niu_phy_template { 2306 const struct niu_phy_ops *ops; 2307 u32 phy_addr_base; 2308 }; 2309 2310 static const struct niu_phy_template phy_template_niu_10g_fiber = { 2311 .ops = &phy_ops_10g_fiber_niu, 2312 .phy_addr_base = 16, 2313 }; 2314 2315 static const struct niu_phy_template phy_template_niu_10g_serdes = { 2316 .ops = &phy_ops_10g_serdes_niu, 2317 .phy_addr_base = 0, 2318 }; 2319 2320 static const struct niu_phy_template phy_template_niu_1g_serdes = { 2321 .ops = &phy_ops_1g_serdes_niu, 2322 .phy_addr_base = 0, 2323 }; 2324 2325 static const struct niu_phy_template phy_template_10g_fiber = { 2326 .ops = &phy_ops_10g_fiber, 2327 .phy_addr_base = 8, 2328 }; 2329 2330 static const struct niu_phy_template phy_template_10g_fiber_hotplug = { 2331 .ops = &phy_ops_10g_fiber_hotplug, 2332 .phy_addr_base = 8, 2333 }; 2334 2335 static const struct niu_phy_template phy_template_niu_10g_hotplug = { 2336 .ops = &phy_ops_niu_10g_hotplug, 2337 .phy_addr_base = 8, 2338 }; 2339 2340 static const struct niu_phy_template phy_template_10g_copper = { 2341 .ops = &phy_ops_10g_copper, 2342 .phy_addr_base = 10, 2343 }; 2344 2345 static const struct niu_phy_template phy_template_1g_fiber = { 2346 .ops = &phy_ops_1g_fiber, 2347 .phy_addr_base = 0, 2348 }; 2349 2350 static const struct niu_phy_template phy_template_1g_copper = { 2351 .ops = &phy_ops_1g_copper, 2352 .phy_addr_base = 0, 2353 }; 2354 2355 static const struct niu_phy_template phy_template_1g_rgmii = { 2356 .ops = &phy_ops_1g_rgmii, 2357 .phy_addr_base = 0, 2358 }; 2359 2360 static const struct niu_phy_template phy_template_10g_serdes = { 2361 .ops = &phy_ops_10g_serdes, 2362 .phy_addr_base = 0, 2363 }; 2364 2365 static int niu_atca_port_num[4] = { 2366 0, 0, 11, 10 2367 }; 2368 2369 static int serdes_init_10g_serdes(struct niu *np) 2370 { 2371 struct niu_link_config *lp = &np->link_config; 2372 unsigned long ctrl_reg, test_cfg_reg, pll_cfg, i; 2373 u64 ctrl_val, test_cfg_val, sig, mask, val; 2374 2375 switch (np->port) { 2376 case 0: 2377 ctrl_reg = ENET_SERDES_0_CTRL_CFG; 2378 test_cfg_reg = ENET_SERDES_0_TEST_CFG; 2379 pll_cfg = ENET_SERDES_0_PLL_CFG; 2380 break; 2381 case 1: 2382 ctrl_reg = ENET_SERDES_1_CTRL_CFG; 2383 test_cfg_reg = ENET_SERDES_1_TEST_CFG; 2384 pll_cfg = ENET_SERDES_1_PLL_CFG; 2385 break; 2386 2387 default: 2388 return -EINVAL; 2389 } 2390 ctrl_val = (ENET_SERDES_CTRL_SDET_0 | 2391 ENET_SERDES_CTRL_SDET_1 | 2392 ENET_SERDES_CTRL_SDET_2 | 2393 ENET_SERDES_CTRL_SDET_3 | 2394 (0x5 << ENET_SERDES_CTRL_EMPH_0_SHIFT) | 2395 (0x5 << ENET_SERDES_CTRL_EMPH_1_SHIFT) | 2396 (0x5 << ENET_SERDES_CTRL_EMPH_2_SHIFT) | 2397 (0x5 << ENET_SERDES_CTRL_EMPH_3_SHIFT) | 2398 (0x1 << ENET_SERDES_CTRL_LADJ_0_SHIFT) | 2399 (0x1 << ENET_SERDES_CTRL_LADJ_1_SHIFT) | 2400 (0x1 << ENET_SERDES_CTRL_LADJ_2_SHIFT) | 2401 (0x1 << ENET_SERDES_CTRL_LADJ_3_SHIFT)); 2402 test_cfg_val = 0; 2403 2404 if (lp->loopback_mode == LOOPBACK_PHY) { 2405 test_cfg_val |= ((ENET_TEST_MD_PAD_LOOPBACK << 2406 ENET_SERDES_TEST_MD_0_SHIFT) | 2407 (ENET_TEST_MD_PAD_LOOPBACK << 2408 ENET_SERDES_TEST_MD_1_SHIFT) | 2409 (ENET_TEST_MD_PAD_LOOPBACK << 2410 ENET_SERDES_TEST_MD_2_SHIFT) | 2411 (ENET_TEST_MD_PAD_LOOPBACK << 2412 ENET_SERDES_TEST_MD_3_SHIFT)); 2413 } 2414 2415 esr_reset(np); 2416 nw64(pll_cfg, ENET_SERDES_PLL_FBDIV2); 2417 nw64(ctrl_reg, ctrl_val); 2418 nw64(test_cfg_reg, test_cfg_val); 2419 2420 /* Initialize all 4 lanes of the SERDES. */ 2421 for (i = 0; i < 4; i++) { 2422 u32 rxtx_ctrl, glue0; 2423 int err; 2424 2425 err = esr_read_rxtx_ctrl(np, i, &rxtx_ctrl); 2426 if (err) 2427 return err; 2428 err = esr_read_glue0(np, i, &glue0); 2429 if (err) 2430 return err; 2431 2432 rxtx_ctrl &= ~(ESR_RXTX_CTRL_VMUXLO); 2433 rxtx_ctrl |= (ESR_RXTX_CTRL_ENSTRETCH | 2434 (2 << ESR_RXTX_CTRL_VMUXLO_SHIFT)); 2435 2436 glue0 &= ~(ESR_GLUE_CTRL0_SRATE | 2437 ESR_GLUE_CTRL0_THCNT | 2438 ESR_GLUE_CTRL0_BLTIME); 2439 glue0 |= (ESR_GLUE_CTRL0_RXLOSENAB | 2440 (0xf << ESR_GLUE_CTRL0_SRATE_SHIFT) | 2441 (0xff << ESR_GLUE_CTRL0_THCNT_SHIFT) | 2442 (BLTIME_300_CYCLES << 2443 ESR_GLUE_CTRL0_BLTIME_SHIFT)); 2444 2445 err = esr_write_rxtx_ctrl(np, i, rxtx_ctrl); 2446 if (err) 2447 return err; 2448 err = esr_write_glue0(np, i, glue0); 2449 if (err) 2450 return err; 2451 } 2452 2453 2454 sig = nr64(ESR_INT_SIGNALS); 2455 switch (np->port) { 2456 case 0: 2457 mask = ESR_INT_SIGNALS_P0_BITS; 2458 val = (ESR_INT_SRDY0_P0 | 2459 ESR_INT_DET0_P0 | 2460 ESR_INT_XSRDY_P0 | 2461 ESR_INT_XDP_P0_CH3 | 2462 ESR_INT_XDP_P0_CH2 | 2463 ESR_INT_XDP_P0_CH1 | 2464 ESR_INT_XDP_P0_CH0); 2465 break; 2466 2467 case 1: 2468 mask = ESR_INT_SIGNALS_P1_BITS; 2469 val = (ESR_INT_SRDY0_P1 | 2470 ESR_INT_DET0_P1 | 2471 ESR_INT_XSRDY_P1 | 2472 ESR_INT_XDP_P1_CH3 | 2473 ESR_INT_XDP_P1_CH2 | 2474 ESR_INT_XDP_P1_CH1 | 2475 ESR_INT_XDP_P1_CH0); 2476 break; 2477 2478 default: 2479 return -EINVAL; 2480 } 2481 2482 if ((sig & mask) != val) { 2483 int err; 2484 err = serdes_init_1g_serdes(np); 2485 if (!err) { 2486 np->flags &= ~NIU_FLAGS_10G; 2487 np->mac_xcvr = MAC_XCVR_PCS; 2488 } else { 2489 netdev_err(np->dev, "Port %u 10G/1G SERDES Link Failed\n", 2490 np->port); 2491 return -ENODEV; 2492 } 2493 } 2494 2495 return 0; 2496 } 2497 2498 static int niu_determine_phy_disposition(struct niu *np) 2499 { 2500 struct niu_parent *parent = np->parent; 2501 u8 plat_type = parent->plat_type; 2502 const struct niu_phy_template *tp; 2503 u32 phy_addr_off = 0; 2504 2505 if (plat_type == PLAT_TYPE_NIU) { 2506 switch (np->flags & 2507 (NIU_FLAGS_10G | 2508 NIU_FLAGS_FIBER | 2509 NIU_FLAGS_XCVR_SERDES)) { 2510 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2511 /* 10G Serdes */ 2512 tp = &phy_template_niu_10g_serdes; 2513 break; 2514 case NIU_FLAGS_XCVR_SERDES: 2515 /* 1G Serdes */ 2516 tp = &phy_template_niu_1g_serdes; 2517 break; 2518 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2519 /* 10G Fiber */ 2520 default: 2521 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2522 tp = &phy_template_niu_10g_hotplug; 2523 if (np->port == 0) 2524 phy_addr_off = 8; 2525 if (np->port == 1) 2526 phy_addr_off = 12; 2527 } else { 2528 tp = &phy_template_niu_10g_fiber; 2529 phy_addr_off += np->port; 2530 } 2531 break; 2532 } 2533 } else { 2534 switch (np->flags & 2535 (NIU_FLAGS_10G | 2536 NIU_FLAGS_FIBER | 2537 NIU_FLAGS_XCVR_SERDES)) { 2538 case 0: 2539 /* 1G copper */ 2540 tp = &phy_template_1g_copper; 2541 if (plat_type == PLAT_TYPE_VF_P0) 2542 phy_addr_off = 10; 2543 else if (plat_type == PLAT_TYPE_VF_P1) 2544 phy_addr_off = 26; 2545 2546 phy_addr_off += (np->port ^ 0x3); 2547 break; 2548 2549 case NIU_FLAGS_10G: 2550 /* 10G copper */ 2551 tp = &phy_template_10g_copper; 2552 break; 2553 2554 case NIU_FLAGS_FIBER: 2555 /* 1G fiber */ 2556 tp = &phy_template_1g_fiber; 2557 break; 2558 2559 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 2560 /* 10G fiber */ 2561 tp = &phy_template_10g_fiber; 2562 if (plat_type == PLAT_TYPE_VF_P0 || 2563 plat_type == PLAT_TYPE_VF_P1) 2564 phy_addr_off = 8; 2565 phy_addr_off += np->port; 2566 if (np->flags & NIU_FLAGS_HOTPLUG_PHY) { 2567 tp = &phy_template_10g_fiber_hotplug; 2568 if (np->port == 0) 2569 phy_addr_off = 8; 2570 if (np->port == 1) 2571 phy_addr_off = 12; 2572 } 2573 break; 2574 2575 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 2576 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 2577 case NIU_FLAGS_XCVR_SERDES: 2578 switch(np->port) { 2579 case 0: 2580 case 1: 2581 tp = &phy_template_10g_serdes; 2582 break; 2583 case 2: 2584 case 3: 2585 tp = &phy_template_1g_rgmii; 2586 break; 2587 default: 2588 return -EINVAL; 2589 } 2590 phy_addr_off = niu_atca_port_num[np->port]; 2591 break; 2592 2593 default: 2594 return -EINVAL; 2595 } 2596 } 2597 2598 np->phy_ops = tp->ops; 2599 np->phy_addr = tp->phy_addr_base + phy_addr_off; 2600 2601 return 0; 2602 } 2603 2604 static int niu_init_link(struct niu *np) 2605 { 2606 struct niu_parent *parent = np->parent; 2607 int err, ignore; 2608 2609 if (parent->plat_type == PLAT_TYPE_NIU) { 2610 err = niu_xcvr_init(np); 2611 if (err) 2612 return err; 2613 msleep(200); 2614 } 2615 err = niu_serdes_init(np); 2616 if (err && !(np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2617 return err; 2618 msleep(200); 2619 err = niu_xcvr_init(np); 2620 if (!err || (np->flags & NIU_FLAGS_HOTPLUG_PHY)) 2621 niu_link_status(np, &ignore); 2622 return 0; 2623 } 2624 2625 static void niu_set_primary_mac(struct niu *np, const unsigned char *addr) 2626 { 2627 u16 reg0 = addr[4] << 8 | addr[5]; 2628 u16 reg1 = addr[2] << 8 | addr[3]; 2629 u16 reg2 = addr[0] << 8 | addr[1]; 2630 2631 if (np->flags & NIU_FLAGS_XMAC) { 2632 nw64_mac(XMAC_ADDR0, reg0); 2633 nw64_mac(XMAC_ADDR1, reg1); 2634 nw64_mac(XMAC_ADDR2, reg2); 2635 } else { 2636 nw64_mac(BMAC_ADDR0, reg0); 2637 nw64_mac(BMAC_ADDR1, reg1); 2638 nw64_mac(BMAC_ADDR2, reg2); 2639 } 2640 } 2641 2642 static int niu_num_alt_addr(struct niu *np) 2643 { 2644 if (np->flags & NIU_FLAGS_XMAC) 2645 return XMAC_NUM_ALT_ADDR; 2646 else 2647 return BMAC_NUM_ALT_ADDR; 2648 } 2649 2650 static int niu_set_alt_mac(struct niu *np, int index, unsigned char *addr) 2651 { 2652 u16 reg0 = addr[4] << 8 | addr[5]; 2653 u16 reg1 = addr[2] << 8 | addr[3]; 2654 u16 reg2 = addr[0] << 8 | addr[1]; 2655 2656 if (index >= niu_num_alt_addr(np)) 2657 return -EINVAL; 2658 2659 if (np->flags & NIU_FLAGS_XMAC) { 2660 nw64_mac(XMAC_ALT_ADDR0(index), reg0); 2661 nw64_mac(XMAC_ALT_ADDR1(index), reg1); 2662 nw64_mac(XMAC_ALT_ADDR2(index), reg2); 2663 } else { 2664 nw64_mac(BMAC_ALT_ADDR0(index), reg0); 2665 nw64_mac(BMAC_ALT_ADDR1(index), reg1); 2666 nw64_mac(BMAC_ALT_ADDR2(index), reg2); 2667 } 2668 2669 return 0; 2670 } 2671 2672 static int niu_enable_alt_mac(struct niu *np, int index, int on) 2673 { 2674 unsigned long reg; 2675 u64 val, mask; 2676 2677 if (index >= niu_num_alt_addr(np)) 2678 return -EINVAL; 2679 2680 if (np->flags & NIU_FLAGS_XMAC) { 2681 reg = XMAC_ADDR_CMPEN; 2682 mask = 1 << index; 2683 } else { 2684 reg = BMAC_ADDR_CMPEN; 2685 mask = 1 << (index + 1); 2686 } 2687 2688 val = nr64_mac(reg); 2689 if (on) 2690 val |= mask; 2691 else 2692 val &= ~mask; 2693 nw64_mac(reg, val); 2694 2695 return 0; 2696 } 2697 2698 static void __set_rdc_table_num_hw(struct niu *np, unsigned long reg, 2699 int num, int mac_pref) 2700 { 2701 u64 val = nr64_mac(reg); 2702 val &= ~(HOST_INFO_MACRDCTBLN | HOST_INFO_MPR); 2703 val |= num; 2704 if (mac_pref) 2705 val |= HOST_INFO_MPR; 2706 nw64_mac(reg, val); 2707 } 2708 2709 static int __set_rdc_table_num(struct niu *np, 2710 int xmac_index, int bmac_index, 2711 int rdc_table_num, int mac_pref) 2712 { 2713 unsigned long reg; 2714 2715 if (rdc_table_num & ~HOST_INFO_MACRDCTBLN) 2716 return -EINVAL; 2717 if (np->flags & NIU_FLAGS_XMAC) 2718 reg = XMAC_HOST_INFO(xmac_index); 2719 else 2720 reg = BMAC_HOST_INFO(bmac_index); 2721 __set_rdc_table_num_hw(np, reg, rdc_table_num, mac_pref); 2722 return 0; 2723 } 2724 2725 static int niu_set_primary_mac_rdc_table(struct niu *np, int table_num, 2726 int mac_pref) 2727 { 2728 return __set_rdc_table_num(np, 17, 0, table_num, mac_pref); 2729 } 2730 2731 static int niu_set_multicast_mac_rdc_table(struct niu *np, int table_num, 2732 int mac_pref) 2733 { 2734 return __set_rdc_table_num(np, 16, 8, table_num, mac_pref); 2735 } 2736 2737 static int niu_set_alt_mac_rdc_table(struct niu *np, int idx, 2738 int table_num, int mac_pref) 2739 { 2740 if (idx >= niu_num_alt_addr(np)) 2741 return -EINVAL; 2742 return __set_rdc_table_num(np, idx, idx + 1, table_num, mac_pref); 2743 } 2744 2745 static u64 vlan_entry_set_parity(u64 reg_val) 2746 { 2747 u64 port01_mask; 2748 u64 port23_mask; 2749 2750 port01_mask = 0x00ff; 2751 port23_mask = 0xff00; 2752 2753 if (hweight64(reg_val & port01_mask) & 1) 2754 reg_val |= ENET_VLAN_TBL_PARITY0; 2755 else 2756 reg_val &= ~ENET_VLAN_TBL_PARITY0; 2757 2758 if (hweight64(reg_val & port23_mask) & 1) 2759 reg_val |= ENET_VLAN_TBL_PARITY1; 2760 else 2761 reg_val &= ~ENET_VLAN_TBL_PARITY1; 2762 2763 return reg_val; 2764 } 2765 2766 static void vlan_tbl_write(struct niu *np, unsigned long index, 2767 int port, int vpr, int rdc_table) 2768 { 2769 u64 reg_val = nr64(ENET_VLAN_TBL(index)); 2770 2771 reg_val &= ~((ENET_VLAN_TBL_VPR | 2772 ENET_VLAN_TBL_VLANRDCTBLN) << 2773 ENET_VLAN_TBL_SHIFT(port)); 2774 if (vpr) 2775 reg_val |= (ENET_VLAN_TBL_VPR << 2776 ENET_VLAN_TBL_SHIFT(port)); 2777 reg_val |= (rdc_table << ENET_VLAN_TBL_SHIFT(port)); 2778 2779 reg_val = vlan_entry_set_parity(reg_val); 2780 2781 nw64(ENET_VLAN_TBL(index), reg_val); 2782 } 2783 2784 static void vlan_tbl_clear(struct niu *np) 2785 { 2786 int i; 2787 2788 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) 2789 nw64(ENET_VLAN_TBL(i), 0); 2790 } 2791 2792 static int tcam_wait_bit(struct niu *np, u64 bit) 2793 { 2794 int limit = 1000; 2795 2796 while (--limit > 0) { 2797 if (nr64(TCAM_CTL) & bit) 2798 break; 2799 udelay(1); 2800 } 2801 if (limit <= 0) 2802 return -ENODEV; 2803 2804 return 0; 2805 } 2806 2807 static int tcam_flush(struct niu *np, int index) 2808 { 2809 nw64(TCAM_KEY_0, 0x00); 2810 nw64(TCAM_KEY_MASK_0, 0xff); 2811 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2812 2813 return tcam_wait_bit(np, TCAM_CTL_STAT); 2814 } 2815 2816 #if 0 2817 static int tcam_read(struct niu *np, int index, 2818 u64 *key, u64 *mask) 2819 { 2820 int err; 2821 2822 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_READ | index)); 2823 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2824 if (!err) { 2825 key[0] = nr64(TCAM_KEY_0); 2826 key[1] = nr64(TCAM_KEY_1); 2827 key[2] = nr64(TCAM_KEY_2); 2828 key[3] = nr64(TCAM_KEY_3); 2829 mask[0] = nr64(TCAM_KEY_MASK_0); 2830 mask[1] = nr64(TCAM_KEY_MASK_1); 2831 mask[2] = nr64(TCAM_KEY_MASK_2); 2832 mask[3] = nr64(TCAM_KEY_MASK_3); 2833 } 2834 return err; 2835 } 2836 #endif 2837 2838 static int tcam_write(struct niu *np, int index, 2839 u64 *key, u64 *mask) 2840 { 2841 nw64(TCAM_KEY_0, key[0]); 2842 nw64(TCAM_KEY_1, key[1]); 2843 nw64(TCAM_KEY_2, key[2]); 2844 nw64(TCAM_KEY_3, key[3]); 2845 nw64(TCAM_KEY_MASK_0, mask[0]); 2846 nw64(TCAM_KEY_MASK_1, mask[1]); 2847 nw64(TCAM_KEY_MASK_2, mask[2]); 2848 nw64(TCAM_KEY_MASK_3, mask[3]); 2849 nw64(TCAM_CTL, (TCAM_CTL_RWC_TCAM_WRITE | index)); 2850 2851 return tcam_wait_bit(np, TCAM_CTL_STAT); 2852 } 2853 2854 #if 0 2855 static int tcam_assoc_read(struct niu *np, int index, u64 *data) 2856 { 2857 int err; 2858 2859 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_READ | index)); 2860 err = tcam_wait_bit(np, TCAM_CTL_STAT); 2861 if (!err) 2862 *data = nr64(TCAM_KEY_1); 2863 2864 return err; 2865 } 2866 #endif 2867 2868 static int tcam_assoc_write(struct niu *np, int index, u64 assoc_data) 2869 { 2870 nw64(TCAM_KEY_1, assoc_data); 2871 nw64(TCAM_CTL, (TCAM_CTL_RWC_RAM_WRITE | index)); 2872 2873 return tcam_wait_bit(np, TCAM_CTL_STAT); 2874 } 2875 2876 static void tcam_enable(struct niu *np, int on) 2877 { 2878 u64 val = nr64(FFLP_CFG_1); 2879 2880 if (on) 2881 val &= ~FFLP_CFG_1_TCAM_DIS; 2882 else 2883 val |= FFLP_CFG_1_TCAM_DIS; 2884 nw64(FFLP_CFG_1, val); 2885 } 2886 2887 static void tcam_set_lat_and_ratio(struct niu *np, u64 latency, u64 ratio) 2888 { 2889 u64 val = nr64(FFLP_CFG_1); 2890 2891 val &= ~(FFLP_CFG_1_FFLPINITDONE | 2892 FFLP_CFG_1_CAMLAT | 2893 FFLP_CFG_1_CAMRATIO); 2894 val |= (latency << FFLP_CFG_1_CAMLAT_SHIFT); 2895 val |= (ratio << FFLP_CFG_1_CAMRATIO_SHIFT); 2896 nw64(FFLP_CFG_1, val); 2897 2898 val = nr64(FFLP_CFG_1); 2899 val |= FFLP_CFG_1_FFLPINITDONE; 2900 nw64(FFLP_CFG_1, val); 2901 } 2902 2903 static int tcam_user_eth_class_enable(struct niu *np, unsigned long class, 2904 int on) 2905 { 2906 unsigned long reg; 2907 u64 val; 2908 2909 if (class < CLASS_CODE_ETHERTYPE1 || 2910 class > CLASS_CODE_ETHERTYPE2) 2911 return -EINVAL; 2912 2913 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2914 val = nr64(reg); 2915 if (on) 2916 val |= L2_CLS_VLD; 2917 else 2918 val &= ~L2_CLS_VLD; 2919 nw64(reg, val); 2920 2921 return 0; 2922 } 2923 2924 #if 0 2925 static int tcam_user_eth_class_set(struct niu *np, unsigned long class, 2926 u64 ether_type) 2927 { 2928 unsigned long reg; 2929 u64 val; 2930 2931 if (class < CLASS_CODE_ETHERTYPE1 || 2932 class > CLASS_CODE_ETHERTYPE2 || 2933 (ether_type & ~(u64)0xffff) != 0) 2934 return -EINVAL; 2935 2936 reg = L2_CLS(class - CLASS_CODE_ETHERTYPE1); 2937 val = nr64(reg); 2938 val &= ~L2_CLS_ETYPE; 2939 val |= (ether_type << L2_CLS_ETYPE_SHIFT); 2940 nw64(reg, val); 2941 2942 return 0; 2943 } 2944 #endif 2945 2946 static int tcam_user_ip_class_enable(struct niu *np, unsigned long class, 2947 int on) 2948 { 2949 unsigned long reg; 2950 u64 val; 2951 2952 if (class < CLASS_CODE_USER_PROG1 || 2953 class > CLASS_CODE_USER_PROG4) 2954 return -EINVAL; 2955 2956 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2957 val = nr64(reg); 2958 if (on) 2959 val |= L3_CLS_VALID; 2960 else 2961 val &= ~L3_CLS_VALID; 2962 nw64(reg, val); 2963 2964 return 0; 2965 } 2966 2967 static int tcam_user_ip_class_set(struct niu *np, unsigned long class, 2968 int ipv6, u64 protocol_id, 2969 u64 tos_mask, u64 tos_val) 2970 { 2971 unsigned long reg; 2972 u64 val; 2973 2974 if (class < CLASS_CODE_USER_PROG1 || 2975 class > CLASS_CODE_USER_PROG4 || 2976 (protocol_id & ~(u64)0xff) != 0 || 2977 (tos_mask & ~(u64)0xff) != 0 || 2978 (tos_val & ~(u64)0xff) != 0) 2979 return -EINVAL; 2980 2981 reg = L3_CLS(class - CLASS_CODE_USER_PROG1); 2982 val = nr64(reg); 2983 val &= ~(L3_CLS_IPVER | L3_CLS_PID | 2984 L3_CLS_TOSMASK | L3_CLS_TOS); 2985 if (ipv6) 2986 val |= L3_CLS_IPVER; 2987 val |= (protocol_id << L3_CLS_PID_SHIFT); 2988 val |= (tos_mask << L3_CLS_TOSMASK_SHIFT); 2989 val |= (tos_val << L3_CLS_TOS_SHIFT); 2990 nw64(reg, val); 2991 2992 return 0; 2993 } 2994 2995 static int tcam_early_init(struct niu *np) 2996 { 2997 unsigned long i; 2998 int err; 2999 3000 tcam_enable(np, 0); 3001 tcam_set_lat_and_ratio(np, 3002 DEFAULT_TCAM_LATENCY, 3003 DEFAULT_TCAM_ACCESS_RATIO); 3004 for (i = CLASS_CODE_ETHERTYPE1; i <= CLASS_CODE_ETHERTYPE2; i++) { 3005 err = tcam_user_eth_class_enable(np, i, 0); 3006 if (err) 3007 return err; 3008 } 3009 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_USER_PROG4; i++) { 3010 err = tcam_user_ip_class_enable(np, i, 0); 3011 if (err) 3012 return err; 3013 } 3014 3015 return 0; 3016 } 3017 3018 static int tcam_flush_all(struct niu *np) 3019 { 3020 unsigned long i; 3021 3022 for (i = 0; i < np->parent->tcam_num_entries; i++) { 3023 int err = tcam_flush(np, i); 3024 if (err) 3025 return err; 3026 } 3027 return 0; 3028 } 3029 3030 static u64 hash_addr_regval(unsigned long index, unsigned long num_entries) 3031 { 3032 return (u64)index | (num_entries == 1 ? HASH_TBL_ADDR_AUTOINC : 0); 3033 } 3034 3035 #if 0 3036 static int hash_read(struct niu *np, unsigned long partition, 3037 unsigned long index, unsigned long num_entries, 3038 u64 *data) 3039 { 3040 u64 val = hash_addr_regval(index, num_entries); 3041 unsigned long i; 3042 3043 if (partition >= FCRAM_NUM_PARTITIONS || 3044 index + num_entries > FCRAM_SIZE) 3045 return -EINVAL; 3046 3047 nw64(HASH_TBL_ADDR(partition), val); 3048 for (i = 0; i < num_entries; i++) 3049 data[i] = nr64(HASH_TBL_DATA(partition)); 3050 3051 return 0; 3052 } 3053 #endif 3054 3055 static int hash_write(struct niu *np, unsigned long partition, 3056 unsigned long index, unsigned long num_entries, 3057 u64 *data) 3058 { 3059 u64 val = hash_addr_regval(index, num_entries); 3060 unsigned long i; 3061 3062 if (partition >= FCRAM_NUM_PARTITIONS || 3063 index + (num_entries * 8) > FCRAM_SIZE) 3064 return -EINVAL; 3065 3066 nw64(HASH_TBL_ADDR(partition), val); 3067 for (i = 0; i < num_entries; i++) 3068 nw64(HASH_TBL_DATA(partition), data[i]); 3069 3070 return 0; 3071 } 3072 3073 static void fflp_reset(struct niu *np) 3074 { 3075 u64 val; 3076 3077 nw64(FFLP_CFG_1, FFLP_CFG_1_PIO_FIO_RST); 3078 udelay(10); 3079 nw64(FFLP_CFG_1, 0); 3080 3081 val = FFLP_CFG_1_FCRAMOUTDR_NORMAL | FFLP_CFG_1_FFLPINITDONE; 3082 nw64(FFLP_CFG_1, val); 3083 } 3084 3085 static void fflp_set_timings(struct niu *np) 3086 { 3087 u64 val = nr64(FFLP_CFG_1); 3088 3089 val &= ~FFLP_CFG_1_FFLPINITDONE; 3090 val |= (DEFAULT_FCRAMRATIO << FFLP_CFG_1_FCRAMRATIO_SHIFT); 3091 nw64(FFLP_CFG_1, val); 3092 3093 val = nr64(FFLP_CFG_1); 3094 val |= FFLP_CFG_1_FFLPINITDONE; 3095 nw64(FFLP_CFG_1, val); 3096 3097 val = nr64(FCRAM_REF_TMR); 3098 val &= ~(FCRAM_REF_TMR_MAX | FCRAM_REF_TMR_MIN); 3099 val |= (DEFAULT_FCRAM_REFRESH_MAX << FCRAM_REF_TMR_MAX_SHIFT); 3100 val |= (DEFAULT_FCRAM_REFRESH_MIN << FCRAM_REF_TMR_MIN_SHIFT); 3101 nw64(FCRAM_REF_TMR, val); 3102 } 3103 3104 static int fflp_set_partition(struct niu *np, u64 partition, 3105 u64 mask, u64 base, int enable) 3106 { 3107 unsigned long reg; 3108 u64 val; 3109 3110 if (partition >= FCRAM_NUM_PARTITIONS || 3111 (mask & ~(u64)0x1f) != 0 || 3112 (base & ~(u64)0x1f) != 0) 3113 return -EINVAL; 3114 3115 reg = FLW_PRT_SEL(partition); 3116 3117 val = nr64(reg); 3118 val &= ~(FLW_PRT_SEL_EXT | FLW_PRT_SEL_MASK | FLW_PRT_SEL_BASE); 3119 val |= (mask << FLW_PRT_SEL_MASK_SHIFT); 3120 val |= (base << FLW_PRT_SEL_BASE_SHIFT); 3121 if (enable) 3122 val |= FLW_PRT_SEL_EXT; 3123 nw64(reg, val); 3124 3125 return 0; 3126 } 3127 3128 static int fflp_disable_all_partitions(struct niu *np) 3129 { 3130 unsigned long i; 3131 3132 for (i = 0; i < FCRAM_NUM_PARTITIONS; i++) { 3133 int err = fflp_set_partition(np, 0, 0, 0, 0); 3134 if (err) 3135 return err; 3136 } 3137 return 0; 3138 } 3139 3140 static void fflp_llcsnap_enable(struct niu *np, int on) 3141 { 3142 u64 val = nr64(FFLP_CFG_1); 3143 3144 if (on) 3145 val |= FFLP_CFG_1_LLCSNAP; 3146 else 3147 val &= ~FFLP_CFG_1_LLCSNAP; 3148 nw64(FFLP_CFG_1, val); 3149 } 3150 3151 static void fflp_errors_enable(struct niu *np, int on) 3152 { 3153 u64 val = nr64(FFLP_CFG_1); 3154 3155 if (on) 3156 val &= ~FFLP_CFG_1_ERRORDIS; 3157 else 3158 val |= FFLP_CFG_1_ERRORDIS; 3159 nw64(FFLP_CFG_1, val); 3160 } 3161 3162 static int fflp_hash_clear(struct niu *np) 3163 { 3164 struct fcram_hash_ipv4 ent; 3165 unsigned long i; 3166 3167 /* IPV4 hash entry with valid bit clear, rest is don't care. */ 3168 memset(&ent, 0, sizeof(ent)); 3169 ent.header = HASH_HEADER_EXT; 3170 3171 for (i = 0; i < FCRAM_SIZE; i += sizeof(ent)) { 3172 int err = hash_write(np, 0, i, 1, (u64 *) &ent); 3173 if (err) 3174 return err; 3175 } 3176 return 0; 3177 } 3178 3179 static int fflp_early_init(struct niu *np) 3180 { 3181 struct niu_parent *parent; 3182 unsigned long flags; 3183 int err; 3184 3185 niu_lock_parent(np, flags); 3186 3187 parent = np->parent; 3188 err = 0; 3189 if (!(parent->flags & PARENT_FLGS_CLS_HWINIT)) { 3190 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3191 fflp_reset(np); 3192 fflp_set_timings(np); 3193 err = fflp_disable_all_partitions(np); 3194 if (err) { 3195 netif_printk(np, probe, KERN_DEBUG, np->dev, 3196 "fflp_disable_all_partitions failed, err=%d\n", 3197 err); 3198 goto out; 3199 } 3200 } 3201 3202 err = tcam_early_init(np); 3203 if (err) { 3204 netif_printk(np, probe, KERN_DEBUG, np->dev, 3205 "tcam_early_init failed, err=%d\n", err); 3206 goto out; 3207 } 3208 fflp_llcsnap_enable(np, 1); 3209 fflp_errors_enable(np, 0); 3210 nw64(H1POLY, 0); 3211 nw64(H2POLY, 0); 3212 3213 err = tcam_flush_all(np); 3214 if (err) { 3215 netif_printk(np, probe, KERN_DEBUG, np->dev, 3216 "tcam_flush_all failed, err=%d\n", err); 3217 goto out; 3218 } 3219 if (np->parent->plat_type != PLAT_TYPE_NIU) { 3220 err = fflp_hash_clear(np); 3221 if (err) { 3222 netif_printk(np, probe, KERN_DEBUG, np->dev, 3223 "fflp_hash_clear failed, err=%d\n", 3224 err); 3225 goto out; 3226 } 3227 } 3228 3229 vlan_tbl_clear(np); 3230 3231 parent->flags |= PARENT_FLGS_CLS_HWINIT; 3232 } 3233 out: 3234 niu_unlock_parent(np, flags); 3235 return err; 3236 } 3237 3238 static int niu_set_flow_key(struct niu *np, unsigned long class_code, u64 key) 3239 { 3240 if (class_code < CLASS_CODE_USER_PROG1 || 3241 class_code > CLASS_CODE_SCTP_IPV6) 3242 return -EINVAL; 3243 3244 nw64(FLOW_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3245 return 0; 3246 } 3247 3248 static int niu_set_tcam_key(struct niu *np, unsigned long class_code, u64 key) 3249 { 3250 if (class_code < CLASS_CODE_USER_PROG1 || 3251 class_code > CLASS_CODE_SCTP_IPV6) 3252 return -EINVAL; 3253 3254 nw64(TCAM_KEY(class_code - CLASS_CODE_USER_PROG1), key); 3255 return 0; 3256 } 3257 3258 /* Entries for the ports are interleaved in the TCAM */ 3259 static u16 tcam_get_index(struct niu *np, u16 idx) 3260 { 3261 /* One entry reserved for IP fragment rule */ 3262 if (idx >= (np->clas.tcam_sz - 1)) 3263 idx = 0; 3264 return np->clas.tcam_top + ((idx+1) * np->parent->num_ports); 3265 } 3266 3267 static u16 tcam_get_size(struct niu *np) 3268 { 3269 /* One entry reserved for IP fragment rule */ 3270 return np->clas.tcam_sz - 1; 3271 } 3272 3273 static u16 tcam_get_valid_entry_cnt(struct niu *np) 3274 { 3275 /* One entry reserved for IP fragment rule */ 3276 return np->clas.tcam_valid_entries - 1; 3277 } 3278 3279 static void niu_rx_skb_append(struct sk_buff *skb, struct page *page, 3280 u32 offset, u32 size, u32 truesize) 3281 { 3282 skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags, page, offset, size); 3283 3284 skb->len += size; 3285 skb->data_len += size; 3286 skb->truesize += truesize; 3287 } 3288 3289 static unsigned int niu_hash_rxaddr(struct rx_ring_info *rp, u64 a) 3290 { 3291 a >>= PAGE_SHIFT; 3292 a ^= (a >> ilog2(MAX_RBR_RING_SIZE)); 3293 3294 return a & (MAX_RBR_RING_SIZE - 1); 3295 } 3296 3297 static struct page *niu_find_rxpage(struct rx_ring_info *rp, u64 addr, 3298 struct page ***link) 3299 { 3300 unsigned int h = niu_hash_rxaddr(rp, addr); 3301 struct page *p, **pp; 3302 3303 addr &= PAGE_MASK; 3304 pp = &rp->rxhash[h]; 3305 for (; (p = *pp) != NULL; pp = &niu_next_page(p)) { 3306 if (p->private == addr) { 3307 *link = pp; 3308 goto found; 3309 } 3310 } 3311 BUG(); 3312 3313 found: 3314 return p; 3315 } 3316 3317 static void niu_hash_page(struct rx_ring_info *rp, struct page *page, u64 base) 3318 { 3319 unsigned int h = niu_hash_rxaddr(rp, base); 3320 3321 page->private = base; 3322 niu_next_page(page) = rp->rxhash[h]; 3323 rp->rxhash[h] = page; 3324 } 3325 3326 static int niu_rbr_add_page(struct niu *np, struct rx_ring_info *rp, 3327 gfp_t mask, int start_index) 3328 { 3329 struct page *page; 3330 u64 addr; 3331 int i; 3332 3333 page = alloc_page(mask); 3334 if (!page) 3335 return -ENOMEM; 3336 3337 addr = np->ops->map_page(np->device, page, 0, 3338 PAGE_SIZE, DMA_FROM_DEVICE); 3339 if (np->ops->mapping_error(np->device, addr)) { 3340 __free_page(page); 3341 return -ENOMEM; 3342 } 3343 3344 niu_hash_page(rp, page, addr); 3345 if (rp->rbr_blocks_per_page > 1) 3346 page_ref_add(page, rp->rbr_blocks_per_page - 1); 3347 3348 for (i = 0; i < rp->rbr_blocks_per_page; i++) { 3349 __le32 *rbr = &rp->rbr[start_index + i]; 3350 3351 *rbr = cpu_to_le32(addr >> RBR_DESCR_ADDR_SHIFT); 3352 addr += rp->rbr_block_size; 3353 } 3354 3355 return 0; 3356 } 3357 3358 static void niu_rbr_refill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3359 { 3360 int index = rp->rbr_index; 3361 3362 rp->rbr_pending++; 3363 if ((rp->rbr_pending % rp->rbr_blocks_per_page) == 0) { 3364 int err = niu_rbr_add_page(np, rp, mask, index); 3365 3366 if (unlikely(err)) { 3367 rp->rbr_pending--; 3368 return; 3369 } 3370 3371 rp->rbr_index += rp->rbr_blocks_per_page; 3372 BUG_ON(rp->rbr_index > rp->rbr_table_size); 3373 if (rp->rbr_index == rp->rbr_table_size) 3374 rp->rbr_index = 0; 3375 3376 if (rp->rbr_pending >= rp->rbr_kick_thresh) { 3377 nw64(RBR_KICK(rp->rx_channel), rp->rbr_pending); 3378 rp->rbr_pending = 0; 3379 } 3380 } 3381 } 3382 3383 static int niu_rx_pkt_ignore(struct niu *np, struct rx_ring_info *rp) 3384 { 3385 unsigned int index = rp->rcr_index; 3386 int num_rcr = 0; 3387 3388 rp->rx_dropped++; 3389 while (1) { 3390 struct page *page, **link; 3391 u64 addr, val; 3392 u32 rcr_size; 3393 3394 num_rcr++; 3395 3396 val = le64_to_cpup(&rp->rcr[index]); 3397 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3398 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3399 page = niu_find_rxpage(rp, addr, &link); 3400 3401 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3402 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3403 if ((page->private + PAGE_SIZE) - rcr_size == addr) { 3404 *link = niu_next_page(page); 3405 np->ops->unmap_page(np->device, page->private, 3406 PAGE_SIZE, DMA_FROM_DEVICE); 3407 page->private = 0; 3408 niu_next_page(page) = NULL; 3409 __free_page(page); 3410 rp->rbr_refill_pending++; 3411 } 3412 3413 index = NEXT_RCR(rp, index); 3414 if (!(val & RCR_ENTRY_MULTI)) 3415 break; 3416 3417 } 3418 rp->rcr_index = index; 3419 3420 return num_rcr; 3421 } 3422 3423 static int niu_process_rx_pkt(struct napi_struct *napi, struct niu *np, 3424 struct rx_ring_info *rp) 3425 { 3426 unsigned int index = rp->rcr_index; 3427 struct rx_pkt_hdr1 *rh; 3428 struct sk_buff *skb; 3429 int len, num_rcr; 3430 3431 skb = netdev_alloc_skb(np->dev, RX_SKB_ALLOC_SIZE); 3432 if (unlikely(!skb)) 3433 return niu_rx_pkt_ignore(np, rp); 3434 3435 num_rcr = 0; 3436 while (1) { 3437 struct page *page, **link; 3438 u32 rcr_size, append_size; 3439 u64 addr, val, off; 3440 3441 num_rcr++; 3442 3443 val = le64_to_cpup(&rp->rcr[index]); 3444 3445 len = (val & RCR_ENTRY_L2_LEN) >> 3446 RCR_ENTRY_L2_LEN_SHIFT; 3447 append_size = len + ETH_HLEN + ETH_FCS_LEN; 3448 3449 addr = (val & RCR_ENTRY_PKT_BUF_ADDR) << 3450 RCR_ENTRY_PKT_BUF_ADDR_SHIFT; 3451 page = niu_find_rxpage(rp, addr, &link); 3452 3453 rcr_size = rp->rbr_sizes[(val & RCR_ENTRY_PKTBUFSZ) >> 3454 RCR_ENTRY_PKTBUFSZ_SHIFT]; 3455 3456 off = addr & ~PAGE_MASK; 3457 if (num_rcr == 1) { 3458 int ptype; 3459 3460 ptype = (val >> RCR_ENTRY_PKT_TYPE_SHIFT); 3461 if ((ptype == RCR_PKT_TYPE_TCP || 3462 ptype == RCR_PKT_TYPE_UDP) && 3463 !(val & (RCR_ENTRY_NOPORT | 3464 RCR_ENTRY_ERROR))) 3465 skb->ip_summed = CHECKSUM_UNNECESSARY; 3466 else 3467 skb_checksum_none_assert(skb); 3468 } else if (!(val & RCR_ENTRY_MULTI)) 3469 append_size = append_size - skb->len; 3470 3471 niu_rx_skb_append(skb, page, off, append_size, rcr_size); 3472 if ((page->private + rp->rbr_block_size) - rcr_size == addr) { 3473 *link = niu_next_page(page); 3474 np->ops->unmap_page(np->device, page->private, 3475 PAGE_SIZE, DMA_FROM_DEVICE); 3476 page->private = 0; 3477 niu_next_page(page) = NULL; 3478 rp->rbr_refill_pending++; 3479 } else 3480 get_page(page); 3481 3482 index = NEXT_RCR(rp, index); 3483 if (!(val & RCR_ENTRY_MULTI)) 3484 break; 3485 3486 } 3487 rp->rcr_index = index; 3488 3489 len += sizeof(*rh); 3490 len = min_t(int, len, sizeof(*rh) + VLAN_ETH_HLEN); 3491 __pskb_pull_tail(skb, len); 3492 3493 rh = (struct rx_pkt_hdr1 *) skb->data; 3494 if (np->dev->features & NETIF_F_RXHASH) 3495 skb_set_hash(skb, 3496 ((u32)rh->hashval2_0 << 24 | 3497 (u32)rh->hashval2_1 << 16 | 3498 (u32)rh->hashval1_1 << 8 | 3499 (u32)rh->hashval1_2 << 0), 3500 PKT_HASH_TYPE_L3); 3501 skb_pull(skb, sizeof(*rh)); 3502 3503 rp->rx_packets++; 3504 rp->rx_bytes += skb->len; 3505 3506 skb->protocol = eth_type_trans(skb, np->dev); 3507 skb_record_rx_queue(skb, rp->rx_channel); 3508 napi_gro_receive(napi, skb); 3509 3510 return num_rcr; 3511 } 3512 3513 static int niu_rbr_fill(struct niu *np, struct rx_ring_info *rp, gfp_t mask) 3514 { 3515 int blocks_per_page = rp->rbr_blocks_per_page; 3516 int err, index = rp->rbr_index; 3517 3518 err = 0; 3519 while (index < (rp->rbr_table_size - blocks_per_page)) { 3520 err = niu_rbr_add_page(np, rp, mask, index); 3521 if (unlikely(err)) 3522 break; 3523 3524 index += blocks_per_page; 3525 } 3526 3527 rp->rbr_index = index; 3528 return err; 3529 } 3530 3531 static void niu_rbr_free(struct niu *np, struct rx_ring_info *rp) 3532 { 3533 int i; 3534 3535 for (i = 0; i < MAX_RBR_RING_SIZE; i++) { 3536 struct page *page; 3537 3538 page = rp->rxhash[i]; 3539 while (page) { 3540 struct page *next = niu_next_page(page); 3541 u64 base = page->private; 3542 3543 np->ops->unmap_page(np->device, base, PAGE_SIZE, 3544 DMA_FROM_DEVICE); 3545 page->private = 0; 3546 niu_next_page(page) = NULL; 3547 3548 __free_page(page); 3549 3550 page = next; 3551 } 3552 } 3553 3554 for (i = 0; i < rp->rbr_table_size; i++) 3555 rp->rbr[i] = cpu_to_le32(0); 3556 rp->rbr_index = 0; 3557 } 3558 3559 static int release_tx_packet(struct niu *np, struct tx_ring_info *rp, int idx) 3560 { 3561 struct tx_buff_info *tb = &rp->tx_buffs[idx]; 3562 struct sk_buff *skb = tb->skb; 3563 struct tx_pkt_hdr *tp; 3564 u64 tx_flags; 3565 int i, len; 3566 3567 tp = (struct tx_pkt_hdr *) skb->data; 3568 tx_flags = le64_to_cpup(&tp->flags); 3569 3570 rp->tx_packets++; 3571 rp->tx_bytes += (((tx_flags & TXHDR_LEN) >> TXHDR_LEN_SHIFT) - 3572 ((tx_flags & TXHDR_PAD) / 2)); 3573 3574 len = skb_headlen(skb); 3575 np->ops->unmap_single(np->device, tb->mapping, 3576 len, DMA_TO_DEVICE); 3577 3578 if (le64_to_cpu(rp->descr[idx]) & TX_DESC_MARK) 3579 rp->mark_pending--; 3580 3581 tb->skb = NULL; 3582 do { 3583 idx = NEXT_TX(rp, idx); 3584 len -= MAX_TX_DESC_LEN; 3585 } while (len > 0); 3586 3587 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 3588 tb = &rp->tx_buffs[idx]; 3589 BUG_ON(tb->skb != NULL); 3590 np->ops->unmap_page(np->device, tb->mapping, 3591 skb_frag_size(&skb_shinfo(skb)->frags[i]), 3592 DMA_TO_DEVICE); 3593 idx = NEXT_TX(rp, idx); 3594 } 3595 3596 dev_kfree_skb(skb); 3597 3598 return idx; 3599 } 3600 3601 #define NIU_TX_WAKEUP_THRESH(rp) ((rp)->pending / 4) 3602 3603 static void niu_tx_work(struct niu *np, struct tx_ring_info *rp) 3604 { 3605 struct netdev_queue *txq; 3606 u16 pkt_cnt, tmp; 3607 int cons, index; 3608 u64 cs; 3609 3610 index = (rp - np->tx_rings); 3611 txq = netdev_get_tx_queue(np->dev, index); 3612 3613 cs = rp->tx_cs; 3614 if (unlikely(!(cs & (TX_CS_MK | TX_CS_MMK)))) 3615 goto out; 3616 3617 tmp = pkt_cnt = (cs & TX_CS_PKT_CNT) >> TX_CS_PKT_CNT_SHIFT; 3618 pkt_cnt = (pkt_cnt - rp->last_pkt_cnt) & 3619 (TX_CS_PKT_CNT >> TX_CS_PKT_CNT_SHIFT); 3620 3621 rp->last_pkt_cnt = tmp; 3622 3623 cons = rp->cons; 3624 3625 netif_printk(np, tx_done, KERN_DEBUG, np->dev, 3626 "%s() pkt_cnt[%u] cons[%d]\n", __func__, pkt_cnt, cons); 3627 3628 while (pkt_cnt--) 3629 cons = release_tx_packet(np, rp, cons); 3630 3631 rp->cons = cons; 3632 smp_mb(); 3633 3634 out: 3635 if (unlikely(netif_tx_queue_stopped(txq) && 3636 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)))) { 3637 __netif_tx_lock(txq, smp_processor_id()); 3638 if (netif_tx_queue_stopped(txq) && 3639 (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp))) 3640 netif_tx_wake_queue(txq); 3641 __netif_tx_unlock(txq); 3642 } 3643 } 3644 3645 static inline void niu_sync_rx_discard_stats(struct niu *np, 3646 struct rx_ring_info *rp, 3647 const int limit) 3648 { 3649 /* This elaborate scheme is needed for reading the RX discard 3650 * counters, as they are only 16-bit and can overflow quickly, 3651 * and because the overflow indication bit is not usable as 3652 * the counter value does not wrap, but remains at max value 3653 * 0xFFFF. 3654 * 3655 * In theory and in practice counters can be lost in between 3656 * reading nr64() and clearing the counter nw64(). For this 3657 * reason, the number of counter clearings nw64() is 3658 * limited/reduced though the limit parameter. 3659 */ 3660 int rx_channel = rp->rx_channel; 3661 u32 misc, wred; 3662 3663 /* RXMISC (Receive Miscellaneous Discard Count), covers the 3664 * following discard events: IPP (Input Port Process), 3665 * FFLP/TCAM, Full RCR (Receive Completion Ring) RBR (Receive 3666 * Block Ring) prefetch buffer is empty. 3667 */ 3668 misc = nr64(RXMISC(rx_channel)); 3669 if (unlikely((misc & RXMISC_COUNT) > limit)) { 3670 nw64(RXMISC(rx_channel), 0); 3671 rp->rx_errors += misc & RXMISC_COUNT; 3672 3673 if (unlikely(misc & RXMISC_OFLOW)) 3674 dev_err(np->device, "rx-%d: Counter overflow RXMISC discard\n", 3675 rx_channel); 3676 3677 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3678 "rx-%d: MISC drop=%u over=%u\n", 3679 rx_channel, misc, misc-limit); 3680 } 3681 3682 /* WRED (Weighted Random Early Discard) by hardware */ 3683 wred = nr64(RED_DIS_CNT(rx_channel)); 3684 if (unlikely((wred & RED_DIS_CNT_COUNT) > limit)) { 3685 nw64(RED_DIS_CNT(rx_channel), 0); 3686 rp->rx_dropped += wred & RED_DIS_CNT_COUNT; 3687 3688 if (unlikely(wred & RED_DIS_CNT_OFLOW)) 3689 dev_err(np->device, "rx-%d: Counter overflow WRED discard\n", rx_channel); 3690 3691 netif_printk(np, rx_err, KERN_DEBUG, np->dev, 3692 "rx-%d: WRED drop=%u over=%u\n", 3693 rx_channel, wred, wred-limit); 3694 } 3695 } 3696 3697 static int niu_rx_work(struct napi_struct *napi, struct niu *np, 3698 struct rx_ring_info *rp, int budget) 3699 { 3700 int qlen, rcr_done = 0, work_done = 0; 3701 struct rxdma_mailbox *mbox = rp->mbox; 3702 u64 stat; 3703 3704 #if 1 3705 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3706 qlen = nr64(RCRSTAT_A(rp->rx_channel)) & RCRSTAT_A_QLEN; 3707 #else 3708 stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 3709 qlen = (le64_to_cpup(&mbox->rcrstat_a) & RCRSTAT_A_QLEN); 3710 #endif 3711 mbox->rx_dma_ctl_stat = 0; 3712 mbox->rcrstat_a = 0; 3713 3714 netif_printk(np, rx_status, KERN_DEBUG, np->dev, 3715 "%s(chan[%d]), stat[%llx] qlen=%d\n", 3716 __func__, rp->rx_channel, (unsigned long long)stat, qlen); 3717 3718 rcr_done = work_done = 0; 3719 qlen = min(qlen, budget); 3720 while (work_done < qlen) { 3721 rcr_done += niu_process_rx_pkt(napi, np, rp); 3722 work_done++; 3723 } 3724 3725 if (rp->rbr_refill_pending >= rp->rbr_kick_thresh) { 3726 unsigned int i; 3727 3728 for (i = 0; i < rp->rbr_refill_pending; i++) 3729 niu_rbr_refill(np, rp, GFP_ATOMIC); 3730 rp->rbr_refill_pending = 0; 3731 } 3732 3733 stat = (RX_DMA_CTL_STAT_MEX | 3734 ((u64)work_done << RX_DMA_CTL_STAT_PKTREAD_SHIFT) | 3735 ((u64)rcr_done << RX_DMA_CTL_STAT_PTRREAD_SHIFT)); 3736 3737 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat); 3738 3739 /* Only sync discards stats when qlen indicate potential for drops */ 3740 if (qlen > 10) 3741 niu_sync_rx_discard_stats(np, rp, 0x7FFF); 3742 3743 return work_done; 3744 } 3745 3746 static int niu_poll_core(struct niu *np, struct niu_ldg *lp, int budget) 3747 { 3748 u64 v0 = lp->v0; 3749 u32 tx_vec = (v0 >> 32); 3750 u32 rx_vec = (v0 & 0xffffffff); 3751 int i, work_done = 0; 3752 3753 netif_printk(np, intr, KERN_DEBUG, np->dev, 3754 "%s() v0[%016llx]\n", __func__, (unsigned long long)v0); 3755 3756 for (i = 0; i < np->num_tx_rings; i++) { 3757 struct tx_ring_info *rp = &np->tx_rings[i]; 3758 if (tx_vec & (1 << rp->tx_channel)) 3759 niu_tx_work(np, rp); 3760 nw64(LD_IM0(LDN_TXDMA(rp->tx_channel)), 0); 3761 } 3762 3763 for (i = 0; i < np->num_rx_rings; i++) { 3764 struct rx_ring_info *rp = &np->rx_rings[i]; 3765 3766 if (rx_vec & (1 << rp->rx_channel)) { 3767 int this_work_done; 3768 3769 this_work_done = niu_rx_work(&lp->napi, np, rp, 3770 budget); 3771 3772 budget -= this_work_done; 3773 work_done += this_work_done; 3774 } 3775 nw64(LD_IM0(LDN_RXDMA(rp->rx_channel)), 0); 3776 } 3777 3778 return work_done; 3779 } 3780 3781 static int niu_poll(struct napi_struct *napi, int budget) 3782 { 3783 struct niu_ldg *lp = container_of(napi, struct niu_ldg, napi); 3784 struct niu *np = lp->np; 3785 int work_done; 3786 3787 work_done = niu_poll_core(np, lp, budget); 3788 3789 if (work_done < budget) { 3790 napi_complete_done(napi, work_done); 3791 niu_ldg_rearm(np, lp, 1); 3792 } 3793 return work_done; 3794 } 3795 3796 static void niu_log_rxchan_errors(struct niu *np, struct rx_ring_info *rp, 3797 u64 stat) 3798 { 3799 netdev_err(np->dev, "RX channel %u errors ( ", rp->rx_channel); 3800 3801 if (stat & RX_DMA_CTL_STAT_RBR_TMOUT) 3802 pr_cont("RBR_TMOUT "); 3803 if (stat & RX_DMA_CTL_STAT_RSP_CNT_ERR) 3804 pr_cont("RSP_CNT "); 3805 if (stat & RX_DMA_CTL_STAT_BYTE_EN_BUS) 3806 pr_cont("BYTE_EN_BUS "); 3807 if (stat & RX_DMA_CTL_STAT_RSP_DAT_ERR) 3808 pr_cont("RSP_DAT "); 3809 if (stat & RX_DMA_CTL_STAT_RCR_ACK_ERR) 3810 pr_cont("RCR_ACK "); 3811 if (stat & RX_DMA_CTL_STAT_RCR_SHA_PAR) 3812 pr_cont("RCR_SHA_PAR "); 3813 if (stat & RX_DMA_CTL_STAT_RBR_PRE_PAR) 3814 pr_cont("RBR_PRE_PAR "); 3815 if (stat & RX_DMA_CTL_STAT_CONFIG_ERR) 3816 pr_cont("CONFIG "); 3817 if (stat & RX_DMA_CTL_STAT_RCRINCON) 3818 pr_cont("RCRINCON "); 3819 if (stat & RX_DMA_CTL_STAT_RCRFULL) 3820 pr_cont("RCRFULL "); 3821 if (stat & RX_DMA_CTL_STAT_RBRFULL) 3822 pr_cont("RBRFULL "); 3823 if (stat & RX_DMA_CTL_STAT_RBRLOGPAGE) 3824 pr_cont("RBRLOGPAGE "); 3825 if (stat & RX_DMA_CTL_STAT_CFIGLOGPAGE) 3826 pr_cont("CFIGLOGPAGE "); 3827 if (stat & RX_DMA_CTL_STAT_DC_FIFO_ERR) 3828 pr_cont("DC_FIDO "); 3829 3830 pr_cont(")\n"); 3831 } 3832 3833 static int niu_rx_error(struct niu *np, struct rx_ring_info *rp) 3834 { 3835 u64 stat = nr64(RX_DMA_CTL_STAT(rp->rx_channel)); 3836 int err = 0; 3837 3838 3839 if (stat & (RX_DMA_CTL_STAT_CHAN_FATAL | 3840 RX_DMA_CTL_STAT_PORT_FATAL)) 3841 err = -EINVAL; 3842 3843 if (err) { 3844 netdev_err(np->dev, "RX channel %u error, stat[%llx]\n", 3845 rp->rx_channel, 3846 (unsigned long long) stat); 3847 3848 niu_log_rxchan_errors(np, rp, stat); 3849 } 3850 3851 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 3852 stat & RX_DMA_CTL_WRITE_CLEAR_ERRS); 3853 3854 return err; 3855 } 3856 3857 static void niu_log_txchan_errors(struct niu *np, struct tx_ring_info *rp, 3858 u64 cs) 3859 { 3860 netdev_err(np->dev, "TX channel %u errors ( ", rp->tx_channel); 3861 3862 if (cs & TX_CS_MBOX_ERR) 3863 pr_cont("MBOX "); 3864 if (cs & TX_CS_PKT_SIZE_ERR) 3865 pr_cont("PKT_SIZE "); 3866 if (cs & TX_CS_TX_RING_OFLOW) 3867 pr_cont("TX_RING_OFLOW "); 3868 if (cs & TX_CS_PREF_BUF_PAR_ERR) 3869 pr_cont("PREF_BUF_PAR "); 3870 if (cs & TX_CS_NACK_PREF) 3871 pr_cont("NACK_PREF "); 3872 if (cs & TX_CS_NACK_PKT_RD) 3873 pr_cont("NACK_PKT_RD "); 3874 if (cs & TX_CS_CONF_PART_ERR) 3875 pr_cont("CONF_PART "); 3876 if (cs & TX_CS_PKT_PRT_ERR) 3877 pr_cont("PKT_PTR "); 3878 3879 pr_cont(")\n"); 3880 } 3881 3882 static int niu_tx_error(struct niu *np, struct tx_ring_info *rp) 3883 { 3884 u64 cs, logh, logl; 3885 3886 cs = nr64(TX_CS(rp->tx_channel)); 3887 logh = nr64(TX_RNG_ERR_LOGH(rp->tx_channel)); 3888 logl = nr64(TX_RNG_ERR_LOGL(rp->tx_channel)); 3889 3890 netdev_err(np->dev, "TX channel %u error, cs[%llx] logh[%llx] logl[%llx]\n", 3891 rp->tx_channel, 3892 (unsigned long long)cs, 3893 (unsigned long long)logh, 3894 (unsigned long long)logl); 3895 3896 niu_log_txchan_errors(np, rp, cs); 3897 3898 return -ENODEV; 3899 } 3900 3901 static int niu_mif_interrupt(struct niu *np) 3902 { 3903 u64 mif_status = nr64(MIF_STATUS); 3904 int phy_mdint = 0; 3905 3906 if (np->flags & NIU_FLAGS_XMAC) { 3907 u64 xrxmac_stat = nr64_mac(XRXMAC_STATUS); 3908 3909 if (xrxmac_stat & XRXMAC_STATUS_PHY_MDINT) 3910 phy_mdint = 1; 3911 } 3912 3913 netdev_err(np->dev, "MIF interrupt, stat[%llx] phy_mdint(%d)\n", 3914 (unsigned long long)mif_status, phy_mdint); 3915 3916 return -ENODEV; 3917 } 3918 3919 static void niu_xmac_interrupt(struct niu *np) 3920 { 3921 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 3922 u64 val; 3923 3924 val = nr64_mac(XTXMAC_STATUS); 3925 if (val & XTXMAC_STATUS_FRAME_CNT_EXP) 3926 mp->tx_frames += TXMAC_FRM_CNT_COUNT; 3927 if (val & XTXMAC_STATUS_BYTE_CNT_EXP) 3928 mp->tx_bytes += TXMAC_BYTE_CNT_COUNT; 3929 if (val & XTXMAC_STATUS_TXFIFO_XFR_ERR) 3930 mp->tx_fifo_errors++; 3931 if (val & XTXMAC_STATUS_TXMAC_OFLOW) 3932 mp->tx_overflow_errors++; 3933 if (val & XTXMAC_STATUS_MAX_PSIZE_ERR) 3934 mp->tx_max_pkt_size_errors++; 3935 if (val & XTXMAC_STATUS_TXMAC_UFLOW) 3936 mp->tx_underflow_errors++; 3937 3938 val = nr64_mac(XRXMAC_STATUS); 3939 if (val & XRXMAC_STATUS_LCL_FLT_STATUS) 3940 mp->rx_local_faults++; 3941 if (val & XRXMAC_STATUS_RFLT_DET) 3942 mp->rx_remote_faults++; 3943 if (val & XRXMAC_STATUS_LFLT_CNT_EXP) 3944 mp->rx_link_faults += LINK_FAULT_CNT_COUNT; 3945 if (val & XRXMAC_STATUS_ALIGNERR_CNT_EXP) 3946 mp->rx_align_errors += RXMAC_ALIGN_ERR_CNT_COUNT; 3947 if (val & XRXMAC_STATUS_RXFRAG_CNT_EXP) 3948 mp->rx_frags += RXMAC_FRAG_CNT_COUNT; 3949 if (val & XRXMAC_STATUS_RXMULTF_CNT_EXP) 3950 mp->rx_mcasts += RXMAC_MC_FRM_CNT_COUNT; 3951 if (val & XRXMAC_STATUS_RXBCAST_CNT_EXP) 3952 mp->rx_bcasts += RXMAC_BC_FRM_CNT_COUNT; 3953 if (val & XRXMAC_STATUS_RXHIST1_CNT_EXP) 3954 mp->rx_hist_cnt1 += RXMAC_HIST_CNT1_COUNT; 3955 if (val & XRXMAC_STATUS_RXHIST2_CNT_EXP) 3956 mp->rx_hist_cnt2 += RXMAC_HIST_CNT2_COUNT; 3957 if (val & XRXMAC_STATUS_RXHIST3_CNT_EXP) 3958 mp->rx_hist_cnt3 += RXMAC_HIST_CNT3_COUNT; 3959 if (val & XRXMAC_STATUS_RXHIST4_CNT_EXP) 3960 mp->rx_hist_cnt4 += RXMAC_HIST_CNT4_COUNT; 3961 if (val & XRXMAC_STATUS_RXHIST5_CNT_EXP) 3962 mp->rx_hist_cnt5 += RXMAC_HIST_CNT5_COUNT; 3963 if (val & XRXMAC_STATUS_RXHIST6_CNT_EXP) 3964 mp->rx_hist_cnt6 += RXMAC_HIST_CNT6_COUNT; 3965 if (val & XRXMAC_STATUS_RXHIST7_CNT_EXP) 3966 mp->rx_hist_cnt7 += RXMAC_HIST_CNT7_COUNT; 3967 if (val & XRXMAC_STATUS_RXOCTET_CNT_EXP) 3968 mp->rx_octets += RXMAC_BT_CNT_COUNT; 3969 if (val & XRXMAC_STATUS_CVIOLERR_CNT_EXP) 3970 mp->rx_code_violations += RXMAC_CD_VIO_CNT_COUNT; 3971 if (val & XRXMAC_STATUS_LENERR_CNT_EXP) 3972 mp->rx_len_errors += RXMAC_MPSZER_CNT_COUNT; 3973 if (val & XRXMAC_STATUS_CRCERR_CNT_EXP) 3974 mp->rx_crc_errors += RXMAC_CRC_ER_CNT_COUNT; 3975 if (val & XRXMAC_STATUS_RXUFLOW) 3976 mp->rx_underflows++; 3977 if (val & XRXMAC_STATUS_RXOFLOW) 3978 mp->rx_overflows++; 3979 3980 val = nr64_mac(XMAC_FC_STAT); 3981 if (val & XMAC_FC_STAT_TX_MAC_NPAUSE) 3982 mp->pause_off_state++; 3983 if (val & XMAC_FC_STAT_TX_MAC_PAUSE) 3984 mp->pause_on_state++; 3985 if (val & XMAC_FC_STAT_RX_MAC_RPAUSE) 3986 mp->pause_received++; 3987 } 3988 3989 static void niu_bmac_interrupt(struct niu *np) 3990 { 3991 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 3992 u64 val; 3993 3994 val = nr64_mac(BTXMAC_STATUS); 3995 if (val & BTXMAC_STATUS_UNDERRUN) 3996 mp->tx_underflow_errors++; 3997 if (val & BTXMAC_STATUS_MAX_PKT_ERR) 3998 mp->tx_max_pkt_size_errors++; 3999 if (val & BTXMAC_STATUS_BYTE_CNT_EXP) 4000 mp->tx_bytes += BTXMAC_BYTE_CNT_COUNT; 4001 if (val & BTXMAC_STATUS_FRAME_CNT_EXP) 4002 mp->tx_frames += BTXMAC_FRM_CNT_COUNT; 4003 4004 val = nr64_mac(BRXMAC_STATUS); 4005 if (val & BRXMAC_STATUS_OVERFLOW) 4006 mp->rx_overflows++; 4007 if (val & BRXMAC_STATUS_FRAME_CNT_EXP) 4008 mp->rx_frames += BRXMAC_FRAME_CNT_COUNT; 4009 if (val & BRXMAC_STATUS_ALIGN_ERR_EXP) 4010 mp->rx_align_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4011 if (val & BRXMAC_STATUS_CRC_ERR_EXP) 4012 mp->rx_crc_errors += BRXMAC_ALIGN_ERR_CNT_COUNT; 4013 if (val & BRXMAC_STATUS_LEN_ERR_EXP) 4014 mp->rx_len_errors += BRXMAC_CODE_VIOL_ERR_CNT_COUNT; 4015 4016 val = nr64_mac(BMAC_CTRL_STATUS); 4017 if (val & BMAC_CTRL_STATUS_NOPAUSE) 4018 mp->pause_off_state++; 4019 if (val & BMAC_CTRL_STATUS_PAUSE) 4020 mp->pause_on_state++; 4021 if (val & BMAC_CTRL_STATUS_PAUSE_RECV) 4022 mp->pause_received++; 4023 } 4024 4025 static int niu_mac_interrupt(struct niu *np) 4026 { 4027 if (np->flags & NIU_FLAGS_XMAC) 4028 niu_xmac_interrupt(np); 4029 else 4030 niu_bmac_interrupt(np); 4031 4032 return 0; 4033 } 4034 4035 static void niu_log_device_error(struct niu *np, u64 stat) 4036 { 4037 netdev_err(np->dev, "Core device errors ( "); 4038 4039 if (stat & SYS_ERR_MASK_META2) 4040 pr_cont("META2 "); 4041 if (stat & SYS_ERR_MASK_META1) 4042 pr_cont("META1 "); 4043 if (stat & SYS_ERR_MASK_PEU) 4044 pr_cont("PEU "); 4045 if (stat & SYS_ERR_MASK_TXC) 4046 pr_cont("TXC "); 4047 if (stat & SYS_ERR_MASK_RDMC) 4048 pr_cont("RDMC "); 4049 if (stat & SYS_ERR_MASK_TDMC) 4050 pr_cont("TDMC "); 4051 if (stat & SYS_ERR_MASK_ZCP) 4052 pr_cont("ZCP "); 4053 if (stat & SYS_ERR_MASK_FFLP) 4054 pr_cont("FFLP "); 4055 if (stat & SYS_ERR_MASK_IPP) 4056 pr_cont("IPP "); 4057 if (stat & SYS_ERR_MASK_MAC) 4058 pr_cont("MAC "); 4059 if (stat & SYS_ERR_MASK_SMX) 4060 pr_cont("SMX "); 4061 4062 pr_cont(")\n"); 4063 } 4064 4065 static int niu_device_error(struct niu *np) 4066 { 4067 u64 stat = nr64(SYS_ERR_STAT); 4068 4069 netdev_err(np->dev, "Core device error, stat[%llx]\n", 4070 (unsigned long long)stat); 4071 4072 niu_log_device_error(np, stat); 4073 4074 return -ENODEV; 4075 } 4076 4077 static int niu_slowpath_interrupt(struct niu *np, struct niu_ldg *lp, 4078 u64 v0, u64 v1, u64 v2) 4079 { 4080 4081 int i, err = 0; 4082 4083 lp->v0 = v0; 4084 lp->v1 = v1; 4085 lp->v2 = v2; 4086 4087 if (v1 & 0x00000000ffffffffULL) { 4088 u32 rx_vec = (v1 & 0xffffffff); 4089 4090 for (i = 0; i < np->num_rx_rings; i++) { 4091 struct rx_ring_info *rp = &np->rx_rings[i]; 4092 4093 if (rx_vec & (1 << rp->rx_channel)) { 4094 int r = niu_rx_error(np, rp); 4095 if (r) { 4096 err = r; 4097 } else { 4098 if (!v0) 4099 nw64(RX_DMA_CTL_STAT(rp->rx_channel), 4100 RX_DMA_CTL_STAT_MEX); 4101 } 4102 } 4103 } 4104 } 4105 if (v1 & 0x7fffffff00000000ULL) { 4106 u32 tx_vec = (v1 >> 32) & 0x7fffffff; 4107 4108 for (i = 0; i < np->num_tx_rings; i++) { 4109 struct tx_ring_info *rp = &np->tx_rings[i]; 4110 4111 if (tx_vec & (1 << rp->tx_channel)) { 4112 int r = niu_tx_error(np, rp); 4113 if (r) 4114 err = r; 4115 } 4116 } 4117 } 4118 if ((v0 | v1) & 0x8000000000000000ULL) { 4119 int r = niu_mif_interrupt(np); 4120 if (r) 4121 err = r; 4122 } 4123 if (v2) { 4124 if (v2 & 0x01ef) { 4125 int r = niu_mac_interrupt(np); 4126 if (r) 4127 err = r; 4128 } 4129 if (v2 & 0x0210) { 4130 int r = niu_device_error(np); 4131 if (r) 4132 err = r; 4133 } 4134 } 4135 4136 if (err) 4137 niu_enable_interrupts(np, 0); 4138 4139 return err; 4140 } 4141 4142 static void niu_rxchan_intr(struct niu *np, struct rx_ring_info *rp, 4143 int ldn) 4144 { 4145 struct rxdma_mailbox *mbox = rp->mbox; 4146 u64 stat_write, stat = le64_to_cpup(&mbox->rx_dma_ctl_stat); 4147 4148 stat_write = (RX_DMA_CTL_STAT_RCRTHRES | 4149 RX_DMA_CTL_STAT_RCRTO); 4150 nw64(RX_DMA_CTL_STAT(rp->rx_channel), stat_write); 4151 4152 netif_printk(np, intr, KERN_DEBUG, np->dev, 4153 "%s() stat[%llx]\n", __func__, (unsigned long long)stat); 4154 } 4155 4156 static void niu_txchan_intr(struct niu *np, struct tx_ring_info *rp, 4157 int ldn) 4158 { 4159 rp->tx_cs = nr64(TX_CS(rp->tx_channel)); 4160 4161 netif_printk(np, intr, KERN_DEBUG, np->dev, 4162 "%s() cs[%llx]\n", __func__, (unsigned long long)rp->tx_cs); 4163 } 4164 4165 static void __niu_fastpath_interrupt(struct niu *np, int ldg, u64 v0) 4166 { 4167 struct niu_parent *parent = np->parent; 4168 u32 rx_vec, tx_vec; 4169 int i; 4170 4171 tx_vec = (v0 >> 32); 4172 rx_vec = (v0 & 0xffffffff); 4173 4174 for (i = 0; i < np->num_rx_rings; i++) { 4175 struct rx_ring_info *rp = &np->rx_rings[i]; 4176 int ldn = LDN_RXDMA(rp->rx_channel); 4177 4178 if (parent->ldg_map[ldn] != ldg) 4179 continue; 4180 4181 nw64(LD_IM0(ldn), LD_IM0_MASK); 4182 if (rx_vec & (1 << rp->rx_channel)) 4183 niu_rxchan_intr(np, rp, ldn); 4184 } 4185 4186 for (i = 0; i < np->num_tx_rings; i++) { 4187 struct tx_ring_info *rp = &np->tx_rings[i]; 4188 int ldn = LDN_TXDMA(rp->tx_channel); 4189 4190 if (parent->ldg_map[ldn] != ldg) 4191 continue; 4192 4193 nw64(LD_IM0(ldn), LD_IM0_MASK); 4194 if (tx_vec & (1 << rp->tx_channel)) 4195 niu_txchan_intr(np, rp, ldn); 4196 } 4197 } 4198 4199 static void niu_schedule_napi(struct niu *np, struct niu_ldg *lp, 4200 u64 v0, u64 v1, u64 v2) 4201 { 4202 if (likely(napi_schedule_prep(&lp->napi))) { 4203 lp->v0 = v0; 4204 lp->v1 = v1; 4205 lp->v2 = v2; 4206 __niu_fastpath_interrupt(np, lp->ldg_num, v0); 4207 __napi_schedule(&lp->napi); 4208 } 4209 } 4210 4211 static irqreturn_t niu_interrupt(int irq, void *dev_id) 4212 { 4213 struct niu_ldg *lp = dev_id; 4214 struct niu *np = lp->np; 4215 int ldg = lp->ldg_num; 4216 unsigned long flags; 4217 u64 v0, v1, v2; 4218 4219 if (netif_msg_intr(np)) 4220 printk(KERN_DEBUG KBUILD_MODNAME ": " "%s() ldg[%p](%d)", 4221 __func__, lp, ldg); 4222 4223 spin_lock_irqsave(&np->lock, flags); 4224 4225 v0 = nr64(LDSV0(ldg)); 4226 v1 = nr64(LDSV1(ldg)); 4227 v2 = nr64(LDSV2(ldg)); 4228 4229 if (netif_msg_intr(np)) 4230 pr_cont(" v0[%llx] v1[%llx] v2[%llx]\n", 4231 (unsigned long long) v0, 4232 (unsigned long long) v1, 4233 (unsigned long long) v2); 4234 4235 if (unlikely(!v0 && !v1 && !v2)) { 4236 spin_unlock_irqrestore(&np->lock, flags); 4237 return IRQ_NONE; 4238 } 4239 4240 if (unlikely((v0 & ((u64)1 << LDN_MIF)) || v1 || v2)) { 4241 int err = niu_slowpath_interrupt(np, lp, v0, v1, v2); 4242 if (err) 4243 goto out; 4244 } 4245 if (likely(v0 & ~((u64)1 << LDN_MIF))) 4246 niu_schedule_napi(np, lp, v0, v1, v2); 4247 else 4248 niu_ldg_rearm(np, lp, 1); 4249 out: 4250 spin_unlock_irqrestore(&np->lock, flags); 4251 4252 return IRQ_HANDLED; 4253 } 4254 4255 static void niu_free_rx_ring_info(struct niu *np, struct rx_ring_info *rp) 4256 { 4257 if (rp->mbox) { 4258 np->ops->free_coherent(np->device, 4259 sizeof(struct rxdma_mailbox), 4260 rp->mbox, rp->mbox_dma); 4261 rp->mbox = NULL; 4262 } 4263 if (rp->rcr) { 4264 np->ops->free_coherent(np->device, 4265 MAX_RCR_RING_SIZE * sizeof(__le64), 4266 rp->rcr, rp->rcr_dma); 4267 rp->rcr = NULL; 4268 rp->rcr_table_size = 0; 4269 rp->rcr_index = 0; 4270 } 4271 if (rp->rbr) { 4272 niu_rbr_free(np, rp); 4273 4274 np->ops->free_coherent(np->device, 4275 MAX_RBR_RING_SIZE * sizeof(__le32), 4276 rp->rbr, rp->rbr_dma); 4277 rp->rbr = NULL; 4278 rp->rbr_table_size = 0; 4279 rp->rbr_index = 0; 4280 } 4281 kfree(rp->rxhash); 4282 rp->rxhash = NULL; 4283 } 4284 4285 static void niu_free_tx_ring_info(struct niu *np, struct tx_ring_info *rp) 4286 { 4287 if (rp->mbox) { 4288 np->ops->free_coherent(np->device, 4289 sizeof(struct txdma_mailbox), 4290 rp->mbox, rp->mbox_dma); 4291 rp->mbox = NULL; 4292 } 4293 if (rp->descr) { 4294 int i; 4295 4296 for (i = 0; i < MAX_TX_RING_SIZE; i++) { 4297 if (rp->tx_buffs[i].skb) 4298 (void) release_tx_packet(np, rp, i); 4299 } 4300 4301 np->ops->free_coherent(np->device, 4302 MAX_TX_RING_SIZE * sizeof(__le64), 4303 rp->descr, rp->descr_dma); 4304 rp->descr = NULL; 4305 rp->pending = 0; 4306 rp->prod = 0; 4307 rp->cons = 0; 4308 rp->wrap_bit = 0; 4309 } 4310 } 4311 4312 static void niu_free_channels(struct niu *np) 4313 { 4314 int i; 4315 4316 if (np->rx_rings) { 4317 for (i = 0; i < np->num_rx_rings; i++) { 4318 struct rx_ring_info *rp = &np->rx_rings[i]; 4319 4320 niu_free_rx_ring_info(np, rp); 4321 } 4322 kfree(np->rx_rings); 4323 np->rx_rings = NULL; 4324 np->num_rx_rings = 0; 4325 } 4326 4327 if (np->tx_rings) { 4328 for (i = 0; i < np->num_tx_rings; i++) { 4329 struct tx_ring_info *rp = &np->tx_rings[i]; 4330 4331 niu_free_tx_ring_info(np, rp); 4332 } 4333 kfree(np->tx_rings); 4334 np->tx_rings = NULL; 4335 np->num_tx_rings = 0; 4336 } 4337 } 4338 4339 static int niu_alloc_rx_ring_info(struct niu *np, 4340 struct rx_ring_info *rp) 4341 { 4342 BUILD_BUG_ON(sizeof(struct rxdma_mailbox) != 64); 4343 4344 rp->rxhash = kzalloc_objs(struct page *, MAX_RBR_RING_SIZE); 4345 if (!rp->rxhash) 4346 return -ENOMEM; 4347 4348 rp->mbox = np->ops->alloc_coherent(np->device, 4349 sizeof(struct rxdma_mailbox), 4350 &rp->mbox_dma, GFP_KERNEL); 4351 if (!rp->mbox) 4352 return -ENOMEM; 4353 if ((unsigned long)rp->mbox & (64UL - 1)) { 4354 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA mailbox %p\n", 4355 rp->mbox); 4356 return -EINVAL; 4357 } 4358 4359 rp->rcr = np->ops->alloc_coherent(np->device, 4360 MAX_RCR_RING_SIZE * sizeof(__le64), 4361 &rp->rcr_dma, GFP_KERNEL); 4362 if (!rp->rcr) 4363 return -ENOMEM; 4364 if ((unsigned long)rp->rcr & (64UL - 1)) { 4365 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RCR table %p\n", 4366 rp->rcr); 4367 return -EINVAL; 4368 } 4369 rp->rcr_table_size = MAX_RCR_RING_SIZE; 4370 rp->rcr_index = 0; 4371 4372 rp->rbr = np->ops->alloc_coherent(np->device, 4373 MAX_RBR_RING_SIZE * sizeof(__le32), 4374 &rp->rbr_dma, GFP_KERNEL); 4375 if (!rp->rbr) 4376 return -ENOMEM; 4377 if ((unsigned long)rp->rbr & (64UL - 1)) { 4378 netdev_err(np->dev, "Coherent alloc gives misaligned RXDMA RBR table %p\n", 4379 rp->rbr); 4380 return -EINVAL; 4381 } 4382 rp->rbr_table_size = MAX_RBR_RING_SIZE; 4383 rp->rbr_index = 0; 4384 rp->rbr_pending = 0; 4385 4386 return 0; 4387 } 4388 4389 static void niu_set_max_burst(struct niu *np, struct tx_ring_info *rp) 4390 { 4391 int mtu = np->dev->mtu; 4392 4393 /* These values are recommended by the HW designers for fair 4394 * utilization of DRR amongst the rings. 4395 */ 4396 rp->max_burst = mtu + 32; 4397 if (rp->max_burst > 4096) 4398 rp->max_burst = 4096; 4399 } 4400 4401 static int niu_alloc_tx_ring_info(struct niu *np, 4402 struct tx_ring_info *rp) 4403 { 4404 BUILD_BUG_ON(sizeof(struct txdma_mailbox) != 64); 4405 4406 rp->mbox = np->ops->alloc_coherent(np->device, 4407 sizeof(struct txdma_mailbox), 4408 &rp->mbox_dma, GFP_KERNEL); 4409 if (!rp->mbox) 4410 return -ENOMEM; 4411 if ((unsigned long)rp->mbox & (64UL - 1)) { 4412 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA mailbox %p\n", 4413 rp->mbox); 4414 return -EINVAL; 4415 } 4416 4417 rp->descr = np->ops->alloc_coherent(np->device, 4418 MAX_TX_RING_SIZE * sizeof(__le64), 4419 &rp->descr_dma, GFP_KERNEL); 4420 if (!rp->descr) 4421 return -ENOMEM; 4422 if ((unsigned long)rp->descr & (64UL - 1)) { 4423 netdev_err(np->dev, "Coherent alloc gives misaligned TXDMA descr table %p\n", 4424 rp->descr); 4425 return -EINVAL; 4426 } 4427 4428 rp->pending = MAX_TX_RING_SIZE; 4429 rp->prod = 0; 4430 rp->cons = 0; 4431 rp->wrap_bit = 0; 4432 4433 /* XXX make these configurable... XXX */ 4434 rp->mark_freq = rp->pending / 4; 4435 4436 niu_set_max_burst(np, rp); 4437 4438 return 0; 4439 } 4440 4441 static void niu_size_rbr(struct niu *np, struct rx_ring_info *rp) 4442 { 4443 u16 bss; 4444 4445 bss = min(PAGE_SHIFT, 15); 4446 4447 rp->rbr_block_size = 1 << bss; 4448 rp->rbr_blocks_per_page = 1 << (PAGE_SHIFT-bss); 4449 4450 rp->rbr_sizes[0] = 256; 4451 rp->rbr_sizes[1] = 1024; 4452 if (np->dev->mtu > ETH_DATA_LEN) { 4453 switch (PAGE_SIZE) { 4454 case 4 * 1024: 4455 rp->rbr_sizes[2] = 4096; 4456 break; 4457 4458 default: 4459 rp->rbr_sizes[2] = 8192; 4460 break; 4461 } 4462 } else { 4463 rp->rbr_sizes[2] = 2048; 4464 } 4465 rp->rbr_sizes[3] = rp->rbr_block_size; 4466 } 4467 4468 static int niu_alloc_channels(struct niu *np) 4469 { 4470 struct niu_parent *parent = np->parent; 4471 int first_rx_channel, first_tx_channel; 4472 int num_rx_rings, num_tx_rings; 4473 struct rx_ring_info *rx_rings; 4474 struct tx_ring_info *tx_rings; 4475 int i, port, err; 4476 4477 port = np->port; 4478 first_rx_channel = first_tx_channel = 0; 4479 for (i = 0; i < port; i++) { 4480 first_rx_channel += parent->rxchan_per_port[i]; 4481 first_tx_channel += parent->txchan_per_port[i]; 4482 } 4483 4484 num_rx_rings = parent->rxchan_per_port[port]; 4485 num_tx_rings = parent->txchan_per_port[port]; 4486 4487 rx_rings = kzalloc_objs(struct rx_ring_info, num_rx_rings); 4488 err = -ENOMEM; 4489 if (!rx_rings) 4490 goto out_err; 4491 4492 np->num_rx_rings = num_rx_rings; 4493 smp_wmb(); 4494 np->rx_rings = rx_rings; 4495 4496 netif_set_real_num_rx_queues(np->dev, num_rx_rings); 4497 4498 for (i = 0; i < np->num_rx_rings; i++) { 4499 struct rx_ring_info *rp = &np->rx_rings[i]; 4500 4501 rp->np = np; 4502 rp->rx_channel = first_rx_channel + i; 4503 4504 err = niu_alloc_rx_ring_info(np, rp); 4505 if (err) 4506 goto out_err; 4507 4508 niu_size_rbr(np, rp); 4509 4510 /* XXX better defaults, configurable, etc... XXX */ 4511 rp->nonsyn_window = 64; 4512 rp->nonsyn_threshold = rp->rcr_table_size - 64; 4513 rp->syn_window = 64; 4514 rp->syn_threshold = rp->rcr_table_size - 64; 4515 rp->rcr_pkt_threshold = 16; 4516 rp->rcr_timeout = 8; 4517 rp->rbr_kick_thresh = RBR_REFILL_MIN; 4518 if (rp->rbr_kick_thresh < rp->rbr_blocks_per_page) 4519 rp->rbr_kick_thresh = rp->rbr_blocks_per_page; 4520 4521 err = niu_rbr_fill(np, rp, GFP_KERNEL); 4522 if (err) 4523 goto out_err; 4524 } 4525 4526 tx_rings = kzalloc_objs(struct tx_ring_info, num_tx_rings); 4527 err = -ENOMEM; 4528 if (!tx_rings) 4529 goto out_err; 4530 4531 np->num_tx_rings = num_tx_rings; 4532 smp_wmb(); 4533 np->tx_rings = tx_rings; 4534 4535 netif_set_real_num_tx_queues(np->dev, num_tx_rings); 4536 4537 for (i = 0; i < np->num_tx_rings; i++) { 4538 struct tx_ring_info *rp = &np->tx_rings[i]; 4539 4540 rp->np = np; 4541 rp->tx_channel = first_tx_channel + i; 4542 4543 err = niu_alloc_tx_ring_info(np, rp); 4544 if (err) 4545 goto out_err; 4546 } 4547 4548 return 0; 4549 4550 out_err: 4551 niu_free_channels(np); 4552 return err; 4553 } 4554 4555 static int niu_tx_cs_sng_poll(struct niu *np, int channel) 4556 { 4557 int limit = 1000; 4558 4559 while (--limit > 0) { 4560 u64 val = nr64(TX_CS(channel)); 4561 if (val & TX_CS_SNG_STATE) 4562 return 0; 4563 } 4564 return -ENODEV; 4565 } 4566 4567 static int niu_tx_channel_stop(struct niu *np, int channel) 4568 { 4569 u64 val = nr64(TX_CS(channel)); 4570 4571 val |= TX_CS_STOP_N_GO; 4572 nw64(TX_CS(channel), val); 4573 4574 return niu_tx_cs_sng_poll(np, channel); 4575 } 4576 4577 static int niu_tx_cs_reset_poll(struct niu *np, int channel) 4578 { 4579 int limit = 1000; 4580 4581 while (--limit > 0) { 4582 u64 val = nr64(TX_CS(channel)); 4583 if (!(val & TX_CS_RST)) 4584 return 0; 4585 } 4586 return -ENODEV; 4587 } 4588 4589 static int niu_tx_channel_reset(struct niu *np, int channel) 4590 { 4591 u64 val = nr64(TX_CS(channel)); 4592 int err; 4593 4594 val |= TX_CS_RST; 4595 nw64(TX_CS(channel), val); 4596 4597 err = niu_tx_cs_reset_poll(np, channel); 4598 if (!err) 4599 nw64(TX_RING_KICK(channel), 0); 4600 4601 return err; 4602 } 4603 4604 static int niu_tx_channel_lpage_init(struct niu *np, int channel) 4605 { 4606 u64 val; 4607 4608 nw64(TX_LOG_MASK1(channel), 0); 4609 nw64(TX_LOG_VAL1(channel), 0); 4610 nw64(TX_LOG_MASK2(channel), 0); 4611 nw64(TX_LOG_VAL2(channel), 0); 4612 nw64(TX_LOG_PAGE_RELO1(channel), 0); 4613 nw64(TX_LOG_PAGE_RELO2(channel), 0); 4614 nw64(TX_LOG_PAGE_HDL(channel), 0); 4615 4616 val = (u64)np->port << TX_LOG_PAGE_VLD_FUNC_SHIFT; 4617 val |= (TX_LOG_PAGE_VLD_PAGE0 | TX_LOG_PAGE_VLD_PAGE1); 4618 nw64(TX_LOG_PAGE_VLD(channel), val); 4619 4620 /* XXX TXDMA 32bit mode? XXX */ 4621 4622 return 0; 4623 } 4624 4625 static void niu_txc_enable_port(struct niu *np, int on) 4626 { 4627 unsigned long flags; 4628 u64 val, mask; 4629 4630 niu_lock_parent(np, flags); 4631 val = nr64(TXC_CONTROL); 4632 mask = (u64)1 << np->port; 4633 if (on) { 4634 val |= TXC_CONTROL_ENABLE | mask; 4635 } else { 4636 val &= ~mask; 4637 if ((val & ~TXC_CONTROL_ENABLE) == 0) 4638 val &= ~TXC_CONTROL_ENABLE; 4639 } 4640 nw64(TXC_CONTROL, val); 4641 niu_unlock_parent(np, flags); 4642 } 4643 4644 static void niu_txc_set_imask(struct niu *np, u64 imask) 4645 { 4646 unsigned long flags; 4647 u64 val; 4648 4649 niu_lock_parent(np, flags); 4650 val = nr64(TXC_INT_MASK); 4651 val &= ~TXC_INT_MASK_VAL(np->port); 4652 val |= (imask << TXC_INT_MASK_VAL_SHIFT(np->port)); 4653 niu_unlock_parent(np, flags); 4654 } 4655 4656 static void niu_txc_port_dma_enable(struct niu *np, int on) 4657 { 4658 u64 val = 0; 4659 4660 if (on) { 4661 int i; 4662 4663 for (i = 0; i < np->num_tx_rings; i++) 4664 val |= (1 << np->tx_rings[i].tx_channel); 4665 } 4666 nw64(TXC_PORT_DMA(np->port), val); 4667 } 4668 4669 static int niu_init_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 4670 { 4671 int err, channel = rp->tx_channel; 4672 u64 val, ring_len; 4673 4674 err = niu_tx_channel_stop(np, channel); 4675 if (err) 4676 return err; 4677 4678 err = niu_tx_channel_reset(np, channel); 4679 if (err) 4680 return err; 4681 4682 err = niu_tx_channel_lpage_init(np, channel); 4683 if (err) 4684 return err; 4685 4686 nw64(TXC_DMA_MAX(channel), rp->max_burst); 4687 nw64(TX_ENT_MSK(channel), 0); 4688 4689 if (rp->descr_dma & ~(TX_RNG_CFIG_STADDR_BASE | 4690 TX_RNG_CFIG_STADDR)) { 4691 netdev_err(np->dev, "TX ring channel %d DMA addr (%llx) is not aligned\n", 4692 channel, (unsigned long long)rp->descr_dma); 4693 return -EINVAL; 4694 } 4695 4696 /* The length field in TX_RNG_CFIG is measured in 64-byte 4697 * blocks. rp->pending is the number of TX descriptors in 4698 * our ring, 8 bytes each, thus we divide by 8 bytes more 4699 * to get the proper value the chip wants. 4700 */ 4701 ring_len = (rp->pending / 8); 4702 4703 val = ((ring_len << TX_RNG_CFIG_LEN_SHIFT) | 4704 rp->descr_dma); 4705 nw64(TX_RNG_CFIG(channel), val); 4706 4707 if (((rp->mbox_dma >> 32) & ~TXDMA_MBH_MBADDR) || 4708 ((u32)rp->mbox_dma & ~TXDMA_MBL_MBADDR)) { 4709 netdev_err(np->dev, "TX ring channel %d MBOX addr (%llx) has invalid bits\n", 4710 channel, (unsigned long long)rp->mbox_dma); 4711 return -EINVAL; 4712 } 4713 nw64(TXDMA_MBH(channel), rp->mbox_dma >> 32); 4714 nw64(TXDMA_MBL(channel), rp->mbox_dma & TXDMA_MBL_MBADDR); 4715 4716 nw64(TX_CS(channel), 0); 4717 4718 rp->last_pkt_cnt = 0; 4719 4720 return 0; 4721 } 4722 4723 static void niu_init_rdc_groups(struct niu *np) 4724 { 4725 struct niu_rdc_tables *tp = &np->parent->rdc_group_cfg[np->port]; 4726 int i, first_table_num = tp->first_table_num; 4727 4728 for (i = 0; i < tp->num_tables; i++) { 4729 struct rdc_table *tbl = &tp->tables[i]; 4730 int this_table = first_table_num + i; 4731 int slot; 4732 4733 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) 4734 nw64(RDC_TBL(this_table, slot), 4735 tbl->rxdma_channel[slot]); 4736 } 4737 4738 nw64(DEF_RDC(np->port), np->parent->rdc_default[np->port]); 4739 } 4740 4741 static void niu_init_drr_weight(struct niu *np) 4742 { 4743 int type = phy_decode(np->parent->port_phy, np->port); 4744 u64 val; 4745 4746 switch (type) { 4747 case PORT_TYPE_10G: 4748 val = PT_DRR_WEIGHT_DEFAULT_10G; 4749 break; 4750 4751 case PORT_TYPE_1G: 4752 default: 4753 val = PT_DRR_WEIGHT_DEFAULT_1G; 4754 break; 4755 } 4756 nw64(PT_DRR_WT(np->port), val); 4757 } 4758 4759 static int niu_init_hostinfo(struct niu *np) 4760 { 4761 struct niu_parent *parent = np->parent; 4762 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 4763 int i, err, num_alt = niu_num_alt_addr(np); 4764 int first_rdc_table = tp->first_table_num; 4765 4766 err = niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 4767 if (err) 4768 return err; 4769 4770 err = niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 4771 if (err) 4772 return err; 4773 4774 for (i = 0; i < num_alt; i++) { 4775 err = niu_set_alt_mac_rdc_table(np, i, first_rdc_table, 1); 4776 if (err) 4777 return err; 4778 } 4779 4780 return 0; 4781 } 4782 4783 static int niu_rx_channel_reset(struct niu *np, int channel) 4784 { 4785 return niu_set_and_wait_clear(np, RXDMA_CFIG1(channel), 4786 RXDMA_CFIG1_RST, 1000, 10, 4787 "RXDMA_CFIG1"); 4788 } 4789 4790 static int niu_rx_channel_lpage_init(struct niu *np, int channel) 4791 { 4792 u64 val; 4793 4794 nw64(RX_LOG_MASK1(channel), 0); 4795 nw64(RX_LOG_VAL1(channel), 0); 4796 nw64(RX_LOG_MASK2(channel), 0); 4797 nw64(RX_LOG_VAL2(channel), 0); 4798 nw64(RX_LOG_PAGE_RELO1(channel), 0); 4799 nw64(RX_LOG_PAGE_RELO2(channel), 0); 4800 nw64(RX_LOG_PAGE_HDL(channel), 0); 4801 4802 val = (u64)np->port << RX_LOG_PAGE_VLD_FUNC_SHIFT; 4803 val |= (RX_LOG_PAGE_VLD_PAGE0 | RX_LOG_PAGE_VLD_PAGE1); 4804 nw64(RX_LOG_PAGE_VLD(channel), val); 4805 4806 return 0; 4807 } 4808 4809 static void niu_rx_channel_wred_init(struct niu *np, struct rx_ring_info *rp) 4810 { 4811 u64 val; 4812 4813 val = (((u64)rp->nonsyn_window << RDC_RED_PARA_WIN_SHIFT) | 4814 ((u64)rp->nonsyn_threshold << RDC_RED_PARA_THRE_SHIFT) | 4815 ((u64)rp->syn_window << RDC_RED_PARA_WIN_SYN_SHIFT) | 4816 ((u64)rp->syn_threshold << RDC_RED_PARA_THRE_SYN_SHIFT)); 4817 nw64(RDC_RED_PARA(rp->rx_channel), val); 4818 } 4819 4820 static int niu_compute_rbr_cfig_b(struct rx_ring_info *rp, u64 *ret) 4821 { 4822 u64 val = 0; 4823 4824 *ret = 0; 4825 switch (rp->rbr_block_size) { 4826 case 4 * 1024: 4827 val |= (RBR_BLKSIZE_4K << RBR_CFIG_B_BLKSIZE_SHIFT); 4828 break; 4829 case 8 * 1024: 4830 val |= (RBR_BLKSIZE_8K << RBR_CFIG_B_BLKSIZE_SHIFT); 4831 break; 4832 case 16 * 1024: 4833 val |= (RBR_BLKSIZE_16K << RBR_CFIG_B_BLKSIZE_SHIFT); 4834 break; 4835 case 32 * 1024: 4836 val |= (RBR_BLKSIZE_32K << RBR_CFIG_B_BLKSIZE_SHIFT); 4837 break; 4838 default: 4839 return -EINVAL; 4840 } 4841 val |= RBR_CFIG_B_VLD2; 4842 switch (rp->rbr_sizes[2]) { 4843 case 2 * 1024: 4844 val |= (RBR_BUFSZ2_2K << RBR_CFIG_B_BUFSZ2_SHIFT); 4845 break; 4846 case 4 * 1024: 4847 val |= (RBR_BUFSZ2_4K << RBR_CFIG_B_BUFSZ2_SHIFT); 4848 break; 4849 case 8 * 1024: 4850 val |= (RBR_BUFSZ2_8K << RBR_CFIG_B_BUFSZ2_SHIFT); 4851 break; 4852 case 16 * 1024: 4853 val |= (RBR_BUFSZ2_16K << RBR_CFIG_B_BUFSZ2_SHIFT); 4854 break; 4855 4856 default: 4857 return -EINVAL; 4858 } 4859 val |= RBR_CFIG_B_VLD1; 4860 switch (rp->rbr_sizes[1]) { 4861 case 1 * 1024: 4862 val |= (RBR_BUFSZ1_1K << RBR_CFIG_B_BUFSZ1_SHIFT); 4863 break; 4864 case 2 * 1024: 4865 val |= (RBR_BUFSZ1_2K << RBR_CFIG_B_BUFSZ1_SHIFT); 4866 break; 4867 case 4 * 1024: 4868 val |= (RBR_BUFSZ1_4K << RBR_CFIG_B_BUFSZ1_SHIFT); 4869 break; 4870 case 8 * 1024: 4871 val |= (RBR_BUFSZ1_8K << RBR_CFIG_B_BUFSZ1_SHIFT); 4872 break; 4873 4874 default: 4875 return -EINVAL; 4876 } 4877 val |= RBR_CFIG_B_VLD0; 4878 switch (rp->rbr_sizes[0]) { 4879 case 256: 4880 val |= (RBR_BUFSZ0_256 << RBR_CFIG_B_BUFSZ0_SHIFT); 4881 break; 4882 case 512: 4883 val |= (RBR_BUFSZ0_512 << RBR_CFIG_B_BUFSZ0_SHIFT); 4884 break; 4885 case 1 * 1024: 4886 val |= (RBR_BUFSZ0_1K << RBR_CFIG_B_BUFSZ0_SHIFT); 4887 break; 4888 case 2 * 1024: 4889 val |= (RBR_BUFSZ0_2K << RBR_CFIG_B_BUFSZ0_SHIFT); 4890 break; 4891 4892 default: 4893 return -EINVAL; 4894 } 4895 4896 *ret = val; 4897 return 0; 4898 } 4899 4900 static int niu_enable_rx_channel(struct niu *np, int channel, int on) 4901 { 4902 u64 val = nr64(RXDMA_CFIG1(channel)); 4903 int limit; 4904 4905 if (on) 4906 val |= RXDMA_CFIG1_EN; 4907 else 4908 val &= ~RXDMA_CFIG1_EN; 4909 nw64(RXDMA_CFIG1(channel), val); 4910 4911 limit = 1000; 4912 while (--limit > 0) { 4913 if (nr64(RXDMA_CFIG1(channel)) & RXDMA_CFIG1_QST) 4914 break; 4915 udelay(10); 4916 } 4917 if (limit <= 0) 4918 return -ENODEV; 4919 return 0; 4920 } 4921 4922 static int niu_init_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 4923 { 4924 int err, channel = rp->rx_channel; 4925 u64 val; 4926 4927 err = niu_rx_channel_reset(np, channel); 4928 if (err) 4929 return err; 4930 4931 err = niu_rx_channel_lpage_init(np, channel); 4932 if (err) 4933 return err; 4934 4935 niu_rx_channel_wred_init(np, rp); 4936 4937 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_RBR_EMPTY); 4938 nw64(RX_DMA_CTL_STAT(channel), 4939 (RX_DMA_CTL_STAT_MEX | 4940 RX_DMA_CTL_STAT_RCRTHRES | 4941 RX_DMA_CTL_STAT_RCRTO | 4942 RX_DMA_CTL_STAT_RBR_EMPTY)); 4943 nw64(RXDMA_CFIG1(channel), rp->mbox_dma >> 32); 4944 nw64(RXDMA_CFIG2(channel), 4945 ((rp->mbox_dma & RXDMA_CFIG2_MBADDR_L) | 4946 RXDMA_CFIG2_FULL_HDR)); 4947 nw64(RBR_CFIG_A(channel), 4948 ((u64)rp->rbr_table_size << RBR_CFIG_A_LEN_SHIFT) | 4949 (rp->rbr_dma & (RBR_CFIG_A_STADDR_BASE | RBR_CFIG_A_STADDR))); 4950 err = niu_compute_rbr_cfig_b(rp, &val); 4951 if (err) 4952 return err; 4953 nw64(RBR_CFIG_B(channel), val); 4954 nw64(RCRCFIG_A(channel), 4955 ((u64)rp->rcr_table_size << RCRCFIG_A_LEN_SHIFT) | 4956 (rp->rcr_dma & (RCRCFIG_A_STADDR_BASE | RCRCFIG_A_STADDR))); 4957 nw64(RCRCFIG_B(channel), 4958 ((u64)rp->rcr_pkt_threshold << RCRCFIG_B_PTHRES_SHIFT) | 4959 RCRCFIG_B_ENTOUT | 4960 ((u64)rp->rcr_timeout << RCRCFIG_B_TIMEOUT_SHIFT)); 4961 4962 err = niu_enable_rx_channel(np, channel, 1); 4963 if (err) 4964 return err; 4965 4966 nw64(RBR_KICK(channel), rp->rbr_index); 4967 4968 val = nr64(RX_DMA_CTL_STAT(channel)); 4969 val |= RX_DMA_CTL_STAT_RBR_EMPTY; 4970 nw64(RX_DMA_CTL_STAT(channel), val); 4971 4972 return 0; 4973 } 4974 4975 static int niu_init_rx_channels(struct niu *np) 4976 { 4977 unsigned long flags; 4978 u64 seed = jiffies_64; 4979 int err, i; 4980 4981 niu_lock_parent(np, flags); 4982 nw64(RX_DMA_CK_DIV, np->parent->rxdma_clock_divider); 4983 nw64(RED_RAN_INIT, RED_RAN_INIT_OPMODE | (seed & RED_RAN_INIT_VAL)); 4984 niu_unlock_parent(np, flags); 4985 4986 /* XXX RXDMA 32bit mode? XXX */ 4987 4988 niu_init_rdc_groups(np); 4989 niu_init_drr_weight(np); 4990 4991 err = niu_init_hostinfo(np); 4992 if (err) 4993 return err; 4994 4995 for (i = 0; i < np->num_rx_rings; i++) { 4996 struct rx_ring_info *rp = &np->rx_rings[i]; 4997 4998 err = niu_init_one_rx_channel(np, rp); 4999 if (err) 5000 return err; 5001 } 5002 5003 return 0; 5004 } 5005 5006 static int niu_set_ip_frag_rule(struct niu *np) 5007 { 5008 struct niu_parent *parent = np->parent; 5009 struct niu_classifier *cp = &np->clas; 5010 struct niu_tcam_entry *tp; 5011 int index, err; 5012 5013 index = cp->tcam_top; 5014 tp = &parent->tcam[index]; 5015 5016 /* Note that the noport bit is the same in both ipv4 and 5017 * ipv6 format TCAM entries. 5018 */ 5019 memset(tp, 0, sizeof(*tp)); 5020 tp->key[1] = TCAM_V4KEY1_NOPORT; 5021 tp->key_mask[1] = TCAM_V4KEY1_NOPORT; 5022 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 5023 ((u64)0 << TCAM_ASSOCDATA_OFFSET_SHIFT)); 5024 err = tcam_write(np, index, tp->key, tp->key_mask); 5025 if (err) 5026 return err; 5027 err = tcam_assoc_write(np, index, tp->assoc_data); 5028 if (err) 5029 return err; 5030 tp->valid = 1; 5031 cp->tcam_valid_entries++; 5032 5033 return 0; 5034 } 5035 5036 static int niu_init_classifier_hw(struct niu *np) 5037 { 5038 struct niu_parent *parent = np->parent; 5039 struct niu_classifier *cp = &np->clas; 5040 int i, err; 5041 5042 nw64(H1POLY, cp->h1_init); 5043 nw64(H2POLY, cp->h2_init); 5044 5045 err = niu_init_hostinfo(np); 5046 if (err) 5047 return err; 5048 5049 for (i = 0; i < ENET_VLAN_TBL_NUM_ENTRIES; i++) { 5050 struct niu_vlan_rdc *vp = &cp->vlan_mappings[i]; 5051 5052 vlan_tbl_write(np, i, np->port, 5053 vp->vlan_pref, vp->rdc_num); 5054 } 5055 5056 for (i = 0; i < cp->num_alt_mac_mappings; i++) { 5057 struct niu_altmac_rdc *ap = &cp->alt_mac_mappings[i]; 5058 5059 err = niu_set_alt_mac_rdc_table(np, ap->alt_mac_num, 5060 ap->rdc_num, ap->mac_pref); 5061 if (err) 5062 return err; 5063 } 5064 5065 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 5066 int index = i - CLASS_CODE_USER_PROG1; 5067 5068 err = niu_set_tcam_key(np, i, parent->tcam_key[index]); 5069 if (err) 5070 return err; 5071 err = niu_set_flow_key(np, i, parent->flow_key[index]); 5072 if (err) 5073 return err; 5074 } 5075 5076 err = niu_set_ip_frag_rule(np); 5077 if (err) 5078 return err; 5079 5080 tcam_enable(np, 1); 5081 5082 return 0; 5083 } 5084 5085 static int niu_zcp_write(struct niu *np, int index, u64 *data) 5086 { 5087 nw64(ZCP_RAM_DATA0, data[0]); 5088 nw64(ZCP_RAM_DATA1, data[1]); 5089 nw64(ZCP_RAM_DATA2, data[2]); 5090 nw64(ZCP_RAM_DATA3, data[3]); 5091 nw64(ZCP_RAM_DATA4, data[4]); 5092 nw64(ZCP_RAM_BE, ZCP_RAM_BE_VAL); 5093 nw64(ZCP_RAM_ACC, 5094 (ZCP_RAM_ACC_WRITE | 5095 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5096 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5097 5098 return niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5099 1000, 100); 5100 } 5101 5102 static int niu_zcp_read(struct niu *np, int index, u64 *data) 5103 { 5104 int err; 5105 5106 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5107 1000, 100); 5108 if (err) { 5109 netdev_err(np->dev, "ZCP read busy won't clear, ZCP_RAM_ACC[%llx]\n", 5110 (unsigned long long)nr64(ZCP_RAM_ACC)); 5111 return err; 5112 } 5113 5114 nw64(ZCP_RAM_ACC, 5115 (ZCP_RAM_ACC_READ | 5116 (0 << ZCP_RAM_ACC_ZFCID_SHIFT) | 5117 (ZCP_RAM_SEL_CFIFO(np->port) << ZCP_RAM_ACC_RAM_SEL_SHIFT))); 5118 5119 err = niu_wait_bits_clear(np, ZCP_RAM_ACC, ZCP_RAM_ACC_BUSY, 5120 1000, 100); 5121 if (err) { 5122 netdev_err(np->dev, "ZCP read busy2 won't clear, ZCP_RAM_ACC[%llx]\n", 5123 (unsigned long long)nr64(ZCP_RAM_ACC)); 5124 return err; 5125 } 5126 5127 data[0] = nr64(ZCP_RAM_DATA0); 5128 data[1] = nr64(ZCP_RAM_DATA1); 5129 data[2] = nr64(ZCP_RAM_DATA2); 5130 data[3] = nr64(ZCP_RAM_DATA3); 5131 data[4] = nr64(ZCP_RAM_DATA4); 5132 5133 return 0; 5134 } 5135 5136 static void niu_zcp_cfifo_reset(struct niu *np) 5137 { 5138 u64 val = nr64(RESET_CFIFO); 5139 5140 val |= RESET_CFIFO_RST(np->port); 5141 nw64(RESET_CFIFO, val); 5142 udelay(10); 5143 5144 val &= ~RESET_CFIFO_RST(np->port); 5145 nw64(RESET_CFIFO, val); 5146 } 5147 5148 static int niu_init_zcp(struct niu *np) 5149 { 5150 u64 data[5], rbuf[5]; 5151 int i, max, err; 5152 5153 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5154 if (np->port == 0 || np->port == 1) 5155 max = ATLAS_P0_P1_CFIFO_ENTRIES; 5156 else 5157 max = ATLAS_P2_P3_CFIFO_ENTRIES; 5158 } else 5159 max = NIU_CFIFO_ENTRIES; 5160 5161 data[0] = 0; 5162 data[1] = 0; 5163 data[2] = 0; 5164 data[3] = 0; 5165 data[4] = 0; 5166 5167 for (i = 0; i < max; i++) { 5168 err = niu_zcp_write(np, i, data); 5169 if (err) 5170 return err; 5171 err = niu_zcp_read(np, i, rbuf); 5172 if (err) 5173 return err; 5174 } 5175 5176 niu_zcp_cfifo_reset(np); 5177 nw64(CFIFO_ECC(np->port), 0); 5178 nw64(ZCP_INT_STAT, ZCP_INT_STAT_ALL); 5179 (void) nr64(ZCP_INT_STAT); 5180 nw64(ZCP_INT_MASK, ZCP_INT_MASK_ALL); 5181 5182 return 0; 5183 } 5184 5185 static void niu_ipp_write(struct niu *np, int index, u64 *data) 5186 { 5187 u64 val = nr64_ipp(IPP_CFIG); 5188 5189 nw64_ipp(IPP_CFIG, val | IPP_CFIG_DFIFO_PIO_W); 5190 nw64_ipp(IPP_DFIFO_WR_PTR, index); 5191 nw64_ipp(IPP_DFIFO_WR0, data[0]); 5192 nw64_ipp(IPP_DFIFO_WR1, data[1]); 5193 nw64_ipp(IPP_DFIFO_WR2, data[2]); 5194 nw64_ipp(IPP_DFIFO_WR3, data[3]); 5195 nw64_ipp(IPP_DFIFO_WR4, data[4]); 5196 nw64_ipp(IPP_CFIG, val & ~IPP_CFIG_DFIFO_PIO_W); 5197 } 5198 5199 static void niu_ipp_read(struct niu *np, int index, u64 *data) 5200 { 5201 nw64_ipp(IPP_DFIFO_RD_PTR, index); 5202 data[0] = nr64_ipp(IPP_DFIFO_RD0); 5203 data[1] = nr64_ipp(IPP_DFIFO_RD1); 5204 data[2] = nr64_ipp(IPP_DFIFO_RD2); 5205 data[3] = nr64_ipp(IPP_DFIFO_RD3); 5206 data[4] = nr64_ipp(IPP_DFIFO_RD4); 5207 } 5208 5209 static int niu_ipp_reset(struct niu *np) 5210 { 5211 return niu_set_and_wait_clear_ipp(np, IPP_CFIG, IPP_CFIG_SOFT_RST, 5212 1000, 100, "IPP_CFIG"); 5213 } 5214 5215 static int niu_init_ipp(struct niu *np) 5216 { 5217 u64 data[5], rbuf[5], val; 5218 int i, max, err; 5219 5220 if (np->parent->plat_type != PLAT_TYPE_NIU) { 5221 if (np->port == 0 || np->port == 1) 5222 max = ATLAS_P0_P1_DFIFO_ENTRIES; 5223 else 5224 max = ATLAS_P2_P3_DFIFO_ENTRIES; 5225 } else 5226 max = NIU_DFIFO_ENTRIES; 5227 5228 data[0] = 0; 5229 data[1] = 0; 5230 data[2] = 0; 5231 data[3] = 0; 5232 data[4] = 0; 5233 5234 for (i = 0; i < max; i++) { 5235 niu_ipp_write(np, i, data); 5236 niu_ipp_read(np, i, rbuf); 5237 } 5238 5239 (void) nr64_ipp(IPP_INT_STAT); 5240 (void) nr64_ipp(IPP_INT_STAT); 5241 5242 err = niu_ipp_reset(np); 5243 if (err) 5244 return err; 5245 5246 (void) nr64_ipp(IPP_PKT_DIS); 5247 (void) nr64_ipp(IPP_BAD_CS_CNT); 5248 (void) nr64_ipp(IPP_ECC); 5249 5250 (void) nr64_ipp(IPP_INT_STAT); 5251 5252 nw64_ipp(IPP_MSK, ~IPP_MSK_ALL); 5253 5254 val = nr64_ipp(IPP_CFIG); 5255 val &= ~IPP_CFIG_IP_MAX_PKT; 5256 val |= (IPP_CFIG_IPP_ENABLE | 5257 IPP_CFIG_DFIFO_ECC_EN | 5258 IPP_CFIG_DROP_BAD_CRC | 5259 IPP_CFIG_CKSUM_EN | 5260 (0x1ffff << IPP_CFIG_IP_MAX_PKT_SHIFT)); 5261 nw64_ipp(IPP_CFIG, val); 5262 5263 return 0; 5264 } 5265 5266 static void niu_handle_led(struct niu *np, int status) 5267 { 5268 u64 val; 5269 val = nr64_mac(XMAC_CONFIG); 5270 5271 if ((np->flags & NIU_FLAGS_10G) != 0 && 5272 (np->flags & NIU_FLAGS_FIBER) != 0) { 5273 if (status) { 5274 val |= XMAC_CONFIG_LED_POLARITY; 5275 val &= ~XMAC_CONFIG_FORCE_LED_ON; 5276 } else { 5277 val |= XMAC_CONFIG_FORCE_LED_ON; 5278 val &= ~XMAC_CONFIG_LED_POLARITY; 5279 } 5280 } 5281 5282 nw64_mac(XMAC_CONFIG, val); 5283 } 5284 5285 static void niu_init_xif_xmac(struct niu *np) 5286 { 5287 struct niu_link_config *lp = &np->link_config; 5288 u64 val; 5289 5290 if (np->flags & NIU_FLAGS_XCVR_SERDES) { 5291 val = nr64(MIF_CONFIG); 5292 val |= MIF_CONFIG_ATCA_GE; 5293 nw64(MIF_CONFIG, val); 5294 } 5295 5296 val = nr64_mac(XMAC_CONFIG); 5297 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5298 5299 val |= XMAC_CONFIG_TX_OUTPUT_EN; 5300 5301 if (lp->loopback_mode == LOOPBACK_MAC) { 5302 val &= ~XMAC_CONFIG_SEL_POR_CLK_SRC; 5303 val |= XMAC_CONFIG_LOOPBACK; 5304 } else { 5305 val &= ~XMAC_CONFIG_LOOPBACK; 5306 } 5307 5308 if (np->flags & NIU_FLAGS_10G) { 5309 val &= ~XMAC_CONFIG_LFS_DISABLE; 5310 } else { 5311 val |= XMAC_CONFIG_LFS_DISABLE; 5312 if (!(np->flags & NIU_FLAGS_FIBER) && 5313 !(np->flags & NIU_FLAGS_XCVR_SERDES)) 5314 val |= XMAC_CONFIG_1G_PCS_BYPASS; 5315 else 5316 val &= ~XMAC_CONFIG_1G_PCS_BYPASS; 5317 } 5318 5319 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5320 5321 if (lp->active_speed == SPEED_100) 5322 val |= XMAC_CONFIG_SEL_CLK_25MHZ; 5323 else 5324 val &= ~XMAC_CONFIG_SEL_CLK_25MHZ; 5325 5326 nw64_mac(XMAC_CONFIG, val); 5327 5328 val = nr64_mac(XMAC_CONFIG); 5329 val &= ~XMAC_CONFIG_MODE_MASK; 5330 if (np->flags & NIU_FLAGS_10G) { 5331 val |= XMAC_CONFIG_MODE_XGMII; 5332 } else { 5333 if (lp->active_speed == SPEED_1000) 5334 val |= XMAC_CONFIG_MODE_GMII; 5335 else 5336 val |= XMAC_CONFIG_MODE_MII; 5337 } 5338 5339 nw64_mac(XMAC_CONFIG, val); 5340 } 5341 5342 static void niu_init_xif_bmac(struct niu *np) 5343 { 5344 struct niu_link_config *lp = &np->link_config; 5345 u64 val; 5346 5347 val = BMAC_XIF_CONFIG_TX_OUTPUT_EN; 5348 5349 if (lp->loopback_mode == LOOPBACK_MAC) 5350 val |= BMAC_XIF_CONFIG_MII_LOOPBACK; 5351 else 5352 val &= ~BMAC_XIF_CONFIG_MII_LOOPBACK; 5353 5354 if (lp->active_speed == SPEED_1000) 5355 val |= BMAC_XIF_CONFIG_GMII_MODE; 5356 else 5357 val &= ~BMAC_XIF_CONFIG_GMII_MODE; 5358 5359 val &= ~(BMAC_XIF_CONFIG_LINK_LED | 5360 BMAC_XIF_CONFIG_LED_POLARITY); 5361 5362 if (!(np->flags & NIU_FLAGS_10G) && 5363 !(np->flags & NIU_FLAGS_FIBER) && 5364 lp->active_speed == SPEED_100) 5365 val |= BMAC_XIF_CONFIG_25MHZ_CLOCK; 5366 else 5367 val &= ~BMAC_XIF_CONFIG_25MHZ_CLOCK; 5368 5369 nw64_mac(BMAC_XIF_CONFIG, val); 5370 } 5371 5372 static void niu_init_xif(struct niu *np) 5373 { 5374 if (np->flags & NIU_FLAGS_XMAC) 5375 niu_init_xif_xmac(np); 5376 else 5377 niu_init_xif_bmac(np); 5378 } 5379 5380 static void niu_pcs_mii_reset(struct niu *np) 5381 { 5382 int limit = 1000; 5383 u64 val = nr64_pcs(PCS_MII_CTL); 5384 val |= PCS_MII_CTL_RST; 5385 nw64_pcs(PCS_MII_CTL, val); 5386 while ((--limit >= 0) && (val & PCS_MII_CTL_RST)) { 5387 udelay(100); 5388 val = nr64_pcs(PCS_MII_CTL); 5389 } 5390 } 5391 5392 static void niu_xpcs_reset(struct niu *np) 5393 { 5394 int limit = 1000; 5395 u64 val = nr64_xpcs(XPCS_CONTROL1); 5396 val |= XPCS_CONTROL1_RESET; 5397 nw64_xpcs(XPCS_CONTROL1, val); 5398 while ((--limit >= 0) && (val & XPCS_CONTROL1_RESET)) { 5399 udelay(100); 5400 val = nr64_xpcs(XPCS_CONTROL1); 5401 } 5402 } 5403 5404 static int niu_init_pcs(struct niu *np) 5405 { 5406 struct niu_link_config *lp = &np->link_config; 5407 u64 val; 5408 5409 switch (np->flags & (NIU_FLAGS_10G | 5410 NIU_FLAGS_FIBER | 5411 NIU_FLAGS_XCVR_SERDES)) { 5412 case NIU_FLAGS_FIBER: 5413 /* 1G fiber */ 5414 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5415 nw64_pcs(PCS_DPATH_MODE, 0); 5416 niu_pcs_mii_reset(np); 5417 break; 5418 5419 case NIU_FLAGS_10G: 5420 case NIU_FLAGS_10G | NIU_FLAGS_FIBER: 5421 case NIU_FLAGS_10G | NIU_FLAGS_XCVR_SERDES: 5422 /* 10G SERDES */ 5423 if (!(np->flags & NIU_FLAGS_XMAC)) 5424 return -EINVAL; 5425 5426 /* 10G copper or fiber */ 5427 val = nr64_mac(XMAC_CONFIG); 5428 val &= ~XMAC_CONFIG_10G_XPCS_BYPASS; 5429 nw64_mac(XMAC_CONFIG, val); 5430 5431 niu_xpcs_reset(np); 5432 5433 val = nr64_xpcs(XPCS_CONTROL1); 5434 if (lp->loopback_mode == LOOPBACK_PHY) 5435 val |= XPCS_CONTROL1_LOOPBACK; 5436 else 5437 val &= ~XPCS_CONTROL1_LOOPBACK; 5438 nw64_xpcs(XPCS_CONTROL1, val); 5439 5440 nw64_xpcs(XPCS_DESKEW_ERR_CNT, 0); 5441 (void) nr64_xpcs(XPCS_SYMERR_CNT01); 5442 (void) nr64_xpcs(XPCS_SYMERR_CNT23); 5443 break; 5444 5445 5446 case NIU_FLAGS_XCVR_SERDES: 5447 /* 1G SERDES */ 5448 niu_pcs_mii_reset(np); 5449 nw64_pcs(PCS_CONF, PCS_CONF_MASK | PCS_CONF_ENABLE); 5450 nw64_pcs(PCS_DPATH_MODE, 0); 5451 break; 5452 5453 case 0: 5454 /* 1G copper */ 5455 case NIU_FLAGS_XCVR_SERDES | NIU_FLAGS_FIBER: 5456 /* 1G RGMII FIBER */ 5457 nw64_pcs(PCS_DPATH_MODE, PCS_DPATH_MODE_MII); 5458 niu_pcs_mii_reset(np); 5459 break; 5460 5461 default: 5462 return -EINVAL; 5463 } 5464 5465 return 0; 5466 } 5467 5468 static int niu_reset_tx_xmac(struct niu *np) 5469 { 5470 return niu_set_and_wait_clear_mac(np, XTXMAC_SW_RST, 5471 (XTXMAC_SW_RST_REG_RS | 5472 XTXMAC_SW_RST_SOFT_RST), 5473 1000, 100, "XTXMAC_SW_RST"); 5474 } 5475 5476 static int niu_reset_tx_bmac(struct niu *np) 5477 { 5478 int limit; 5479 5480 nw64_mac(BTXMAC_SW_RST, BTXMAC_SW_RST_RESET); 5481 limit = 1000; 5482 while (--limit >= 0) { 5483 if (!(nr64_mac(BTXMAC_SW_RST) & BTXMAC_SW_RST_RESET)) 5484 break; 5485 udelay(100); 5486 } 5487 if (limit < 0) { 5488 dev_err(np->device, "Port %u TX BMAC would not reset, BTXMAC_SW_RST[%llx]\n", 5489 np->port, 5490 (unsigned long long) nr64_mac(BTXMAC_SW_RST)); 5491 return -ENODEV; 5492 } 5493 5494 return 0; 5495 } 5496 5497 static int niu_reset_tx_mac(struct niu *np) 5498 { 5499 if (np->flags & NIU_FLAGS_XMAC) 5500 return niu_reset_tx_xmac(np); 5501 else 5502 return niu_reset_tx_bmac(np); 5503 } 5504 5505 static void niu_init_tx_xmac(struct niu *np, u64 min, u64 max) 5506 { 5507 u64 val; 5508 5509 val = nr64_mac(XMAC_MIN); 5510 val &= ~(XMAC_MIN_TX_MIN_PKT_SIZE | 5511 XMAC_MIN_RX_MIN_PKT_SIZE); 5512 val |= (min << XMAC_MIN_RX_MIN_PKT_SIZE_SHFT); 5513 val |= (min << XMAC_MIN_TX_MIN_PKT_SIZE_SHFT); 5514 nw64_mac(XMAC_MIN, val); 5515 5516 nw64_mac(XMAC_MAX, max); 5517 5518 nw64_mac(XTXMAC_STAT_MSK, ~(u64)0); 5519 5520 val = nr64_mac(XMAC_IPG); 5521 if (np->flags & NIU_FLAGS_10G) { 5522 val &= ~XMAC_IPG_IPG_XGMII; 5523 val |= (IPG_12_15_XGMII << XMAC_IPG_IPG_XGMII_SHIFT); 5524 } else { 5525 val &= ~XMAC_IPG_IPG_MII_GMII; 5526 val |= (IPG_12_MII_GMII << XMAC_IPG_IPG_MII_GMII_SHIFT); 5527 } 5528 nw64_mac(XMAC_IPG, val); 5529 5530 val = nr64_mac(XMAC_CONFIG); 5531 val &= ~(XMAC_CONFIG_ALWAYS_NO_CRC | 5532 XMAC_CONFIG_STRETCH_MODE | 5533 XMAC_CONFIG_VAR_MIN_IPG_EN | 5534 XMAC_CONFIG_TX_ENABLE); 5535 nw64_mac(XMAC_CONFIG, val); 5536 5537 nw64_mac(TXMAC_FRM_CNT, 0); 5538 nw64_mac(TXMAC_BYTE_CNT, 0); 5539 } 5540 5541 static void niu_init_tx_bmac(struct niu *np, u64 min, u64 max) 5542 { 5543 u64 val; 5544 5545 nw64_mac(BMAC_MIN_FRAME, min); 5546 nw64_mac(BMAC_MAX_FRAME, max); 5547 5548 nw64_mac(BTXMAC_STATUS_MASK, ~(u64)0); 5549 nw64_mac(BMAC_CTRL_TYPE, 0x8808); 5550 nw64_mac(BMAC_PREAMBLE_SIZE, 7); 5551 5552 val = nr64_mac(BTXMAC_CONFIG); 5553 val &= ~(BTXMAC_CONFIG_FCS_DISABLE | 5554 BTXMAC_CONFIG_ENABLE); 5555 nw64_mac(BTXMAC_CONFIG, val); 5556 } 5557 5558 static void niu_init_tx_mac(struct niu *np) 5559 { 5560 u64 min, max; 5561 5562 min = 64; 5563 if (np->dev->mtu > ETH_DATA_LEN) 5564 max = 9216; 5565 else 5566 max = 1522; 5567 5568 /* The XMAC_MIN register only accepts values for TX min which 5569 * have the low 3 bits cleared. 5570 */ 5571 BUG_ON(min & 0x7); 5572 5573 if (np->flags & NIU_FLAGS_XMAC) 5574 niu_init_tx_xmac(np, min, max); 5575 else 5576 niu_init_tx_bmac(np, min, max); 5577 } 5578 5579 static int niu_reset_rx_xmac(struct niu *np) 5580 { 5581 int limit; 5582 5583 nw64_mac(XRXMAC_SW_RST, 5584 XRXMAC_SW_RST_REG_RS | XRXMAC_SW_RST_SOFT_RST); 5585 limit = 1000; 5586 while (--limit >= 0) { 5587 if (!(nr64_mac(XRXMAC_SW_RST) & (XRXMAC_SW_RST_REG_RS | 5588 XRXMAC_SW_RST_SOFT_RST))) 5589 break; 5590 udelay(100); 5591 } 5592 if (limit < 0) { 5593 dev_err(np->device, "Port %u RX XMAC would not reset, XRXMAC_SW_RST[%llx]\n", 5594 np->port, 5595 (unsigned long long) nr64_mac(XRXMAC_SW_RST)); 5596 return -ENODEV; 5597 } 5598 5599 return 0; 5600 } 5601 5602 static int niu_reset_rx_bmac(struct niu *np) 5603 { 5604 int limit; 5605 5606 nw64_mac(BRXMAC_SW_RST, BRXMAC_SW_RST_RESET); 5607 limit = 1000; 5608 while (--limit >= 0) { 5609 if (!(nr64_mac(BRXMAC_SW_RST) & BRXMAC_SW_RST_RESET)) 5610 break; 5611 udelay(100); 5612 } 5613 if (limit < 0) { 5614 dev_err(np->device, "Port %u RX BMAC would not reset, BRXMAC_SW_RST[%llx]\n", 5615 np->port, 5616 (unsigned long long) nr64_mac(BRXMAC_SW_RST)); 5617 return -ENODEV; 5618 } 5619 5620 return 0; 5621 } 5622 5623 static int niu_reset_rx_mac(struct niu *np) 5624 { 5625 if (np->flags & NIU_FLAGS_XMAC) 5626 return niu_reset_rx_xmac(np); 5627 else 5628 return niu_reset_rx_bmac(np); 5629 } 5630 5631 static void niu_init_rx_xmac(struct niu *np) 5632 { 5633 struct niu_parent *parent = np->parent; 5634 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5635 int first_rdc_table = tp->first_table_num; 5636 unsigned long i; 5637 u64 val; 5638 5639 nw64_mac(XMAC_ADD_FILT0, 0); 5640 nw64_mac(XMAC_ADD_FILT1, 0); 5641 nw64_mac(XMAC_ADD_FILT2, 0); 5642 nw64_mac(XMAC_ADD_FILT12_MASK, 0); 5643 nw64_mac(XMAC_ADD_FILT00_MASK, 0); 5644 for (i = 0; i < MAC_NUM_HASH; i++) 5645 nw64_mac(XMAC_HASH_TBL(i), 0); 5646 nw64_mac(XRXMAC_STAT_MSK, ~(u64)0); 5647 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5648 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5649 5650 val = nr64_mac(XMAC_CONFIG); 5651 val &= ~(XMAC_CONFIG_RX_MAC_ENABLE | 5652 XMAC_CONFIG_PROMISCUOUS | 5653 XMAC_CONFIG_PROMISC_GROUP | 5654 XMAC_CONFIG_ERR_CHK_DIS | 5655 XMAC_CONFIG_RX_CRC_CHK_DIS | 5656 XMAC_CONFIG_RESERVED_MULTICAST | 5657 XMAC_CONFIG_RX_CODEV_CHK_DIS | 5658 XMAC_CONFIG_ADDR_FILTER_EN | 5659 XMAC_CONFIG_RCV_PAUSE_ENABLE | 5660 XMAC_CONFIG_STRIP_CRC | 5661 XMAC_CONFIG_PASS_FLOW_CTRL | 5662 XMAC_CONFIG_MAC2IPP_PKT_CNT_EN); 5663 val |= (XMAC_CONFIG_HASH_FILTER_EN); 5664 nw64_mac(XMAC_CONFIG, val); 5665 5666 nw64_mac(RXMAC_BT_CNT, 0); 5667 nw64_mac(RXMAC_BC_FRM_CNT, 0); 5668 nw64_mac(RXMAC_MC_FRM_CNT, 0); 5669 nw64_mac(RXMAC_FRAG_CNT, 0); 5670 nw64_mac(RXMAC_HIST_CNT1, 0); 5671 nw64_mac(RXMAC_HIST_CNT2, 0); 5672 nw64_mac(RXMAC_HIST_CNT3, 0); 5673 nw64_mac(RXMAC_HIST_CNT4, 0); 5674 nw64_mac(RXMAC_HIST_CNT5, 0); 5675 nw64_mac(RXMAC_HIST_CNT6, 0); 5676 nw64_mac(RXMAC_HIST_CNT7, 0); 5677 nw64_mac(RXMAC_MPSZER_CNT, 0); 5678 nw64_mac(RXMAC_CRC_ER_CNT, 0); 5679 nw64_mac(RXMAC_CD_VIO_CNT, 0); 5680 nw64_mac(LINK_FAULT_CNT, 0); 5681 } 5682 5683 static void niu_init_rx_bmac(struct niu *np) 5684 { 5685 struct niu_parent *parent = np->parent; 5686 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[np->port]; 5687 int first_rdc_table = tp->first_table_num; 5688 unsigned long i; 5689 u64 val; 5690 5691 nw64_mac(BMAC_ADD_FILT0, 0); 5692 nw64_mac(BMAC_ADD_FILT1, 0); 5693 nw64_mac(BMAC_ADD_FILT2, 0); 5694 nw64_mac(BMAC_ADD_FILT12_MASK, 0); 5695 nw64_mac(BMAC_ADD_FILT00_MASK, 0); 5696 for (i = 0; i < MAC_NUM_HASH; i++) 5697 nw64_mac(BMAC_HASH_TBL(i), 0); 5698 niu_set_primary_mac_rdc_table(np, first_rdc_table, 1); 5699 niu_set_multicast_mac_rdc_table(np, first_rdc_table, 1); 5700 nw64_mac(BRXMAC_STATUS_MASK, ~(u64)0); 5701 5702 val = nr64_mac(BRXMAC_CONFIG); 5703 val &= ~(BRXMAC_CONFIG_ENABLE | 5704 BRXMAC_CONFIG_STRIP_PAD | 5705 BRXMAC_CONFIG_STRIP_FCS | 5706 BRXMAC_CONFIG_PROMISC | 5707 BRXMAC_CONFIG_PROMISC_GRP | 5708 BRXMAC_CONFIG_ADDR_FILT_EN | 5709 BRXMAC_CONFIG_DISCARD_DIS); 5710 val |= (BRXMAC_CONFIG_HASH_FILT_EN); 5711 nw64_mac(BRXMAC_CONFIG, val); 5712 5713 val = nr64_mac(BMAC_ADDR_CMPEN); 5714 val |= BMAC_ADDR_CMPEN_EN0; 5715 nw64_mac(BMAC_ADDR_CMPEN, val); 5716 } 5717 5718 static void niu_init_rx_mac(struct niu *np) 5719 { 5720 niu_set_primary_mac(np, np->dev->dev_addr); 5721 5722 if (np->flags & NIU_FLAGS_XMAC) 5723 niu_init_rx_xmac(np); 5724 else 5725 niu_init_rx_bmac(np); 5726 } 5727 5728 static void niu_enable_tx_xmac(struct niu *np, int on) 5729 { 5730 u64 val = nr64_mac(XMAC_CONFIG); 5731 5732 if (on) 5733 val |= XMAC_CONFIG_TX_ENABLE; 5734 else 5735 val &= ~XMAC_CONFIG_TX_ENABLE; 5736 nw64_mac(XMAC_CONFIG, val); 5737 } 5738 5739 static void niu_enable_tx_bmac(struct niu *np, int on) 5740 { 5741 u64 val = nr64_mac(BTXMAC_CONFIG); 5742 5743 if (on) 5744 val |= BTXMAC_CONFIG_ENABLE; 5745 else 5746 val &= ~BTXMAC_CONFIG_ENABLE; 5747 nw64_mac(BTXMAC_CONFIG, val); 5748 } 5749 5750 static void niu_enable_tx_mac(struct niu *np, int on) 5751 { 5752 if (np->flags & NIU_FLAGS_XMAC) 5753 niu_enable_tx_xmac(np, on); 5754 else 5755 niu_enable_tx_bmac(np, on); 5756 } 5757 5758 static void niu_enable_rx_xmac(struct niu *np, int on) 5759 { 5760 u64 val = nr64_mac(XMAC_CONFIG); 5761 5762 val &= ~(XMAC_CONFIG_HASH_FILTER_EN | 5763 XMAC_CONFIG_PROMISCUOUS); 5764 5765 if (np->flags & NIU_FLAGS_MCAST) 5766 val |= XMAC_CONFIG_HASH_FILTER_EN; 5767 if (np->flags & NIU_FLAGS_PROMISC) 5768 val |= XMAC_CONFIG_PROMISCUOUS; 5769 5770 if (on) 5771 val |= XMAC_CONFIG_RX_MAC_ENABLE; 5772 else 5773 val &= ~XMAC_CONFIG_RX_MAC_ENABLE; 5774 nw64_mac(XMAC_CONFIG, val); 5775 } 5776 5777 static void niu_enable_rx_bmac(struct niu *np, int on) 5778 { 5779 u64 val = nr64_mac(BRXMAC_CONFIG); 5780 5781 val &= ~(BRXMAC_CONFIG_HASH_FILT_EN | 5782 BRXMAC_CONFIG_PROMISC); 5783 5784 if (np->flags & NIU_FLAGS_MCAST) 5785 val |= BRXMAC_CONFIG_HASH_FILT_EN; 5786 if (np->flags & NIU_FLAGS_PROMISC) 5787 val |= BRXMAC_CONFIG_PROMISC; 5788 5789 if (on) 5790 val |= BRXMAC_CONFIG_ENABLE; 5791 else 5792 val &= ~BRXMAC_CONFIG_ENABLE; 5793 nw64_mac(BRXMAC_CONFIG, val); 5794 } 5795 5796 static void niu_enable_rx_mac(struct niu *np, int on) 5797 { 5798 if (np->flags & NIU_FLAGS_XMAC) 5799 niu_enable_rx_xmac(np, on); 5800 else 5801 niu_enable_rx_bmac(np, on); 5802 } 5803 5804 static int niu_init_mac(struct niu *np) 5805 { 5806 int err; 5807 5808 niu_init_xif(np); 5809 err = niu_init_pcs(np); 5810 if (err) 5811 return err; 5812 5813 err = niu_reset_tx_mac(np); 5814 if (err) 5815 return err; 5816 niu_init_tx_mac(np); 5817 err = niu_reset_rx_mac(np); 5818 if (err) 5819 return err; 5820 niu_init_rx_mac(np); 5821 5822 /* This looks hookey but the RX MAC reset we just did will 5823 * undo some of the state we setup in niu_init_tx_mac() so we 5824 * have to call it again. In particular, the RX MAC reset will 5825 * set the XMAC_MAX register back to its default value. 5826 */ 5827 niu_init_tx_mac(np); 5828 niu_enable_tx_mac(np, 1); 5829 5830 niu_enable_rx_mac(np, 1); 5831 5832 return 0; 5833 } 5834 5835 static void niu_stop_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5836 { 5837 (void) niu_tx_channel_stop(np, rp->tx_channel); 5838 } 5839 5840 static void niu_stop_tx_channels(struct niu *np) 5841 { 5842 int i; 5843 5844 for (i = 0; i < np->num_tx_rings; i++) { 5845 struct tx_ring_info *rp = &np->tx_rings[i]; 5846 5847 niu_stop_one_tx_channel(np, rp); 5848 } 5849 } 5850 5851 static void niu_reset_one_tx_channel(struct niu *np, struct tx_ring_info *rp) 5852 { 5853 (void) niu_tx_channel_reset(np, rp->tx_channel); 5854 } 5855 5856 static void niu_reset_tx_channels(struct niu *np) 5857 { 5858 int i; 5859 5860 for (i = 0; i < np->num_tx_rings; i++) { 5861 struct tx_ring_info *rp = &np->tx_rings[i]; 5862 5863 niu_reset_one_tx_channel(np, rp); 5864 } 5865 } 5866 5867 static void niu_stop_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5868 { 5869 (void) niu_enable_rx_channel(np, rp->rx_channel, 0); 5870 } 5871 5872 static void niu_stop_rx_channels(struct niu *np) 5873 { 5874 int i; 5875 5876 for (i = 0; i < np->num_rx_rings; i++) { 5877 struct rx_ring_info *rp = &np->rx_rings[i]; 5878 5879 niu_stop_one_rx_channel(np, rp); 5880 } 5881 } 5882 5883 static void niu_reset_one_rx_channel(struct niu *np, struct rx_ring_info *rp) 5884 { 5885 int channel = rp->rx_channel; 5886 5887 (void) niu_rx_channel_reset(np, channel); 5888 nw64(RX_DMA_ENT_MSK(channel), RX_DMA_ENT_MSK_ALL); 5889 nw64(RX_DMA_CTL_STAT(channel), 0); 5890 (void) niu_enable_rx_channel(np, channel, 0); 5891 } 5892 5893 static void niu_reset_rx_channels(struct niu *np) 5894 { 5895 int i; 5896 5897 for (i = 0; i < np->num_rx_rings; i++) { 5898 struct rx_ring_info *rp = &np->rx_rings[i]; 5899 5900 niu_reset_one_rx_channel(np, rp); 5901 } 5902 } 5903 5904 static void niu_disable_ipp(struct niu *np) 5905 { 5906 u64 rd, wr, val; 5907 int limit; 5908 5909 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5910 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5911 limit = 100; 5912 while (--limit >= 0 && (rd != wr)) { 5913 rd = nr64_ipp(IPP_DFIFO_RD_PTR); 5914 wr = nr64_ipp(IPP_DFIFO_WR_PTR); 5915 } 5916 if (limit < 0 && 5917 (rd != 0 && wr != 1)) { 5918 netdev_err(np->dev, "IPP would not quiesce, rd_ptr[%llx] wr_ptr[%llx]\n", 5919 (unsigned long long)nr64_ipp(IPP_DFIFO_RD_PTR), 5920 (unsigned long long)nr64_ipp(IPP_DFIFO_WR_PTR)); 5921 } 5922 5923 val = nr64_ipp(IPP_CFIG); 5924 val &= ~(IPP_CFIG_IPP_ENABLE | 5925 IPP_CFIG_DFIFO_ECC_EN | 5926 IPP_CFIG_DROP_BAD_CRC | 5927 IPP_CFIG_CKSUM_EN); 5928 nw64_ipp(IPP_CFIG, val); 5929 5930 (void) niu_ipp_reset(np); 5931 } 5932 5933 static int niu_init_hw(struct niu *np) 5934 { 5935 int i, err; 5936 5937 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TXC\n"); 5938 niu_txc_enable_port(np, 1); 5939 niu_txc_port_dma_enable(np, 1); 5940 niu_txc_set_imask(np, 0); 5941 5942 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize TX channels\n"); 5943 for (i = 0; i < np->num_tx_rings; i++) { 5944 struct tx_ring_info *rp = &np->tx_rings[i]; 5945 5946 err = niu_init_one_tx_channel(np, rp); 5947 if (err) 5948 return err; 5949 } 5950 5951 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize RX channels\n"); 5952 err = niu_init_rx_channels(np); 5953 if (err) 5954 goto out_uninit_tx_channels; 5955 5956 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize classifier\n"); 5957 err = niu_init_classifier_hw(np); 5958 if (err) 5959 goto out_uninit_rx_channels; 5960 5961 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize ZCP\n"); 5962 err = niu_init_zcp(np); 5963 if (err) 5964 goto out_uninit_rx_channels; 5965 5966 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize IPP\n"); 5967 err = niu_init_ipp(np); 5968 if (err) 5969 goto out_uninit_rx_channels; 5970 5971 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Initialize MAC\n"); 5972 err = niu_init_mac(np); 5973 if (err) 5974 goto out_uninit_ipp; 5975 5976 return 0; 5977 5978 out_uninit_ipp: 5979 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit IPP\n"); 5980 niu_disable_ipp(np); 5981 5982 out_uninit_rx_channels: 5983 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit RX channels\n"); 5984 niu_stop_rx_channels(np); 5985 niu_reset_rx_channels(np); 5986 5987 out_uninit_tx_channels: 5988 netif_printk(np, ifup, KERN_DEBUG, np->dev, "Uninit TX channels\n"); 5989 niu_stop_tx_channels(np); 5990 niu_reset_tx_channels(np); 5991 5992 return err; 5993 } 5994 5995 static void niu_stop_hw(struct niu *np) 5996 { 5997 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable interrupts\n"); 5998 niu_enable_interrupts(np, 0); 5999 6000 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable RX MAC\n"); 6001 niu_enable_rx_mac(np, 0); 6002 6003 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Disable IPP\n"); 6004 niu_disable_ipp(np); 6005 6006 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop TX channels\n"); 6007 niu_stop_tx_channels(np); 6008 6009 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Stop RX channels\n"); 6010 niu_stop_rx_channels(np); 6011 6012 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset TX channels\n"); 6013 niu_reset_tx_channels(np); 6014 6015 netif_printk(np, ifdown, KERN_DEBUG, np->dev, "Reset RX channels\n"); 6016 niu_reset_rx_channels(np); 6017 } 6018 6019 static void niu_set_irq_name(struct niu *np) 6020 { 6021 int port = np->port; 6022 int i, j = 1; 6023 6024 sprintf(np->irq_name[0], "%s:MAC", np->dev->name); 6025 6026 if (port == 0) { 6027 sprintf(np->irq_name[1], "%s:MIF", np->dev->name); 6028 sprintf(np->irq_name[2], "%s:SYSERR", np->dev->name); 6029 j = 3; 6030 } 6031 6032 for (i = 0; i < np->num_ldg - j; i++) { 6033 if (i < np->num_rx_rings) 6034 sprintf(np->irq_name[i+j], "%s-rx-%d", 6035 np->dev->name, i); 6036 else if (i < np->num_tx_rings + np->num_rx_rings) 6037 sprintf(np->irq_name[i+j], "%s-tx-%d", np->dev->name, 6038 i - np->num_rx_rings); 6039 } 6040 } 6041 6042 static int niu_request_irq(struct niu *np) 6043 { 6044 int i, j, err; 6045 6046 niu_set_irq_name(np); 6047 6048 err = 0; 6049 for (i = 0; i < np->num_ldg; i++) { 6050 struct niu_ldg *lp = &np->ldg[i]; 6051 6052 err = request_irq(lp->irq, niu_interrupt, IRQF_SHARED, 6053 np->irq_name[i], lp); 6054 if (err) 6055 goto out_free_irqs; 6056 6057 } 6058 6059 return 0; 6060 6061 out_free_irqs: 6062 for (j = 0; j < i; j++) { 6063 struct niu_ldg *lp = &np->ldg[j]; 6064 6065 free_irq(lp->irq, lp); 6066 } 6067 return err; 6068 } 6069 6070 static void niu_free_irq(struct niu *np) 6071 { 6072 int i; 6073 6074 for (i = 0; i < np->num_ldg; i++) { 6075 struct niu_ldg *lp = &np->ldg[i]; 6076 6077 free_irq(lp->irq, lp); 6078 } 6079 } 6080 6081 static void niu_enable_napi(struct niu *np) 6082 { 6083 int i; 6084 6085 for (i = 0; i < np->num_ldg; i++) 6086 napi_enable_locked(&np->ldg[i].napi); 6087 } 6088 6089 static void niu_disable_napi(struct niu *np) 6090 { 6091 int i; 6092 6093 for (i = 0; i < np->num_ldg; i++) 6094 napi_disable(&np->ldg[i].napi); 6095 } 6096 6097 static int niu_open(struct net_device *dev) 6098 { 6099 struct niu *np = netdev_priv(dev); 6100 int err; 6101 6102 netif_carrier_off(dev); 6103 6104 err = niu_alloc_channels(np); 6105 if (err) 6106 goto out_err; 6107 6108 err = niu_enable_interrupts(np, 0); 6109 if (err) 6110 goto out_free_channels; 6111 6112 err = niu_request_irq(np); 6113 if (err) 6114 goto out_free_channels; 6115 6116 netdev_lock(dev); 6117 niu_enable_napi(np); 6118 netdev_unlock(dev); 6119 6120 spin_lock_irq(&np->lock); 6121 6122 err = niu_init_hw(np); 6123 if (!err) { 6124 timer_setup(&np->timer, niu_timer, 0); 6125 np->timer.expires = jiffies + HZ; 6126 6127 err = niu_enable_interrupts(np, 1); 6128 if (err) 6129 niu_stop_hw(np); 6130 } 6131 6132 spin_unlock_irq(&np->lock); 6133 6134 if (err) { 6135 niu_disable_napi(np); 6136 goto out_free_irq; 6137 } 6138 6139 netif_tx_start_all_queues(dev); 6140 6141 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6142 netif_carrier_on(dev); 6143 6144 add_timer(&np->timer); 6145 6146 return 0; 6147 6148 out_free_irq: 6149 niu_free_irq(np); 6150 6151 out_free_channels: 6152 niu_free_channels(np); 6153 6154 out_err: 6155 return err; 6156 } 6157 6158 static void niu_full_shutdown(struct niu *np, struct net_device *dev) 6159 { 6160 cancel_work_sync(&np->reset_task); 6161 6162 niu_disable_napi(np); 6163 netif_tx_stop_all_queues(dev); 6164 6165 timer_delete_sync(&np->timer); 6166 6167 spin_lock_irq(&np->lock); 6168 6169 niu_stop_hw(np); 6170 6171 spin_unlock_irq(&np->lock); 6172 } 6173 6174 static int niu_close(struct net_device *dev) 6175 { 6176 struct niu *np = netdev_priv(dev); 6177 6178 niu_full_shutdown(np, dev); 6179 6180 niu_free_irq(np); 6181 6182 niu_free_channels(np); 6183 6184 niu_handle_led(np, 0); 6185 6186 return 0; 6187 } 6188 6189 static void niu_sync_xmac_stats(struct niu *np) 6190 { 6191 struct niu_xmac_stats *mp = &np->mac_stats.xmac; 6192 6193 mp->tx_frames += nr64_mac(TXMAC_FRM_CNT); 6194 mp->tx_bytes += nr64_mac(TXMAC_BYTE_CNT); 6195 6196 mp->rx_link_faults += nr64_mac(LINK_FAULT_CNT); 6197 mp->rx_align_errors += nr64_mac(RXMAC_ALIGN_ERR_CNT); 6198 mp->rx_frags += nr64_mac(RXMAC_FRAG_CNT); 6199 mp->rx_mcasts += nr64_mac(RXMAC_MC_FRM_CNT); 6200 mp->rx_bcasts += nr64_mac(RXMAC_BC_FRM_CNT); 6201 mp->rx_hist_cnt1 += nr64_mac(RXMAC_HIST_CNT1); 6202 mp->rx_hist_cnt2 += nr64_mac(RXMAC_HIST_CNT2); 6203 mp->rx_hist_cnt3 += nr64_mac(RXMAC_HIST_CNT3); 6204 mp->rx_hist_cnt4 += nr64_mac(RXMAC_HIST_CNT4); 6205 mp->rx_hist_cnt5 += nr64_mac(RXMAC_HIST_CNT5); 6206 mp->rx_hist_cnt6 += nr64_mac(RXMAC_HIST_CNT6); 6207 mp->rx_hist_cnt7 += nr64_mac(RXMAC_HIST_CNT7); 6208 mp->rx_octets += nr64_mac(RXMAC_BT_CNT); 6209 mp->rx_code_violations += nr64_mac(RXMAC_CD_VIO_CNT); 6210 mp->rx_len_errors += nr64_mac(RXMAC_MPSZER_CNT); 6211 mp->rx_crc_errors += nr64_mac(RXMAC_CRC_ER_CNT); 6212 } 6213 6214 static void niu_sync_bmac_stats(struct niu *np) 6215 { 6216 struct niu_bmac_stats *mp = &np->mac_stats.bmac; 6217 6218 mp->tx_bytes += nr64_mac(BTXMAC_BYTE_CNT); 6219 mp->tx_frames += nr64_mac(BTXMAC_FRM_CNT); 6220 6221 mp->rx_frames += nr64_mac(BRXMAC_FRAME_CNT); 6222 mp->rx_align_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6223 mp->rx_crc_errors += nr64_mac(BRXMAC_ALIGN_ERR_CNT); 6224 mp->rx_len_errors += nr64_mac(BRXMAC_CODE_VIOL_ERR_CNT); 6225 } 6226 6227 static void niu_sync_mac_stats(struct niu *np) 6228 { 6229 if (np->flags & NIU_FLAGS_XMAC) 6230 niu_sync_xmac_stats(np); 6231 else 6232 niu_sync_bmac_stats(np); 6233 } 6234 6235 static void niu_get_rx_stats(struct niu *np, 6236 struct rtnl_link_stats64 *stats) 6237 { 6238 u64 pkts, dropped, errors, bytes; 6239 struct rx_ring_info *rx_rings; 6240 int i; 6241 6242 pkts = dropped = errors = bytes = 0; 6243 6244 rx_rings = READ_ONCE(np->rx_rings); 6245 if (!rx_rings) 6246 goto no_rings; 6247 6248 for (i = 0; i < np->num_rx_rings; i++) { 6249 struct rx_ring_info *rp = &rx_rings[i]; 6250 6251 niu_sync_rx_discard_stats(np, rp, 0); 6252 6253 pkts += rp->rx_packets; 6254 bytes += rp->rx_bytes; 6255 dropped += rp->rx_dropped; 6256 errors += rp->rx_errors; 6257 } 6258 6259 no_rings: 6260 stats->rx_packets = pkts; 6261 stats->rx_bytes = bytes; 6262 stats->rx_dropped = dropped; 6263 stats->rx_errors = errors; 6264 } 6265 6266 static void niu_get_tx_stats(struct niu *np, 6267 struct rtnl_link_stats64 *stats) 6268 { 6269 u64 pkts, errors, bytes; 6270 struct tx_ring_info *tx_rings; 6271 int i; 6272 6273 pkts = errors = bytes = 0; 6274 6275 tx_rings = READ_ONCE(np->tx_rings); 6276 if (!tx_rings) 6277 goto no_rings; 6278 6279 for (i = 0; i < np->num_tx_rings; i++) { 6280 struct tx_ring_info *rp = &tx_rings[i]; 6281 6282 pkts += rp->tx_packets; 6283 bytes += rp->tx_bytes; 6284 errors += rp->tx_errors; 6285 } 6286 6287 no_rings: 6288 stats->tx_packets = pkts; 6289 stats->tx_bytes = bytes; 6290 stats->tx_errors = errors; 6291 } 6292 6293 static void niu_get_stats(struct net_device *dev, 6294 struct rtnl_link_stats64 *stats) 6295 { 6296 struct niu *np = netdev_priv(dev); 6297 6298 if (netif_running(dev)) { 6299 niu_get_rx_stats(np, stats); 6300 niu_get_tx_stats(np, stats); 6301 } 6302 } 6303 6304 static void niu_load_hash_xmac(struct niu *np, u16 *hash) 6305 { 6306 int i; 6307 6308 for (i = 0; i < 16; i++) 6309 nw64_mac(XMAC_HASH_TBL(i), hash[i]); 6310 } 6311 6312 static void niu_load_hash_bmac(struct niu *np, u16 *hash) 6313 { 6314 int i; 6315 6316 for (i = 0; i < 16; i++) 6317 nw64_mac(BMAC_HASH_TBL(i), hash[i]); 6318 } 6319 6320 static void niu_load_hash(struct niu *np, u16 *hash) 6321 { 6322 if (np->flags & NIU_FLAGS_XMAC) 6323 niu_load_hash_xmac(np, hash); 6324 else 6325 niu_load_hash_bmac(np, hash); 6326 } 6327 6328 static void niu_set_rx_mode(struct net_device *dev) 6329 { 6330 struct niu *np = netdev_priv(dev); 6331 int i, alt_cnt, err; 6332 struct netdev_hw_addr *ha; 6333 unsigned long flags; 6334 u16 hash[16] = { 0, }; 6335 6336 spin_lock_irqsave(&np->lock, flags); 6337 niu_enable_rx_mac(np, 0); 6338 6339 np->flags &= ~(NIU_FLAGS_MCAST | NIU_FLAGS_PROMISC); 6340 if (dev->flags & IFF_PROMISC) 6341 np->flags |= NIU_FLAGS_PROMISC; 6342 if ((dev->flags & IFF_ALLMULTI) || (!netdev_mc_empty(dev))) 6343 np->flags |= NIU_FLAGS_MCAST; 6344 6345 alt_cnt = netdev_uc_count(dev); 6346 if (alt_cnt > niu_num_alt_addr(np)) { 6347 alt_cnt = 0; 6348 np->flags |= NIU_FLAGS_PROMISC; 6349 } 6350 6351 if (alt_cnt) { 6352 int index = 0; 6353 6354 netdev_for_each_uc_addr(ha, dev) { 6355 err = niu_set_alt_mac(np, index, ha->addr); 6356 if (err) 6357 netdev_warn(dev, "Error %d adding alt mac %d\n", 6358 err, index); 6359 err = niu_enable_alt_mac(np, index, 1); 6360 if (err) 6361 netdev_warn(dev, "Error %d enabling alt mac %d\n", 6362 err, index); 6363 6364 index++; 6365 } 6366 } else { 6367 int alt_start; 6368 if (np->flags & NIU_FLAGS_XMAC) 6369 alt_start = 0; 6370 else 6371 alt_start = 1; 6372 for (i = alt_start; i < niu_num_alt_addr(np); i++) { 6373 err = niu_enable_alt_mac(np, i, 0); 6374 if (err) 6375 netdev_warn(dev, "Error %d disabling alt mac %d\n", 6376 err, i); 6377 } 6378 } 6379 if (dev->flags & IFF_ALLMULTI) { 6380 for (i = 0; i < 16; i++) 6381 hash[i] = 0xffff; 6382 } else if (!netdev_mc_empty(dev)) { 6383 netdev_for_each_mc_addr(ha, dev) { 6384 u32 crc = ether_crc_le(ETH_ALEN, ha->addr); 6385 6386 crc >>= 24; 6387 hash[crc >> 4] |= (1 << (15 - (crc & 0xf))); 6388 } 6389 } 6390 6391 if (np->flags & NIU_FLAGS_MCAST) 6392 niu_load_hash(np, hash); 6393 6394 niu_enable_rx_mac(np, 1); 6395 spin_unlock_irqrestore(&np->lock, flags); 6396 } 6397 6398 static int niu_set_mac_addr(struct net_device *dev, void *p) 6399 { 6400 struct niu *np = netdev_priv(dev); 6401 struct sockaddr *addr = p; 6402 unsigned long flags; 6403 6404 if (!is_valid_ether_addr(addr->sa_data)) 6405 return -EADDRNOTAVAIL; 6406 6407 eth_hw_addr_set(dev, addr->sa_data); 6408 6409 if (!netif_running(dev)) 6410 return 0; 6411 6412 spin_lock_irqsave(&np->lock, flags); 6413 niu_enable_rx_mac(np, 0); 6414 niu_set_primary_mac(np, dev->dev_addr); 6415 niu_enable_rx_mac(np, 1); 6416 spin_unlock_irqrestore(&np->lock, flags); 6417 6418 return 0; 6419 } 6420 6421 static int niu_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 6422 { 6423 return -EOPNOTSUPP; 6424 } 6425 6426 static void niu_netif_stop(struct niu *np) 6427 { 6428 netif_trans_update(np->dev); /* prevent tx timeout */ 6429 6430 niu_disable_napi(np); 6431 6432 netif_tx_disable(np->dev); 6433 } 6434 6435 static void niu_netif_start(struct niu *np) 6436 { 6437 /* NOTE: unconditional netif_wake_queue is only appropriate 6438 * so long as all callers are assured to have free tx slots 6439 * (such as after niu_init_hw). 6440 */ 6441 netif_tx_wake_all_queues(np->dev); 6442 6443 niu_enable_napi(np); 6444 6445 niu_enable_interrupts(np, 1); 6446 } 6447 6448 static void niu_reset_buffers(struct niu *np) 6449 { 6450 int i, j, k, err; 6451 6452 if (np->rx_rings) { 6453 for (i = 0; i < np->num_rx_rings; i++) { 6454 struct rx_ring_info *rp = &np->rx_rings[i]; 6455 6456 for (j = 0, k = 0; j < MAX_RBR_RING_SIZE; j++) { 6457 struct page *page; 6458 6459 page = rp->rxhash[j]; 6460 while (page) { 6461 struct page *next = niu_next_page(page); 6462 u64 base = page->private; 6463 base = base >> RBR_DESCR_ADDR_SHIFT; 6464 rp->rbr[k++] = cpu_to_le32(base); 6465 page = next; 6466 } 6467 } 6468 for (; k < MAX_RBR_RING_SIZE; k++) { 6469 err = niu_rbr_add_page(np, rp, GFP_ATOMIC, k); 6470 if (unlikely(err)) 6471 break; 6472 } 6473 6474 rp->rbr_index = rp->rbr_table_size - 1; 6475 rp->rcr_index = 0; 6476 rp->rbr_pending = 0; 6477 rp->rbr_refill_pending = 0; 6478 } 6479 } 6480 if (np->tx_rings) { 6481 for (i = 0; i < np->num_tx_rings; i++) { 6482 struct tx_ring_info *rp = &np->tx_rings[i]; 6483 6484 for (j = 0; j < MAX_TX_RING_SIZE; j++) { 6485 if (rp->tx_buffs[j].skb) 6486 (void) release_tx_packet(np, rp, j); 6487 } 6488 6489 rp->pending = MAX_TX_RING_SIZE; 6490 rp->prod = 0; 6491 rp->cons = 0; 6492 rp->wrap_bit = 0; 6493 } 6494 } 6495 } 6496 6497 static void niu_reset_task(struct work_struct *work) 6498 { 6499 struct niu *np = container_of(work, struct niu, reset_task); 6500 unsigned long flags; 6501 int err; 6502 6503 spin_lock_irqsave(&np->lock, flags); 6504 if (!netif_running(np->dev)) { 6505 spin_unlock_irqrestore(&np->lock, flags); 6506 return; 6507 } 6508 6509 spin_unlock_irqrestore(&np->lock, flags); 6510 6511 timer_delete_sync(&np->timer); 6512 6513 niu_netif_stop(np); 6514 6515 spin_lock_irqsave(&np->lock, flags); 6516 6517 niu_stop_hw(np); 6518 6519 spin_unlock_irqrestore(&np->lock, flags); 6520 6521 niu_reset_buffers(np); 6522 6523 netdev_lock(np->dev); 6524 spin_lock_irqsave(&np->lock, flags); 6525 6526 err = niu_init_hw(np); 6527 if (!err) { 6528 np->timer.expires = jiffies + HZ; 6529 add_timer(&np->timer); 6530 niu_netif_start(np); 6531 } 6532 6533 spin_unlock_irqrestore(&np->lock, flags); 6534 netdev_unlock(np->dev); 6535 } 6536 6537 static void niu_tx_timeout(struct net_device *dev, unsigned int txqueue) 6538 { 6539 struct niu *np = netdev_priv(dev); 6540 6541 dev_err(np->device, "%s: Transmit timed out, resetting\n", 6542 dev->name); 6543 6544 schedule_work(&np->reset_task); 6545 } 6546 6547 static void niu_set_txd(struct tx_ring_info *rp, int index, 6548 u64 mapping, u64 len, u64 mark, 6549 u64 n_frags) 6550 { 6551 __le64 *desc = &rp->descr[index]; 6552 6553 *desc = cpu_to_le64(mark | 6554 (n_frags << TX_DESC_NUM_PTR_SHIFT) | 6555 (len << TX_DESC_TR_LEN_SHIFT) | 6556 (mapping & TX_DESC_SAD)); 6557 } 6558 6559 static u64 niu_compute_tx_flags(struct sk_buff *skb, struct ethhdr *ehdr, 6560 u64 pad_bytes, u64 len) 6561 { 6562 u16 eth_proto, eth_proto_inner; 6563 u64 csum_bits, l3off, ihl, ret; 6564 u8 ip_proto; 6565 int ipv6; 6566 6567 eth_proto = be16_to_cpu(ehdr->h_proto); 6568 eth_proto_inner = eth_proto; 6569 if (eth_proto == ETH_P_8021Q) { 6570 struct vlan_ethhdr *vp = (struct vlan_ethhdr *) ehdr; 6571 __be16 val = vp->h_vlan_encapsulated_proto; 6572 6573 eth_proto_inner = be16_to_cpu(val); 6574 } 6575 6576 ipv6 = ihl = 0; 6577 switch (skb->protocol) { 6578 case cpu_to_be16(ETH_P_IP): 6579 ip_proto = ip_hdr(skb)->protocol; 6580 ihl = ip_hdr(skb)->ihl; 6581 break; 6582 case cpu_to_be16(ETH_P_IPV6): 6583 ip_proto = ipv6_hdr(skb)->nexthdr; 6584 ihl = (40 >> 2); 6585 ipv6 = 1; 6586 break; 6587 default: 6588 ip_proto = ihl = 0; 6589 break; 6590 } 6591 6592 csum_bits = TXHDR_CSUM_NONE; 6593 if (skb->ip_summed == CHECKSUM_PARTIAL) { 6594 u64 start, stuff; 6595 6596 csum_bits = (ip_proto == IPPROTO_TCP ? 6597 TXHDR_CSUM_TCP : 6598 (ip_proto == IPPROTO_UDP ? 6599 TXHDR_CSUM_UDP : TXHDR_CSUM_SCTP)); 6600 6601 start = skb_checksum_start_offset(skb) - 6602 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6603 stuff = start + skb->csum_offset; 6604 6605 csum_bits |= (start / 2) << TXHDR_L4START_SHIFT; 6606 csum_bits |= (stuff / 2) << TXHDR_L4STUFF_SHIFT; 6607 } 6608 6609 l3off = skb_network_offset(skb) - 6610 (pad_bytes + sizeof(struct tx_pkt_hdr)); 6611 6612 ret = (((pad_bytes / 2) << TXHDR_PAD_SHIFT) | 6613 (len << TXHDR_LEN_SHIFT) | 6614 ((l3off / 2) << TXHDR_L3START_SHIFT) | 6615 (ihl << TXHDR_IHL_SHIFT) | 6616 ((eth_proto_inner < ETH_P_802_3_MIN) ? TXHDR_LLC : 0) | 6617 ((eth_proto == ETH_P_8021Q) ? TXHDR_VLAN : 0) | 6618 (ipv6 ? TXHDR_IP_VER : 0) | 6619 csum_bits); 6620 6621 return ret; 6622 } 6623 6624 static netdev_tx_t niu_start_xmit(struct sk_buff *skb, 6625 struct net_device *dev) 6626 { 6627 struct niu *np = netdev_priv(dev); 6628 unsigned long align, headroom; 6629 struct netdev_queue *txq; 6630 struct tx_ring_info *rp; 6631 struct tx_pkt_hdr *tp; 6632 unsigned int len, nfg; 6633 struct ethhdr *ehdr; 6634 int prod, i, tlen; 6635 u64 mapping, mrk; 6636 6637 i = skb_get_queue_mapping(skb); 6638 rp = &np->tx_rings[i]; 6639 txq = netdev_get_tx_queue(dev, i); 6640 6641 if (niu_tx_avail(rp) <= (skb_shinfo(skb)->nr_frags + 1)) { 6642 netif_tx_stop_queue(txq); 6643 dev_err(np->device, "%s: BUG! Tx ring full when queue awake!\n", dev->name); 6644 rp->tx_errors++; 6645 return NETDEV_TX_BUSY; 6646 } 6647 6648 if (eth_skb_pad(skb)) 6649 goto out; 6650 6651 len = sizeof(struct tx_pkt_hdr) + 15; 6652 if (skb_headroom(skb) < len) { 6653 struct sk_buff *skb_new; 6654 6655 skb_new = skb_realloc_headroom(skb, len); 6656 if (!skb_new) 6657 goto out_drop; 6658 kfree_skb(skb); 6659 skb = skb_new; 6660 } else 6661 skb_orphan(skb); 6662 6663 align = ((unsigned long) skb->data & (16 - 1)); 6664 headroom = align + sizeof(struct tx_pkt_hdr); 6665 6666 ehdr = (struct ethhdr *) skb->data; 6667 tp = skb_push(skb, headroom); 6668 6669 len = skb->len - sizeof(struct tx_pkt_hdr); 6670 tp->flags = cpu_to_le64(niu_compute_tx_flags(skb, ehdr, align, len)); 6671 tp->resv = 0; 6672 6673 len = skb_headlen(skb); 6674 mapping = np->ops->map_single(np->device, skb->data, 6675 len, DMA_TO_DEVICE); 6676 if (np->ops->mapping_error(np->device, mapping)) 6677 goto out_drop; 6678 6679 prod = rp->prod; 6680 6681 rp->tx_buffs[prod].skb = skb; 6682 rp->tx_buffs[prod].mapping = mapping; 6683 6684 mrk = TX_DESC_SOP; 6685 if (++rp->mark_counter == rp->mark_freq) { 6686 rp->mark_counter = 0; 6687 mrk |= TX_DESC_MARK; 6688 rp->mark_pending++; 6689 } 6690 6691 tlen = len; 6692 nfg = skb_shinfo(skb)->nr_frags; 6693 while (tlen > 0) { 6694 tlen -= MAX_TX_DESC_LEN; 6695 nfg++; 6696 } 6697 6698 while (len > 0) { 6699 unsigned int this_len = len; 6700 6701 if (this_len > MAX_TX_DESC_LEN) 6702 this_len = MAX_TX_DESC_LEN; 6703 6704 niu_set_txd(rp, prod, mapping, this_len, mrk, nfg); 6705 mrk = nfg = 0; 6706 6707 prod = NEXT_TX(rp, prod); 6708 mapping += this_len; 6709 len -= this_len; 6710 } 6711 6712 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) { 6713 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 6714 6715 len = skb_frag_size(frag); 6716 mapping = np->ops->map_page(np->device, skb_frag_page(frag), 6717 skb_frag_off(frag), len, 6718 DMA_TO_DEVICE); 6719 if (np->ops->mapping_error(np->device, mapping)) 6720 goto out_unmap; 6721 6722 rp->tx_buffs[prod].skb = NULL; 6723 rp->tx_buffs[prod].mapping = mapping; 6724 6725 niu_set_txd(rp, prod, mapping, len, 0, 0); 6726 6727 prod = NEXT_TX(rp, prod); 6728 } 6729 6730 if (prod < rp->prod) 6731 rp->wrap_bit ^= TX_RING_KICK_WRAP; 6732 rp->prod = prod; 6733 6734 nw64(TX_RING_KICK(rp->tx_channel), rp->wrap_bit | (prod << 3)); 6735 6736 if (unlikely(niu_tx_avail(rp) <= (MAX_SKB_FRAGS + 1))) { 6737 netif_tx_stop_queue(txq); 6738 if (niu_tx_avail(rp) > NIU_TX_WAKEUP_THRESH(rp)) 6739 netif_tx_wake_queue(txq); 6740 } 6741 6742 out: 6743 return NETDEV_TX_OK; 6744 6745 out_unmap: 6746 while (i--) { 6747 const skb_frag_t *frag; 6748 6749 prod = PREVIOUS_TX(rp, prod); 6750 frag = &skb_shinfo(skb)->frags[i]; 6751 np->ops->unmap_page(np->device, rp->tx_buffs[prod].mapping, 6752 skb_frag_size(frag), DMA_TO_DEVICE); 6753 } 6754 6755 np->ops->unmap_single(np->device, rp->tx_buffs[rp->prod].mapping, 6756 skb_headlen(skb), DMA_TO_DEVICE); 6757 6758 out_drop: 6759 rp->tx_errors++; 6760 kfree_skb(skb); 6761 goto out; 6762 } 6763 6764 static int niu_change_mtu(struct net_device *dev, int new_mtu) 6765 { 6766 struct niu *np = netdev_priv(dev); 6767 int err, orig_jumbo, new_jumbo; 6768 6769 orig_jumbo = (dev->mtu > ETH_DATA_LEN); 6770 new_jumbo = (new_mtu > ETH_DATA_LEN); 6771 6772 WRITE_ONCE(dev->mtu, new_mtu); 6773 6774 if (!netif_running(dev) || 6775 (orig_jumbo == new_jumbo)) 6776 return 0; 6777 6778 niu_full_shutdown(np, dev); 6779 6780 niu_free_channels(np); 6781 6782 netdev_lock(dev); 6783 niu_enable_napi(np); 6784 netdev_unlock(dev); 6785 6786 err = niu_alloc_channels(np); 6787 if (err) 6788 return err; 6789 6790 spin_lock_irq(&np->lock); 6791 6792 err = niu_init_hw(np); 6793 if (!err) { 6794 timer_setup(&np->timer, niu_timer, 0); 6795 np->timer.expires = jiffies + HZ; 6796 6797 err = niu_enable_interrupts(np, 1); 6798 if (err) 6799 niu_stop_hw(np); 6800 } 6801 6802 spin_unlock_irq(&np->lock); 6803 6804 if (!err) { 6805 netif_tx_start_all_queues(dev); 6806 if (np->link_config.loopback_mode != LOOPBACK_DISABLED) 6807 netif_carrier_on(dev); 6808 6809 add_timer(&np->timer); 6810 } 6811 6812 return err; 6813 } 6814 6815 static void niu_get_drvinfo(struct net_device *dev, 6816 struct ethtool_drvinfo *info) 6817 { 6818 struct niu *np = netdev_priv(dev); 6819 struct niu_vpd *vpd = &np->vpd; 6820 6821 strscpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 6822 strscpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 6823 snprintf(info->fw_version, sizeof(info->fw_version), "%d.%d", 6824 vpd->fcode_major, vpd->fcode_minor); 6825 if (np->parent->plat_type != PLAT_TYPE_NIU) 6826 strscpy(info->bus_info, pci_name(np->pdev), 6827 sizeof(info->bus_info)); 6828 } 6829 6830 static int niu_get_link_ksettings(struct net_device *dev, 6831 struct ethtool_link_ksettings *cmd) 6832 { 6833 struct niu *np = netdev_priv(dev); 6834 struct niu_link_config *lp; 6835 6836 lp = &np->link_config; 6837 6838 memset(cmd, 0, sizeof(*cmd)); 6839 cmd->base.phy_address = np->phy_addr; 6840 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 6841 lp->supported); 6842 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 6843 lp->active_advertising); 6844 cmd->base.autoneg = lp->active_autoneg; 6845 cmd->base.speed = lp->active_speed; 6846 cmd->base.duplex = lp->active_duplex; 6847 cmd->base.port = (np->flags & NIU_FLAGS_FIBER) ? PORT_FIBRE : PORT_TP; 6848 6849 return 0; 6850 } 6851 6852 static int niu_set_link_ksettings(struct net_device *dev, 6853 const struct ethtool_link_ksettings *cmd) 6854 { 6855 struct niu *np = netdev_priv(dev); 6856 struct niu_link_config *lp = &np->link_config; 6857 6858 ethtool_convert_link_mode_to_legacy_u32(&lp->advertising, 6859 cmd->link_modes.advertising); 6860 lp->speed = cmd->base.speed; 6861 lp->duplex = cmd->base.duplex; 6862 lp->autoneg = cmd->base.autoneg; 6863 return niu_init_link(np); 6864 } 6865 6866 static u32 niu_get_msglevel(struct net_device *dev) 6867 { 6868 struct niu *np = netdev_priv(dev); 6869 return np->msg_enable; 6870 } 6871 6872 static void niu_set_msglevel(struct net_device *dev, u32 value) 6873 { 6874 struct niu *np = netdev_priv(dev); 6875 np->msg_enable = value; 6876 } 6877 6878 static int niu_nway_reset(struct net_device *dev) 6879 { 6880 struct niu *np = netdev_priv(dev); 6881 6882 if (np->link_config.autoneg) 6883 return niu_init_link(np); 6884 6885 return 0; 6886 } 6887 6888 static int niu_get_eeprom_len(struct net_device *dev) 6889 { 6890 struct niu *np = netdev_priv(dev); 6891 6892 return np->eeprom_len; 6893 } 6894 6895 static int niu_get_eeprom(struct net_device *dev, 6896 struct ethtool_eeprom *eeprom, u8 *data) 6897 { 6898 struct niu *np = netdev_priv(dev); 6899 u32 offset, len, val; 6900 6901 offset = eeprom->offset; 6902 len = eeprom->len; 6903 6904 if (offset + len < offset) 6905 return -EINVAL; 6906 if (offset >= np->eeprom_len) 6907 return -EINVAL; 6908 if (offset + len > np->eeprom_len) 6909 len = eeprom->len = np->eeprom_len - offset; 6910 6911 if (offset & 3) { 6912 u32 b_offset, b_count; 6913 6914 b_offset = offset & 3; 6915 b_count = 4 - b_offset; 6916 if (b_count > len) 6917 b_count = len; 6918 6919 val = nr64(ESPC_NCR((offset - b_offset) / 4)); 6920 memcpy(data, ((char *)&val) + b_offset, b_count); 6921 data += b_count; 6922 len -= b_count; 6923 offset += b_count; 6924 } 6925 while (len >= 4) { 6926 val = nr64(ESPC_NCR(offset / 4)); 6927 memcpy(data, &val, 4); 6928 data += 4; 6929 len -= 4; 6930 offset += 4; 6931 } 6932 if (len) { 6933 val = nr64(ESPC_NCR(offset / 4)); 6934 memcpy(data, &val, len); 6935 } 6936 return 0; 6937 } 6938 6939 static void niu_ethflow_to_l3proto(int flow_type, u8 *pid) 6940 { 6941 switch (flow_type) { 6942 case TCP_V4_FLOW: 6943 case TCP_V6_FLOW: 6944 *pid = IPPROTO_TCP; 6945 break; 6946 case UDP_V4_FLOW: 6947 case UDP_V6_FLOW: 6948 *pid = IPPROTO_UDP; 6949 break; 6950 case SCTP_V4_FLOW: 6951 case SCTP_V6_FLOW: 6952 *pid = IPPROTO_SCTP; 6953 break; 6954 case AH_V4_FLOW: 6955 case AH_V6_FLOW: 6956 *pid = IPPROTO_AH; 6957 break; 6958 case ESP_V4_FLOW: 6959 case ESP_V6_FLOW: 6960 *pid = IPPROTO_ESP; 6961 break; 6962 default: 6963 *pid = 0; 6964 break; 6965 } 6966 } 6967 6968 static int niu_class_to_ethflow(u64 class, int *flow_type) 6969 { 6970 switch (class) { 6971 case CLASS_CODE_TCP_IPV4: 6972 *flow_type = TCP_V4_FLOW; 6973 break; 6974 case CLASS_CODE_UDP_IPV4: 6975 *flow_type = UDP_V4_FLOW; 6976 break; 6977 case CLASS_CODE_AH_ESP_IPV4: 6978 *flow_type = AH_V4_FLOW; 6979 break; 6980 case CLASS_CODE_SCTP_IPV4: 6981 *flow_type = SCTP_V4_FLOW; 6982 break; 6983 case CLASS_CODE_TCP_IPV6: 6984 *flow_type = TCP_V6_FLOW; 6985 break; 6986 case CLASS_CODE_UDP_IPV6: 6987 *flow_type = UDP_V6_FLOW; 6988 break; 6989 case CLASS_CODE_AH_ESP_IPV6: 6990 *flow_type = AH_V6_FLOW; 6991 break; 6992 case CLASS_CODE_SCTP_IPV6: 6993 *flow_type = SCTP_V6_FLOW; 6994 break; 6995 case CLASS_CODE_USER_PROG1: 6996 case CLASS_CODE_USER_PROG2: 6997 case CLASS_CODE_USER_PROG3: 6998 case CLASS_CODE_USER_PROG4: 6999 *flow_type = IP_USER_FLOW; 7000 break; 7001 default: 7002 return -EINVAL; 7003 } 7004 7005 return 0; 7006 } 7007 7008 static int niu_ethflow_to_class(int flow_type, u64 *class) 7009 { 7010 switch (flow_type) { 7011 case TCP_V4_FLOW: 7012 *class = CLASS_CODE_TCP_IPV4; 7013 break; 7014 case UDP_V4_FLOW: 7015 *class = CLASS_CODE_UDP_IPV4; 7016 break; 7017 case AH_ESP_V4_FLOW: 7018 case AH_V4_FLOW: 7019 case ESP_V4_FLOW: 7020 *class = CLASS_CODE_AH_ESP_IPV4; 7021 break; 7022 case SCTP_V4_FLOW: 7023 *class = CLASS_CODE_SCTP_IPV4; 7024 break; 7025 case TCP_V6_FLOW: 7026 *class = CLASS_CODE_TCP_IPV6; 7027 break; 7028 case UDP_V6_FLOW: 7029 *class = CLASS_CODE_UDP_IPV6; 7030 break; 7031 case AH_ESP_V6_FLOW: 7032 case AH_V6_FLOW: 7033 case ESP_V6_FLOW: 7034 *class = CLASS_CODE_AH_ESP_IPV6; 7035 break; 7036 case SCTP_V6_FLOW: 7037 *class = CLASS_CODE_SCTP_IPV6; 7038 break; 7039 default: 7040 return 0; 7041 } 7042 7043 return 1; 7044 } 7045 7046 static u64 niu_flowkey_to_ethflow(u64 flow_key) 7047 { 7048 u64 ethflow = 0; 7049 7050 if (flow_key & FLOW_KEY_L2DA) 7051 ethflow |= RXH_L2DA; 7052 if (flow_key & FLOW_KEY_VLAN) 7053 ethflow |= RXH_VLAN; 7054 if (flow_key & FLOW_KEY_IPSA) 7055 ethflow |= RXH_IP_SRC; 7056 if (flow_key & FLOW_KEY_IPDA) 7057 ethflow |= RXH_IP_DST; 7058 if (flow_key & FLOW_KEY_PROTO) 7059 ethflow |= RXH_L3_PROTO; 7060 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT)) 7061 ethflow |= RXH_L4_B_0_1; 7062 if (flow_key & (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT)) 7063 ethflow |= RXH_L4_B_2_3; 7064 7065 return ethflow; 7066 7067 } 7068 7069 static int niu_ethflow_to_flowkey(u64 ethflow, u64 *flow_key) 7070 { 7071 u64 key = 0; 7072 7073 if (ethflow & RXH_L2DA) 7074 key |= FLOW_KEY_L2DA; 7075 if (ethflow & RXH_VLAN) 7076 key |= FLOW_KEY_VLAN; 7077 if (ethflow & RXH_IP_SRC) 7078 key |= FLOW_KEY_IPSA; 7079 if (ethflow & RXH_IP_DST) 7080 key |= FLOW_KEY_IPDA; 7081 if (ethflow & RXH_L3_PROTO) 7082 key |= FLOW_KEY_PROTO; 7083 if (ethflow & RXH_L4_B_0_1) 7084 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_0_SHIFT); 7085 if (ethflow & RXH_L4_B_2_3) 7086 key |= (FLOW_KEY_L4_BYTE12 << FLOW_KEY_L4_1_SHIFT); 7087 7088 *flow_key = key; 7089 7090 return 1; 7091 7092 } 7093 7094 static int niu_get_rxfh_fields(struct net_device *dev, 7095 struct ethtool_rxfh_fields *nfc) 7096 { 7097 struct niu *np = netdev_priv(dev); 7098 u64 class; 7099 7100 nfc->data = 0; 7101 7102 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7103 return -EINVAL; 7104 7105 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7106 TCAM_KEY_DISC) 7107 nfc->data = RXH_DISCARD; 7108 else 7109 nfc->data = niu_flowkey_to_ethflow(np->parent->flow_key[class - 7110 CLASS_CODE_USER_PROG1]); 7111 return 0; 7112 } 7113 7114 static void niu_get_ip4fs_from_tcam_key(struct niu_tcam_entry *tp, 7115 struct ethtool_rx_flow_spec *fsp) 7116 { 7117 u32 tmp; 7118 u16 prt; 7119 7120 tmp = (tp->key[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7121 fsp->h_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7122 7123 tmp = (tp->key[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7124 fsp->h_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7125 7126 tmp = (tp->key_mask[3] & TCAM_V4KEY3_SADDR) >> TCAM_V4KEY3_SADDR_SHIFT; 7127 fsp->m_u.tcp_ip4_spec.ip4src = cpu_to_be32(tmp); 7128 7129 tmp = (tp->key_mask[3] & TCAM_V4KEY3_DADDR) >> TCAM_V4KEY3_DADDR_SHIFT; 7130 fsp->m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(tmp); 7131 7132 fsp->h_u.tcp_ip4_spec.tos = (tp->key[2] & TCAM_V4KEY2_TOS) >> 7133 TCAM_V4KEY2_TOS_SHIFT; 7134 fsp->m_u.tcp_ip4_spec.tos = (tp->key_mask[2] & TCAM_V4KEY2_TOS) >> 7135 TCAM_V4KEY2_TOS_SHIFT; 7136 7137 switch (fsp->flow_type) { 7138 case TCP_V4_FLOW: 7139 case UDP_V4_FLOW: 7140 case SCTP_V4_FLOW: 7141 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7142 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7143 fsp->h_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7144 7145 prt = ((tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7146 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7147 fsp->h_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7148 7149 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7150 TCAM_V4KEY2_PORT_SPI_SHIFT) >> 16; 7151 fsp->m_u.tcp_ip4_spec.psrc = cpu_to_be16(prt); 7152 7153 prt = ((tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7154 TCAM_V4KEY2_PORT_SPI_SHIFT) & 0xffff; 7155 fsp->m_u.tcp_ip4_spec.pdst = cpu_to_be16(prt); 7156 break; 7157 case AH_V4_FLOW: 7158 case ESP_V4_FLOW: 7159 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7160 TCAM_V4KEY2_PORT_SPI_SHIFT; 7161 fsp->h_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7162 7163 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7164 TCAM_V4KEY2_PORT_SPI_SHIFT; 7165 fsp->m_u.ah_ip4_spec.spi = cpu_to_be32(tmp); 7166 break; 7167 case IP_USER_FLOW: 7168 tmp = (tp->key[2] & TCAM_V4KEY2_PORT_SPI) >> 7169 TCAM_V4KEY2_PORT_SPI_SHIFT; 7170 fsp->h_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7171 7172 tmp = (tp->key_mask[2] & TCAM_V4KEY2_PORT_SPI) >> 7173 TCAM_V4KEY2_PORT_SPI_SHIFT; 7174 fsp->m_u.usr_ip4_spec.l4_4_bytes = cpu_to_be32(tmp); 7175 7176 fsp->h_u.usr_ip4_spec.proto = 7177 (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7178 TCAM_V4KEY2_PROTO_SHIFT; 7179 fsp->m_u.usr_ip4_spec.proto = 7180 (tp->key_mask[2] & TCAM_V4KEY2_PROTO) >> 7181 TCAM_V4KEY2_PROTO_SHIFT; 7182 7183 fsp->h_u.usr_ip4_spec.ip_ver = ETH_RX_NFC_IP4; 7184 break; 7185 default: 7186 break; 7187 } 7188 } 7189 7190 static int niu_get_ethtool_tcam_entry(struct niu *np, 7191 struct ethtool_rxnfc *nfc) 7192 { 7193 struct niu_parent *parent = np->parent; 7194 struct niu_tcam_entry *tp; 7195 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7196 u16 idx; 7197 u64 class; 7198 int ret = 0; 7199 7200 idx = tcam_get_index(np, (u16)nfc->fs.location); 7201 7202 tp = &parent->tcam[idx]; 7203 if (!tp->valid) { 7204 netdev_info(np->dev, "niu%d: entry [%d] invalid for idx[%d]\n", 7205 parent->index, (u16)nfc->fs.location, idx); 7206 return -EINVAL; 7207 } 7208 7209 /* fill the flow spec entry */ 7210 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7211 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7212 ret = niu_class_to_ethflow(class, &fsp->flow_type); 7213 if (ret < 0) { 7214 netdev_info(np->dev, "niu%d: niu_class_to_ethflow failed\n", 7215 parent->index); 7216 goto out; 7217 } 7218 7219 if (fsp->flow_type == AH_V4_FLOW || fsp->flow_type == AH_V6_FLOW) { 7220 u32 proto = (tp->key[2] & TCAM_V4KEY2_PROTO) >> 7221 TCAM_V4KEY2_PROTO_SHIFT; 7222 if (proto == IPPROTO_ESP) { 7223 if (fsp->flow_type == AH_V4_FLOW) 7224 fsp->flow_type = ESP_V4_FLOW; 7225 else 7226 fsp->flow_type = ESP_V6_FLOW; 7227 } 7228 } 7229 7230 switch (fsp->flow_type) { 7231 case TCP_V4_FLOW: 7232 case UDP_V4_FLOW: 7233 case SCTP_V4_FLOW: 7234 case AH_V4_FLOW: 7235 case ESP_V4_FLOW: 7236 niu_get_ip4fs_from_tcam_key(tp, fsp); 7237 break; 7238 case TCP_V6_FLOW: 7239 case UDP_V6_FLOW: 7240 case SCTP_V6_FLOW: 7241 case AH_V6_FLOW: 7242 case ESP_V6_FLOW: 7243 /* Not yet implemented */ 7244 ret = -EINVAL; 7245 break; 7246 case IP_USER_FLOW: 7247 niu_get_ip4fs_from_tcam_key(tp, fsp); 7248 break; 7249 default: 7250 ret = -EINVAL; 7251 break; 7252 } 7253 7254 if (ret < 0) 7255 goto out; 7256 7257 if (tp->assoc_data & TCAM_ASSOCDATA_DISC) 7258 fsp->ring_cookie = RX_CLS_FLOW_DISC; 7259 else 7260 fsp->ring_cookie = (tp->assoc_data & TCAM_ASSOCDATA_OFFSET) >> 7261 TCAM_ASSOCDATA_OFFSET_SHIFT; 7262 7263 /* put the tcam size here */ 7264 nfc->data = tcam_get_size(np); 7265 out: 7266 return ret; 7267 } 7268 7269 static int niu_get_ethtool_tcam_all(struct niu *np, 7270 struct ethtool_rxnfc *nfc, 7271 u32 *rule_locs) 7272 { 7273 struct niu_parent *parent = np->parent; 7274 struct niu_tcam_entry *tp; 7275 int i, idx, cnt; 7276 unsigned long flags; 7277 int ret = 0; 7278 7279 /* put the tcam size here */ 7280 nfc->data = tcam_get_size(np); 7281 7282 niu_lock_parent(np, flags); 7283 for (cnt = 0, i = 0; i < nfc->data; i++) { 7284 idx = tcam_get_index(np, i); 7285 tp = &parent->tcam[idx]; 7286 if (!tp->valid) 7287 continue; 7288 if (cnt == nfc->rule_cnt) { 7289 ret = -EMSGSIZE; 7290 break; 7291 } 7292 rule_locs[cnt] = i; 7293 cnt++; 7294 } 7295 niu_unlock_parent(np, flags); 7296 7297 nfc->rule_cnt = cnt; 7298 7299 return ret; 7300 } 7301 7302 static u32 niu_get_rx_ring_count(struct net_device *dev) 7303 { 7304 struct niu *np = netdev_priv(dev); 7305 7306 return np->num_rx_rings; 7307 } 7308 7309 static int niu_get_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd, 7310 u32 *rule_locs) 7311 { 7312 struct niu *np = netdev_priv(dev); 7313 int ret = 0; 7314 7315 switch (cmd->cmd) { 7316 case ETHTOOL_GRXCLSRLCNT: 7317 cmd->rule_cnt = tcam_get_valid_entry_cnt(np); 7318 break; 7319 case ETHTOOL_GRXCLSRULE: 7320 ret = niu_get_ethtool_tcam_entry(np, cmd); 7321 break; 7322 case ETHTOOL_GRXCLSRLALL: 7323 ret = niu_get_ethtool_tcam_all(np, cmd, rule_locs); 7324 break; 7325 default: 7326 ret = -EINVAL; 7327 break; 7328 } 7329 7330 return ret; 7331 } 7332 7333 static int niu_set_rxfh_fields(struct net_device *dev, 7334 const struct ethtool_rxfh_fields *nfc, 7335 struct netlink_ext_ack *extack) 7336 { 7337 struct niu *np = netdev_priv(dev); 7338 u64 class; 7339 u64 flow_key = 0; 7340 unsigned long flags; 7341 7342 if (!niu_ethflow_to_class(nfc->flow_type, &class)) 7343 return -EINVAL; 7344 7345 if (class < CLASS_CODE_USER_PROG1 || 7346 class > CLASS_CODE_SCTP_IPV6) 7347 return -EINVAL; 7348 7349 if (nfc->data & RXH_DISCARD) { 7350 niu_lock_parent(np, flags); 7351 flow_key = np->parent->tcam_key[class - 7352 CLASS_CODE_USER_PROG1]; 7353 flow_key |= TCAM_KEY_DISC; 7354 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7355 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7356 niu_unlock_parent(np, flags); 7357 return 0; 7358 } else { 7359 /* Discard was set before, but is not set now */ 7360 if (np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] & 7361 TCAM_KEY_DISC) { 7362 niu_lock_parent(np, flags); 7363 flow_key = np->parent->tcam_key[class - 7364 CLASS_CODE_USER_PROG1]; 7365 flow_key &= ~TCAM_KEY_DISC; 7366 nw64(TCAM_KEY(class - CLASS_CODE_USER_PROG1), 7367 flow_key); 7368 np->parent->tcam_key[class - CLASS_CODE_USER_PROG1] = 7369 flow_key; 7370 niu_unlock_parent(np, flags); 7371 } 7372 } 7373 7374 if (!niu_ethflow_to_flowkey(nfc->data, &flow_key)) 7375 return -EINVAL; 7376 7377 niu_lock_parent(np, flags); 7378 nw64(FLOW_KEY(class - CLASS_CODE_USER_PROG1), flow_key); 7379 np->parent->flow_key[class - CLASS_CODE_USER_PROG1] = flow_key; 7380 niu_unlock_parent(np, flags); 7381 7382 return 0; 7383 } 7384 7385 static void niu_get_tcamkey_from_ip4fs(struct ethtool_rx_flow_spec *fsp, 7386 struct niu_tcam_entry *tp, 7387 int l2_rdc_tab, u64 class) 7388 { 7389 u8 pid = 0; 7390 u32 sip, dip, sipm, dipm, spi, spim; 7391 u16 sport, dport, spm, dpm; 7392 7393 sip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4src); 7394 sipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4src); 7395 dip = be32_to_cpu(fsp->h_u.tcp_ip4_spec.ip4dst); 7396 dipm = be32_to_cpu(fsp->m_u.tcp_ip4_spec.ip4dst); 7397 7398 tp->key[0] = class << TCAM_V4KEY0_CLASS_CODE_SHIFT; 7399 tp->key_mask[0] = TCAM_V4KEY0_CLASS_CODE; 7400 tp->key[1] = (u64)l2_rdc_tab << TCAM_V4KEY1_L2RDCNUM_SHIFT; 7401 tp->key_mask[1] = TCAM_V4KEY1_L2RDCNUM; 7402 7403 tp->key[3] = (u64)sip << TCAM_V4KEY3_SADDR_SHIFT; 7404 tp->key[3] |= dip; 7405 7406 tp->key_mask[3] = (u64)sipm << TCAM_V4KEY3_SADDR_SHIFT; 7407 tp->key_mask[3] |= dipm; 7408 7409 tp->key[2] |= ((u64)fsp->h_u.tcp_ip4_spec.tos << 7410 TCAM_V4KEY2_TOS_SHIFT); 7411 tp->key_mask[2] |= ((u64)fsp->m_u.tcp_ip4_spec.tos << 7412 TCAM_V4KEY2_TOS_SHIFT); 7413 switch (fsp->flow_type) { 7414 case TCP_V4_FLOW: 7415 case UDP_V4_FLOW: 7416 case SCTP_V4_FLOW: 7417 sport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.psrc); 7418 spm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.psrc); 7419 dport = be16_to_cpu(fsp->h_u.tcp_ip4_spec.pdst); 7420 dpm = be16_to_cpu(fsp->m_u.tcp_ip4_spec.pdst); 7421 7422 tp->key[2] |= (((u64)sport << 16) | dport); 7423 tp->key_mask[2] |= (((u64)spm << 16) | dpm); 7424 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7425 break; 7426 case AH_V4_FLOW: 7427 case ESP_V4_FLOW: 7428 spi = be32_to_cpu(fsp->h_u.ah_ip4_spec.spi); 7429 spim = be32_to_cpu(fsp->m_u.ah_ip4_spec.spi); 7430 7431 tp->key[2] |= spi; 7432 tp->key_mask[2] |= spim; 7433 niu_ethflow_to_l3proto(fsp->flow_type, &pid); 7434 break; 7435 case IP_USER_FLOW: 7436 spi = be32_to_cpu(fsp->h_u.usr_ip4_spec.l4_4_bytes); 7437 spim = be32_to_cpu(fsp->m_u.usr_ip4_spec.l4_4_bytes); 7438 7439 tp->key[2] |= spi; 7440 tp->key_mask[2] |= spim; 7441 pid = fsp->h_u.usr_ip4_spec.proto; 7442 break; 7443 default: 7444 break; 7445 } 7446 7447 tp->key[2] |= ((u64)pid << TCAM_V4KEY2_PROTO_SHIFT); 7448 if (pid) { 7449 tp->key_mask[2] |= TCAM_V4KEY2_PROTO; 7450 } 7451 } 7452 7453 static int niu_add_ethtool_tcam_entry(struct niu *np, 7454 struct ethtool_rxnfc *nfc) 7455 { 7456 struct niu_parent *parent = np->parent; 7457 struct niu_tcam_entry *tp; 7458 struct ethtool_rx_flow_spec *fsp = &nfc->fs; 7459 struct niu_rdc_tables *rdc_table = &parent->rdc_group_cfg[np->port]; 7460 int l2_rdc_table = rdc_table->first_table_num; 7461 u16 idx; 7462 u64 class; 7463 unsigned long flags; 7464 int err, ret; 7465 7466 ret = 0; 7467 7468 idx = nfc->fs.location; 7469 if (idx >= tcam_get_size(np)) 7470 return -EINVAL; 7471 7472 if (fsp->flow_type == IP_USER_FLOW) { 7473 int i; 7474 int add_usr_cls = 0; 7475 struct ethtool_usrip4_spec *uspec = &fsp->h_u.usr_ip4_spec; 7476 struct ethtool_usrip4_spec *umask = &fsp->m_u.usr_ip4_spec; 7477 7478 if (uspec->ip_ver != ETH_RX_NFC_IP4) 7479 return -EINVAL; 7480 7481 niu_lock_parent(np, flags); 7482 7483 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7484 if (parent->l3_cls[i]) { 7485 if (uspec->proto == parent->l3_cls_pid[i]) { 7486 class = parent->l3_cls[i]; 7487 parent->l3_cls_refcnt[i]++; 7488 add_usr_cls = 1; 7489 break; 7490 } 7491 } else { 7492 /* Program new user IP class */ 7493 switch (i) { 7494 case 0: 7495 class = CLASS_CODE_USER_PROG1; 7496 break; 7497 case 1: 7498 class = CLASS_CODE_USER_PROG2; 7499 break; 7500 case 2: 7501 class = CLASS_CODE_USER_PROG3; 7502 break; 7503 case 3: 7504 class = CLASS_CODE_USER_PROG4; 7505 break; 7506 default: 7507 class = CLASS_CODE_UNRECOG; 7508 break; 7509 } 7510 ret = tcam_user_ip_class_set(np, class, 0, 7511 uspec->proto, 7512 uspec->tos, 7513 umask->tos); 7514 if (ret) 7515 goto out; 7516 7517 ret = tcam_user_ip_class_enable(np, class, 1); 7518 if (ret) 7519 goto out; 7520 parent->l3_cls[i] = class; 7521 parent->l3_cls_pid[i] = uspec->proto; 7522 parent->l3_cls_refcnt[i]++; 7523 add_usr_cls = 1; 7524 break; 7525 } 7526 } 7527 if (!add_usr_cls) { 7528 netdev_info(np->dev, "niu%d: %s(): Could not find/insert class for pid %d\n", 7529 parent->index, __func__, uspec->proto); 7530 ret = -EINVAL; 7531 goto out; 7532 } 7533 niu_unlock_parent(np, flags); 7534 } else { 7535 if (!niu_ethflow_to_class(fsp->flow_type, &class)) { 7536 return -EINVAL; 7537 } 7538 } 7539 7540 niu_lock_parent(np, flags); 7541 7542 idx = tcam_get_index(np, idx); 7543 tp = &parent->tcam[idx]; 7544 7545 memset(tp, 0, sizeof(*tp)); 7546 7547 /* fill in the tcam key and mask */ 7548 switch (fsp->flow_type) { 7549 case TCP_V4_FLOW: 7550 case UDP_V4_FLOW: 7551 case SCTP_V4_FLOW: 7552 case AH_V4_FLOW: 7553 case ESP_V4_FLOW: 7554 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7555 break; 7556 case TCP_V6_FLOW: 7557 case UDP_V6_FLOW: 7558 case SCTP_V6_FLOW: 7559 case AH_V6_FLOW: 7560 case ESP_V6_FLOW: 7561 /* Not yet implemented */ 7562 netdev_info(np->dev, "niu%d: In %s(): flow %d for IPv6 not implemented\n", 7563 parent->index, __func__, fsp->flow_type); 7564 ret = -EINVAL; 7565 goto out; 7566 case IP_USER_FLOW: 7567 niu_get_tcamkey_from_ip4fs(fsp, tp, l2_rdc_table, class); 7568 break; 7569 default: 7570 netdev_info(np->dev, "niu%d: In %s(): Unknown flow type %d\n", 7571 parent->index, __func__, fsp->flow_type); 7572 ret = -EINVAL; 7573 goto out; 7574 } 7575 7576 /* fill in the assoc data */ 7577 if (fsp->ring_cookie == RX_CLS_FLOW_DISC) { 7578 tp->assoc_data = TCAM_ASSOCDATA_DISC; 7579 } else { 7580 if (fsp->ring_cookie >= np->num_rx_rings) { 7581 netdev_info(np->dev, "niu%d: In %s(): Invalid RX ring %lld\n", 7582 parent->index, __func__, 7583 (long long)fsp->ring_cookie); 7584 ret = -EINVAL; 7585 goto out; 7586 } 7587 tp->assoc_data = (TCAM_ASSOCDATA_TRES_USE_OFFSET | 7588 (fsp->ring_cookie << 7589 TCAM_ASSOCDATA_OFFSET_SHIFT)); 7590 } 7591 7592 err = tcam_write(np, idx, tp->key, tp->key_mask); 7593 if (err) { 7594 ret = -EINVAL; 7595 goto out; 7596 } 7597 err = tcam_assoc_write(np, idx, tp->assoc_data); 7598 if (err) { 7599 ret = -EINVAL; 7600 goto out; 7601 } 7602 7603 /* validate the entry */ 7604 tp->valid = 1; 7605 np->clas.tcam_valid_entries++; 7606 out: 7607 niu_unlock_parent(np, flags); 7608 7609 return ret; 7610 } 7611 7612 static int niu_del_ethtool_tcam_entry(struct niu *np, u32 loc) 7613 { 7614 struct niu_parent *parent = np->parent; 7615 struct niu_tcam_entry *tp; 7616 u16 idx; 7617 unsigned long flags; 7618 u64 class; 7619 int ret = 0; 7620 7621 if (loc >= tcam_get_size(np)) 7622 return -EINVAL; 7623 7624 niu_lock_parent(np, flags); 7625 7626 idx = tcam_get_index(np, loc); 7627 tp = &parent->tcam[idx]; 7628 7629 /* if the entry is of a user defined class, then update*/ 7630 class = (tp->key[0] & TCAM_V4KEY0_CLASS_CODE) >> 7631 TCAM_V4KEY0_CLASS_CODE_SHIFT; 7632 7633 if (class >= CLASS_CODE_USER_PROG1 && class <= CLASS_CODE_USER_PROG4) { 7634 int i; 7635 for (i = 0; i < NIU_L3_PROG_CLS; i++) { 7636 if (parent->l3_cls[i] == class) { 7637 parent->l3_cls_refcnt[i]--; 7638 if (!parent->l3_cls_refcnt[i]) { 7639 /* disable class */ 7640 ret = tcam_user_ip_class_enable(np, 7641 class, 7642 0); 7643 if (ret) 7644 goto out; 7645 parent->l3_cls[i] = 0; 7646 parent->l3_cls_pid[i] = 0; 7647 } 7648 break; 7649 } 7650 } 7651 if (i == NIU_L3_PROG_CLS) { 7652 netdev_info(np->dev, "niu%d: In %s(): Usr class 0x%llx not found\n", 7653 parent->index, __func__, 7654 (unsigned long long)class); 7655 ret = -EINVAL; 7656 goto out; 7657 } 7658 } 7659 7660 ret = tcam_flush(np, idx); 7661 if (ret) 7662 goto out; 7663 7664 /* invalidate the entry */ 7665 tp->valid = 0; 7666 np->clas.tcam_valid_entries--; 7667 out: 7668 niu_unlock_parent(np, flags); 7669 7670 return ret; 7671 } 7672 7673 static int niu_set_nfc(struct net_device *dev, struct ethtool_rxnfc *cmd) 7674 { 7675 struct niu *np = netdev_priv(dev); 7676 int ret = 0; 7677 7678 switch (cmd->cmd) { 7679 case ETHTOOL_SRXCLSRLINS: 7680 ret = niu_add_ethtool_tcam_entry(np, cmd); 7681 break; 7682 case ETHTOOL_SRXCLSRLDEL: 7683 ret = niu_del_ethtool_tcam_entry(np, cmd->fs.location); 7684 break; 7685 default: 7686 ret = -EINVAL; 7687 break; 7688 } 7689 7690 return ret; 7691 } 7692 7693 static const struct { 7694 const char string[ETH_GSTRING_LEN]; 7695 } niu_xmac_stat_keys[] = { 7696 { "tx_frames" }, 7697 { "tx_bytes" }, 7698 { "tx_fifo_errors" }, 7699 { "tx_overflow_errors" }, 7700 { "tx_max_pkt_size_errors" }, 7701 { "tx_underflow_errors" }, 7702 { "rx_local_faults" }, 7703 { "rx_remote_faults" }, 7704 { "rx_link_faults" }, 7705 { "rx_align_errors" }, 7706 { "rx_frags" }, 7707 { "rx_mcasts" }, 7708 { "rx_bcasts" }, 7709 { "rx_hist_cnt1" }, 7710 { "rx_hist_cnt2" }, 7711 { "rx_hist_cnt3" }, 7712 { "rx_hist_cnt4" }, 7713 { "rx_hist_cnt5" }, 7714 { "rx_hist_cnt6" }, 7715 { "rx_hist_cnt7" }, 7716 { "rx_octets" }, 7717 { "rx_code_violations" }, 7718 { "rx_len_errors" }, 7719 { "rx_crc_errors" }, 7720 { "rx_underflows" }, 7721 { "rx_overflows" }, 7722 { "pause_off_state" }, 7723 { "pause_on_state" }, 7724 { "pause_received" }, 7725 }; 7726 7727 #define NUM_XMAC_STAT_KEYS ARRAY_SIZE(niu_xmac_stat_keys) 7728 7729 static const struct { 7730 const char string[ETH_GSTRING_LEN]; 7731 } niu_bmac_stat_keys[] = { 7732 { "tx_underflow_errors" }, 7733 { "tx_max_pkt_size_errors" }, 7734 { "tx_bytes" }, 7735 { "tx_frames" }, 7736 { "rx_overflows" }, 7737 { "rx_frames" }, 7738 { "rx_align_errors" }, 7739 { "rx_crc_errors" }, 7740 { "rx_len_errors" }, 7741 { "pause_off_state" }, 7742 { "pause_on_state" }, 7743 { "pause_received" }, 7744 }; 7745 7746 #define NUM_BMAC_STAT_KEYS ARRAY_SIZE(niu_bmac_stat_keys) 7747 7748 static const struct { 7749 const char string[ETH_GSTRING_LEN]; 7750 } niu_rxchan_stat_keys[] = { 7751 { "rx_channel" }, 7752 { "rx_packets" }, 7753 { "rx_bytes" }, 7754 { "rx_dropped" }, 7755 { "rx_errors" }, 7756 }; 7757 7758 #define NUM_RXCHAN_STAT_KEYS ARRAY_SIZE(niu_rxchan_stat_keys) 7759 7760 static const struct { 7761 const char string[ETH_GSTRING_LEN]; 7762 } niu_txchan_stat_keys[] = { 7763 { "tx_channel" }, 7764 { "tx_packets" }, 7765 { "tx_bytes" }, 7766 { "tx_errors" }, 7767 }; 7768 7769 #define NUM_TXCHAN_STAT_KEYS ARRAY_SIZE(niu_txchan_stat_keys) 7770 7771 static void niu_get_strings(struct net_device *dev, u32 stringset, u8 *data) 7772 { 7773 struct niu *np = netdev_priv(dev); 7774 int i; 7775 7776 if (stringset != ETH_SS_STATS) 7777 return; 7778 7779 if (np->flags & NIU_FLAGS_XMAC) { 7780 memcpy(data, niu_xmac_stat_keys, 7781 sizeof(niu_xmac_stat_keys)); 7782 data += sizeof(niu_xmac_stat_keys); 7783 } else { 7784 memcpy(data, niu_bmac_stat_keys, 7785 sizeof(niu_bmac_stat_keys)); 7786 data += sizeof(niu_bmac_stat_keys); 7787 } 7788 for (i = 0; i < np->num_rx_rings; i++) { 7789 memcpy(data, niu_rxchan_stat_keys, 7790 sizeof(niu_rxchan_stat_keys)); 7791 data += sizeof(niu_rxchan_stat_keys); 7792 } 7793 for (i = 0; i < np->num_tx_rings; i++) { 7794 memcpy(data, niu_txchan_stat_keys, 7795 sizeof(niu_txchan_stat_keys)); 7796 data += sizeof(niu_txchan_stat_keys); 7797 } 7798 } 7799 7800 static int niu_get_sset_count(struct net_device *dev, int stringset) 7801 { 7802 struct niu *np = netdev_priv(dev); 7803 7804 if (stringset != ETH_SS_STATS) 7805 return -EINVAL; 7806 7807 return (np->flags & NIU_FLAGS_XMAC ? 7808 NUM_XMAC_STAT_KEYS : 7809 NUM_BMAC_STAT_KEYS) + 7810 (np->num_rx_rings * NUM_RXCHAN_STAT_KEYS) + 7811 (np->num_tx_rings * NUM_TXCHAN_STAT_KEYS); 7812 } 7813 7814 static void niu_get_ethtool_stats(struct net_device *dev, 7815 struct ethtool_stats *stats, u64 *data) 7816 { 7817 struct niu *np = netdev_priv(dev); 7818 int i; 7819 7820 niu_sync_mac_stats(np); 7821 if (np->flags & NIU_FLAGS_XMAC) { 7822 memcpy(data, &np->mac_stats.xmac, 7823 sizeof(struct niu_xmac_stats)); 7824 data += (sizeof(struct niu_xmac_stats) / sizeof(u64)); 7825 } else { 7826 memcpy(data, &np->mac_stats.bmac, 7827 sizeof(struct niu_bmac_stats)); 7828 data += (sizeof(struct niu_bmac_stats) / sizeof(u64)); 7829 } 7830 for (i = 0; i < np->num_rx_rings; i++) { 7831 struct rx_ring_info *rp = &np->rx_rings[i]; 7832 7833 niu_sync_rx_discard_stats(np, rp, 0); 7834 7835 data[0] = rp->rx_channel; 7836 data[1] = rp->rx_packets; 7837 data[2] = rp->rx_bytes; 7838 data[3] = rp->rx_dropped; 7839 data[4] = rp->rx_errors; 7840 data += 5; 7841 } 7842 for (i = 0; i < np->num_tx_rings; i++) { 7843 struct tx_ring_info *rp = &np->tx_rings[i]; 7844 7845 data[0] = rp->tx_channel; 7846 data[1] = rp->tx_packets; 7847 data[2] = rp->tx_bytes; 7848 data[3] = rp->tx_errors; 7849 data += 4; 7850 } 7851 } 7852 7853 static u64 niu_led_state_save(struct niu *np) 7854 { 7855 if (np->flags & NIU_FLAGS_XMAC) 7856 return nr64_mac(XMAC_CONFIG); 7857 else 7858 return nr64_mac(BMAC_XIF_CONFIG); 7859 } 7860 7861 static void niu_led_state_restore(struct niu *np, u64 val) 7862 { 7863 if (np->flags & NIU_FLAGS_XMAC) 7864 nw64_mac(XMAC_CONFIG, val); 7865 else 7866 nw64_mac(BMAC_XIF_CONFIG, val); 7867 } 7868 7869 static void niu_force_led(struct niu *np, int on) 7870 { 7871 u64 val, reg, bit; 7872 7873 if (np->flags & NIU_FLAGS_XMAC) { 7874 reg = XMAC_CONFIG; 7875 bit = XMAC_CONFIG_FORCE_LED_ON; 7876 } else { 7877 reg = BMAC_XIF_CONFIG; 7878 bit = BMAC_XIF_CONFIG_LINK_LED; 7879 } 7880 7881 val = nr64_mac(reg); 7882 if (on) 7883 val |= bit; 7884 else 7885 val &= ~bit; 7886 nw64_mac(reg, val); 7887 } 7888 7889 static int niu_set_phys_id(struct net_device *dev, 7890 enum ethtool_phys_id_state state) 7891 7892 { 7893 struct niu *np = netdev_priv(dev); 7894 7895 if (!netif_running(dev)) 7896 return -EAGAIN; 7897 7898 switch (state) { 7899 case ETHTOOL_ID_ACTIVE: 7900 np->orig_led_state = niu_led_state_save(np); 7901 return 1; /* cycle on/off once per second */ 7902 7903 case ETHTOOL_ID_ON: 7904 niu_force_led(np, 1); 7905 break; 7906 7907 case ETHTOOL_ID_OFF: 7908 niu_force_led(np, 0); 7909 break; 7910 7911 case ETHTOOL_ID_INACTIVE: 7912 niu_led_state_restore(np, np->orig_led_state); 7913 } 7914 7915 return 0; 7916 } 7917 7918 static const struct ethtool_ops niu_ethtool_ops = { 7919 .get_drvinfo = niu_get_drvinfo, 7920 .get_link = ethtool_op_get_link, 7921 .get_msglevel = niu_get_msglevel, 7922 .set_msglevel = niu_set_msglevel, 7923 .nway_reset = niu_nway_reset, 7924 .get_eeprom_len = niu_get_eeprom_len, 7925 .get_eeprom = niu_get_eeprom, 7926 .get_strings = niu_get_strings, 7927 .get_sset_count = niu_get_sset_count, 7928 .get_ethtool_stats = niu_get_ethtool_stats, 7929 .set_phys_id = niu_set_phys_id, 7930 .get_rxnfc = niu_get_nfc, 7931 .set_rxnfc = niu_set_nfc, 7932 .get_rx_ring_count = niu_get_rx_ring_count, 7933 .get_rxfh_fields = niu_get_rxfh_fields, 7934 .set_rxfh_fields = niu_set_rxfh_fields, 7935 .get_link_ksettings = niu_get_link_ksettings, 7936 .set_link_ksettings = niu_set_link_ksettings, 7937 }; 7938 7939 static int niu_ldg_assign_ldn(struct niu *np, struct niu_parent *parent, 7940 int ldg, int ldn) 7941 { 7942 if (ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) 7943 return -EINVAL; 7944 if (ldn < 0 || ldn > LDN_MAX) 7945 return -EINVAL; 7946 7947 parent->ldg_map[ldn] = ldg; 7948 7949 if (np->parent->plat_type == PLAT_TYPE_NIU) { 7950 /* On N2 NIU, the ldn-->ldg assignments are setup and fixed by 7951 * the firmware, and we're not supposed to change them. 7952 * Validate the mapping, because if it's wrong we probably 7953 * won't get any interrupts and that's painful to debug. 7954 */ 7955 if (nr64(LDG_NUM(ldn)) != ldg) { 7956 dev_err(np->device, "Port %u, mismatched LDG assignment for ldn %d, should be %d is %llu\n", 7957 np->port, ldn, ldg, 7958 (unsigned long long) nr64(LDG_NUM(ldn))); 7959 return -EINVAL; 7960 } 7961 } else 7962 nw64(LDG_NUM(ldn), ldg); 7963 7964 return 0; 7965 } 7966 7967 static int niu_set_ldg_timer_res(struct niu *np, int res) 7968 { 7969 if (res < 0 || res > LDG_TIMER_RES_VAL) 7970 return -EINVAL; 7971 7972 7973 nw64(LDG_TIMER_RES, res); 7974 7975 return 0; 7976 } 7977 7978 static int niu_set_ldg_sid(struct niu *np, int ldg, int func, int vector) 7979 { 7980 if ((ldg < NIU_LDG_MIN || ldg > NIU_LDG_MAX) || 7981 (func < 0 || func > 3) || 7982 (vector < 0 || vector > 0x1f)) 7983 return -EINVAL; 7984 7985 nw64(SID(ldg), (func << SID_FUNC_SHIFT) | vector); 7986 7987 return 0; 7988 } 7989 7990 static int niu_pci_eeprom_read(struct niu *np, u32 addr) 7991 { 7992 u64 frame, frame_base = (ESPC_PIO_STAT_READ_START | 7993 (addr << ESPC_PIO_STAT_ADDR_SHIFT)); 7994 int limit; 7995 7996 if (addr > (ESPC_PIO_STAT_ADDR >> ESPC_PIO_STAT_ADDR_SHIFT)) 7997 return -EINVAL; 7998 7999 frame = frame_base; 8000 nw64(ESPC_PIO_STAT, frame); 8001 limit = 64; 8002 do { 8003 udelay(5); 8004 frame = nr64(ESPC_PIO_STAT); 8005 if (frame & ESPC_PIO_STAT_READ_END) 8006 break; 8007 } while (limit--); 8008 if (!(frame & ESPC_PIO_STAT_READ_END)) { 8009 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 8010 (unsigned long long) frame); 8011 return -ENODEV; 8012 } 8013 8014 frame = frame_base; 8015 nw64(ESPC_PIO_STAT, frame); 8016 limit = 64; 8017 do { 8018 udelay(5); 8019 frame = nr64(ESPC_PIO_STAT); 8020 if (frame & ESPC_PIO_STAT_READ_END) 8021 break; 8022 } while (limit--); 8023 if (!(frame & ESPC_PIO_STAT_READ_END)) { 8024 dev_err(np->device, "EEPROM read timeout frame[%llx]\n", 8025 (unsigned long long) frame); 8026 return -ENODEV; 8027 } 8028 8029 frame = nr64(ESPC_PIO_STAT); 8030 return (frame & ESPC_PIO_STAT_DATA) >> ESPC_PIO_STAT_DATA_SHIFT; 8031 } 8032 8033 static int niu_pci_eeprom_read16(struct niu *np, u32 off) 8034 { 8035 int err = niu_pci_eeprom_read(np, off); 8036 u16 val; 8037 8038 if (err < 0) 8039 return err; 8040 val = (err << 8); 8041 err = niu_pci_eeprom_read(np, off + 1); 8042 if (err < 0) 8043 return err; 8044 val |= (err & 0xff); 8045 8046 return val; 8047 } 8048 8049 static int niu_pci_eeprom_read16_swp(struct niu *np, u32 off) 8050 { 8051 int err = niu_pci_eeprom_read(np, off); 8052 u16 val; 8053 8054 if (err < 0) 8055 return err; 8056 8057 val = (err & 0xff); 8058 err = niu_pci_eeprom_read(np, off + 1); 8059 if (err < 0) 8060 return err; 8061 8062 val |= (err & 0xff) << 8; 8063 8064 return val; 8065 } 8066 8067 static int niu_pci_vpd_get_propname(struct niu *np, u32 off, char *namebuf, 8068 int namebuf_len) 8069 { 8070 int i; 8071 8072 for (i = 0; i < namebuf_len; i++) { 8073 int err = niu_pci_eeprom_read(np, off + i); 8074 if (err < 0) 8075 return err; 8076 *namebuf++ = err; 8077 if (!err) 8078 break; 8079 } 8080 if (i >= namebuf_len) 8081 return -EINVAL; 8082 8083 return i + 1; 8084 } 8085 8086 static void niu_vpd_parse_version(struct niu *np) 8087 { 8088 struct niu_vpd *vpd = &np->vpd; 8089 int len = strlen(vpd->version) + 1; 8090 const char *s = vpd->version; 8091 int i; 8092 8093 for (i = 0; i < len - 5; i++) { 8094 if (!strncmp(s + i, "FCode ", 6)) 8095 break; 8096 } 8097 if (i >= len - 5) 8098 return; 8099 8100 s += i + 5; 8101 sscanf(s, "%d.%d", &vpd->fcode_major, &vpd->fcode_minor); 8102 8103 netif_printk(np, probe, KERN_DEBUG, np->dev, 8104 "VPD_SCAN: FCODE major(%d) minor(%d)\n", 8105 vpd->fcode_major, vpd->fcode_minor); 8106 if (vpd->fcode_major > NIU_VPD_MIN_MAJOR || 8107 (vpd->fcode_major == NIU_VPD_MIN_MAJOR && 8108 vpd->fcode_minor >= NIU_VPD_MIN_MINOR)) 8109 np->flags |= NIU_FLAGS_VPD_VALID; 8110 } 8111 8112 /* ESPC_PIO_EN_ENABLE must be set */ 8113 static int niu_pci_vpd_scan_props(struct niu *np, u32 start, u32 end) 8114 { 8115 unsigned int found_mask = 0; 8116 #define FOUND_MASK_MODEL 0x00000001 8117 #define FOUND_MASK_BMODEL 0x00000002 8118 #define FOUND_MASK_VERS 0x00000004 8119 #define FOUND_MASK_MAC 0x00000008 8120 #define FOUND_MASK_NMAC 0x00000010 8121 #define FOUND_MASK_PHY 0x00000020 8122 #define FOUND_MASK_ALL 0x0000003f 8123 8124 netif_printk(np, probe, KERN_DEBUG, np->dev, 8125 "VPD_SCAN: start[%x] end[%x]\n", start, end); 8126 while (start < end) { 8127 int len, err, prop_len; 8128 char namebuf[64]; 8129 u8 *prop_buf; 8130 int max_len; 8131 8132 if (found_mask == FOUND_MASK_ALL) { 8133 niu_vpd_parse_version(np); 8134 return 1; 8135 } 8136 8137 err = niu_pci_eeprom_read(np, start + 2); 8138 if (err < 0) 8139 return err; 8140 len = err; 8141 start += 3; 8142 8143 prop_len = niu_pci_eeprom_read(np, start + 4); 8144 if (prop_len < 0) 8145 return prop_len; 8146 err = niu_pci_vpd_get_propname(np, start + 5, namebuf, 64); 8147 if (err < 0) 8148 return err; 8149 8150 prop_buf = NULL; 8151 max_len = 0; 8152 if (!strcmp(namebuf, "model")) { 8153 prop_buf = np->vpd.model; 8154 max_len = NIU_VPD_MODEL_MAX; 8155 found_mask |= FOUND_MASK_MODEL; 8156 } else if (!strcmp(namebuf, "board-model")) { 8157 prop_buf = np->vpd.board_model; 8158 max_len = NIU_VPD_BD_MODEL_MAX; 8159 found_mask |= FOUND_MASK_BMODEL; 8160 } else if (!strcmp(namebuf, "version")) { 8161 prop_buf = np->vpd.version; 8162 max_len = NIU_VPD_VERSION_MAX; 8163 found_mask |= FOUND_MASK_VERS; 8164 } else if (!strcmp(namebuf, "local-mac-address")) { 8165 prop_buf = np->vpd.local_mac; 8166 max_len = ETH_ALEN; 8167 found_mask |= FOUND_MASK_MAC; 8168 } else if (!strcmp(namebuf, "num-mac-addresses")) { 8169 prop_buf = &np->vpd.mac_num; 8170 max_len = 1; 8171 found_mask |= FOUND_MASK_NMAC; 8172 } else if (!strcmp(namebuf, "phy-type")) { 8173 prop_buf = np->vpd.phy_type; 8174 max_len = NIU_VPD_PHY_TYPE_MAX; 8175 found_mask |= FOUND_MASK_PHY; 8176 } 8177 8178 if (max_len && prop_len > max_len) { 8179 dev_err(np->device, "Property '%s' length (%d) is too long\n", namebuf, prop_len); 8180 return -EINVAL; 8181 } 8182 8183 if (prop_buf) { 8184 u32 off = start + 5 + err; 8185 int i; 8186 8187 netif_printk(np, probe, KERN_DEBUG, np->dev, 8188 "VPD_SCAN: Reading in property [%s] len[%d]\n", 8189 namebuf, prop_len); 8190 for (i = 0; i < prop_len; i++) { 8191 err = niu_pci_eeprom_read(np, off + i); 8192 if (err < 0) 8193 return err; 8194 *prop_buf++ = err; 8195 } 8196 } 8197 8198 start += len; 8199 } 8200 8201 return 0; 8202 } 8203 8204 /* ESPC_PIO_EN_ENABLE must be set */ 8205 static int niu_pci_vpd_fetch(struct niu *np, u32 start) 8206 { 8207 u32 offset; 8208 int err; 8209 8210 err = niu_pci_eeprom_read16_swp(np, start + 1); 8211 if (err < 0) 8212 return err; 8213 8214 offset = err + 3; 8215 8216 while (start + offset < ESPC_EEPROM_SIZE) { 8217 u32 here = start + offset; 8218 u32 end; 8219 8220 err = niu_pci_eeprom_read(np, here); 8221 if (err < 0) 8222 return err; 8223 if (err != 0x90) 8224 return -EINVAL; 8225 8226 err = niu_pci_eeprom_read16_swp(np, here + 1); 8227 if (err < 0) 8228 return err; 8229 8230 here = start + offset + 3; 8231 end = start + offset + err; 8232 8233 offset += err; 8234 8235 err = niu_pci_vpd_scan_props(np, here, end); 8236 if (err < 0) 8237 return err; 8238 /* ret == 1 is not an error */ 8239 if (err == 1) 8240 return 0; 8241 } 8242 return 0; 8243 } 8244 8245 /* ESPC_PIO_EN_ENABLE must be set */ 8246 static u32 niu_pci_vpd_offset(struct niu *np) 8247 { 8248 u32 start = 0, end = ESPC_EEPROM_SIZE, ret; 8249 int err; 8250 8251 while (start < end) { 8252 ret = start; 8253 8254 /* ROM header signature? */ 8255 err = niu_pci_eeprom_read16(np, start + 0); 8256 if (err != 0x55aa) 8257 return 0; 8258 8259 /* Apply offset to PCI data structure. */ 8260 err = niu_pci_eeprom_read16(np, start + 23); 8261 if (err < 0) 8262 return 0; 8263 start += err; 8264 8265 /* Check for "PCIR" signature. */ 8266 err = niu_pci_eeprom_read16(np, start + 0); 8267 if (err != 0x5043) 8268 return 0; 8269 err = niu_pci_eeprom_read16(np, start + 2); 8270 if (err != 0x4952) 8271 return 0; 8272 8273 /* Check for OBP image type. */ 8274 err = niu_pci_eeprom_read(np, start + 20); 8275 if (err < 0) 8276 return 0; 8277 if (err != 0x01) { 8278 err = niu_pci_eeprom_read(np, ret + 2); 8279 if (err < 0) 8280 return 0; 8281 8282 start = ret + (err * 512); 8283 continue; 8284 } 8285 8286 err = niu_pci_eeprom_read16_swp(np, start + 8); 8287 if (err < 0) 8288 return err; 8289 ret += err; 8290 8291 err = niu_pci_eeprom_read(np, ret + 0); 8292 if (err != 0x82) 8293 return 0; 8294 8295 return ret; 8296 } 8297 8298 return 0; 8299 } 8300 8301 static int niu_phy_type_prop_decode(struct niu *np, const char *phy_prop) 8302 { 8303 if (!strcmp(phy_prop, "mif")) { 8304 /* 1G copper, MII */ 8305 np->flags &= ~(NIU_FLAGS_FIBER | 8306 NIU_FLAGS_10G); 8307 np->mac_xcvr = MAC_XCVR_MII; 8308 } else if (!strcmp(phy_prop, "xgf")) { 8309 /* 10G fiber, XPCS */ 8310 np->flags |= (NIU_FLAGS_10G | 8311 NIU_FLAGS_FIBER); 8312 np->mac_xcvr = MAC_XCVR_XPCS; 8313 } else if (!strcmp(phy_prop, "pcs")) { 8314 /* 1G fiber, PCS */ 8315 np->flags &= ~NIU_FLAGS_10G; 8316 np->flags |= NIU_FLAGS_FIBER; 8317 np->mac_xcvr = MAC_XCVR_PCS; 8318 } else if (!strcmp(phy_prop, "xgc")) { 8319 /* 10G copper, XPCS */ 8320 np->flags |= NIU_FLAGS_10G; 8321 np->flags &= ~NIU_FLAGS_FIBER; 8322 np->mac_xcvr = MAC_XCVR_XPCS; 8323 } else if (!strcmp(phy_prop, "xgsd") || !strcmp(phy_prop, "gsd")) { 8324 /* 10G Serdes or 1G Serdes, default to 10G */ 8325 np->flags |= NIU_FLAGS_10G; 8326 np->flags &= ~NIU_FLAGS_FIBER; 8327 np->flags |= NIU_FLAGS_XCVR_SERDES; 8328 np->mac_xcvr = MAC_XCVR_XPCS; 8329 } else { 8330 return -EINVAL; 8331 } 8332 return 0; 8333 } 8334 8335 static int niu_pci_vpd_get_nports(struct niu *np) 8336 { 8337 int ports = 0; 8338 8339 if ((!strcmp(np->vpd.model, NIU_QGC_LP_MDL_STR)) || 8340 (!strcmp(np->vpd.model, NIU_QGC_PEM_MDL_STR)) || 8341 (!strcmp(np->vpd.model, NIU_MARAMBA_MDL_STR)) || 8342 (!strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) || 8343 (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR))) { 8344 ports = 4; 8345 } else if ((!strcmp(np->vpd.model, NIU_2XGF_LP_MDL_STR)) || 8346 (!strcmp(np->vpd.model, NIU_2XGF_PEM_MDL_STR)) || 8347 (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) || 8348 (!strcmp(np->vpd.model, NIU_2XGF_MRVL_MDL_STR))) { 8349 ports = 2; 8350 } 8351 8352 return ports; 8353 } 8354 8355 static void niu_pci_vpd_validate(struct niu *np) 8356 { 8357 struct net_device *dev = np->dev; 8358 struct niu_vpd *vpd = &np->vpd; 8359 u8 addr[ETH_ALEN]; 8360 u8 val8; 8361 8362 if (!is_valid_ether_addr(&vpd->local_mac[0])) { 8363 dev_err(np->device, "VPD MAC invalid, falling back to SPROM\n"); 8364 8365 np->flags &= ~NIU_FLAGS_VPD_VALID; 8366 return; 8367 } 8368 8369 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8370 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8371 np->flags |= NIU_FLAGS_10G; 8372 np->flags &= ~NIU_FLAGS_FIBER; 8373 np->flags |= NIU_FLAGS_XCVR_SERDES; 8374 np->mac_xcvr = MAC_XCVR_PCS; 8375 if (np->port > 1) { 8376 np->flags |= NIU_FLAGS_FIBER; 8377 np->flags &= ~NIU_FLAGS_10G; 8378 } 8379 if (np->flags & NIU_FLAGS_10G) 8380 np->mac_xcvr = MAC_XCVR_XPCS; 8381 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8382 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 8383 NIU_FLAGS_HOTPLUG_PHY); 8384 } else if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 8385 dev_err(np->device, "Illegal phy string [%s]\n", 8386 np->vpd.phy_type); 8387 dev_err(np->device, "Falling back to SPROM\n"); 8388 np->flags &= ~NIU_FLAGS_VPD_VALID; 8389 return; 8390 } 8391 8392 ether_addr_copy(addr, vpd->local_mac); 8393 8394 val8 = addr[5]; 8395 addr[5] += np->port; 8396 if (addr[5] < val8) 8397 addr[4]++; 8398 8399 eth_hw_addr_set(dev, addr); 8400 } 8401 8402 static int niu_pci_probe_sprom(struct niu *np) 8403 { 8404 struct net_device *dev = np->dev; 8405 u8 addr[ETH_ALEN]; 8406 int len, i; 8407 u64 val, sum; 8408 u8 val8; 8409 8410 val = (nr64(ESPC_VER_IMGSZ) & ESPC_VER_IMGSZ_IMGSZ); 8411 val >>= ESPC_VER_IMGSZ_IMGSZ_SHIFT; 8412 len = val / 4; 8413 8414 np->eeprom_len = len; 8415 8416 netif_printk(np, probe, KERN_DEBUG, np->dev, 8417 "SPROM: Image size %llu\n", (unsigned long long)val); 8418 8419 sum = 0; 8420 for (i = 0; i < len; i++) { 8421 val = nr64(ESPC_NCR(i)); 8422 sum += (val >> 0) & 0xff; 8423 sum += (val >> 8) & 0xff; 8424 sum += (val >> 16) & 0xff; 8425 sum += (val >> 24) & 0xff; 8426 } 8427 netif_printk(np, probe, KERN_DEBUG, np->dev, 8428 "SPROM: Checksum %x\n", (int)(sum & 0xff)); 8429 if ((sum & 0xff) != 0xab) { 8430 dev_err(np->device, "Bad SPROM checksum (%x, should be 0xab)\n", (int)(sum & 0xff)); 8431 return -EINVAL; 8432 } 8433 8434 val = nr64(ESPC_PHY_TYPE); 8435 switch (np->port) { 8436 case 0: 8437 val8 = (val & ESPC_PHY_TYPE_PORT0) >> 8438 ESPC_PHY_TYPE_PORT0_SHIFT; 8439 break; 8440 case 1: 8441 val8 = (val & ESPC_PHY_TYPE_PORT1) >> 8442 ESPC_PHY_TYPE_PORT1_SHIFT; 8443 break; 8444 case 2: 8445 val8 = (val & ESPC_PHY_TYPE_PORT2) >> 8446 ESPC_PHY_TYPE_PORT2_SHIFT; 8447 break; 8448 case 3: 8449 val8 = (val & ESPC_PHY_TYPE_PORT3) >> 8450 ESPC_PHY_TYPE_PORT3_SHIFT; 8451 break; 8452 default: 8453 dev_err(np->device, "Bogus port number %u\n", 8454 np->port); 8455 return -EINVAL; 8456 } 8457 netif_printk(np, probe, KERN_DEBUG, np->dev, 8458 "SPROM: PHY type %x\n", val8); 8459 8460 switch (val8) { 8461 case ESPC_PHY_TYPE_1G_COPPER: 8462 /* 1G copper, MII */ 8463 np->flags &= ~(NIU_FLAGS_FIBER | 8464 NIU_FLAGS_10G); 8465 np->mac_xcvr = MAC_XCVR_MII; 8466 break; 8467 8468 case ESPC_PHY_TYPE_1G_FIBER: 8469 /* 1G fiber, PCS */ 8470 np->flags &= ~NIU_FLAGS_10G; 8471 np->flags |= NIU_FLAGS_FIBER; 8472 np->mac_xcvr = MAC_XCVR_PCS; 8473 break; 8474 8475 case ESPC_PHY_TYPE_10G_COPPER: 8476 /* 10G copper, XPCS */ 8477 np->flags |= NIU_FLAGS_10G; 8478 np->flags &= ~NIU_FLAGS_FIBER; 8479 np->mac_xcvr = MAC_XCVR_XPCS; 8480 break; 8481 8482 case ESPC_PHY_TYPE_10G_FIBER: 8483 /* 10G fiber, XPCS */ 8484 np->flags |= (NIU_FLAGS_10G | 8485 NIU_FLAGS_FIBER); 8486 np->mac_xcvr = MAC_XCVR_XPCS; 8487 break; 8488 8489 default: 8490 dev_err(np->device, "Bogus SPROM phy type %u\n", val8); 8491 return -EINVAL; 8492 } 8493 8494 val = nr64(ESPC_MAC_ADDR0); 8495 netif_printk(np, probe, KERN_DEBUG, np->dev, 8496 "SPROM: MAC_ADDR0[%08llx]\n", (unsigned long long)val); 8497 addr[0] = (val >> 0) & 0xff; 8498 addr[1] = (val >> 8) & 0xff; 8499 addr[2] = (val >> 16) & 0xff; 8500 addr[3] = (val >> 24) & 0xff; 8501 8502 val = nr64(ESPC_MAC_ADDR1); 8503 netif_printk(np, probe, KERN_DEBUG, np->dev, 8504 "SPROM: MAC_ADDR1[%08llx]\n", (unsigned long long)val); 8505 addr[4] = (val >> 0) & 0xff; 8506 addr[5] = (val >> 8) & 0xff; 8507 8508 if (!is_valid_ether_addr(addr)) { 8509 dev_err(np->device, "SPROM MAC address invalid [ %pM ]\n", 8510 addr); 8511 return -EINVAL; 8512 } 8513 8514 val8 = addr[5]; 8515 addr[5] += np->port; 8516 if (addr[5] < val8) 8517 addr[4]++; 8518 8519 eth_hw_addr_set(dev, addr); 8520 8521 val = nr64(ESPC_MOD_STR_LEN); 8522 netif_printk(np, probe, KERN_DEBUG, np->dev, 8523 "SPROM: MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8524 if (val >= 8 * 4) 8525 return -EINVAL; 8526 8527 for (i = 0; i < val; i += 4) { 8528 u64 tmp = nr64(ESPC_NCR(5 + (i / 4))); 8529 8530 np->vpd.model[i + 3] = (tmp >> 0) & 0xff; 8531 np->vpd.model[i + 2] = (tmp >> 8) & 0xff; 8532 np->vpd.model[i + 1] = (tmp >> 16) & 0xff; 8533 np->vpd.model[i + 0] = (tmp >> 24) & 0xff; 8534 } 8535 np->vpd.model[val] = '\0'; 8536 8537 val = nr64(ESPC_BD_MOD_STR_LEN); 8538 netif_printk(np, probe, KERN_DEBUG, np->dev, 8539 "SPROM: BD_MOD_STR_LEN[%llu]\n", (unsigned long long)val); 8540 if (val >= 4 * 4) 8541 return -EINVAL; 8542 8543 for (i = 0; i < val; i += 4) { 8544 u64 tmp = nr64(ESPC_NCR(14 + (i / 4))); 8545 8546 np->vpd.board_model[i + 3] = (tmp >> 0) & 0xff; 8547 np->vpd.board_model[i + 2] = (tmp >> 8) & 0xff; 8548 np->vpd.board_model[i + 1] = (tmp >> 16) & 0xff; 8549 np->vpd.board_model[i + 0] = (tmp >> 24) & 0xff; 8550 } 8551 np->vpd.board_model[val] = '\0'; 8552 8553 np->vpd.mac_num = 8554 nr64(ESPC_NUM_PORTS_MACS) & ESPC_NUM_PORTS_MACS_VAL; 8555 netif_printk(np, probe, KERN_DEBUG, np->dev, 8556 "SPROM: NUM_PORTS_MACS[%d]\n", np->vpd.mac_num); 8557 8558 return 0; 8559 } 8560 8561 static int niu_get_and_validate_port(struct niu *np) 8562 { 8563 struct niu_parent *parent = np->parent; 8564 8565 if (np->port <= 1) 8566 np->flags |= NIU_FLAGS_XMAC; 8567 8568 if (!parent->num_ports) { 8569 if (parent->plat_type == PLAT_TYPE_NIU) { 8570 parent->num_ports = 2; 8571 } else { 8572 parent->num_ports = niu_pci_vpd_get_nports(np); 8573 if (!parent->num_ports) { 8574 /* Fall back to SPROM as last resort. 8575 * This will fail on most cards. 8576 */ 8577 parent->num_ports = nr64(ESPC_NUM_PORTS_MACS) & 8578 ESPC_NUM_PORTS_MACS_VAL; 8579 8580 /* All of the current probing methods fail on 8581 * Maramba on-board parts. 8582 */ 8583 if (!parent->num_ports) 8584 parent->num_ports = 4; 8585 } 8586 } 8587 } 8588 8589 if (np->port >= parent->num_ports) 8590 return -ENODEV; 8591 8592 return 0; 8593 } 8594 8595 static int phy_record(struct niu_parent *parent, struct phy_probe_info *p, 8596 int dev_id_1, int dev_id_2, u8 phy_port, int type) 8597 { 8598 u32 id = (dev_id_1 << 16) | dev_id_2; 8599 u8 idx; 8600 8601 if (dev_id_1 < 0 || dev_id_2 < 0) 8602 return 0; 8603 if (type == PHY_TYPE_PMA_PMD || type == PHY_TYPE_PCS) { 8604 /* Because of the NIU_PHY_ID_MASK being applied, the 8704 8605 * test covers the 8706 as well. 8606 */ 8607 if (((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM8704) && 8608 ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_MRVL88X2011)) 8609 return 0; 8610 } else { 8611 if ((id & NIU_PHY_ID_MASK) != NIU_PHY_ID_BCM5464R) 8612 return 0; 8613 } 8614 8615 pr_info("niu%d: Found PHY %08x type %s at phy_port %u\n", 8616 parent->index, id, 8617 type == PHY_TYPE_PMA_PMD ? "PMA/PMD" : 8618 type == PHY_TYPE_PCS ? "PCS" : "MII", 8619 phy_port); 8620 8621 if (p->cur[type] >= NIU_MAX_PORTS) { 8622 pr_err("Too many PHY ports\n"); 8623 return -EINVAL; 8624 } 8625 idx = p->cur[type]; 8626 p->phy_id[type][idx] = id; 8627 p->phy_port[type][idx] = phy_port; 8628 p->cur[type] = idx + 1; 8629 return 0; 8630 } 8631 8632 static int port_has_10g(struct phy_probe_info *p, int port) 8633 { 8634 int i; 8635 8636 for (i = 0; i < p->cur[PHY_TYPE_PMA_PMD]; i++) { 8637 if (p->phy_port[PHY_TYPE_PMA_PMD][i] == port) 8638 return 1; 8639 } 8640 for (i = 0; i < p->cur[PHY_TYPE_PCS]; i++) { 8641 if (p->phy_port[PHY_TYPE_PCS][i] == port) 8642 return 1; 8643 } 8644 8645 return 0; 8646 } 8647 8648 static int count_10g_ports(struct phy_probe_info *p, int *lowest) 8649 { 8650 int port, cnt; 8651 8652 cnt = 0; 8653 *lowest = 32; 8654 for (port = 8; port < 32; port++) { 8655 if (port_has_10g(p, port)) { 8656 if (!cnt) 8657 *lowest = port; 8658 cnt++; 8659 } 8660 } 8661 8662 return cnt; 8663 } 8664 8665 static int count_1g_ports(struct phy_probe_info *p, int *lowest) 8666 { 8667 *lowest = 32; 8668 if (p->cur[PHY_TYPE_MII]) 8669 *lowest = p->phy_port[PHY_TYPE_MII][0]; 8670 8671 return p->cur[PHY_TYPE_MII]; 8672 } 8673 8674 static void niu_n2_divide_channels(struct niu_parent *parent) 8675 { 8676 int num_ports = parent->num_ports; 8677 int i; 8678 8679 for (i = 0; i < num_ports; i++) { 8680 parent->rxchan_per_port[i] = (16 / num_ports); 8681 parent->txchan_per_port[i] = (16 / num_ports); 8682 8683 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8684 parent->index, i, 8685 parent->rxchan_per_port[i], 8686 parent->txchan_per_port[i]); 8687 } 8688 } 8689 8690 static void niu_divide_channels(struct niu_parent *parent, 8691 int num_10g, int num_1g) 8692 { 8693 int num_ports = parent->num_ports; 8694 int rx_chans_per_10g, rx_chans_per_1g; 8695 int tx_chans_per_10g, tx_chans_per_1g; 8696 int i, tot_rx, tot_tx; 8697 8698 if (!num_10g || !num_1g) { 8699 rx_chans_per_10g = rx_chans_per_1g = 8700 (NIU_NUM_RXCHAN / num_ports); 8701 tx_chans_per_10g = tx_chans_per_1g = 8702 (NIU_NUM_TXCHAN / num_ports); 8703 } else { 8704 rx_chans_per_1g = NIU_NUM_RXCHAN / 8; 8705 rx_chans_per_10g = (NIU_NUM_RXCHAN - 8706 (rx_chans_per_1g * num_1g)) / 8707 num_10g; 8708 8709 tx_chans_per_1g = NIU_NUM_TXCHAN / 6; 8710 tx_chans_per_10g = (NIU_NUM_TXCHAN - 8711 (tx_chans_per_1g * num_1g)) / 8712 num_10g; 8713 } 8714 8715 tot_rx = tot_tx = 0; 8716 for (i = 0; i < num_ports; i++) { 8717 int type = phy_decode(parent->port_phy, i); 8718 8719 if (type == PORT_TYPE_10G) { 8720 parent->rxchan_per_port[i] = rx_chans_per_10g; 8721 parent->txchan_per_port[i] = tx_chans_per_10g; 8722 } else { 8723 parent->rxchan_per_port[i] = rx_chans_per_1g; 8724 parent->txchan_per_port[i] = tx_chans_per_1g; 8725 } 8726 pr_info("niu%d: Port %u [%u RX chans] [%u TX chans]\n", 8727 parent->index, i, 8728 parent->rxchan_per_port[i], 8729 parent->txchan_per_port[i]); 8730 tot_rx += parent->rxchan_per_port[i]; 8731 tot_tx += parent->txchan_per_port[i]; 8732 } 8733 8734 if (tot_rx > NIU_NUM_RXCHAN) { 8735 pr_err("niu%d: Too many RX channels (%d), resetting to one per port\n", 8736 parent->index, tot_rx); 8737 for (i = 0; i < num_ports; i++) 8738 parent->rxchan_per_port[i] = 1; 8739 } 8740 if (tot_tx > NIU_NUM_TXCHAN) { 8741 pr_err("niu%d: Too many TX channels (%d), resetting to one per port\n", 8742 parent->index, tot_tx); 8743 for (i = 0; i < num_ports; i++) 8744 parent->txchan_per_port[i] = 1; 8745 } 8746 if (tot_rx < NIU_NUM_RXCHAN || tot_tx < NIU_NUM_TXCHAN) { 8747 pr_warn("niu%d: Driver bug, wasted channels, RX[%d] TX[%d]\n", 8748 parent->index, tot_rx, tot_tx); 8749 } 8750 } 8751 8752 static void niu_divide_rdc_groups(struct niu_parent *parent, 8753 int num_10g, int num_1g) 8754 { 8755 int i, num_ports = parent->num_ports; 8756 int rdc_group, rdc_groups_per_port; 8757 int rdc_channel_base; 8758 8759 rdc_group = 0; 8760 rdc_groups_per_port = NIU_NUM_RDC_TABLES / num_ports; 8761 8762 rdc_channel_base = 0; 8763 8764 for (i = 0; i < num_ports; i++) { 8765 struct niu_rdc_tables *tp = &parent->rdc_group_cfg[i]; 8766 int grp, num_channels = parent->rxchan_per_port[i]; 8767 int this_channel_offset; 8768 8769 tp->first_table_num = rdc_group; 8770 tp->num_tables = rdc_groups_per_port; 8771 this_channel_offset = 0; 8772 for (grp = 0; grp < tp->num_tables; grp++) { 8773 struct rdc_table *rt = &tp->tables[grp]; 8774 int slot; 8775 8776 pr_info("niu%d: Port %d RDC tbl(%d) [ ", 8777 parent->index, i, tp->first_table_num + grp); 8778 for (slot = 0; slot < NIU_RDC_TABLE_SLOTS; slot++) { 8779 rt->rxdma_channel[slot] = 8780 rdc_channel_base + this_channel_offset; 8781 8782 pr_cont("%d ", rt->rxdma_channel[slot]); 8783 8784 if (++this_channel_offset == num_channels) 8785 this_channel_offset = 0; 8786 } 8787 pr_cont("]\n"); 8788 } 8789 8790 parent->rdc_default[i] = rdc_channel_base; 8791 8792 rdc_channel_base += num_channels; 8793 rdc_group += rdc_groups_per_port; 8794 } 8795 } 8796 8797 static int fill_phy_probe_info(struct niu *np, struct niu_parent *parent, 8798 struct phy_probe_info *info) 8799 { 8800 unsigned long flags; 8801 int port, err; 8802 8803 memset(info, 0, sizeof(*info)); 8804 8805 /* Port 0 to 7 are reserved for onboard Serdes, probe the rest. */ 8806 niu_lock_parent(np, flags); 8807 err = 0; 8808 for (port = 8; port < 32; port++) { 8809 int dev_id_1, dev_id_2; 8810 8811 dev_id_1 = mdio_read(np, port, 8812 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID1); 8813 dev_id_2 = mdio_read(np, port, 8814 NIU_PMA_PMD_DEV_ADDR, MII_PHYSID2); 8815 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8816 PHY_TYPE_PMA_PMD); 8817 if (err) 8818 break; 8819 dev_id_1 = mdio_read(np, port, 8820 NIU_PCS_DEV_ADDR, MII_PHYSID1); 8821 dev_id_2 = mdio_read(np, port, 8822 NIU_PCS_DEV_ADDR, MII_PHYSID2); 8823 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8824 PHY_TYPE_PCS); 8825 if (err) 8826 break; 8827 dev_id_1 = mii_read(np, port, MII_PHYSID1); 8828 dev_id_2 = mii_read(np, port, MII_PHYSID2); 8829 err = phy_record(parent, info, dev_id_1, dev_id_2, port, 8830 PHY_TYPE_MII); 8831 if (err) 8832 break; 8833 } 8834 niu_unlock_parent(np, flags); 8835 8836 return err; 8837 } 8838 8839 static int walk_phys(struct niu *np, struct niu_parent *parent) 8840 { 8841 struct phy_probe_info *info = &parent->phy_probe_info; 8842 int lowest_10g, lowest_1g; 8843 int num_10g, num_1g; 8844 u32 val; 8845 int err; 8846 8847 num_10g = num_1g = 0; 8848 8849 if (!strcmp(np->vpd.model, NIU_ALONSO_MDL_STR) || 8850 !strcmp(np->vpd.model, NIU_KIMI_MDL_STR)) { 8851 num_10g = 0; 8852 num_1g = 2; 8853 parent->plat_type = PLAT_TYPE_ATCA_CP3220; 8854 parent->num_ports = 4; 8855 val = (phy_encode(PORT_TYPE_1G, 0) | 8856 phy_encode(PORT_TYPE_1G, 1) | 8857 phy_encode(PORT_TYPE_1G, 2) | 8858 phy_encode(PORT_TYPE_1G, 3)); 8859 } else if (!strcmp(np->vpd.model, NIU_FOXXY_MDL_STR)) { 8860 num_10g = 2; 8861 num_1g = 0; 8862 parent->num_ports = 2; 8863 val = (phy_encode(PORT_TYPE_10G, 0) | 8864 phy_encode(PORT_TYPE_10G, 1)); 8865 } else if ((np->flags & NIU_FLAGS_XCVR_SERDES) && 8866 (parent->plat_type == PLAT_TYPE_NIU)) { 8867 /* this is the Monza case */ 8868 if (np->flags & NIU_FLAGS_10G) { 8869 val = (phy_encode(PORT_TYPE_10G, 0) | 8870 phy_encode(PORT_TYPE_10G, 1)); 8871 } else { 8872 val = (phy_encode(PORT_TYPE_1G, 0) | 8873 phy_encode(PORT_TYPE_1G, 1)); 8874 } 8875 } else { 8876 err = fill_phy_probe_info(np, parent, info); 8877 if (err) 8878 return err; 8879 8880 num_10g = count_10g_ports(info, &lowest_10g); 8881 num_1g = count_1g_ports(info, &lowest_1g); 8882 8883 switch ((num_10g << 4) | num_1g) { 8884 case 0x24: 8885 if (lowest_1g == 10) 8886 parent->plat_type = PLAT_TYPE_VF_P0; 8887 else if (lowest_1g == 26) 8888 parent->plat_type = PLAT_TYPE_VF_P1; 8889 else 8890 goto unknown_vg_1g_port; 8891 8892 fallthrough; 8893 case 0x22: 8894 val = (phy_encode(PORT_TYPE_10G, 0) | 8895 phy_encode(PORT_TYPE_10G, 1) | 8896 phy_encode(PORT_TYPE_1G, 2) | 8897 phy_encode(PORT_TYPE_1G, 3)); 8898 break; 8899 8900 case 0x20: 8901 val = (phy_encode(PORT_TYPE_10G, 0) | 8902 phy_encode(PORT_TYPE_10G, 1)); 8903 break; 8904 8905 case 0x10: 8906 val = phy_encode(PORT_TYPE_10G, np->port); 8907 break; 8908 8909 case 0x14: 8910 if (lowest_1g == 10) 8911 parent->plat_type = PLAT_TYPE_VF_P0; 8912 else if (lowest_1g == 26) 8913 parent->plat_type = PLAT_TYPE_VF_P1; 8914 else 8915 goto unknown_vg_1g_port; 8916 8917 fallthrough; 8918 case 0x13: 8919 if ((lowest_10g & 0x7) == 0) 8920 val = (phy_encode(PORT_TYPE_10G, 0) | 8921 phy_encode(PORT_TYPE_1G, 1) | 8922 phy_encode(PORT_TYPE_1G, 2) | 8923 phy_encode(PORT_TYPE_1G, 3)); 8924 else 8925 val = (phy_encode(PORT_TYPE_1G, 0) | 8926 phy_encode(PORT_TYPE_10G, 1) | 8927 phy_encode(PORT_TYPE_1G, 2) | 8928 phy_encode(PORT_TYPE_1G, 3)); 8929 break; 8930 8931 case 0x04: 8932 if (lowest_1g == 10) 8933 parent->plat_type = PLAT_TYPE_VF_P0; 8934 else if (lowest_1g == 26) 8935 parent->plat_type = PLAT_TYPE_VF_P1; 8936 else 8937 goto unknown_vg_1g_port; 8938 8939 val = (phy_encode(PORT_TYPE_1G, 0) | 8940 phy_encode(PORT_TYPE_1G, 1) | 8941 phy_encode(PORT_TYPE_1G, 2) | 8942 phy_encode(PORT_TYPE_1G, 3)); 8943 break; 8944 8945 default: 8946 pr_err("Unsupported port config 10G[%d] 1G[%d]\n", 8947 num_10g, num_1g); 8948 return -EINVAL; 8949 } 8950 } 8951 8952 parent->port_phy = val; 8953 8954 if (parent->plat_type == PLAT_TYPE_NIU) 8955 niu_n2_divide_channels(parent); 8956 else 8957 niu_divide_channels(parent, num_10g, num_1g); 8958 8959 niu_divide_rdc_groups(parent, num_10g, num_1g); 8960 8961 return 0; 8962 8963 unknown_vg_1g_port: 8964 pr_err("Cannot identify platform type, 1gport=%d\n", lowest_1g); 8965 return -EINVAL; 8966 } 8967 8968 static int niu_probe_ports(struct niu *np) 8969 { 8970 struct niu_parent *parent = np->parent; 8971 int err, i; 8972 8973 if (parent->port_phy == PORT_PHY_UNKNOWN) { 8974 err = walk_phys(np, parent); 8975 if (err) 8976 return err; 8977 8978 niu_set_ldg_timer_res(np, 2); 8979 for (i = 0; i <= LDN_MAX; i++) 8980 niu_ldn_irq_enable(np, i, 0); 8981 } 8982 8983 if (parent->port_phy == PORT_PHY_INVALID) 8984 return -EINVAL; 8985 8986 return 0; 8987 } 8988 8989 static int niu_classifier_swstate_init(struct niu *np) 8990 { 8991 struct niu_classifier *cp = &np->clas; 8992 8993 cp->tcam_top = (u16) np->port; 8994 cp->tcam_sz = np->parent->tcam_num_entries / np->parent->num_ports; 8995 cp->h1_init = 0xffffffff; 8996 cp->h2_init = 0xffff; 8997 8998 return fflp_early_init(np); 8999 } 9000 9001 static void niu_link_config_init(struct niu *np) 9002 { 9003 struct niu_link_config *lp = &np->link_config; 9004 9005 lp->advertising = (ADVERTISED_10baseT_Half | 9006 ADVERTISED_10baseT_Full | 9007 ADVERTISED_100baseT_Half | 9008 ADVERTISED_100baseT_Full | 9009 ADVERTISED_1000baseT_Half | 9010 ADVERTISED_1000baseT_Full | 9011 ADVERTISED_10000baseT_Full | 9012 ADVERTISED_Autoneg); 9013 lp->speed = lp->active_speed = SPEED_INVALID; 9014 lp->duplex = DUPLEX_FULL; 9015 lp->active_duplex = DUPLEX_INVALID; 9016 lp->autoneg = 1; 9017 #if 0 9018 lp->loopback_mode = LOOPBACK_MAC; 9019 lp->active_speed = SPEED_10000; 9020 lp->active_duplex = DUPLEX_FULL; 9021 #else 9022 lp->loopback_mode = LOOPBACK_DISABLED; 9023 #endif 9024 } 9025 9026 static int niu_init_mac_ipp_pcs_base(struct niu *np) 9027 { 9028 switch (np->port) { 9029 case 0: 9030 np->mac_regs = np->regs + XMAC_PORT0_OFF; 9031 np->ipp_off = 0x00000; 9032 np->pcs_off = 0x04000; 9033 np->xpcs_off = 0x02000; 9034 break; 9035 9036 case 1: 9037 np->mac_regs = np->regs + XMAC_PORT1_OFF; 9038 np->ipp_off = 0x08000; 9039 np->pcs_off = 0x0a000; 9040 np->xpcs_off = 0x08000; 9041 break; 9042 9043 case 2: 9044 np->mac_regs = np->regs + BMAC_PORT2_OFF; 9045 np->ipp_off = 0x04000; 9046 np->pcs_off = 0x0e000; 9047 np->xpcs_off = ~0UL; 9048 break; 9049 9050 case 3: 9051 np->mac_regs = np->regs + BMAC_PORT3_OFF; 9052 np->ipp_off = 0x0c000; 9053 np->pcs_off = 0x12000; 9054 np->xpcs_off = ~0UL; 9055 break; 9056 9057 default: 9058 dev_err(np->device, "Port %u is invalid, cannot compute MAC block offset\n", np->port); 9059 return -EINVAL; 9060 } 9061 9062 return 0; 9063 } 9064 9065 static void niu_try_msix(struct niu *np, u8 *ldg_num_map) 9066 { 9067 struct msix_entry msi_vec[NIU_NUM_LDG]; 9068 struct niu_parent *parent = np->parent; 9069 struct pci_dev *pdev = np->pdev; 9070 int i, num_irqs; 9071 u8 first_ldg; 9072 9073 first_ldg = (NIU_NUM_LDG / parent->num_ports) * np->port; 9074 for (i = 0; i < (NIU_NUM_LDG / parent->num_ports); i++) 9075 ldg_num_map[i] = first_ldg + i; 9076 9077 num_irqs = (parent->rxchan_per_port[np->port] + 9078 parent->txchan_per_port[np->port] + 9079 (np->port == 0 ? 3 : 1)); 9080 BUG_ON(num_irqs > (NIU_NUM_LDG / parent->num_ports)); 9081 9082 for (i = 0; i < num_irqs; i++) { 9083 msi_vec[i].vector = 0; 9084 msi_vec[i].entry = i; 9085 } 9086 9087 pdev->dev_flags |= PCI_DEV_FLAGS_MSIX_TOUCH_ENTRY_DATA_FIRST; 9088 9089 num_irqs = pci_enable_msix_range(pdev, msi_vec, 1, num_irqs); 9090 if (num_irqs < 0) { 9091 np->flags &= ~NIU_FLAGS_MSIX; 9092 return; 9093 } 9094 9095 np->flags |= NIU_FLAGS_MSIX; 9096 for (i = 0; i < num_irqs; i++) 9097 np->ldg[i].irq = msi_vec[i].vector; 9098 np->num_ldg = num_irqs; 9099 } 9100 9101 static int niu_n2_irq_init(struct niu *np, u8 *ldg_num_map) 9102 { 9103 #ifdef CONFIG_SPARC64 9104 struct platform_device *op = np->op; 9105 const u32 *int_prop; 9106 int i; 9107 9108 int_prop = of_get_property(op->dev.of_node, "interrupts", NULL); 9109 if (!int_prop) 9110 return -ENODEV; 9111 9112 for (i = 0; i < op->archdata.num_irqs; i++) { 9113 ldg_num_map[i] = int_prop[i]; 9114 np->ldg[i].irq = op->archdata.irqs[i]; 9115 } 9116 9117 np->num_ldg = op->archdata.num_irqs; 9118 9119 return 0; 9120 #else 9121 return -EINVAL; 9122 #endif 9123 } 9124 9125 static int niu_ldg_init(struct niu *np) 9126 { 9127 struct niu_parent *parent = np->parent; 9128 u8 ldg_num_map[NIU_NUM_LDG]; 9129 int first_chan, num_chan; 9130 int i, err, ldg_rotor; 9131 u8 port; 9132 9133 np->num_ldg = 1; 9134 np->ldg[0].irq = np->dev->irq; 9135 if (parent->plat_type == PLAT_TYPE_NIU) { 9136 err = niu_n2_irq_init(np, ldg_num_map); 9137 if (err) 9138 return err; 9139 } else 9140 niu_try_msix(np, ldg_num_map); 9141 9142 port = np->port; 9143 for (i = 0; i < np->num_ldg; i++) { 9144 struct niu_ldg *lp = &np->ldg[i]; 9145 9146 netif_napi_add(np->dev, &lp->napi, niu_poll); 9147 9148 lp->np = np; 9149 lp->ldg_num = ldg_num_map[i]; 9150 lp->timer = 2; /* XXX */ 9151 9152 /* On N2 NIU the firmware has setup the SID mappings so they go 9153 * to the correct values that will route the LDG to the proper 9154 * interrupt in the NCU interrupt table. 9155 */ 9156 if (np->parent->plat_type != PLAT_TYPE_NIU) { 9157 err = niu_set_ldg_sid(np, lp->ldg_num, port, i); 9158 if (err) 9159 return err; 9160 } 9161 } 9162 9163 /* We adopt the LDG assignment ordering used by the N2 NIU 9164 * 'interrupt' properties because that simplifies a lot of 9165 * things. This ordering is: 9166 * 9167 * MAC 9168 * MIF (if port zero) 9169 * SYSERR (if port zero) 9170 * RX channels 9171 * TX channels 9172 */ 9173 9174 ldg_rotor = 0; 9175 9176 err = niu_ldg_assign_ldn(np, parent, ldg_num_map[ldg_rotor], 9177 LDN_MAC(port)); 9178 if (err) 9179 return err; 9180 9181 ldg_rotor++; 9182 if (ldg_rotor == np->num_ldg) 9183 ldg_rotor = 0; 9184 9185 if (port == 0) { 9186 err = niu_ldg_assign_ldn(np, parent, 9187 ldg_num_map[ldg_rotor], 9188 LDN_MIF); 9189 if (err) 9190 return err; 9191 9192 ldg_rotor++; 9193 if (ldg_rotor == np->num_ldg) 9194 ldg_rotor = 0; 9195 9196 err = niu_ldg_assign_ldn(np, parent, 9197 ldg_num_map[ldg_rotor], 9198 LDN_DEVICE_ERROR); 9199 if (err) 9200 return err; 9201 9202 ldg_rotor++; 9203 if (ldg_rotor == np->num_ldg) 9204 ldg_rotor = 0; 9205 9206 } 9207 9208 first_chan = 0; 9209 for (i = 0; i < port; i++) 9210 first_chan += parent->rxchan_per_port[i]; 9211 num_chan = parent->rxchan_per_port[port]; 9212 9213 for (i = first_chan; i < (first_chan + num_chan); i++) { 9214 err = niu_ldg_assign_ldn(np, parent, 9215 ldg_num_map[ldg_rotor], 9216 LDN_RXDMA(i)); 9217 if (err) 9218 return err; 9219 ldg_rotor++; 9220 if (ldg_rotor == np->num_ldg) 9221 ldg_rotor = 0; 9222 } 9223 9224 first_chan = 0; 9225 for (i = 0; i < port; i++) 9226 first_chan += parent->txchan_per_port[i]; 9227 num_chan = parent->txchan_per_port[port]; 9228 for (i = first_chan; i < (first_chan + num_chan); i++) { 9229 err = niu_ldg_assign_ldn(np, parent, 9230 ldg_num_map[ldg_rotor], 9231 LDN_TXDMA(i)); 9232 if (err) 9233 return err; 9234 ldg_rotor++; 9235 if (ldg_rotor == np->num_ldg) 9236 ldg_rotor = 0; 9237 } 9238 9239 return 0; 9240 } 9241 9242 static void niu_ldg_free(struct niu *np) 9243 { 9244 if (np->flags & NIU_FLAGS_MSIX) 9245 pci_disable_msix(np->pdev); 9246 } 9247 9248 static int niu_get_of_props(struct niu *np) 9249 { 9250 #ifdef CONFIG_SPARC64 9251 struct net_device *dev = np->dev; 9252 struct device_node *dp; 9253 const char *phy_type; 9254 const u8 *mac_addr; 9255 const char *model; 9256 int prop_len; 9257 9258 if (np->parent->plat_type == PLAT_TYPE_NIU) 9259 dp = np->op->dev.of_node; 9260 else 9261 dp = pci_device_to_OF_node(np->pdev); 9262 9263 phy_type = of_get_property(dp, "phy-type", NULL); 9264 if (!phy_type) { 9265 netdev_err(dev, "%pOF: OF node lacks phy-type property\n", dp); 9266 return -EINVAL; 9267 } 9268 9269 if (!strcmp(phy_type, "none")) 9270 return -ENODEV; 9271 9272 strcpy(np->vpd.phy_type, phy_type); 9273 9274 if (niu_phy_type_prop_decode(np, np->vpd.phy_type)) { 9275 netdev_err(dev, "%pOF: Illegal phy string [%s]\n", 9276 dp, np->vpd.phy_type); 9277 return -EINVAL; 9278 } 9279 9280 mac_addr = of_get_property(dp, "local-mac-address", &prop_len); 9281 if (!mac_addr) { 9282 netdev_err(dev, "%pOF: OF node lacks local-mac-address property\n", 9283 dp); 9284 return -EINVAL; 9285 } 9286 if (prop_len != dev->addr_len) { 9287 netdev_err(dev, "%pOF: OF MAC address prop len (%d) is wrong\n", 9288 dp, prop_len); 9289 } 9290 eth_hw_addr_set(dev, mac_addr); 9291 if (!is_valid_ether_addr(&dev->dev_addr[0])) { 9292 netdev_err(dev, "%pOF: OF MAC address is invalid\n", dp); 9293 netdev_err(dev, "%pOF: [ %pM ]\n", dp, dev->dev_addr); 9294 return -EINVAL; 9295 } 9296 9297 model = of_get_property(dp, "model", NULL); 9298 9299 if (model) 9300 strcpy(np->vpd.model, model); 9301 9302 if (of_property_read_bool(dp, "hot-swappable-phy")) { 9303 np->flags |= (NIU_FLAGS_10G | NIU_FLAGS_FIBER | 9304 NIU_FLAGS_HOTPLUG_PHY); 9305 } 9306 9307 return 0; 9308 #else 9309 return -EINVAL; 9310 #endif 9311 } 9312 9313 static int niu_get_invariants(struct niu *np) 9314 { 9315 int err, have_props; 9316 u32 offset; 9317 9318 err = niu_get_of_props(np); 9319 if (err == -ENODEV) 9320 return err; 9321 9322 have_props = !err; 9323 9324 err = niu_init_mac_ipp_pcs_base(np); 9325 if (err) 9326 return err; 9327 9328 if (have_props) { 9329 err = niu_get_and_validate_port(np); 9330 if (err) 9331 return err; 9332 9333 } else { 9334 if (np->parent->plat_type == PLAT_TYPE_NIU) 9335 return -EINVAL; 9336 9337 nw64(ESPC_PIO_EN, ESPC_PIO_EN_ENABLE); 9338 offset = niu_pci_vpd_offset(np); 9339 netif_printk(np, probe, KERN_DEBUG, np->dev, 9340 "%s() VPD offset [%08x]\n", __func__, offset); 9341 if (offset) { 9342 err = niu_pci_vpd_fetch(np, offset); 9343 if (err < 0) 9344 return err; 9345 } 9346 nw64(ESPC_PIO_EN, 0); 9347 9348 if (np->flags & NIU_FLAGS_VPD_VALID) { 9349 niu_pci_vpd_validate(np); 9350 err = niu_get_and_validate_port(np); 9351 if (err) 9352 return err; 9353 } 9354 9355 if (!(np->flags & NIU_FLAGS_VPD_VALID)) { 9356 err = niu_get_and_validate_port(np); 9357 if (err) 9358 return err; 9359 err = niu_pci_probe_sprom(np); 9360 if (err) 9361 return err; 9362 } 9363 } 9364 9365 err = niu_probe_ports(np); 9366 if (err) 9367 return err; 9368 9369 niu_ldg_init(np); 9370 9371 niu_classifier_swstate_init(np); 9372 niu_link_config_init(np); 9373 9374 err = niu_determine_phy_disposition(np); 9375 if (!err) 9376 err = niu_init_link(np); 9377 9378 return err; 9379 } 9380 9381 static LIST_HEAD(niu_parent_list); 9382 static DEFINE_MUTEX(niu_parent_lock); 9383 static int niu_parent_index; 9384 9385 static ssize_t show_port_phy(struct device *dev, 9386 struct device_attribute *attr, char *buf) 9387 { 9388 struct platform_device *plat_dev = to_platform_device(dev); 9389 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9390 u32 port_phy = p->port_phy; 9391 char *orig_buf = buf; 9392 int i; 9393 9394 if (port_phy == PORT_PHY_UNKNOWN || 9395 port_phy == PORT_PHY_INVALID) 9396 return 0; 9397 9398 for (i = 0; i < p->num_ports; i++) { 9399 const char *type_str; 9400 int type; 9401 9402 type = phy_decode(port_phy, i); 9403 if (type == PORT_TYPE_10G) 9404 type_str = "10G"; 9405 else 9406 type_str = "1G"; 9407 buf += sprintf(buf, 9408 (i == 0) ? "%s" : " %s", 9409 type_str); 9410 } 9411 buf += sprintf(buf, "\n"); 9412 return buf - orig_buf; 9413 } 9414 9415 static ssize_t show_plat_type(struct device *dev, 9416 struct device_attribute *attr, char *buf) 9417 { 9418 struct platform_device *plat_dev = to_platform_device(dev); 9419 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9420 const char *type_str; 9421 9422 switch (p->plat_type) { 9423 case PLAT_TYPE_ATLAS: 9424 type_str = "atlas"; 9425 break; 9426 case PLAT_TYPE_NIU: 9427 type_str = "niu"; 9428 break; 9429 case PLAT_TYPE_VF_P0: 9430 type_str = "vf_p0"; 9431 break; 9432 case PLAT_TYPE_VF_P1: 9433 type_str = "vf_p1"; 9434 break; 9435 default: 9436 type_str = "unknown"; 9437 break; 9438 } 9439 9440 return sprintf(buf, "%s\n", type_str); 9441 } 9442 9443 static ssize_t __show_chan_per_port(struct device *dev, 9444 struct device_attribute *attr, char *buf, 9445 int rx) 9446 { 9447 struct platform_device *plat_dev = to_platform_device(dev); 9448 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9449 char *orig_buf = buf; 9450 u8 *arr; 9451 int i; 9452 9453 arr = (rx ? p->rxchan_per_port : p->txchan_per_port); 9454 9455 for (i = 0; i < p->num_ports; i++) { 9456 buf += sprintf(buf, 9457 (i == 0) ? "%d" : " %d", 9458 arr[i]); 9459 } 9460 buf += sprintf(buf, "\n"); 9461 9462 return buf - orig_buf; 9463 } 9464 9465 static ssize_t show_rxchan_per_port(struct device *dev, 9466 struct device_attribute *attr, char *buf) 9467 { 9468 return __show_chan_per_port(dev, attr, buf, 1); 9469 } 9470 9471 static ssize_t show_txchan_per_port(struct device *dev, 9472 struct device_attribute *attr, char *buf) 9473 { 9474 return __show_chan_per_port(dev, attr, buf, 1); 9475 } 9476 9477 static ssize_t show_num_ports(struct device *dev, 9478 struct device_attribute *attr, char *buf) 9479 { 9480 struct platform_device *plat_dev = to_platform_device(dev); 9481 struct niu_parent *p = dev_get_platdata(&plat_dev->dev); 9482 9483 return sprintf(buf, "%d\n", p->num_ports); 9484 } 9485 9486 static struct device_attribute niu_parent_attributes[] = { 9487 __ATTR(port_phy, 0444, show_port_phy, NULL), 9488 __ATTR(plat_type, 0444, show_plat_type, NULL), 9489 __ATTR(rxchan_per_port, 0444, show_rxchan_per_port, NULL), 9490 __ATTR(txchan_per_port, 0444, show_txchan_per_port, NULL), 9491 __ATTR(num_ports, 0444, show_num_ports, NULL), 9492 {} 9493 }; 9494 9495 static struct niu_parent *niu_new_parent(struct niu *np, 9496 union niu_parent_id *id, u8 ptype) 9497 { 9498 struct platform_device *plat_dev; 9499 struct niu_parent *p; 9500 int i; 9501 9502 plat_dev = platform_device_register_simple("niu-board", niu_parent_index, 9503 NULL, 0); 9504 if (IS_ERR(plat_dev)) 9505 return NULL; 9506 9507 for (i = 0; niu_parent_attributes[i].attr.name; i++) { 9508 int err = device_create_file(&plat_dev->dev, 9509 &niu_parent_attributes[i]); 9510 if (err) 9511 goto fail_unregister; 9512 } 9513 9514 p = kzalloc_obj(*p); 9515 if (!p) 9516 goto fail_unregister; 9517 9518 p->index = niu_parent_index++; 9519 9520 plat_dev->dev.platform_data = p; 9521 p->plat_dev = plat_dev; 9522 9523 memcpy(&p->id, id, sizeof(*id)); 9524 p->plat_type = ptype; 9525 INIT_LIST_HEAD(&p->list); 9526 atomic_set(&p->refcnt, 0); 9527 list_add(&p->list, &niu_parent_list); 9528 spin_lock_init(&p->lock); 9529 9530 p->rxdma_clock_divider = 7500; 9531 9532 p->tcam_num_entries = NIU_PCI_TCAM_ENTRIES; 9533 if (p->plat_type == PLAT_TYPE_NIU) 9534 p->tcam_num_entries = NIU_NONPCI_TCAM_ENTRIES; 9535 9536 for (i = CLASS_CODE_USER_PROG1; i <= CLASS_CODE_SCTP_IPV6; i++) { 9537 int index = i - CLASS_CODE_USER_PROG1; 9538 9539 p->tcam_key[index] = TCAM_KEY_TSEL; 9540 p->flow_key[index] = (FLOW_KEY_IPSA | 9541 FLOW_KEY_IPDA | 9542 FLOW_KEY_PROTO | 9543 (FLOW_KEY_L4_BYTE12 << 9544 FLOW_KEY_L4_0_SHIFT) | 9545 (FLOW_KEY_L4_BYTE12 << 9546 FLOW_KEY_L4_1_SHIFT)); 9547 } 9548 9549 for (i = 0; i < LDN_MAX + 1; i++) 9550 p->ldg_map[i] = LDG_INVALID; 9551 9552 return p; 9553 9554 fail_unregister: 9555 platform_device_unregister(plat_dev); 9556 return NULL; 9557 } 9558 9559 static struct niu_parent *niu_get_parent(struct niu *np, 9560 union niu_parent_id *id, u8 ptype) 9561 { 9562 struct niu_parent *p, *tmp; 9563 int port = np->port; 9564 9565 mutex_lock(&niu_parent_lock); 9566 p = NULL; 9567 list_for_each_entry(tmp, &niu_parent_list, list) { 9568 if (!memcmp(id, &tmp->id, sizeof(*id))) { 9569 p = tmp; 9570 break; 9571 } 9572 } 9573 if (!p) 9574 p = niu_new_parent(np, id, ptype); 9575 9576 if (p) { 9577 char port_name[8]; 9578 int err; 9579 9580 sprintf(port_name, "port%d", port); 9581 err = sysfs_create_link(&p->plat_dev->dev.kobj, 9582 &np->device->kobj, 9583 port_name); 9584 if (!err) { 9585 p->ports[port] = np; 9586 atomic_inc(&p->refcnt); 9587 } 9588 } 9589 mutex_unlock(&niu_parent_lock); 9590 9591 return p; 9592 } 9593 9594 static void niu_put_parent(struct niu *np) 9595 { 9596 struct niu_parent *p = np->parent; 9597 u8 port = np->port; 9598 char port_name[8]; 9599 9600 BUG_ON(!p || p->ports[port] != np); 9601 9602 netif_printk(np, probe, KERN_DEBUG, np->dev, 9603 "%s() port[%u]\n", __func__, port); 9604 9605 sprintf(port_name, "port%d", port); 9606 9607 mutex_lock(&niu_parent_lock); 9608 9609 sysfs_remove_link(&p->plat_dev->dev.kobj, port_name); 9610 9611 p->ports[port] = NULL; 9612 np->parent = NULL; 9613 9614 if (atomic_dec_and_test(&p->refcnt)) { 9615 list_del(&p->list); 9616 platform_device_unregister(p->plat_dev); 9617 } 9618 9619 mutex_unlock(&niu_parent_lock); 9620 } 9621 9622 static void *niu_pci_alloc_coherent(struct device *dev, size_t size, 9623 u64 *handle, gfp_t flag) 9624 { 9625 dma_addr_t dh; 9626 void *ret; 9627 9628 ret = dma_alloc_coherent(dev, size, &dh, flag); 9629 if (ret) 9630 *handle = dh; 9631 return ret; 9632 } 9633 9634 static void niu_pci_free_coherent(struct device *dev, size_t size, 9635 void *cpu_addr, u64 handle) 9636 { 9637 dma_free_coherent(dev, size, cpu_addr, handle); 9638 } 9639 9640 static u64 niu_pci_map_page(struct device *dev, struct page *page, 9641 unsigned long offset, size_t size, 9642 enum dma_data_direction direction) 9643 { 9644 return dma_map_page(dev, page, offset, size, direction); 9645 } 9646 9647 static void niu_pci_unmap_page(struct device *dev, u64 dma_address, 9648 size_t size, enum dma_data_direction direction) 9649 { 9650 dma_unmap_page(dev, dma_address, size, direction); 9651 } 9652 9653 static u64 niu_pci_map_single(struct device *dev, void *cpu_addr, 9654 size_t size, 9655 enum dma_data_direction direction) 9656 { 9657 return dma_map_single(dev, cpu_addr, size, direction); 9658 } 9659 9660 static void niu_pci_unmap_single(struct device *dev, u64 dma_address, 9661 size_t size, 9662 enum dma_data_direction direction) 9663 { 9664 dma_unmap_single(dev, dma_address, size, direction); 9665 } 9666 9667 static int niu_pci_mapping_error(struct device *dev, u64 addr) 9668 { 9669 return dma_mapping_error(dev, addr); 9670 } 9671 9672 static const struct niu_ops niu_pci_ops = { 9673 .alloc_coherent = niu_pci_alloc_coherent, 9674 .free_coherent = niu_pci_free_coherent, 9675 .map_page = niu_pci_map_page, 9676 .unmap_page = niu_pci_unmap_page, 9677 .map_single = niu_pci_map_single, 9678 .unmap_single = niu_pci_unmap_single, 9679 .mapping_error = niu_pci_mapping_error, 9680 }; 9681 9682 static void niu_driver_version(void) 9683 { 9684 static int niu_version_printed; 9685 9686 if (niu_version_printed++ == 0) 9687 pr_info("%s", version); 9688 } 9689 9690 static struct net_device *niu_alloc_and_init(struct device *gen_dev, 9691 struct pci_dev *pdev, 9692 struct platform_device *op, 9693 const struct niu_ops *ops, u8 port) 9694 { 9695 struct net_device *dev; 9696 struct niu *np; 9697 9698 dev = alloc_etherdev_mq(sizeof(struct niu), NIU_NUM_TXCHAN); 9699 if (!dev) 9700 return NULL; 9701 9702 SET_NETDEV_DEV(dev, gen_dev); 9703 9704 np = netdev_priv(dev); 9705 np->dev = dev; 9706 np->pdev = pdev; 9707 np->op = op; 9708 np->device = gen_dev; 9709 np->ops = ops; 9710 9711 np->msg_enable = niu_debug; 9712 9713 spin_lock_init(&np->lock); 9714 INIT_WORK(&np->reset_task, niu_reset_task); 9715 9716 np->port = port; 9717 9718 return dev; 9719 } 9720 9721 static const struct net_device_ops niu_netdev_ops = { 9722 .ndo_open = niu_open, 9723 .ndo_stop = niu_close, 9724 .ndo_start_xmit = niu_start_xmit, 9725 .ndo_get_stats64 = niu_get_stats, 9726 .ndo_set_rx_mode = niu_set_rx_mode, 9727 .ndo_validate_addr = eth_validate_addr, 9728 .ndo_set_mac_address = niu_set_mac_addr, 9729 .ndo_eth_ioctl = niu_ioctl, 9730 .ndo_tx_timeout = niu_tx_timeout, 9731 .ndo_change_mtu = niu_change_mtu, 9732 }; 9733 9734 static void niu_assign_netdev_ops(struct net_device *dev) 9735 { 9736 dev->netdev_ops = &niu_netdev_ops; 9737 dev->ethtool_ops = &niu_ethtool_ops; 9738 dev->watchdog_timeo = NIU_TX_TIMEOUT; 9739 } 9740 9741 static void niu_device_announce(struct niu *np) 9742 { 9743 struct net_device *dev = np->dev; 9744 9745 pr_info("%s: NIU Ethernet %pM\n", dev->name, dev->dev_addr); 9746 9747 if (np->parent->plat_type == PLAT_TYPE_ATCA_CP3220) { 9748 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9749 dev->name, 9750 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9751 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9752 (np->flags & NIU_FLAGS_FIBER ? "RGMII FIBER" : "SERDES"), 9753 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9754 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9755 np->vpd.phy_type); 9756 } else { 9757 pr_info("%s: Port type[%s] mode[%s:%s] XCVR[%s] phy[%s]\n", 9758 dev->name, 9759 (np->flags & NIU_FLAGS_XMAC ? "XMAC" : "BMAC"), 9760 (np->flags & NIU_FLAGS_10G ? "10G" : "1G"), 9761 (np->flags & NIU_FLAGS_FIBER ? "FIBER" : 9762 (np->flags & NIU_FLAGS_XCVR_SERDES ? "SERDES" : 9763 "COPPER")), 9764 (np->mac_xcvr == MAC_XCVR_MII ? "MII" : 9765 (np->mac_xcvr == MAC_XCVR_PCS ? "PCS" : "XPCS")), 9766 np->vpd.phy_type); 9767 } 9768 } 9769 9770 static void niu_set_basic_features(struct net_device *dev) 9771 { 9772 dev->hw_features = NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_RXHASH; 9773 dev->features |= dev->hw_features | NETIF_F_RXCSUM; 9774 } 9775 9776 static int niu_pci_init_one(struct pci_dev *pdev, 9777 const struct pci_device_id *ent) 9778 { 9779 union niu_parent_id parent_id; 9780 struct net_device *dev; 9781 struct niu *np; 9782 int err; 9783 9784 niu_driver_version(); 9785 9786 err = pci_enable_device(pdev); 9787 if (err) { 9788 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 9789 return err; 9790 } 9791 9792 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) || 9793 !(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) { 9794 dev_err(&pdev->dev, "Cannot find proper PCI device base addresses, aborting\n"); 9795 err = -ENODEV; 9796 goto err_out_disable_pdev; 9797 } 9798 9799 err = pci_request_regions(pdev, DRV_MODULE_NAME); 9800 if (err) { 9801 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 9802 goto err_out_disable_pdev; 9803 } 9804 9805 if (!pci_is_pcie(pdev)) { 9806 dev_err(&pdev->dev, "Cannot find PCI Express capability, aborting\n"); 9807 err = -ENODEV; 9808 goto err_out_free_res; 9809 } 9810 9811 dev = niu_alloc_and_init(&pdev->dev, pdev, NULL, 9812 &niu_pci_ops, PCI_FUNC(pdev->devfn)); 9813 if (!dev) { 9814 err = -ENOMEM; 9815 goto err_out_free_res; 9816 } 9817 np = netdev_priv(dev); 9818 9819 memset(&parent_id, 0, sizeof(parent_id)); 9820 parent_id.pci.domain = pci_domain_nr(pdev->bus); 9821 parent_id.pci.bus = pdev->bus->number; 9822 parent_id.pci.device = PCI_SLOT(pdev->devfn); 9823 9824 np->parent = niu_get_parent(np, &parent_id, 9825 PLAT_TYPE_ATLAS); 9826 if (!np->parent) { 9827 err = -ENOMEM; 9828 goto err_out_free_dev; 9829 } 9830 9831 pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, 9832 PCI_EXP_DEVCTL_NOSNOOP_EN, 9833 PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | 9834 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE | 9835 PCI_EXP_DEVCTL_RELAX_EN); 9836 9837 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44)); 9838 if (!err) 9839 dev->features |= NETIF_F_HIGHDMA; 9840 if (err) { 9841 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); 9842 if (err) { 9843 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 9844 goto err_out_release_parent; 9845 } 9846 } 9847 9848 niu_set_basic_features(dev); 9849 9850 dev->priv_flags |= IFF_UNICAST_FLT; 9851 9852 np->regs = pci_ioremap_bar(pdev, 0); 9853 if (!np->regs) { 9854 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 9855 err = -ENOMEM; 9856 goto err_out_release_parent; 9857 } 9858 9859 pci_set_master(pdev); 9860 pci_save_state(pdev); 9861 9862 dev->irq = pdev->irq; 9863 9864 /* MTU range: 68 - 9216 */ 9865 dev->min_mtu = ETH_MIN_MTU; 9866 dev->max_mtu = NIU_MAX_MTU; 9867 9868 niu_assign_netdev_ops(dev); 9869 9870 err = niu_get_invariants(np); 9871 if (err) { 9872 if (err != -ENODEV) 9873 dev_err(&pdev->dev, "Problem fetching invariants of chip, aborting\n"); 9874 goto err_out_iounmap; 9875 } 9876 9877 err = register_netdev(dev); 9878 if (err) { 9879 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); 9880 goto err_out_iounmap; 9881 } 9882 9883 pci_set_drvdata(pdev, dev); 9884 9885 niu_device_announce(np); 9886 9887 return 0; 9888 9889 err_out_iounmap: 9890 if (np->regs) { 9891 iounmap(np->regs); 9892 np->regs = NULL; 9893 } 9894 9895 err_out_release_parent: 9896 niu_put_parent(np); 9897 9898 err_out_free_dev: 9899 free_netdev(dev); 9900 9901 err_out_free_res: 9902 pci_release_regions(pdev); 9903 9904 err_out_disable_pdev: 9905 pci_disable_device(pdev); 9906 9907 return err; 9908 } 9909 9910 static void niu_pci_remove_one(struct pci_dev *pdev) 9911 { 9912 struct net_device *dev = pci_get_drvdata(pdev); 9913 9914 if (dev) { 9915 struct niu *np = netdev_priv(dev); 9916 9917 unregister_netdev(dev); 9918 if (np->regs) { 9919 iounmap(np->regs); 9920 np->regs = NULL; 9921 } 9922 9923 niu_ldg_free(np); 9924 9925 niu_put_parent(np); 9926 9927 free_netdev(dev); 9928 pci_release_regions(pdev); 9929 pci_disable_device(pdev); 9930 } 9931 } 9932 9933 static int __maybe_unused niu_suspend(struct device *dev_d) 9934 { 9935 struct net_device *dev = dev_get_drvdata(dev_d); 9936 struct niu *np = netdev_priv(dev); 9937 unsigned long flags; 9938 9939 if (!netif_running(dev)) 9940 return 0; 9941 9942 flush_work(&np->reset_task); 9943 niu_netif_stop(np); 9944 9945 timer_delete_sync(&np->timer); 9946 9947 spin_lock_irqsave(&np->lock, flags); 9948 niu_enable_interrupts(np, 0); 9949 spin_unlock_irqrestore(&np->lock, flags); 9950 9951 netif_device_detach(dev); 9952 9953 spin_lock_irqsave(&np->lock, flags); 9954 niu_stop_hw(np); 9955 spin_unlock_irqrestore(&np->lock, flags); 9956 9957 return 0; 9958 } 9959 9960 static int __maybe_unused niu_resume(struct device *dev_d) 9961 { 9962 struct net_device *dev = dev_get_drvdata(dev_d); 9963 struct niu *np = netdev_priv(dev); 9964 unsigned long flags; 9965 int err; 9966 9967 if (!netif_running(dev)) 9968 return 0; 9969 9970 netif_device_attach(dev); 9971 9972 spin_lock_irqsave(&np->lock, flags); 9973 9974 netdev_lock(dev); 9975 err = niu_init_hw(np); 9976 if (!err) { 9977 np->timer.expires = jiffies + HZ; 9978 add_timer(&np->timer); 9979 niu_netif_start(np); 9980 } 9981 9982 spin_unlock_irqrestore(&np->lock, flags); 9983 netdev_unlock(dev); 9984 9985 return err; 9986 } 9987 9988 static SIMPLE_DEV_PM_OPS(niu_pm_ops, niu_suspend, niu_resume); 9989 9990 static struct pci_driver niu_pci_driver = { 9991 .name = DRV_MODULE_NAME, 9992 .id_table = niu_pci_tbl, 9993 .probe = niu_pci_init_one, 9994 .remove = niu_pci_remove_one, 9995 .driver.pm = &niu_pm_ops, 9996 }; 9997 9998 #ifdef CONFIG_SPARC64 9999 static void *niu_phys_alloc_coherent(struct device *dev, size_t size, 10000 u64 *dma_addr, gfp_t flag) 10001 { 10002 unsigned long order = get_order(size); 10003 unsigned long page = __get_free_pages(flag, order); 10004 10005 if (page == 0UL) 10006 return NULL; 10007 memset((char *)page, 0, PAGE_SIZE << order); 10008 *dma_addr = __pa(page); 10009 10010 return (void *) page; 10011 } 10012 10013 static void niu_phys_free_coherent(struct device *dev, size_t size, 10014 void *cpu_addr, u64 handle) 10015 { 10016 unsigned long order = get_order(size); 10017 10018 free_pages((unsigned long) cpu_addr, order); 10019 } 10020 10021 static u64 niu_phys_map_page(struct device *dev, struct page *page, 10022 unsigned long offset, size_t size, 10023 enum dma_data_direction direction) 10024 { 10025 return page_to_phys(page) + offset; 10026 } 10027 10028 static void niu_phys_unmap_page(struct device *dev, u64 dma_address, 10029 size_t size, enum dma_data_direction direction) 10030 { 10031 /* Nothing to do. */ 10032 } 10033 10034 static u64 niu_phys_map_single(struct device *dev, void *cpu_addr, 10035 size_t size, 10036 enum dma_data_direction direction) 10037 { 10038 return __pa(cpu_addr); 10039 } 10040 10041 static void niu_phys_unmap_single(struct device *dev, u64 dma_address, 10042 size_t size, 10043 enum dma_data_direction direction) 10044 { 10045 /* Nothing to do. */ 10046 } 10047 10048 static int niu_phys_mapping_error(struct device *dev, u64 dma_address) 10049 { 10050 return false; 10051 } 10052 10053 static const struct niu_ops niu_phys_ops = { 10054 .alloc_coherent = niu_phys_alloc_coherent, 10055 .free_coherent = niu_phys_free_coherent, 10056 .map_page = niu_phys_map_page, 10057 .unmap_page = niu_phys_unmap_page, 10058 .map_single = niu_phys_map_single, 10059 .unmap_single = niu_phys_unmap_single, 10060 .mapping_error = niu_phys_mapping_error, 10061 }; 10062 10063 static int niu_of_probe(struct platform_device *op) 10064 { 10065 union niu_parent_id parent_id; 10066 struct net_device *dev; 10067 struct niu *np; 10068 const u32 *reg; 10069 int err; 10070 10071 niu_driver_version(); 10072 10073 reg = of_get_property(op->dev.of_node, "reg", NULL); 10074 if (!reg) { 10075 dev_err(&op->dev, "%pOF: No 'reg' property, aborting\n", 10076 op->dev.of_node); 10077 return -ENODEV; 10078 } 10079 10080 dev = niu_alloc_and_init(&op->dev, NULL, op, 10081 &niu_phys_ops, reg[0] & 0x1); 10082 if (!dev) { 10083 err = -ENOMEM; 10084 goto err_out; 10085 } 10086 np = netdev_priv(dev); 10087 10088 memset(&parent_id, 0, sizeof(parent_id)); 10089 parent_id.of = of_get_parent(op->dev.of_node); 10090 10091 np->parent = niu_get_parent(np, &parent_id, 10092 PLAT_TYPE_NIU); 10093 if (!np->parent) { 10094 err = -ENOMEM; 10095 goto err_out_free_dev; 10096 } 10097 10098 niu_set_basic_features(dev); 10099 10100 np->regs = of_ioremap(&op->resource[1], 0, 10101 resource_size(&op->resource[1]), 10102 "niu regs"); 10103 if (!np->regs) { 10104 dev_err(&op->dev, "Cannot map device registers, aborting\n"); 10105 err = -ENOMEM; 10106 goto err_out_release_parent; 10107 } 10108 10109 np->vir_regs_1 = of_ioremap(&op->resource[2], 0, 10110 resource_size(&op->resource[2]), 10111 "niu vregs-1"); 10112 if (!np->vir_regs_1) { 10113 dev_err(&op->dev, "Cannot map device vir registers 1, aborting\n"); 10114 err = -ENOMEM; 10115 goto err_out_iounmap; 10116 } 10117 10118 np->vir_regs_2 = of_ioremap(&op->resource[3], 0, 10119 resource_size(&op->resource[3]), 10120 "niu vregs-2"); 10121 if (!np->vir_regs_2) { 10122 dev_err(&op->dev, "Cannot map device vir registers 2, aborting\n"); 10123 err = -ENOMEM; 10124 goto err_out_iounmap; 10125 } 10126 10127 niu_assign_netdev_ops(dev); 10128 10129 err = niu_get_invariants(np); 10130 if (err) { 10131 if (err != -ENODEV) 10132 dev_err(&op->dev, "Problem fetching invariants of chip, aborting\n"); 10133 goto err_out_iounmap; 10134 } 10135 10136 err = register_netdev(dev); 10137 if (err) { 10138 dev_err(&op->dev, "Cannot register net device, aborting\n"); 10139 goto err_out_iounmap; 10140 } 10141 10142 platform_set_drvdata(op, dev); 10143 10144 niu_device_announce(np); 10145 10146 return 0; 10147 10148 err_out_iounmap: 10149 if (np->vir_regs_1) { 10150 of_iounmap(&op->resource[2], np->vir_regs_1, 10151 resource_size(&op->resource[2])); 10152 np->vir_regs_1 = NULL; 10153 } 10154 10155 if (np->vir_regs_2) { 10156 of_iounmap(&op->resource[3], np->vir_regs_2, 10157 resource_size(&op->resource[3])); 10158 np->vir_regs_2 = NULL; 10159 } 10160 10161 if (np->regs) { 10162 of_iounmap(&op->resource[1], np->regs, 10163 resource_size(&op->resource[1])); 10164 np->regs = NULL; 10165 } 10166 10167 err_out_release_parent: 10168 niu_put_parent(np); 10169 10170 err_out_free_dev: 10171 free_netdev(dev); 10172 10173 err_out: 10174 return err; 10175 } 10176 10177 static void niu_of_remove(struct platform_device *op) 10178 { 10179 struct net_device *dev = platform_get_drvdata(op); 10180 10181 if (dev) { 10182 struct niu *np = netdev_priv(dev); 10183 10184 unregister_netdev(dev); 10185 10186 if (np->vir_regs_1) { 10187 of_iounmap(&op->resource[2], np->vir_regs_1, 10188 resource_size(&op->resource[2])); 10189 np->vir_regs_1 = NULL; 10190 } 10191 10192 if (np->vir_regs_2) { 10193 of_iounmap(&op->resource[3], np->vir_regs_2, 10194 resource_size(&op->resource[3])); 10195 np->vir_regs_2 = NULL; 10196 } 10197 10198 if (np->regs) { 10199 of_iounmap(&op->resource[1], np->regs, 10200 resource_size(&op->resource[1])); 10201 np->regs = NULL; 10202 } 10203 10204 niu_ldg_free(np); 10205 10206 niu_put_parent(np); 10207 10208 free_netdev(dev); 10209 } 10210 } 10211 10212 static const struct of_device_id niu_match[] = { 10213 { 10214 .name = "network", 10215 .compatible = "SUNW,niusl", 10216 }, 10217 {}, 10218 }; 10219 MODULE_DEVICE_TABLE(of, niu_match); 10220 10221 static struct platform_driver niu_of_driver = { 10222 .driver = { 10223 .name = "niu", 10224 .of_match_table = niu_match, 10225 }, 10226 .probe = niu_of_probe, 10227 .remove = niu_of_remove, 10228 }; 10229 10230 #endif /* CONFIG_SPARC64 */ 10231 10232 static int __init niu_init(void) 10233 { 10234 int err = 0; 10235 10236 BUILD_BUG_ON(PAGE_SIZE < 4 * 1024); 10237 10238 BUILD_BUG_ON(offsetof(struct page, mapping) != 10239 offsetof(union niu_page, next)); 10240 10241 niu_debug = netif_msg_init(debug, NIU_MSG_DEFAULT); 10242 10243 #ifdef CONFIG_SPARC64 10244 err = platform_driver_register(&niu_of_driver); 10245 #endif 10246 10247 if (!err) { 10248 err = pci_register_driver(&niu_pci_driver); 10249 #ifdef CONFIG_SPARC64 10250 if (err) 10251 platform_driver_unregister(&niu_of_driver); 10252 #endif 10253 } 10254 10255 return err; 10256 } 10257 10258 static void __exit niu_exit(void) 10259 { 10260 pci_unregister_driver(&niu_pci_driver); 10261 #ifdef CONFIG_SPARC64 10262 platform_driver_unregister(&niu_of_driver); 10263 #endif 10264 } 10265 10266 module_init(niu_init); 10267 module_exit(niu_exit); 10268