1 // SPDX-License-Identifier: GPL-2.0+ 2 /* cassini.c: Sun Microsystems Cassini(+) ethernet driver. 3 * 4 * Copyright (C) 2004 Sun Microsystems Inc. 5 * Copyright (C) 2003 Adrian Sun (asun@darksunrising.com) 6 * 7 * This driver uses the sungem driver (c) David Miller 8 * (davem@redhat.com) as its basis. 9 * 10 * The cassini chip has a number of features that distinguish it from 11 * the gem chip: 12 * 4 transmit descriptor rings that are used for either QoS (VLAN) or 13 * load balancing (non-VLAN mode) 14 * batching of multiple packets 15 * multiple CPU dispatching 16 * page-based RX descriptor engine with separate completion rings 17 * Gigabit support (GMII and PCS interface) 18 * MIF link up/down detection works 19 * 20 * RX is handled by page sized buffers that are attached as fragments to 21 * the skb. here's what's done: 22 * -- driver allocates pages at a time and keeps reference counts 23 * on them. 24 * -- the upper protocol layers assume that the header is in the skb 25 * itself. as a result, cassini will copy a small amount (64 bytes) 26 * to make them happy. 27 * -- driver appends the rest of the data pages as frags to skbuffs 28 * and increments the reference count 29 * -- on page reclamation, the driver swaps the page with a spare page. 30 * if that page is still in use, it frees its reference to that page, 31 * and allocates a new page for use. otherwise, it just recycles the 32 * the page. 33 * 34 * NOTE: cassini can parse the header. however, it's not worth it 35 * as long as the network stack requires a header copy. 36 * 37 * TX has 4 queues. currently these queues are used in a round-robin 38 * fashion for load balancing. They can also be used for QoS. for that 39 * to work, however, QoS information needs to be exposed down to the driver 40 * level so that subqueues get targeted to particular transmit rings. 41 * alternatively, the queues can be configured via use of the all-purpose 42 * ioctl. 43 * 44 * RX DATA: the rx completion ring has all the info, but the rx desc 45 * ring has all of the data. RX can conceivably come in under multiple 46 * interrupts, but the INT# assignment needs to be set up properly by 47 * the BIOS and conveyed to the driver. PCI BIOSes don't know how to do 48 * that. also, the two descriptor rings are designed to distinguish between 49 * encrypted and non-encrypted packets, but we use them for buffering 50 * instead. 51 * 52 * by default, the selective clear mask is set up to process rx packets. 53 */ 54 55 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 56 57 #include <linux/module.h> 58 #include <linux/kernel.h> 59 #include <linux/types.h> 60 #include <linux/compiler.h> 61 #include <linux/slab.h> 62 #include <linux/delay.h> 63 #include <linux/init.h> 64 #include <linux/interrupt.h> 65 #include <linux/vmalloc.h> 66 #include <linux/ioport.h> 67 #include <linux/pci.h> 68 #include <linux/mm.h> 69 #include <linux/highmem.h> 70 #include <linux/list.h> 71 #include <linux/dma-mapping.h> 72 73 #include <linux/netdevice.h> 74 #include <linux/etherdevice.h> 75 #include <linux/skbuff.h> 76 #include <linux/ethtool.h> 77 #include <linux/crc32.h> 78 #include <linux/random.h> 79 #include <linux/mii.h> 80 #include <linux/ip.h> 81 #include <linux/tcp.h> 82 #include <linux/mutex.h> 83 #include <linux/firmware.h> 84 85 #include <net/checksum.h> 86 87 #include <linux/atomic.h> 88 #include <asm/io.h> 89 #include <asm/byteorder.h> 90 #include <linux/uaccess.h> 91 #include <linux/jiffies.h> 92 93 #define cas_page_map(x) kmap_atomic((x)) 94 #define cas_page_unmap(x) kunmap_atomic((x)) 95 #define CAS_NCPUS num_online_cpus() 96 97 #define cas_skb_release(x) netif_rx(x) 98 99 /* select which firmware to use */ 100 #define USE_HP_WORKAROUND 101 #define HP_WORKAROUND_DEFAULT /* select which firmware to use as default */ 102 #define CAS_HP_ALT_FIRMWARE cas_prog_null /* alternate firmware */ 103 104 #include "cassini.h" 105 106 #define USE_TX_COMPWB /* use completion writeback registers */ 107 #define USE_CSMA_CD_PROTO /* standard CSMA/CD */ 108 #define USE_RX_BLANK /* hw interrupt mitigation */ 109 #undef USE_ENTROPY_DEV /* don't test for entropy device */ 110 111 /* NOTE: these aren't useable unless PCI interrupts can be assigned. 112 * also, we need to make cp->lock finer-grained. 113 */ 114 #undef USE_PCI_INTB 115 #undef USE_PCI_INTC 116 #undef USE_PCI_INTD 117 #undef USE_QOS 118 119 #undef USE_VPD_DEBUG /* debug vpd information if defined */ 120 121 /* rx processing options */ 122 #define USE_PAGE_ORDER /* specify to allocate large rx pages */ 123 #define RX_DONT_BATCH 0 /* if 1, don't batch flows */ 124 #define RX_COPY_ALWAYS 0 /* if 0, use frags */ 125 #define RX_COPY_MIN 64 /* copy a little to make upper layers happy */ 126 #undef RX_COUNT_BUFFERS /* define to calculate RX buffer stats */ 127 128 #define DRV_MODULE_NAME "cassini" 129 #define DRV_MODULE_VERSION "1.6" 130 #define DRV_MODULE_RELDATE "21 May 2008" 131 132 #define CAS_DEF_MSG_ENABLE \ 133 (NETIF_MSG_DRV | \ 134 NETIF_MSG_PROBE | \ 135 NETIF_MSG_LINK | \ 136 NETIF_MSG_TIMER | \ 137 NETIF_MSG_IFDOWN | \ 138 NETIF_MSG_IFUP | \ 139 NETIF_MSG_RX_ERR | \ 140 NETIF_MSG_TX_ERR) 141 142 /* length of time before we decide the hardware is borked, 143 * and dev->tx_timeout() should be called to fix the problem 144 */ 145 #define CAS_TX_TIMEOUT (HZ) 146 #define CAS_LINK_TIMEOUT (22*HZ/10) 147 #define CAS_LINK_FAST_TIMEOUT (1) 148 149 /* timeout values for state changing. these specify the number 150 * of 10us delays to be used before giving up. 151 */ 152 #define STOP_TRIES_PHY 1000 153 #define STOP_TRIES 5000 154 155 /* specify a minimum frame size to deal with some fifo issues 156 * max mtu == 2 * page size - ethernet header - 64 - swivel = 157 * 2 * page_size - 0x50 158 */ 159 #define CAS_MIN_FRAME 97 160 #define CAS_1000MB_MIN_FRAME 255 161 #define CAS_MIN_MTU 60 162 #define CAS_MAX_MTU min(((cp->page_size << 1) - 0x50), 9000) 163 164 #if 1 165 /* 166 * Eliminate these and use separate atomic counters for each, to 167 * avoid a race condition. 168 */ 169 #else 170 #define CAS_RESET_MTU 1 171 #define CAS_RESET_ALL 2 172 #define CAS_RESET_SPARE 3 173 #endif 174 175 static char version[] = 176 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n"; 177 178 static int cassini_debug = -1; /* -1 == use CAS_DEF_MSG_ENABLE as value */ 179 static int link_mode; 180 181 MODULE_AUTHOR("Adrian Sun (asun@darksunrising.com)"); 182 MODULE_DESCRIPTION("Sun Cassini(+) ethernet driver"); 183 MODULE_LICENSE("GPL"); 184 MODULE_FIRMWARE("sun/cassini.bin"); 185 module_param(cassini_debug, int, 0); 186 MODULE_PARM_DESC(cassini_debug, "Cassini bitmapped debugging message enable value"); 187 module_param(link_mode, int, 0); 188 MODULE_PARM_DESC(link_mode, "default link mode"); 189 190 /* 191 * Work around for a PCS bug in which the link goes down due to the chip 192 * being confused and never showing a link status of "up." 193 */ 194 #define DEFAULT_LINKDOWN_TIMEOUT 5 195 /* 196 * Value in seconds, for user input. 197 */ 198 static int linkdown_timeout = DEFAULT_LINKDOWN_TIMEOUT; 199 module_param(linkdown_timeout, int, 0); 200 MODULE_PARM_DESC(linkdown_timeout, 201 "min reset interval in sec. for PCS linkdown issue; disabled if not positive"); 202 203 /* 204 * value in 'ticks' (units used by jiffies). Set when we init the 205 * module because 'HZ' in actually a function call on some flavors of 206 * Linux. This will default to DEFAULT_LINKDOWN_TIMEOUT * HZ. 207 */ 208 static int link_transition_timeout; 209 210 211 212 static u16 link_modes[] = { 213 BMCR_ANENABLE, /* 0 : autoneg */ 214 0, /* 1 : 10bt half duplex */ 215 BMCR_SPEED100, /* 2 : 100bt half duplex */ 216 BMCR_FULLDPLX, /* 3 : 10bt full duplex */ 217 BMCR_SPEED100|BMCR_FULLDPLX, /* 4 : 100bt full duplex */ 218 CAS_BMCR_SPEED1000|BMCR_FULLDPLX /* 5 : 1000bt full duplex */ 219 }; 220 221 static const struct pci_device_id cas_pci_tbl[] = { 222 { PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_CASSINI, 223 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 224 { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_SATURN, 225 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL }, 226 { 0, } 227 }; 228 229 MODULE_DEVICE_TABLE(pci, cas_pci_tbl); 230 231 static void cas_set_link_modes(struct cas *cp); 232 233 static inline void cas_lock_tx(struct cas *cp) 234 { 235 int i; 236 237 for (i = 0; i < N_TX_RINGS; i++) 238 spin_lock_nested(&cp->tx_lock[i], i); 239 } 240 241 /* WTZ: QA was finding deadlock problems with the previous 242 * versions after long test runs with multiple cards per machine. 243 * See if replacing cas_lock_all with safer versions helps. The 244 * symptoms QA is reporting match those we'd expect if interrupts 245 * aren't being properly restored, and we fixed a previous deadlock 246 * with similar symptoms by using save/restore versions in other 247 * places. 248 */ 249 #define cas_lock_all_save(cp, flags) \ 250 do { \ 251 struct cas *xxxcp = (cp); \ 252 spin_lock_irqsave(&xxxcp->lock, flags); \ 253 cas_lock_tx(xxxcp); \ 254 } while (0) 255 256 static inline void cas_unlock_tx(struct cas *cp) 257 { 258 int i; 259 260 for (i = N_TX_RINGS; i > 0; i--) 261 spin_unlock(&cp->tx_lock[i - 1]); 262 } 263 264 #define cas_unlock_all_restore(cp, flags) \ 265 do { \ 266 struct cas *xxxcp = (cp); \ 267 cas_unlock_tx(xxxcp); \ 268 spin_unlock_irqrestore(&xxxcp->lock, flags); \ 269 } while (0) 270 271 static void cas_disable_irq(struct cas *cp, const int ring) 272 { 273 /* Make sure we won't get any more interrupts */ 274 if (ring == 0) { 275 writel(0xFFFFFFFF, cp->regs + REG_INTR_MASK); 276 return; 277 } 278 279 /* disable completion interrupts and selectively mask */ 280 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 281 switch (ring) { 282 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 283 #ifdef USE_PCI_INTB 284 case 1: 285 #endif 286 #ifdef USE_PCI_INTC 287 case 2: 288 #endif 289 #ifdef USE_PCI_INTD 290 case 3: 291 #endif 292 writel(INTRN_MASK_CLEAR_ALL | INTRN_MASK_RX_EN, 293 cp->regs + REG_PLUS_INTRN_MASK(ring)); 294 break; 295 #endif 296 default: 297 writel(INTRN_MASK_CLEAR_ALL, cp->regs + 298 REG_PLUS_INTRN_MASK(ring)); 299 break; 300 } 301 } 302 } 303 304 static inline void cas_mask_intr(struct cas *cp) 305 { 306 int i; 307 308 for (i = 0; i < N_RX_COMP_RINGS; i++) 309 cas_disable_irq(cp, i); 310 } 311 312 static void cas_enable_irq(struct cas *cp, const int ring) 313 { 314 if (ring == 0) { /* all but TX_DONE */ 315 writel(INTR_TX_DONE, cp->regs + REG_INTR_MASK); 316 return; 317 } 318 319 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 320 switch (ring) { 321 #if defined (USE_PCI_INTB) || defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 322 #ifdef USE_PCI_INTB 323 case 1: 324 #endif 325 #ifdef USE_PCI_INTC 326 case 2: 327 #endif 328 #ifdef USE_PCI_INTD 329 case 3: 330 #endif 331 writel(INTRN_MASK_RX_EN, cp->regs + 332 REG_PLUS_INTRN_MASK(ring)); 333 break; 334 #endif 335 default: 336 break; 337 } 338 } 339 } 340 341 static inline void cas_unmask_intr(struct cas *cp) 342 { 343 int i; 344 345 for (i = 0; i < N_RX_COMP_RINGS; i++) 346 cas_enable_irq(cp, i); 347 } 348 349 static inline void cas_entropy_gather(struct cas *cp) 350 { 351 #ifdef USE_ENTROPY_DEV 352 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) 353 return; 354 355 batch_entropy_store(readl(cp->regs + REG_ENTROPY_IV), 356 readl(cp->regs + REG_ENTROPY_IV), 357 sizeof(uint64_t)*8); 358 #endif 359 } 360 361 static inline void cas_entropy_reset(struct cas *cp) 362 { 363 #ifdef USE_ENTROPY_DEV 364 if ((cp->cas_flags & CAS_FLAG_ENTROPY_DEV) == 0) 365 return; 366 367 writel(BIM_LOCAL_DEV_PAD | BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_EXT, 368 cp->regs + REG_BIM_LOCAL_DEV_EN); 369 writeb(ENTROPY_RESET_STC_MODE, cp->regs + REG_ENTROPY_RESET); 370 writeb(0x55, cp->regs + REG_ENTROPY_RAND_REG); 371 372 /* if we read back 0x0, we don't have an entropy device */ 373 if (readb(cp->regs + REG_ENTROPY_RAND_REG) == 0) 374 cp->cas_flags &= ~CAS_FLAG_ENTROPY_DEV; 375 #endif 376 } 377 378 /* access to the phy. the following assumes that we've initialized the MIF to 379 * be in frame rather than bit-bang mode 380 */ 381 static u16 cas_phy_read(struct cas *cp, int reg) 382 { 383 u32 cmd; 384 int limit = STOP_TRIES_PHY; 385 386 cmd = MIF_FRAME_ST | MIF_FRAME_OP_READ; 387 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); 388 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); 389 cmd |= MIF_FRAME_TURN_AROUND_MSB; 390 writel(cmd, cp->regs + REG_MIF_FRAME); 391 392 /* poll for completion */ 393 while (limit-- > 0) { 394 udelay(10); 395 cmd = readl(cp->regs + REG_MIF_FRAME); 396 if (cmd & MIF_FRAME_TURN_AROUND_LSB) 397 return cmd & MIF_FRAME_DATA_MASK; 398 } 399 return 0xFFFF; /* -1 */ 400 } 401 402 static int cas_phy_write(struct cas *cp, int reg, u16 val) 403 { 404 int limit = STOP_TRIES_PHY; 405 u32 cmd; 406 407 cmd = MIF_FRAME_ST | MIF_FRAME_OP_WRITE; 408 cmd |= CAS_BASE(MIF_FRAME_PHY_ADDR, cp->phy_addr); 409 cmd |= CAS_BASE(MIF_FRAME_REG_ADDR, reg); 410 cmd |= MIF_FRAME_TURN_AROUND_MSB; 411 cmd |= val & MIF_FRAME_DATA_MASK; 412 writel(cmd, cp->regs + REG_MIF_FRAME); 413 414 /* poll for completion */ 415 while (limit-- > 0) { 416 udelay(10); 417 cmd = readl(cp->regs + REG_MIF_FRAME); 418 if (cmd & MIF_FRAME_TURN_AROUND_LSB) 419 return 0; 420 } 421 return -1; 422 } 423 424 static void cas_phy_powerup(struct cas *cp) 425 { 426 u16 ctl = cas_phy_read(cp, MII_BMCR); 427 428 if ((ctl & BMCR_PDOWN) == 0) 429 return; 430 ctl &= ~BMCR_PDOWN; 431 cas_phy_write(cp, MII_BMCR, ctl); 432 } 433 434 static void cas_phy_powerdown(struct cas *cp) 435 { 436 u16 ctl = cas_phy_read(cp, MII_BMCR); 437 438 if (ctl & BMCR_PDOWN) 439 return; 440 ctl |= BMCR_PDOWN; 441 cas_phy_write(cp, MII_BMCR, ctl); 442 } 443 444 /* cp->lock held. note: the last put_page will free the buffer */ 445 static int cas_page_free(struct cas *cp, cas_page_t *page) 446 { 447 dma_unmap_page(&cp->pdev->dev, page->dma_addr, cp->page_size, 448 DMA_FROM_DEVICE); 449 __free_pages(page->buffer, cp->page_order); 450 kfree(page); 451 return 0; 452 } 453 454 #ifdef RX_COUNT_BUFFERS 455 #define RX_USED_ADD(x, y) ((x)->used += (y)) 456 #define RX_USED_SET(x, y) ((x)->used = (y)) 457 #else 458 #define RX_USED_ADD(x, y) do { } while(0) 459 #define RX_USED_SET(x, y) do { } while(0) 460 #endif 461 462 /* local page allocation routines for the receive buffers. jumbo pages 463 * require at least 8K contiguous and 8K aligned buffers. 464 */ 465 static cas_page_t *cas_page_alloc(struct cas *cp, const gfp_t flags) 466 { 467 cas_page_t *page; 468 469 page = kmalloc(sizeof(cas_page_t), flags); 470 if (!page) 471 return NULL; 472 473 INIT_LIST_HEAD(&page->list); 474 RX_USED_SET(page, 0); 475 page->buffer = alloc_pages(flags, cp->page_order); 476 if (!page->buffer) 477 goto page_err; 478 page->dma_addr = dma_map_page(&cp->pdev->dev, page->buffer, 0, 479 cp->page_size, DMA_FROM_DEVICE); 480 return page; 481 482 page_err: 483 kfree(page); 484 return NULL; 485 } 486 487 /* initialize spare pool of rx buffers, but allocate during the open */ 488 static void cas_spare_init(struct cas *cp) 489 { 490 spin_lock(&cp->rx_inuse_lock); 491 INIT_LIST_HEAD(&cp->rx_inuse_list); 492 spin_unlock(&cp->rx_inuse_lock); 493 494 spin_lock(&cp->rx_spare_lock); 495 INIT_LIST_HEAD(&cp->rx_spare_list); 496 cp->rx_spares_needed = RX_SPARE_COUNT; 497 spin_unlock(&cp->rx_spare_lock); 498 } 499 500 /* used on close. free all the spare buffers. */ 501 static void cas_spare_free(struct cas *cp) 502 { 503 struct list_head list, *elem, *tmp; 504 505 /* free spare buffers */ 506 INIT_LIST_HEAD(&list); 507 spin_lock(&cp->rx_spare_lock); 508 list_splice_init(&cp->rx_spare_list, &list); 509 spin_unlock(&cp->rx_spare_lock); 510 list_for_each_safe(elem, tmp, &list) { 511 cas_page_free(cp, list_entry(elem, cas_page_t, list)); 512 } 513 514 INIT_LIST_HEAD(&list); 515 #if 1 516 /* 517 * Looks like Adrian had protected this with a different 518 * lock than used everywhere else to manipulate this list. 519 */ 520 spin_lock(&cp->rx_inuse_lock); 521 list_splice_init(&cp->rx_inuse_list, &list); 522 spin_unlock(&cp->rx_inuse_lock); 523 #else 524 spin_lock(&cp->rx_spare_lock); 525 list_splice_init(&cp->rx_inuse_list, &list); 526 spin_unlock(&cp->rx_spare_lock); 527 #endif 528 list_for_each_safe(elem, tmp, &list) { 529 cas_page_free(cp, list_entry(elem, cas_page_t, list)); 530 } 531 } 532 533 /* replenish spares if needed */ 534 static void cas_spare_recover(struct cas *cp, const gfp_t flags) 535 { 536 struct list_head list, *elem, *tmp; 537 int needed, i; 538 539 /* check inuse list. if we don't need any more free buffers, 540 * just free it 541 */ 542 543 /* make a local copy of the list */ 544 INIT_LIST_HEAD(&list); 545 spin_lock(&cp->rx_inuse_lock); 546 list_splice_init(&cp->rx_inuse_list, &list); 547 spin_unlock(&cp->rx_inuse_lock); 548 549 list_for_each_safe(elem, tmp, &list) { 550 cas_page_t *page = list_entry(elem, cas_page_t, list); 551 552 /* 553 * With the lockless pagecache, cassini buffering scheme gets 554 * slightly less accurate: we might find that a page has an 555 * elevated reference count here, due to a speculative ref, 556 * and skip it as in-use. Ideally we would be able to reclaim 557 * it. However this would be such a rare case, it doesn't 558 * matter too much as we should pick it up the next time round. 559 * 560 * Importantly, if we find that the page has a refcount of 1 561 * here (our refcount), then we know it is definitely not inuse 562 * so we can reuse it. 563 */ 564 if (page_count(page->buffer) > 1) 565 continue; 566 567 list_del(elem); 568 spin_lock(&cp->rx_spare_lock); 569 if (cp->rx_spares_needed > 0) { 570 list_add(elem, &cp->rx_spare_list); 571 cp->rx_spares_needed--; 572 spin_unlock(&cp->rx_spare_lock); 573 } else { 574 spin_unlock(&cp->rx_spare_lock); 575 cas_page_free(cp, page); 576 } 577 } 578 579 /* put any inuse buffers back on the list */ 580 if (!list_empty(&list)) { 581 spin_lock(&cp->rx_inuse_lock); 582 list_splice(&list, &cp->rx_inuse_list); 583 spin_unlock(&cp->rx_inuse_lock); 584 } 585 586 spin_lock(&cp->rx_spare_lock); 587 needed = cp->rx_spares_needed; 588 spin_unlock(&cp->rx_spare_lock); 589 if (!needed) 590 return; 591 592 /* we still need spares, so try to allocate some */ 593 INIT_LIST_HEAD(&list); 594 i = 0; 595 while (i < needed) { 596 cas_page_t *spare = cas_page_alloc(cp, flags); 597 if (!spare) 598 break; 599 list_add(&spare->list, &list); 600 i++; 601 } 602 603 spin_lock(&cp->rx_spare_lock); 604 list_splice(&list, &cp->rx_spare_list); 605 cp->rx_spares_needed -= i; 606 spin_unlock(&cp->rx_spare_lock); 607 } 608 609 /* pull a page from the list. */ 610 static cas_page_t *cas_page_dequeue(struct cas *cp) 611 { 612 struct list_head *entry; 613 int recover; 614 615 spin_lock(&cp->rx_spare_lock); 616 if (list_empty(&cp->rx_spare_list)) { 617 /* try to do a quick recovery */ 618 spin_unlock(&cp->rx_spare_lock); 619 cas_spare_recover(cp, GFP_ATOMIC); 620 spin_lock(&cp->rx_spare_lock); 621 if (list_empty(&cp->rx_spare_list)) { 622 netif_err(cp, rx_err, cp->dev, 623 "no spare buffers available\n"); 624 spin_unlock(&cp->rx_spare_lock); 625 return NULL; 626 } 627 } 628 629 entry = cp->rx_spare_list.next; 630 list_del(entry); 631 recover = ++cp->rx_spares_needed; 632 spin_unlock(&cp->rx_spare_lock); 633 634 /* trigger the timer to do the recovery */ 635 if ((recover & (RX_SPARE_RECOVER_VAL - 1)) == 0) { 636 #if 1 637 atomic_inc(&cp->reset_task_pending); 638 atomic_inc(&cp->reset_task_pending_spare); 639 schedule_work(&cp->reset_task); 640 #else 641 atomic_set(&cp->reset_task_pending, CAS_RESET_SPARE); 642 schedule_work(&cp->reset_task); 643 #endif 644 } 645 return list_entry(entry, cas_page_t, list); 646 } 647 648 649 static void cas_mif_poll(struct cas *cp, const int enable) 650 { 651 u32 cfg; 652 653 cfg = readl(cp->regs + REG_MIF_CFG); 654 cfg &= (MIF_CFG_MDIO_0 | MIF_CFG_MDIO_1); 655 656 if (cp->phy_type & CAS_PHY_MII_MDIO1) 657 cfg |= MIF_CFG_PHY_SELECT; 658 659 /* poll and interrupt on link status change. */ 660 if (enable) { 661 cfg |= MIF_CFG_POLL_EN; 662 cfg |= CAS_BASE(MIF_CFG_POLL_REG, MII_BMSR); 663 cfg |= CAS_BASE(MIF_CFG_POLL_PHY, cp->phy_addr); 664 } 665 writel((enable) ? ~(BMSR_LSTATUS | BMSR_ANEGCOMPLETE) : 0xFFFF, 666 cp->regs + REG_MIF_MASK); 667 writel(cfg, cp->regs + REG_MIF_CFG); 668 } 669 670 /* Must be invoked under cp->lock */ 671 static void cas_begin_auto_negotiation(struct cas *cp, 672 const struct ethtool_link_ksettings *ep) 673 { 674 u16 ctl; 675 #if 1 676 int lcntl; 677 int changed = 0; 678 int oldstate = cp->lstate; 679 int link_was_not_down = !(oldstate == link_down); 680 #endif 681 /* Setup link parameters */ 682 if (!ep) 683 goto start_aneg; 684 lcntl = cp->link_cntl; 685 if (ep->base.autoneg == AUTONEG_ENABLE) { 686 cp->link_cntl = BMCR_ANENABLE; 687 } else { 688 u32 speed = ep->base.speed; 689 cp->link_cntl = 0; 690 if (speed == SPEED_100) 691 cp->link_cntl |= BMCR_SPEED100; 692 else if (speed == SPEED_1000) 693 cp->link_cntl |= CAS_BMCR_SPEED1000; 694 if (ep->base.duplex == DUPLEX_FULL) 695 cp->link_cntl |= BMCR_FULLDPLX; 696 } 697 #if 1 698 changed = (lcntl != cp->link_cntl); 699 #endif 700 start_aneg: 701 if (cp->lstate == link_up) { 702 netdev_info(cp->dev, "PCS link down\n"); 703 } else { 704 if (changed) { 705 netdev_info(cp->dev, "link configuration changed\n"); 706 } 707 } 708 cp->lstate = link_down; 709 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 710 if (!cp->hw_running) 711 return; 712 #if 1 713 /* 714 * WTZ: If the old state was link_up, we turn off the carrier 715 * to replicate everything we do elsewhere on a link-down 716 * event when we were already in a link-up state.. 717 */ 718 if (oldstate == link_up) 719 netif_carrier_off(cp->dev); 720 if (changed && link_was_not_down) { 721 /* 722 * WTZ: This branch will simply schedule a full reset after 723 * we explicitly changed link modes in an ioctl. See if this 724 * fixes the link-problems we were having for forced mode. 725 */ 726 atomic_inc(&cp->reset_task_pending); 727 atomic_inc(&cp->reset_task_pending_all); 728 schedule_work(&cp->reset_task); 729 cp->timer_ticks = 0; 730 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 731 return; 732 } 733 #endif 734 if (cp->phy_type & CAS_PHY_SERDES) { 735 u32 val = readl(cp->regs + REG_PCS_MII_CTRL); 736 737 if (cp->link_cntl & BMCR_ANENABLE) { 738 val |= (PCS_MII_RESTART_AUTONEG | PCS_MII_AUTONEG_EN); 739 cp->lstate = link_aneg; 740 } else { 741 if (cp->link_cntl & BMCR_FULLDPLX) 742 val |= PCS_MII_CTRL_DUPLEX; 743 val &= ~PCS_MII_AUTONEG_EN; 744 cp->lstate = link_force_ok; 745 } 746 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 747 writel(val, cp->regs + REG_PCS_MII_CTRL); 748 749 } else { 750 cas_mif_poll(cp, 0); 751 ctl = cas_phy_read(cp, MII_BMCR); 752 ctl &= ~(BMCR_FULLDPLX | BMCR_SPEED100 | 753 CAS_BMCR_SPEED1000 | BMCR_ANENABLE); 754 ctl |= cp->link_cntl; 755 if (ctl & BMCR_ANENABLE) { 756 ctl |= BMCR_ANRESTART; 757 cp->lstate = link_aneg; 758 } else { 759 cp->lstate = link_force_ok; 760 } 761 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 762 cas_phy_write(cp, MII_BMCR, ctl); 763 cas_mif_poll(cp, 1); 764 } 765 766 cp->timer_ticks = 0; 767 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 768 } 769 770 /* Must be invoked under cp->lock. */ 771 static int cas_reset_mii_phy(struct cas *cp) 772 { 773 int limit = STOP_TRIES_PHY; 774 u16 val; 775 776 cas_phy_write(cp, MII_BMCR, BMCR_RESET); 777 udelay(100); 778 while (--limit) { 779 val = cas_phy_read(cp, MII_BMCR); 780 if ((val & BMCR_RESET) == 0) 781 break; 782 udelay(10); 783 } 784 return limit <= 0; 785 } 786 787 static void cas_saturn_firmware_init(struct cas *cp) 788 { 789 const struct firmware *fw; 790 const char fw_name[] = "sun/cassini.bin"; 791 int err; 792 793 if (PHY_NS_DP83065 != cp->phy_id) 794 return; 795 796 err = request_firmware(&fw, fw_name, &cp->pdev->dev); 797 if (err) { 798 pr_err("Failed to load firmware \"%s\"\n", 799 fw_name); 800 return; 801 } 802 if (fw->size < 2) { 803 pr_err("bogus length %zu in \"%s\"\n", 804 fw->size, fw_name); 805 goto out; 806 } 807 cp->fw_load_addr= fw->data[1] << 8 | fw->data[0]; 808 cp->fw_size = fw->size - 2; 809 cp->fw_data = vmalloc(cp->fw_size); 810 if (!cp->fw_data) 811 goto out; 812 memcpy(cp->fw_data, &fw->data[2], cp->fw_size); 813 out: 814 release_firmware(fw); 815 } 816 817 static void cas_saturn_firmware_load(struct cas *cp) 818 { 819 int i; 820 821 if (!cp->fw_data) 822 return; 823 824 cas_phy_powerdown(cp); 825 826 /* expanded memory access mode */ 827 cas_phy_write(cp, DP83065_MII_MEM, 0x0); 828 829 /* pointer configuration for new firmware */ 830 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff9); 831 cas_phy_write(cp, DP83065_MII_REGD, 0xbd); 832 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffa); 833 cas_phy_write(cp, DP83065_MII_REGD, 0x82); 834 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffb); 835 cas_phy_write(cp, DP83065_MII_REGD, 0x0); 836 cas_phy_write(cp, DP83065_MII_REGE, 0x8ffc); 837 cas_phy_write(cp, DP83065_MII_REGD, 0x39); 838 839 /* download new firmware */ 840 cas_phy_write(cp, DP83065_MII_MEM, 0x1); 841 cas_phy_write(cp, DP83065_MII_REGE, cp->fw_load_addr); 842 for (i = 0; i < cp->fw_size; i++) 843 cas_phy_write(cp, DP83065_MII_REGD, cp->fw_data[i]); 844 845 /* enable firmware */ 846 cas_phy_write(cp, DP83065_MII_REGE, 0x8ff8); 847 cas_phy_write(cp, DP83065_MII_REGD, 0x1); 848 } 849 850 851 /* phy initialization */ 852 static void cas_phy_init(struct cas *cp) 853 { 854 u16 val; 855 856 /* if we're in MII/GMII mode, set up phy */ 857 if (CAS_PHY_MII(cp->phy_type)) { 858 writel(PCS_DATAPATH_MODE_MII, 859 cp->regs + REG_PCS_DATAPATH_MODE); 860 861 cas_mif_poll(cp, 0); 862 cas_reset_mii_phy(cp); /* take out of isolate mode */ 863 864 if (PHY_LUCENT_B0 == cp->phy_id) { 865 /* workaround link up/down issue with lucent */ 866 cas_phy_write(cp, LUCENT_MII_REG, 0x8000); 867 cas_phy_write(cp, MII_BMCR, 0x00f1); 868 cas_phy_write(cp, LUCENT_MII_REG, 0x0); 869 870 } else if (PHY_BROADCOM_B0 == (cp->phy_id & 0xFFFFFFFC)) { 871 /* workarounds for broadcom phy */ 872 cas_phy_write(cp, BROADCOM_MII_REG8, 0x0C20); 873 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0012); 874 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1804); 875 cas_phy_write(cp, BROADCOM_MII_REG7, 0x0013); 876 cas_phy_write(cp, BROADCOM_MII_REG5, 0x1204); 877 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); 878 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0132); 879 cas_phy_write(cp, BROADCOM_MII_REG7, 0x8006); 880 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0232); 881 cas_phy_write(cp, BROADCOM_MII_REG7, 0x201F); 882 cas_phy_write(cp, BROADCOM_MII_REG5, 0x0A20); 883 884 } else if (PHY_BROADCOM_5411 == cp->phy_id) { 885 val = cas_phy_read(cp, BROADCOM_MII_REG4); 886 val = cas_phy_read(cp, BROADCOM_MII_REG4); 887 if (val & 0x0080) { 888 /* link workaround */ 889 cas_phy_write(cp, BROADCOM_MII_REG4, 890 val & ~0x0080); 891 } 892 893 } else if (cp->cas_flags & CAS_FLAG_SATURN) { 894 writel((cp->phy_type & CAS_PHY_MII_MDIO0) ? 895 SATURN_PCFG_FSI : 0x0, 896 cp->regs + REG_SATURN_PCFG); 897 898 /* load firmware to address 10Mbps auto-negotiation 899 * issue. NOTE: this will need to be changed if the 900 * default firmware gets fixed. 901 */ 902 if (PHY_NS_DP83065 == cp->phy_id) { 903 cas_saturn_firmware_load(cp); 904 } 905 cas_phy_powerup(cp); 906 } 907 908 /* advertise capabilities */ 909 val = cas_phy_read(cp, MII_BMCR); 910 val &= ~BMCR_ANENABLE; 911 cas_phy_write(cp, MII_BMCR, val); 912 udelay(10); 913 914 cas_phy_write(cp, MII_ADVERTISE, 915 cas_phy_read(cp, MII_ADVERTISE) | 916 (ADVERTISE_10HALF | ADVERTISE_10FULL | 917 ADVERTISE_100HALF | ADVERTISE_100FULL | 918 CAS_ADVERTISE_PAUSE | 919 CAS_ADVERTISE_ASYM_PAUSE)); 920 921 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 922 /* make sure that we don't advertise half 923 * duplex to avoid a chip issue 924 */ 925 val = cas_phy_read(cp, CAS_MII_1000_CTRL); 926 val &= ~CAS_ADVERTISE_1000HALF; 927 val |= CAS_ADVERTISE_1000FULL; 928 cas_phy_write(cp, CAS_MII_1000_CTRL, val); 929 } 930 931 } else { 932 /* reset pcs for serdes */ 933 u32 val; 934 int limit; 935 936 writel(PCS_DATAPATH_MODE_SERDES, 937 cp->regs + REG_PCS_DATAPATH_MODE); 938 939 /* enable serdes pins on saturn */ 940 if (cp->cas_flags & CAS_FLAG_SATURN) 941 writel(0, cp->regs + REG_SATURN_PCFG); 942 943 /* Reset PCS unit. */ 944 val = readl(cp->regs + REG_PCS_MII_CTRL); 945 val |= PCS_MII_RESET; 946 writel(val, cp->regs + REG_PCS_MII_CTRL); 947 948 limit = STOP_TRIES; 949 while (--limit > 0) { 950 udelay(10); 951 if ((readl(cp->regs + REG_PCS_MII_CTRL) & 952 PCS_MII_RESET) == 0) 953 break; 954 } 955 if (limit <= 0) 956 netdev_warn(cp->dev, "PCS reset bit would not clear [%08x]\n", 957 readl(cp->regs + REG_PCS_STATE_MACHINE)); 958 959 /* Make sure PCS is disabled while changing advertisement 960 * configuration. 961 */ 962 writel(0x0, cp->regs + REG_PCS_CFG); 963 964 /* Advertise all capabilities except half-duplex. */ 965 val = readl(cp->regs + REG_PCS_MII_ADVERT); 966 val &= ~PCS_MII_ADVERT_HD; 967 val |= (PCS_MII_ADVERT_FD | PCS_MII_ADVERT_SYM_PAUSE | 968 PCS_MII_ADVERT_ASYM_PAUSE); 969 writel(val, cp->regs + REG_PCS_MII_ADVERT); 970 971 /* enable PCS */ 972 writel(PCS_CFG_EN, cp->regs + REG_PCS_CFG); 973 974 /* pcs workaround: enable sync detect */ 975 writel(PCS_SERDES_CTRL_SYNCD_EN, 976 cp->regs + REG_PCS_SERDES_CTRL); 977 } 978 } 979 980 981 static int cas_pcs_link_check(struct cas *cp) 982 { 983 u32 stat, state_machine; 984 int retval = 0; 985 986 /* The link status bit latches on zero, so you must 987 * read it twice in such a case to see a transition 988 * to the link being up. 989 */ 990 stat = readl(cp->regs + REG_PCS_MII_STATUS); 991 if ((stat & PCS_MII_STATUS_LINK_STATUS) == 0) 992 stat = readl(cp->regs + REG_PCS_MII_STATUS); 993 994 /* The remote-fault indication is only valid 995 * when autoneg has completed. 996 */ 997 if ((stat & (PCS_MII_STATUS_AUTONEG_COMP | 998 PCS_MII_STATUS_REMOTE_FAULT)) == 999 (PCS_MII_STATUS_AUTONEG_COMP | PCS_MII_STATUS_REMOTE_FAULT)) 1000 netif_info(cp, link, cp->dev, "PCS RemoteFault\n"); 1001 1002 /* work around link detection issue by querying the PCS state 1003 * machine directly. 1004 */ 1005 state_machine = readl(cp->regs + REG_PCS_STATE_MACHINE); 1006 if ((state_machine & PCS_SM_LINK_STATE_MASK) != SM_LINK_STATE_UP) { 1007 stat &= ~PCS_MII_STATUS_LINK_STATUS; 1008 } else if (state_machine & PCS_SM_WORD_SYNC_STATE_MASK) { 1009 stat |= PCS_MII_STATUS_LINK_STATUS; 1010 } 1011 1012 if (stat & PCS_MII_STATUS_LINK_STATUS) { 1013 if (cp->lstate != link_up) { 1014 if (cp->opened) { 1015 cp->lstate = link_up; 1016 cp->link_transition = LINK_TRANSITION_LINK_UP; 1017 1018 cas_set_link_modes(cp); 1019 netif_carrier_on(cp->dev); 1020 } 1021 } 1022 } else if (cp->lstate == link_up) { 1023 cp->lstate = link_down; 1024 if (link_transition_timeout != 0 && 1025 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && 1026 !cp->link_transition_jiffies_valid) { 1027 /* 1028 * force a reset, as a workaround for the 1029 * link-failure problem. May want to move this to a 1030 * point a bit earlier in the sequence. If we had 1031 * generated a reset a short time ago, we'll wait for 1032 * the link timer to check the status until a 1033 * timer expires (link_transistion_jiffies_valid is 1034 * true when the timer is running.) Instead of using 1035 * a system timer, we just do a check whenever the 1036 * link timer is running - this clears the flag after 1037 * a suitable delay. 1038 */ 1039 retval = 1; 1040 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; 1041 cp->link_transition_jiffies = jiffies; 1042 cp->link_transition_jiffies_valid = 1; 1043 } else { 1044 cp->link_transition = LINK_TRANSITION_ON_FAILURE; 1045 } 1046 netif_carrier_off(cp->dev); 1047 if (cp->opened) 1048 netif_info(cp, link, cp->dev, "PCS link down\n"); 1049 1050 /* Cassini only: if you force a mode, there can be 1051 * sync problems on link down. to fix that, the following 1052 * things need to be checked: 1053 * 1) read serialink state register 1054 * 2) read pcs status register to verify link down. 1055 * 3) if link down and serial link == 0x03, then you need 1056 * to global reset the chip. 1057 */ 1058 if ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0) { 1059 /* should check to see if we're in a forced mode */ 1060 stat = readl(cp->regs + REG_PCS_SERDES_STATE); 1061 if (stat == 0x03) 1062 return 1; 1063 } 1064 } else if (cp->lstate == link_down) { 1065 if (link_transition_timeout != 0 && 1066 cp->link_transition != LINK_TRANSITION_REQUESTED_RESET && 1067 !cp->link_transition_jiffies_valid) { 1068 /* force a reset, as a workaround for the 1069 * link-failure problem. May want to move 1070 * this to a point a bit earlier in the 1071 * sequence. 1072 */ 1073 retval = 1; 1074 cp->link_transition = LINK_TRANSITION_REQUESTED_RESET; 1075 cp->link_transition_jiffies = jiffies; 1076 cp->link_transition_jiffies_valid = 1; 1077 } else { 1078 cp->link_transition = LINK_TRANSITION_STILL_FAILED; 1079 } 1080 } 1081 1082 return retval; 1083 } 1084 1085 static int cas_pcs_interrupt(struct net_device *dev, 1086 struct cas *cp, u32 status) 1087 { 1088 u32 stat = readl(cp->regs + REG_PCS_INTR_STATUS); 1089 1090 if ((stat & PCS_INTR_STATUS_LINK_CHANGE) == 0) 1091 return 0; 1092 return cas_pcs_link_check(cp); 1093 } 1094 1095 static int cas_txmac_interrupt(struct net_device *dev, 1096 struct cas *cp, u32 status) 1097 { 1098 u32 txmac_stat = readl(cp->regs + REG_MAC_TX_STATUS); 1099 1100 if (!txmac_stat) 1101 return 0; 1102 1103 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 1104 "txmac interrupt, txmac_stat: 0x%x\n", txmac_stat); 1105 1106 /* Defer timer expiration is quite normal, 1107 * don't even log the event. 1108 */ 1109 if ((txmac_stat & MAC_TX_DEFER_TIMER) && 1110 !(txmac_stat & ~MAC_TX_DEFER_TIMER)) 1111 return 0; 1112 1113 spin_lock(&cp->stat_lock[0]); 1114 if (txmac_stat & MAC_TX_UNDERRUN) { 1115 netdev_err(dev, "TX MAC xmit underrun\n"); 1116 cp->net_stats[0].tx_fifo_errors++; 1117 } 1118 1119 if (txmac_stat & MAC_TX_MAX_PACKET_ERR) { 1120 netdev_err(dev, "TX MAC max packet size error\n"); 1121 cp->net_stats[0].tx_errors++; 1122 } 1123 1124 /* The rest are all cases of one of the 16-bit TX 1125 * counters expiring. 1126 */ 1127 if (txmac_stat & MAC_TX_COLL_NORMAL) 1128 cp->net_stats[0].collisions += 0x10000; 1129 1130 if (txmac_stat & MAC_TX_COLL_EXCESS) { 1131 cp->net_stats[0].tx_aborted_errors += 0x10000; 1132 cp->net_stats[0].collisions += 0x10000; 1133 } 1134 1135 if (txmac_stat & MAC_TX_COLL_LATE) { 1136 cp->net_stats[0].tx_aborted_errors += 0x10000; 1137 cp->net_stats[0].collisions += 0x10000; 1138 } 1139 spin_unlock(&cp->stat_lock[0]); 1140 1141 /* We do not keep track of MAC_TX_COLL_FIRST and 1142 * MAC_TX_PEAK_ATTEMPTS events. 1143 */ 1144 return 0; 1145 } 1146 1147 static void cas_load_firmware(struct cas *cp, cas_hp_inst_t *firmware) 1148 { 1149 cas_hp_inst_t *inst; 1150 u32 val; 1151 int i; 1152 1153 i = 0; 1154 while ((inst = firmware) && inst->note) { 1155 writel(i, cp->regs + REG_HP_INSTR_RAM_ADDR); 1156 1157 val = CAS_BASE(HP_INSTR_RAM_HI_VAL, inst->val); 1158 val |= CAS_BASE(HP_INSTR_RAM_HI_MASK, inst->mask); 1159 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_HI); 1160 1161 val = CAS_BASE(HP_INSTR_RAM_MID_OUTARG, inst->outarg >> 10); 1162 val |= CAS_BASE(HP_INSTR_RAM_MID_OUTOP, inst->outop); 1163 val |= CAS_BASE(HP_INSTR_RAM_MID_FNEXT, inst->fnext); 1164 val |= CAS_BASE(HP_INSTR_RAM_MID_FOFF, inst->foff); 1165 val |= CAS_BASE(HP_INSTR_RAM_MID_SNEXT, inst->snext); 1166 val |= CAS_BASE(HP_INSTR_RAM_MID_SOFF, inst->soff); 1167 val |= CAS_BASE(HP_INSTR_RAM_MID_OP, inst->op); 1168 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_MID); 1169 1170 val = CAS_BASE(HP_INSTR_RAM_LOW_OUTMASK, inst->outmask); 1171 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTSHIFT, inst->outshift); 1172 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTEN, inst->outenab); 1173 val |= CAS_BASE(HP_INSTR_RAM_LOW_OUTARG, inst->outarg); 1174 writel(val, cp->regs + REG_HP_INSTR_RAM_DATA_LOW); 1175 ++firmware; 1176 ++i; 1177 } 1178 } 1179 1180 static void cas_init_rx_dma(struct cas *cp) 1181 { 1182 u64 desc_dma = cp->block_dvma; 1183 u32 val; 1184 int i, size; 1185 1186 /* rx free descriptors */ 1187 val = CAS_BASE(RX_CFG_SWIVEL, RX_SWIVEL_OFF_VAL); 1188 val |= CAS_BASE(RX_CFG_DESC_RING, RX_DESC_RINGN_INDEX(0)); 1189 val |= CAS_BASE(RX_CFG_COMP_RING, RX_COMP_RINGN_INDEX(0)); 1190 if ((N_RX_DESC_RINGS > 1) && 1191 (cp->cas_flags & CAS_FLAG_REG_PLUS)) /* do desc 2 */ 1192 val |= CAS_BASE(RX_CFG_DESC_RING1, RX_DESC_RINGN_INDEX(1)); 1193 writel(val, cp->regs + REG_RX_CFG); 1194 1195 val = (unsigned long) cp->init_rxds[0] - 1196 (unsigned long) cp->init_block; 1197 writel((desc_dma + val) >> 32, cp->regs + REG_RX_DB_HI); 1198 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_DB_LOW); 1199 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); 1200 1201 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1202 /* rx desc 2 is for IPSEC packets. however, 1203 * we don't it that for that purpose. 1204 */ 1205 val = (unsigned long) cp->init_rxds[1] - 1206 (unsigned long) cp->init_block; 1207 writel((desc_dma + val) >> 32, cp->regs + REG_PLUS_RX_DB1_HI); 1208 writel((desc_dma + val) & 0xffffffff, cp->regs + 1209 REG_PLUS_RX_DB1_LOW); 1210 writel(RX_DESC_RINGN_SIZE(1) - 4, cp->regs + 1211 REG_PLUS_RX_KICK1); 1212 } 1213 1214 /* rx completion registers */ 1215 val = (unsigned long) cp->init_rxcs[0] - 1216 (unsigned long) cp->init_block; 1217 writel((desc_dma + val) >> 32, cp->regs + REG_RX_CB_HI); 1218 writel((desc_dma + val) & 0xffffffff, cp->regs + REG_RX_CB_LOW); 1219 1220 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1221 /* rx comp 2-4 */ 1222 for (i = 1; i < MAX_RX_COMP_RINGS; i++) { 1223 val = (unsigned long) cp->init_rxcs[i] - 1224 (unsigned long) cp->init_block; 1225 writel((desc_dma + val) >> 32, cp->regs + 1226 REG_PLUS_RX_CBN_HI(i)); 1227 writel((desc_dma + val) & 0xffffffff, cp->regs + 1228 REG_PLUS_RX_CBN_LOW(i)); 1229 } 1230 } 1231 1232 /* read selective clear regs to prevent spurious interrupts 1233 * on reset because complete == kick. 1234 * selective clear set up to prevent interrupts on resets 1235 */ 1236 readl(cp->regs + REG_INTR_STATUS_ALIAS); 1237 writel(INTR_RX_DONE | INTR_RX_BUF_UNAVAIL, cp->regs + REG_ALIAS_CLEAR); 1238 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1239 for (i = 1; i < N_RX_COMP_RINGS; i++) 1240 readl(cp->regs + REG_PLUS_INTRN_STATUS_ALIAS(i)); 1241 1242 /* 2 is different from 3 and 4 */ 1243 if (N_RX_COMP_RINGS > 1) 1244 writel(INTR_RX_DONE_ALT | INTR_RX_BUF_UNAVAIL_1, 1245 cp->regs + REG_PLUS_ALIASN_CLEAR(1)); 1246 1247 for (i = 2; i < N_RX_COMP_RINGS; i++) 1248 writel(INTR_RX_DONE_ALT, 1249 cp->regs + REG_PLUS_ALIASN_CLEAR(i)); 1250 } 1251 1252 /* set up pause thresholds */ 1253 val = CAS_BASE(RX_PAUSE_THRESH_OFF, 1254 cp->rx_pause_off / RX_PAUSE_THRESH_QUANTUM); 1255 val |= CAS_BASE(RX_PAUSE_THRESH_ON, 1256 cp->rx_pause_on / RX_PAUSE_THRESH_QUANTUM); 1257 writel(val, cp->regs + REG_RX_PAUSE_THRESH); 1258 1259 /* zero out dma reassembly buffers */ 1260 for (i = 0; i < 64; i++) { 1261 writel(i, cp->regs + REG_RX_TABLE_ADDR); 1262 writel(0x0, cp->regs + REG_RX_TABLE_DATA_LOW); 1263 writel(0x0, cp->regs + REG_RX_TABLE_DATA_MID); 1264 writel(0x0, cp->regs + REG_RX_TABLE_DATA_HI); 1265 } 1266 1267 /* make sure address register is 0 for normal operation */ 1268 writel(0x0, cp->regs + REG_RX_CTRL_FIFO_ADDR); 1269 writel(0x0, cp->regs + REG_RX_IPP_FIFO_ADDR); 1270 1271 /* interrupt mitigation */ 1272 #ifdef USE_RX_BLANK 1273 val = CAS_BASE(RX_BLANK_INTR_TIME, RX_BLANK_INTR_TIME_VAL); 1274 val |= CAS_BASE(RX_BLANK_INTR_PKT, RX_BLANK_INTR_PKT_VAL); 1275 writel(val, cp->regs + REG_RX_BLANK); 1276 #else 1277 writel(0x0, cp->regs + REG_RX_BLANK); 1278 #endif 1279 1280 /* interrupt generation as a function of low water marks for 1281 * free desc and completion entries. these are used to trigger 1282 * housekeeping for rx descs. we don't use the free interrupt 1283 * as it's not very useful 1284 */ 1285 /* val = CAS_BASE(RX_AE_THRESH_FREE, RX_AE_FREEN_VAL(0)); */ 1286 val = CAS_BASE(RX_AE_THRESH_COMP, RX_AE_COMP_VAL); 1287 writel(val, cp->regs + REG_RX_AE_THRESH); 1288 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 1289 val = CAS_BASE(RX_AE1_THRESH_FREE, RX_AE_FREEN_VAL(1)); 1290 writel(val, cp->regs + REG_PLUS_RX_AE1_THRESH); 1291 } 1292 1293 /* Random early detect registers. useful for congestion avoidance. 1294 * this should be tunable. 1295 */ 1296 writel(0x0, cp->regs + REG_RX_RED); 1297 1298 /* receive page sizes. default == 2K (0x800) */ 1299 val = 0; 1300 if (cp->page_size == 0x1000) 1301 val = 0x1; 1302 else if (cp->page_size == 0x2000) 1303 val = 0x2; 1304 else if (cp->page_size == 0x4000) 1305 val = 0x3; 1306 1307 /* round mtu + offset. constrain to page size. */ 1308 size = cp->dev->mtu + 64; 1309 if (size > cp->page_size) 1310 size = cp->page_size; 1311 1312 if (size <= 0x400) 1313 i = 0x0; 1314 else if (size <= 0x800) 1315 i = 0x1; 1316 else if (size <= 0x1000) 1317 i = 0x2; 1318 else 1319 i = 0x3; 1320 1321 cp->mtu_stride = 1 << (i + 10); 1322 val = CAS_BASE(RX_PAGE_SIZE, val); 1323 val |= CAS_BASE(RX_PAGE_SIZE_MTU_STRIDE, i); 1324 val |= CAS_BASE(RX_PAGE_SIZE_MTU_COUNT, cp->page_size >> (i + 10)); 1325 val |= CAS_BASE(RX_PAGE_SIZE_MTU_OFF, 0x1); 1326 writel(val, cp->regs + REG_RX_PAGE_SIZE); 1327 1328 /* enable the header parser if desired */ 1329 if (CAS_HP_FIRMWARE == cas_prog_null) 1330 return; 1331 1332 val = CAS_BASE(HP_CFG_NUM_CPU, CAS_NCPUS > 63 ? 0 : CAS_NCPUS); 1333 val |= HP_CFG_PARSE_EN | HP_CFG_SYN_INC_MASK; 1334 val |= CAS_BASE(HP_CFG_TCP_THRESH, HP_TCP_THRESH_VAL); 1335 writel(val, cp->regs + REG_HP_CFG); 1336 } 1337 1338 static inline void cas_rxc_init(struct cas_rx_comp *rxc) 1339 { 1340 memset(rxc, 0, sizeof(*rxc)); 1341 rxc->word4 = cpu_to_le64(RX_COMP4_ZERO); 1342 } 1343 1344 /* NOTE: we use the ENC RX DESC ring for spares. the rx_page[0,1] 1345 * flipping is protected by the fact that the chip will not 1346 * hand back the same page index while it's being processed. 1347 */ 1348 static inline cas_page_t *cas_page_spare(struct cas *cp, const int index) 1349 { 1350 cas_page_t *page = cp->rx_pages[1][index]; 1351 cas_page_t *new; 1352 1353 if (page_count(page->buffer) == 1) 1354 return page; 1355 1356 new = cas_page_dequeue(cp); 1357 if (new) { 1358 spin_lock(&cp->rx_inuse_lock); 1359 list_add(&page->list, &cp->rx_inuse_list); 1360 spin_unlock(&cp->rx_inuse_lock); 1361 } 1362 return new; 1363 } 1364 1365 /* this needs to be changed if we actually use the ENC RX DESC ring */ 1366 static cas_page_t *cas_page_swap(struct cas *cp, const int ring, 1367 const int index) 1368 { 1369 cas_page_t **page0 = cp->rx_pages[0]; 1370 cas_page_t **page1 = cp->rx_pages[1]; 1371 1372 /* swap if buffer is in use */ 1373 if (page_count(page0[index]->buffer) > 1) { 1374 cas_page_t *new = cas_page_spare(cp, index); 1375 if (new) { 1376 page1[index] = page0[index]; 1377 page0[index] = new; 1378 } 1379 } 1380 RX_USED_SET(page0[index], 0); 1381 return page0[index]; 1382 } 1383 1384 static void cas_clean_rxds(struct cas *cp) 1385 { 1386 /* only clean ring 0 as ring 1 is used for spare buffers */ 1387 struct cas_rx_desc *rxd = cp->init_rxds[0]; 1388 int i, size; 1389 1390 /* release all rx flows */ 1391 for (i = 0; i < N_RX_FLOWS; i++) { 1392 struct sk_buff *skb; 1393 while ((skb = __skb_dequeue(&cp->rx_flows[i]))) { 1394 cas_skb_release(skb); 1395 } 1396 } 1397 1398 /* initialize descriptors */ 1399 size = RX_DESC_RINGN_SIZE(0); 1400 for (i = 0; i < size; i++) { 1401 cas_page_t *page = cas_page_swap(cp, 0, i); 1402 rxd[i].buffer = cpu_to_le64(page->dma_addr); 1403 rxd[i].index = cpu_to_le64(CAS_BASE(RX_INDEX_NUM, i) | 1404 CAS_BASE(RX_INDEX_RING, 0)); 1405 } 1406 1407 cp->rx_old[0] = RX_DESC_RINGN_SIZE(0) - 4; 1408 cp->rx_last[0] = 0; 1409 cp->cas_flags &= ~CAS_FLAG_RXD_POST(0); 1410 } 1411 1412 static void cas_clean_rxcs(struct cas *cp) 1413 { 1414 int i, j; 1415 1416 /* take ownership of rx comp descriptors */ 1417 memset(cp->rx_cur, 0, sizeof(*cp->rx_cur)*N_RX_COMP_RINGS); 1418 memset(cp->rx_new, 0, sizeof(*cp->rx_new)*N_RX_COMP_RINGS); 1419 for (i = 0; i < N_RX_COMP_RINGS; i++) { 1420 struct cas_rx_comp *rxc = cp->init_rxcs[i]; 1421 for (j = 0; j < RX_COMP_RINGN_SIZE(i); j++) { 1422 cas_rxc_init(rxc + j); 1423 } 1424 } 1425 } 1426 1427 #if 0 1428 /* When we get a RX fifo overflow, the RX unit is probably hung 1429 * so we do the following. 1430 * 1431 * If any part of the reset goes wrong, we return 1 and that causes the 1432 * whole chip to be reset. 1433 */ 1434 static int cas_rxmac_reset(struct cas *cp) 1435 { 1436 struct net_device *dev = cp->dev; 1437 int limit; 1438 u32 val; 1439 1440 /* First, reset MAC RX. */ 1441 writel(cp->mac_rx_cfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 1442 for (limit = 0; limit < STOP_TRIES; limit++) { 1443 if (!(readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN)) 1444 break; 1445 udelay(10); 1446 } 1447 if (limit == STOP_TRIES) { 1448 netdev_err(dev, "RX MAC will not disable, resetting whole chip\n"); 1449 return 1; 1450 } 1451 1452 /* Second, disable RX DMA. */ 1453 writel(0, cp->regs + REG_RX_CFG); 1454 for (limit = 0; limit < STOP_TRIES; limit++) { 1455 if (!(readl(cp->regs + REG_RX_CFG) & RX_CFG_DMA_EN)) 1456 break; 1457 udelay(10); 1458 } 1459 if (limit == STOP_TRIES) { 1460 netdev_err(dev, "RX DMA will not disable, resetting whole chip\n"); 1461 return 1; 1462 } 1463 1464 mdelay(5); 1465 1466 /* Execute RX reset command. */ 1467 writel(SW_RESET_RX, cp->regs + REG_SW_RESET); 1468 for (limit = 0; limit < STOP_TRIES; limit++) { 1469 if (!(readl(cp->regs + REG_SW_RESET) & SW_RESET_RX)) 1470 break; 1471 udelay(10); 1472 } 1473 if (limit == STOP_TRIES) { 1474 netdev_err(dev, "RX reset command will not execute, resetting whole chip\n"); 1475 return 1; 1476 } 1477 1478 /* reset driver rx state */ 1479 cas_clean_rxds(cp); 1480 cas_clean_rxcs(cp); 1481 1482 /* Now, reprogram the rest of RX unit. */ 1483 cas_init_rx_dma(cp); 1484 1485 /* re-enable */ 1486 val = readl(cp->regs + REG_RX_CFG); 1487 writel(val | RX_CFG_DMA_EN, cp->regs + REG_RX_CFG); 1488 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); 1489 val = readl(cp->regs + REG_MAC_RX_CFG); 1490 writel(val | MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 1491 return 0; 1492 } 1493 #endif 1494 1495 static int cas_rxmac_interrupt(struct net_device *dev, struct cas *cp, 1496 u32 status) 1497 { 1498 u32 stat = readl(cp->regs + REG_MAC_RX_STATUS); 1499 1500 if (!stat) 1501 return 0; 1502 1503 netif_dbg(cp, intr, cp->dev, "rxmac interrupt, stat: 0x%x\n", stat); 1504 1505 /* these are all rollovers */ 1506 spin_lock(&cp->stat_lock[0]); 1507 if (stat & MAC_RX_ALIGN_ERR) 1508 cp->net_stats[0].rx_frame_errors += 0x10000; 1509 1510 if (stat & MAC_RX_CRC_ERR) 1511 cp->net_stats[0].rx_crc_errors += 0x10000; 1512 1513 if (stat & MAC_RX_LEN_ERR) 1514 cp->net_stats[0].rx_length_errors += 0x10000; 1515 1516 if (stat & MAC_RX_OVERFLOW) { 1517 cp->net_stats[0].rx_over_errors++; 1518 cp->net_stats[0].rx_fifo_errors++; 1519 } 1520 1521 /* We do not track MAC_RX_FRAME_COUNT and MAC_RX_VIOL_ERR 1522 * events. 1523 */ 1524 spin_unlock(&cp->stat_lock[0]); 1525 return 0; 1526 } 1527 1528 static int cas_mac_interrupt(struct net_device *dev, struct cas *cp, 1529 u32 status) 1530 { 1531 u32 stat = readl(cp->regs + REG_MAC_CTRL_STATUS); 1532 1533 if (!stat) 1534 return 0; 1535 1536 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 1537 "mac interrupt, stat: 0x%x\n", stat); 1538 1539 /* This interrupt is just for pause frame and pause 1540 * tracking. It is useful for diagnostics and debug 1541 * but probably by default we will mask these events. 1542 */ 1543 if (stat & MAC_CTRL_PAUSE_STATE) 1544 cp->pause_entered++; 1545 1546 if (stat & MAC_CTRL_PAUSE_RECEIVED) 1547 cp->pause_last_time_recvd = (stat >> 16); 1548 1549 return 0; 1550 } 1551 1552 1553 /* Must be invoked under cp->lock. */ 1554 static inline int cas_mdio_link_not_up(struct cas *cp) 1555 { 1556 u16 val; 1557 1558 switch (cp->lstate) { 1559 case link_force_ret: 1560 netif_info(cp, link, cp->dev, "Autoneg failed again, keeping forced mode\n"); 1561 cas_phy_write(cp, MII_BMCR, cp->link_fcntl); 1562 cp->timer_ticks = 5; 1563 cp->lstate = link_force_ok; 1564 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1565 break; 1566 1567 case link_aneg: 1568 val = cas_phy_read(cp, MII_BMCR); 1569 1570 /* Try forced modes. we try things in the following order: 1571 * 1000 full -> 100 full/half -> 10 half 1572 */ 1573 val &= ~(BMCR_ANRESTART | BMCR_ANENABLE); 1574 val |= BMCR_FULLDPLX; 1575 val |= (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 1576 CAS_BMCR_SPEED1000 : BMCR_SPEED100; 1577 cas_phy_write(cp, MII_BMCR, val); 1578 cp->timer_ticks = 5; 1579 cp->lstate = link_force_try; 1580 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1581 break; 1582 1583 case link_force_try: 1584 /* Downgrade from 1000 to 100 to 10 Mbps if necessary. */ 1585 val = cas_phy_read(cp, MII_BMCR); 1586 cp->timer_ticks = 5; 1587 if (val & CAS_BMCR_SPEED1000) { /* gigabit */ 1588 val &= ~CAS_BMCR_SPEED1000; 1589 val |= (BMCR_SPEED100 | BMCR_FULLDPLX); 1590 cas_phy_write(cp, MII_BMCR, val); 1591 break; 1592 } 1593 1594 if (val & BMCR_SPEED100) { 1595 if (val & BMCR_FULLDPLX) /* fd failed */ 1596 val &= ~BMCR_FULLDPLX; 1597 else { /* 100Mbps failed */ 1598 val &= ~BMCR_SPEED100; 1599 } 1600 cas_phy_write(cp, MII_BMCR, val); 1601 break; 1602 } 1603 break; 1604 default: 1605 break; 1606 } 1607 return 0; 1608 } 1609 1610 1611 /* must be invoked with cp->lock held */ 1612 static int cas_mii_link_check(struct cas *cp, const u16 bmsr) 1613 { 1614 int restart; 1615 1616 if (bmsr & BMSR_LSTATUS) { 1617 /* Ok, here we got a link. If we had it due to a forced 1618 * fallback, and we were configured for autoneg, we 1619 * retry a short autoneg pass. If you know your hub is 1620 * broken, use ethtool ;) 1621 */ 1622 if ((cp->lstate == link_force_try) && 1623 (cp->link_cntl & BMCR_ANENABLE)) { 1624 cp->lstate = link_force_ret; 1625 cp->link_transition = LINK_TRANSITION_LINK_CONFIG; 1626 cas_mif_poll(cp, 0); 1627 cp->link_fcntl = cas_phy_read(cp, MII_BMCR); 1628 cp->timer_ticks = 5; 1629 if (cp->opened) 1630 netif_info(cp, link, cp->dev, 1631 "Got link after fallback, retrying autoneg once...\n"); 1632 cas_phy_write(cp, MII_BMCR, 1633 cp->link_fcntl | BMCR_ANENABLE | 1634 BMCR_ANRESTART); 1635 cas_mif_poll(cp, 1); 1636 1637 } else if (cp->lstate != link_up) { 1638 cp->lstate = link_up; 1639 cp->link_transition = LINK_TRANSITION_LINK_UP; 1640 1641 if (cp->opened) { 1642 cas_set_link_modes(cp); 1643 netif_carrier_on(cp->dev); 1644 } 1645 } 1646 return 0; 1647 } 1648 1649 /* link not up. if the link was previously up, we restart the 1650 * whole process 1651 */ 1652 restart = 0; 1653 if (cp->lstate == link_up) { 1654 cp->lstate = link_down; 1655 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 1656 1657 netif_carrier_off(cp->dev); 1658 if (cp->opened) 1659 netif_info(cp, link, cp->dev, "Link down\n"); 1660 restart = 1; 1661 1662 } else if (++cp->timer_ticks > 10) 1663 cas_mdio_link_not_up(cp); 1664 1665 return restart; 1666 } 1667 1668 static int cas_mif_interrupt(struct net_device *dev, struct cas *cp, 1669 u32 status) 1670 { 1671 u32 stat = readl(cp->regs + REG_MIF_STATUS); 1672 u16 bmsr; 1673 1674 /* check for a link change */ 1675 if (CAS_VAL(MIF_STATUS_POLL_STATUS, stat) == 0) 1676 return 0; 1677 1678 bmsr = CAS_VAL(MIF_STATUS_POLL_DATA, stat); 1679 return cas_mii_link_check(cp, bmsr); 1680 } 1681 1682 static int cas_pci_interrupt(struct net_device *dev, struct cas *cp, 1683 u32 status) 1684 { 1685 u32 stat = readl(cp->regs + REG_PCI_ERR_STATUS); 1686 1687 if (!stat) 1688 return 0; 1689 1690 netdev_err(dev, "PCI error [%04x:%04x]", 1691 stat, readl(cp->regs + REG_BIM_DIAG)); 1692 1693 /* cassini+ has this reserved */ 1694 if ((stat & PCI_ERR_BADACK) && 1695 ((cp->cas_flags & CAS_FLAG_REG_PLUS) == 0)) 1696 pr_cont(" <No ACK64# during ABS64 cycle>"); 1697 1698 if (stat & PCI_ERR_DTRTO) 1699 pr_cont(" <Delayed transaction timeout>"); 1700 if (stat & PCI_ERR_OTHER) 1701 pr_cont(" <other>"); 1702 if (stat & PCI_ERR_BIM_DMA_WRITE) 1703 pr_cont(" <BIM DMA 0 write req>"); 1704 if (stat & PCI_ERR_BIM_DMA_READ) 1705 pr_cont(" <BIM DMA 0 read req>"); 1706 pr_cont("\n"); 1707 1708 if (stat & PCI_ERR_OTHER) { 1709 int pci_errs; 1710 1711 /* Interrogate PCI config space for the 1712 * true cause. 1713 */ 1714 pci_errs = pci_status_get_and_clear_errors(cp->pdev); 1715 1716 netdev_err(dev, "PCI status errors[%04x]\n", pci_errs); 1717 if (pci_errs & PCI_STATUS_PARITY) 1718 netdev_err(dev, "PCI parity error detected\n"); 1719 if (pci_errs & PCI_STATUS_SIG_TARGET_ABORT) 1720 netdev_err(dev, "PCI target abort\n"); 1721 if (pci_errs & PCI_STATUS_REC_TARGET_ABORT) 1722 netdev_err(dev, "PCI master acks target abort\n"); 1723 if (pci_errs & PCI_STATUS_REC_MASTER_ABORT) 1724 netdev_err(dev, "PCI master abort\n"); 1725 if (pci_errs & PCI_STATUS_SIG_SYSTEM_ERROR) 1726 netdev_err(dev, "PCI system error SERR#\n"); 1727 if (pci_errs & PCI_STATUS_DETECTED_PARITY) 1728 netdev_err(dev, "PCI parity error\n"); 1729 } 1730 1731 /* For all PCI errors, we should reset the chip. */ 1732 return 1; 1733 } 1734 1735 /* All non-normal interrupt conditions get serviced here. 1736 * Returns non-zero if we should just exit the interrupt 1737 * handler right now (ie. if we reset the card which invalidates 1738 * all of the other original irq status bits). 1739 */ 1740 static int cas_abnormal_irq(struct net_device *dev, struct cas *cp, 1741 u32 status) 1742 { 1743 if (status & INTR_RX_TAG_ERROR) { 1744 /* corrupt RX tag framing */ 1745 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 1746 "corrupt rx tag framing\n"); 1747 spin_lock(&cp->stat_lock[0]); 1748 cp->net_stats[0].rx_errors++; 1749 spin_unlock(&cp->stat_lock[0]); 1750 goto do_reset; 1751 } 1752 1753 if (status & INTR_RX_LEN_MISMATCH) { 1754 /* length mismatch. */ 1755 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 1756 "length mismatch for rx frame\n"); 1757 spin_lock(&cp->stat_lock[0]); 1758 cp->net_stats[0].rx_errors++; 1759 spin_unlock(&cp->stat_lock[0]); 1760 goto do_reset; 1761 } 1762 1763 if (status & INTR_PCS_STATUS) { 1764 if (cas_pcs_interrupt(dev, cp, status)) 1765 goto do_reset; 1766 } 1767 1768 if (status & INTR_TX_MAC_STATUS) { 1769 if (cas_txmac_interrupt(dev, cp, status)) 1770 goto do_reset; 1771 } 1772 1773 if (status & INTR_RX_MAC_STATUS) { 1774 if (cas_rxmac_interrupt(dev, cp, status)) 1775 goto do_reset; 1776 } 1777 1778 if (status & INTR_MAC_CTRL_STATUS) { 1779 if (cas_mac_interrupt(dev, cp, status)) 1780 goto do_reset; 1781 } 1782 1783 if (status & INTR_MIF_STATUS) { 1784 if (cas_mif_interrupt(dev, cp, status)) 1785 goto do_reset; 1786 } 1787 1788 if (status & INTR_PCI_ERROR_STATUS) { 1789 if (cas_pci_interrupt(dev, cp, status)) 1790 goto do_reset; 1791 } 1792 return 0; 1793 1794 do_reset: 1795 #if 1 1796 atomic_inc(&cp->reset_task_pending); 1797 atomic_inc(&cp->reset_task_pending_all); 1798 netdev_err(dev, "reset called in cas_abnormal_irq [0x%x]\n", status); 1799 schedule_work(&cp->reset_task); 1800 #else 1801 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); 1802 netdev_err(dev, "reset called in cas_abnormal_irq\n"); 1803 schedule_work(&cp->reset_task); 1804 #endif 1805 return 1; 1806 } 1807 1808 /* NOTE: CAS_TABORT returns 1 or 2 so that it can be used when 1809 * determining whether to do a netif_stop/wakeup 1810 */ 1811 #define CAS_TABORT(x) (((x)->cas_flags & CAS_FLAG_TARGET_ABORT) ? 2 : 1) 1812 #define CAS_ROUND_PAGE(x) (((x) + PAGE_SIZE - 1) & PAGE_MASK) 1813 static inline int cas_calc_tabort(struct cas *cp, const unsigned long addr, 1814 const int len) 1815 { 1816 unsigned long off = addr + len; 1817 1818 if (CAS_TABORT(cp) == 1) 1819 return 0; 1820 if ((CAS_ROUND_PAGE(off) - off) > TX_TARGET_ABORT_LEN) 1821 return 0; 1822 return TX_TARGET_ABORT_LEN; 1823 } 1824 1825 static inline void cas_tx_ringN(struct cas *cp, int ring, int limit) 1826 { 1827 struct cas_tx_desc *txds; 1828 struct sk_buff **skbs; 1829 struct net_device *dev = cp->dev; 1830 int entry, count; 1831 1832 spin_lock(&cp->tx_lock[ring]); 1833 txds = cp->init_txds[ring]; 1834 skbs = cp->tx_skbs[ring]; 1835 entry = cp->tx_old[ring]; 1836 1837 count = TX_BUFF_COUNT(ring, entry, limit); 1838 while (entry != limit) { 1839 struct sk_buff *skb = skbs[entry]; 1840 dma_addr_t daddr; 1841 u32 dlen; 1842 int frag; 1843 1844 if (!skb) { 1845 /* this should never occur */ 1846 entry = TX_DESC_NEXT(ring, entry); 1847 continue; 1848 } 1849 1850 /* however, we might get only a partial skb release. */ 1851 count -= skb_shinfo(skb)->nr_frags + 1852 + cp->tx_tiny_use[ring][entry].nbufs + 1; 1853 if (count < 0) 1854 break; 1855 1856 netif_printk(cp, tx_done, KERN_DEBUG, cp->dev, 1857 "tx[%d] done, slot %d\n", ring, entry); 1858 1859 skbs[entry] = NULL; 1860 cp->tx_tiny_use[ring][entry].nbufs = 0; 1861 1862 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 1863 struct cas_tx_desc *txd = txds + entry; 1864 1865 daddr = le64_to_cpu(txd->buffer); 1866 dlen = CAS_VAL(TX_DESC_BUFLEN, 1867 le64_to_cpu(txd->control)); 1868 dma_unmap_page(&cp->pdev->dev, daddr, dlen, 1869 DMA_TO_DEVICE); 1870 entry = TX_DESC_NEXT(ring, entry); 1871 1872 /* tiny buffer may follow */ 1873 if (cp->tx_tiny_use[ring][entry].used) { 1874 cp->tx_tiny_use[ring][entry].used = 0; 1875 entry = TX_DESC_NEXT(ring, entry); 1876 } 1877 } 1878 1879 spin_lock(&cp->stat_lock[ring]); 1880 cp->net_stats[ring].tx_packets++; 1881 cp->net_stats[ring].tx_bytes += skb->len; 1882 spin_unlock(&cp->stat_lock[ring]); 1883 dev_consume_skb_irq(skb); 1884 } 1885 cp->tx_old[ring] = entry; 1886 1887 /* this is wrong for multiple tx rings. the net device needs 1888 * multiple queues for this to do the right thing. we wait 1889 * for 2*packets to be available when using tiny buffers 1890 */ 1891 if (netif_queue_stopped(dev) && 1892 (TX_BUFFS_AVAIL(cp, ring) > CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1))) 1893 netif_wake_queue(dev); 1894 spin_unlock(&cp->tx_lock[ring]); 1895 } 1896 1897 static void cas_tx(struct net_device *dev, struct cas *cp, 1898 u32 status) 1899 { 1900 int limit, ring; 1901 #ifdef USE_TX_COMPWB 1902 u64 compwb = le64_to_cpu(cp->init_block->tx_compwb); 1903 #endif 1904 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 1905 "tx interrupt, status: 0x%x, %llx\n", 1906 status, (unsigned long long)compwb); 1907 /* process all the rings */ 1908 for (ring = 0; ring < N_TX_RINGS; ring++) { 1909 #ifdef USE_TX_COMPWB 1910 /* use the completion writeback registers */ 1911 limit = (CAS_VAL(TX_COMPWB_MSB, compwb) << 8) | 1912 CAS_VAL(TX_COMPWB_LSB, compwb); 1913 compwb = TX_COMPWB_NEXT(compwb); 1914 #else 1915 limit = readl(cp->regs + REG_TX_COMPN(ring)); 1916 #endif 1917 if (cp->tx_old[ring] != limit) 1918 cas_tx_ringN(cp, ring, limit); 1919 } 1920 } 1921 1922 1923 static int cas_rx_process_pkt(struct cas *cp, struct cas_rx_comp *rxc, 1924 int entry, const u64 *words, 1925 struct sk_buff **skbref) 1926 { 1927 int dlen, hlen, len, i, alloclen; 1928 int off, swivel = RX_SWIVEL_OFF_VAL; 1929 struct cas_page *page; 1930 struct sk_buff *skb; 1931 void *addr, *crcaddr; 1932 __sum16 csum; 1933 char *p; 1934 1935 hlen = CAS_VAL(RX_COMP2_HDR_SIZE, words[1]); 1936 dlen = CAS_VAL(RX_COMP1_DATA_SIZE, words[0]); 1937 len = hlen + dlen; 1938 1939 if (RX_COPY_ALWAYS || (words[2] & RX_COMP3_SMALL_PKT)) 1940 alloclen = len; 1941 else 1942 alloclen = max(hlen, RX_COPY_MIN); 1943 1944 skb = netdev_alloc_skb(cp->dev, alloclen + swivel + cp->crc_size); 1945 if (skb == NULL) 1946 return -1; 1947 1948 *skbref = skb; 1949 skb_reserve(skb, swivel); 1950 1951 p = skb->data; 1952 addr = crcaddr = NULL; 1953 if (hlen) { /* always copy header pages */ 1954 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); 1955 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1956 off = CAS_VAL(RX_COMP2_HDR_OFF, words[1]) * 0x100 + 1957 swivel; 1958 1959 i = hlen; 1960 if (!dlen) /* attach FCS */ 1961 i += cp->crc_size; 1962 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, 1963 i, DMA_FROM_DEVICE); 1964 addr = cas_page_map(page->buffer); 1965 memcpy(p, addr + off, i); 1966 dma_sync_single_for_device(&cp->pdev->dev, 1967 page->dma_addr + off, i, 1968 DMA_FROM_DEVICE); 1969 cas_page_unmap(addr); 1970 RX_USED_ADD(page, 0x100); 1971 p += hlen; 1972 swivel = 0; 1973 } 1974 1975 1976 if (alloclen < (hlen + dlen)) { 1977 skb_frag_t *frag = skb_shinfo(skb)->frags; 1978 1979 /* normal or jumbo packets. we use frags */ 1980 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 1981 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 1982 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; 1983 1984 hlen = min(cp->page_size - off, dlen); 1985 if (hlen < 0) { 1986 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 1987 "rx page overflow: %d\n", hlen); 1988 dev_kfree_skb_irq(skb); 1989 return -1; 1990 } 1991 i = hlen; 1992 if (i == dlen) /* attach FCS */ 1993 i += cp->crc_size; 1994 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, 1995 i, DMA_FROM_DEVICE); 1996 1997 /* make sure we always copy a header */ 1998 swivel = 0; 1999 if (p == (char *) skb->data) { /* not split */ 2000 addr = cas_page_map(page->buffer); 2001 memcpy(p, addr + off, RX_COPY_MIN); 2002 dma_sync_single_for_device(&cp->pdev->dev, 2003 page->dma_addr + off, i, 2004 DMA_FROM_DEVICE); 2005 cas_page_unmap(addr); 2006 off += RX_COPY_MIN; 2007 swivel = RX_COPY_MIN; 2008 RX_USED_ADD(page, cp->mtu_stride); 2009 } else { 2010 RX_USED_ADD(page, hlen); 2011 } 2012 skb_put(skb, alloclen); 2013 2014 skb_shinfo(skb)->nr_frags++; 2015 skb->data_len += hlen - swivel; 2016 skb->truesize += hlen - swivel; 2017 skb->len += hlen - swivel; 2018 2019 __skb_frag_set_page(frag, page->buffer); 2020 __skb_frag_ref(frag); 2021 skb_frag_off_set(frag, off); 2022 skb_frag_size_set(frag, hlen - swivel); 2023 2024 /* any more data? */ 2025 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { 2026 hlen = dlen; 2027 off = 0; 2028 2029 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2030 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 2031 dma_sync_single_for_cpu(&cp->pdev->dev, 2032 page->dma_addr, 2033 hlen + cp->crc_size, 2034 DMA_FROM_DEVICE); 2035 dma_sync_single_for_device(&cp->pdev->dev, 2036 page->dma_addr, 2037 hlen + cp->crc_size, 2038 DMA_FROM_DEVICE); 2039 2040 skb_shinfo(skb)->nr_frags++; 2041 skb->data_len += hlen; 2042 skb->len += hlen; 2043 frag++; 2044 2045 __skb_frag_set_page(frag, page->buffer); 2046 __skb_frag_ref(frag); 2047 skb_frag_off_set(frag, 0); 2048 skb_frag_size_set(frag, hlen); 2049 RX_USED_ADD(page, hlen + cp->crc_size); 2050 } 2051 2052 if (cp->crc_size) { 2053 addr = cas_page_map(page->buffer); 2054 crcaddr = addr + off + hlen; 2055 } 2056 2057 } else { 2058 /* copying packet */ 2059 if (!dlen) 2060 goto end_copy_pkt; 2061 2062 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 2063 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 2064 off = CAS_VAL(RX_COMP1_DATA_OFF, words[0]) + swivel; 2065 hlen = min(cp->page_size - off, dlen); 2066 if (hlen < 0) { 2067 netif_printk(cp, rx_err, KERN_DEBUG, cp->dev, 2068 "rx page overflow: %d\n", hlen); 2069 dev_kfree_skb_irq(skb); 2070 return -1; 2071 } 2072 i = hlen; 2073 if (i == dlen) /* attach FCS */ 2074 i += cp->crc_size; 2075 dma_sync_single_for_cpu(&cp->pdev->dev, page->dma_addr + off, 2076 i, DMA_FROM_DEVICE); 2077 addr = cas_page_map(page->buffer); 2078 memcpy(p, addr + off, i); 2079 dma_sync_single_for_device(&cp->pdev->dev, 2080 page->dma_addr + off, i, 2081 DMA_FROM_DEVICE); 2082 cas_page_unmap(addr); 2083 if (p == (char *) skb->data) /* not split */ 2084 RX_USED_ADD(page, cp->mtu_stride); 2085 else 2086 RX_USED_ADD(page, i); 2087 2088 /* any more data? */ 2089 if ((words[0] & RX_COMP1_SPLIT_PKT) && ((dlen -= hlen) > 0)) { 2090 p += hlen; 2091 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2092 page = cp->rx_pages[CAS_VAL(RX_INDEX_RING, i)][CAS_VAL(RX_INDEX_NUM, i)]; 2093 dma_sync_single_for_cpu(&cp->pdev->dev, 2094 page->dma_addr, 2095 dlen + cp->crc_size, 2096 DMA_FROM_DEVICE); 2097 addr = cas_page_map(page->buffer); 2098 memcpy(p, addr, dlen + cp->crc_size); 2099 dma_sync_single_for_device(&cp->pdev->dev, 2100 page->dma_addr, 2101 dlen + cp->crc_size, 2102 DMA_FROM_DEVICE); 2103 cas_page_unmap(addr); 2104 RX_USED_ADD(page, dlen + cp->crc_size); 2105 } 2106 end_copy_pkt: 2107 if (cp->crc_size) { 2108 addr = NULL; 2109 crcaddr = skb->data + alloclen; 2110 } 2111 skb_put(skb, alloclen); 2112 } 2113 2114 csum = (__force __sum16)htons(CAS_VAL(RX_COMP4_TCP_CSUM, words[3])); 2115 if (cp->crc_size) { 2116 /* checksum includes FCS. strip it out. */ 2117 csum = csum_fold(csum_partial(crcaddr, cp->crc_size, 2118 csum_unfold(csum))); 2119 if (addr) 2120 cas_page_unmap(addr); 2121 } 2122 skb->protocol = eth_type_trans(skb, cp->dev); 2123 if (skb->protocol == htons(ETH_P_IP)) { 2124 skb->csum = csum_unfold(~csum); 2125 skb->ip_summed = CHECKSUM_COMPLETE; 2126 } else 2127 skb_checksum_none_assert(skb); 2128 return len; 2129 } 2130 2131 2132 /* we can handle up to 64 rx flows at a time. we do the same thing 2133 * as nonreassm except that we batch up the buffers. 2134 * NOTE: we currently just treat each flow as a bunch of packets that 2135 * we pass up. a better way would be to coalesce the packets 2136 * into a jumbo packet. to do that, we need to do the following: 2137 * 1) the first packet will have a clean split between header and 2138 * data. save both. 2139 * 2) each time the next flow packet comes in, extend the 2140 * data length and merge the checksums. 2141 * 3) on flow release, fix up the header. 2142 * 4) make sure the higher layer doesn't care. 2143 * because packets get coalesced, we shouldn't run into fragment count 2144 * issues. 2145 */ 2146 static inline void cas_rx_flow_pkt(struct cas *cp, const u64 *words, 2147 struct sk_buff *skb) 2148 { 2149 int flowid = CAS_VAL(RX_COMP3_FLOWID, words[2]) & (N_RX_FLOWS - 1); 2150 struct sk_buff_head *flow = &cp->rx_flows[flowid]; 2151 2152 /* this is protected at a higher layer, so no need to 2153 * do any additional locking here. stick the buffer 2154 * at the end. 2155 */ 2156 __skb_queue_tail(flow, skb); 2157 if (words[0] & RX_COMP1_RELEASE_FLOW) { 2158 while ((skb = __skb_dequeue(flow))) { 2159 cas_skb_release(skb); 2160 } 2161 } 2162 } 2163 2164 /* put rx descriptor back on ring. if a buffer is in use by a higher 2165 * layer, this will need to put in a replacement. 2166 */ 2167 static void cas_post_page(struct cas *cp, const int ring, const int index) 2168 { 2169 cas_page_t *new; 2170 int entry; 2171 2172 entry = cp->rx_old[ring]; 2173 2174 new = cas_page_swap(cp, ring, index); 2175 cp->init_rxds[ring][entry].buffer = cpu_to_le64(new->dma_addr); 2176 cp->init_rxds[ring][entry].index = 2177 cpu_to_le64(CAS_BASE(RX_INDEX_NUM, index) | 2178 CAS_BASE(RX_INDEX_RING, ring)); 2179 2180 entry = RX_DESC_ENTRY(ring, entry + 1); 2181 cp->rx_old[ring] = entry; 2182 2183 if (entry % 4) 2184 return; 2185 2186 if (ring == 0) 2187 writel(entry, cp->regs + REG_RX_KICK); 2188 else if ((N_RX_DESC_RINGS > 1) && 2189 (cp->cas_flags & CAS_FLAG_REG_PLUS)) 2190 writel(entry, cp->regs + REG_PLUS_RX_KICK1); 2191 } 2192 2193 2194 /* only when things are bad */ 2195 static int cas_post_rxds_ringN(struct cas *cp, int ring, int num) 2196 { 2197 unsigned int entry, last, count, released; 2198 int cluster; 2199 cas_page_t **page = cp->rx_pages[ring]; 2200 2201 entry = cp->rx_old[ring]; 2202 2203 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 2204 "rxd[%d] interrupt, done: %d\n", ring, entry); 2205 2206 cluster = -1; 2207 count = entry & 0x3; 2208 last = RX_DESC_ENTRY(ring, num ? entry + num - 4: entry - 4); 2209 released = 0; 2210 while (entry != last) { 2211 /* make a new buffer if it's still in use */ 2212 if (page_count(page[entry]->buffer) > 1) { 2213 cas_page_t *new = cas_page_dequeue(cp); 2214 if (!new) { 2215 /* let the timer know that we need to 2216 * do this again 2217 */ 2218 cp->cas_flags |= CAS_FLAG_RXD_POST(ring); 2219 if (!timer_pending(&cp->link_timer)) 2220 mod_timer(&cp->link_timer, jiffies + 2221 CAS_LINK_FAST_TIMEOUT); 2222 cp->rx_old[ring] = entry; 2223 cp->rx_last[ring] = num ? num - released : 0; 2224 return -ENOMEM; 2225 } 2226 spin_lock(&cp->rx_inuse_lock); 2227 list_add(&page[entry]->list, &cp->rx_inuse_list); 2228 spin_unlock(&cp->rx_inuse_lock); 2229 cp->init_rxds[ring][entry].buffer = 2230 cpu_to_le64(new->dma_addr); 2231 page[entry] = new; 2232 2233 } 2234 2235 if (++count == 4) { 2236 cluster = entry; 2237 count = 0; 2238 } 2239 released++; 2240 entry = RX_DESC_ENTRY(ring, entry + 1); 2241 } 2242 cp->rx_old[ring] = entry; 2243 2244 if (cluster < 0) 2245 return 0; 2246 2247 if (ring == 0) 2248 writel(cluster, cp->regs + REG_RX_KICK); 2249 else if ((N_RX_DESC_RINGS > 1) && 2250 (cp->cas_flags & CAS_FLAG_REG_PLUS)) 2251 writel(cluster, cp->regs + REG_PLUS_RX_KICK1); 2252 return 0; 2253 } 2254 2255 2256 /* process a completion ring. packets are set up in three basic ways: 2257 * small packets: should be copied header + data in single buffer. 2258 * large packets: header and data in a single buffer. 2259 * split packets: header in a separate buffer from data. 2260 * data may be in multiple pages. data may be > 256 2261 * bytes but in a single page. 2262 * 2263 * NOTE: RX page posting is done in this routine as well. while there's 2264 * the capability of using multiple RX completion rings, it isn't 2265 * really worthwhile due to the fact that the page posting will 2266 * force serialization on the single descriptor ring. 2267 */ 2268 static int cas_rx_ringN(struct cas *cp, int ring, int budget) 2269 { 2270 struct cas_rx_comp *rxcs = cp->init_rxcs[ring]; 2271 int entry, drops; 2272 int npackets = 0; 2273 2274 netif_printk(cp, intr, KERN_DEBUG, cp->dev, 2275 "rx[%d] interrupt, done: %d/%d\n", 2276 ring, 2277 readl(cp->regs + REG_RX_COMP_HEAD), cp->rx_new[ring]); 2278 2279 entry = cp->rx_new[ring]; 2280 drops = 0; 2281 while (1) { 2282 struct cas_rx_comp *rxc = rxcs + entry; 2283 struct sk_buff *skb; 2284 int type, len; 2285 u64 words[4]; 2286 int i, dring; 2287 2288 words[0] = le64_to_cpu(rxc->word1); 2289 words[1] = le64_to_cpu(rxc->word2); 2290 words[2] = le64_to_cpu(rxc->word3); 2291 words[3] = le64_to_cpu(rxc->word4); 2292 2293 /* don't touch if still owned by hw */ 2294 type = CAS_VAL(RX_COMP1_TYPE, words[0]); 2295 if (type == 0) 2296 break; 2297 2298 /* hw hasn't cleared the zero bit yet */ 2299 if (words[3] & RX_COMP4_ZERO) { 2300 break; 2301 } 2302 2303 /* get info on the packet */ 2304 if (words[3] & (RX_COMP4_LEN_MISMATCH | RX_COMP4_BAD)) { 2305 spin_lock(&cp->stat_lock[ring]); 2306 cp->net_stats[ring].rx_errors++; 2307 if (words[3] & RX_COMP4_LEN_MISMATCH) 2308 cp->net_stats[ring].rx_length_errors++; 2309 if (words[3] & RX_COMP4_BAD) 2310 cp->net_stats[ring].rx_crc_errors++; 2311 spin_unlock(&cp->stat_lock[ring]); 2312 2313 /* We'll just return it to Cassini. */ 2314 drop_it: 2315 spin_lock(&cp->stat_lock[ring]); 2316 ++cp->net_stats[ring].rx_dropped; 2317 spin_unlock(&cp->stat_lock[ring]); 2318 goto next; 2319 } 2320 2321 len = cas_rx_process_pkt(cp, rxc, entry, words, &skb); 2322 if (len < 0) { 2323 ++drops; 2324 goto drop_it; 2325 } 2326 2327 /* see if it's a flow re-assembly or not. the driver 2328 * itself handles release back up. 2329 */ 2330 if (RX_DONT_BATCH || (type == 0x2)) { 2331 /* non-reassm: these always get released */ 2332 cas_skb_release(skb); 2333 } else { 2334 cas_rx_flow_pkt(cp, words, skb); 2335 } 2336 2337 spin_lock(&cp->stat_lock[ring]); 2338 cp->net_stats[ring].rx_packets++; 2339 cp->net_stats[ring].rx_bytes += len; 2340 spin_unlock(&cp->stat_lock[ring]); 2341 2342 next: 2343 npackets++; 2344 2345 /* should it be released? */ 2346 if (words[0] & RX_COMP1_RELEASE_HDR) { 2347 i = CAS_VAL(RX_COMP2_HDR_INDEX, words[1]); 2348 dring = CAS_VAL(RX_INDEX_RING, i); 2349 i = CAS_VAL(RX_INDEX_NUM, i); 2350 cas_post_page(cp, dring, i); 2351 } 2352 2353 if (words[0] & RX_COMP1_RELEASE_DATA) { 2354 i = CAS_VAL(RX_COMP1_DATA_INDEX, words[0]); 2355 dring = CAS_VAL(RX_INDEX_RING, i); 2356 i = CAS_VAL(RX_INDEX_NUM, i); 2357 cas_post_page(cp, dring, i); 2358 } 2359 2360 if (words[0] & RX_COMP1_RELEASE_NEXT) { 2361 i = CAS_VAL(RX_COMP2_NEXT_INDEX, words[1]); 2362 dring = CAS_VAL(RX_INDEX_RING, i); 2363 i = CAS_VAL(RX_INDEX_NUM, i); 2364 cas_post_page(cp, dring, i); 2365 } 2366 2367 /* skip to the next entry */ 2368 entry = RX_COMP_ENTRY(ring, entry + 1 + 2369 CAS_VAL(RX_COMP1_SKIP, words[0])); 2370 #ifdef USE_NAPI 2371 if (budget && (npackets >= budget)) 2372 break; 2373 #endif 2374 } 2375 cp->rx_new[ring] = entry; 2376 2377 if (drops) 2378 netdev_info(cp->dev, "Memory squeeze, deferring packet\n"); 2379 return npackets; 2380 } 2381 2382 2383 /* put completion entries back on the ring */ 2384 static void cas_post_rxcs_ringN(struct net_device *dev, 2385 struct cas *cp, int ring) 2386 { 2387 struct cas_rx_comp *rxc = cp->init_rxcs[ring]; 2388 int last, entry; 2389 2390 last = cp->rx_cur[ring]; 2391 entry = cp->rx_new[ring]; 2392 netif_printk(cp, intr, KERN_DEBUG, dev, 2393 "rxc[%d] interrupt, done: %d/%d\n", 2394 ring, readl(cp->regs + REG_RX_COMP_HEAD), entry); 2395 2396 /* zero and re-mark descriptors */ 2397 while (last != entry) { 2398 cas_rxc_init(rxc + last); 2399 last = RX_COMP_ENTRY(ring, last + 1); 2400 } 2401 cp->rx_cur[ring] = last; 2402 2403 if (ring == 0) 2404 writel(last, cp->regs + REG_RX_COMP_TAIL); 2405 else if (cp->cas_flags & CAS_FLAG_REG_PLUS) 2406 writel(last, cp->regs + REG_PLUS_RX_COMPN_TAIL(ring)); 2407 } 2408 2409 2410 2411 /* cassini can use all four PCI interrupts for the completion ring. 2412 * rings 3 and 4 are identical 2413 */ 2414 #if defined(USE_PCI_INTC) || defined(USE_PCI_INTD) 2415 static inline void cas_handle_irqN(struct net_device *dev, 2416 struct cas *cp, const u32 status, 2417 const int ring) 2418 { 2419 if (status & (INTR_RX_COMP_FULL_ALT | INTR_RX_COMP_AF_ALT)) 2420 cas_post_rxcs_ringN(dev, cp, ring); 2421 } 2422 2423 static irqreturn_t cas_interruptN(int irq, void *dev_id) 2424 { 2425 struct net_device *dev = dev_id; 2426 struct cas *cp = netdev_priv(dev); 2427 unsigned long flags; 2428 int ring = (irq == cp->pci_irq_INTC) ? 2 : 3; 2429 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(ring)); 2430 2431 /* check for shared irq */ 2432 if (status == 0) 2433 return IRQ_NONE; 2434 2435 spin_lock_irqsave(&cp->lock, flags); 2436 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ 2437 #ifdef USE_NAPI 2438 cas_mask_intr(cp); 2439 napi_schedule(&cp->napi); 2440 #else 2441 cas_rx_ringN(cp, ring, 0); 2442 #endif 2443 status &= ~INTR_RX_DONE_ALT; 2444 } 2445 2446 if (status) 2447 cas_handle_irqN(dev, cp, status, ring); 2448 spin_unlock_irqrestore(&cp->lock, flags); 2449 return IRQ_HANDLED; 2450 } 2451 #endif 2452 2453 #ifdef USE_PCI_INTB 2454 /* everything but rx packets */ 2455 static inline void cas_handle_irq1(struct cas *cp, const u32 status) 2456 { 2457 if (status & INTR_RX_BUF_UNAVAIL_1) { 2458 /* Frame arrived, no free RX buffers available. 2459 * NOTE: we can get this on a link transition. */ 2460 cas_post_rxds_ringN(cp, 1, 0); 2461 spin_lock(&cp->stat_lock[1]); 2462 cp->net_stats[1].rx_dropped++; 2463 spin_unlock(&cp->stat_lock[1]); 2464 } 2465 2466 if (status & INTR_RX_BUF_AE_1) 2467 cas_post_rxds_ringN(cp, 1, RX_DESC_RINGN_SIZE(1) - 2468 RX_AE_FREEN_VAL(1)); 2469 2470 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) 2471 cas_post_rxcs_ringN(cp, 1); 2472 } 2473 2474 /* ring 2 handles a few more events than 3 and 4 */ 2475 static irqreturn_t cas_interrupt1(int irq, void *dev_id) 2476 { 2477 struct net_device *dev = dev_id; 2478 struct cas *cp = netdev_priv(dev); 2479 unsigned long flags; 2480 u32 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); 2481 2482 /* check for shared interrupt */ 2483 if (status == 0) 2484 return IRQ_NONE; 2485 2486 spin_lock_irqsave(&cp->lock, flags); 2487 if (status & INTR_RX_DONE_ALT) { /* handle rx separately */ 2488 #ifdef USE_NAPI 2489 cas_mask_intr(cp); 2490 napi_schedule(&cp->napi); 2491 #else 2492 cas_rx_ringN(cp, 1, 0); 2493 #endif 2494 status &= ~INTR_RX_DONE_ALT; 2495 } 2496 if (status) 2497 cas_handle_irq1(cp, status); 2498 spin_unlock_irqrestore(&cp->lock, flags); 2499 return IRQ_HANDLED; 2500 } 2501 #endif 2502 2503 static inline void cas_handle_irq(struct net_device *dev, 2504 struct cas *cp, const u32 status) 2505 { 2506 /* housekeeping interrupts */ 2507 if (status & INTR_ERROR_MASK) 2508 cas_abnormal_irq(dev, cp, status); 2509 2510 if (status & INTR_RX_BUF_UNAVAIL) { 2511 /* Frame arrived, no free RX buffers available. 2512 * NOTE: we can get this on a link transition. 2513 */ 2514 cas_post_rxds_ringN(cp, 0, 0); 2515 spin_lock(&cp->stat_lock[0]); 2516 cp->net_stats[0].rx_dropped++; 2517 spin_unlock(&cp->stat_lock[0]); 2518 } else if (status & INTR_RX_BUF_AE) { 2519 cas_post_rxds_ringN(cp, 0, RX_DESC_RINGN_SIZE(0) - 2520 RX_AE_FREEN_VAL(0)); 2521 } 2522 2523 if (status & (INTR_RX_COMP_AF | INTR_RX_COMP_FULL)) 2524 cas_post_rxcs_ringN(dev, cp, 0); 2525 } 2526 2527 static irqreturn_t cas_interrupt(int irq, void *dev_id) 2528 { 2529 struct net_device *dev = dev_id; 2530 struct cas *cp = netdev_priv(dev); 2531 unsigned long flags; 2532 u32 status = readl(cp->regs + REG_INTR_STATUS); 2533 2534 if (status == 0) 2535 return IRQ_NONE; 2536 2537 spin_lock_irqsave(&cp->lock, flags); 2538 if (status & (INTR_TX_ALL | INTR_TX_INTME)) { 2539 cas_tx(dev, cp, status); 2540 status &= ~(INTR_TX_ALL | INTR_TX_INTME); 2541 } 2542 2543 if (status & INTR_RX_DONE) { 2544 #ifdef USE_NAPI 2545 cas_mask_intr(cp); 2546 napi_schedule(&cp->napi); 2547 #else 2548 cas_rx_ringN(cp, 0, 0); 2549 #endif 2550 status &= ~INTR_RX_DONE; 2551 } 2552 2553 if (status) 2554 cas_handle_irq(dev, cp, status); 2555 spin_unlock_irqrestore(&cp->lock, flags); 2556 return IRQ_HANDLED; 2557 } 2558 2559 2560 #ifdef USE_NAPI 2561 static int cas_poll(struct napi_struct *napi, int budget) 2562 { 2563 struct cas *cp = container_of(napi, struct cas, napi); 2564 struct net_device *dev = cp->dev; 2565 int i, enable_intr, credits; 2566 u32 status = readl(cp->regs + REG_INTR_STATUS); 2567 unsigned long flags; 2568 2569 spin_lock_irqsave(&cp->lock, flags); 2570 cas_tx(dev, cp, status); 2571 spin_unlock_irqrestore(&cp->lock, flags); 2572 2573 /* NAPI rx packets. we spread the credits across all of the 2574 * rxc rings 2575 * 2576 * to make sure we're fair with the work we loop through each 2577 * ring N_RX_COMP_RING times with a request of 2578 * budget / N_RX_COMP_RINGS 2579 */ 2580 enable_intr = 1; 2581 credits = 0; 2582 for (i = 0; i < N_RX_COMP_RINGS; i++) { 2583 int j; 2584 for (j = 0; j < N_RX_COMP_RINGS; j++) { 2585 credits += cas_rx_ringN(cp, j, budget / N_RX_COMP_RINGS); 2586 if (credits >= budget) { 2587 enable_intr = 0; 2588 goto rx_comp; 2589 } 2590 } 2591 } 2592 2593 rx_comp: 2594 /* final rx completion */ 2595 spin_lock_irqsave(&cp->lock, flags); 2596 if (status) 2597 cas_handle_irq(dev, cp, status); 2598 2599 #ifdef USE_PCI_INTB 2600 if (N_RX_COMP_RINGS > 1) { 2601 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(1)); 2602 if (status) 2603 cas_handle_irq1(dev, cp, status); 2604 } 2605 #endif 2606 2607 #ifdef USE_PCI_INTC 2608 if (N_RX_COMP_RINGS > 2) { 2609 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(2)); 2610 if (status) 2611 cas_handle_irqN(dev, cp, status, 2); 2612 } 2613 #endif 2614 2615 #ifdef USE_PCI_INTD 2616 if (N_RX_COMP_RINGS > 3) { 2617 status = readl(cp->regs + REG_PLUS_INTRN_STATUS(3)); 2618 if (status) 2619 cas_handle_irqN(dev, cp, status, 3); 2620 } 2621 #endif 2622 spin_unlock_irqrestore(&cp->lock, flags); 2623 if (enable_intr) { 2624 napi_complete(napi); 2625 cas_unmask_intr(cp); 2626 } 2627 return credits; 2628 } 2629 #endif 2630 2631 #ifdef CONFIG_NET_POLL_CONTROLLER 2632 static void cas_netpoll(struct net_device *dev) 2633 { 2634 struct cas *cp = netdev_priv(dev); 2635 2636 cas_disable_irq(cp, 0); 2637 cas_interrupt(cp->pdev->irq, dev); 2638 cas_enable_irq(cp, 0); 2639 2640 #ifdef USE_PCI_INTB 2641 if (N_RX_COMP_RINGS > 1) { 2642 /* cas_interrupt1(); */ 2643 } 2644 #endif 2645 #ifdef USE_PCI_INTC 2646 if (N_RX_COMP_RINGS > 2) { 2647 /* cas_interruptN(); */ 2648 } 2649 #endif 2650 #ifdef USE_PCI_INTD 2651 if (N_RX_COMP_RINGS > 3) { 2652 /* cas_interruptN(); */ 2653 } 2654 #endif 2655 } 2656 #endif 2657 2658 static void cas_tx_timeout(struct net_device *dev, unsigned int txqueue) 2659 { 2660 struct cas *cp = netdev_priv(dev); 2661 2662 netdev_err(dev, "transmit timed out, resetting\n"); 2663 if (!cp->hw_running) { 2664 netdev_err(dev, "hrm.. hw not running!\n"); 2665 return; 2666 } 2667 2668 netdev_err(dev, "MIF_STATE[%08x]\n", 2669 readl(cp->regs + REG_MIF_STATE_MACHINE)); 2670 2671 netdev_err(dev, "MAC_STATE[%08x]\n", 2672 readl(cp->regs + REG_MAC_STATE_MACHINE)); 2673 2674 netdev_err(dev, "TX_STATE[%08x:%08x:%08x] FIFO[%08x:%08x:%08x] SM1[%08x] SM2[%08x]\n", 2675 readl(cp->regs + REG_TX_CFG), 2676 readl(cp->regs + REG_MAC_TX_STATUS), 2677 readl(cp->regs + REG_MAC_TX_CFG), 2678 readl(cp->regs + REG_TX_FIFO_PKT_CNT), 2679 readl(cp->regs + REG_TX_FIFO_WRITE_PTR), 2680 readl(cp->regs + REG_TX_FIFO_READ_PTR), 2681 readl(cp->regs + REG_TX_SM_1), 2682 readl(cp->regs + REG_TX_SM_2)); 2683 2684 netdev_err(dev, "RX_STATE[%08x:%08x:%08x]\n", 2685 readl(cp->regs + REG_RX_CFG), 2686 readl(cp->regs + REG_MAC_RX_STATUS), 2687 readl(cp->regs + REG_MAC_RX_CFG)); 2688 2689 netdev_err(dev, "HP_STATE[%08x:%08x:%08x:%08x]\n", 2690 readl(cp->regs + REG_HP_STATE_MACHINE), 2691 readl(cp->regs + REG_HP_STATUS0), 2692 readl(cp->regs + REG_HP_STATUS1), 2693 readl(cp->regs + REG_HP_STATUS2)); 2694 2695 #if 1 2696 atomic_inc(&cp->reset_task_pending); 2697 atomic_inc(&cp->reset_task_pending_all); 2698 schedule_work(&cp->reset_task); 2699 #else 2700 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); 2701 schedule_work(&cp->reset_task); 2702 #endif 2703 } 2704 2705 static inline int cas_intme(int ring, int entry) 2706 { 2707 /* Algorithm: IRQ every 1/2 of descriptors. */ 2708 if (!(entry & ((TX_DESC_RINGN_SIZE(ring) >> 1) - 1))) 2709 return 1; 2710 return 0; 2711 } 2712 2713 2714 static void cas_write_txd(struct cas *cp, int ring, int entry, 2715 dma_addr_t mapping, int len, u64 ctrl, int last) 2716 { 2717 struct cas_tx_desc *txd = cp->init_txds[ring] + entry; 2718 2719 ctrl |= CAS_BASE(TX_DESC_BUFLEN, len); 2720 if (cas_intme(ring, entry)) 2721 ctrl |= TX_DESC_INTME; 2722 if (last) 2723 ctrl |= TX_DESC_EOF; 2724 txd->control = cpu_to_le64(ctrl); 2725 txd->buffer = cpu_to_le64(mapping); 2726 } 2727 2728 static inline void *tx_tiny_buf(struct cas *cp, const int ring, 2729 const int entry) 2730 { 2731 return cp->tx_tiny_bufs[ring] + TX_TINY_BUF_LEN*entry; 2732 } 2733 2734 static inline dma_addr_t tx_tiny_map(struct cas *cp, const int ring, 2735 const int entry, const int tentry) 2736 { 2737 cp->tx_tiny_use[ring][tentry].nbufs++; 2738 cp->tx_tiny_use[ring][entry].used = 1; 2739 return cp->tx_tiny_dvma[ring] + TX_TINY_BUF_LEN*entry; 2740 } 2741 2742 static inline int cas_xmit_tx_ringN(struct cas *cp, int ring, 2743 struct sk_buff *skb) 2744 { 2745 struct net_device *dev = cp->dev; 2746 int entry, nr_frags, frag, tabort, tentry; 2747 dma_addr_t mapping; 2748 unsigned long flags; 2749 u64 ctrl; 2750 u32 len; 2751 2752 spin_lock_irqsave(&cp->tx_lock[ring], flags); 2753 2754 /* This is a hard error, log it. */ 2755 if (TX_BUFFS_AVAIL(cp, ring) <= 2756 CAS_TABORT(cp)*(skb_shinfo(skb)->nr_frags + 1)) { 2757 netif_stop_queue(dev); 2758 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); 2759 netdev_err(dev, "BUG! Tx Ring full when queue awake!\n"); 2760 return 1; 2761 } 2762 2763 ctrl = 0; 2764 if (skb->ip_summed == CHECKSUM_PARTIAL) { 2765 const u64 csum_start_off = skb_checksum_start_offset(skb); 2766 const u64 csum_stuff_off = csum_start_off + skb->csum_offset; 2767 2768 ctrl = TX_DESC_CSUM_EN | 2769 CAS_BASE(TX_DESC_CSUM_START, csum_start_off) | 2770 CAS_BASE(TX_DESC_CSUM_STUFF, csum_stuff_off); 2771 } 2772 2773 entry = cp->tx_new[ring]; 2774 cp->tx_skbs[ring][entry] = skb; 2775 2776 nr_frags = skb_shinfo(skb)->nr_frags; 2777 len = skb_headlen(skb); 2778 mapping = dma_map_page(&cp->pdev->dev, virt_to_page(skb->data), 2779 offset_in_page(skb->data), len, DMA_TO_DEVICE); 2780 2781 tentry = entry; 2782 tabort = cas_calc_tabort(cp, (unsigned long) skb->data, len); 2783 if (unlikely(tabort)) { 2784 /* NOTE: len is always > tabort */ 2785 cas_write_txd(cp, ring, entry, mapping, len - tabort, 2786 ctrl | TX_DESC_SOF, 0); 2787 entry = TX_DESC_NEXT(ring, entry); 2788 2789 skb_copy_from_linear_data_offset(skb, len - tabort, 2790 tx_tiny_buf(cp, ring, entry), tabort); 2791 mapping = tx_tiny_map(cp, ring, entry, tentry); 2792 cas_write_txd(cp, ring, entry, mapping, tabort, ctrl, 2793 (nr_frags == 0)); 2794 } else { 2795 cas_write_txd(cp, ring, entry, mapping, len, ctrl | 2796 TX_DESC_SOF, (nr_frags == 0)); 2797 } 2798 entry = TX_DESC_NEXT(ring, entry); 2799 2800 for (frag = 0; frag < nr_frags; frag++) { 2801 const skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag]; 2802 2803 len = skb_frag_size(fragp); 2804 mapping = skb_frag_dma_map(&cp->pdev->dev, fragp, 0, len, 2805 DMA_TO_DEVICE); 2806 2807 tabort = cas_calc_tabort(cp, skb_frag_off(fragp), len); 2808 if (unlikely(tabort)) { 2809 void *addr; 2810 2811 /* NOTE: len is always > tabort */ 2812 cas_write_txd(cp, ring, entry, mapping, len - tabort, 2813 ctrl, 0); 2814 entry = TX_DESC_NEXT(ring, entry); 2815 2816 addr = cas_page_map(skb_frag_page(fragp)); 2817 memcpy(tx_tiny_buf(cp, ring, entry), 2818 addr + skb_frag_off(fragp) + len - tabort, 2819 tabort); 2820 cas_page_unmap(addr); 2821 mapping = tx_tiny_map(cp, ring, entry, tentry); 2822 len = tabort; 2823 } 2824 2825 cas_write_txd(cp, ring, entry, mapping, len, ctrl, 2826 (frag + 1 == nr_frags)); 2827 entry = TX_DESC_NEXT(ring, entry); 2828 } 2829 2830 cp->tx_new[ring] = entry; 2831 if (TX_BUFFS_AVAIL(cp, ring) <= CAS_TABORT(cp)*(MAX_SKB_FRAGS + 1)) 2832 netif_stop_queue(dev); 2833 2834 netif_printk(cp, tx_queued, KERN_DEBUG, dev, 2835 "tx[%d] queued, slot %d, skblen %d, avail %d\n", 2836 ring, entry, skb->len, TX_BUFFS_AVAIL(cp, ring)); 2837 writel(entry, cp->regs + REG_TX_KICKN(ring)); 2838 spin_unlock_irqrestore(&cp->tx_lock[ring], flags); 2839 return 0; 2840 } 2841 2842 static netdev_tx_t cas_start_xmit(struct sk_buff *skb, struct net_device *dev) 2843 { 2844 struct cas *cp = netdev_priv(dev); 2845 2846 /* this is only used as a load-balancing hint, so it doesn't 2847 * need to be SMP safe 2848 */ 2849 static int ring; 2850 2851 if (skb_padto(skb, cp->min_frame_size)) 2852 return NETDEV_TX_OK; 2853 2854 /* XXX: we need some higher-level QoS hooks to steer packets to 2855 * individual queues. 2856 */ 2857 if (cas_xmit_tx_ringN(cp, ring++ & N_TX_RINGS_MASK, skb)) 2858 return NETDEV_TX_BUSY; 2859 return NETDEV_TX_OK; 2860 } 2861 2862 static void cas_init_tx_dma(struct cas *cp) 2863 { 2864 u64 desc_dma = cp->block_dvma; 2865 unsigned long off; 2866 u32 val; 2867 int i; 2868 2869 /* set up tx completion writeback registers. must be 8-byte aligned */ 2870 #ifdef USE_TX_COMPWB 2871 off = offsetof(struct cas_init_block, tx_compwb); 2872 writel((desc_dma + off) >> 32, cp->regs + REG_TX_COMPWB_DB_HI); 2873 writel((desc_dma + off) & 0xffffffff, cp->regs + REG_TX_COMPWB_DB_LOW); 2874 #endif 2875 2876 /* enable completion writebacks, enable paced mode, 2877 * disable read pipe, and disable pre-interrupt compwbs 2878 */ 2879 val = TX_CFG_COMPWB_Q1 | TX_CFG_COMPWB_Q2 | 2880 TX_CFG_COMPWB_Q3 | TX_CFG_COMPWB_Q4 | 2881 TX_CFG_DMA_RDPIPE_DIS | TX_CFG_PACED_MODE | 2882 TX_CFG_INTR_COMPWB_DIS; 2883 2884 /* write out tx ring info and tx desc bases */ 2885 for (i = 0; i < MAX_TX_RINGS; i++) { 2886 off = (unsigned long) cp->init_txds[i] - 2887 (unsigned long) cp->init_block; 2888 2889 val |= CAS_TX_RINGN_BASE(i); 2890 writel((desc_dma + off) >> 32, cp->regs + REG_TX_DBN_HI(i)); 2891 writel((desc_dma + off) & 0xffffffff, cp->regs + 2892 REG_TX_DBN_LOW(i)); 2893 /* don't zero out the kick register here as the system 2894 * will wedge 2895 */ 2896 } 2897 writel(val, cp->regs + REG_TX_CFG); 2898 2899 /* program max burst sizes. these numbers should be different 2900 * if doing QoS. 2901 */ 2902 #ifdef USE_QOS 2903 writel(0x800, cp->regs + REG_TX_MAXBURST_0); 2904 writel(0x1600, cp->regs + REG_TX_MAXBURST_1); 2905 writel(0x2400, cp->regs + REG_TX_MAXBURST_2); 2906 writel(0x4800, cp->regs + REG_TX_MAXBURST_3); 2907 #else 2908 writel(0x800, cp->regs + REG_TX_MAXBURST_0); 2909 writel(0x800, cp->regs + REG_TX_MAXBURST_1); 2910 writel(0x800, cp->regs + REG_TX_MAXBURST_2); 2911 writel(0x800, cp->regs + REG_TX_MAXBURST_3); 2912 #endif 2913 } 2914 2915 /* Must be invoked under cp->lock. */ 2916 static inline void cas_init_dma(struct cas *cp) 2917 { 2918 cas_init_tx_dma(cp); 2919 cas_init_rx_dma(cp); 2920 } 2921 2922 static void cas_process_mc_list(struct cas *cp) 2923 { 2924 u16 hash_table[16]; 2925 u32 crc; 2926 struct netdev_hw_addr *ha; 2927 int i = 1; 2928 2929 memset(hash_table, 0, sizeof(hash_table)); 2930 netdev_for_each_mc_addr(ha, cp->dev) { 2931 if (i <= CAS_MC_EXACT_MATCH_SIZE) { 2932 /* use the alternate mac address registers for the 2933 * first 15 multicast addresses 2934 */ 2935 writel((ha->addr[4] << 8) | ha->addr[5], 2936 cp->regs + REG_MAC_ADDRN(i*3 + 0)); 2937 writel((ha->addr[2] << 8) | ha->addr[3], 2938 cp->regs + REG_MAC_ADDRN(i*3 + 1)); 2939 writel((ha->addr[0] << 8) | ha->addr[1], 2940 cp->regs + REG_MAC_ADDRN(i*3 + 2)); 2941 i++; 2942 } 2943 else { 2944 /* use hw hash table for the next series of 2945 * multicast addresses 2946 */ 2947 crc = ether_crc_le(ETH_ALEN, ha->addr); 2948 crc >>= 24; 2949 hash_table[crc >> 4] |= 1 << (15 - (crc & 0xf)); 2950 } 2951 } 2952 for (i = 0; i < 16; i++) 2953 writel(hash_table[i], cp->regs + REG_MAC_HASH_TABLEN(i)); 2954 } 2955 2956 /* Must be invoked under cp->lock. */ 2957 static u32 cas_setup_multicast(struct cas *cp) 2958 { 2959 u32 rxcfg = 0; 2960 int i; 2961 2962 if (cp->dev->flags & IFF_PROMISC) { 2963 rxcfg |= MAC_RX_CFG_PROMISC_EN; 2964 2965 } else if (cp->dev->flags & IFF_ALLMULTI) { 2966 for (i=0; i < 16; i++) 2967 writel(0xFFFF, cp->regs + REG_MAC_HASH_TABLEN(i)); 2968 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; 2969 2970 } else { 2971 cas_process_mc_list(cp); 2972 rxcfg |= MAC_RX_CFG_HASH_FILTER_EN; 2973 } 2974 2975 return rxcfg; 2976 } 2977 2978 /* must be invoked under cp->stat_lock[N_TX_RINGS] */ 2979 static void cas_clear_mac_err(struct cas *cp) 2980 { 2981 writel(0, cp->regs + REG_MAC_COLL_NORMAL); 2982 writel(0, cp->regs + REG_MAC_COLL_FIRST); 2983 writel(0, cp->regs + REG_MAC_COLL_EXCESS); 2984 writel(0, cp->regs + REG_MAC_COLL_LATE); 2985 writel(0, cp->regs + REG_MAC_TIMER_DEFER); 2986 writel(0, cp->regs + REG_MAC_ATTEMPTS_PEAK); 2987 writel(0, cp->regs + REG_MAC_RECV_FRAME); 2988 writel(0, cp->regs + REG_MAC_LEN_ERR); 2989 writel(0, cp->regs + REG_MAC_ALIGN_ERR); 2990 writel(0, cp->regs + REG_MAC_FCS_ERR); 2991 writel(0, cp->regs + REG_MAC_RX_CODE_ERR); 2992 } 2993 2994 2995 static void cas_mac_reset(struct cas *cp) 2996 { 2997 int i; 2998 2999 /* do both TX and RX reset */ 3000 writel(0x1, cp->regs + REG_MAC_TX_RESET); 3001 writel(0x1, cp->regs + REG_MAC_RX_RESET); 3002 3003 /* wait for TX */ 3004 i = STOP_TRIES; 3005 while (i-- > 0) { 3006 if (readl(cp->regs + REG_MAC_TX_RESET) == 0) 3007 break; 3008 udelay(10); 3009 } 3010 3011 /* wait for RX */ 3012 i = STOP_TRIES; 3013 while (i-- > 0) { 3014 if (readl(cp->regs + REG_MAC_RX_RESET) == 0) 3015 break; 3016 udelay(10); 3017 } 3018 3019 if (readl(cp->regs + REG_MAC_TX_RESET) | 3020 readl(cp->regs + REG_MAC_RX_RESET)) 3021 netdev_err(cp->dev, "mac tx[%d]/rx[%d] reset failed [%08x]\n", 3022 readl(cp->regs + REG_MAC_TX_RESET), 3023 readl(cp->regs + REG_MAC_RX_RESET), 3024 readl(cp->regs + REG_MAC_STATE_MACHINE)); 3025 } 3026 3027 3028 /* Must be invoked under cp->lock. */ 3029 static void cas_init_mac(struct cas *cp) 3030 { 3031 const unsigned char *e = &cp->dev->dev_addr[0]; 3032 int i; 3033 cas_mac_reset(cp); 3034 3035 /* setup core arbitration weight register */ 3036 writel(CAWR_RR_DIS, cp->regs + REG_CAWR); 3037 3038 #if !defined(CONFIG_SPARC64) && !defined(CONFIG_ALPHA) 3039 /* set the infinite burst register for chips that don't have 3040 * pci issues. 3041 */ 3042 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) == 0) 3043 writel(INF_BURST_EN, cp->regs + REG_INF_BURST); 3044 #endif 3045 3046 writel(0x1BF0, cp->regs + REG_MAC_SEND_PAUSE); 3047 3048 writel(0x00, cp->regs + REG_MAC_IPG0); 3049 writel(0x08, cp->regs + REG_MAC_IPG1); 3050 writel(0x04, cp->regs + REG_MAC_IPG2); 3051 3052 /* change later for 802.3z */ 3053 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 3054 3055 /* min frame + FCS */ 3056 writel(ETH_ZLEN + 4, cp->regs + REG_MAC_FRAMESIZE_MIN); 3057 3058 /* Ethernet payload + header + FCS + optional VLAN tag. NOTE: we 3059 * specify the maximum frame size to prevent RX tag errors on 3060 * oversized frames. 3061 */ 3062 writel(CAS_BASE(MAC_FRAMESIZE_MAX_BURST, 0x2000) | 3063 CAS_BASE(MAC_FRAMESIZE_MAX_FRAME, 3064 (CAS_MAX_MTU + ETH_HLEN + 4 + 4)), 3065 cp->regs + REG_MAC_FRAMESIZE_MAX); 3066 3067 /* NOTE: crc_size is used as a surrogate for half-duplex. 3068 * workaround saturn half-duplex issue by increasing preamble 3069 * size to 65 bytes. 3070 */ 3071 if ((cp->cas_flags & CAS_FLAG_SATURN) && cp->crc_size) 3072 writel(0x41, cp->regs + REG_MAC_PA_SIZE); 3073 else 3074 writel(0x07, cp->regs + REG_MAC_PA_SIZE); 3075 writel(0x04, cp->regs + REG_MAC_JAM_SIZE); 3076 writel(0x10, cp->regs + REG_MAC_ATTEMPT_LIMIT); 3077 writel(0x8808, cp->regs + REG_MAC_CTRL_TYPE); 3078 3079 writel((e[5] | (e[4] << 8)) & 0x3ff, cp->regs + REG_MAC_RANDOM_SEED); 3080 3081 writel(0, cp->regs + REG_MAC_ADDR_FILTER0); 3082 writel(0, cp->regs + REG_MAC_ADDR_FILTER1); 3083 writel(0, cp->regs + REG_MAC_ADDR_FILTER2); 3084 writel(0, cp->regs + REG_MAC_ADDR_FILTER2_1_MASK); 3085 writel(0, cp->regs + REG_MAC_ADDR_FILTER0_MASK); 3086 3087 /* setup mac address in perfect filter array */ 3088 for (i = 0; i < 45; i++) 3089 writel(0x0, cp->regs + REG_MAC_ADDRN(i)); 3090 3091 writel((e[4] << 8) | e[5], cp->regs + REG_MAC_ADDRN(0)); 3092 writel((e[2] << 8) | e[3], cp->regs + REG_MAC_ADDRN(1)); 3093 writel((e[0] << 8) | e[1], cp->regs + REG_MAC_ADDRN(2)); 3094 3095 writel(0x0001, cp->regs + REG_MAC_ADDRN(42)); 3096 writel(0xc200, cp->regs + REG_MAC_ADDRN(43)); 3097 writel(0x0180, cp->regs + REG_MAC_ADDRN(44)); 3098 3099 cp->mac_rx_cfg = cas_setup_multicast(cp); 3100 3101 spin_lock(&cp->stat_lock[N_TX_RINGS]); 3102 cas_clear_mac_err(cp); 3103 spin_unlock(&cp->stat_lock[N_TX_RINGS]); 3104 3105 /* Setup MAC interrupts. We want to get all of the interesting 3106 * counter expiration events, but we do not want to hear about 3107 * normal rx/tx as the DMA engine tells us that. 3108 */ 3109 writel(MAC_TX_FRAME_XMIT, cp->regs + REG_MAC_TX_MASK); 3110 writel(MAC_RX_FRAME_RECV, cp->regs + REG_MAC_RX_MASK); 3111 3112 /* Don't enable even the PAUSE interrupts for now, we 3113 * make no use of those events other than to record them. 3114 */ 3115 writel(0xffffffff, cp->regs + REG_MAC_CTRL_MASK); 3116 } 3117 3118 /* Must be invoked under cp->lock. */ 3119 static void cas_init_pause_thresholds(struct cas *cp) 3120 { 3121 /* Calculate pause thresholds. Setting the OFF threshold to the 3122 * full RX fifo size effectively disables PAUSE generation 3123 */ 3124 if (cp->rx_fifo_size <= (2 * 1024)) { 3125 cp->rx_pause_off = cp->rx_pause_on = cp->rx_fifo_size; 3126 } else { 3127 int max_frame = (cp->dev->mtu + ETH_HLEN + 4 + 4 + 64) & ~63; 3128 if (max_frame * 3 > cp->rx_fifo_size) { 3129 cp->rx_pause_off = 7104; 3130 cp->rx_pause_on = 960; 3131 } else { 3132 int off = (cp->rx_fifo_size - (max_frame * 2)); 3133 int on = off - max_frame; 3134 cp->rx_pause_off = off; 3135 cp->rx_pause_on = on; 3136 } 3137 } 3138 } 3139 3140 static int cas_vpd_match(const void __iomem *p, const char *str) 3141 { 3142 int len = strlen(str) + 1; 3143 int i; 3144 3145 for (i = 0; i < len; i++) { 3146 if (readb(p + i) != str[i]) 3147 return 0; 3148 } 3149 return 1; 3150 } 3151 3152 3153 /* get the mac address by reading the vpd information in the rom. 3154 * also get the phy type and determine if there's an entropy generator. 3155 * NOTE: this is a bit convoluted for the following reasons: 3156 * 1) vpd info has order-dependent mac addresses for multinic cards 3157 * 2) the only way to determine the nic order is to use the slot 3158 * number. 3159 * 3) fiber cards don't have bridges, so their slot numbers don't 3160 * mean anything. 3161 * 4) we don't actually know we have a fiber card until after 3162 * the mac addresses are parsed. 3163 */ 3164 static int cas_get_vpd_info(struct cas *cp, unsigned char *dev_addr, 3165 const int offset) 3166 { 3167 void __iomem *p = cp->regs + REG_EXPANSION_ROM_RUN_START; 3168 void __iomem *base, *kstart; 3169 int i, len; 3170 int found = 0; 3171 #define VPD_FOUND_MAC 0x01 3172 #define VPD_FOUND_PHY 0x02 3173 3174 int phy_type = CAS_PHY_MII_MDIO0; /* default phy type */ 3175 int mac_off = 0; 3176 3177 #if defined(CONFIG_SPARC) 3178 const unsigned char *addr; 3179 #endif 3180 3181 /* give us access to the PROM */ 3182 writel(BIM_LOCAL_DEV_PROM | BIM_LOCAL_DEV_PAD, 3183 cp->regs + REG_BIM_LOCAL_DEV_EN); 3184 3185 /* check for an expansion rom */ 3186 if (readb(p) != 0x55 || readb(p + 1) != 0xaa) 3187 goto use_random_mac_addr; 3188 3189 /* search for beginning of vpd */ 3190 base = NULL; 3191 for (i = 2; i < EXPANSION_ROM_SIZE; i++) { 3192 /* check for PCIR */ 3193 if ((readb(p + i + 0) == 0x50) && 3194 (readb(p + i + 1) == 0x43) && 3195 (readb(p + i + 2) == 0x49) && 3196 (readb(p + i + 3) == 0x52)) { 3197 base = p + (readb(p + i + 8) | 3198 (readb(p + i + 9) << 8)); 3199 break; 3200 } 3201 } 3202 3203 if (!base || (readb(base) != 0x82)) 3204 goto use_random_mac_addr; 3205 3206 i = (readb(base + 1) | (readb(base + 2) << 8)) + 3; 3207 while (i < EXPANSION_ROM_SIZE) { 3208 if (readb(base + i) != 0x90) /* no vpd found */ 3209 goto use_random_mac_addr; 3210 3211 /* found a vpd field */ 3212 len = readb(base + i + 1) | (readb(base + i + 2) << 8); 3213 3214 /* extract keywords */ 3215 kstart = base + i + 3; 3216 p = kstart; 3217 while ((p - kstart) < len) { 3218 int klen = readb(p + 2); 3219 int j; 3220 char type; 3221 3222 p += 3; 3223 3224 /* look for the following things: 3225 * -- correct length == 29 3226 * 3 (type) + 2 (size) + 3227 * 18 (strlen("local-mac-address") + 1) + 3228 * 6 (mac addr) 3229 * -- VPD Instance 'I' 3230 * -- VPD Type Bytes 'B' 3231 * -- VPD data length == 6 3232 * -- property string == local-mac-address 3233 * 3234 * -- correct length == 24 3235 * 3 (type) + 2 (size) + 3236 * 12 (strlen("entropy-dev") + 1) + 3237 * 7 (strlen("vms110") + 1) 3238 * -- VPD Instance 'I' 3239 * -- VPD Type String 'B' 3240 * -- VPD data length == 7 3241 * -- property string == entropy-dev 3242 * 3243 * -- correct length == 18 3244 * 3 (type) + 2 (size) + 3245 * 9 (strlen("phy-type") + 1) + 3246 * 4 (strlen("pcs") + 1) 3247 * -- VPD Instance 'I' 3248 * -- VPD Type String 'S' 3249 * -- VPD data length == 4 3250 * -- property string == phy-type 3251 * 3252 * -- correct length == 23 3253 * 3 (type) + 2 (size) + 3254 * 14 (strlen("phy-interface") + 1) + 3255 * 4 (strlen("pcs") + 1) 3256 * -- VPD Instance 'I' 3257 * -- VPD Type String 'S' 3258 * -- VPD data length == 4 3259 * -- property string == phy-interface 3260 */ 3261 if (readb(p) != 'I') 3262 goto next; 3263 3264 /* finally, check string and length */ 3265 type = readb(p + 3); 3266 if (type == 'B') { 3267 if ((klen == 29) && readb(p + 4) == 6 && 3268 cas_vpd_match(p + 5, 3269 "local-mac-address")) { 3270 if (mac_off++ > offset) 3271 goto next; 3272 3273 /* set mac address */ 3274 for (j = 0; j < 6; j++) 3275 dev_addr[j] = 3276 readb(p + 23 + j); 3277 goto found_mac; 3278 } 3279 } 3280 3281 if (type != 'S') 3282 goto next; 3283 3284 #ifdef USE_ENTROPY_DEV 3285 if ((klen == 24) && 3286 cas_vpd_match(p + 5, "entropy-dev") && 3287 cas_vpd_match(p + 17, "vms110")) { 3288 cp->cas_flags |= CAS_FLAG_ENTROPY_DEV; 3289 goto next; 3290 } 3291 #endif 3292 3293 if (found & VPD_FOUND_PHY) 3294 goto next; 3295 3296 if ((klen == 18) && readb(p + 4) == 4 && 3297 cas_vpd_match(p + 5, "phy-type")) { 3298 if (cas_vpd_match(p + 14, "pcs")) { 3299 phy_type = CAS_PHY_SERDES; 3300 goto found_phy; 3301 } 3302 } 3303 3304 if ((klen == 23) && readb(p + 4) == 4 && 3305 cas_vpd_match(p + 5, "phy-interface")) { 3306 if (cas_vpd_match(p + 19, "pcs")) { 3307 phy_type = CAS_PHY_SERDES; 3308 goto found_phy; 3309 } 3310 } 3311 found_mac: 3312 found |= VPD_FOUND_MAC; 3313 goto next; 3314 3315 found_phy: 3316 found |= VPD_FOUND_PHY; 3317 3318 next: 3319 p += klen; 3320 } 3321 i += len + 3; 3322 } 3323 3324 use_random_mac_addr: 3325 if (found & VPD_FOUND_MAC) 3326 goto done; 3327 3328 #if defined(CONFIG_SPARC) 3329 addr = of_get_property(cp->of_node, "local-mac-address", NULL); 3330 if (addr != NULL) { 3331 memcpy(dev_addr, addr, ETH_ALEN); 3332 goto done; 3333 } 3334 #endif 3335 3336 /* Sun MAC prefix then 3 random bytes. */ 3337 pr_info("MAC address not found in ROM VPD\n"); 3338 dev_addr[0] = 0x08; 3339 dev_addr[1] = 0x00; 3340 dev_addr[2] = 0x20; 3341 get_random_bytes(dev_addr + 3, 3); 3342 3343 done: 3344 writel(0, cp->regs + REG_BIM_LOCAL_DEV_EN); 3345 return phy_type; 3346 } 3347 3348 /* check pci invariants */ 3349 static void cas_check_pci_invariants(struct cas *cp) 3350 { 3351 struct pci_dev *pdev = cp->pdev; 3352 3353 cp->cas_flags = 0; 3354 if ((pdev->vendor == PCI_VENDOR_ID_SUN) && 3355 (pdev->device == PCI_DEVICE_ID_SUN_CASSINI)) { 3356 if (pdev->revision >= CAS_ID_REVPLUS) 3357 cp->cas_flags |= CAS_FLAG_REG_PLUS; 3358 if (pdev->revision < CAS_ID_REVPLUS02u) 3359 cp->cas_flags |= CAS_FLAG_TARGET_ABORT; 3360 3361 /* Original Cassini supports HW CSUM, but it's not 3362 * enabled by default as it can trigger TX hangs. 3363 */ 3364 if (pdev->revision < CAS_ID_REV2) 3365 cp->cas_flags |= CAS_FLAG_NO_HW_CSUM; 3366 } else { 3367 /* Only sun has original cassini chips. */ 3368 cp->cas_flags |= CAS_FLAG_REG_PLUS; 3369 3370 /* We use a flag because the same phy might be externally 3371 * connected. 3372 */ 3373 if ((pdev->vendor == PCI_VENDOR_ID_NS) && 3374 (pdev->device == PCI_DEVICE_ID_NS_SATURN)) 3375 cp->cas_flags |= CAS_FLAG_SATURN; 3376 } 3377 } 3378 3379 3380 static int cas_check_invariants(struct cas *cp) 3381 { 3382 struct pci_dev *pdev = cp->pdev; 3383 u8 addr[ETH_ALEN]; 3384 u32 cfg; 3385 int i; 3386 3387 /* get page size for rx buffers. */ 3388 cp->page_order = 0; 3389 #ifdef USE_PAGE_ORDER 3390 if (PAGE_SHIFT < CAS_JUMBO_PAGE_SHIFT) { 3391 /* see if we can allocate larger pages */ 3392 struct page *page = alloc_pages(GFP_ATOMIC, 3393 CAS_JUMBO_PAGE_SHIFT - 3394 PAGE_SHIFT); 3395 if (page) { 3396 __free_pages(page, CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT); 3397 cp->page_order = CAS_JUMBO_PAGE_SHIFT - PAGE_SHIFT; 3398 } else { 3399 printk("MTU limited to %d bytes\n", CAS_MAX_MTU); 3400 } 3401 } 3402 #endif 3403 cp->page_size = (PAGE_SIZE << cp->page_order); 3404 3405 /* Fetch the FIFO configurations. */ 3406 cp->tx_fifo_size = readl(cp->regs + REG_TX_FIFO_SIZE) * 64; 3407 cp->rx_fifo_size = RX_FIFO_SIZE; 3408 3409 /* finish phy determination. MDIO1 takes precedence over MDIO0 if 3410 * they're both connected. 3411 */ 3412 cp->phy_type = cas_get_vpd_info(cp, addr, PCI_SLOT(pdev->devfn)); 3413 eth_hw_addr_set(cp->dev, addr); 3414 if (cp->phy_type & CAS_PHY_SERDES) { 3415 cp->cas_flags |= CAS_FLAG_1000MB_CAP; 3416 return 0; /* no more checking needed */ 3417 } 3418 3419 /* MII */ 3420 cfg = readl(cp->regs + REG_MIF_CFG); 3421 if (cfg & MIF_CFG_MDIO_1) { 3422 cp->phy_type = CAS_PHY_MII_MDIO1; 3423 } else if (cfg & MIF_CFG_MDIO_0) { 3424 cp->phy_type = CAS_PHY_MII_MDIO0; 3425 } 3426 3427 cas_mif_poll(cp, 0); 3428 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); 3429 3430 for (i = 0; i < 32; i++) { 3431 u32 phy_id; 3432 int j; 3433 3434 for (j = 0; j < 3; j++) { 3435 cp->phy_addr = i; 3436 phy_id = cas_phy_read(cp, MII_PHYSID1) << 16; 3437 phy_id |= cas_phy_read(cp, MII_PHYSID2); 3438 if (phy_id && (phy_id != 0xFFFFFFFF)) { 3439 cp->phy_id = phy_id; 3440 goto done; 3441 } 3442 } 3443 } 3444 pr_err("MII phy did not respond [%08x]\n", 3445 readl(cp->regs + REG_MIF_STATE_MACHINE)); 3446 return -1; 3447 3448 done: 3449 /* see if we can do gigabit */ 3450 cfg = cas_phy_read(cp, MII_BMSR); 3451 if ((cfg & CAS_BMSR_1000_EXTEND) && 3452 cas_phy_read(cp, CAS_MII_1000_EXTEND)) 3453 cp->cas_flags |= CAS_FLAG_1000MB_CAP; 3454 return 0; 3455 } 3456 3457 /* Must be invoked under cp->lock. */ 3458 static inline void cas_start_dma(struct cas *cp) 3459 { 3460 int i; 3461 u32 val; 3462 int txfailed = 0; 3463 3464 /* enable dma */ 3465 val = readl(cp->regs + REG_TX_CFG) | TX_CFG_DMA_EN; 3466 writel(val, cp->regs + REG_TX_CFG); 3467 val = readl(cp->regs + REG_RX_CFG) | RX_CFG_DMA_EN; 3468 writel(val, cp->regs + REG_RX_CFG); 3469 3470 /* enable the mac */ 3471 val = readl(cp->regs + REG_MAC_TX_CFG) | MAC_TX_CFG_EN; 3472 writel(val, cp->regs + REG_MAC_TX_CFG); 3473 val = readl(cp->regs + REG_MAC_RX_CFG) | MAC_RX_CFG_EN; 3474 writel(val, cp->regs + REG_MAC_RX_CFG); 3475 3476 i = STOP_TRIES; 3477 while (i-- > 0) { 3478 val = readl(cp->regs + REG_MAC_TX_CFG); 3479 if ((val & MAC_TX_CFG_EN)) 3480 break; 3481 udelay(10); 3482 } 3483 if (i < 0) txfailed = 1; 3484 i = STOP_TRIES; 3485 while (i-- > 0) { 3486 val = readl(cp->regs + REG_MAC_RX_CFG); 3487 if ((val & MAC_RX_CFG_EN)) { 3488 if (txfailed) { 3489 netdev_err(cp->dev, 3490 "enabling mac failed [tx:%08x:%08x]\n", 3491 readl(cp->regs + REG_MIF_STATE_MACHINE), 3492 readl(cp->regs + REG_MAC_STATE_MACHINE)); 3493 } 3494 goto enable_rx_done; 3495 } 3496 udelay(10); 3497 } 3498 netdev_err(cp->dev, "enabling mac failed [%s:%08x:%08x]\n", 3499 (txfailed ? "tx,rx" : "rx"), 3500 readl(cp->regs + REG_MIF_STATE_MACHINE), 3501 readl(cp->regs + REG_MAC_STATE_MACHINE)); 3502 3503 enable_rx_done: 3504 cas_unmask_intr(cp); /* enable interrupts */ 3505 writel(RX_DESC_RINGN_SIZE(0) - 4, cp->regs + REG_RX_KICK); 3506 writel(0, cp->regs + REG_RX_COMP_TAIL); 3507 3508 if (cp->cas_flags & CAS_FLAG_REG_PLUS) { 3509 if (N_RX_DESC_RINGS > 1) 3510 writel(RX_DESC_RINGN_SIZE(1) - 4, 3511 cp->regs + REG_PLUS_RX_KICK1); 3512 3513 for (i = 1; i < N_RX_COMP_RINGS; i++) 3514 writel(0, cp->regs + REG_PLUS_RX_COMPN_TAIL(i)); 3515 } 3516 } 3517 3518 /* Must be invoked under cp->lock. */ 3519 static void cas_read_pcs_link_mode(struct cas *cp, int *fd, int *spd, 3520 int *pause) 3521 { 3522 u32 val = readl(cp->regs + REG_PCS_MII_LPA); 3523 *fd = (val & PCS_MII_LPA_FD) ? 1 : 0; 3524 *pause = (val & PCS_MII_LPA_SYM_PAUSE) ? 0x01 : 0x00; 3525 if (val & PCS_MII_LPA_ASYM_PAUSE) 3526 *pause |= 0x10; 3527 *spd = 1000; 3528 } 3529 3530 /* Must be invoked under cp->lock. */ 3531 static void cas_read_mii_link_mode(struct cas *cp, int *fd, int *spd, 3532 int *pause) 3533 { 3534 u32 val; 3535 3536 *fd = 0; 3537 *spd = 10; 3538 *pause = 0; 3539 3540 /* use GMII registers */ 3541 val = cas_phy_read(cp, MII_LPA); 3542 if (val & CAS_LPA_PAUSE) 3543 *pause = 0x01; 3544 3545 if (val & CAS_LPA_ASYM_PAUSE) 3546 *pause |= 0x10; 3547 3548 if (val & LPA_DUPLEX) 3549 *fd = 1; 3550 if (val & LPA_100) 3551 *spd = 100; 3552 3553 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 3554 val = cas_phy_read(cp, CAS_MII_1000_STATUS); 3555 if (val & (CAS_LPA_1000FULL | CAS_LPA_1000HALF)) 3556 *spd = 1000; 3557 if (val & CAS_LPA_1000FULL) 3558 *fd = 1; 3559 } 3560 } 3561 3562 /* A link-up condition has occurred, initialize and enable the 3563 * rest of the chip. 3564 * 3565 * Must be invoked under cp->lock. 3566 */ 3567 static void cas_set_link_modes(struct cas *cp) 3568 { 3569 u32 val; 3570 int full_duplex, speed, pause; 3571 3572 full_duplex = 0; 3573 speed = 10; 3574 pause = 0; 3575 3576 if (CAS_PHY_MII(cp->phy_type)) { 3577 cas_mif_poll(cp, 0); 3578 val = cas_phy_read(cp, MII_BMCR); 3579 if (val & BMCR_ANENABLE) { 3580 cas_read_mii_link_mode(cp, &full_duplex, &speed, 3581 &pause); 3582 } else { 3583 if (val & BMCR_FULLDPLX) 3584 full_duplex = 1; 3585 3586 if (val & BMCR_SPEED100) 3587 speed = 100; 3588 else if (val & CAS_BMCR_SPEED1000) 3589 speed = (cp->cas_flags & CAS_FLAG_1000MB_CAP) ? 3590 1000 : 100; 3591 } 3592 cas_mif_poll(cp, 1); 3593 3594 } else { 3595 val = readl(cp->regs + REG_PCS_MII_CTRL); 3596 cas_read_pcs_link_mode(cp, &full_duplex, &speed, &pause); 3597 if ((val & PCS_MII_AUTONEG_EN) == 0) { 3598 if (val & PCS_MII_CTRL_DUPLEX) 3599 full_duplex = 1; 3600 } 3601 } 3602 3603 netif_info(cp, link, cp->dev, "Link up at %d Mbps, %s-duplex\n", 3604 speed, full_duplex ? "full" : "half"); 3605 3606 val = MAC_XIF_TX_MII_OUTPUT_EN | MAC_XIF_LINK_LED; 3607 if (CAS_PHY_MII(cp->phy_type)) { 3608 val |= MAC_XIF_MII_BUFFER_OUTPUT_EN; 3609 if (!full_duplex) 3610 val |= MAC_XIF_DISABLE_ECHO; 3611 } 3612 if (full_duplex) 3613 val |= MAC_XIF_FDPLX_LED; 3614 if (speed == 1000) 3615 val |= MAC_XIF_GMII_MODE; 3616 writel(val, cp->regs + REG_MAC_XIF_CFG); 3617 3618 /* deal with carrier and collision detect. */ 3619 val = MAC_TX_CFG_IPG_EN; 3620 if (full_duplex) { 3621 val |= MAC_TX_CFG_IGNORE_CARRIER; 3622 val |= MAC_TX_CFG_IGNORE_COLL; 3623 } else { 3624 #ifndef USE_CSMA_CD_PROTO 3625 val |= MAC_TX_CFG_NEVER_GIVE_UP_EN; 3626 val |= MAC_TX_CFG_NEVER_GIVE_UP_LIM; 3627 #endif 3628 } 3629 /* val now set up for REG_MAC_TX_CFG */ 3630 3631 /* If gigabit and half-duplex, enable carrier extension 3632 * mode. increase slot time to 512 bytes as well. 3633 * else, disable it and make sure slot time is 64 bytes. 3634 * also activate checksum bug workaround 3635 */ 3636 if ((speed == 1000) && !full_duplex) { 3637 writel(val | MAC_TX_CFG_CARRIER_EXTEND, 3638 cp->regs + REG_MAC_TX_CFG); 3639 3640 val = readl(cp->regs + REG_MAC_RX_CFG); 3641 val &= ~MAC_RX_CFG_STRIP_FCS; /* checksum workaround */ 3642 writel(val | MAC_RX_CFG_CARRIER_EXTEND, 3643 cp->regs + REG_MAC_RX_CFG); 3644 3645 writel(0x200, cp->regs + REG_MAC_SLOT_TIME); 3646 3647 cp->crc_size = 4; 3648 /* minimum size gigabit frame at half duplex */ 3649 cp->min_frame_size = CAS_1000MB_MIN_FRAME; 3650 3651 } else { 3652 writel(val, cp->regs + REG_MAC_TX_CFG); 3653 3654 /* checksum bug workaround. don't strip FCS when in 3655 * half-duplex mode 3656 */ 3657 val = readl(cp->regs + REG_MAC_RX_CFG); 3658 if (full_duplex) { 3659 val |= MAC_RX_CFG_STRIP_FCS; 3660 cp->crc_size = 0; 3661 cp->min_frame_size = CAS_MIN_MTU; 3662 } else { 3663 val &= ~MAC_RX_CFG_STRIP_FCS; 3664 cp->crc_size = 4; 3665 cp->min_frame_size = CAS_MIN_FRAME; 3666 } 3667 writel(val & ~MAC_RX_CFG_CARRIER_EXTEND, 3668 cp->regs + REG_MAC_RX_CFG); 3669 writel(0x40, cp->regs + REG_MAC_SLOT_TIME); 3670 } 3671 3672 if (netif_msg_link(cp)) { 3673 if (pause & 0x01) { 3674 netdev_info(cp->dev, "Pause is enabled (rxfifo: %d off: %d on: %d)\n", 3675 cp->rx_fifo_size, 3676 cp->rx_pause_off, 3677 cp->rx_pause_on); 3678 } else if (pause & 0x10) { 3679 netdev_info(cp->dev, "TX pause enabled\n"); 3680 } else { 3681 netdev_info(cp->dev, "Pause is disabled\n"); 3682 } 3683 } 3684 3685 val = readl(cp->regs + REG_MAC_CTRL_CFG); 3686 val &= ~(MAC_CTRL_CFG_SEND_PAUSE_EN | MAC_CTRL_CFG_RECV_PAUSE_EN); 3687 if (pause) { /* symmetric or asymmetric pause */ 3688 val |= MAC_CTRL_CFG_SEND_PAUSE_EN; 3689 if (pause & 0x01) { /* symmetric pause */ 3690 val |= MAC_CTRL_CFG_RECV_PAUSE_EN; 3691 } 3692 } 3693 writel(val, cp->regs + REG_MAC_CTRL_CFG); 3694 cas_start_dma(cp); 3695 } 3696 3697 /* Must be invoked under cp->lock. */ 3698 static void cas_init_hw(struct cas *cp, int restart_link) 3699 { 3700 if (restart_link) 3701 cas_phy_init(cp); 3702 3703 cas_init_pause_thresholds(cp); 3704 cas_init_mac(cp); 3705 cas_init_dma(cp); 3706 3707 if (restart_link) { 3708 /* Default aneg parameters */ 3709 cp->timer_ticks = 0; 3710 cas_begin_auto_negotiation(cp, NULL); 3711 } else if (cp->lstate == link_up) { 3712 cas_set_link_modes(cp); 3713 netif_carrier_on(cp->dev); 3714 } 3715 } 3716 3717 /* Must be invoked under cp->lock. on earlier cassini boards, 3718 * SOFT_0 is tied to PCI reset. we use this to force a pci reset, 3719 * let it settle out, and then restore pci state. 3720 */ 3721 static void cas_hard_reset(struct cas *cp) 3722 { 3723 writel(BIM_LOCAL_DEV_SOFT_0, cp->regs + REG_BIM_LOCAL_DEV_EN); 3724 udelay(20); 3725 pci_restore_state(cp->pdev); 3726 } 3727 3728 3729 static void cas_global_reset(struct cas *cp, int blkflag) 3730 { 3731 int limit; 3732 3733 /* issue a global reset. don't use RSTOUT. */ 3734 if (blkflag && !CAS_PHY_MII(cp->phy_type)) { 3735 /* For PCS, when the blkflag is set, we should set the 3736 * SW_REST_BLOCK_PCS_SLINK bit to prevent the results of 3737 * the last autonegotiation from being cleared. We'll 3738 * need some special handling if the chip is set into a 3739 * loopback mode. 3740 */ 3741 writel((SW_RESET_TX | SW_RESET_RX | SW_RESET_BLOCK_PCS_SLINK), 3742 cp->regs + REG_SW_RESET); 3743 } else { 3744 writel(SW_RESET_TX | SW_RESET_RX, cp->regs + REG_SW_RESET); 3745 } 3746 3747 /* need to wait at least 3ms before polling register */ 3748 mdelay(3); 3749 3750 limit = STOP_TRIES; 3751 while (limit-- > 0) { 3752 u32 val = readl(cp->regs + REG_SW_RESET); 3753 if ((val & (SW_RESET_TX | SW_RESET_RX)) == 0) 3754 goto done; 3755 udelay(10); 3756 } 3757 netdev_err(cp->dev, "sw reset failed\n"); 3758 3759 done: 3760 /* enable various BIM interrupts */ 3761 writel(BIM_CFG_DPAR_INTR_ENABLE | BIM_CFG_RMA_INTR_ENABLE | 3762 BIM_CFG_RTA_INTR_ENABLE, cp->regs + REG_BIM_CFG); 3763 3764 /* clear out pci error status mask for handled errors. 3765 * we don't deal with DMA counter overflows as they happen 3766 * all the time. 3767 */ 3768 writel(0xFFFFFFFFU & ~(PCI_ERR_BADACK | PCI_ERR_DTRTO | 3769 PCI_ERR_OTHER | PCI_ERR_BIM_DMA_WRITE | 3770 PCI_ERR_BIM_DMA_READ), cp->regs + 3771 REG_PCI_ERR_STATUS_MASK); 3772 3773 /* set up for MII by default to address mac rx reset timeout 3774 * issue 3775 */ 3776 writel(PCS_DATAPATH_MODE_MII, cp->regs + REG_PCS_DATAPATH_MODE); 3777 } 3778 3779 static void cas_reset(struct cas *cp, int blkflag) 3780 { 3781 u32 val; 3782 3783 cas_mask_intr(cp); 3784 cas_global_reset(cp, blkflag); 3785 cas_mac_reset(cp); 3786 cas_entropy_reset(cp); 3787 3788 /* disable dma engines. */ 3789 val = readl(cp->regs + REG_TX_CFG); 3790 val &= ~TX_CFG_DMA_EN; 3791 writel(val, cp->regs + REG_TX_CFG); 3792 3793 val = readl(cp->regs + REG_RX_CFG); 3794 val &= ~RX_CFG_DMA_EN; 3795 writel(val, cp->regs + REG_RX_CFG); 3796 3797 /* program header parser */ 3798 if ((cp->cas_flags & CAS_FLAG_TARGET_ABORT) || 3799 (CAS_HP_ALT_FIRMWARE == cas_prog_null)) { 3800 cas_load_firmware(cp, CAS_HP_FIRMWARE); 3801 } else { 3802 cas_load_firmware(cp, CAS_HP_ALT_FIRMWARE); 3803 } 3804 3805 /* clear out error registers */ 3806 spin_lock(&cp->stat_lock[N_TX_RINGS]); 3807 cas_clear_mac_err(cp); 3808 spin_unlock(&cp->stat_lock[N_TX_RINGS]); 3809 } 3810 3811 /* Shut down the chip, must be called with pm_mutex held. */ 3812 static void cas_shutdown(struct cas *cp) 3813 { 3814 unsigned long flags; 3815 3816 /* Make us not-running to avoid timers respawning */ 3817 cp->hw_running = 0; 3818 3819 del_timer_sync(&cp->link_timer); 3820 3821 /* Stop the reset task */ 3822 #if 0 3823 while (atomic_read(&cp->reset_task_pending_mtu) || 3824 atomic_read(&cp->reset_task_pending_spare) || 3825 atomic_read(&cp->reset_task_pending_all)) 3826 schedule(); 3827 3828 #else 3829 while (atomic_read(&cp->reset_task_pending)) 3830 schedule(); 3831 #endif 3832 /* Actually stop the chip */ 3833 cas_lock_all_save(cp, flags); 3834 cas_reset(cp, 0); 3835 if (cp->cas_flags & CAS_FLAG_SATURN) 3836 cas_phy_powerdown(cp); 3837 cas_unlock_all_restore(cp, flags); 3838 } 3839 3840 static int cas_change_mtu(struct net_device *dev, int new_mtu) 3841 { 3842 struct cas *cp = netdev_priv(dev); 3843 3844 dev->mtu = new_mtu; 3845 if (!netif_running(dev) || !netif_device_present(dev)) 3846 return 0; 3847 3848 /* let the reset task handle it */ 3849 #if 1 3850 atomic_inc(&cp->reset_task_pending); 3851 if ((cp->phy_type & CAS_PHY_SERDES)) { 3852 atomic_inc(&cp->reset_task_pending_all); 3853 } else { 3854 atomic_inc(&cp->reset_task_pending_mtu); 3855 } 3856 schedule_work(&cp->reset_task); 3857 #else 3858 atomic_set(&cp->reset_task_pending, (cp->phy_type & CAS_PHY_SERDES) ? 3859 CAS_RESET_ALL : CAS_RESET_MTU); 3860 pr_err("reset called in cas_change_mtu\n"); 3861 schedule_work(&cp->reset_task); 3862 #endif 3863 3864 flush_work(&cp->reset_task); 3865 return 0; 3866 } 3867 3868 static void cas_clean_txd(struct cas *cp, int ring) 3869 { 3870 struct cas_tx_desc *txd = cp->init_txds[ring]; 3871 struct sk_buff *skb, **skbs = cp->tx_skbs[ring]; 3872 u64 daddr, dlen; 3873 int i, size; 3874 3875 size = TX_DESC_RINGN_SIZE(ring); 3876 for (i = 0; i < size; i++) { 3877 int frag; 3878 3879 if (skbs[i] == NULL) 3880 continue; 3881 3882 skb = skbs[i]; 3883 skbs[i] = NULL; 3884 3885 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) { 3886 int ent = i & (size - 1); 3887 3888 /* first buffer is never a tiny buffer and so 3889 * needs to be unmapped. 3890 */ 3891 daddr = le64_to_cpu(txd[ent].buffer); 3892 dlen = CAS_VAL(TX_DESC_BUFLEN, 3893 le64_to_cpu(txd[ent].control)); 3894 dma_unmap_page(&cp->pdev->dev, daddr, dlen, 3895 DMA_TO_DEVICE); 3896 3897 if (frag != skb_shinfo(skb)->nr_frags) { 3898 i++; 3899 3900 /* next buffer might by a tiny buffer. 3901 * skip past it. 3902 */ 3903 ent = i & (size - 1); 3904 if (cp->tx_tiny_use[ring][ent].used) 3905 i++; 3906 } 3907 } 3908 dev_kfree_skb_any(skb); 3909 } 3910 3911 /* zero out tiny buf usage */ 3912 memset(cp->tx_tiny_use[ring], 0, size*sizeof(*cp->tx_tiny_use[ring])); 3913 } 3914 3915 /* freed on close */ 3916 static inline void cas_free_rx_desc(struct cas *cp, int ring) 3917 { 3918 cas_page_t **page = cp->rx_pages[ring]; 3919 int i, size; 3920 3921 size = RX_DESC_RINGN_SIZE(ring); 3922 for (i = 0; i < size; i++) { 3923 if (page[i]) { 3924 cas_page_free(cp, page[i]); 3925 page[i] = NULL; 3926 } 3927 } 3928 } 3929 3930 static void cas_free_rxds(struct cas *cp) 3931 { 3932 int i; 3933 3934 for (i = 0; i < N_RX_DESC_RINGS; i++) 3935 cas_free_rx_desc(cp, i); 3936 } 3937 3938 /* Must be invoked under cp->lock. */ 3939 static void cas_clean_rings(struct cas *cp) 3940 { 3941 int i; 3942 3943 /* need to clean all tx rings */ 3944 memset(cp->tx_old, 0, sizeof(*cp->tx_old)*N_TX_RINGS); 3945 memset(cp->tx_new, 0, sizeof(*cp->tx_new)*N_TX_RINGS); 3946 for (i = 0; i < N_TX_RINGS; i++) 3947 cas_clean_txd(cp, i); 3948 3949 /* zero out init block */ 3950 memset(cp->init_block, 0, sizeof(struct cas_init_block)); 3951 cas_clean_rxds(cp); 3952 cas_clean_rxcs(cp); 3953 } 3954 3955 /* allocated on open */ 3956 static inline int cas_alloc_rx_desc(struct cas *cp, int ring) 3957 { 3958 cas_page_t **page = cp->rx_pages[ring]; 3959 int size, i = 0; 3960 3961 size = RX_DESC_RINGN_SIZE(ring); 3962 for (i = 0; i < size; i++) { 3963 if ((page[i] = cas_page_alloc(cp, GFP_KERNEL)) == NULL) 3964 return -1; 3965 } 3966 return 0; 3967 } 3968 3969 static int cas_alloc_rxds(struct cas *cp) 3970 { 3971 int i; 3972 3973 for (i = 0; i < N_RX_DESC_RINGS; i++) { 3974 if (cas_alloc_rx_desc(cp, i) < 0) { 3975 cas_free_rxds(cp); 3976 return -1; 3977 } 3978 } 3979 return 0; 3980 } 3981 3982 static void cas_reset_task(struct work_struct *work) 3983 { 3984 struct cas *cp = container_of(work, struct cas, reset_task); 3985 #if 0 3986 int pending = atomic_read(&cp->reset_task_pending); 3987 #else 3988 int pending_all = atomic_read(&cp->reset_task_pending_all); 3989 int pending_spare = atomic_read(&cp->reset_task_pending_spare); 3990 int pending_mtu = atomic_read(&cp->reset_task_pending_mtu); 3991 3992 if (pending_all == 0 && pending_spare == 0 && pending_mtu == 0) { 3993 /* We can have more tasks scheduled than actually 3994 * needed. 3995 */ 3996 atomic_dec(&cp->reset_task_pending); 3997 return; 3998 } 3999 #endif 4000 /* The link went down, we reset the ring, but keep 4001 * DMA stopped. Use this function for reset 4002 * on error as well. 4003 */ 4004 if (cp->hw_running) { 4005 unsigned long flags; 4006 4007 /* Make sure we don't get interrupts or tx packets */ 4008 netif_device_detach(cp->dev); 4009 cas_lock_all_save(cp, flags); 4010 4011 if (cp->opened) { 4012 /* We call cas_spare_recover when we call cas_open. 4013 * but we do not initialize the lists cas_spare_recover 4014 * uses until cas_open is called. 4015 */ 4016 cas_spare_recover(cp, GFP_ATOMIC); 4017 } 4018 #if 1 4019 /* test => only pending_spare set */ 4020 if (!pending_all && !pending_mtu) 4021 goto done; 4022 #else 4023 if (pending == CAS_RESET_SPARE) 4024 goto done; 4025 #endif 4026 /* when pending == CAS_RESET_ALL, the following 4027 * call to cas_init_hw will restart auto negotiation. 4028 * Setting the second argument of cas_reset to 4029 * !(pending == CAS_RESET_ALL) will set this argument 4030 * to 1 (avoiding reinitializing the PHY for the normal 4031 * PCS case) when auto negotiation is not restarted. 4032 */ 4033 #if 1 4034 cas_reset(cp, !(pending_all > 0)); 4035 if (cp->opened) 4036 cas_clean_rings(cp); 4037 cas_init_hw(cp, (pending_all > 0)); 4038 #else 4039 cas_reset(cp, !(pending == CAS_RESET_ALL)); 4040 if (cp->opened) 4041 cas_clean_rings(cp); 4042 cas_init_hw(cp, pending == CAS_RESET_ALL); 4043 #endif 4044 4045 done: 4046 cas_unlock_all_restore(cp, flags); 4047 netif_device_attach(cp->dev); 4048 } 4049 #if 1 4050 atomic_sub(pending_all, &cp->reset_task_pending_all); 4051 atomic_sub(pending_spare, &cp->reset_task_pending_spare); 4052 atomic_sub(pending_mtu, &cp->reset_task_pending_mtu); 4053 atomic_dec(&cp->reset_task_pending); 4054 #else 4055 atomic_set(&cp->reset_task_pending, 0); 4056 #endif 4057 } 4058 4059 static void cas_link_timer(struct timer_list *t) 4060 { 4061 struct cas *cp = from_timer(cp, t, link_timer); 4062 int mask, pending = 0, reset = 0; 4063 unsigned long flags; 4064 4065 if (link_transition_timeout != 0 && 4066 cp->link_transition_jiffies_valid && 4067 time_is_before_jiffies(cp->link_transition_jiffies + 4068 link_transition_timeout)) { 4069 /* One-second counter so link-down workaround doesn't 4070 * cause resets to occur so fast as to fool the switch 4071 * into thinking the link is down. 4072 */ 4073 cp->link_transition_jiffies_valid = 0; 4074 } 4075 4076 if (!cp->hw_running) 4077 return; 4078 4079 spin_lock_irqsave(&cp->lock, flags); 4080 cas_lock_tx(cp); 4081 cas_entropy_gather(cp); 4082 4083 /* If the link task is still pending, we just 4084 * reschedule the link timer 4085 */ 4086 #if 1 4087 if (atomic_read(&cp->reset_task_pending_all) || 4088 atomic_read(&cp->reset_task_pending_spare) || 4089 atomic_read(&cp->reset_task_pending_mtu)) 4090 goto done; 4091 #else 4092 if (atomic_read(&cp->reset_task_pending)) 4093 goto done; 4094 #endif 4095 4096 /* check for rx cleaning */ 4097 if ((mask = (cp->cas_flags & CAS_FLAG_RXD_POST_MASK))) { 4098 int i, rmask; 4099 4100 for (i = 0; i < MAX_RX_DESC_RINGS; i++) { 4101 rmask = CAS_FLAG_RXD_POST(i); 4102 if ((mask & rmask) == 0) 4103 continue; 4104 4105 /* post_rxds will do a mod_timer */ 4106 if (cas_post_rxds_ringN(cp, i, cp->rx_last[i]) < 0) { 4107 pending = 1; 4108 continue; 4109 } 4110 cp->cas_flags &= ~rmask; 4111 } 4112 } 4113 4114 if (CAS_PHY_MII(cp->phy_type)) { 4115 u16 bmsr; 4116 cas_mif_poll(cp, 0); 4117 bmsr = cas_phy_read(cp, MII_BMSR); 4118 /* WTZ: Solaris driver reads this twice, but that 4119 * may be due to the PCS case and the use of a 4120 * common implementation. Read it twice here to be 4121 * safe. 4122 */ 4123 bmsr = cas_phy_read(cp, MII_BMSR); 4124 cas_mif_poll(cp, 1); 4125 readl(cp->regs + REG_MIF_STATUS); /* avoid dups */ 4126 reset = cas_mii_link_check(cp, bmsr); 4127 } else { 4128 reset = cas_pcs_link_check(cp); 4129 } 4130 4131 if (reset) 4132 goto done; 4133 4134 /* check for tx state machine confusion */ 4135 if ((readl(cp->regs + REG_MAC_TX_STATUS) & MAC_TX_FRAME_XMIT) == 0) { 4136 u32 val = readl(cp->regs + REG_MAC_STATE_MACHINE); 4137 u32 wptr, rptr; 4138 int tlm = CAS_VAL(MAC_SM_TLM, val); 4139 4140 if (((tlm == 0x5) || (tlm == 0x3)) && 4141 (CAS_VAL(MAC_SM_ENCAP_SM, val) == 0)) { 4142 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, 4143 "tx err: MAC_STATE[%08x]\n", val); 4144 reset = 1; 4145 goto done; 4146 } 4147 4148 val = readl(cp->regs + REG_TX_FIFO_PKT_CNT); 4149 wptr = readl(cp->regs + REG_TX_FIFO_WRITE_PTR); 4150 rptr = readl(cp->regs + REG_TX_FIFO_READ_PTR); 4151 if ((val == 0) && (wptr != rptr)) { 4152 netif_printk(cp, tx_err, KERN_DEBUG, cp->dev, 4153 "tx err: TX_FIFO[%08x:%08x:%08x]\n", 4154 val, wptr, rptr); 4155 reset = 1; 4156 } 4157 4158 if (reset) 4159 cas_hard_reset(cp); 4160 } 4161 4162 done: 4163 if (reset) { 4164 #if 1 4165 atomic_inc(&cp->reset_task_pending); 4166 atomic_inc(&cp->reset_task_pending_all); 4167 schedule_work(&cp->reset_task); 4168 #else 4169 atomic_set(&cp->reset_task_pending, CAS_RESET_ALL); 4170 pr_err("reset called in cas_link_timer\n"); 4171 schedule_work(&cp->reset_task); 4172 #endif 4173 } 4174 4175 if (!pending) 4176 mod_timer(&cp->link_timer, jiffies + CAS_LINK_TIMEOUT); 4177 cas_unlock_tx(cp); 4178 spin_unlock_irqrestore(&cp->lock, flags); 4179 } 4180 4181 /* tiny buffers are used to avoid target abort issues with 4182 * older cassini's 4183 */ 4184 static void cas_tx_tiny_free(struct cas *cp) 4185 { 4186 struct pci_dev *pdev = cp->pdev; 4187 int i; 4188 4189 for (i = 0; i < N_TX_RINGS; i++) { 4190 if (!cp->tx_tiny_bufs[i]) 4191 continue; 4192 4193 dma_free_coherent(&pdev->dev, TX_TINY_BUF_BLOCK, 4194 cp->tx_tiny_bufs[i], cp->tx_tiny_dvma[i]); 4195 cp->tx_tiny_bufs[i] = NULL; 4196 } 4197 } 4198 4199 static int cas_tx_tiny_alloc(struct cas *cp) 4200 { 4201 struct pci_dev *pdev = cp->pdev; 4202 int i; 4203 4204 for (i = 0; i < N_TX_RINGS; i++) { 4205 cp->tx_tiny_bufs[i] = 4206 dma_alloc_coherent(&pdev->dev, TX_TINY_BUF_BLOCK, 4207 &cp->tx_tiny_dvma[i], GFP_KERNEL); 4208 if (!cp->tx_tiny_bufs[i]) { 4209 cas_tx_tiny_free(cp); 4210 return -1; 4211 } 4212 } 4213 return 0; 4214 } 4215 4216 4217 static int cas_open(struct net_device *dev) 4218 { 4219 struct cas *cp = netdev_priv(dev); 4220 int hw_was_up, err; 4221 unsigned long flags; 4222 4223 mutex_lock(&cp->pm_mutex); 4224 4225 hw_was_up = cp->hw_running; 4226 4227 /* The power-management mutex protects the hw_running 4228 * etc. state so it is safe to do this bit without cp->lock 4229 */ 4230 if (!cp->hw_running) { 4231 /* Reset the chip */ 4232 cas_lock_all_save(cp, flags); 4233 /* We set the second arg to cas_reset to zero 4234 * because cas_init_hw below will have its second 4235 * argument set to non-zero, which will force 4236 * autonegotiation to start. 4237 */ 4238 cas_reset(cp, 0); 4239 cp->hw_running = 1; 4240 cas_unlock_all_restore(cp, flags); 4241 } 4242 4243 err = -ENOMEM; 4244 if (cas_tx_tiny_alloc(cp) < 0) 4245 goto err_unlock; 4246 4247 /* alloc rx descriptors */ 4248 if (cas_alloc_rxds(cp) < 0) 4249 goto err_tx_tiny; 4250 4251 /* allocate spares */ 4252 cas_spare_init(cp); 4253 cas_spare_recover(cp, GFP_KERNEL); 4254 4255 /* We can now request the interrupt as we know it's masked 4256 * on the controller. cassini+ has up to 4 interrupts 4257 * that can be used, but you need to do explicit pci interrupt 4258 * mapping to expose them 4259 */ 4260 if (request_irq(cp->pdev->irq, cas_interrupt, 4261 IRQF_SHARED, dev->name, (void *) dev)) { 4262 netdev_err(cp->dev, "failed to request irq !\n"); 4263 err = -EAGAIN; 4264 goto err_spare; 4265 } 4266 4267 #ifdef USE_NAPI 4268 napi_enable(&cp->napi); 4269 #endif 4270 /* init hw */ 4271 cas_lock_all_save(cp, flags); 4272 cas_clean_rings(cp); 4273 cas_init_hw(cp, !hw_was_up); 4274 cp->opened = 1; 4275 cas_unlock_all_restore(cp, flags); 4276 4277 netif_start_queue(dev); 4278 mutex_unlock(&cp->pm_mutex); 4279 return 0; 4280 4281 err_spare: 4282 cas_spare_free(cp); 4283 cas_free_rxds(cp); 4284 err_tx_tiny: 4285 cas_tx_tiny_free(cp); 4286 err_unlock: 4287 mutex_unlock(&cp->pm_mutex); 4288 return err; 4289 } 4290 4291 static int cas_close(struct net_device *dev) 4292 { 4293 unsigned long flags; 4294 struct cas *cp = netdev_priv(dev); 4295 4296 #ifdef USE_NAPI 4297 napi_disable(&cp->napi); 4298 #endif 4299 /* Make sure we don't get distracted by suspend/resume */ 4300 mutex_lock(&cp->pm_mutex); 4301 4302 netif_stop_queue(dev); 4303 4304 /* Stop traffic, mark us closed */ 4305 cas_lock_all_save(cp, flags); 4306 cp->opened = 0; 4307 cas_reset(cp, 0); 4308 cas_phy_init(cp); 4309 cas_begin_auto_negotiation(cp, NULL); 4310 cas_clean_rings(cp); 4311 cas_unlock_all_restore(cp, flags); 4312 4313 free_irq(cp->pdev->irq, (void *) dev); 4314 cas_spare_free(cp); 4315 cas_free_rxds(cp); 4316 cas_tx_tiny_free(cp); 4317 mutex_unlock(&cp->pm_mutex); 4318 return 0; 4319 } 4320 4321 static struct { 4322 const char name[ETH_GSTRING_LEN]; 4323 } ethtool_cassini_statnames[] = { 4324 {"collisions"}, 4325 {"rx_bytes"}, 4326 {"rx_crc_errors"}, 4327 {"rx_dropped"}, 4328 {"rx_errors"}, 4329 {"rx_fifo_errors"}, 4330 {"rx_frame_errors"}, 4331 {"rx_length_errors"}, 4332 {"rx_over_errors"}, 4333 {"rx_packets"}, 4334 {"tx_aborted_errors"}, 4335 {"tx_bytes"}, 4336 {"tx_dropped"}, 4337 {"tx_errors"}, 4338 {"tx_fifo_errors"}, 4339 {"tx_packets"} 4340 }; 4341 #define CAS_NUM_STAT_KEYS ARRAY_SIZE(ethtool_cassini_statnames) 4342 4343 static struct { 4344 const int offsets; /* neg. values for 2nd arg to cas_read_phy */ 4345 } ethtool_register_table[] = { 4346 {-MII_BMSR}, 4347 {-MII_BMCR}, 4348 {REG_CAWR}, 4349 {REG_INF_BURST}, 4350 {REG_BIM_CFG}, 4351 {REG_RX_CFG}, 4352 {REG_HP_CFG}, 4353 {REG_MAC_TX_CFG}, 4354 {REG_MAC_RX_CFG}, 4355 {REG_MAC_CTRL_CFG}, 4356 {REG_MAC_XIF_CFG}, 4357 {REG_MIF_CFG}, 4358 {REG_PCS_CFG}, 4359 {REG_SATURN_PCFG}, 4360 {REG_PCS_MII_STATUS}, 4361 {REG_PCS_STATE_MACHINE}, 4362 {REG_MAC_COLL_EXCESS}, 4363 {REG_MAC_COLL_LATE} 4364 }; 4365 #define CAS_REG_LEN ARRAY_SIZE(ethtool_register_table) 4366 #define CAS_MAX_REGS (sizeof (u32)*CAS_REG_LEN) 4367 4368 static void cas_read_regs(struct cas *cp, u8 *ptr, int len) 4369 { 4370 u8 *p; 4371 int i; 4372 unsigned long flags; 4373 4374 spin_lock_irqsave(&cp->lock, flags); 4375 for (i = 0, p = ptr; i < len ; i ++, p += sizeof(u32)) { 4376 u16 hval; 4377 u32 val; 4378 if (ethtool_register_table[i].offsets < 0) { 4379 hval = cas_phy_read(cp, 4380 -ethtool_register_table[i].offsets); 4381 val = hval; 4382 } else { 4383 val= readl(cp->regs+ethtool_register_table[i].offsets); 4384 } 4385 memcpy(p, (u8 *)&val, sizeof(u32)); 4386 } 4387 spin_unlock_irqrestore(&cp->lock, flags); 4388 } 4389 4390 static struct net_device_stats *cas_get_stats(struct net_device *dev) 4391 { 4392 struct cas *cp = netdev_priv(dev); 4393 struct net_device_stats *stats = cp->net_stats; 4394 unsigned long flags; 4395 int i; 4396 unsigned long tmp; 4397 4398 /* we collate all of the stats into net_stats[N_TX_RING] */ 4399 if (!cp->hw_running) 4400 return stats + N_TX_RINGS; 4401 4402 /* collect outstanding stats */ 4403 /* WTZ: the Cassini spec gives these as 16 bit counters but 4404 * stored in 32-bit words. Added a mask of 0xffff to be safe, 4405 * in case the chip somehow puts any garbage in the other bits. 4406 * Also, counter usage didn't seem to mach what Adrian did 4407 * in the parts of the code that set these quantities. Made 4408 * that consistent. 4409 */ 4410 spin_lock_irqsave(&cp->stat_lock[N_TX_RINGS], flags); 4411 stats[N_TX_RINGS].rx_crc_errors += 4412 readl(cp->regs + REG_MAC_FCS_ERR) & 0xffff; 4413 stats[N_TX_RINGS].rx_frame_errors += 4414 readl(cp->regs + REG_MAC_ALIGN_ERR) &0xffff; 4415 stats[N_TX_RINGS].rx_length_errors += 4416 readl(cp->regs + REG_MAC_LEN_ERR) & 0xffff; 4417 #if 1 4418 tmp = (readl(cp->regs + REG_MAC_COLL_EXCESS) & 0xffff) + 4419 (readl(cp->regs + REG_MAC_COLL_LATE) & 0xffff); 4420 stats[N_TX_RINGS].tx_aborted_errors += tmp; 4421 stats[N_TX_RINGS].collisions += 4422 tmp + (readl(cp->regs + REG_MAC_COLL_NORMAL) & 0xffff); 4423 #else 4424 stats[N_TX_RINGS].tx_aborted_errors += 4425 readl(cp->regs + REG_MAC_COLL_EXCESS); 4426 stats[N_TX_RINGS].collisions += readl(cp->regs + REG_MAC_COLL_EXCESS) + 4427 readl(cp->regs + REG_MAC_COLL_LATE); 4428 #endif 4429 cas_clear_mac_err(cp); 4430 4431 /* saved bits that are unique to ring 0 */ 4432 spin_lock(&cp->stat_lock[0]); 4433 stats[N_TX_RINGS].collisions += stats[0].collisions; 4434 stats[N_TX_RINGS].rx_over_errors += stats[0].rx_over_errors; 4435 stats[N_TX_RINGS].rx_frame_errors += stats[0].rx_frame_errors; 4436 stats[N_TX_RINGS].rx_fifo_errors += stats[0].rx_fifo_errors; 4437 stats[N_TX_RINGS].tx_aborted_errors += stats[0].tx_aborted_errors; 4438 stats[N_TX_RINGS].tx_fifo_errors += stats[0].tx_fifo_errors; 4439 spin_unlock(&cp->stat_lock[0]); 4440 4441 for (i = 0; i < N_TX_RINGS; i++) { 4442 spin_lock(&cp->stat_lock[i]); 4443 stats[N_TX_RINGS].rx_length_errors += 4444 stats[i].rx_length_errors; 4445 stats[N_TX_RINGS].rx_crc_errors += stats[i].rx_crc_errors; 4446 stats[N_TX_RINGS].rx_packets += stats[i].rx_packets; 4447 stats[N_TX_RINGS].tx_packets += stats[i].tx_packets; 4448 stats[N_TX_RINGS].rx_bytes += stats[i].rx_bytes; 4449 stats[N_TX_RINGS].tx_bytes += stats[i].tx_bytes; 4450 stats[N_TX_RINGS].rx_errors += stats[i].rx_errors; 4451 stats[N_TX_RINGS].tx_errors += stats[i].tx_errors; 4452 stats[N_TX_RINGS].rx_dropped += stats[i].rx_dropped; 4453 stats[N_TX_RINGS].tx_dropped += stats[i].tx_dropped; 4454 memset(stats + i, 0, sizeof(struct net_device_stats)); 4455 spin_unlock(&cp->stat_lock[i]); 4456 } 4457 spin_unlock_irqrestore(&cp->stat_lock[N_TX_RINGS], flags); 4458 return stats + N_TX_RINGS; 4459 } 4460 4461 4462 static void cas_set_multicast(struct net_device *dev) 4463 { 4464 struct cas *cp = netdev_priv(dev); 4465 u32 rxcfg, rxcfg_new; 4466 unsigned long flags; 4467 int limit = STOP_TRIES; 4468 4469 if (!cp->hw_running) 4470 return; 4471 4472 spin_lock_irqsave(&cp->lock, flags); 4473 rxcfg = readl(cp->regs + REG_MAC_RX_CFG); 4474 4475 /* disable RX MAC and wait for completion */ 4476 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 4477 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_EN) { 4478 if (!limit--) 4479 break; 4480 udelay(10); 4481 } 4482 4483 /* disable hash filter and wait for completion */ 4484 limit = STOP_TRIES; 4485 rxcfg &= ~(MAC_RX_CFG_PROMISC_EN | MAC_RX_CFG_HASH_FILTER_EN); 4486 writel(rxcfg & ~MAC_RX_CFG_EN, cp->regs + REG_MAC_RX_CFG); 4487 while (readl(cp->regs + REG_MAC_RX_CFG) & MAC_RX_CFG_HASH_FILTER_EN) { 4488 if (!limit--) 4489 break; 4490 udelay(10); 4491 } 4492 4493 /* program hash filters */ 4494 cp->mac_rx_cfg = rxcfg_new = cas_setup_multicast(cp); 4495 rxcfg |= rxcfg_new; 4496 writel(rxcfg, cp->regs + REG_MAC_RX_CFG); 4497 spin_unlock_irqrestore(&cp->lock, flags); 4498 } 4499 4500 static void cas_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 4501 { 4502 struct cas *cp = netdev_priv(dev); 4503 strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver)); 4504 strlcpy(info->version, DRV_MODULE_VERSION, sizeof(info->version)); 4505 strlcpy(info->bus_info, pci_name(cp->pdev), sizeof(info->bus_info)); 4506 } 4507 4508 static int cas_get_link_ksettings(struct net_device *dev, 4509 struct ethtool_link_ksettings *cmd) 4510 { 4511 struct cas *cp = netdev_priv(dev); 4512 u16 bmcr; 4513 int full_duplex, speed, pause; 4514 unsigned long flags; 4515 enum link_state linkstate = link_up; 4516 u32 supported, advertising; 4517 4518 advertising = 0; 4519 supported = SUPPORTED_Autoneg; 4520 if (cp->cas_flags & CAS_FLAG_1000MB_CAP) { 4521 supported |= SUPPORTED_1000baseT_Full; 4522 advertising |= ADVERTISED_1000baseT_Full; 4523 } 4524 4525 /* Record PHY settings if HW is on. */ 4526 spin_lock_irqsave(&cp->lock, flags); 4527 bmcr = 0; 4528 linkstate = cp->lstate; 4529 if (CAS_PHY_MII(cp->phy_type)) { 4530 cmd->base.port = PORT_MII; 4531 cmd->base.phy_address = cp->phy_addr; 4532 advertising |= ADVERTISED_TP | ADVERTISED_MII | 4533 ADVERTISED_10baseT_Half | 4534 ADVERTISED_10baseT_Full | 4535 ADVERTISED_100baseT_Half | 4536 ADVERTISED_100baseT_Full; 4537 4538 supported |= 4539 (SUPPORTED_10baseT_Half | 4540 SUPPORTED_10baseT_Full | 4541 SUPPORTED_100baseT_Half | 4542 SUPPORTED_100baseT_Full | 4543 SUPPORTED_TP | SUPPORTED_MII); 4544 4545 if (cp->hw_running) { 4546 cas_mif_poll(cp, 0); 4547 bmcr = cas_phy_read(cp, MII_BMCR); 4548 cas_read_mii_link_mode(cp, &full_duplex, 4549 &speed, &pause); 4550 cas_mif_poll(cp, 1); 4551 } 4552 4553 } else { 4554 cmd->base.port = PORT_FIBRE; 4555 cmd->base.phy_address = 0; 4556 supported |= SUPPORTED_FIBRE; 4557 advertising |= ADVERTISED_FIBRE; 4558 4559 if (cp->hw_running) { 4560 /* pcs uses the same bits as mii */ 4561 bmcr = readl(cp->regs + REG_PCS_MII_CTRL); 4562 cas_read_pcs_link_mode(cp, &full_duplex, 4563 &speed, &pause); 4564 } 4565 } 4566 spin_unlock_irqrestore(&cp->lock, flags); 4567 4568 if (bmcr & BMCR_ANENABLE) { 4569 advertising |= ADVERTISED_Autoneg; 4570 cmd->base.autoneg = AUTONEG_ENABLE; 4571 cmd->base.speed = ((speed == 10) ? 4572 SPEED_10 : 4573 ((speed == 1000) ? 4574 SPEED_1000 : SPEED_100)); 4575 cmd->base.duplex = full_duplex ? DUPLEX_FULL : DUPLEX_HALF; 4576 } else { 4577 cmd->base.autoneg = AUTONEG_DISABLE; 4578 cmd->base.speed = ((bmcr & CAS_BMCR_SPEED1000) ? 4579 SPEED_1000 : 4580 ((bmcr & BMCR_SPEED100) ? 4581 SPEED_100 : SPEED_10)); 4582 cmd->base.duplex = (bmcr & BMCR_FULLDPLX) ? 4583 DUPLEX_FULL : DUPLEX_HALF; 4584 } 4585 if (linkstate != link_up) { 4586 /* Force these to "unknown" if the link is not up and 4587 * autonogotiation in enabled. We can set the link 4588 * speed to 0, but not cmd->duplex, 4589 * because its legal values are 0 and 1. Ethtool will 4590 * print the value reported in parentheses after the 4591 * word "Unknown" for unrecognized values. 4592 * 4593 * If in forced mode, we report the speed and duplex 4594 * settings that we configured. 4595 */ 4596 if (cp->link_cntl & BMCR_ANENABLE) { 4597 cmd->base.speed = 0; 4598 cmd->base.duplex = 0xff; 4599 } else { 4600 cmd->base.speed = SPEED_10; 4601 if (cp->link_cntl & BMCR_SPEED100) { 4602 cmd->base.speed = SPEED_100; 4603 } else if (cp->link_cntl & CAS_BMCR_SPEED1000) { 4604 cmd->base.speed = SPEED_1000; 4605 } 4606 cmd->base.duplex = (cp->link_cntl & BMCR_FULLDPLX) ? 4607 DUPLEX_FULL : DUPLEX_HALF; 4608 } 4609 } 4610 4611 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported, 4612 supported); 4613 ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising, 4614 advertising); 4615 4616 return 0; 4617 } 4618 4619 static int cas_set_link_ksettings(struct net_device *dev, 4620 const struct ethtool_link_ksettings *cmd) 4621 { 4622 struct cas *cp = netdev_priv(dev); 4623 unsigned long flags; 4624 u32 speed = cmd->base.speed; 4625 4626 /* Verify the settings we care about. */ 4627 if (cmd->base.autoneg != AUTONEG_ENABLE && 4628 cmd->base.autoneg != AUTONEG_DISABLE) 4629 return -EINVAL; 4630 4631 if (cmd->base.autoneg == AUTONEG_DISABLE && 4632 ((speed != SPEED_1000 && 4633 speed != SPEED_100 && 4634 speed != SPEED_10) || 4635 (cmd->base.duplex != DUPLEX_HALF && 4636 cmd->base.duplex != DUPLEX_FULL))) 4637 return -EINVAL; 4638 4639 /* Apply settings and restart link process. */ 4640 spin_lock_irqsave(&cp->lock, flags); 4641 cas_begin_auto_negotiation(cp, cmd); 4642 spin_unlock_irqrestore(&cp->lock, flags); 4643 return 0; 4644 } 4645 4646 static int cas_nway_reset(struct net_device *dev) 4647 { 4648 struct cas *cp = netdev_priv(dev); 4649 unsigned long flags; 4650 4651 if ((cp->link_cntl & BMCR_ANENABLE) == 0) 4652 return -EINVAL; 4653 4654 /* Restart link process. */ 4655 spin_lock_irqsave(&cp->lock, flags); 4656 cas_begin_auto_negotiation(cp, NULL); 4657 spin_unlock_irqrestore(&cp->lock, flags); 4658 4659 return 0; 4660 } 4661 4662 static u32 cas_get_link(struct net_device *dev) 4663 { 4664 struct cas *cp = netdev_priv(dev); 4665 return cp->lstate == link_up; 4666 } 4667 4668 static u32 cas_get_msglevel(struct net_device *dev) 4669 { 4670 struct cas *cp = netdev_priv(dev); 4671 return cp->msg_enable; 4672 } 4673 4674 static void cas_set_msglevel(struct net_device *dev, u32 value) 4675 { 4676 struct cas *cp = netdev_priv(dev); 4677 cp->msg_enable = value; 4678 } 4679 4680 static int cas_get_regs_len(struct net_device *dev) 4681 { 4682 struct cas *cp = netdev_priv(dev); 4683 return cp->casreg_len < CAS_MAX_REGS ? cp->casreg_len: CAS_MAX_REGS; 4684 } 4685 4686 static void cas_get_regs(struct net_device *dev, struct ethtool_regs *regs, 4687 void *p) 4688 { 4689 struct cas *cp = netdev_priv(dev); 4690 regs->version = 0; 4691 /* cas_read_regs handles locks (cp->lock). */ 4692 cas_read_regs(cp, p, regs->len / sizeof(u32)); 4693 } 4694 4695 static int cas_get_sset_count(struct net_device *dev, int sset) 4696 { 4697 switch (sset) { 4698 case ETH_SS_STATS: 4699 return CAS_NUM_STAT_KEYS; 4700 default: 4701 return -EOPNOTSUPP; 4702 } 4703 } 4704 4705 static void cas_get_strings(struct net_device *dev, u32 stringset, u8 *data) 4706 { 4707 memcpy(data, ðtool_cassini_statnames, 4708 CAS_NUM_STAT_KEYS * ETH_GSTRING_LEN); 4709 } 4710 4711 static void cas_get_ethtool_stats(struct net_device *dev, 4712 struct ethtool_stats *estats, u64 *data) 4713 { 4714 struct cas *cp = netdev_priv(dev); 4715 struct net_device_stats *stats = cas_get_stats(cp->dev); 4716 int i = 0; 4717 data[i++] = stats->collisions; 4718 data[i++] = stats->rx_bytes; 4719 data[i++] = stats->rx_crc_errors; 4720 data[i++] = stats->rx_dropped; 4721 data[i++] = stats->rx_errors; 4722 data[i++] = stats->rx_fifo_errors; 4723 data[i++] = stats->rx_frame_errors; 4724 data[i++] = stats->rx_length_errors; 4725 data[i++] = stats->rx_over_errors; 4726 data[i++] = stats->rx_packets; 4727 data[i++] = stats->tx_aborted_errors; 4728 data[i++] = stats->tx_bytes; 4729 data[i++] = stats->tx_dropped; 4730 data[i++] = stats->tx_errors; 4731 data[i++] = stats->tx_fifo_errors; 4732 data[i++] = stats->tx_packets; 4733 BUG_ON(i != CAS_NUM_STAT_KEYS); 4734 } 4735 4736 static const struct ethtool_ops cas_ethtool_ops = { 4737 .get_drvinfo = cas_get_drvinfo, 4738 .nway_reset = cas_nway_reset, 4739 .get_link = cas_get_link, 4740 .get_msglevel = cas_get_msglevel, 4741 .set_msglevel = cas_set_msglevel, 4742 .get_regs_len = cas_get_regs_len, 4743 .get_regs = cas_get_regs, 4744 .get_sset_count = cas_get_sset_count, 4745 .get_strings = cas_get_strings, 4746 .get_ethtool_stats = cas_get_ethtool_stats, 4747 .get_link_ksettings = cas_get_link_ksettings, 4748 .set_link_ksettings = cas_set_link_ksettings, 4749 }; 4750 4751 static int cas_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd) 4752 { 4753 struct cas *cp = netdev_priv(dev); 4754 struct mii_ioctl_data *data = if_mii(ifr); 4755 unsigned long flags; 4756 int rc = -EOPNOTSUPP; 4757 4758 /* Hold the PM mutex while doing ioctl's or we may collide 4759 * with open/close and power management and oops. 4760 */ 4761 mutex_lock(&cp->pm_mutex); 4762 switch (cmd) { 4763 case SIOCGMIIPHY: /* Get address of MII PHY in use. */ 4764 data->phy_id = cp->phy_addr; 4765 fallthrough; 4766 4767 case SIOCGMIIREG: /* Read MII PHY register. */ 4768 spin_lock_irqsave(&cp->lock, flags); 4769 cas_mif_poll(cp, 0); 4770 data->val_out = cas_phy_read(cp, data->reg_num & 0x1f); 4771 cas_mif_poll(cp, 1); 4772 spin_unlock_irqrestore(&cp->lock, flags); 4773 rc = 0; 4774 break; 4775 4776 case SIOCSMIIREG: /* Write MII PHY register. */ 4777 spin_lock_irqsave(&cp->lock, flags); 4778 cas_mif_poll(cp, 0); 4779 rc = cas_phy_write(cp, data->reg_num & 0x1f, data->val_in); 4780 cas_mif_poll(cp, 1); 4781 spin_unlock_irqrestore(&cp->lock, flags); 4782 break; 4783 default: 4784 break; 4785 } 4786 4787 mutex_unlock(&cp->pm_mutex); 4788 return rc; 4789 } 4790 4791 /* When this chip sits underneath an Intel 31154 bridge, it is the 4792 * only subordinate device and we can tweak the bridge settings to 4793 * reflect that fact. 4794 */ 4795 static void cas_program_bridge(struct pci_dev *cas_pdev) 4796 { 4797 struct pci_dev *pdev = cas_pdev->bus->self; 4798 u32 val; 4799 4800 if (!pdev) 4801 return; 4802 4803 if (pdev->vendor != 0x8086 || pdev->device != 0x537c) 4804 return; 4805 4806 /* Clear bit 10 (Bus Parking Control) in the Secondary 4807 * Arbiter Control/Status Register which lives at offset 4808 * 0x41. Using a 32-bit word read/modify/write at 0x40 4809 * is much simpler so that's how we do this. 4810 */ 4811 pci_read_config_dword(pdev, 0x40, &val); 4812 val &= ~0x00040000; 4813 pci_write_config_dword(pdev, 0x40, val); 4814 4815 /* Max out the Multi-Transaction Timer settings since 4816 * Cassini is the only device present. 4817 * 4818 * The register is 16-bit and lives at 0x50. When the 4819 * settings are enabled, it extends the GRANT# signal 4820 * for a requestor after a transaction is complete. This 4821 * allows the next request to run without first needing 4822 * to negotiate the GRANT# signal back. 4823 * 4824 * Bits 12:10 define the grant duration: 4825 * 4826 * 1 -- 16 clocks 4827 * 2 -- 32 clocks 4828 * 3 -- 64 clocks 4829 * 4 -- 128 clocks 4830 * 5 -- 256 clocks 4831 * 4832 * All other values are illegal. 4833 * 4834 * Bits 09:00 define which REQ/GNT signal pairs get the 4835 * GRANT# signal treatment. We set them all. 4836 */ 4837 pci_write_config_word(pdev, 0x50, (5 << 10) | 0x3ff); 4838 4839 /* The Read Prefecth Policy register is 16-bit and sits at 4840 * offset 0x52. It enables a "smart" pre-fetch policy. We 4841 * enable it and max out all of the settings since only one 4842 * device is sitting underneath and thus bandwidth sharing is 4843 * not an issue. 4844 * 4845 * The register has several 3 bit fields, which indicates a 4846 * multiplier applied to the base amount of prefetching the 4847 * chip would do. These fields are at: 4848 * 4849 * 15:13 --- ReRead Primary Bus 4850 * 12:10 --- FirstRead Primary Bus 4851 * 09:07 --- ReRead Secondary Bus 4852 * 06:04 --- FirstRead Secondary Bus 4853 * 4854 * Bits 03:00 control which REQ/GNT pairs the prefetch settings 4855 * get enabled on. Bit 3 is a grouped enabler which controls 4856 * all of the REQ/GNT pairs from [8:3]. Bits 2 to 0 control 4857 * the individual REQ/GNT pairs [2:0]. 4858 */ 4859 pci_write_config_word(pdev, 0x52, 4860 (0x7 << 13) | 4861 (0x7 << 10) | 4862 (0x7 << 7) | 4863 (0x7 << 4) | 4864 (0xf << 0)); 4865 4866 /* Force cacheline size to 0x8 */ 4867 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08); 4868 4869 /* Force latency timer to maximum setting so Cassini can 4870 * sit on the bus as long as it likes. 4871 */ 4872 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xff); 4873 } 4874 4875 static const struct net_device_ops cas_netdev_ops = { 4876 .ndo_open = cas_open, 4877 .ndo_stop = cas_close, 4878 .ndo_start_xmit = cas_start_xmit, 4879 .ndo_get_stats = cas_get_stats, 4880 .ndo_set_rx_mode = cas_set_multicast, 4881 .ndo_eth_ioctl = cas_ioctl, 4882 .ndo_tx_timeout = cas_tx_timeout, 4883 .ndo_change_mtu = cas_change_mtu, 4884 .ndo_set_mac_address = eth_mac_addr, 4885 .ndo_validate_addr = eth_validate_addr, 4886 #ifdef CONFIG_NET_POLL_CONTROLLER 4887 .ndo_poll_controller = cas_netpoll, 4888 #endif 4889 }; 4890 4891 static int cas_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) 4892 { 4893 static int cas_version_printed = 0; 4894 unsigned long casreg_len; 4895 struct net_device *dev; 4896 struct cas *cp; 4897 u16 pci_cmd; 4898 int i, err; 4899 u8 orig_cacheline_size = 0, cas_cacheline_size = 0; 4900 4901 if (cas_version_printed++ == 0) 4902 pr_info("%s", version); 4903 4904 err = pci_enable_device(pdev); 4905 if (err) { 4906 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n"); 4907 return err; 4908 } 4909 4910 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { 4911 dev_err(&pdev->dev, "Cannot find proper PCI device " 4912 "base address, aborting\n"); 4913 err = -ENODEV; 4914 goto err_out_disable_pdev; 4915 } 4916 4917 dev = alloc_etherdev(sizeof(*cp)); 4918 if (!dev) { 4919 err = -ENOMEM; 4920 goto err_out_disable_pdev; 4921 } 4922 SET_NETDEV_DEV(dev, &pdev->dev); 4923 4924 err = pci_request_regions(pdev, dev->name); 4925 if (err) { 4926 dev_err(&pdev->dev, "Cannot obtain PCI resources, aborting\n"); 4927 goto err_out_free_netdev; 4928 } 4929 pci_set_master(pdev); 4930 4931 /* we must always turn on parity response or else parity 4932 * doesn't get generated properly. disable SERR/PERR as well. 4933 * in addition, we want to turn MWI on. 4934 */ 4935 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 4936 pci_cmd &= ~PCI_COMMAND_SERR; 4937 pci_cmd |= PCI_COMMAND_PARITY; 4938 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 4939 if (pci_try_set_mwi(pdev)) 4940 pr_warn("Could not enable MWI for %s\n", pci_name(pdev)); 4941 4942 cas_program_bridge(pdev); 4943 4944 /* 4945 * On some architectures, the default cache line size set 4946 * by pci_try_set_mwi reduces perforamnce. We have to increase 4947 * it for this case. To start, we'll print some configuration 4948 * data. 4949 */ 4950 #if 1 4951 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, 4952 &orig_cacheline_size); 4953 if (orig_cacheline_size < CAS_PREF_CACHELINE_SIZE) { 4954 cas_cacheline_size = 4955 (CAS_PREF_CACHELINE_SIZE < SMP_CACHE_BYTES) ? 4956 CAS_PREF_CACHELINE_SIZE : SMP_CACHE_BYTES; 4957 if (pci_write_config_byte(pdev, 4958 PCI_CACHE_LINE_SIZE, 4959 cas_cacheline_size)) { 4960 dev_err(&pdev->dev, "Could not set PCI cache " 4961 "line size\n"); 4962 goto err_out_free_res; 4963 } 4964 } 4965 #endif 4966 4967 4968 /* Configure DMA attributes. */ 4969 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 4970 if (err) { 4971 dev_err(&pdev->dev, "No usable DMA configuration, aborting\n"); 4972 goto err_out_free_res; 4973 } 4974 4975 casreg_len = pci_resource_len(pdev, 0); 4976 4977 cp = netdev_priv(dev); 4978 cp->pdev = pdev; 4979 #if 1 4980 /* A value of 0 indicates we never explicitly set it */ 4981 cp->orig_cacheline_size = cas_cacheline_size ? orig_cacheline_size: 0; 4982 #endif 4983 cp->dev = dev; 4984 cp->msg_enable = (cassini_debug < 0) ? CAS_DEF_MSG_ENABLE : 4985 cassini_debug; 4986 4987 #if defined(CONFIG_SPARC) 4988 cp->of_node = pci_device_to_OF_node(pdev); 4989 #endif 4990 4991 cp->link_transition = LINK_TRANSITION_UNKNOWN; 4992 cp->link_transition_jiffies_valid = 0; 4993 4994 spin_lock_init(&cp->lock); 4995 spin_lock_init(&cp->rx_inuse_lock); 4996 spin_lock_init(&cp->rx_spare_lock); 4997 for (i = 0; i < N_TX_RINGS; i++) { 4998 spin_lock_init(&cp->stat_lock[i]); 4999 spin_lock_init(&cp->tx_lock[i]); 5000 } 5001 spin_lock_init(&cp->stat_lock[N_TX_RINGS]); 5002 mutex_init(&cp->pm_mutex); 5003 5004 timer_setup(&cp->link_timer, cas_link_timer, 0); 5005 5006 #if 1 5007 /* Just in case the implementation of atomic operations 5008 * change so that an explicit initialization is necessary. 5009 */ 5010 atomic_set(&cp->reset_task_pending, 0); 5011 atomic_set(&cp->reset_task_pending_all, 0); 5012 atomic_set(&cp->reset_task_pending_spare, 0); 5013 atomic_set(&cp->reset_task_pending_mtu, 0); 5014 #endif 5015 INIT_WORK(&cp->reset_task, cas_reset_task); 5016 5017 /* Default link parameters */ 5018 if (link_mode >= 0 && link_mode < 6) 5019 cp->link_cntl = link_modes[link_mode]; 5020 else 5021 cp->link_cntl = BMCR_ANENABLE; 5022 cp->lstate = link_down; 5023 cp->link_transition = LINK_TRANSITION_LINK_DOWN; 5024 netif_carrier_off(cp->dev); 5025 cp->timer_ticks = 0; 5026 5027 /* give us access to cassini registers */ 5028 cp->regs = pci_iomap(pdev, 0, casreg_len); 5029 if (!cp->regs) { 5030 dev_err(&pdev->dev, "Cannot map device registers, aborting\n"); 5031 goto err_out_free_res; 5032 } 5033 cp->casreg_len = casreg_len; 5034 5035 pci_save_state(pdev); 5036 cas_check_pci_invariants(cp); 5037 cas_hard_reset(cp); 5038 cas_reset(cp, 0); 5039 if (cas_check_invariants(cp)) 5040 goto err_out_iounmap; 5041 if (cp->cas_flags & CAS_FLAG_SATURN) 5042 cas_saturn_firmware_init(cp); 5043 5044 cp->init_block = 5045 dma_alloc_coherent(&pdev->dev, sizeof(struct cas_init_block), 5046 &cp->block_dvma, GFP_KERNEL); 5047 if (!cp->init_block) { 5048 dev_err(&pdev->dev, "Cannot allocate init block, aborting\n"); 5049 goto err_out_iounmap; 5050 } 5051 5052 for (i = 0; i < N_TX_RINGS; i++) 5053 cp->init_txds[i] = cp->init_block->txds[i]; 5054 5055 for (i = 0; i < N_RX_DESC_RINGS; i++) 5056 cp->init_rxds[i] = cp->init_block->rxds[i]; 5057 5058 for (i = 0; i < N_RX_COMP_RINGS; i++) 5059 cp->init_rxcs[i] = cp->init_block->rxcs[i]; 5060 5061 for (i = 0; i < N_RX_FLOWS; i++) 5062 skb_queue_head_init(&cp->rx_flows[i]); 5063 5064 dev->netdev_ops = &cas_netdev_ops; 5065 dev->ethtool_ops = &cas_ethtool_ops; 5066 dev->watchdog_timeo = CAS_TX_TIMEOUT; 5067 5068 #ifdef USE_NAPI 5069 netif_napi_add(dev, &cp->napi, cas_poll, 64); 5070 #endif 5071 dev->irq = pdev->irq; 5072 dev->dma = 0; 5073 5074 /* Cassini features. */ 5075 if ((cp->cas_flags & CAS_FLAG_NO_HW_CSUM) == 0) 5076 dev->features |= NETIF_F_HW_CSUM | NETIF_F_SG; 5077 5078 dev->features |= NETIF_F_HIGHDMA; 5079 5080 /* MTU range: 60 - varies or 9000 */ 5081 dev->min_mtu = CAS_MIN_MTU; 5082 dev->max_mtu = CAS_MAX_MTU; 5083 5084 if (register_netdev(dev)) { 5085 dev_err(&pdev->dev, "Cannot register net device, aborting\n"); 5086 goto err_out_free_consistent; 5087 } 5088 5089 i = readl(cp->regs + REG_BIM_CFG); 5090 netdev_info(dev, "Sun Cassini%s (%sbit/%sMHz PCI/%s) Ethernet[%d] %pM\n", 5091 (cp->cas_flags & CAS_FLAG_REG_PLUS) ? "+" : "", 5092 (i & BIM_CFG_32BIT) ? "32" : "64", 5093 (i & BIM_CFG_66MHZ) ? "66" : "33", 5094 (cp->phy_type == CAS_PHY_SERDES) ? "Fi" : "Cu", pdev->irq, 5095 dev->dev_addr); 5096 5097 pci_set_drvdata(pdev, dev); 5098 cp->hw_running = 1; 5099 cas_entropy_reset(cp); 5100 cas_phy_init(cp); 5101 cas_begin_auto_negotiation(cp, NULL); 5102 return 0; 5103 5104 err_out_free_consistent: 5105 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block), 5106 cp->init_block, cp->block_dvma); 5107 5108 err_out_iounmap: 5109 mutex_lock(&cp->pm_mutex); 5110 if (cp->hw_running) 5111 cas_shutdown(cp); 5112 mutex_unlock(&cp->pm_mutex); 5113 5114 pci_iounmap(pdev, cp->regs); 5115 5116 5117 err_out_free_res: 5118 pci_release_regions(pdev); 5119 5120 /* Try to restore it in case the error occurred after we 5121 * set it. 5122 */ 5123 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, orig_cacheline_size); 5124 5125 err_out_free_netdev: 5126 free_netdev(dev); 5127 5128 err_out_disable_pdev: 5129 pci_disable_device(pdev); 5130 return -ENODEV; 5131 } 5132 5133 static void cas_remove_one(struct pci_dev *pdev) 5134 { 5135 struct net_device *dev = pci_get_drvdata(pdev); 5136 struct cas *cp; 5137 if (!dev) 5138 return; 5139 5140 cp = netdev_priv(dev); 5141 unregister_netdev(dev); 5142 5143 vfree(cp->fw_data); 5144 5145 mutex_lock(&cp->pm_mutex); 5146 cancel_work_sync(&cp->reset_task); 5147 if (cp->hw_running) 5148 cas_shutdown(cp); 5149 mutex_unlock(&cp->pm_mutex); 5150 5151 #if 1 5152 if (cp->orig_cacheline_size) { 5153 /* Restore the cache line size if we had modified 5154 * it. 5155 */ 5156 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 5157 cp->orig_cacheline_size); 5158 } 5159 #endif 5160 dma_free_coherent(&pdev->dev, sizeof(struct cas_init_block), 5161 cp->init_block, cp->block_dvma); 5162 pci_iounmap(pdev, cp->regs); 5163 free_netdev(dev); 5164 pci_release_regions(pdev); 5165 pci_disable_device(pdev); 5166 } 5167 5168 static int __maybe_unused cas_suspend(struct device *dev_d) 5169 { 5170 struct net_device *dev = dev_get_drvdata(dev_d); 5171 struct cas *cp = netdev_priv(dev); 5172 unsigned long flags; 5173 5174 mutex_lock(&cp->pm_mutex); 5175 5176 /* If the driver is opened, we stop the DMA */ 5177 if (cp->opened) { 5178 netif_device_detach(dev); 5179 5180 cas_lock_all_save(cp, flags); 5181 5182 /* We can set the second arg of cas_reset to 0 5183 * because on resume, we'll call cas_init_hw with 5184 * its second arg set so that autonegotiation is 5185 * restarted. 5186 */ 5187 cas_reset(cp, 0); 5188 cas_clean_rings(cp); 5189 cas_unlock_all_restore(cp, flags); 5190 } 5191 5192 if (cp->hw_running) 5193 cas_shutdown(cp); 5194 mutex_unlock(&cp->pm_mutex); 5195 5196 return 0; 5197 } 5198 5199 static int __maybe_unused cas_resume(struct device *dev_d) 5200 { 5201 struct net_device *dev = dev_get_drvdata(dev_d); 5202 struct cas *cp = netdev_priv(dev); 5203 5204 netdev_info(dev, "resuming\n"); 5205 5206 mutex_lock(&cp->pm_mutex); 5207 cas_hard_reset(cp); 5208 if (cp->opened) { 5209 unsigned long flags; 5210 cas_lock_all_save(cp, flags); 5211 cas_reset(cp, 0); 5212 cp->hw_running = 1; 5213 cas_clean_rings(cp); 5214 cas_init_hw(cp, 1); 5215 cas_unlock_all_restore(cp, flags); 5216 5217 netif_device_attach(dev); 5218 } 5219 mutex_unlock(&cp->pm_mutex); 5220 return 0; 5221 } 5222 5223 static SIMPLE_DEV_PM_OPS(cas_pm_ops, cas_suspend, cas_resume); 5224 5225 static struct pci_driver cas_driver = { 5226 .name = DRV_MODULE_NAME, 5227 .id_table = cas_pci_tbl, 5228 .probe = cas_init_one, 5229 .remove = cas_remove_one, 5230 .driver.pm = &cas_pm_ops, 5231 }; 5232 5233 static int __init cas_init(void) 5234 { 5235 if (linkdown_timeout > 0) 5236 link_transition_timeout = linkdown_timeout * HZ; 5237 else 5238 link_transition_timeout = 0; 5239 5240 return pci_register_driver(&cas_driver); 5241 } 5242 5243 static void __exit cas_cleanup(void) 5244 { 5245 pci_unregister_driver(&cas_driver); 5246 } 5247 5248 module_init(cas_init); 5249 module_exit(cas_cleanup); 5250