1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 2 /* 3 * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. 4 * stmmac TC Handling (HW only) 5 */ 6 7 #include <net/pkt_cls.h> 8 #include <net/tc_act/tc_gact.h> 9 #include "common.h" 10 #include "dwmac4.h" 11 #include "dwmac5.h" 12 #include "stmmac.h" 13 14 static void tc_fill_all_pass_entry(struct stmmac_tc_entry *entry) 15 { 16 memset(entry, 0, sizeof(*entry)); 17 entry->in_use = true; 18 entry->is_last = true; 19 entry->is_frag = false; 20 entry->prio = ~0x0; 21 entry->handle = 0; 22 entry->val.match_data = 0x0; 23 entry->val.match_en = 0x0; 24 entry->val.af = 1; 25 entry->val.dma_ch_no = 0x0; 26 } 27 28 static struct stmmac_tc_entry *tc_find_entry(struct stmmac_priv *priv, 29 struct tc_cls_u32_offload *cls, 30 bool free) 31 { 32 struct stmmac_tc_entry *entry, *first = NULL, *dup = NULL; 33 u32 loc = cls->knode.handle; 34 int i; 35 36 for (i = 0; i < priv->tc_entries_max; i++) { 37 entry = &priv->tc_entries[i]; 38 if (!entry->in_use && !first && free) 39 first = entry; 40 if ((entry->handle == loc) && !free && !entry->is_frag) 41 dup = entry; 42 } 43 44 if (dup) 45 return dup; 46 if (first) { 47 first->handle = loc; 48 first->in_use = true; 49 50 /* Reset HW values */ 51 memset(&first->val, 0, sizeof(first->val)); 52 } 53 54 return first; 55 } 56 57 static int tc_fill_actions(struct stmmac_tc_entry *entry, 58 struct stmmac_tc_entry *frag, 59 struct tc_cls_u32_offload *cls) 60 { 61 struct stmmac_tc_entry *action_entry = entry; 62 const struct tc_action *act; 63 struct tcf_exts *exts; 64 int i; 65 66 exts = cls->knode.exts; 67 if (!tcf_exts_has_actions(exts)) 68 return -EINVAL; 69 if (frag) 70 action_entry = frag; 71 72 tcf_exts_for_each_action(i, act, exts) { 73 /* Accept */ 74 if (is_tcf_gact_ok(act)) { 75 action_entry->val.af = 1; 76 break; 77 } 78 /* Drop */ 79 if (is_tcf_gact_shot(act)) { 80 action_entry->val.rf = 1; 81 break; 82 } 83 84 /* Unsupported */ 85 return -EINVAL; 86 } 87 88 return 0; 89 } 90 91 static int tc_fill_entry(struct stmmac_priv *priv, 92 struct tc_cls_u32_offload *cls) 93 { 94 struct stmmac_tc_entry *entry, *frag = NULL; 95 struct tc_u32_sel *sel = cls->knode.sel; 96 u32 off, data, mask, real_off, rem; 97 u32 prio = cls->common.prio << 16; 98 int ret; 99 100 /* Only 1 match per entry */ 101 if (sel->nkeys <= 0 || sel->nkeys > 1) 102 return -EINVAL; 103 104 off = sel->keys[0].off << sel->offshift; 105 data = sel->keys[0].val; 106 mask = sel->keys[0].mask; 107 108 switch (ntohs(cls->common.protocol)) { 109 case ETH_P_ALL: 110 break; 111 case ETH_P_IP: 112 off += ETH_HLEN; 113 break; 114 default: 115 return -EINVAL; 116 } 117 118 if (off > priv->tc_off_max) 119 return -EINVAL; 120 121 real_off = off / 4; 122 rem = off % 4; 123 124 entry = tc_find_entry(priv, cls, true); 125 if (!entry) 126 return -EINVAL; 127 128 if (rem) { 129 frag = tc_find_entry(priv, cls, true); 130 if (!frag) { 131 ret = -EINVAL; 132 goto err_unuse; 133 } 134 135 entry->frag_ptr = frag; 136 entry->val.match_en = (mask << (rem * 8)) & 137 GENMASK(31, rem * 8); 138 entry->val.match_data = (data << (rem * 8)) & 139 GENMASK(31, rem * 8); 140 entry->val.frame_offset = real_off; 141 entry->prio = prio; 142 143 frag->val.match_en = (mask >> (rem * 8)) & 144 GENMASK(rem * 8 - 1, 0); 145 frag->val.match_data = (data >> (rem * 8)) & 146 GENMASK(rem * 8 - 1, 0); 147 frag->val.frame_offset = real_off + 1; 148 frag->prio = prio; 149 frag->is_frag = true; 150 } else { 151 entry->frag_ptr = NULL; 152 entry->val.match_en = mask; 153 entry->val.match_data = data; 154 entry->val.frame_offset = real_off; 155 entry->prio = prio; 156 } 157 158 ret = tc_fill_actions(entry, frag, cls); 159 if (ret) 160 goto err_unuse; 161 162 return 0; 163 164 err_unuse: 165 if (frag) 166 frag->in_use = false; 167 entry->in_use = false; 168 return ret; 169 } 170 171 static void tc_unfill_entry(struct stmmac_priv *priv, 172 struct tc_cls_u32_offload *cls) 173 { 174 struct stmmac_tc_entry *entry; 175 176 entry = tc_find_entry(priv, cls, false); 177 if (!entry) 178 return; 179 180 entry->in_use = false; 181 if (entry->frag_ptr) { 182 entry = entry->frag_ptr; 183 entry->is_frag = false; 184 entry->in_use = false; 185 } 186 } 187 188 static int tc_config_knode(struct stmmac_priv *priv, 189 struct tc_cls_u32_offload *cls) 190 { 191 int ret; 192 193 ret = tc_fill_entry(priv, cls); 194 if (ret) 195 return ret; 196 197 ret = stmmac_rxp_config(priv, priv->hw->pcsr, priv->tc_entries, 198 priv->tc_entries_max); 199 if (ret) 200 goto err_unfill; 201 202 return 0; 203 204 err_unfill: 205 tc_unfill_entry(priv, cls); 206 return ret; 207 } 208 209 static int tc_delete_knode(struct stmmac_priv *priv, 210 struct tc_cls_u32_offload *cls) 211 { 212 /* Set entry and fragments as not used */ 213 tc_unfill_entry(priv, cls); 214 215 return stmmac_rxp_config(priv, priv->hw->pcsr, priv->tc_entries, 216 priv->tc_entries_max); 217 } 218 219 static int tc_setup_cls_u32(struct stmmac_priv *priv, 220 struct tc_cls_u32_offload *cls) 221 { 222 switch (cls->command) { 223 case TC_CLSU32_REPLACE_KNODE: 224 tc_unfill_entry(priv, cls); 225 fallthrough; 226 case TC_CLSU32_NEW_KNODE: 227 return tc_config_knode(priv, cls); 228 case TC_CLSU32_DELETE_KNODE: 229 return tc_delete_knode(priv, cls); 230 default: 231 return -EOPNOTSUPP; 232 } 233 } 234 235 static int tc_rfs_init(struct stmmac_priv *priv) 236 { 237 int i; 238 239 priv->rfs_entries_max[STMMAC_RFS_T_VLAN] = 8; 240 priv->rfs_entries_max[STMMAC_RFS_T_LLDP] = 1; 241 priv->rfs_entries_max[STMMAC_RFS_T_1588] = 1; 242 243 for (i = 0; i < STMMAC_RFS_T_MAX; i++) 244 priv->rfs_entries_total += priv->rfs_entries_max[i]; 245 246 priv->rfs_entries = devm_kcalloc(priv->device, 247 priv->rfs_entries_total, 248 sizeof(*priv->rfs_entries), 249 GFP_KERNEL); 250 if (!priv->rfs_entries) 251 return -ENOMEM; 252 253 dev_info(priv->device, "Enabled RFS Flow TC (entries=%d)\n", 254 priv->rfs_entries_total); 255 256 return 0; 257 } 258 259 static int tc_init(struct stmmac_priv *priv) 260 { 261 struct dma_features *dma_cap = &priv->dma_cap; 262 unsigned int count; 263 int ret, i; 264 265 if (dma_cap->l3l4fnum) { 266 priv->flow_entries_max = dma_cap->l3l4fnum; 267 priv->flow_entries = devm_kcalloc(priv->device, 268 dma_cap->l3l4fnum, 269 sizeof(*priv->flow_entries), 270 GFP_KERNEL); 271 if (!priv->flow_entries) 272 return -ENOMEM; 273 274 for (i = 0; i < priv->flow_entries_max; i++) 275 priv->flow_entries[i].idx = i; 276 277 dev_info(priv->device, "Enabled L3L4 Flow TC (entries=%d)\n", 278 priv->flow_entries_max); 279 } 280 281 ret = tc_rfs_init(priv); 282 if (ret) 283 return -ENOMEM; 284 285 if (!priv->plat->fpe_cfg) { 286 priv->plat->fpe_cfg = devm_kzalloc(priv->device, 287 sizeof(*priv->plat->fpe_cfg), 288 GFP_KERNEL); 289 if (!priv->plat->fpe_cfg) 290 return -ENOMEM; 291 } else { 292 memset(priv->plat->fpe_cfg, 0, sizeof(*priv->plat->fpe_cfg)); 293 } 294 295 /* Fail silently as we can still use remaining features, e.g. CBS */ 296 if (!dma_cap->frpsel) 297 return 0; 298 299 switch (dma_cap->frpbs) { 300 case 0x0: 301 priv->tc_off_max = 64; 302 break; 303 case 0x1: 304 priv->tc_off_max = 128; 305 break; 306 case 0x2: 307 priv->tc_off_max = 256; 308 break; 309 default: 310 return -EINVAL; 311 } 312 313 switch (dma_cap->frpes) { 314 case 0x0: 315 count = 64; 316 break; 317 case 0x1: 318 count = 128; 319 break; 320 case 0x2: 321 count = 256; 322 break; 323 default: 324 return -EINVAL; 325 } 326 327 /* Reserve one last filter which lets all pass */ 328 priv->tc_entries_max = count; 329 priv->tc_entries = devm_kcalloc(priv->device, 330 count, sizeof(*priv->tc_entries), GFP_KERNEL); 331 if (!priv->tc_entries) 332 return -ENOMEM; 333 334 tc_fill_all_pass_entry(&priv->tc_entries[count - 1]); 335 336 dev_info(priv->device, "Enabling HW TC (entries=%d, max_off=%d)\n", 337 priv->tc_entries_max, priv->tc_off_max); 338 339 return 0; 340 } 341 342 static int tc_setup_cbs(struct stmmac_priv *priv, 343 struct tc_cbs_qopt_offload *qopt) 344 { 345 u32 tx_queues_count = priv->plat->tx_queues_to_use; 346 s64 port_transmit_rate_kbps; 347 u32 queue = qopt->queue; 348 u32 mode_to_use; 349 u64 value; 350 u32 ptr; 351 int ret; 352 353 /* Queue 0 is not AVB capable */ 354 if (queue <= 0 || queue >= tx_queues_count) 355 return -EINVAL; 356 if (!priv->dma_cap.av) 357 return -EOPNOTSUPP; 358 359 port_transmit_rate_kbps = qopt->idleslope - qopt->sendslope; 360 361 /* Port Transmit Rate and Speed Divider */ 362 switch (div_s64(port_transmit_rate_kbps, 1000)) { 363 case SPEED_10000: 364 case SPEED_5000: 365 ptr = 32; 366 break; 367 case SPEED_2500: 368 case SPEED_1000: 369 ptr = 8; 370 break; 371 case SPEED_100: 372 ptr = 4; 373 break; 374 default: 375 netdev_err(priv->dev, 376 "Invalid portTransmitRate %lld (idleSlope - sendSlope)\n", 377 port_transmit_rate_kbps); 378 return -EINVAL; 379 } 380 381 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 382 if (mode_to_use == MTL_QUEUE_DCB && qopt->enable) { 383 ret = stmmac_dma_qmode(priv, priv->ioaddr, queue, MTL_QUEUE_AVB); 384 if (ret) 385 return ret; 386 387 priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_AVB; 388 } else if (!qopt->enable) { 389 ret = stmmac_dma_qmode(priv, priv->ioaddr, queue, 390 MTL_QUEUE_DCB); 391 if (ret) 392 return ret; 393 394 priv->plat->tx_queues_cfg[queue].mode_to_use = MTL_QUEUE_DCB; 395 } 396 397 /* Final adjustments for HW */ 398 value = div_s64(qopt->idleslope * 1024ll * ptr, port_transmit_rate_kbps); 399 priv->plat->tx_queues_cfg[queue].idle_slope = value & GENMASK(31, 0); 400 401 value = div_s64(-qopt->sendslope * 1024ll * ptr, port_transmit_rate_kbps); 402 priv->plat->tx_queues_cfg[queue].send_slope = value & GENMASK(31, 0); 403 404 value = qopt->hicredit * 1024ll * 8; 405 priv->plat->tx_queues_cfg[queue].high_credit = value & GENMASK(31, 0); 406 407 value = qopt->locredit * 1024ll * 8; 408 priv->plat->tx_queues_cfg[queue].low_credit = value & GENMASK(31, 0); 409 410 ret = stmmac_config_cbs(priv, priv->hw, 411 priv->plat->tx_queues_cfg[queue].send_slope, 412 priv->plat->tx_queues_cfg[queue].idle_slope, 413 priv->plat->tx_queues_cfg[queue].high_credit, 414 priv->plat->tx_queues_cfg[queue].low_credit, 415 queue); 416 if (ret) 417 return ret; 418 419 dev_info(priv->device, "CBS queue %d: send %d, idle %d, hi %d, lo %d\n", 420 queue, qopt->sendslope, qopt->idleslope, 421 qopt->hicredit, qopt->locredit); 422 return 0; 423 } 424 425 static int tc_parse_flow_actions(struct stmmac_priv *priv, 426 struct flow_action *action, 427 struct stmmac_flow_entry *entry, 428 struct netlink_ext_ack *extack) 429 { 430 struct flow_action_entry *act; 431 int i; 432 433 if (!flow_action_has_entries(action)) 434 return -EINVAL; 435 436 if (!flow_action_basic_hw_stats_check(action, extack)) 437 return -EOPNOTSUPP; 438 439 flow_action_for_each(i, act, action) { 440 switch (act->id) { 441 case FLOW_ACTION_DROP: 442 entry->action |= STMMAC_FLOW_ACTION_DROP; 443 return 0; 444 default: 445 break; 446 } 447 } 448 449 /* Nothing to do, maybe inverse filter ? */ 450 return 0; 451 } 452 453 #define ETHER_TYPE_FULL_MASK cpu_to_be16(~0) 454 455 static int tc_add_basic_flow(struct stmmac_priv *priv, 456 struct flow_cls_offload *cls, 457 struct stmmac_flow_entry *entry) 458 { 459 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 460 struct flow_dissector *dissector = rule->match.dissector; 461 struct flow_match_basic match; 462 463 /* Nothing to do here */ 464 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_BASIC)) 465 return -EINVAL; 466 467 flow_rule_match_basic(rule, &match); 468 469 entry->ip_proto = match.key->ip_proto; 470 return 0; 471 } 472 473 static int tc_add_ip4_flow(struct stmmac_priv *priv, 474 struct flow_cls_offload *cls, 475 struct stmmac_flow_entry *entry) 476 { 477 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 478 struct flow_dissector *dissector = rule->match.dissector; 479 bool inv = entry->action & STMMAC_FLOW_ACTION_DROP; 480 struct flow_match_ipv4_addrs match; 481 u32 hw_match; 482 int ret; 483 484 /* Nothing to do here */ 485 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_IPV4_ADDRS)) 486 return -EINVAL; 487 488 flow_rule_match_ipv4_addrs(rule, &match); 489 hw_match = ntohl(match.key->src) & ntohl(match.mask->src); 490 if (hw_match) { 491 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, true, 492 false, true, inv, hw_match); 493 if (ret) 494 return ret; 495 } 496 497 hw_match = ntohl(match.key->dst) & ntohl(match.mask->dst); 498 if (hw_match) { 499 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, true, 500 false, false, inv, hw_match); 501 if (ret) 502 return ret; 503 } 504 505 return 0; 506 } 507 508 static int tc_add_ports_flow(struct stmmac_priv *priv, 509 struct flow_cls_offload *cls, 510 struct stmmac_flow_entry *entry) 511 { 512 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 513 struct flow_dissector *dissector = rule->match.dissector; 514 bool inv = entry->action & STMMAC_FLOW_ACTION_DROP; 515 struct flow_match_ports match; 516 u32 hw_match; 517 bool is_udp; 518 int ret; 519 520 /* Nothing to do here */ 521 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_PORTS)) 522 return -EINVAL; 523 524 switch (entry->ip_proto) { 525 case IPPROTO_TCP: 526 is_udp = false; 527 break; 528 case IPPROTO_UDP: 529 is_udp = true; 530 break; 531 default: 532 return -EINVAL; 533 } 534 535 flow_rule_match_ports(rule, &match); 536 537 hw_match = ntohs(match.key->src) & ntohs(match.mask->src); 538 if (hw_match) { 539 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, true, 540 is_udp, true, inv, hw_match); 541 if (ret) 542 return ret; 543 } 544 545 hw_match = ntohs(match.key->dst) & ntohs(match.mask->dst); 546 if (hw_match) { 547 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, true, 548 is_udp, false, inv, hw_match); 549 if (ret) 550 return ret; 551 } 552 553 entry->is_l4 = true; 554 return 0; 555 } 556 557 static struct stmmac_flow_entry *tc_find_flow(struct stmmac_priv *priv, 558 struct flow_cls_offload *cls, 559 bool get_free) 560 { 561 int i; 562 563 for (i = 0; i < priv->flow_entries_max; i++) { 564 struct stmmac_flow_entry *entry = &priv->flow_entries[i]; 565 566 if (entry->cookie == cls->cookie) 567 return entry; 568 if (get_free && (entry->in_use == false)) 569 return entry; 570 } 571 572 return NULL; 573 } 574 575 static struct { 576 int (*fn)(struct stmmac_priv *priv, struct flow_cls_offload *cls, 577 struct stmmac_flow_entry *entry); 578 } tc_flow_parsers[] = { 579 { .fn = tc_add_basic_flow }, 580 { .fn = tc_add_ip4_flow }, 581 { .fn = tc_add_ports_flow }, 582 }; 583 584 static int tc_add_flow(struct stmmac_priv *priv, 585 struct flow_cls_offload *cls) 586 { 587 struct stmmac_flow_entry *entry = tc_find_flow(priv, cls, false); 588 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 589 int i, ret; 590 591 if (!entry) { 592 entry = tc_find_flow(priv, cls, true); 593 if (!entry) 594 return -ENOENT; 595 } 596 597 ret = tc_parse_flow_actions(priv, &rule->action, entry, 598 cls->common.extack); 599 if (ret) 600 return ret; 601 602 for (i = 0; i < ARRAY_SIZE(tc_flow_parsers); i++) { 603 ret = tc_flow_parsers[i].fn(priv, cls, entry); 604 if (!ret) 605 entry->in_use = true; 606 } 607 608 if (!entry->in_use) 609 return -EINVAL; 610 611 entry->cookie = cls->cookie; 612 return 0; 613 } 614 615 static int tc_del_flow(struct stmmac_priv *priv, 616 struct flow_cls_offload *cls) 617 { 618 struct stmmac_flow_entry *entry = tc_find_flow(priv, cls, false); 619 int ret; 620 621 if (!entry || !entry->in_use) 622 return -ENOENT; 623 624 if (entry->is_l4) { 625 ret = stmmac_config_l4_filter(priv, priv->hw, entry->idx, false, 626 false, false, false, 0); 627 } else { 628 ret = stmmac_config_l3_filter(priv, priv->hw, entry->idx, false, 629 false, false, false, 0); 630 } 631 632 entry->in_use = false; 633 entry->cookie = 0; 634 entry->is_l4 = false; 635 return ret; 636 } 637 638 static struct stmmac_rfs_entry *tc_find_rfs(struct stmmac_priv *priv, 639 struct flow_cls_offload *cls, 640 bool get_free) 641 { 642 int i; 643 644 for (i = 0; i < priv->rfs_entries_total; i++) { 645 struct stmmac_rfs_entry *entry = &priv->rfs_entries[i]; 646 647 if (entry->cookie == cls->cookie) 648 return entry; 649 if (get_free && entry->in_use == false) 650 return entry; 651 } 652 653 return NULL; 654 } 655 656 #define VLAN_PRIO_FULL_MASK (0x07) 657 658 static int tc_add_vlan_flow(struct stmmac_priv *priv, 659 struct flow_cls_offload *cls) 660 { 661 struct stmmac_rfs_entry *entry = tc_find_rfs(priv, cls, false); 662 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 663 struct flow_dissector *dissector = rule->match.dissector; 664 int tc = tc_classid_to_hwtc(priv->dev, cls->classid); 665 struct flow_match_vlan match; 666 667 if (!entry) { 668 entry = tc_find_rfs(priv, cls, true); 669 if (!entry) 670 return -ENOENT; 671 } 672 673 if (priv->rfs_entries_cnt[STMMAC_RFS_T_VLAN] >= 674 priv->rfs_entries_max[STMMAC_RFS_T_VLAN]) 675 return -ENOENT; 676 677 /* Nothing to do here */ 678 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_VLAN)) 679 return -EINVAL; 680 681 if (tc < 0) { 682 netdev_err(priv->dev, "Invalid traffic class\n"); 683 return -EINVAL; 684 } 685 686 flow_rule_match_vlan(rule, &match); 687 688 if (match.mask->vlan_priority) { 689 u32 prio; 690 691 if (match.mask->vlan_priority != VLAN_PRIO_FULL_MASK) { 692 netdev_err(priv->dev, "Only full mask is supported for VLAN priority"); 693 return -EINVAL; 694 } 695 696 prio = BIT(match.key->vlan_priority); 697 stmmac_rx_queue_prio(priv, priv->hw, prio, tc); 698 699 entry->in_use = true; 700 entry->cookie = cls->cookie; 701 entry->tc = tc; 702 entry->type = STMMAC_RFS_T_VLAN; 703 priv->rfs_entries_cnt[STMMAC_RFS_T_VLAN]++; 704 } 705 706 return 0; 707 } 708 709 static int tc_del_vlan_flow(struct stmmac_priv *priv, 710 struct flow_cls_offload *cls) 711 { 712 struct stmmac_rfs_entry *entry = tc_find_rfs(priv, cls, false); 713 714 if (!entry || !entry->in_use || entry->type != STMMAC_RFS_T_VLAN) 715 return -ENOENT; 716 717 stmmac_rx_queue_prio(priv, priv->hw, 0, entry->tc); 718 719 entry->in_use = false; 720 entry->cookie = 0; 721 entry->tc = 0; 722 entry->type = 0; 723 724 priv->rfs_entries_cnt[STMMAC_RFS_T_VLAN]--; 725 726 return 0; 727 } 728 729 static int tc_add_ethtype_flow(struct stmmac_priv *priv, 730 struct flow_cls_offload *cls) 731 { 732 struct stmmac_rfs_entry *entry = tc_find_rfs(priv, cls, false); 733 struct flow_rule *rule = flow_cls_offload_flow_rule(cls); 734 struct flow_dissector *dissector = rule->match.dissector; 735 int tc = tc_classid_to_hwtc(priv->dev, cls->classid); 736 struct flow_match_basic match; 737 738 if (!entry) { 739 entry = tc_find_rfs(priv, cls, true); 740 if (!entry) 741 return -ENOENT; 742 } 743 744 /* Nothing to do here */ 745 if (!dissector_uses_key(dissector, FLOW_DISSECTOR_KEY_BASIC)) 746 return -EINVAL; 747 748 if (tc < 0) { 749 netdev_err(priv->dev, "Invalid traffic class\n"); 750 return -EINVAL; 751 } 752 753 flow_rule_match_basic(rule, &match); 754 755 if (match.mask->n_proto) { 756 u16 etype = ntohs(match.key->n_proto); 757 758 if (match.mask->n_proto != ETHER_TYPE_FULL_MASK) { 759 netdev_err(priv->dev, "Only full mask is supported for EthType filter"); 760 return -EINVAL; 761 } 762 switch (etype) { 763 case ETH_P_LLDP: 764 if (priv->rfs_entries_cnt[STMMAC_RFS_T_LLDP] >= 765 priv->rfs_entries_max[STMMAC_RFS_T_LLDP]) 766 return -ENOENT; 767 768 entry->type = STMMAC_RFS_T_LLDP; 769 priv->rfs_entries_cnt[STMMAC_RFS_T_LLDP]++; 770 771 stmmac_rx_queue_routing(priv, priv->hw, 772 PACKET_DCBCPQ, tc); 773 break; 774 case ETH_P_1588: 775 if (priv->rfs_entries_cnt[STMMAC_RFS_T_1588] >= 776 priv->rfs_entries_max[STMMAC_RFS_T_1588]) 777 return -ENOENT; 778 779 entry->type = STMMAC_RFS_T_1588; 780 priv->rfs_entries_cnt[STMMAC_RFS_T_1588]++; 781 782 stmmac_rx_queue_routing(priv, priv->hw, 783 PACKET_PTPQ, tc); 784 break; 785 default: 786 netdev_err(priv->dev, "EthType(0x%x) is not supported", etype); 787 return -EINVAL; 788 } 789 790 entry->in_use = true; 791 entry->cookie = cls->cookie; 792 entry->tc = tc; 793 entry->etype = etype; 794 795 return 0; 796 } 797 798 return -EINVAL; 799 } 800 801 static int tc_del_ethtype_flow(struct stmmac_priv *priv, 802 struct flow_cls_offload *cls) 803 { 804 struct stmmac_rfs_entry *entry = tc_find_rfs(priv, cls, false); 805 806 if (!entry || !entry->in_use || 807 entry->type < STMMAC_RFS_T_LLDP || 808 entry->type > STMMAC_RFS_T_1588) 809 return -ENOENT; 810 811 switch (entry->etype) { 812 case ETH_P_LLDP: 813 stmmac_rx_queue_routing(priv, priv->hw, 814 PACKET_DCBCPQ, 0); 815 priv->rfs_entries_cnt[STMMAC_RFS_T_LLDP]--; 816 break; 817 case ETH_P_1588: 818 stmmac_rx_queue_routing(priv, priv->hw, 819 PACKET_PTPQ, 0); 820 priv->rfs_entries_cnt[STMMAC_RFS_T_1588]--; 821 break; 822 default: 823 netdev_err(priv->dev, "EthType(0x%x) is not supported", 824 entry->etype); 825 return -EINVAL; 826 } 827 828 entry->in_use = false; 829 entry->cookie = 0; 830 entry->tc = 0; 831 entry->etype = 0; 832 entry->type = 0; 833 834 return 0; 835 } 836 837 static int tc_add_flow_cls(struct stmmac_priv *priv, 838 struct flow_cls_offload *cls) 839 { 840 int ret; 841 842 ret = tc_add_flow(priv, cls); 843 if (!ret) 844 return ret; 845 846 ret = tc_add_ethtype_flow(priv, cls); 847 if (!ret) 848 return ret; 849 850 return tc_add_vlan_flow(priv, cls); 851 } 852 853 static int tc_del_flow_cls(struct stmmac_priv *priv, 854 struct flow_cls_offload *cls) 855 { 856 int ret; 857 858 ret = tc_del_flow(priv, cls); 859 if (!ret) 860 return ret; 861 862 ret = tc_del_ethtype_flow(priv, cls); 863 if (!ret) 864 return ret; 865 866 return tc_del_vlan_flow(priv, cls); 867 } 868 869 static int tc_setup_cls(struct stmmac_priv *priv, 870 struct flow_cls_offload *cls) 871 { 872 int ret = 0; 873 874 /* When RSS is enabled, the filtering will be bypassed */ 875 if (priv->rss.enable) 876 return -EBUSY; 877 878 switch (cls->command) { 879 case FLOW_CLS_REPLACE: 880 ret = tc_add_flow_cls(priv, cls); 881 break; 882 case FLOW_CLS_DESTROY: 883 ret = tc_del_flow_cls(priv, cls); 884 break; 885 default: 886 return -EOPNOTSUPP; 887 } 888 889 return ret; 890 } 891 892 struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time, 893 ktime_t current_time, 894 u64 cycle_time) 895 { 896 struct timespec64 time; 897 898 if (ktime_after(old_base_time, current_time)) { 899 time = ktime_to_timespec64(old_base_time); 900 } else { 901 s64 n; 902 ktime_t base_time; 903 904 n = div64_s64(ktime_sub_ns(current_time, old_base_time), 905 cycle_time); 906 base_time = ktime_add_ns(old_base_time, 907 (n + 1) * cycle_time); 908 909 time = ktime_to_timespec64(base_time); 910 } 911 912 return time; 913 } 914 915 static void tc_taprio_map_maxsdu_txq(struct stmmac_priv *priv, 916 struct tc_taprio_qopt_offload *qopt) 917 { 918 u32 num_tc = qopt->mqprio.qopt.num_tc; 919 u32 offset, count, i, j; 920 921 /* QueueMaxSDU received from the driver corresponds to the Linux traffic 922 * class. Map queueMaxSDU per Linux traffic class to DWMAC Tx queues. 923 */ 924 for (i = 0; i < num_tc; i++) { 925 if (!qopt->max_sdu[i]) 926 continue; 927 928 offset = qopt->mqprio.qopt.offset[i]; 929 count = qopt->mqprio.qopt.count[i]; 930 931 for (j = offset; j < offset + count; j++) 932 priv->est->max_sdu[j] = qopt->max_sdu[i] + ETH_HLEN - ETH_TLEN; 933 } 934 } 935 936 static int tc_taprio_configure(struct stmmac_priv *priv, 937 struct tc_taprio_qopt_offload *qopt) 938 { 939 u32 size, wid = priv->dma_cap.estwid, dep = priv->dma_cap.estdep; 940 struct timespec64 time, current_time, qopt_time; 941 ktime_t current_time_ns; 942 bool fpe = false; 943 int i, ret = 0; 944 u64 ctr; 945 946 if (qopt->base_time < 0) 947 return -ERANGE; 948 949 if (!priv->dma_cap.estsel) 950 return -EOPNOTSUPP; 951 952 switch (wid) { 953 case 0x1: 954 wid = 16; 955 break; 956 case 0x2: 957 wid = 20; 958 break; 959 case 0x3: 960 wid = 24; 961 break; 962 default: 963 return -EOPNOTSUPP; 964 } 965 966 switch (dep) { 967 case 0x1: 968 dep = 64; 969 break; 970 case 0x2: 971 dep = 128; 972 break; 973 case 0x3: 974 dep = 256; 975 break; 976 case 0x4: 977 dep = 512; 978 break; 979 case 0x5: 980 dep = 1024; 981 break; 982 default: 983 return -EOPNOTSUPP; 984 } 985 986 if (qopt->cmd == TAPRIO_CMD_DESTROY) 987 goto disable; 988 989 if (qopt->num_entries >= dep) 990 return -EINVAL; 991 if (!qopt->cycle_time) 992 return -ERANGE; 993 if (qopt->cycle_time_extension >= BIT(wid + 7)) 994 return -ERANGE; 995 996 if (!priv->est) { 997 priv->est = devm_kzalloc(priv->device, sizeof(*priv->est), 998 GFP_KERNEL); 999 if (!priv->est) 1000 return -ENOMEM; 1001 1002 mutex_init(&priv->est_lock); 1003 } else { 1004 mutex_lock(&priv->est_lock); 1005 memset(priv->est, 0, sizeof(*priv->est)); 1006 mutex_unlock(&priv->est_lock); 1007 } 1008 1009 size = qopt->num_entries; 1010 1011 mutex_lock(&priv->est_lock); 1012 priv->est->gcl_size = size; 1013 priv->est->enable = qopt->cmd == TAPRIO_CMD_REPLACE; 1014 mutex_unlock(&priv->est_lock); 1015 1016 for (i = 0; i < size; i++) { 1017 s64 delta_ns = qopt->entries[i].interval; 1018 u32 gates = qopt->entries[i].gate_mask; 1019 1020 if (delta_ns > GENMASK(wid, 0)) 1021 return -ERANGE; 1022 if (gates > GENMASK(31 - wid, 0)) 1023 return -ERANGE; 1024 1025 switch (qopt->entries[i].command) { 1026 case TC_TAPRIO_CMD_SET_GATES: 1027 if (fpe) 1028 return -EINVAL; 1029 break; 1030 case TC_TAPRIO_CMD_SET_AND_HOLD: 1031 gates |= BIT(0); 1032 fpe = true; 1033 break; 1034 case TC_TAPRIO_CMD_SET_AND_RELEASE: 1035 gates &= ~BIT(0); 1036 fpe = true; 1037 break; 1038 default: 1039 return -EOPNOTSUPP; 1040 } 1041 1042 priv->est->gcl[i] = delta_ns | (gates << wid); 1043 } 1044 1045 mutex_lock(&priv->est_lock); 1046 /* Adjust for real system time */ 1047 priv->ptp_clock_ops.gettime64(&priv->ptp_clock_ops, ¤t_time); 1048 current_time_ns = timespec64_to_ktime(current_time); 1049 time = stmmac_calc_tas_basetime(qopt->base_time, current_time_ns, 1050 qopt->cycle_time); 1051 1052 priv->est->btr[0] = (u32)time.tv_nsec; 1053 priv->est->btr[1] = (u32)time.tv_sec; 1054 1055 qopt_time = ktime_to_timespec64(qopt->base_time); 1056 priv->est->btr_reserve[0] = (u32)qopt_time.tv_nsec; 1057 priv->est->btr_reserve[1] = (u32)qopt_time.tv_sec; 1058 1059 ctr = qopt->cycle_time; 1060 priv->est->ctr[0] = do_div(ctr, NSEC_PER_SEC); 1061 priv->est->ctr[1] = (u32)ctr; 1062 1063 priv->est->ter = qopt->cycle_time_extension; 1064 1065 tc_taprio_map_maxsdu_txq(priv, qopt); 1066 1067 if (fpe && !priv->dma_cap.fpesel) { 1068 mutex_unlock(&priv->est_lock); 1069 return -EOPNOTSUPP; 1070 } 1071 1072 /* Actual FPE register configuration will be done after FPE handshake 1073 * is success. 1074 */ 1075 priv->plat->fpe_cfg->enable = fpe; 1076 1077 ret = stmmac_est_configure(priv, priv, priv->est, 1078 priv->plat->clk_ptp_rate); 1079 mutex_unlock(&priv->est_lock); 1080 if (ret) { 1081 netdev_err(priv->dev, "failed to configure EST\n"); 1082 goto disable; 1083 } 1084 1085 netdev_info(priv->dev, "configured EST\n"); 1086 1087 if (fpe) { 1088 stmmac_fpe_handshake(priv, true); 1089 netdev_info(priv->dev, "start FPE handshake\n"); 1090 } 1091 1092 return 0; 1093 1094 disable: 1095 if (priv->est) { 1096 mutex_lock(&priv->est_lock); 1097 priv->est->enable = false; 1098 stmmac_est_configure(priv, priv, priv->est, 1099 priv->plat->clk_ptp_rate); 1100 /* Reset taprio status */ 1101 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 1102 priv->xstats.max_sdu_txq_drop[i] = 0; 1103 priv->xstats.mtl_est_txq_hlbf[i] = 0; 1104 } 1105 mutex_unlock(&priv->est_lock); 1106 } 1107 1108 priv->plat->fpe_cfg->enable = false; 1109 stmmac_fpe_configure(priv, priv->ioaddr, 1110 priv->plat->fpe_cfg, 1111 priv->plat->tx_queues_to_use, 1112 priv->plat->rx_queues_to_use, 1113 false); 1114 netdev_info(priv->dev, "disabled FPE\n"); 1115 1116 stmmac_fpe_handshake(priv, false); 1117 netdev_info(priv->dev, "stop FPE handshake\n"); 1118 1119 return ret; 1120 } 1121 1122 static void tc_taprio_stats(struct stmmac_priv *priv, 1123 struct tc_taprio_qopt_offload *qopt) 1124 { 1125 u64 window_drops = 0; 1126 int i = 0; 1127 1128 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 1129 window_drops += priv->xstats.max_sdu_txq_drop[i] + 1130 priv->xstats.mtl_est_txq_hlbf[i]; 1131 qopt->stats.window_drops = window_drops; 1132 1133 /* Transmission overrun doesn't happen for stmmac, hence always 0 */ 1134 qopt->stats.tx_overruns = 0; 1135 } 1136 1137 static void tc_taprio_queue_stats(struct stmmac_priv *priv, 1138 struct tc_taprio_qopt_offload *qopt) 1139 { 1140 struct tc_taprio_qopt_queue_stats *q_stats = &qopt->queue_stats; 1141 int queue = qopt->queue_stats.queue; 1142 1143 q_stats->stats.window_drops = priv->xstats.max_sdu_txq_drop[queue] + 1144 priv->xstats.mtl_est_txq_hlbf[queue]; 1145 1146 /* Transmission overrun doesn't happen for stmmac, hence always 0 */ 1147 q_stats->stats.tx_overruns = 0; 1148 } 1149 1150 static int tc_setup_taprio(struct stmmac_priv *priv, 1151 struct tc_taprio_qopt_offload *qopt) 1152 { 1153 int err = 0; 1154 1155 switch (qopt->cmd) { 1156 case TAPRIO_CMD_REPLACE: 1157 case TAPRIO_CMD_DESTROY: 1158 err = tc_taprio_configure(priv, qopt); 1159 break; 1160 case TAPRIO_CMD_STATS: 1161 tc_taprio_stats(priv, qopt); 1162 break; 1163 case TAPRIO_CMD_QUEUE_STATS: 1164 tc_taprio_queue_stats(priv, qopt); 1165 break; 1166 default: 1167 err = -EOPNOTSUPP; 1168 } 1169 1170 return err; 1171 } 1172 1173 static int tc_setup_etf(struct stmmac_priv *priv, 1174 struct tc_etf_qopt_offload *qopt) 1175 { 1176 if (!priv->dma_cap.tbssel) 1177 return -EOPNOTSUPP; 1178 if (qopt->queue >= priv->plat->tx_queues_to_use) 1179 return -EINVAL; 1180 if (!(priv->dma_conf.tx_queue[qopt->queue].tbs & STMMAC_TBS_AVAIL)) 1181 return -EINVAL; 1182 1183 if (qopt->enable) 1184 priv->dma_conf.tx_queue[qopt->queue].tbs |= STMMAC_TBS_EN; 1185 else 1186 priv->dma_conf.tx_queue[qopt->queue].tbs &= ~STMMAC_TBS_EN; 1187 1188 netdev_info(priv->dev, "%s ETF for Queue %d\n", 1189 qopt->enable ? "enabled" : "disabled", qopt->queue); 1190 return 0; 1191 } 1192 1193 static int tc_query_caps(struct stmmac_priv *priv, 1194 struct tc_query_caps_base *base) 1195 { 1196 switch (base->type) { 1197 case TC_SETUP_QDISC_TAPRIO: { 1198 struct tc_taprio_caps *caps = base->caps; 1199 1200 if (!priv->dma_cap.estsel) 1201 return -EOPNOTSUPP; 1202 1203 caps->gate_mask_per_txq = true; 1204 caps->supports_queue_max_sdu = true; 1205 1206 return 0; 1207 } 1208 default: 1209 return -EOPNOTSUPP; 1210 } 1211 } 1212 1213 const struct stmmac_tc_ops dwmac510_tc_ops = { 1214 .init = tc_init, 1215 .setup_cls_u32 = tc_setup_cls_u32, 1216 .setup_cbs = tc_setup_cbs, 1217 .setup_cls = tc_setup_cls, 1218 .setup_taprio = tc_setup_taprio, 1219 .setup_etf = tc_setup_etf, 1220 .query_caps = tc_query_caps, 1221 }; 1222