1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethernet Driver -- MDIO bus implementation 4 Provides Bus interface for MII registers 5 6 Copyright (C) 2007-2009 STMicroelectronics Ltd 7 8 9 Author: Carl Shaw <carl.shaw@st.com> 10 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> 11 *******************************************************************************/ 12 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/mii.h> 17 #include <linux/of_mdio.h> 18 #include <linux/phy.h> 19 #include <linux/property.h> 20 #include <linux/slab.h> 21 22 #include "dwxgmac2.h" 23 #include "stmmac.h" 24 25 #define MII_BUSY 0x00000001 26 #define MII_WRITE 0x00000002 27 28 /* GMAC4 defines */ 29 #define MII_GMAC4_GOC_SHIFT 2 30 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT) 31 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT) 32 33 /* XGMAC defines */ 34 #define MII_XGMAC_SADDR BIT(18) 35 #define MII_XGMAC_CMD_SHIFT 16 36 #define MII_XGMAC_WRITE (1 << MII_XGMAC_CMD_SHIFT) 37 #define MII_XGMAC_READ (3 << MII_XGMAC_CMD_SHIFT) 38 #define MII_XGMAC_BUSY BIT(22) 39 #define MII_XGMAC_MAX_C22ADDR 3 40 #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0) 41 42 static int stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, 43 int phyreg, u32 *hw_addr) 44 { 45 unsigned int mii_data = priv->hw->mii.data; 46 u32 tmp; 47 48 /* HW does not support C22 addr >= 4 */ 49 if (phyaddr > MII_XGMAC_MAX_C22ADDR) 50 return -ENODEV; 51 /* Wait until any existing MII operation is complete */ 52 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 53 !(tmp & MII_XGMAC_BUSY), 100, 10000)) 54 return -EBUSY; 55 56 /* Set port as Clause 22 */ 57 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); 58 tmp &= ~MII_XGMAC_C22P_MASK; 59 tmp |= BIT(phyaddr); 60 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); 61 62 *hw_addr = (phyaddr << 16) | (phyreg & 0x1f); 63 return 0; 64 } 65 66 static int stmmac_xgmac2_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) 67 { 68 struct net_device *ndev = bus->priv; 69 struct stmmac_priv *priv = netdev_priv(ndev); 70 unsigned int mii_address = priv->hw->mii.addr; 71 unsigned int mii_data = priv->hw->mii.data; 72 u32 tmp, addr, value = MII_XGMAC_BUSY; 73 int ret; 74 75 if (phyreg & MII_ADDR_C45) { 76 return -EOPNOTSUPP; 77 } else { 78 ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 79 if (ret) 80 return ret; 81 } 82 83 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 84 & priv->hw->mii.clk_csr_mask; 85 value |= MII_XGMAC_SADDR | MII_XGMAC_READ; 86 87 /* Wait until any existing MII operation is complete */ 88 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 89 !(tmp & MII_XGMAC_BUSY), 100, 10000)) 90 return -EBUSY; 91 92 /* Set the MII address register to read */ 93 writel(addr, priv->ioaddr + mii_address); 94 writel(value, priv->ioaddr + mii_data); 95 96 /* Wait until any existing MII operation is complete */ 97 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 98 !(tmp & MII_XGMAC_BUSY), 100, 10000)) 99 return -EBUSY; 100 101 /* Read the data from the MII data register */ 102 return readl(priv->ioaddr + mii_data) & GENMASK(15, 0); 103 } 104 105 static int stmmac_xgmac2_mdio_write(struct mii_bus *bus, int phyaddr, 106 int phyreg, u16 phydata) 107 { 108 struct net_device *ndev = bus->priv; 109 struct stmmac_priv *priv = netdev_priv(ndev); 110 unsigned int mii_address = priv->hw->mii.addr; 111 unsigned int mii_data = priv->hw->mii.data; 112 u32 addr, tmp, value = MII_XGMAC_BUSY; 113 int ret; 114 115 if (phyreg & MII_ADDR_C45) { 116 return -EOPNOTSUPP; 117 } else { 118 ret = stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 119 if (ret) 120 return ret; 121 } 122 123 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 124 & priv->hw->mii.clk_csr_mask; 125 value |= phydata | MII_XGMAC_SADDR; 126 value |= MII_XGMAC_WRITE; 127 128 /* Wait until any existing MII operation is complete */ 129 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 130 !(tmp & MII_XGMAC_BUSY), 100, 10000)) 131 return -EBUSY; 132 133 /* Set the MII address register to write */ 134 writel(addr, priv->ioaddr + mii_address); 135 writel(value, priv->ioaddr + mii_data); 136 137 /* Wait until any existing MII operation is complete */ 138 return readl_poll_timeout(priv->ioaddr + mii_data, tmp, 139 !(tmp & MII_XGMAC_BUSY), 100, 10000); 140 } 141 142 /** 143 * stmmac_mdio_read 144 * @bus: points to the mii_bus structure 145 * @phyaddr: MII addr 146 * @phyreg: MII reg 147 * Description: it reads data from the MII register from within the phy device. 148 * For the 7111 GMAC, we must set the bit 0 in the MII address register while 149 * accessing the PHY registers. 150 * Fortunately, it seems this has no drawback for the 7109 MAC. 151 */ 152 static int stmmac_mdio_read(struct mii_bus *bus, int phyaddr, int phyreg) 153 { 154 struct net_device *ndev = bus->priv; 155 struct stmmac_priv *priv = netdev_priv(ndev); 156 unsigned int mii_address = priv->hw->mii.addr; 157 unsigned int mii_data = priv->hw->mii.data; 158 u32 v; 159 int data; 160 u32 value = MII_BUSY; 161 162 value |= (phyaddr << priv->hw->mii.addr_shift) 163 & priv->hw->mii.addr_mask; 164 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 165 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 166 & priv->hw->mii.clk_csr_mask; 167 if (priv->plat->has_gmac4) 168 value |= MII_GMAC4_READ; 169 170 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 171 100, 10000)) 172 return -EBUSY; 173 174 writel(value, priv->ioaddr + mii_address); 175 176 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 177 100, 10000)) 178 return -EBUSY; 179 180 /* Read the data from the MII data register */ 181 data = (int)readl(priv->ioaddr + mii_data); 182 183 return data; 184 } 185 186 /** 187 * stmmac_mdio_write 188 * @bus: points to the mii_bus structure 189 * @phyaddr: MII addr 190 * @phyreg: MII reg 191 * @phydata: phy data 192 * Description: it writes the data into the MII register from within the device. 193 */ 194 static int stmmac_mdio_write(struct mii_bus *bus, int phyaddr, int phyreg, 195 u16 phydata) 196 { 197 struct net_device *ndev = bus->priv; 198 struct stmmac_priv *priv = netdev_priv(ndev); 199 unsigned int mii_address = priv->hw->mii.addr; 200 unsigned int mii_data = priv->hw->mii.data; 201 u32 v; 202 u32 value = MII_BUSY; 203 204 value |= (phyaddr << priv->hw->mii.addr_shift) 205 & priv->hw->mii.addr_mask; 206 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 207 208 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 209 & priv->hw->mii.clk_csr_mask; 210 if (priv->plat->has_gmac4) 211 value |= MII_GMAC4_WRITE; 212 else 213 value |= MII_WRITE; 214 215 /* Wait until any existing MII operation is complete */ 216 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 217 100, 10000)) 218 return -EBUSY; 219 220 /* Set the MII address register to write */ 221 writel(phydata, priv->ioaddr + mii_data); 222 writel(value, priv->ioaddr + mii_address); 223 224 /* Wait until any existing MII operation is complete */ 225 return readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 226 100, 10000); 227 } 228 229 /** 230 * stmmac_mdio_reset 231 * @bus: points to the mii_bus structure 232 * Description: reset the MII bus 233 */ 234 int stmmac_mdio_reset(struct mii_bus *bus) 235 { 236 #if IS_ENABLED(CONFIG_STMMAC_PLATFORM) 237 struct net_device *ndev = bus->priv; 238 struct stmmac_priv *priv = netdev_priv(ndev); 239 unsigned int mii_address = priv->hw->mii.addr; 240 241 #ifdef CONFIG_OF 242 if (priv->device->of_node) { 243 struct gpio_desc *reset_gpio; 244 u32 delays[3] = { 0, 0, 0 }; 245 int ret; 246 247 reset_gpio = devm_gpiod_get_optional(priv->device, 248 "snps,reset", 249 GPIOD_OUT_LOW); 250 if (IS_ERR(reset_gpio)) 251 return PTR_ERR(reset_gpio); 252 253 ret = device_property_read_u32_array(priv->device, 254 "snps,reset-delays-us", 255 delays, 256 ARRAY_SIZE(delays)); 257 if (ret) { 258 dev_err(ndev->dev.parent, 259 "invalid property snps,reset-delays-us\n"); 260 return -EINVAL; 261 } 262 263 if (delays[0]) 264 msleep(DIV_ROUND_UP(delays[0], 1000)); 265 266 gpiod_set_value_cansleep(reset_gpio, 1); 267 if (delays[1]) 268 msleep(DIV_ROUND_UP(delays[1], 1000)); 269 270 gpiod_set_value_cansleep(reset_gpio, 0); 271 if (delays[2]) 272 msleep(DIV_ROUND_UP(delays[2], 1000)); 273 } 274 #endif 275 276 /* This is a workaround for problems with the STE101P PHY. 277 * It doesn't complete its reset until at least one clock cycle 278 * on MDC, so perform a dummy mdio read. To be updated for GMAC4 279 * if needed. 280 */ 281 if (!priv->plat->has_gmac4) 282 writel(0, priv->ioaddr + mii_address); 283 #endif 284 return 0; 285 } 286 287 /** 288 * stmmac_mdio_register 289 * @ndev: net device structure 290 * Description: it registers the MII bus 291 */ 292 int stmmac_mdio_register(struct net_device *ndev) 293 { 294 int err = 0; 295 struct mii_bus *new_bus; 296 struct stmmac_priv *priv = netdev_priv(ndev); 297 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 298 struct device_node *mdio_node = priv->plat->mdio_node; 299 struct device *dev = ndev->dev.parent; 300 int addr, found, max_addr; 301 302 if (!mdio_bus_data) 303 return 0; 304 305 new_bus = mdiobus_alloc(); 306 if (!new_bus) 307 return -ENOMEM; 308 309 if (mdio_bus_data->irqs) 310 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq)); 311 312 new_bus->name = "stmmac"; 313 314 if (priv->plat->has_xgmac) { 315 new_bus->read = &stmmac_xgmac2_mdio_read; 316 new_bus->write = &stmmac_xgmac2_mdio_write; 317 318 /* Right now only C22 phys are supported */ 319 max_addr = MII_XGMAC_MAX_C22ADDR + 1; 320 321 /* Check if DT specified an unsupported phy addr */ 322 if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR) 323 dev_err(dev, "Unsupported phy_addr (max=%d)\n", 324 MII_XGMAC_MAX_C22ADDR); 325 } else { 326 new_bus->read = &stmmac_mdio_read; 327 new_bus->write = &stmmac_mdio_write; 328 max_addr = PHY_MAX_ADDR; 329 } 330 331 new_bus->reset = &stmmac_mdio_reset; 332 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", 333 new_bus->name, priv->plat->bus_id); 334 new_bus->priv = ndev; 335 new_bus->phy_mask = mdio_bus_data->phy_mask; 336 new_bus->parent = priv->device; 337 338 err = of_mdiobus_register(new_bus, mdio_node); 339 if (err != 0) { 340 dev_err(dev, "Cannot register the MDIO bus\n"); 341 goto bus_register_fail; 342 } 343 344 if (priv->plat->phy_node || mdio_node) 345 goto bus_register_done; 346 347 found = 0; 348 for (addr = 0; addr < max_addr; addr++) { 349 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr); 350 351 if (!phydev) 352 continue; 353 354 /* 355 * If an IRQ was provided to be assigned after 356 * the bus probe, do it here. 357 */ 358 if (!mdio_bus_data->irqs && 359 (mdio_bus_data->probed_phy_irq > 0)) { 360 new_bus->irq[addr] = mdio_bus_data->probed_phy_irq; 361 phydev->irq = mdio_bus_data->probed_phy_irq; 362 } 363 364 /* 365 * If we're going to bind the MAC to this PHY bus, 366 * and no PHY number was provided to the MAC, 367 * use the one probed here. 368 */ 369 if (priv->plat->phy_addr == -1) 370 priv->plat->phy_addr = addr; 371 372 phy_attached_info(phydev); 373 found = 1; 374 } 375 376 if (!found && !mdio_node) { 377 dev_warn(dev, "No PHY found\n"); 378 mdiobus_unregister(new_bus); 379 mdiobus_free(new_bus); 380 return -ENODEV; 381 } 382 383 bus_register_done: 384 priv->mii = new_bus; 385 386 return 0; 387 388 bus_register_fail: 389 mdiobus_free(new_bus); 390 return err; 391 } 392 393 /** 394 * stmmac_mdio_unregister 395 * @ndev: net device structure 396 * Description: it unregisters the MII bus 397 */ 398 int stmmac_mdio_unregister(struct net_device *ndev) 399 { 400 struct stmmac_priv *priv = netdev_priv(ndev); 401 402 if (!priv->mii) 403 return 0; 404 405 mdiobus_unregister(priv->mii); 406 priv->mii->priv = NULL; 407 mdiobus_free(priv->mii); 408 priv->mii = NULL; 409 410 return 0; 411 } 412