1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethernet Driver -- MDIO bus implementation 4 Provides Bus interface for MII registers 5 6 Copyright (C) 2007-2009 STMicroelectronics Ltd 7 8 9 Author: Carl Shaw <carl.shaw@st.com> 10 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> 11 *******************************************************************************/ 12 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/mii.h> 17 #include <linux/of_mdio.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/phy.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 23 #include "dwxgmac2.h" 24 #include "stmmac.h" 25 26 #define MII_BUSY 0x00000001 27 #define MII_WRITE 0x00000002 28 #define MII_DATA_MASK GENMASK(15, 0) 29 30 /* GMAC4 defines */ 31 #define MII_GMAC4_GOC_SHIFT 2 32 #define MII_GMAC4_REG_ADDR_SHIFT 16 33 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT) 34 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT) 35 #define MII_GMAC4_C45E BIT(1) 36 37 /* XGMAC defines */ 38 #define MII_XGMAC_SADDR BIT(18) 39 #define MII_XGMAC_CMD_SHIFT 16 40 #define MII_XGMAC_WRITE (1 << MII_XGMAC_CMD_SHIFT) 41 #define MII_XGMAC_READ (3 << MII_XGMAC_CMD_SHIFT) 42 #define MII_XGMAC_BUSY BIT(22) 43 #define MII_XGMAC_MAX_C22ADDR 3 44 #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0) 45 #define MII_XGMAC_PA_SHIFT 16 46 #define MII_XGMAC_DA_SHIFT 21 47 48 static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr, 49 int devad, int phyreg, u32 *hw_addr) 50 { 51 u32 tmp; 52 53 /* Set port as Clause 45 */ 54 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); 55 tmp &= ~BIT(phyaddr); 56 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); 57 58 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff); 59 *hw_addr |= devad << MII_XGMAC_DA_SHIFT; 60 } 61 62 static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, 63 int phyreg, u32 *hw_addr) 64 { 65 u32 tmp = 0; 66 67 if (priv->synopsys_id < DWXGMAC_CORE_2_20) { 68 /* Until ver 2.20 XGMAC does not support C22 addr >= 4. Those 69 * bits above bit 3 of XGMAC_MDIO_C22P register are reserved. 70 */ 71 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); 72 tmp &= ~MII_XGMAC_C22P_MASK; 73 } 74 /* Set port as Clause 22 */ 75 tmp |= BIT(phyaddr); 76 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); 77 78 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f); 79 } 80 81 static int stmmac_xgmac2_mdio_read(struct stmmac_priv *priv, u32 addr, 82 u32 value) 83 { 84 unsigned int mii_address = priv->hw->mii.addr; 85 unsigned int mii_data = priv->hw->mii.data; 86 u32 tmp; 87 int ret; 88 89 ret = pm_runtime_resume_and_get(priv->device); 90 if (ret < 0) 91 return ret; 92 93 /* Wait until any existing MII operation is complete */ 94 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 95 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 96 ret = -EBUSY; 97 goto err_disable_clks; 98 } 99 100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 101 & priv->hw->mii.clk_csr_mask; 102 value |= MII_XGMAC_READ; 103 104 /* Wait until any existing MII operation is complete */ 105 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 106 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 107 ret = -EBUSY; 108 goto err_disable_clks; 109 } 110 111 /* Set the MII address register to read */ 112 writel(addr, priv->ioaddr + mii_address); 113 writel(value, priv->ioaddr + mii_data); 114 115 /* Wait until any existing MII operation is complete */ 116 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 117 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 118 ret = -EBUSY; 119 goto err_disable_clks; 120 } 121 122 /* Read the data from the MII data register */ 123 ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0); 124 125 err_disable_clks: 126 pm_runtime_put(priv->device); 127 128 return ret; 129 } 130 131 static int stmmac_xgmac2_mdio_read_c22(struct mii_bus *bus, int phyaddr, 132 int phyreg) 133 { 134 struct stmmac_priv *priv = netdev_priv(bus->priv); 135 u32 addr; 136 137 /* Until ver 2.20 XGMAC does not support C22 addr >= 4 */ 138 if (priv->synopsys_id < DWXGMAC_CORE_2_20 && 139 phyaddr > MII_XGMAC_MAX_C22ADDR) 140 return -ENODEV; 141 142 stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 143 144 return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY); 145 } 146 147 static int stmmac_xgmac2_mdio_read_c45(struct mii_bus *bus, int phyaddr, 148 int devad, int phyreg) 149 { 150 struct stmmac_priv *priv = netdev_priv(bus->priv); 151 u32 addr; 152 153 stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr); 154 155 return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY); 156 } 157 158 static int stmmac_xgmac2_mdio_write(struct stmmac_priv *priv, u32 addr, 159 u32 value, u16 phydata) 160 { 161 unsigned int mii_address = priv->hw->mii.addr; 162 unsigned int mii_data = priv->hw->mii.data; 163 u32 tmp; 164 int ret; 165 166 ret = pm_runtime_resume_and_get(priv->device); 167 if (ret < 0) 168 return ret; 169 170 /* Wait until any existing MII operation is complete */ 171 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 172 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 173 ret = -EBUSY; 174 goto err_disable_clks; 175 } 176 177 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 178 & priv->hw->mii.clk_csr_mask; 179 value |= phydata; 180 value |= MII_XGMAC_WRITE; 181 182 /* Wait until any existing MII operation is complete */ 183 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 184 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 185 ret = -EBUSY; 186 goto err_disable_clks; 187 } 188 189 /* Set the MII address register to write */ 190 writel(addr, priv->ioaddr + mii_address); 191 writel(value, priv->ioaddr + mii_data); 192 193 /* Wait until any existing MII operation is complete */ 194 ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp, 195 !(tmp & MII_XGMAC_BUSY), 100, 10000); 196 197 err_disable_clks: 198 pm_runtime_put(priv->device); 199 200 return ret; 201 } 202 203 static int stmmac_xgmac2_mdio_write_c22(struct mii_bus *bus, int phyaddr, 204 int phyreg, u16 phydata) 205 { 206 struct stmmac_priv *priv = netdev_priv(bus->priv); 207 u32 addr; 208 209 /* Until ver 2.20 XGMAC does not support C22 addr >= 4 */ 210 if (priv->synopsys_id < DWXGMAC_CORE_2_20 && 211 phyaddr > MII_XGMAC_MAX_C22ADDR) 212 return -ENODEV; 213 214 stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 215 216 return stmmac_xgmac2_mdio_write(priv, addr, 217 MII_XGMAC_BUSY | MII_XGMAC_SADDR, phydata); 218 } 219 220 static int stmmac_xgmac2_mdio_write_c45(struct mii_bus *bus, int phyaddr, 221 int devad, int phyreg, u16 phydata) 222 { 223 struct stmmac_priv *priv = netdev_priv(bus->priv); 224 u32 addr; 225 226 stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr); 227 228 return stmmac_xgmac2_mdio_write(priv, addr, MII_XGMAC_BUSY, 229 phydata); 230 } 231 232 static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value) 233 { 234 unsigned int mii_address = priv->hw->mii.addr; 235 unsigned int mii_data = priv->hw->mii.data; 236 u32 v; 237 238 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 239 100, 10000)) 240 return -EBUSY; 241 242 writel(data, priv->ioaddr + mii_data); 243 writel(value, priv->ioaddr + mii_address); 244 245 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 246 100, 10000)) 247 return -EBUSY; 248 249 /* Read the data from the MII data register */ 250 return readl(priv->ioaddr + mii_data) & MII_DATA_MASK; 251 } 252 253 /** 254 * stmmac_mdio_read_c22 255 * @bus: points to the mii_bus structure 256 * @phyaddr: MII addr 257 * @phyreg: MII reg 258 * Description: it reads data from the MII register from within the phy device. 259 * For the 7111 GMAC, we must set the bit 0 in the MII address register while 260 * accessing the PHY registers. 261 * Fortunately, it seems this has no drawback for the 7109 MAC. 262 */ 263 static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg) 264 { 265 struct stmmac_priv *priv = netdev_priv(bus->priv); 266 u32 value = MII_BUSY; 267 int data = 0; 268 269 data = pm_runtime_resume_and_get(priv->device); 270 if (data < 0) 271 return data; 272 273 value |= (phyaddr << priv->hw->mii.addr_shift) 274 & priv->hw->mii.addr_mask; 275 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 276 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 277 & priv->hw->mii.clk_csr_mask; 278 if (priv->plat->has_gmac4) 279 value |= MII_GMAC4_READ; 280 281 data = stmmac_mdio_read(priv, data, value); 282 283 pm_runtime_put(priv->device); 284 285 return data; 286 } 287 288 /** 289 * stmmac_mdio_read_c45 290 * @bus: points to the mii_bus structure 291 * @phyaddr: MII addr 292 * @devad: device address to read 293 * @phyreg: MII reg 294 * Description: it reads data from the MII register from within the phy device. 295 * For the 7111 GMAC, we must set the bit 0 in the MII address register while 296 * accessing the PHY registers. 297 * Fortunately, it seems this has no drawback for the 7109 MAC. 298 */ 299 static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad, 300 int phyreg) 301 { 302 struct stmmac_priv *priv = netdev_priv(bus->priv); 303 u32 value = MII_BUSY; 304 int data = 0; 305 306 data = pm_runtime_resume_and_get(priv->device); 307 if (data < 0) 308 return data; 309 310 value |= (phyaddr << priv->hw->mii.addr_shift) 311 & priv->hw->mii.addr_mask; 312 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 313 & priv->hw->mii.clk_csr_mask; 314 value |= MII_GMAC4_READ; 315 value |= MII_GMAC4_C45E; 316 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 317 318 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; 319 320 data = stmmac_mdio_read(priv, data, value); 321 322 pm_runtime_put(priv->device); 323 324 return data; 325 } 326 327 static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value) 328 { 329 unsigned int mii_address = priv->hw->mii.addr; 330 unsigned int mii_data = priv->hw->mii.data; 331 u32 v; 332 333 /* Wait until any existing MII operation is complete */ 334 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 335 100, 10000)) 336 return -EBUSY; 337 338 /* Set the MII address register to write */ 339 writel(data, priv->ioaddr + mii_data); 340 writel(value, priv->ioaddr + mii_address); 341 342 /* Wait until any existing MII operation is complete */ 343 return readl_poll_timeout(priv->ioaddr + mii_address, v, 344 !(v & MII_BUSY), 100, 10000); 345 } 346 347 /** 348 * stmmac_mdio_write_c22 349 * @bus: points to the mii_bus structure 350 * @phyaddr: MII addr 351 * @phyreg: MII reg 352 * @phydata: phy data 353 * Description: it writes the data into the MII register from within the device. 354 */ 355 static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg, 356 u16 phydata) 357 { 358 struct stmmac_priv *priv = netdev_priv(bus->priv); 359 int ret, data = phydata; 360 u32 value = MII_BUSY; 361 362 ret = pm_runtime_resume_and_get(priv->device); 363 if (ret < 0) 364 return ret; 365 366 value |= (phyaddr << priv->hw->mii.addr_shift) 367 & priv->hw->mii.addr_mask; 368 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 369 370 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 371 & priv->hw->mii.clk_csr_mask; 372 if (priv->plat->has_gmac4) 373 value |= MII_GMAC4_WRITE; 374 else 375 value |= MII_WRITE; 376 377 ret = stmmac_mdio_write(priv, data, value); 378 379 pm_runtime_put(priv->device); 380 381 return ret; 382 } 383 384 /** 385 * stmmac_mdio_write_c45 386 * @bus: points to the mii_bus structure 387 * @phyaddr: MII addr 388 * @phyreg: MII reg 389 * @devad: device address to read 390 * @phydata: phy data 391 * Description: it writes the data into the MII register from within the device. 392 */ 393 static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr, 394 int devad, int phyreg, u16 phydata) 395 { 396 struct stmmac_priv *priv = netdev_priv(bus->priv); 397 int ret, data = phydata; 398 u32 value = MII_BUSY; 399 400 ret = pm_runtime_resume_and_get(priv->device); 401 if (ret < 0) 402 return ret; 403 404 value |= (phyaddr << priv->hw->mii.addr_shift) 405 & priv->hw->mii.addr_mask; 406 407 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 408 & priv->hw->mii.clk_csr_mask; 409 410 value |= MII_GMAC4_WRITE; 411 value |= MII_GMAC4_C45E; 412 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 413 414 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; 415 416 ret = stmmac_mdio_write(priv, data, value); 417 418 pm_runtime_put(priv->device); 419 420 return ret; 421 } 422 423 /** 424 * stmmac_mdio_reset 425 * @bus: points to the mii_bus structure 426 * Description: reset the MII bus 427 */ 428 int stmmac_mdio_reset(struct mii_bus *bus) 429 { 430 #if IS_ENABLED(CONFIG_STMMAC_PLATFORM) 431 struct stmmac_priv *priv = netdev_priv(bus->priv); 432 unsigned int mii_address = priv->hw->mii.addr; 433 434 #ifdef CONFIG_OF 435 if (priv->device->of_node) { 436 struct gpio_desc *reset_gpio; 437 u32 delays[3] = { 0, 0, 0 }; 438 439 reset_gpio = devm_gpiod_get_optional(priv->device, 440 "snps,reset", 441 GPIOD_OUT_LOW); 442 if (IS_ERR(reset_gpio)) 443 return PTR_ERR(reset_gpio); 444 445 device_property_read_u32_array(priv->device, 446 "snps,reset-delays-us", 447 delays, ARRAY_SIZE(delays)); 448 449 if (delays[0]) 450 msleep(DIV_ROUND_UP(delays[0], 1000)); 451 452 gpiod_set_value_cansleep(reset_gpio, 1); 453 if (delays[1]) 454 msleep(DIV_ROUND_UP(delays[1], 1000)); 455 456 gpiod_set_value_cansleep(reset_gpio, 0); 457 if (delays[2]) 458 msleep(DIV_ROUND_UP(delays[2], 1000)); 459 } 460 #endif 461 462 /* This is a workaround for problems with the STE101P PHY. 463 * It doesn't complete its reset until at least one clock cycle 464 * on MDC, so perform a dummy mdio read. To be updated for GMAC4 465 * if needed. 466 */ 467 if (!priv->plat->has_gmac4) 468 writel(0, priv->ioaddr + mii_address); 469 #endif 470 return 0; 471 } 472 473 int stmmac_pcs_setup(struct net_device *ndev) 474 { 475 struct stmmac_priv *priv = netdev_priv(ndev); 476 struct fwnode_handle *devnode, *pcsnode; 477 struct dw_xpcs *xpcs = NULL; 478 int addr, ret; 479 480 devnode = priv->plat->port_node; 481 482 if (priv->plat->pcs_init) { 483 ret = priv->plat->pcs_init(priv); 484 } else if (fwnode_property_present(devnode, "pcs-handle")) { 485 pcsnode = fwnode_find_reference(devnode, "pcs-handle", 0); 486 xpcs = xpcs_create_fwnode(pcsnode); 487 fwnode_handle_put(pcsnode); 488 ret = PTR_ERR_OR_ZERO(xpcs); 489 } else if (priv->plat->mdio_bus_data && 490 priv->plat->mdio_bus_data->pcs_mask) { 491 addr = ffs(priv->plat->mdio_bus_data->pcs_mask) - 1; 492 xpcs = xpcs_create_mdiodev(priv->mii, addr); 493 ret = PTR_ERR_OR_ZERO(xpcs); 494 } else { 495 return 0; 496 } 497 498 if (ret) 499 return dev_err_probe(priv->device, ret, "No xPCS found\n"); 500 501 if (xpcs) 502 xpcs_config_eee_mult_fact(xpcs, priv->plat->mult_fact_100ns); 503 504 priv->hw->xpcs = xpcs; 505 506 return 0; 507 } 508 509 void stmmac_pcs_clean(struct net_device *ndev) 510 { 511 struct stmmac_priv *priv = netdev_priv(ndev); 512 513 if (priv->plat->pcs_exit) 514 priv->plat->pcs_exit(priv); 515 516 if (!priv->hw->xpcs) 517 return; 518 519 xpcs_destroy(priv->hw->xpcs); 520 priv->hw->xpcs = NULL; 521 } 522 523 /** 524 * stmmac_mdio_register 525 * @ndev: net device structure 526 * Description: it registers the MII bus 527 */ 528 int stmmac_mdio_register(struct net_device *ndev) 529 { 530 int err = 0; 531 struct mii_bus *new_bus; 532 struct stmmac_priv *priv = netdev_priv(ndev); 533 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 534 struct device_node *mdio_node = priv->plat->mdio_node; 535 struct device *dev = ndev->dev.parent; 536 struct fwnode_handle *fixed_node; 537 struct fwnode_handle *fwnode; 538 int addr, found, max_addr; 539 540 if (!mdio_bus_data) 541 return 0; 542 543 new_bus = mdiobus_alloc(); 544 if (!new_bus) 545 return -ENOMEM; 546 547 if (mdio_bus_data->irqs) 548 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq)); 549 550 new_bus->name = "stmmac"; 551 552 if (priv->plat->has_xgmac) { 553 new_bus->read = &stmmac_xgmac2_mdio_read_c22; 554 new_bus->write = &stmmac_xgmac2_mdio_write_c22; 555 new_bus->read_c45 = &stmmac_xgmac2_mdio_read_c45; 556 new_bus->write_c45 = &stmmac_xgmac2_mdio_write_c45; 557 558 if (priv->synopsys_id < DWXGMAC_CORE_2_20) { 559 /* Right now only C22 phys are supported */ 560 max_addr = MII_XGMAC_MAX_C22ADDR + 1; 561 562 /* Check if DT specified an unsupported phy addr */ 563 if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR) 564 dev_err(dev, "Unsupported phy_addr (max=%d)\n", 565 MII_XGMAC_MAX_C22ADDR); 566 } else { 567 /* XGMAC version 2.20 onwards support 32 phy addr */ 568 max_addr = PHY_MAX_ADDR; 569 } 570 } else { 571 new_bus->read = &stmmac_mdio_read_c22; 572 new_bus->write = &stmmac_mdio_write_c22; 573 if (priv->plat->has_gmac4) { 574 new_bus->read_c45 = &stmmac_mdio_read_c45; 575 new_bus->write_c45 = &stmmac_mdio_write_c45; 576 } 577 578 max_addr = PHY_MAX_ADDR; 579 } 580 581 if (mdio_bus_data->needs_reset) 582 new_bus->reset = &stmmac_mdio_reset; 583 584 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", 585 new_bus->name, priv->plat->bus_id); 586 new_bus->priv = ndev; 587 new_bus->phy_mask = mdio_bus_data->phy_mask | mdio_bus_data->pcs_mask; 588 new_bus->parent = priv->device; 589 590 err = of_mdiobus_register(new_bus, mdio_node); 591 if (err == -ENODEV) { 592 err = 0; 593 dev_info(dev, "MDIO bus is disabled\n"); 594 goto bus_register_fail; 595 } else if (err) { 596 dev_err_probe(dev, err, "Cannot register the MDIO bus\n"); 597 goto bus_register_fail; 598 } 599 600 /* Looks like we need a dummy read for XGMAC only and C45 PHYs */ 601 if (priv->plat->has_xgmac) 602 stmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0); 603 604 /* If fixed-link is set, skip PHY scanning */ 605 fwnode = priv->plat->port_node; 606 if (!fwnode) 607 fwnode = dev_fwnode(priv->device); 608 609 if (fwnode) { 610 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link"); 611 if (fixed_node) { 612 fwnode_handle_put(fixed_node); 613 goto bus_register_done; 614 } 615 } 616 617 if (priv->plat->phy_node || mdio_node) 618 goto bus_register_done; 619 620 found = 0; 621 for (addr = 0; addr < max_addr; addr++) { 622 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr); 623 624 if (!phydev) 625 continue; 626 627 /* 628 * If an IRQ was provided to be assigned after 629 * the bus probe, do it here. 630 */ 631 if (!mdio_bus_data->irqs && 632 (mdio_bus_data->probed_phy_irq > 0)) { 633 new_bus->irq[addr] = mdio_bus_data->probed_phy_irq; 634 phydev->irq = mdio_bus_data->probed_phy_irq; 635 } 636 637 /* 638 * If we're going to bind the MAC to this PHY bus, 639 * and no PHY number was provided to the MAC, 640 * use the one probed here. 641 */ 642 if (priv->plat->phy_addr == -1) 643 priv->plat->phy_addr = addr; 644 645 phy_attached_info(phydev); 646 found = 1; 647 } 648 649 if (!found && !mdio_node) { 650 dev_warn(dev, "No PHY found\n"); 651 err = -ENODEV; 652 goto no_phy_found; 653 } 654 655 bus_register_done: 656 priv->mii = new_bus; 657 658 return 0; 659 660 no_phy_found: 661 mdiobus_unregister(new_bus); 662 bus_register_fail: 663 mdiobus_free(new_bus); 664 return err; 665 } 666 667 /** 668 * stmmac_mdio_unregister 669 * @ndev: net device structure 670 * Description: it unregisters the MII bus 671 */ 672 int stmmac_mdio_unregister(struct net_device *ndev) 673 { 674 struct stmmac_priv *priv = netdev_priv(ndev); 675 676 if (!priv->mii) 677 return 0; 678 679 mdiobus_unregister(priv->mii); 680 priv->mii->priv = NULL; 681 mdiobus_free(priv->mii); 682 priv->mii = NULL; 683 684 return 0; 685 } 686