1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 STMMAC Ethernet Driver -- MDIO bus implementation 4 Provides Bus interface for MII registers 5 6 Copyright (C) 2007-2009 STMicroelectronics Ltd 7 8 9 Author: Carl Shaw <carl.shaw@st.com> 10 Maintainer: Giuseppe Cavallaro <peppe.cavallaro@st.com> 11 *******************************************************************************/ 12 13 #include <linux/gpio/consumer.h> 14 #include <linux/io.h> 15 #include <linux/iopoll.h> 16 #include <linux/mii.h> 17 #include <linux/of_mdio.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/phy.h> 20 #include <linux/property.h> 21 #include <linux/slab.h> 22 23 #include "dwxgmac2.h" 24 #include "stmmac.h" 25 26 #define MII_BUSY 0x00000001 27 #define MII_WRITE 0x00000002 28 #define MII_DATA_MASK GENMASK(15, 0) 29 30 /* GMAC4 defines */ 31 #define MII_GMAC4_GOC_SHIFT 2 32 #define MII_GMAC4_REG_ADDR_SHIFT 16 33 #define MII_GMAC4_WRITE (1 << MII_GMAC4_GOC_SHIFT) 34 #define MII_GMAC4_READ (3 << MII_GMAC4_GOC_SHIFT) 35 #define MII_GMAC4_C45E BIT(1) 36 37 /* XGMAC defines */ 38 #define MII_XGMAC_SADDR BIT(18) 39 #define MII_XGMAC_CMD_SHIFT 16 40 #define MII_XGMAC_WRITE (1 << MII_XGMAC_CMD_SHIFT) 41 #define MII_XGMAC_READ (3 << MII_XGMAC_CMD_SHIFT) 42 #define MII_XGMAC_BUSY BIT(22) 43 #define MII_XGMAC_MAX_C22ADDR 3 44 #define MII_XGMAC_C22P_MASK GENMASK(MII_XGMAC_MAX_C22ADDR, 0) 45 #define MII_XGMAC_PA_SHIFT 16 46 #define MII_XGMAC_DA_SHIFT 21 47 48 static void stmmac_xgmac2_c45_format(struct stmmac_priv *priv, int phyaddr, 49 int devad, int phyreg, u32 *hw_addr) 50 { 51 u32 tmp; 52 53 /* Set port as Clause 45 */ 54 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); 55 tmp &= ~BIT(phyaddr); 56 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); 57 58 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0xffff); 59 *hw_addr |= devad << MII_XGMAC_DA_SHIFT; 60 } 61 62 static void stmmac_xgmac2_c22_format(struct stmmac_priv *priv, int phyaddr, 63 int phyreg, u32 *hw_addr) 64 { 65 u32 tmp = 0; 66 67 if (priv->synopsys_id < DWXGMAC_CORE_2_20) { 68 /* Until ver 2.20 XGMAC does not support C22 addr >= 4. Those 69 * bits above bit 3 of XGMAC_MDIO_C22P register are reserved. 70 */ 71 tmp = readl(priv->ioaddr + XGMAC_MDIO_C22P); 72 tmp &= ~MII_XGMAC_C22P_MASK; 73 } 74 /* Set port as Clause 22 */ 75 tmp |= BIT(phyaddr); 76 writel(tmp, priv->ioaddr + XGMAC_MDIO_C22P); 77 78 *hw_addr = (phyaddr << MII_XGMAC_PA_SHIFT) | (phyreg & 0x1f); 79 } 80 81 static int stmmac_xgmac2_mdio_read(struct stmmac_priv *priv, u32 addr, 82 u32 value) 83 { 84 unsigned int mii_address = priv->hw->mii.addr; 85 unsigned int mii_data = priv->hw->mii.data; 86 u32 tmp; 87 int ret; 88 89 ret = pm_runtime_resume_and_get(priv->device); 90 if (ret < 0) 91 return ret; 92 93 /* Wait until any existing MII operation is complete */ 94 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 95 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 96 ret = -EBUSY; 97 goto err_disable_clks; 98 } 99 100 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 101 & priv->hw->mii.clk_csr_mask; 102 value |= MII_XGMAC_READ; 103 104 /* Wait until any existing MII operation is complete */ 105 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 106 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 107 ret = -EBUSY; 108 goto err_disable_clks; 109 } 110 111 /* Set the MII address register to read */ 112 writel(addr, priv->ioaddr + mii_address); 113 writel(value, priv->ioaddr + mii_data); 114 115 /* Wait until any existing MII operation is complete */ 116 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 117 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 118 ret = -EBUSY; 119 goto err_disable_clks; 120 } 121 122 /* Read the data from the MII data register */ 123 ret = (int)readl(priv->ioaddr + mii_data) & GENMASK(15, 0); 124 125 err_disable_clks: 126 pm_runtime_put(priv->device); 127 128 return ret; 129 } 130 131 static int stmmac_xgmac2_mdio_read_c22(struct mii_bus *bus, int phyaddr, 132 int phyreg) 133 { 134 struct stmmac_priv *priv = netdev_priv(bus->priv); 135 u32 addr; 136 137 /* Until ver 2.20 XGMAC does not support C22 addr >= 4 */ 138 if (priv->synopsys_id < DWXGMAC_CORE_2_20 && 139 phyaddr > MII_XGMAC_MAX_C22ADDR) 140 return -ENODEV; 141 142 stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 143 144 return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY); 145 } 146 147 static int stmmac_xgmac2_mdio_read_c45(struct mii_bus *bus, int phyaddr, 148 int devad, int phyreg) 149 { 150 struct stmmac_priv *priv = netdev_priv(bus->priv); 151 u32 addr; 152 153 stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr); 154 155 return stmmac_xgmac2_mdio_read(priv, addr, MII_XGMAC_BUSY); 156 } 157 158 static int stmmac_xgmac2_mdio_write(struct stmmac_priv *priv, u32 addr, 159 u32 value, u16 phydata) 160 { 161 unsigned int mii_address = priv->hw->mii.addr; 162 unsigned int mii_data = priv->hw->mii.data; 163 u32 tmp; 164 int ret; 165 166 ret = pm_runtime_resume_and_get(priv->device); 167 if (ret < 0) 168 return ret; 169 170 /* Wait until any existing MII operation is complete */ 171 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 172 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 173 ret = -EBUSY; 174 goto err_disable_clks; 175 } 176 177 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 178 & priv->hw->mii.clk_csr_mask; 179 value |= phydata; 180 value |= MII_XGMAC_WRITE; 181 182 /* Wait until any existing MII operation is complete */ 183 if (readl_poll_timeout(priv->ioaddr + mii_data, tmp, 184 !(tmp & MII_XGMAC_BUSY), 100, 10000)) { 185 ret = -EBUSY; 186 goto err_disable_clks; 187 } 188 189 /* Set the MII address register to write */ 190 writel(addr, priv->ioaddr + mii_address); 191 writel(value, priv->ioaddr + mii_data); 192 193 /* Wait until any existing MII operation is complete */ 194 ret = readl_poll_timeout(priv->ioaddr + mii_data, tmp, 195 !(tmp & MII_XGMAC_BUSY), 100, 10000); 196 197 err_disable_clks: 198 pm_runtime_put(priv->device); 199 200 return ret; 201 } 202 203 static int stmmac_xgmac2_mdio_write_c22(struct mii_bus *bus, int phyaddr, 204 int phyreg, u16 phydata) 205 { 206 struct stmmac_priv *priv = netdev_priv(bus->priv); 207 u32 addr; 208 209 /* Until ver 2.20 XGMAC does not support C22 addr >= 4 */ 210 if (priv->synopsys_id < DWXGMAC_CORE_2_20 && 211 phyaddr > MII_XGMAC_MAX_C22ADDR) 212 return -ENODEV; 213 214 stmmac_xgmac2_c22_format(priv, phyaddr, phyreg, &addr); 215 216 return stmmac_xgmac2_mdio_write(priv, addr, 217 MII_XGMAC_BUSY | MII_XGMAC_SADDR, phydata); 218 } 219 220 static int stmmac_xgmac2_mdio_write_c45(struct mii_bus *bus, int phyaddr, 221 int devad, int phyreg, u16 phydata) 222 { 223 struct stmmac_priv *priv = netdev_priv(bus->priv); 224 u32 addr; 225 226 stmmac_xgmac2_c45_format(priv, phyaddr, devad, phyreg, &addr); 227 228 return stmmac_xgmac2_mdio_write(priv, addr, MII_XGMAC_BUSY, 229 phydata); 230 } 231 232 static int stmmac_mdio_read(struct stmmac_priv *priv, int data, u32 value) 233 { 234 unsigned int mii_address = priv->hw->mii.addr; 235 unsigned int mii_data = priv->hw->mii.data; 236 u32 v; 237 238 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 239 100, 10000)) 240 return -EBUSY; 241 242 writel(data, priv->ioaddr + mii_data); 243 writel(value, priv->ioaddr + mii_address); 244 245 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 246 100, 10000)) 247 return -EBUSY; 248 249 /* Read the data from the MII data register */ 250 return readl(priv->ioaddr + mii_data) & MII_DATA_MASK; 251 } 252 253 /** 254 * stmmac_mdio_read_c22 255 * @bus: points to the mii_bus structure 256 * @phyaddr: MII addr 257 * @phyreg: MII reg 258 * Description: it reads data from the MII register from within the phy device. 259 * For the 7111 GMAC, we must set the bit 0 in the MII address register while 260 * accessing the PHY registers. 261 * Fortunately, it seems this has no drawback for the 7109 MAC. 262 */ 263 static int stmmac_mdio_read_c22(struct mii_bus *bus, int phyaddr, int phyreg) 264 { 265 struct stmmac_priv *priv = netdev_priv(bus->priv); 266 u32 value = MII_BUSY; 267 int data = 0; 268 269 data = pm_runtime_resume_and_get(priv->device); 270 if (data < 0) 271 return data; 272 273 value |= (phyaddr << priv->hw->mii.addr_shift) 274 & priv->hw->mii.addr_mask; 275 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 276 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 277 & priv->hw->mii.clk_csr_mask; 278 if (priv->plat->has_gmac4) 279 value |= MII_GMAC4_READ; 280 281 data = stmmac_mdio_read(priv, data, value); 282 283 pm_runtime_put(priv->device); 284 285 return data; 286 } 287 288 /** 289 * stmmac_mdio_read_c45 290 * @bus: points to the mii_bus structure 291 * @phyaddr: MII addr 292 * @devad: device address to read 293 * @phyreg: MII reg 294 * Description: it reads data from the MII register from within the phy device. 295 * For the 7111 GMAC, we must set the bit 0 in the MII address register while 296 * accessing the PHY registers. 297 * Fortunately, it seems this has no drawback for the 7109 MAC. 298 */ 299 static int stmmac_mdio_read_c45(struct mii_bus *bus, int phyaddr, int devad, 300 int phyreg) 301 { 302 struct stmmac_priv *priv = netdev_priv(bus->priv); 303 u32 value = MII_BUSY; 304 int data = 0; 305 306 data = pm_runtime_get_sync(priv->device); 307 if (data < 0) { 308 pm_runtime_put_noidle(priv->device); 309 return data; 310 } 311 312 value |= (phyaddr << priv->hw->mii.addr_shift) 313 & priv->hw->mii.addr_mask; 314 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 315 & priv->hw->mii.clk_csr_mask; 316 value |= MII_GMAC4_READ; 317 value |= MII_GMAC4_C45E; 318 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 319 320 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; 321 322 data = stmmac_mdio_read(priv, data, value); 323 324 pm_runtime_put(priv->device); 325 326 return data; 327 } 328 329 static int stmmac_mdio_write(struct stmmac_priv *priv, int data, u32 value) 330 { 331 unsigned int mii_address = priv->hw->mii.addr; 332 unsigned int mii_data = priv->hw->mii.data; 333 u32 v; 334 335 /* Wait until any existing MII operation is complete */ 336 if (readl_poll_timeout(priv->ioaddr + mii_address, v, !(v & MII_BUSY), 337 100, 10000)) 338 return -EBUSY; 339 340 /* Set the MII address register to write */ 341 writel(data, priv->ioaddr + mii_data); 342 writel(value, priv->ioaddr + mii_address); 343 344 /* Wait until any existing MII operation is complete */ 345 return readl_poll_timeout(priv->ioaddr + mii_address, v, 346 !(v & MII_BUSY), 100, 10000); 347 } 348 349 /** 350 * stmmac_mdio_write_c22 351 * @bus: points to the mii_bus structure 352 * @phyaddr: MII addr 353 * @phyreg: MII reg 354 * @phydata: phy data 355 * Description: it writes the data into the MII register from within the device. 356 */ 357 static int stmmac_mdio_write_c22(struct mii_bus *bus, int phyaddr, int phyreg, 358 u16 phydata) 359 { 360 struct stmmac_priv *priv = netdev_priv(bus->priv); 361 int ret, data = phydata; 362 u32 value = MII_BUSY; 363 364 ret = pm_runtime_resume_and_get(priv->device); 365 if (ret < 0) 366 return ret; 367 368 value |= (phyaddr << priv->hw->mii.addr_shift) 369 & priv->hw->mii.addr_mask; 370 value |= (phyreg << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 371 372 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 373 & priv->hw->mii.clk_csr_mask; 374 if (priv->plat->has_gmac4) 375 value |= MII_GMAC4_WRITE; 376 else 377 value |= MII_WRITE; 378 379 ret = stmmac_mdio_write(priv, data, value); 380 381 pm_runtime_put(priv->device); 382 383 return ret; 384 } 385 386 /** 387 * stmmac_mdio_write_c45 388 * @bus: points to the mii_bus structure 389 * @phyaddr: MII addr 390 * @phyreg: MII reg 391 * @devad: device address to read 392 * @phydata: phy data 393 * Description: it writes the data into the MII register from within the device. 394 */ 395 static int stmmac_mdio_write_c45(struct mii_bus *bus, int phyaddr, 396 int devad, int phyreg, u16 phydata) 397 { 398 struct stmmac_priv *priv = netdev_priv(bus->priv); 399 int ret, data = phydata; 400 u32 value = MII_BUSY; 401 402 ret = pm_runtime_get_sync(priv->device); 403 if (ret < 0) { 404 pm_runtime_put_noidle(priv->device); 405 return ret; 406 } 407 408 value |= (phyaddr << priv->hw->mii.addr_shift) 409 & priv->hw->mii.addr_mask; 410 411 value |= (priv->clk_csr << priv->hw->mii.clk_csr_shift) 412 & priv->hw->mii.clk_csr_mask; 413 414 value |= MII_GMAC4_WRITE; 415 value |= MII_GMAC4_C45E; 416 value |= (devad << priv->hw->mii.reg_shift) & priv->hw->mii.reg_mask; 417 418 data |= phyreg << MII_GMAC4_REG_ADDR_SHIFT; 419 420 ret = stmmac_mdio_write(priv, data, value); 421 422 pm_runtime_put(priv->device); 423 424 return ret; 425 } 426 427 /** 428 * stmmac_mdio_reset 429 * @bus: points to the mii_bus structure 430 * Description: reset the MII bus 431 */ 432 int stmmac_mdio_reset(struct mii_bus *bus) 433 { 434 #if IS_ENABLED(CONFIG_STMMAC_PLATFORM) 435 struct stmmac_priv *priv = netdev_priv(bus->priv); 436 unsigned int mii_address = priv->hw->mii.addr; 437 438 #ifdef CONFIG_OF 439 if (priv->device->of_node) { 440 struct gpio_desc *reset_gpio; 441 u32 delays[3] = { 0, 0, 0 }; 442 443 reset_gpio = devm_gpiod_get_optional(priv->device, 444 "snps,reset", 445 GPIOD_OUT_LOW); 446 if (IS_ERR(reset_gpio)) 447 return PTR_ERR(reset_gpio); 448 449 device_property_read_u32_array(priv->device, 450 "snps,reset-delays-us", 451 delays, ARRAY_SIZE(delays)); 452 453 if (delays[0]) 454 msleep(DIV_ROUND_UP(delays[0], 1000)); 455 456 gpiod_set_value_cansleep(reset_gpio, 1); 457 if (delays[1]) 458 msleep(DIV_ROUND_UP(delays[1], 1000)); 459 460 gpiod_set_value_cansleep(reset_gpio, 0); 461 if (delays[2]) 462 msleep(DIV_ROUND_UP(delays[2], 1000)); 463 } 464 #endif 465 466 /* This is a workaround for problems with the STE101P PHY. 467 * It doesn't complete its reset until at least one clock cycle 468 * on MDC, so perform a dummy mdio read. To be updated for GMAC4 469 * if needed. 470 */ 471 if (!priv->plat->has_gmac4) 472 writel(0, priv->ioaddr + mii_address); 473 #endif 474 return 0; 475 } 476 477 int stmmac_pcs_setup(struct net_device *ndev) 478 { 479 struct stmmac_priv *priv = netdev_priv(ndev); 480 struct fwnode_handle *devnode, *pcsnode; 481 struct dw_xpcs *xpcs = NULL; 482 int addr, ret; 483 484 devnode = priv->plat->port_node; 485 486 if (priv->plat->pcs_init) { 487 ret = priv->plat->pcs_init(priv); 488 } else if (fwnode_property_present(devnode, "pcs-handle")) { 489 pcsnode = fwnode_find_reference(devnode, "pcs-handle", 0); 490 xpcs = xpcs_create_fwnode(pcsnode); 491 fwnode_handle_put(pcsnode); 492 ret = PTR_ERR_OR_ZERO(xpcs); 493 } else if (priv->plat->mdio_bus_data && 494 priv->plat->mdio_bus_data->pcs_mask) { 495 addr = ffs(priv->plat->mdio_bus_data->pcs_mask) - 1; 496 xpcs = xpcs_create_mdiodev(priv->mii, addr); 497 ret = PTR_ERR_OR_ZERO(xpcs); 498 } else { 499 return 0; 500 } 501 502 if (ret) 503 return dev_err_probe(priv->device, ret, "No xPCS found\n"); 504 505 if (xpcs) 506 xpcs_config_eee_mult_fact(xpcs, priv->plat->mult_fact_100ns); 507 508 priv->hw->xpcs = xpcs; 509 510 return 0; 511 } 512 513 void stmmac_pcs_clean(struct net_device *ndev) 514 { 515 struct stmmac_priv *priv = netdev_priv(ndev); 516 517 if (priv->plat->pcs_exit) 518 priv->plat->pcs_exit(priv); 519 520 if (!priv->hw->xpcs) 521 return; 522 523 xpcs_destroy(priv->hw->xpcs); 524 priv->hw->xpcs = NULL; 525 } 526 527 /** 528 * stmmac_mdio_register 529 * @ndev: net device structure 530 * Description: it registers the MII bus 531 */ 532 int stmmac_mdio_register(struct net_device *ndev) 533 { 534 int err = 0; 535 struct mii_bus *new_bus; 536 struct stmmac_priv *priv = netdev_priv(ndev); 537 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 538 struct device_node *mdio_node = priv->plat->mdio_node; 539 struct device *dev = ndev->dev.parent; 540 struct fwnode_handle *fixed_node; 541 struct fwnode_handle *fwnode; 542 int addr, found, max_addr; 543 544 if (!mdio_bus_data) 545 return 0; 546 547 new_bus = mdiobus_alloc(); 548 if (!new_bus) 549 return -ENOMEM; 550 551 if (mdio_bus_data->irqs) 552 memcpy(new_bus->irq, mdio_bus_data->irqs, sizeof(new_bus->irq)); 553 554 new_bus->name = "stmmac"; 555 556 if (priv->plat->has_xgmac) { 557 new_bus->read = &stmmac_xgmac2_mdio_read_c22; 558 new_bus->write = &stmmac_xgmac2_mdio_write_c22; 559 new_bus->read_c45 = &stmmac_xgmac2_mdio_read_c45; 560 new_bus->write_c45 = &stmmac_xgmac2_mdio_write_c45; 561 562 if (priv->synopsys_id < DWXGMAC_CORE_2_20) { 563 /* Right now only C22 phys are supported */ 564 max_addr = MII_XGMAC_MAX_C22ADDR + 1; 565 566 /* Check if DT specified an unsupported phy addr */ 567 if (priv->plat->phy_addr > MII_XGMAC_MAX_C22ADDR) 568 dev_err(dev, "Unsupported phy_addr (max=%d)\n", 569 MII_XGMAC_MAX_C22ADDR); 570 } else { 571 /* XGMAC version 2.20 onwards support 32 phy addr */ 572 max_addr = PHY_MAX_ADDR; 573 } 574 } else { 575 new_bus->read = &stmmac_mdio_read_c22; 576 new_bus->write = &stmmac_mdio_write_c22; 577 if (priv->plat->has_gmac4) { 578 new_bus->read_c45 = &stmmac_mdio_read_c45; 579 new_bus->write_c45 = &stmmac_mdio_write_c45; 580 } 581 582 max_addr = PHY_MAX_ADDR; 583 } 584 585 if (mdio_bus_data->needs_reset) 586 new_bus->reset = &stmmac_mdio_reset; 587 588 snprintf(new_bus->id, MII_BUS_ID_SIZE, "%s-%x", 589 new_bus->name, priv->plat->bus_id); 590 new_bus->priv = ndev; 591 new_bus->phy_mask = mdio_bus_data->phy_mask | mdio_bus_data->pcs_mask; 592 new_bus->parent = priv->device; 593 594 err = of_mdiobus_register(new_bus, mdio_node); 595 if (err == -ENODEV) { 596 err = 0; 597 dev_info(dev, "MDIO bus is disabled\n"); 598 goto bus_register_fail; 599 } else if (err) { 600 dev_err_probe(dev, err, "Cannot register the MDIO bus\n"); 601 goto bus_register_fail; 602 } 603 604 /* Looks like we need a dummy read for XGMAC only and C45 PHYs */ 605 if (priv->plat->has_xgmac) 606 stmmac_xgmac2_mdio_read_c45(new_bus, 0, 0, 0); 607 608 /* If fixed-link is set, skip PHY scanning */ 609 fwnode = priv->plat->port_node; 610 if (!fwnode) 611 fwnode = dev_fwnode(priv->device); 612 613 if (fwnode) { 614 fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link"); 615 if (fixed_node) { 616 fwnode_handle_put(fixed_node); 617 goto bus_register_done; 618 } 619 } 620 621 if (priv->plat->phy_node || mdio_node) 622 goto bus_register_done; 623 624 found = 0; 625 for (addr = 0; addr < max_addr; addr++) { 626 struct phy_device *phydev = mdiobus_get_phy(new_bus, addr); 627 628 if (!phydev) 629 continue; 630 631 /* 632 * If an IRQ was provided to be assigned after 633 * the bus probe, do it here. 634 */ 635 if (!mdio_bus_data->irqs && 636 (mdio_bus_data->probed_phy_irq > 0)) { 637 new_bus->irq[addr] = mdio_bus_data->probed_phy_irq; 638 phydev->irq = mdio_bus_data->probed_phy_irq; 639 } 640 641 /* 642 * If we're going to bind the MAC to this PHY bus, 643 * and no PHY number was provided to the MAC, 644 * use the one probed here. 645 */ 646 if (priv->plat->phy_addr == -1) 647 priv->plat->phy_addr = addr; 648 649 phy_attached_info(phydev); 650 found = 1; 651 } 652 653 if (!found && !mdio_node) { 654 dev_warn(dev, "No PHY found\n"); 655 err = -ENODEV; 656 goto no_phy_found; 657 } 658 659 bus_register_done: 660 priv->mii = new_bus; 661 662 return 0; 663 664 no_phy_found: 665 mdiobus_unregister(new_bus); 666 bus_register_fail: 667 mdiobus_free(new_bus); 668 return err; 669 } 670 671 /** 672 * stmmac_mdio_unregister 673 * @ndev: net device structure 674 * Description: it unregisters the MII bus 675 */ 676 int stmmac_mdio_unregister(struct net_device *ndev) 677 { 678 struct stmmac_priv *priv = netdev_priv(ndev); 679 680 if (!priv->mii) 681 return 0; 682 683 mdiobus_unregister(priv->mii); 684 priv->mii->priv = NULL; 685 mdiobus_free(priv->mii); 686 priv->mii = NULL; 687 688 return 0; 689 } 690