1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 /* As long as the interface is active, we keep the timestamping counter enabled 54 * with fine resolution and binary rollover. This avoid non-monotonic behavior 55 * (clock jumps) when changing timestamping settings at runtime. 56 */ 57 #define STMMAC_HWTS_ACTIVE (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | \ 58 PTP_TCR_TSCTRLSSR) 59 60 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 61 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 62 63 /* Module parameters */ 64 #define TX_TIMEO 5000 65 static int watchdog = TX_TIMEO; 66 module_param(watchdog, int, 0644); 67 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 68 69 static int debug = -1; 70 module_param(debug, int, 0644); 71 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 72 73 static int phyaddr = -1; 74 module_param(phyaddr, int, 0444); 75 MODULE_PARM_DESC(phyaddr, "Physical device address"); 76 77 #define STMMAC_TX_THRESH(x) ((x)->dma_conf.dma_tx_size / 4) 78 #define STMMAC_RX_THRESH(x) ((x)->dma_conf.dma_rx_size / 4) 79 80 /* Limit to make sure XDP TX and slow path can coexist */ 81 #define STMMAC_XSK_TX_BUDGET_MAX 256 82 #define STMMAC_TX_XSK_AVAIL 16 83 #define STMMAC_RX_FILL_BATCH 16 84 85 #define STMMAC_XDP_PASS 0 86 #define STMMAC_XDP_CONSUMED BIT(0) 87 #define STMMAC_XDP_TX BIT(1) 88 #define STMMAC_XDP_REDIRECT BIT(2) 89 90 static int flow_ctrl = FLOW_AUTO; 91 module_param(flow_ctrl, int, 0644); 92 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 93 94 static int pause = PAUSE_TIME; 95 module_param(pause, int, 0644); 96 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 97 98 #define TC_DEFAULT 64 99 static int tc = TC_DEFAULT; 100 module_param(tc, int, 0644); 101 MODULE_PARM_DESC(tc, "DMA threshold control value"); 102 103 #define DEFAULT_BUFSIZE 1536 104 static int buf_sz = DEFAULT_BUFSIZE; 105 module_param(buf_sz, int, 0644); 106 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 107 108 #define STMMAC_RX_COPYBREAK 256 109 110 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 111 NETIF_MSG_LINK | NETIF_MSG_IFUP | 112 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 113 114 #define STMMAC_DEFAULT_LPI_TIMER 1000 115 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 116 module_param(eee_timer, int, 0644); 117 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 118 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 119 120 /* By default the driver will use the ring mode to manage tx and rx descriptors, 121 * but allow user to force to use the chain instead of the ring 122 */ 123 static unsigned int chain_mode; 124 module_param(chain_mode, int, 0444); 125 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 126 127 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 128 /* For MSI interrupts handling */ 129 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 130 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 131 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 132 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 133 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue); 134 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue); 135 static void stmmac_reset_queues_param(struct stmmac_priv *priv); 136 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 137 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 138 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 139 u32 rxmode, u32 chan); 140 141 #ifdef CONFIG_DEBUG_FS 142 static const struct net_device_ops stmmac_netdev_ops; 143 static void stmmac_init_fs(struct net_device *dev); 144 static void stmmac_exit_fs(struct net_device *dev); 145 #endif 146 147 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 148 149 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 150 { 151 int ret = 0; 152 153 if (enabled) { 154 ret = clk_prepare_enable(priv->plat->stmmac_clk); 155 if (ret) 156 return ret; 157 ret = clk_prepare_enable(priv->plat->pclk); 158 if (ret) { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 return ret; 161 } 162 if (priv->plat->clks_config) { 163 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 164 if (ret) { 165 clk_disable_unprepare(priv->plat->stmmac_clk); 166 clk_disable_unprepare(priv->plat->pclk); 167 return ret; 168 } 169 } 170 } else { 171 clk_disable_unprepare(priv->plat->stmmac_clk); 172 clk_disable_unprepare(priv->plat->pclk); 173 if (priv->plat->clks_config) 174 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 175 } 176 177 return ret; 178 } 179 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 180 181 /** 182 * stmmac_verify_args - verify the driver parameters. 183 * Description: it checks the driver parameters and set a default in case of 184 * errors. 185 */ 186 static void stmmac_verify_args(void) 187 { 188 if (unlikely(watchdog < 0)) 189 watchdog = TX_TIMEO; 190 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 191 buf_sz = DEFAULT_BUFSIZE; 192 if (unlikely(flow_ctrl > 1)) 193 flow_ctrl = FLOW_AUTO; 194 else if (likely(flow_ctrl < 0)) 195 flow_ctrl = FLOW_OFF; 196 if (unlikely((pause < 0) || (pause > 0xffff))) 197 pause = PAUSE_TIME; 198 if (eee_timer < 0) 199 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 200 } 201 202 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 203 { 204 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 205 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 206 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 207 u32 queue; 208 209 for (queue = 0; queue < maxq; queue++) { 210 struct stmmac_channel *ch = &priv->channel[queue]; 211 212 if (stmmac_xdp_is_enabled(priv) && 213 test_bit(queue, priv->af_xdp_zc_qps)) { 214 napi_disable(&ch->rxtx_napi); 215 continue; 216 } 217 218 if (queue < rx_queues_cnt) 219 napi_disable(&ch->rx_napi); 220 if (queue < tx_queues_cnt) 221 napi_disable(&ch->tx_napi); 222 } 223 } 224 225 /** 226 * stmmac_disable_all_queues - Disable all queues 227 * @priv: driver private structure 228 */ 229 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 230 { 231 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 232 struct stmmac_rx_queue *rx_q; 233 u32 queue; 234 235 /* synchronize_rcu() needed for pending XDP buffers to drain */ 236 for (queue = 0; queue < rx_queues_cnt; queue++) { 237 rx_q = &priv->dma_conf.rx_queue[queue]; 238 if (rx_q->xsk_pool) { 239 synchronize_rcu(); 240 break; 241 } 242 } 243 244 __stmmac_disable_all_queues(priv); 245 } 246 247 /** 248 * stmmac_enable_all_queues - Enable all queues 249 * @priv: driver private structure 250 */ 251 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 252 { 253 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 254 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 255 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 256 u32 queue; 257 258 for (queue = 0; queue < maxq; queue++) { 259 struct stmmac_channel *ch = &priv->channel[queue]; 260 261 if (stmmac_xdp_is_enabled(priv) && 262 test_bit(queue, priv->af_xdp_zc_qps)) { 263 napi_enable(&ch->rxtx_napi); 264 continue; 265 } 266 267 if (queue < rx_queues_cnt) 268 napi_enable(&ch->rx_napi); 269 if (queue < tx_queues_cnt) 270 napi_enable(&ch->tx_napi); 271 } 272 } 273 274 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 275 { 276 if (!test_bit(STMMAC_DOWN, &priv->state) && 277 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 278 queue_work(priv->wq, &priv->service_task); 279 } 280 281 static void stmmac_global_err(struct stmmac_priv *priv) 282 { 283 netif_carrier_off(priv->dev); 284 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 285 stmmac_service_event_schedule(priv); 286 } 287 288 /** 289 * stmmac_clk_csr_set - dynamically set the MDC clock 290 * @priv: driver private structure 291 * Description: this is to dynamically set the MDC clock according to the csr 292 * clock input. 293 * Note: 294 * If a specific clk_csr value is passed from the platform 295 * this means that the CSR Clock Range selection cannot be 296 * changed at run-time and it is fixed (as reported in the driver 297 * documentation). Viceversa the driver will try to set the MDC 298 * clock dynamically according to the actual clock input. 299 */ 300 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 301 { 302 u32 clk_rate; 303 304 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 305 306 /* Platform provided default clk_csr would be assumed valid 307 * for all other cases except for the below mentioned ones. 308 * For values higher than the IEEE 802.3 specified frequency 309 * we can not estimate the proper divider as it is not known 310 * the frequency of clk_csr_i. So we do not change the default 311 * divider. 312 */ 313 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 314 if (clk_rate < CSR_F_35M) 315 priv->clk_csr = STMMAC_CSR_20_35M; 316 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 317 priv->clk_csr = STMMAC_CSR_35_60M; 318 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 319 priv->clk_csr = STMMAC_CSR_60_100M; 320 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 321 priv->clk_csr = STMMAC_CSR_100_150M; 322 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 323 priv->clk_csr = STMMAC_CSR_150_250M; 324 else if ((clk_rate >= CSR_F_250M) && (clk_rate <= CSR_F_300M)) 325 priv->clk_csr = STMMAC_CSR_250_300M; 326 } 327 328 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) { 329 if (clk_rate > 160000000) 330 priv->clk_csr = 0x03; 331 else if (clk_rate > 80000000) 332 priv->clk_csr = 0x02; 333 else if (clk_rate > 40000000) 334 priv->clk_csr = 0x01; 335 else 336 priv->clk_csr = 0; 337 } 338 339 if (priv->plat->has_xgmac) { 340 if (clk_rate > 400000000) 341 priv->clk_csr = 0x5; 342 else if (clk_rate > 350000000) 343 priv->clk_csr = 0x4; 344 else if (clk_rate > 300000000) 345 priv->clk_csr = 0x3; 346 else if (clk_rate > 250000000) 347 priv->clk_csr = 0x2; 348 else if (clk_rate > 150000000) 349 priv->clk_csr = 0x1; 350 else 351 priv->clk_csr = 0x0; 352 } 353 } 354 355 static void print_pkt(unsigned char *buf, int len) 356 { 357 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 358 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 359 } 360 361 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 362 { 363 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 364 u32 avail; 365 366 if (tx_q->dirty_tx > tx_q->cur_tx) 367 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 368 else 369 avail = priv->dma_conf.dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 370 371 return avail; 372 } 373 374 /** 375 * stmmac_rx_dirty - Get RX queue dirty 376 * @priv: driver private structure 377 * @queue: RX queue index 378 */ 379 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 380 { 381 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 382 u32 dirty; 383 384 if (rx_q->dirty_rx <= rx_q->cur_rx) 385 dirty = rx_q->cur_rx - rx_q->dirty_rx; 386 else 387 dirty = priv->dma_conf.dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 388 389 return dirty; 390 } 391 392 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 393 { 394 int tx_lpi_timer; 395 396 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 397 priv->eee_sw_timer_en = en ? 0 : 1; 398 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 399 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 400 } 401 402 /** 403 * stmmac_enable_eee_mode - check and enter in LPI mode 404 * @priv: driver private structure 405 * Description: this function is to verify and enter in LPI mode in case of 406 * EEE. 407 */ 408 static int stmmac_enable_eee_mode(struct stmmac_priv *priv) 409 { 410 u32 tx_cnt = priv->plat->tx_queues_to_use; 411 u32 queue; 412 413 /* check if all TX queues have the work finished */ 414 for (queue = 0; queue < tx_cnt; queue++) { 415 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 416 417 if (tx_q->dirty_tx != tx_q->cur_tx) 418 return -EBUSY; /* still unfinished work */ 419 } 420 421 /* Check and enter in LPI mode */ 422 if (!priv->tx_path_in_lpi_mode) 423 stmmac_set_eee_mode(priv, priv->hw, 424 priv->plat->flags & STMMAC_FLAG_EN_TX_LPI_CLOCKGATING); 425 return 0; 426 } 427 428 /** 429 * stmmac_disable_eee_mode - disable and exit from LPI mode 430 * @priv: driver private structure 431 * Description: this function is to exit and disable EEE in case of 432 * LPI state is true. This is called by the xmit. 433 */ 434 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 435 { 436 if (!priv->eee_sw_timer_en) { 437 stmmac_lpi_entry_timer_config(priv, 0); 438 return; 439 } 440 441 stmmac_reset_eee_mode(priv, priv->hw); 442 del_timer_sync(&priv->eee_ctrl_timer); 443 priv->tx_path_in_lpi_mode = false; 444 } 445 446 /** 447 * stmmac_eee_ctrl_timer - EEE TX SW timer. 448 * @t: timer_list struct containing private info 449 * Description: 450 * if there is no data transfer and if we are not in LPI state, 451 * then MAC Transmitter can be moved to LPI state. 452 */ 453 static void stmmac_eee_ctrl_timer(struct timer_list *t) 454 { 455 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 456 457 if (stmmac_enable_eee_mode(priv)) 458 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 459 } 460 461 /** 462 * stmmac_eee_init - init EEE 463 * @priv: driver private structure 464 * Description: 465 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 466 * can also manage EEE, this function enable the LPI state and start related 467 * timer. 468 */ 469 bool stmmac_eee_init(struct stmmac_priv *priv) 470 { 471 int eee_tw_timer = priv->eee_tw_timer; 472 473 /* Using PCS we cannot dial with the phy registers at this stage 474 * so we do not support extra feature like EEE. 475 */ 476 if (priv->hw->pcs == STMMAC_PCS_TBI || 477 priv->hw->pcs == STMMAC_PCS_RTBI) 478 return false; 479 480 /* Check if MAC core supports the EEE feature. */ 481 if (!priv->dma_cap.eee) 482 return false; 483 484 mutex_lock(&priv->lock); 485 486 /* Check if it needs to be deactivated */ 487 if (!priv->eee_active) { 488 if (priv->eee_enabled) { 489 netdev_dbg(priv->dev, "disable EEE\n"); 490 stmmac_lpi_entry_timer_config(priv, 0); 491 del_timer_sync(&priv->eee_ctrl_timer); 492 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 493 if (priv->hw->xpcs) 494 xpcs_config_eee(priv->hw->xpcs, 495 priv->plat->mult_fact_100ns, 496 false); 497 } 498 mutex_unlock(&priv->lock); 499 return false; 500 } 501 502 if (priv->eee_active && !priv->eee_enabled) { 503 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 504 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 505 eee_tw_timer); 506 if (priv->hw->xpcs) 507 xpcs_config_eee(priv->hw->xpcs, 508 priv->plat->mult_fact_100ns, 509 true); 510 } 511 512 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 513 del_timer_sync(&priv->eee_ctrl_timer); 514 priv->tx_path_in_lpi_mode = false; 515 stmmac_lpi_entry_timer_config(priv, 1); 516 } else { 517 stmmac_lpi_entry_timer_config(priv, 0); 518 mod_timer(&priv->eee_ctrl_timer, 519 STMMAC_LPI_T(priv->tx_lpi_timer)); 520 } 521 522 mutex_unlock(&priv->lock); 523 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 524 return true; 525 } 526 527 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 528 * @priv: driver private structure 529 * @p : descriptor pointer 530 * @skb : the socket buffer 531 * Description : 532 * This function will read timestamp from the descriptor & pass it to stack. 533 * and also perform some sanity checks. 534 */ 535 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 536 struct dma_desc *p, struct sk_buff *skb) 537 { 538 struct skb_shared_hwtstamps shhwtstamp; 539 bool found = false; 540 u64 ns = 0; 541 542 if (!priv->hwts_tx_en) 543 return; 544 545 /* exit if skb doesn't support hw tstamp */ 546 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 547 return; 548 549 /* check tx tstamp status */ 550 if (stmmac_get_tx_timestamp_status(priv, p)) { 551 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 552 found = true; 553 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 554 found = true; 555 } 556 557 if (found) { 558 ns -= priv->plat->cdc_error_adj; 559 560 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 561 shhwtstamp.hwtstamp = ns_to_ktime(ns); 562 563 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 564 /* pass tstamp to stack */ 565 skb_tstamp_tx(skb, &shhwtstamp); 566 } 567 } 568 569 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 570 * @priv: driver private structure 571 * @p : descriptor pointer 572 * @np : next descriptor pointer 573 * @skb : the socket buffer 574 * Description : 575 * This function will read received packet's timestamp from the descriptor 576 * and pass it to stack. It also perform some sanity checks. 577 */ 578 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 579 struct dma_desc *np, struct sk_buff *skb) 580 { 581 struct skb_shared_hwtstamps *shhwtstamp = NULL; 582 struct dma_desc *desc = p; 583 u64 ns = 0; 584 585 if (!priv->hwts_rx_en) 586 return; 587 /* For GMAC4, the valid timestamp is from CTX next desc. */ 588 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 589 desc = np; 590 591 /* Check if timestamp is available */ 592 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 593 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 594 595 ns -= priv->plat->cdc_error_adj; 596 597 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 598 shhwtstamp = skb_hwtstamps(skb); 599 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 600 shhwtstamp->hwtstamp = ns_to_ktime(ns); 601 } else { 602 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 603 } 604 } 605 606 /** 607 * stmmac_hwtstamp_set - control hardware timestamping. 608 * @dev: device pointer. 609 * @ifr: An IOCTL specific structure, that can contain a pointer to 610 * a proprietary structure used to pass information to the driver. 611 * Description: 612 * This function configures the MAC to enable/disable both outgoing(TX) 613 * and incoming(RX) packets time stamping based on user input. 614 * Return Value: 615 * 0 on success and an appropriate -ve integer on failure. 616 */ 617 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 618 { 619 struct stmmac_priv *priv = netdev_priv(dev); 620 struct hwtstamp_config config; 621 u32 ptp_v2 = 0; 622 u32 tstamp_all = 0; 623 u32 ptp_over_ipv4_udp = 0; 624 u32 ptp_over_ipv6_udp = 0; 625 u32 ptp_over_ethernet = 0; 626 u32 snap_type_sel = 0; 627 u32 ts_master_en = 0; 628 u32 ts_event_en = 0; 629 630 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 631 netdev_alert(priv->dev, "No support for HW time stamping\n"); 632 priv->hwts_tx_en = 0; 633 priv->hwts_rx_en = 0; 634 635 return -EOPNOTSUPP; 636 } 637 638 if (copy_from_user(&config, ifr->ifr_data, 639 sizeof(config))) 640 return -EFAULT; 641 642 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 643 __func__, config.flags, config.tx_type, config.rx_filter); 644 645 if (config.tx_type != HWTSTAMP_TX_OFF && 646 config.tx_type != HWTSTAMP_TX_ON) 647 return -ERANGE; 648 649 if (priv->adv_ts) { 650 switch (config.rx_filter) { 651 case HWTSTAMP_FILTER_NONE: 652 /* time stamp no incoming packet at all */ 653 config.rx_filter = HWTSTAMP_FILTER_NONE; 654 break; 655 656 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 657 /* PTP v1, UDP, any kind of event packet */ 658 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 659 /* 'xmac' hardware can support Sync, Pdelay_Req and 660 * Pdelay_resp by setting bit14 and bits17/16 to 01 661 * This leaves Delay_Req timestamps out. 662 * Enable all events *and* general purpose message 663 * timestamping 664 */ 665 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 666 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 667 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 668 break; 669 670 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 671 /* PTP v1, UDP, Sync packet */ 672 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 673 /* take time stamp for SYNC messages only */ 674 ts_event_en = PTP_TCR_TSEVNTENA; 675 676 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 677 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 678 break; 679 680 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 681 /* PTP v1, UDP, Delay_req packet */ 682 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 683 /* take time stamp for Delay_Req messages only */ 684 ts_master_en = PTP_TCR_TSMSTRENA; 685 ts_event_en = PTP_TCR_TSEVNTENA; 686 687 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 688 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 689 break; 690 691 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 692 /* PTP v2, UDP, any kind of event packet */ 693 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 694 ptp_v2 = PTP_TCR_TSVER2ENA; 695 /* take time stamp for all event messages */ 696 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 697 698 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 699 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 700 break; 701 702 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 703 /* PTP v2, UDP, Sync packet */ 704 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 705 ptp_v2 = PTP_TCR_TSVER2ENA; 706 /* take time stamp for SYNC messages only */ 707 ts_event_en = PTP_TCR_TSEVNTENA; 708 709 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 710 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 711 break; 712 713 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 714 /* PTP v2, UDP, Delay_req packet */ 715 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 716 ptp_v2 = PTP_TCR_TSVER2ENA; 717 /* take time stamp for Delay_Req messages only */ 718 ts_master_en = PTP_TCR_TSMSTRENA; 719 ts_event_en = PTP_TCR_TSEVNTENA; 720 721 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 722 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 723 break; 724 725 case HWTSTAMP_FILTER_PTP_V2_EVENT: 726 /* PTP v2/802.AS1 any layer, any kind of event packet */ 727 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 728 ptp_v2 = PTP_TCR_TSVER2ENA; 729 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 730 if (priv->synopsys_id < DWMAC_CORE_4_10) 731 ts_event_en = PTP_TCR_TSEVNTENA; 732 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 733 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 734 ptp_over_ethernet = PTP_TCR_TSIPENA; 735 break; 736 737 case HWTSTAMP_FILTER_PTP_V2_SYNC: 738 /* PTP v2/802.AS1, any layer, Sync packet */ 739 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 740 ptp_v2 = PTP_TCR_TSVER2ENA; 741 /* take time stamp for SYNC messages only */ 742 ts_event_en = PTP_TCR_TSEVNTENA; 743 744 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 745 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 746 ptp_over_ethernet = PTP_TCR_TSIPENA; 747 break; 748 749 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 750 /* PTP v2/802.AS1, any layer, Delay_req packet */ 751 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 752 ptp_v2 = PTP_TCR_TSVER2ENA; 753 /* take time stamp for Delay_Req messages only */ 754 ts_master_en = PTP_TCR_TSMSTRENA; 755 ts_event_en = PTP_TCR_TSEVNTENA; 756 757 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 758 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 759 ptp_over_ethernet = PTP_TCR_TSIPENA; 760 break; 761 762 case HWTSTAMP_FILTER_NTP_ALL: 763 case HWTSTAMP_FILTER_ALL: 764 /* time stamp any incoming packet */ 765 config.rx_filter = HWTSTAMP_FILTER_ALL; 766 tstamp_all = PTP_TCR_TSENALL; 767 break; 768 769 default: 770 return -ERANGE; 771 } 772 } else { 773 switch (config.rx_filter) { 774 case HWTSTAMP_FILTER_NONE: 775 config.rx_filter = HWTSTAMP_FILTER_NONE; 776 break; 777 default: 778 /* PTP v1, UDP, any kind of event packet */ 779 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 780 break; 781 } 782 } 783 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 784 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 785 786 priv->systime_flags = STMMAC_HWTS_ACTIVE; 787 788 if (priv->hwts_tx_en || priv->hwts_rx_en) { 789 priv->systime_flags |= tstamp_all | ptp_v2 | 790 ptp_over_ethernet | ptp_over_ipv6_udp | 791 ptp_over_ipv4_udp | ts_event_en | 792 ts_master_en | snap_type_sel; 793 } 794 795 stmmac_config_hw_tstamping(priv, priv->ptpaddr, priv->systime_flags); 796 797 memcpy(&priv->tstamp_config, &config, sizeof(config)); 798 799 return copy_to_user(ifr->ifr_data, &config, 800 sizeof(config)) ? -EFAULT : 0; 801 } 802 803 /** 804 * stmmac_hwtstamp_get - read hardware timestamping. 805 * @dev: device pointer. 806 * @ifr: An IOCTL specific structure, that can contain a pointer to 807 * a proprietary structure used to pass information to the driver. 808 * Description: 809 * This function obtain the current hardware timestamping settings 810 * as requested. 811 */ 812 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 813 { 814 struct stmmac_priv *priv = netdev_priv(dev); 815 struct hwtstamp_config *config = &priv->tstamp_config; 816 817 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 818 return -EOPNOTSUPP; 819 820 return copy_to_user(ifr->ifr_data, config, 821 sizeof(*config)) ? -EFAULT : 0; 822 } 823 824 /** 825 * stmmac_init_tstamp_counter - init hardware timestamping counter 826 * @priv: driver private structure 827 * @systime_flags: timestamping flags 828 * Description: 829 * Initialize hardware counter for packet timestamping. 830 * This is valid as long as the interface is open and not suspended. 831 * Will be rerun after resuming from suspend, case in which the timestamping 832 * flags updated by stmmac_hwtstamp_set() also need to be restored. 833 */ 834 int stmmac_init_tstamp_counter(struct stmmac_priv *priv, u32 systime_flags) 835 { 836 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 837 struct timespec64 now; 838 u32 sec_inc = 0; 839 u64 temp = 0; 840 841 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 842 return -EOPNOTSUPP; 843 844 stmmac_config_hw_tstamping(priv, priv->ptpaddr, systime_flags); 845 priv->systime_flags = systime_flags; 846 847 /* program Sub Second Increment reg */ 848 stmmac_config_sub_second_increment(priv, priv->ptpaddr, 849 priv->plat->clk_ptp_rate, 850 xmac, &sec_inc); 851 temp = div_u64(1000000000ULL, sec_inc); 852 853 /* Store sub second increment for later use */ 854 priv->sub_second_inc = sec_inc; 855 856 /* calculate default added value: 857 * formula is : 858 * addend = (2^32)/freq_div_ratio; 859 * where, freq_div_ratio = 1e9ns/sec_inc 860 */ 861 temp = (u64)(temp << 32); 862 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 863 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 864 865 /* initialize system time */ 866 ktime_get_real_ts64(&now); 867 868 /* lower 32 bits of tv_sec are safe until y2106 */ 869 stmmac_init_systime(priv, priv->ptpaddr, (u32)now.tv_sec, now.tv_nsec); 870 871 return 0; 872 } 873 EXPORT_SYMBOL_GPL(stmmac_init_tstamp_counter); 874 875 /** 876 * stmmac_init_ptp - init PTP 877 * @priv: driver private structure 878 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 879 * This is done by looking at the HW cap. register. 880 * This function also registers the ptp driver. 881 */ 882 static int stmmac_init_ptp(struct stmmac_priv *priv) 883 { 884 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 885 int ret; 886 887 if (priv->plat->ptp_clk_freq_config) 888 priv->plat->ptp_clk_freq_config(priv); 889 890 ret = stmmac_init_tstamp_counter(priv, STMMAC_HWTS_ACTIVE); 891 if (ret) 892 return ret; 893 894 priv->adv_ts = 0; 895 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 896 if (xmac && priv->dma_cap.atime_stamp) 897 priv->adv_ts = 1; 898 /* Dwmac 3.x core with extend_desc can support adv_ts */ 899 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 900 priv->adv_ts = 1; 901 902 if (priv->dma_cap.time_stamp) 903 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 904 905 if (priv->adv_ts) 906 netdev_info(priv->dev, 907 "IEEE 1588-2008 Advanced Timestamp supported\n"); 908 909 priv->hwts_tx_en = 0; 910 priv->hwts_rx_en = 0; 911 912 stmmac_correct_latency(priv, priv); 913 914 return 0; 915 } 916 917 static void stmmac_release_ptp(struct stmmac_priv *priv) 918 { 919 clk_disable_unprepare(priv->plat->clk_ptp_ref); 920 stmmac_ptp_unregister(priv); 921 } 922 923 /** 924 * stmmac_mac_flow_ctrl - Configure flow control in all queues 925 * @priv: driver private structure 926 * @duplex: duplex passed to the next function 927 * Description: It is used for configuring the flow control in all queues 928 */ 929 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 930 { 931 u32 tx_cnt = priv->plat->tx_queues_to_use; 932 933 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 934 priv->pause, tx_cnt); 935 } 936 937 static struct phylink_pcs *stmmac_mac_select_pcs(struct phylink_config *config, 938 phy_interface_t interface) 939 { 940 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 941 942 if (priv->hw->xpcs) 943 return &priv->hw->xpcs->pcs; 944 945 if (priv->hw->lynx_pcs) 946 return priv->hw->lynx_pcs; 947 948 return NULL; 949 } 950 951 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 952 const struct phylink_link_state *state) 953 { 954 /* Nothing to do, xpcs_config() handles everything */ 955 } 956 957 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 958 { 959 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 960 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 961 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 962 bool *hs_enable = &fpe_cfg->hs_enable; 963 964 if (is_up && *hs_enable) { 965 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 966 } else { 967 *lo_state = FPE_STATE_OFF; 968 *lp_state = FPE_STATE_OFF; 969 } 970 } 971 972 static void stmmac_mac_link_down(struct phylink_config *config, 973 unsigned int mode, phy_interface_t interface) 974 { 975 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 976 977 stmmac_mac_set(priv, priv->ioaddr, false); 978 priv->eee_active = false; 979 priv->tx_lpi_enabled = false; 980 priv->eee_enabled = stmmac_eee_init(priv); 981 stmmac_set_eee_pls(priv, priv->hw, false); 982 983 if (priv->dma_cap.fpesel) 984 stmmac_fpe_link_state_handle(priv, false); 985 } 986 987 static void stmmac_mac_link_up(struct phylink_config *config, 988 struct phy_device *phy, 989 unsigned int mode, phy_interface_t interface, 990 int speed, int duplex, 991 bool tx_pause, bool rx_pause) 992 { 993 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 994 u32 old_ctrl, ctrl; 995 996 if ((priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && 997 priv->plat->serdes_powerup) 998 priv->plat->serdes_powerup(priv->dev, priv->plat->bsp_priv); 999 1000 old_ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 1001 ctrl = old_ctrl & ~priv->hw->link.speed_mask; 1002 1003 if (interface == PHY_INTERFACE_MODE_USXGMII) { 1004 switch (speed) { 1005 case SPEED_10000: 1006 ctrl |= priv->hw->link.xgmii.speed10000; 1007 break; 1008 case SPEED_5000: 1009 ctrl |= priv->hw->link.xgmii.speed5000; 1010 break; 1011 case SPEED_2500: 1012 ctrl |= priv->hw->link.xgmii.speed2500; 1013 break; 1014 default: 1015 return; 1016 } 1017 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1018 switch (speed) { 1019 case SPEED_100000: 1020 ctrl |= priv->hw->link.xlgmii.speed100000; 1021 break; 1022 case SPEED_50000: 1023 ctrl |= priv->hw->link.xlgmii.speed50000; 1024 break; 1025 case SPEED_40000: 1026 ctrl |= priv->hw->link.xlgmii.speed40000; 1027 break; 1028 case SPEED_25000: 1029 ctrl |= priv->hw->link.xlgmii.speed25000; 1030 break; 1031 case SPEED_10000: 1032 ctrl |= priv->hw->link.xgmii.speed10000; 1033 break; 1034 case SPEED_2500: 1035 ctrl |= priv->hw->link.speed2500; 1036 break; 1037 case SPEED_1000: 1038 ctrl |= priv->hw->link.speed1000; 1039 break; 1040 default: 1041 return; 1042 } 1043 } else { 1044 switch (speed) { 1045 case SPEED_2500: 1046 ctrl |= priv->hw->link.speed2500; 1047 break; 1048 case SPEED_1000: 1049 ctrl |= priv->hw->link.speed1000; 1050 break; 1051 case SPEED_100: 1052 ctrl |= priv->hw->link.speed100; 1053 break; 1054 case SPEED_10: 1055 ctrl |= priv->hw->link.speed10; 1056 break; 1057 default: 1058 return; 1059 } 1060 } 1061 1062 priv->speed = speed; 1063 1064 if (priv->plat->fix_mac_speed) 1065 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1066 1067 if (!duplex) 1068 ctrl &= ~priv->hw->link.duplex; 1069 else 1070 ctrl |= priv->hw->link.duplex; 1071 1072 /* Flow Control operation */ 1073 if (rx_pause && tx_pause) 1074 priv->flow_ctrl = FLOW_AUTO; 1075 else if (rx_pause && !tx_pause) 1076 priv->flow_ctrl = FLOW_RX; 1077 else if (!rx_pause && tx_pause) 1078 priv->flow_ctrl = FLOW_TX; 1079 else 1080 priv->flow_ctrl = FLOW_OFF; 1081 1082 stmmac_mac_flow_ctrl(priv, duplex); 1083 1084 if (ctrl != old_ctrl) 1085 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1086 1087 stmmac_mac_set(priv, priv->ioaddr, true); 1088 if (phy && priv->dma_cap.eee) { 1089 priv->eee_active = 1090 phy_init_eee(phy, !(priv->plat->flags & 1091 STMMAC_FLAG_RX_CLK_RUNS_IN_LPI)) >= 0; 1092 priv->eee_enabled = stmmac_eee_init(priv); 1093 priv->tx_lpi_enabled = priv->eee_enabled; 1094 stmmac_set_eee_pls(priv, priv->hw, true); 1095 } 1096 1097 if (priv->dma_cap.fpesel) 1098 stmmac_fpe_link_state_handle(priv, true); 1099 1100 stmmac_correct_latency(priv, priv); 1101 } 1102 1103 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1104 .mac_select_pcs = stmmac_mac_select_pcs, 1105 .mac_config = stmmac_mac_config, 1106 .mac_link_down = stmmac_mac_link_down, 1107 .mac_link_up = stmmac_mac_link_up, 1108 }; 1109 1110 /** 1111 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1112 * @priv: driver private structure 1113 * Description: this is to verify if the HW supports the PCS. 1114 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1115 * configured for the TBI, RTBI, or SGMII PHY interface. 1116 */ 1117 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1118 { 1119 int interface = priv->plat->interface; 1120 1121 if (priv->dma_cap.pcs) { 1122 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1123 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1124 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1125 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1126 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1127 priv->hw->pcs = STMMAC_PCS_RGMII; 1128 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1129 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1130 priv->hw->pcs = STMMAC_PCS_SGMII; 1131 } 1132 } 1133 } 1134 1135 /** 1136 * stmmac_init_phy - PHY initialization 1137 * @dev: net device structure 1138 * Description: it initializes the driver's PHY state, and attaches the PHY 1139 * to the mac driver. 1140 * Return value: 1141 * 0 on success 1142 */ 1143 static int stmmac_init_phy(struct net_device *dev) 1144 { 1145 struct stmmac_priv *priv = netdev_priv(dev); 1146 struct fwnode_handle *phy_fwnode; 1147 struct fwnode_handle *fwnode; 1148 int ret; 1149 1150 if (!phylink_expects_phy(priv->phylink)) 1151 return 0; 1152 1153 fwnode = of_fwnode_handle(priv->plat->phylink_node); 1154 if (!fwnode) 1155 fwnode = dev_fwnode(priv->device); 1156 1157 if (fwnode) 1158 phy_fwnode = fwnode_get_phy_node(fwnode); 1159 else 1160 phy_fwnode = NULL; 1161 1162 /* Some DT bindings do not set-up the PHY handle. Let's try to 1163 * manually parse it 1164 */ 1165 if (!phy_fwnode || IS_ERR(phy_fwnode)) { 1166 int addr = priv->plat->phy_addr; 1167 struct phy_device *phydev; 1168 1169 if (addr < 0) { 1170 netdev_err(priv->dev, "no phy found\n"); 1171 return -ENODEV; 1172 } 1173 1174 phydev = mdiobus_get_phy(priv->mii, addr); 1175 if (!phydev) { 1176 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1177 return -ENODEV; 1178 } 1179 1180 ret = phylink_connect_phy(priv->phylink, phydev); 1181 } else { 1182 fwnode_handle_put(phy_fwnode); 1183 ret = phylink_fwnode_phy_connect(priv->phylink, fwnode, 0); 1184 } 1185 1186 if (!priv->plat->pmt) { 1187 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1188 1189 phylink_ethtool_get_wol(priv->phylink, &wol); 1190 device_set_wakeup_capable(priv->device, !!wol.supported); 1191 device_set_wakeup_enable(priv->device, !!wol.wolopts); 1192 } 1193 1194 return ret; 1195 } 1196 1197 static int stmmac_phy_setup(struct stmmac_priv *priv) 1198 { 1199 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1200 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1201 int max_speed = priv->plat->max_speed; 1202 int mode = priv->plat->phy_interface; 1203 struct phylink *phylink; 1204 1205 priv->phylink_config.dev = &priv->dev->dev; 1206 priv->phylink_config.type = PHYLINK_NETDEV; 1207 if (priv->plat->mdio_bus_data) 1208 priv->phylink_config.ovr_an_inband = 1209 mdio_bus_data->xpcs_an_inband; 1210 1211 if (!fwnode) 1212 fwnode = dev_fwnode(priv->device); 1213 1214 /* Set the platform/firmware specified interface mode */ 1215 __set_bit(mode, priv->phylink_config.supported_interfaces); 1216 1217 /* If we have an xpcs, it defines which PHY interfaces are supported. */ 1218 if (priv->hw->xpcs) 1219 xpcs_get_interfaces(priv->hw->xpcs, 1220 priv->phylink_config.supported_interfaces); 1221 1222 priv->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 1223 MAC_10 | MAC_100; 1224 1225 if (!max_speed || max_speed >= 1000) 1226 priv->phylink_config.mac_capabilities |= MAC_1000; 1227 1228 if (priv->plat->has_gmac4) { 1229 if (!max_speed || max_speed >= 2500) 1230 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1231 } else if (priv->plat->has_xgmac) { 1232 if (!max_speed || max_speed >= 2500) 1233 priv->phylink_config.mac_capabilities |= MAC_2500FD; 1234 if (!max_speed || max_speed >= 5000) 1235 priv->phylink_config.mac_capabilities |= MAC_5000FD; 1236 if (!max_speed || max_speed >= 10000) 1237 priv->phylink_config.mac_capabilities |= MAC_10000FD; 1238 if (!max_speed || max_speed >= 25000) 1239 priv->phylink_config.mac_capabilities |= MAC_25000FD; 1240 if (!max_speed || max_speed >= 40000) 1241 priv->phylink_config.mac_capabilities |= MAC_40000FD; 1242 if (!max_speed || max_speed >= 50000) 1243 priv->phylink_config.mac_capabilities |= MAC_50000FD; 1244 if (!max_speed || max_speed >= 100000) 1245 priv->phylink_config.mac_capabilities |= MAC_100000FD; 1246 } 1247 1248 /* Half-Duplex can only work with single queue */ 1249 if (priv->plat->tx_queues_to_use > 1) 1250 priv->phylink_config.mac_capabilities &= 1251 ~(MAC_10HD | MAC_100HD | MAC_1000HD); 1252 priv->phylink_config.mac_managed_pm = true; 1253 1254 phylink = phylink_create(&priv->phylink_config, fwnode, 1255 mode, &stmmac_phylink_mac_ops); 1256 if (IS_ERR(phylink)) 1257 return PTR_ERR(phylink); 1258 1259 priv->phylink = phylink; 1260 return 0; 1261 } 1262 1263 static void stmmac_display_rx_rings(struct stmmac_priv *priv, 1264 struct stmmac_dma_conf *dma_conf) 1265 { 1266 u32 rx_cnt = priv->plat->rx_queues_to_use; 1267 unsigned int desc_size; 1268 void *head_rx; 1269 u32 queue; 1270 1271 /* Display RX rings */ 1272 for (queue = 0; queue < rx_cnt; queue++) { 1273 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1274 1275 pr_info("\tRX Queue %u rings\n", queue); 1276 1277 if (priv->extend_desc) { 1278 head_rx = (void *)rx_q->dma_erx; 1279 desc_size = sizeof(struct dma_extended_desc); 1280 } else { 1281 head_rx = (void *)rx_q->dma_rx; 1282 desc_size = sizeof(struct dma_desc); 1283 } 1284 1285 /* Display RX ring */ 1286 stmmac_display_ring(priv, head_rx, dma_conf->dma_rx_size, true, 1287 rx_q->dma_rx_phy, desc_size); 1288 } 1289 } 1290 1291 static void stmmac_display_tx_rings(struct stmmac_priv *priv, 1292 struct stmmac_dma_conf *dma_conf) 1293 { 1294 u32 tx_cnt = priv->plat->tx_queues_to_use; 1295 unsigned int desc_size; 1296 void *head_tx; 1297 u32 queue; 1298 1299 /* Display TX rings */ 1300 for (queue = 0; queue < tx_cnt; queue++) { 1301 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1302 1303 pr_info("\tTX Queue %d rings\n", queue); 1304 1305 if (priv->extend_desc) { 1306 head_tx = (void *)tx_q->dma_etx; 1307 desc_size = sizeof(struct dma_extended_desc); 1308 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1309 head_tx = (void *)tx_q->dma_entx; 1310 desc_size = sizeof(struct dma_edesc); 1311 } else { 1312 head_tx = (void *)tx_q->dma_tx; 1313 desc_size = sizeof(struct dma_desc); 1314 } 1315 1316 stmmac_display_ring(priv, head_tx, dma_conf->dma_tx_size, false, 1317 tx_q->dma_tx_phy, desc_size); 1318 } 1319 } 1320 1321 static void stmmac_display_rings(struct stmmac_priv *priv, 1322 struct stmmac_dma_conf *dma_conf) 1323 { 1324 /* Display RX ring */ 1325 stmmac_display_rx_rings(priv, dma_conf); 1326 1327 /* Display TX ring */ 1328 stmmac_display_tx_rings(priv, dma_conf); 1329 } 1330 1331 static int stmmac_set_bfsize(int mtu, int bufsize) 1332 { 1333 int ret = bufsize; 1334 1335 if (mtu >= BUF_SIZE_8KiB) 1336 ret = BUF_SIZE_16KiB; 1337 else if (mtu >= BUF_SIZE_4KiB) 1338 ret = BUF_SIZE_8KiB; 1339 else if (mtu >= BUF_SIZE_2KiB) 1340 ret = BUF_SIZE_4KiB; 1341 else if (mtu > DEFAULT_BUFSIZE) 1342 ret = BUF_SIZE_2KiB; 1343 else 1344 ret = DEFAULT_BUFSIZE; 1345 1346 return ret; 1347 } 1348 1349 /** 1350 * stmmac_clear_rx_descriptors - clear RX descriptors 1351 * @priv: driver private structure 1352 * @dma_conf: structure to take the dma data 1353 * @queue: RX queue index 1354 * Description: this function is called to clear the RX descriptors 1355 * in case of both basic and extended descriptors are used. 1356 */ 1357 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, 1358 struct stmmac_dma_conf *dma_conf, 1359 u32 queue) 1360 { 1361 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1362 int i; 1363 1364 /* Clear the RX descriptors */ 1365 for (i = 0; i < dma_conf->dma_rx_size; i++) 1366 if (priv->extend_desc) 1367 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1368 priv->use_riwt, priv->mode, 1369 (i == dma_conf->dma_rx_size - 1), 1370 dma_conf->dma_buf_sz); 1371 else 1372 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1373 priv->use_riwt, priv->mode, 1374 (i == dma_conf->dma_rx_size - 1), 1375 dma_conf->dma_buf_sz); 1376 } 1377 1378 /** 1379 * stmmac_clear_tx_descriptors - clear tx descriptors 1380 * @priv: driver private structure 1381 * @dma_conf: structure to take the dma data 1382 * @queue: TX queue index. 1383 * Description: this function is called to clear the TX descriptors 1384 * in case of both basic and extended descriptors are used. 1385 */ 1386 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, 1387 struct stmmac_dma_conf *dma_conf, 1388 u32 queue) 1389 { 1390 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1391 int i; 1392 1393 /* Clear the TX descriptors */ 1394 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1395 int last = (i == (dma_conf->dma_tx_size - 1)); 1396 struct dma_desc *p; 1397 1398 if (priv->extend_desc) 1399 p = &tx_q->dma_etx[i].basic; 1400 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1401 p = &tx_q->dma_entx[i].basic; 1402 else 1403 p = &tx_q->dma_tx[i]; 1404 1405 stmmac_init_tx_desc(priv, p, priv->mode, last); 1406 } 1407 } 1408 1409 /** 1410 * stmmac_clear_descriptors - clear descriptors 1411 * @priv: driver private structure 1412 * @dma_conf: structure to take the dma data 1413 * Description: this function is called to clear the TX and RX descriptors 1414 * in case of both basic and extended descriptors are used. 1415 */ 1416 static void stmmac_clear_descriptors(struct stmmac_priv *priv, 1417 struct stmmac_dma_conf *dma_conf) 1418 { 1419 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1420 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1421 u32 queue; 1422 1423 /* Clear the RX descriptors */ 1424 for (queue = 0; queue < rx_queue_cnt; queue++) 1425 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1426 1427 /* Clear the TX descriptors */ 1428 for (queue = 0; queue < tx_queue_cnt; queue++) 1429 stmmac_clear_tx_descriptors(priv, dma_conf, queue); 1430 } 1431 1432 /** 1433 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1434 * @priv: driver private structure 1435 * @dma_conf: structure to take the dma data 1436 * @p: descriptor pointer 1437 * @i: descriptor index 1438 * @flags: gfp flag 1439 * @queue: RX queue index 1440 * Description: this function is called to allocate a receive buffer, perform 1441 * the DMA mapping and init the descriptor. 1442 */ 1443 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, 1444 struct stmmac_dma_conf *dma_conf, 1445 struct dma_desc *p, 1446 int i, gfp_t flags, u32 queue) 1447 { 1448 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1449 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1450 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 1451 1452 if (priv->dma_cap.host_dma_width <= 32) 1453 gfp |= GFP_DMA32; 1454 1455 if (!buf->page) { 1456 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1457 if (!buf->page) 1458 return -ENOMEM; 1459 buf->page_offset = stmmac_rx_offset(priv); 1460 } 1461 1462 if (priv->sph && !buf->sec_page) { 1463 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 1464 if (!buf->sec_page) 1465 return -ENOMEM; 1466 1467 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1468 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1469 } else { 1470 buf->sec_page = NULL; 1471 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1472 } 1473 1474 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1475 1476 stmmac_set_desc_addr(priv, p, buf->addr); 1477 if (dma_conf->dma_buf_sz == BUF_SIZE_16KiB) 1478 stmmac_init_desc3(priv, p); 1479 1480 return 0; 1481 } 1482 1483 /** 1484 * stmmac_free_rx_buffer - free RX dma buffers 1485 * @priv: private structure 1486 * @rx_q: RX queue 1487 * @i: buffer index. 1488 */ 1489 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, 1490 struct stmmac_rx_queue *rx_q, 1491 int i) 1492 { 1493 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1494 1495 if (buf->page) 1496 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1497 buf->page = NULL; 1498 1499 if (buf->sec_page) 1500 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1501 buf->sec_page = NULL; 1502 } 1503 1504 /** 1505 * stmmac_free_tx_buffer - free RX dma buffers 1506 * @priv: private structure 1507 * @dma_conf: structure to take the dma data 1508 * @queue: RX queue index 1509 * @i: buffer index. 1510 */ 1511 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, 1512 struct stmmac_dma_conf *dma_conf, 1513 u32 queue, int i) 1514 { 1515 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1516 1517 if (tx_q->tx_skbuff_dma[i].buf && 1518 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1519 if (tx_q->tx_skbuff_dma[i].map_as_page) 1520 dma_unmap_page(priv->device, 1521 tx_q->tx_skbuff_dma[i].buf, 1522 tx_q->tx_skbuff_dma[i].len, 1523 DMA_TO_DEVICE); 1524 else 1525 dma_unmap_single(priv->device, 1526 tx_q->tx_skbuff_dma[i].buf, 1527 tx_q->tx_skbuff_dma[i].len, 1528 DMA_TO_DEVICE); 1529 } 1530 1531 if (tx_q->xdpf[i] && 1532 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1533 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1534 xdp_return_frame(tx_q->xdpf[i]); 1535 tx_q->xdpf[i] = NULL; 1536 } 1537 1538 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1539 tx_q->xsk_frames_done++; 1540 1541 if (tx_q->tx_skbuff[i] && 1542 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1543 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1544 tx_q->tx_skbuff[i] = NULL; 1545 } 1546 1547 tx_q->tx_skbuff_dma[i].buf = 0; 1548 tx_q->tx_skbuff_dma[i].map_as_page = false; 1549 } 1550 1551 /** 1552 * dma_free_rx_skbufs - free RX dma buffers 1553 * @priv: private structure 1554 * @dma_conf: structure to take the dma data 1555 * @queue: RX queue index 1556 */ 1557 static void dma_free_rx_skbufs(struct stmmac_priv *priv, 1558 struct stmmac_dma_conf *dma_conf, 1559 u32 queue) 1560 { 1561 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1562 int i; 1563 1564 for (i = 0; i < dma_conf->dma_rx_size; i++) 1565 stmmac_free_rx_buffer(priv, rx_q, i); 1566 } 1567 1568 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, 1569 struct stmmac_dma_conf *dma_conf, 1570 u32 queue, gfp_t flags) 1571 { 1572 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1573 int i; 1574 1575 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1576 struct dma_desc *p; 1577 int ret; 1578 1579 if (priv->extend_desc) 1580 p = &((rx_q->dma_erx + i)->basic); 1581 else 1582 p = rx_q->dma_rx + i; 1583 1584 ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, flags, 1585 queue); 1586 if (ret) 1587 return ret; 1588 1589 rx_q->buf_alloc_num++; 1590 } 1591 1592 return 0; 1593 } 1594 1595 /** 1596 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1597 * @priv: private structure 1598 * @dma_conf: structure to take the dma data 1599 * @queue: RX queue index 1600 */ 1601 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, 1602 struct stmmac_dma_conf *dma_conf, 1603 u32 queue) 1604 { 1605 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1606 int i; 1607 1608 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1609 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1610 1611 if (!buf->xdp) 1612 continue; 1613 1614 xsk_buff_free(buf->xdp); 1615 buf->xdp = NULL; 1616 } 1617 } 1618 1619 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, 1620 struct stmmac_dma_conf *dma_conf, 1621 u32 queue) 1622 { 1623 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1624 int i; 1625 1626 /* struct stmmac_xdp_buff is using cb field (maximum size of 24 bytes) 1627 * in struct xdp_buff_xsk to stash driver specific information. Thus, 1628 * use this macro to make sure no size violations. 1629 */ 1630 XSK_CHECK_PRIV_TYPE(struct stmmac_xdp_buff); 1631 1632 for (i = 0; i < dma_conf->dma_rx_size; i++) { 1633 struct stmmac_rx_buffer *buf; 1634 dma_addr_t dma_addr; 1635 struct dma_desc *p; 1636 1637 if (priv->extend_desc) 1638 p = (struct dma_desc *)(rx_q->dma_erx + i); 1639 else 1640 p = rx_q->dma_rx + i; 1641 1642 buf = &rx_q->buf_pool[i]; 1643 1644 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1645 if (!buf->xdp) 1646 return -ENOMEM; 1647 1648 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1649 stmmac_set_desc_addr(priv, p, dma_addr); 1650 rx_q->buf_alloc_num++; 1651 } 1652 1653 return 0; 1654 } 1655 1656 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1657 { 1658 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1659 return NULL; 1660 1661 return xsk_get_pool_from_qid(priv->dev, queue); 1662 } 1663 1664 /** 1665 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1666 * @priv: driver private structure 1667 * @dma_conf: structure to take the dma data 1668 * @queue: RX queue index 1669 * @flags: gfp flag. 1670 * Description: this function initializes the DMA RX descriptors 1671 * and allocates the socket buffers. It supports the chained and ring 1672 * modes. 1673 */ 1674 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, 1675 struct stmmac_dma_conf *dma_conf, 1676 u32 queue, gfp_t flags) 1677 { 1678 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1679 int ret; 1680 1681 netif_dbg(priv, probe, priv->dev, 1682 "(%s) dma_rx_phy=0x%08x\n", __func__, 1683 (u32)rx_q->dma_rx_phy); 1684 1685 stmmac_clear_rx_descriptors(priv, dma_conf, queue); 1686 1687 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1688 1689 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1690 1691 if (rx_q->xsk_pool) { 1692 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1693 MEM_TYPE_XSK_BUFF_POOL, 1694 NULL)); 1695 netdev_info(priv->dev, 1696 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1697 rx_q->queue_index); 1698 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1699 } else { 1700 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1701 MEM_TYPE_PAGE_POOL, 1702 rx_q->page_pool)); 1703 netdev_info(priv->dev, 1704 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1705 rx_q->queue_index); 1706 } 1707 1708 if (rx_q->xsk_pool) { 1709 /* RX XDP ZC buffer pool may not be populated, e.g. 1710 * xdpsock TX-only. 1711 */ 1712 stmmac_alloc_rx_buffers_zc(priv, dma_conf, queue); 1713 } else { 1714 ret = stmmac_alloc_rx_buffers(priv, dma_conf, queue, flags); 1715 if (ret < 0) 1716 return -ENOMEM; 1717 } 1718 1719 /* Setup the chained descriptor addresses */ 1720 if (priv->mode == STMMAC_CHAIN_MODE) { 1721 if (priv->extend_desc) 1722 stmmac_mode_init(priv, rx_q->dma_erx, 1723 rx_q->dma_rx_phy, 1724 dma_conf->dma_rx_size, 1); 1725 else 1726 stmmac_mode_init(priv, rx_q->dma_rx, 1727 rx_q->dma_rx_phy, 1728 dma_conf->dma_rx_size, 0); 1729 } 1730 1731 return 0; 1732 } 1733 1734 static int init_dma_rx_desc_rings(struct net_device *dev, 1735 struct stmmac_dma_conf *dma_conf, 1736 gfp_t flags) 1737 { 1738 struct stmmac_priv *priv = netdev_priv(dev); 1739 u32 rx_count = priv->plat->rx_queues_to_use; 1740 int queue; 1741 int ret; 1742 1743 /* RX INITIALIZATION */ 1744 netif_dbg(priv, probe, priv->dev, 1745 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1746 1747 for (queue = 0; queue < rx_count; queue++) { 1748 ret = __init_dma_rx_desc_rings(priv, dma_conf, queue, flags); 1749 if (ret) 1750 goto err_init_rx_buffers; 1751 } 1752 1753 return 0; 1754 1755 err_init_rx_buffers: 1756 while (queue >= 0) { 1757 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1758 1759 if (rx_q->xsk_pool) 1760 dma_free_rx_xskbufs(priv, dma_conf, queue); 1761 else 1762 dma_free_rx_skbufs(priv, dma_conf, queue); 1763 1764 rx_q->buf_alloc_num = 0; 1765 rx_q->xsk_pool = NULL; 1766 1767 queue--; 1768 } 1769 1770 return ret; 1771 } 1772 1773 /** 1774 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1775 * @priv: driver private structure 1776 * @dma_conf: structure to take the dma data 1777 * @queue: TX queue index 1778 * Description: this function initializes the DMA TX descriptors 1779 * and allocates the socket buffers. It supports the chained and ring 1780 * modes. 1781 */ 1782 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, 1783 struct stmmac_dma_conf *dma_conf, 1784 u32 queue) 1785 { 1786 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1787 int i; 1788 1789 netif_dbg(priv, probe, priv->dev, 1790 "(%s) dma_tx_phy=0x%08x\n", __func__, 1791 (u32)tx_q->dma_tx_phy); 1792 1793 /* Setup the chained descriptor addresses */ 1794 if (priv->mode == STMMAC_CHAIN_MODE) { 1795 if (priv->extend_desc) 1796 stmmac_mode_init(priv, tx_q->dma_etx, 1797 tx_q->dma_tx_phy, 1798 dma_conf->dma_tx_size, 1); 1799 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1800 stmmac_mode_init(priv, tx_q->dma_tx, 1801 tx_q->dma_tx_phy, 1802 dma_conf->dma_tx_size, 0); 1803 } 1804 1805 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1806 1807 for (i = 0; i < dma_conf->dma_tx_size; i++) { 1808 struct dma_desc *p; 1809 1810 if (priv->extend_desc) 1811 p = &((tx_q->dma_etx + i)->basic); 1812 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1813 p = &((tx_q->dma_entx + i)->basic); 1814 else 1815 p = tx_q->dma_tx + i; 1816 1817 stmmac_clear_desc(priv, p); 1818 1819 tx_q->tx_skbuff_dma[i].buf = 0; 1820 tx_q->tx_skbuff_dma[i].map_as_page = false; 1821 tx_q->tx_skbuff_dma[i].len = 0; 1822 tx_q->tx_skbuff_dma[i].last_segment = false; 1823 tx_q->tx_skbuff[i] = NULL; 1824 } 1825 1826 return 0; 1827 } 1828 1829 static int init_dma_tx_desc_rings(struct net_device *dev, 1830 struct stmmac_dma_conf *dma_conf) 1831 { 1832 struct stmmac_priv *priv = netdev_priv(dev); 1833 u32 tx_queue_cnt; 1834 u32 queue; 1835 1836 tx_queue_cnt = priv->plat->tx_queues_to_use; 1837 1838 for (queue = 0; queue < tx_queue_cnt; queue++) 1839 __init_dma_tx_desc_rings(priv, dma_conf, queue); 1840 1841 return 0; 1842 } 1843 1844 /** 1845 * init_dma_desc_rings - init the RX/TX descriptor rings 1846 * @dev: net device structure 1847 * @dma_conf: structure to take the dma data 1848 * @flags: gfp flag. 1849 * Description: this function initializes the DMA RX/TX descriptors 1850 * and allocates the socket buffers. It supports the chained and ring 1851 * modes. 1852 */ 1853 static int init_dma_desc_rings(struct net_device *dev, 1854 struct stmmac_dma_conf *dma_conf, 1855 gfp_t flags) 1856 { 1857 struct stmmac_priv *priv = netdev_priv(dev); 1858 int ret; 1859 1860 ret = init_dma_rx_desc_rings(dev, dma_conf, flags); 1861 if (ret) 1862 return ret; 1863 1864 ret = init_dma_tx_desc_rings(dev, dma_conf); 1865 1866 stmmac_clear_descriptors(priv, dma_conf); 1867 1868 if (netif_msg_hw(priv)) 1869 stmmac_display_rings(priv, dma_conf); 1870 1871 return ret; 1872 } 1873 1874 /** 1875 * dma_free_tx_skbufs - free TX dma buffers 1876 * @priv: private structure 1877 * @dma_conf: structure to take the dma data 1878 * @queue: TX queue index 1879 */ 1880 static void dma_free_tx_skbufs(struct stmmac_priv *priv, 1881 struct stmmac_dma_conf *dma_conf, 1882 u32 queue) 1883 { 1884 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1885 int i; 1886 1887 tx_q->xsk_frames_done = 0; 1888 1889 for (i = 0; i < dma_conf->dma_tx_size; i++) 1890 stmmac_free_tx_buffer(priv, dma_conf, queue, i); 1891 1892 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1893 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1894 tx_q->xsk_frames_done = 0; 1895 tx_q->xsk_pool = NULL; 1896 } 1897 } 1898 1899 /** 1900 * stmmac_free_tx_skbufs - free TX skb buffers 1901 * @priv: private structure 1902 */ 1903 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1904 { 1905 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1906 u32 queue; 1907 1908 for (queue = 0; queue < tx_queue_cnt; queue++) 1909 dma_free_tx_skbufs(priv, &priv->dma_conf, queue); 1910 } 1911 1912 /** 1913 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1914 * @priv: private structure 1915 * @dma_conf: structure to take the dma data 1916 * @queue: RX queue index 1917 */ 1918 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, 1919 struct stmmac_dma_conf *dma_conf, 1920 u32 queue) 1921 { 1922 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 1923 1924 /* Release the DMA RX socket buffers */ 1925 if (rx_q->xsk_pool) 1926 dma_free_rx_xskbufs(priv, dma_conf, queue); 1927 else 1928 dma_free_rx_skbufs(priv, dma_conf, queue); 1929 1930 rx_q->buf_alloc_num = 0; 1931 rx_q->xsk_pool = NULL; 1932 1933 /* Free DMA regions of consistent memory previously allocated */ 1934 if (!priv->extend_desc) 1935 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1936 sizeof(struct dma_desc), 1937 rx_q->dma_rx, rx_q->dma_rx_phy); 1938 else 1939 dma_free_coherent(priv->device, dma_conf->dma_rx_size * 1940 sizeof(struct dma_extended_desc), 1941 rx_q->dma_erx, rx_q->dma_rx_phy); 1942 1943 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1944 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1945 1946 kfree(rx_q->buf_pool); 1947 if (rx_q->page_pool) 1948 page_pool_destroy(rx_q->page_pool); 1949 } 1950 1951 static void free_dma_rx_desc_resources(struct stmmac_priv *priv, 1952 struct stmmac_dma_conf *dma_conf) 1953 { 1954 u32 rx_count = priv->plat->rx_queues_to_use; 1955 u32 queue; 1956 1957 /* Free RX queue resources */ 1958 for (queue = 0; queue < rx_count; queue++) 1959 __free_dma_rx_desc_resources(priv, dma_conf, queue); 1960 } 1961 1962 /** 1963 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1964 * @priv: private structure 1965 * @dma_conf: structure to take the dma data 1966 * @queue: TX queue index 1967 */ 1968 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, 1969 struct stmmac_dma_conf *dma_conf, 1970 u32 queue) 1971 { 1972 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 1973 size_t size; 1974 void *addr; 1975 1976 /* Release the DMA TX socket buffers */ 1977 dma_free_tx_skbufs(priv, dma_conf, queue); 1978 1979 if (priv->extend_desc) { 1980 size = sizeof(struct dma_extended_desc); 1981 addr = tx_q->dma_etx; 1982 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1983 size = sizeof(struct dma_edesc); 1984 addr = tx_q->dma_entx; 1985 } else { 1986 size = sizeof(struct dma_desc); 1987 addr = tx_q->dma_tx; 1988 } 1989 1990 size *= dma_conf->dma_tx_size; 1991 1992 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1993 1994 kfree(tx_q->tx_skbuff_dma); 1995 kfree(tx_q->tx_skbuff); 1996 } 1997 1998 static void free_dma_tx_desc_resources(struct stmmac_priv *priv, 1999 struct stmmac_dma_conf *dma_conf) 2000 { 2001 u32 tx_count = priv->plat->tx_queues_to_use; 2002 u32 queue; 2003 2004 /* Free TX queue resources */ 2005 for (queue = 0; queue < tx_count; queue++) 2006 __free_dma_tx_desc_resources(priv, dma_conf, queue); 2007 } 2008 2009 /** 2010 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 2011 * @priv: private structure 2012 * @dma_conf: structure to take the dma data 2013 * @queue: RX queue index 2014 * Description: according to which descriptor can be used (extend or basic) 2015 * this function allocates the resources for TX and RX paths. In case of 2016 * reception, for example, it pre-allocated the RX socket buffer in order to 2017 * allow zero-copy mechanism. 2018 */ 2019 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2020 struct stmmac_dma_conf *dma_conf, 2021 u32 queue) 2022 { 2023 struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; 2024 struct stmmac_channel *ch = &priv->channel[queue]; 2025 bool xdp_prog = stmmac_xdp_is_enabled(priv); 2026 struct page_pool_params pp_params = { 0 }; 2027 unsigned int num_pages; 2028 unsigned int napi_id; 2029 int ret; 2030 2031 rx_q->queue_index = queue; 2032 rx_q->priv_data = priv; 2033 2034 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 2035 pp_params.pool_size = dma_conf->dma_rx_size; 2036 num_pages = DIV_ROUND_UP(dma_conf->dma_buf_sz, PAGE_SIZE); 2037 pp_params.order = ilog2(num_pages); 2038 pp_params.nid = dev_to_node(priv->device); 2039 pp_params.dev = priv->device; 2040 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 2041 pp_params.offset = stmmac_rx_offset(priv); 2042 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 2043 2044 rx_q->page_pool = page_pool_create(&pp_params); 2045 if (IS_ERR(rx_q->page_pool)) { 2046 ret = PTR_ERR(rx_q->page_pool); 2047 rx_q->page_pool = NULL; 2048 return ret; 2049 } 2050 2051 rx_q->buf_pool = kcalloc(dma_conf->dma_rx_size, 2052 sizeof(*rx_q->buf_pool), 2053 GFP_KERNEL); 2054 if (!rx_q->buf_pool) 2055 return -ENOMEM; 2056 2057 if (priv->extend_desc) { 2058 rx_q->dma_erx = dma_alloc_coherent(priv->device, 2059 dma_conf->dma_rx_size * 2060 sizeof(struct dma_extended_desc), 2061 &rx_q->dma_rx_phy, 2062 GFP_KERNEL); 2063 if (!rx_q->dma_erx) 2064 return -ENOMEM; 2065 2066 } else { 2067 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2068 dma_conf->dma_rx_size * 2069 sizeof(struct dma_desc), 2070 &rx_q->dma_rx_phy, 2071 GFP_KERNEL); 2072 if (!rx_q->dma_rx) 2073 return -ENOMEM; 2074 } 2075 2076 if (stmmac_xdp_is_enabled(priv) && 2077 test_bit(queue, priv->af_xdp_zc_qps)) 2078 napi_id = ch->rxtx_napi.napi_id; 2079 else 2080 napi_id = ch->rx_napi.napi_id; 2081 2082 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2083 rx_q->queue_index, 2084 napi_id); 2085 if (ret) { 2086 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2087 return -EINVAL; 2088 } 2089 2090 return 0; 2091 } 2092 2093 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv, 2094 struct stmmac_dma_conf *dma_conf) 2095 { 2096 u32 rx_count = priv->plat->rx_queues_to_use; 2097 u32 queue; 2098 int ret; 2099 2100 /* RX queues buffers and DMA */ 2101 for (queue = 0; queue < rx_count; queue++) { 2102 ret = __alloc_dma_rx_desc_resources(priv, dma_conf, queue); 2103 if (ret) 2104 goto err_dma; 2105 } 2106 2107 return 0; 2108 2109 err_dma: 2110 free_dma_rx_desc_resources(priv, dma_conf); 2111 2112 return ret; 2113 } 2114 2115 /** 2116 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2117 * @priv: private structure 2118 * @dma_conf: structure to take the dma data 2119 * @queue: TX queue index 2120 * Description: according to which descriptor can be used (extend or basic) 2121 * this function allocates the resources for TX and RX paths. In case of 2122 * reception, for example, it pre-allocated the RX socket buffer in order to 2123 * allow zero-copy mechanism. 2124 */ 2125 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2126 struct stmmac_dma_conf *dma_conf, 2127 u32 queue) 2128 { 2129 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[queue]; 2130 size_t size; 2131 void *addr; 2132 2133 tx_q->queue_index = queue; 2134 tx_q->priv_data = priv; 2135 2136 tx_q->tx_skbuff_dma = kcalloc(dma_conf->dma_tx_size, 2137 sizeof(*tx_q->tx_skbuff_dma), 2138 GFP_KERNEL); 2139 if (!tx_q->tx_skbuff_dma) 2140 return -ENOMEM; 2141 2142 tx_q->tx_skbuff = kcalloc(dma_conf->dma_tx_size, 2143 sizeof(struct sk_buff *), 2144 GFP_KERNEL); 2145 if (!tx_q->tx_skbuff) 2146 return -ENOMEM; 2147 2148 if (priv->extend_desc) 2149 size = sizeof(struct dma_extended_desc); 2150 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2151 size = sizeof(struct dma_edesc); 2152 else 2153 size = sizeof(struct dma_desc); 2154 2155 size *= dma_conf->dma_tx_size; 2156 2157 addr = dma_alloc_coherent(priv->device, size, 2158 &tx_q->dma_tx_phy, GFP_KERNEL); 2159 if (!addr) 2160 return -ENOMEM; 2161 2162 if (priv->extend_desc) 2163 tx_q->dma_etx = addr; 2164 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2165 tx_q->dma_entx = addr; 2166 else 2167 tx_q->dma_tx = addr; 2168 2169 return 0; 2170 } 2171 2172 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv, 2173 struct stmmac_dma_conf *dma_conf) 2174 { 2175 u32 tx_count = priv->plat->tx_queues_to_use; 2176 u32 queue; 2177 int ret; 2178 2179 /* TX queues buffers and DMA */ 2180 for (queue = 0; queue < tx_count; queue++) { 2181 ret = __alloc_dma_tx_desc_resources(priv, dma_conf, queue); 2182 if (ret) 2183 goto err_dma; 2184 } 2185 2186 return 0; 2187 2188 err_dma: 2189 free_dma_tx_desc_resources(priv, dma_conf); 2190 return ret; 2191 } 2192 2193 /** 2194 * alloc_dma_desc_resources - alloc TX/RX resources. 2195 * @priv: private structure 2196 * @dma_conf: structure to take the dma data 2197 * Description: according to which descriptor can be used (extend or basic) 2198 * this function allocates the resources for TX and RX paths. In case of 2199 * reception, for example, it pre-allocated the RX socket buffer in order to 2200 * allow zero-copy mechanism. 2201 */ 2202 static int alloc_dma_desc_resources(struct stmmac_priv *priv, 2203 struct stmmac_dma_conf *dma_conf) 2204 { 2205 /* RX Allocation */ 2206 int ret = alloc_dma_rx_desc_resources(priv, dma_conf); 2207 2208 if (ret) 2209 return ret; 2210 2211 ret = alloc_dma_tx_desc_resources(priv, dma_conf); 2212 2213 return ret; 2214 } 2215 2216 /** 2217 * free_dma_desc_resources - free dma desc resources 2218 * @priv: private structure 2219 * @dma_conf: structure to take the dma data 2220 */ 2221 static void free_dma_desc_resources(struct stmmac_priv *priv, 2222 struct stmmac_dma_conf *dma_conf) 2223 { 2224 /* Release the DMA TX socket buffers */ 2225 free_dma_tx_desc_resources(priv, dma_conf); 2226 2227 /* Release the DMA RX socket buffers later 2228 * to ensure all pending XDP_TX buffers are returned. 2229 */ 2230 free_dma_rx_desc_resources(priv, dma_conf); 2231 } 2232 2233 /** 2234 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2235 * @priv: driver private structure 2236 * Description: It is used for enabling the rx queues in the MAC 2237 */ 2238 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2239 { 2240 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2241 int queue; 2242 u8 mode; 2243 2244 for (queue = 0; queue < rx_queues_count; queue++) { 2245 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2246 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2247 } 2248 } 2249 2250 /** 2251 * stmmac_start_rx_dma - start RX DMA channel 2252 * @priv: driver private structure 2253 * @chan: RX channel index 2254 * Description: 2255 * This starts a RX DMA channel 2256 */ 2257 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2258 { 2259 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2260 stmmac_start_rx(priv, priv->ioaddr, chan); 2261 } 2262 2263 /** 2264 * stmmac_start_tx_dma - start TX DMA channel 2265 * @priv: driver private structure 2266 * @chan: TX channel index 2267 * Description: 2268 * This starts a TX DMA channel 2269 */ 2270 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2271 { 2272 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2273 stmmac_start_tx(priv, priv->ioaddr, chan); 2274 } 2275 2276 /** 2277 * stmmac_stop_rx_dma - stop RX DMA channel 2278 * @priv: driver private structure 2279 * @chan: RX channel index 2280 * Description: 2281 * This stops a RX DMA channel 2282 */ 2283 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2284 { 2285 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2286 stmmac_stop_rx(priv, priv->ioaddr, chan); 2287 } 2288 2289 /** 2290 * stmmac_stop_tx_dma - stop TX DMA channel 2291 * @priv: driver private structure 2292 * @chan: TX channel index 2293 * Description: 2294 * This stops a TX DMA channel 2295 */ 2296 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2297 { 2298 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2299 stmmac_stop_tx(priv, priv->ioaddr, chan); 2300 } 2301 2302 static void stmmac_enable_all_dma_irq(struct stmmac_priv *priv) 2303 { 2304 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2305 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2306 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2307 u32 chan; 2308 2309 for (chan = 0; chan < dma_csr_ch; chan++) { 2310 struct stmmac_channel *ch = &priv->channel[chan]; 2311 unsigned long flags; 2312 2313 spin_lock_irqsave(&ch->lock, flags); 2314 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2315 spin_unlock_irqrestore(&ch->lock, flags); 2316 } 2317 } 2318 2319 /** 2320 * stmmac_start_all_dma - start all RX and TX DMA channels 2321 * @priv: driver private structure 2322 * Description: 2323 * This starts all the RX and TX DMA channels 2324 */ 2325 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2326 { 2327 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2328 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2329 u32 chan = 0; 2330 2331 for (chan = 0; chan < rx_channels_count; chan++) 2332 stmmac_start_rx_dma(priv, chan); 2333 2334 for (chan = 0; chan < tx_channels_count; chan++) 2335 stmmac_start_tx_dma(priv, chan); 2336 } 2337 2338 /** 2339 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2340 * @priv: driver private structure 2341 * Description: 2342 * This stops the RX and TX DMA channels 2343 */ 2344 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2345 { 2346 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2347 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2348 u32 chan = 0; 2349 2350 for (chan = 0; chan < rx_channels_count; chan++) 2351 stmmac_stop_rx_dma(priv, chan); 2352 2353 for (chan = 0; chan < tx_channels_count; chan++) 2354 stmmac_stop_tx_dma(priv, chan); 2355 } 2356 2357 /** 2358 * stmmac_dma_operation_mode - HW DMA operation mode 2359 * @priv: driver private structure 2360 * Description: it is used for configuring the DMA operation mode register in 2361 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2362 */ 2363 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2364 { 2365 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2366 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2367 int rxfifosz = priv->plat->rx_fifo_size; 2368 int txfifosz = priv->plat->tx_fifo_size; 2369 u32 txmode = 0; 2370 u32 rxmode = 0; 2371 u32 chan = 0; 2372 u8 qmode = 0; 2373 2374 if (rxfifosz == 0) 2375 rxfifosz = priv->dma_cap.rx_fifo_size; 2376 if (txfifosz == 0) 2377 txfifosz = priv->dma_cap.tx_fifo_size; 2378 2379 /* Adjust for real per queue fifo size */ 2380 rxfifosz /= rx_channels_count; 2381 txfifosz /= tx_channels_count; 2382 2383 if (priv->plat->force_thresh_dma_mode) { 2384 txmode = tc; 2385 rxmode = tc; 2386 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2387 /* 2388 * In case of GMAC, SF mode can be enabled 2389 * to perform the TX COE in HW. This depends on: 2390 * 1) TX COE if actually supported 2391 * 2) There is no bugged Jumbo frame support 2392 * that needs to not insert csum in the TDES. 2393 */ 2394 txmode = SF_DMA_MODE; 2395 rxmode = SF_DMA_MODE; 2396 priv->xstats.threshold = SF_DMA_MODE; 2397 } else { 2398 txmode = tc; 2399 rxmode = SF_DMA_MODE; 2400 } 2401 2402 /* configure all channels */ 2403 for (chan = 0; chan < rx_channels_count; chan++) { 2404 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2405 u32 buf_size; 2406 2407 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2408 2409 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2410 rxfifosz, qmode); 2411 2412 if (rx_q->xsk_pool) { 2413 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2414 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2415 buf_size, 2416 chan); 2417 } else { 2418 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2419 priv->dma_conf.dma_buf_sz, 2420 chan); 2421 } 2422 } 2423 2424 for (chan = 0; chan < tx_channels_count; chan++) { 2425 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2426 2427 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2428 txfifosz, qmode); 2429 } 2430 } 2431 2432 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2433 { 2434 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2435 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2436 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2437 unsigned int entry = tx_q->cur_tx; 2438 struct dma_desc *tx_desc = NULL; 2439 struct xdp_desc xdp_desc; 2440 bool work_done = true; 2441 u32 tx_set_ic_bit = 0; 2442 unsigned long flags; 2443 2444 /* Avoids TX time-out as we are sharing with slow path */ 2445 txq_trans_cond_update(nq); 2446 2447 budget = min(budget, stmmac_tx_avail(priv, queue)); 2448 2449 while (budget-- > 0) { 2450 dma_addr_t dma_addr; 2451 bool set_ic; 2452 2453 /* We are sharing with slow path and stop XSK TX desc submission when 2454 * available TX ring is less than threshold. 2455 */ 2456 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2457 !netif_carrier_ok(priv->dev)) { 2458 work_done = false; 2459 break; 2460 } 2461 2462 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2463 break; 2464 2465 if (likely(priv->extend_desc)) 2466 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2467 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2468 tx_desc = &tx_q->dma_entx[entry].basic; 2469 else 2470 tx_desc = tx_q->dma_tx + entry; 2471 2472 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2473 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2474 2475 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2476 2477 /* To return XDP buffer to XSK pool, we simple call 2478 * xsk_tx_completed(), so we don't need to fill up 2479 * 'buf' and 'xdpf'. 2480 */ 2481 tx_q->tx_skbuff_dma[entry].buf = 0; 2482 tx_q->xdpf[entry] = NULL; 2483 2484 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2485 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2486 tx_q->tx_skbuff_dma[entry].last_segment = true; 2487 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2488 2489 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2490 2491 tx_q->tx_count_frames++; 2492 2493 if (!priv->tx_coal_frames[queue]) 2494 set_ic = false; 2495 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2496 set_ic = true; 2497 else 2498 set_ic = false; 2499 2500 if (set_ic) { 2501 tx_q->tx_count_frames = 0; 2502 stmmac_set_tx_ic(priv, tx_desc); 2503 tx_set_ic_bit++; 2504 } 2505 2506 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2507 true, priv->mode, true, true, 2508 xdp_desc.len); 2509 2510 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2511 2512 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 2513 entry = tx_q->cur_tx; 2514 } 2515 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 2516 tx_q->txq_stats.tx_set_ic_bit += tx_set_ic_bit; 2517 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 2518 2519 if (tx_desc) { 2520 stmmac_flush_tx_descriptors(priv, queue); 2521 xsk_tx_release(pool); 2522 } 2523 2524 /* Return true if all of the 3 conditions are met 2525 * a) TX Budget is still available 2526 * b) work_done = true when XSK TX desc peek is empty (no more 2527 * pending XSK TX for transmission) 2528 */ 2529 return !!budget && work_done; 2530 } 2531 2532 static void stmmac_bump_dma_threshold(struct stmmac_priv *priv, u32 chan) 2533 { 2534 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && tc <= 256) { 2535 tc += 64; 2536 2537 if (priv->plat->force_thresh_dma_mode) 2538 stmmac_set_dma_operation_mode(priv, tc, tc, chan); 2539 else 2540 stmmac_set_dma_operation_mode(priv, tc, SF_DMA_MODE, 2541 chan); 2542 2543 priv->xstats.threshold = tc; 2544 } 2545 } 2546 2547 /** 2548 * stmmac_tx_clean - to manage the transmission completion 2549 * @priv: driver private structure 2550 * @budget: napi budget limiting this functions packet handling 2551 * @queue: TX queue index 2552 * Description: it reclaims the transmit resources after transmission completes. 2553 */ 2554 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2555 { 2556 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 2557 unsigned int bytes_compl = 0, pkts_compl = 0; 2558 unsigned int entry, xmits = 0, count = 0; 2559 u32 tx_packets = 0, tx_errors = 0; 2560 unsigned long flags; 2561 2562 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2563 2564 tx_q->xsk_frames_done = 0; 2565 2566 entry = tx_q->dirty_tx; 2567 2568 /* Try to clean all TX complete frame in 1 shot */ 2569 while ((entry != tx_q->cur_tx) && count < priv->dma_conf.dma_tx_size) { 2570 struct xdp_frame *xdpf; 2571 struct sk_buff *skb; 2572 struct dma_desc *p; 2573 int status; 2574 2575 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2576 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2577 xdpf = tx_q->xdpf[entry]; 2578 skb = NULL; 2579 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2580 xdpf = NULL; 2581 skb = tx_q->tx_skbuff[entry]; 2582 } else { 2583 xdpf = NULL; 2584 skb = NULL; 2585 } 2586 2587 if (priv->extend_desc) 2588 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2589 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2590 p = &tx_q->dma_entx[entry].basic; 2591 else 2592 p = tx_q->dma_tx + entry; 2593 2594 status = stmmac_tx_status(priv, &priv->xstats, p, priv->ioaddr); 2595 /* Check if the descriptor is owned by the DMA */ 2596 if (unlikely(status & tx_dma_own)) 2597 break; 2598 2599 count++; 2600 2601 /* Make sure descriptor fields are read after reading 2602 * the own bit. 2603 */ 2604 dma_rmb(); 2605 2606 /* Just consider the last segment and ...*/ 2607 if (likely(!(status & tx_not_ls))) { 2608 /* ... verify the status error condition */ 2609 if (unlikely(status & tx_err)) { 2610 tx_errors++; 2611 if (unlikely(status & tx_err_bump_tc)) 2612 stmmac_bump_dma_threshold(priv, queue); 2613 } else { 2614 tx_packets++; 2615 } 2616 if (skb) 2617 stmmac_get_tx_hwtstamp(priv, p, skb); 2618 } 2619 2620 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2621 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2622 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2623 dma_unmap_page(priv->device, 2624 tx_q->tx_skbuff_dma[entry].buf, 2625 tx_q->tx_skbuff_dma[entry].len, 2626 DMA_TO_DEVICE); 2627 else 2628 dma_unmap_single(priv->device, 2629 tx_q->tx_skbuff_dma[entry].buf, 2630 tx_q->tx_skbuff_dma[entry].len, 2631 DMA_TO_DEVICE); 2632 tx_q->tx_skbuff_dma[entry].buf = 0; 2633 tx_q->tx_skbuff_dma[entry].len = 0; 2634 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2635 } 2636 2637 stmmac_clean_desc3(priv, tx_q, p); 2638 2639 tx_q->tx_skbuff_dma[entry].last_segment = false; 2640 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2641 2642 if (xdpf && 2643 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2644 xdp_return_frame_rx_napi(xdpf); 2645 tx_q->xdpf[entry] = NULL; 2646 } 2647 2648 if (xdpf && 2649 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2650 xdp_return_frame(xdpf); 2651 tx_q->xdpf[entry] = NULL; 2652 } 2653 2654 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2655 tx_q->xsk_frames_done++; 2656 2657 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2658 if (likely(skb)) { 2659 pkts_compl++; 2660 bytes_compl += skb->len; 2661 dev_consume_skb_any(skb); 2662 tx_q->tx_skbuff[entry] = NULL; 2663 } 2664 } 2665 2666 stmmac_release_tx_desc(priv, p, priv->mode); 2667 2668 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 2669 } 2670 tx_q->dirty_tx = entry; 2671 2672 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2673 pkts_compl, bytes_compl); 2674 2675 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2676 queue))) && 2677 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2678 2679 netif_dbg(priv, tx_done, priv->dev, 2680 "%s: restart transmit\n", __func__); 2681 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2682 } 2683 2684 if (tx_q->xsk_pool) { 2685 bool work_done; 2686 2687 if (tx_q->xsk_frames_done) 2688 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2689 2690 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2691 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2692 2693 /* For XSK TX, we try to send as many as possible. 2694 * If XSK work done (XSK TX desc empty and budget still 2695 * available), return "budget - 1" to reenable TX IRQ. 2696 * Else, return "budget" to make NAPI continue polling. 2697 */ 2698 work_done = stmmac_xdp_xmit_zc(priv, queue, 2699 STMMAC_XSK_TX_BUDGET_MAX); 2700 if (work_done) 2701 xmits = budget - 1; 2702 else 2703 xmits = budget; 2704 } 2705 2706 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2707 priv->eee_sw_timer_en) { 2708 if (stmmac_enable_eee_mode(priv)) 2709 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2710 } 2711 2712 /* We still have pending packets, let's call for a new scheduling */ 2713 if (tx_q->dirty_tx != tx_q->cur_tx) 2714 hrtimer_start(&tx_q->txtimer, 2715 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2716 HRTIMER_MODE_REL); 2717 2718 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 2719 tx_q->txq_stats.tx_packets += tx_packets; 2720 tx_q->txq_stats.tx_pkt_n += tx_packets; 2721 tx_q->txq_stats.tx_clean++; 2722 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 2723 2724 priv->xstats.tx_errors += tx_errors; 2725 2726 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2727 2728 /* Combine decisions from TX clean and XSK TX */ 2729 return max(count, xmits); 2730 } 2731 2732 /** 2733 * stmmac_tx_err - to manage the tx error 2734 * @priv: driver private structure 2735 * @chan: channel index 2736 * Description: it cleans the descriptors and restarts the transmission 2737 * in case of transmission errors. 2738 */ 2739 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2740 { 2741 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2742 2743 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2744 2745 stmmac_stop_tx_dma(priv, chan); 2746 dma_free_tx_skbufs(priv, &priv->dma_conf, chan); 2747 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, chan); 2748 stmmac_reset_tx_queue(priv, chan); 2749 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2750 tx_q->dma_tx_phy, chan); 2751 stmmac_start_tx_dma(priv, chan); 2752 2753 priv->xstats.tx_errors++; 2754 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2755 } 2756 2757 /** 2758 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2759 * @priv: driver private structure 2760 * @txmode: TX operating mode 2761 * @rxmode: RX operating mode 2762 * @chan: channel index 2763 * Description: it is used for configuring of the DMA operation mode in 2764 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2765 * mode. 2766 */ 2767 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2768 u32 rxmode, u32 chan) 2769 { 2770 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2771 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2772 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2773 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2774 int rxfifosz = priv->plat->rx_fifo_size; 2775 int txfifosz = priv->plat->tx_fifo_size; 2776 2777 if (rxfifosz == 0) 2778 rxfifosz = priv->dma_cap.rx_fifo_size; 2779 if (txfifosz == 0) 2780 txfifosz = priv->dma_cap.tx_fifo_size; 2781 2782 /* Adjust for real per queue fifo size */ 2783 rxfifosz /= rx_channels_count; 2784 txfifosz /= tx_channels_count; 2785 2786 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2787 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2788 } 2789 2790 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2791 { 2792 int ret; 2793 2794 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2795 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2796 if (ret && (ret != -EINVAL)) { 2797 stmmac_global_err(priv); 2798 return true; 2799 } 2800 2801 return false; 2802 } 2803 2804 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2805 { 2806 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2807 &priv->xstats, chan, dir); 2808 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[chan]; 2809 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 2810 struct stmmac_channel *ch = &priv->channel[chan]; 2811 struct napi_struct *rx_napi; 2812 struct napi_struct *tx_napi; 2813 unsigned long flags; 2814 2815 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2816 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2817 2818 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2819 if (napi_schedule_prep(rx_napi)) { 2820 spin_lock_irqsave(&ch->lock, flags); 2821 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2822 spin_unlock_irqrestore(&ch->lock, flags); 2823 __napi_schedule(rx_napi); 2824 } 2825 } 2826 2827 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2828 if (napi_schedule_prep(tx_napi)) { 2829 spin_lock_irqsave(&ch->lock, flags); 2830 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2831 spin_unlock_irqrestore(&ch->lock, flags); 2832 __napi_schedule(tx_napi); 2833 } 2834 } 2835 2836 return status; 2837 } 2838 2839 /** 2840 * stmmac_dma_interrupt - DMA ISR 2841 * @priv: driver private structure 2842 * Description: this is the DMA ISR. It is called by the main ISR. 2843 * It calls the dwmac dma routine and schedule poll method in case of some 2844 * work can be done. 2845 */ 2846 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2847 { 2848 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2849 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2850 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2851 tx_channel_count : rx_channel_count; 2852 u32 chan; 2853 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2854 2855 /* Make sure we never check beyond our status buffer. */ 2856 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2857 channels_to_check = ARRAY_SIZE(status); 2858 2859 for (chan = 0; chan < channels_to_check; chan++) 2860 status[chan] = stmmac_napi_check(priv, chan, 2861 DMA_DIR_RXTX); 2862 2863 for (chan = 0; chan < tx_channel_count; chan++) { 2864 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2865 /* Try to bump up the dma threshold on this failure */ 2866 stmmac_bump_dma_threshold(priv, chan); 2867 } else if (unlikely(status[chan] == tx_hard_error)) { 2868 stmmac_tx_err(priv, chan); 2869 } 2870 } 2871 } 2872 2873 /** 2874 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2875 * @priv: driver private structure 2876 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2877 */ 2878 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2879 { 2880 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2881 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2882 2883 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2884 2885 if (priv->dma_cap.rmon) { 2886 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2887 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2888 } else 2889 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2890 } 2891 2892 /** 2893 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2894 * @priv: driver private structure 2895 * Description: 2896 * new GMAC chip generations have a new register to indicate the 2897 * presence of the optional feature/functions. 2898 * This can be also used to override the value passed through the 2899 * platform and necessary for old MAC10/100 and GMAC chips. 2900 */ 2901 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2902 { 2903 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2904 } 2905 2906 /** 2907 * stmmac_check_ether_addr - check if the MAC addr is valid 2908 * @priv: driver private structure 2909 * Description: 2910 * it is to verify if the MAC address is valid, in case of failures it 2911 * generates a random MAC address 2912 */ 2913 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2914 { 2915 u8 addr[ETH_ALEN]; 2916 2917 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2918 stmmac_get_umac_addr(priv, priv->hw, addr, 0); 2919 if (is_valid_ether_addr(addr)) 2920 eth_hw_addr_set(priv->dev, addr); 2921 else 2922 eth_hw_addr_random(priv->dev); 2923 dev_info(priv->device, "device MAC address %pM\n", 2924 priv->dev->dev_addr); 2925 } 2926 } 2927 2928 /** 2929 * stmmac_init_dma_engine - DMA init. 2930 * @priv: driver private structure 2931 * Description: 2932 * It inits the DMA invoking the specific MAC/GMAC callback. 2933 * Some DMA parameters can be passed from the platform; 2934 * in case of these are not passed a default is kept for the MAC or GMAC. 2935 */ 2936 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2937 { 2938 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2939 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2940 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2941 struct stmmac_rx_queue *rx_q; 2942 struct stmmac_tx_queue *tx_q; 2943 u32 chan = 0; 2944 int atds = 0; 2945 int ret = 0; 2946 2947 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2948 dev_err(priv->device, "Invalid DMA configuration\n"); 2949 return -EINVAL; 2950 } 2951 2952 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2953 atds = 1; 2954 2955 ret = stmmac_reset(priv, priv->ioaddr); 2956 if (ret) { 2957 dev_err(priv->device, "Failed to reset the dma\n"); 2958 return ret; 2959 } 2960 2961 /* DMA Configuration */ 2962 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2963 2964 if (priv->plat->axi) 2965 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2966 2967 /* DMA CSR Channel configuration */ 2968 for (chan = 0; chan < dma_csr_ch; chan++) { 2969 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2970 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 2971 } 2972 2973 /* DMA RX Channel Configuration */ 2974 for (chan = 0; chan < rx_channels_count; chan++) { 2975 rx_q = &priv->dma_conf.rx_queue[chan]; 2976 2977 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2978 rx_q->dma_rx_phy, chan); 2979 2980 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2981 (rx_q->buf_alloc_num * 2982 sizeof(struct dma_desc)); 2983 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2984 rx_q->rx_tail_addr, chan); 2985 } 2986 2987 /* DMA TX Channel Configuration */ 2988 for (chan = 0; chan < tx_channels_count; chan++) { 2989 tx_q = &priv->dma_conf.tx_queue[chan]; 2990 2991 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2992 tx_q->dma_tx_phy, chan); 2993 2994 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2995 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2996 tx_q->tx_tail_addr, chan); 2997 } 2998 2999 return ret; 3000 } 3001 3002 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 3003 { 3004 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 3005 3006 hrtimer_start(&tx_q->txtimer, 3007 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 3008 HRTIMER_MODE_REL); 3009 } 3010 3011 /** 3012 * stmmac_tx_timer - mitigation sw timer for tx. 3013 * @t: data pointer 3014 * Description: 3015 * This is the timer handler to directly invoke the stmmac_tx_clean. 3016 */ 3017 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 3018 { 3019 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 3020 struct stmmac_priv *priv = tx_q->priv_data; 3021 struct stmmac_channel *ch; 3022 struct napi_struct *napi; 3023 3024 ch = &priv->channel[tx_q->queue_index]; 3025 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 3026 3027 if (likely(napi_schedule_prep(napi))) { 3028 unsigned long flags; 3029 3030 spin_lock_irqsave(&ch->lock, flags); 3031 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 3032 spin_unlock_irqrestore(&ch->lock, flags); 3033 __napi_schedule(napi); 3034 } 3035 3036 return HRTIMER_NORESTART; 3037 } 3038 3039 /** 3040 * stmmac_init_coalesce - init mitigation options. 3041 * @priv: driver private structure 3042 * Description: 3043 * This inits the coalesce parameters: i.e. timer rate, 3044 * timer handler and default threshold used for enabling the 3045 * interrupt on completion bit. 3046 */ 3047 static void stmmac_init_coalesce(struct stmmac_priv *priv) 3048 { 3049 u32 tx_channel_count = priv->plat->tx_queues_to_use; 3050 u32 rx_channel_count = priv->plat->rx_queues_to_use; 3051 u32 chan; 3052 3053 for (chan = 0; chan < tx_channel_count; chan++) { 3054 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3055 3056 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 3057 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 3058 3059 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 3060 tx_q->txtimer.function = stmmac_tx_timer; 3061 } 3062 3063 for (chan = 0; chan < rx_channel_count; chan++) 3064 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 3065 } 3066 3067 static void stmmac_set_rings_length(struct stmmac_priv *priv) 3068 { 3069 u32 rx_channels_count = priv->plat->rx_queues_to_use; 3070 u32 tx_channels_count = priv->plat->tx_queues_to_use; 3071 u32 chan; 3072 3073 /* set TX ring length */ 3074 for (chan = 0; chan < tx_channels_count; chan++) 3075 stmmac_set_tx_ring_len(priv, priv->ioaddr, 3076 (priv->dma_conf.dma_tx_size - 1), chan); 3077 3078 /* set RX ring length */ 3079 for (chan = 0; chan < rx_channels_count; chan++) 3080 stmmac_set_rx_ring_len(priv, priv->ioaddr, 3081 (priv->dma_conf.dma_rx_size - 1), chan); 3082 } 3083 3084 /** 3085 * stmmac_set_tx_queue_weight - Set TX queue weight 3086 * @priv: driver private structure 3087 * Description: It is used for setting TX queues weight 3088 */ 3089 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 3090 { 3091 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3092 u32 weight; 3093 u32 queue; 3094 3095 for (queue = 0; queue < tx_queues_count; queue++) { 3096 weight = priv->plat->tx_queues_cfg[queue].weight; 3097 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 3098 } 3099 } 3100 3101 /** 3102 * stmmac_configure_cbs - Configure CBS in TX queue 3103 * @priv: driver private structure 3104 * Description: It is used for configuring CBS in AVB TX queues 3105 */ 3106 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3107 { 3108 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3109 u32 mode_to_use; 3110 u32 queue; 3111 3112 /* queue 0 is reserved for legacy traffic */ 3113 for (queue = 1; queue < tx_queues_count; queue++) { 3114 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3115 if (mode_to_use == MTL_QUEUE_DCB) 3116 continue; 3117 3118 stmmac_config_cbs(priv, priv->hw, 3119 priv->plat->tx_queues_cfg[queue].send_slope, 3120 priv->plat->tx_queues_cfg[queue].idle_slope, 3121 priv->plat->tx_queues_cfg[queue].high_credit, 3122 priv->plat->tx_queues_cfg[queue].low_credit, 3123 queue); 3124 } 3125 } 3126 3127 /** 3128 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3129 * @priv: driver private structure 3130 * Description: It is used for mapping RX queues to RX dma channels 3131 */ 3132 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3133 { 3134 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3135 u32 queue; 3136 u32 chan; 3137 3138 for (queue = 0; queue < rx_queues_count; queue++) { 3139 chan = priv->plat->rx_queues_cfg[queue].chan; 3140 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3141 } 3142 } 3143 3144 /** 3145 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3146 * @priv: driver private structure 3147 * Description: It is used for configuring the RX Queue Priority 3148 */ 3149 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3150 { 3151 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3152 u32 queue; 3153 u32 prio; 3154 3155 for (queue = 0; queue < rx_queues_count; queue++) { 3156 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3157 continue; 3158 3159 prio = priv->plat->rx_queues_cfg[queue].prio; 3160 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3161 } 3162 } 3163 3164 /** 3165 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3166 * @priv: driver private structure 3167 * Description: It is used for configuring the TX Queue Priority 3168 */ 3169 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3170 { 3171 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3172 u32 queue; 3173 u32 prio; 3174 3175 for (queue = 0; queue < tx_queues_count; queue++) { 3176 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3177 continue; 3178 3179 prio = priv->plat->tx_queues_cfg[queue].prio; 3180 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3181 } 3182 } 3183 3184 /** 3185 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3186 * @priv: driver private structure 3187 * Description: It is used for configuring the RX queue routing 3188 */ 3189 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3190 { 3191 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3192 u32 queue; 3193 u8 packet; 3194 3195 for (queue = 0; queue < rx_queues_count; queue++) { 3196 /* no specific packet type routing specified for the queue */ 3197 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3198 continue; 3199 3200 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3201 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3202 } 3203 } 3204 3205 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3206 { 3207 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3208 priv->rss.enable = false; 3209 return; 3210 } 3211 3212 if (priv->dev->features & NETIF_F_RXHASH) 3213 priv->rss.enable = true; 3214 else 3215 priv->rss.enable = false; 3216 3217 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3218 priv->plat->rx_queues_to_use); 3219 } 3220 3221 /** 3222 * stmmac_mtl_configuration - Configure MTL 3223 * @priv: driver private structure 3224 * Description: It is used for configurring MTL 3225 */ 3226 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3227 { 3228 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3229 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3230 3231 if (tx_queues_count > 1) 3232 stmmac_set_tx_queue_weight(priv); 3233 3234 /* Configure MTL RX algorithms */ 3235 if (rx_queues_count > 1) 3236 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3237 priv->plat->rx_sched_algorithm); 3238 3239 /* Configure MTL TX algorithms */ 3240 if (tx_queues_count > 1) 3241 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3242 priv->plat->tx_sched_algorithm); 3243 3244 /* Configure CBS in AVB TX queues */ 3245 if (tx_queues_count > 1) 3246 stmmac_configure_cbs(priv); 3247 3248 /* Map RX MTL to DMA channels */ 3249 stmmac_rx_queue_dma_chan_map(priv); 3250 3251 /* Enable MAC RX Queues */ 3252 stmmac_mac_enable_rx_queues(priv); 3253 3254 /* Set RX priorities */ 3255 if (rx_queues_count > 1) 3256 stmmac_mac_config_rx_queues_prio(priv); 3257 3258 /* Set TX priorities */ 3259 if (tx_queues_count > 1) 3260 stmmac_mac_config_tx_queues_prio(priv); 3261 3262 /* Set RX routing */ 3263 if (rx_queues_count > 1) 3264 stmmac_mac_config_rx_queues_routing(priv); 3265 3266 /* Receive Side Scaling */ 3267 if (rx_queues_count > 1) 3268 stmmac_mac_config_rss(priv); 3269 } 3270 3271 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3272 { 3273 if (priv->dma_cap.asp) { 3274 netdev_info(priv->dev, "Enabling Safety Features\n"); 3275 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3276 priv->plat->safety_feat_cfg); 3277 } else { 3278 netdev_info(priv->dev, "No Safety Features support found\n"); 3279 } 3280 } 3281 3282 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3283 { 3284 char *name; 3285 3286 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3287 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3288 3289 name = priv->wq_name; 3290 sprintf(name, "%s-fpe", priv->dev->name); 3291 3292 priv->fpe_wq = create_singlethread_workqueue(name); 3293 if (!priv->fpe_wq) { 3294 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3295 3296 return -ENOMEM; 3297 } 3298 netdev_info(priv->dev, "FPE workqueue start"); 3299 3300 return 0; 3301 } 3302 3303 /** 3304 * stmmac_hw_setup - setup mac in a usable state. 3305 * @dev : pointer to the device structure. 3306 * @ptp_register: register PTP if set 3307 * Description: 3308 * this is the main function to setup the HW in a usable state because the 3309 * dma engine is reset, the core registers are configured (e.g. AXI, 3310 * Checksum features, timers). The DMA is ready to start receiving and 3311 * transmitting. 3312 * Return value: 3313 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3314 * file on failure. 3315 */ 3316 static int stmmac_hw_setup(struct net_device *dev, bool ptp_register) 3317 { 3318 struct stmmac_priv *priv = netdev_priv(dev); 3319 u32 rx_cnt = priv->plat->rx_queues_to_use; 3320 u32 tx_cnt = priv->plat->tx_queues_to_use; 3321 bool sph_en; 3322 u32 chan; 3323 int ret; 3324 3325 /* DMA initialization and SW reset */ 3326 ret = stmmac_init_dma_engine(priv); 3327 if (ret < 0) { 3328 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3329 __func__); 3330 return ret; 3331 } 3332 3333 /* Copy the MAC addr into the HW */ 3334 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3335 3336 /* PS and related bits will be programmed according to the speed */ 3337 if (priv->hw->pcs) { 3338 int speed = priv->plat->mac_port_sel_speed; 3339 3340 if ((speed == SPEED_10) || (speed == SPEED_100) || 3341 (speed == SPEED_1000)) { 3342 priv->hw->ps = speed; 3343 } else { 3344 dev_warn(priv->device, "invalid port speed\n"); 3345 priv->hw->ps = 0; 3346 } 3347 } 3348 3349 /* Initialize the MAC Core */ 3350 stmmac_core_init(priv, priv->hw, dev); 3351 3352 /* Initialize MTL*/ 3353 stmmac_mtl_configuration(priv); 3354 3355 /* Initialize Safety Features */ 3356 stmmac_safety_feat_configuration(priv); 3357 3358 ret = stmmac_rx_ipc(priv, priv->hw); 3359 if (!ret) { 3360 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3361 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3362 priv->hw->rx_csum = 0; 3363 } 3364 3365 /* Enable the MAC Rx/Tx */ 3366 stmmac_mac_set(priv, priv->ioaddr, true); 3367 3368 /* Set the HW DMA mode and the COE */ 3369 stmmac_dma_operation_mode(priv); 3370 3371 stmmac_mmc_setup(priv); 3372 3373 if (ptp_register) { 3374 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3375 if (ret < 0) 3376 netdev_warn(priv->dev, 3377 "failed to enable PTP reference clock: %pe\n", 3378 ERR_PTR(ret)); 3379 } 3380 3381 ret = stmmac_init_ptp(priv); 3382 if (ret == -EOPNOTSUPP) 3383 netdev_info(priv->dev, "PTP not supported by HW\n"); 3384 else if (ret) 3385 netdev_warn(priv->dev, "PTP init failed\n"); 3386 else if (ptp_register) 3387 stmmac_ptp_register(priv); 3388 3389 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3390 3391 /* Convert the timer from msec to usec */ 3392 if (!priv->tx_lpi_timer) 3393 priv->tx_lpi_timer = eee_timer * 1000; 3394 3395 if (priv->use_riwt) { 3396 u32 queue; 3397 3398 for (queue = 0; queue < rx_cnt; queue++) { 3399 if (!priv->rx_riwt[queue]) 3400 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3401 3402 stmmac_rx_watchdog(priv, priv->ioaddr, 3403 priv->rx_riwt[queue], queue); 3404 } 3405 } 3406 3407 if (priv->hw->pcs) 3408 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3409 3410 /* set TX and RX rings length */ 3411 stmmac_set_rings_length(priv); 3412 3413 /* Enable TSO */ 3414 if (priv->tso) { 3415 for (chan = 0; chan < tx_cnt; chan++) { 3416 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3417 3418 /* TSO and TBS cannot co-exist */ 3419 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3420 continue; 3421 3422 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3423 } 3424 } 3425 3426 /* Enable Split Header */ 3427 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3428 for (chan = 0; chan < rx_cnt; chan++) 3429 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3430 3431 3432 /* VLAN Tag Insertion */ 3433 if (priv->dma_cap.vlins) 3434 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3435 3436 /* TBS */ 3437 for (chan = 0; chan < tx_cnt; chan++) { 3438 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[chan]; 3439 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3440 3441 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3442 } 3443 3444 /* Configure real RX and TX queues */ 3445 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3446 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3447 3448 /* Start the ball rolling... */ 3449 stmmac_start_all_dma(priv); 3450 3451 if (priv->dma_cap.fpesel) { 3452 stmmac_fpe_start_wq(priv); 3453 3454 if (priv->plat->fpe_cfg->enable) 3455 stmmac_fpe_handshake(priv, true); 3456 } 3457 3458 return 0; 3459 } 3460 3461 static void stmmac_hw_teardown(struct net_device *dev) 3462 { 3463 struct stmmac_priv *priv = netdev_priv(dev); 3464 3465 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3466 } 3467 3468 static void stmmac_free_irq(struct net_device *dev, 3469 enum request_irq_err irq_err, int irq_idx) 3470 { 3471 struct stmmac_priv *priv = netdev_priv(dev); 3472 int j; 3473 3474 switch (irq_err) { 3475 case REQ_IRQ_ERR_ALL: 3476 irq_idx = priv->plat->tx_queues_to_use; 3477 fallthrough; 3478 case REQ_IRQ_ERR_TX: 3479 for (j = irq_idx - 1; j >= 0; j--) { 3480 if (priv->tx_irq[j] > 0) { 3481 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3482 free_irq(priv->tx_irq[j], &priv->dma_conf.tx_queue[j]); 3483 } 3484 } 3485 irq_idx = priv->plat->rx_queues_to_use; 3486 fallthrough; 3487 case REQ_IRQ_ERR_RX: 3488 for (j = irq_idx - 1; j >= 0; j--) { 3489 if (priv->rx_irq[j] > 0) { 3490 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3491 free_irq(priv->rx_irq[j], &priv->dma_conf.rx_queue[j]); 3492 } 3493 } 3494 3495 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3496 free_irq(priv->sfty_ue_irq, dev); 3497 fallthrough; 3498 case REQ_IRQ_ERR_SFTY_UE: 3499 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3500 free_irq(priv->sfty_ce_irq, dev); 3501 fallthrough; 3502 case REQ_IRQ_ERR_SFTY_CE: 3503 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3504 free_irq(priv->lpi_irq, dev); 3505 fallthrough; 3506 case REQ_IRQ_ERR_LPI: 3507 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3508 free_irq(priv->wol_irq, dev); 3509 fallthrough; 3510 case REQ_IRQ_ERR_WOL: 3511 free_irq(dev->irq, dev); 3512 fallthrough; 3513 case REQ_IRQ_ERR_MAC: 3514 case REQ_IRQ_ERR_NO: 3515 /* If MAC IRQ request error, no more IRQ to free */ 3516 break; 3517 } 3518 } 3519 3520 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3521 { 3522 struct stmmac_priv *priv = netdev_priv(dev); 3523 enum request_irq_err irq_err; 3524 cpumask_t cpu_mask; 3525 int irq_idx = 0; 3526 char *int_name; 3527 int ret; 3528 int i; 3529 3530 /* For common interrupt */ 3531 int_name = priv->int_name_mac; 3532 sprintf(int_name, "%s:%s", dev->name, "mac"); 3533 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3534 0, int_name, dev); 3535 if (unlikely(ret < 0)) { 3536 netdev_err(priv->dev, 3537 "%s: alloc mac MSI %d (error: %d)\n", 3538 __func__, dev->irq, ret); 3539 irq_err = REQ_IRQ_ERR_MAC; 3540 goto irq_error; 3541 } 3542 3543 /* Request the Wake IRQ in case of another line 3544 * is used for WoL 3545 */ 3546 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3547 int_name = priv->int_name_wol; 3548 sprintf(int_name, "%s:%s", dev->name, "wol"); 3549 ret = request_irq(priv->wol_irq, 3550 stmmac_mac_interrupt, 3551 0, int_name, dev); 3552 if (unlikely(ret < 0)) { 3553 netdev_err(priv->dev, 3554 "%s: alloc wol MSI %d (error: %d)\n", 3555 __func__, priv->wol_irq, ret); 3556 irq_err = REQ_IRQ_ERR_WOL; 3557 goto irq_error; 3558 } 3559 } 3560 3561 /* Request the LPI IRQ in case of another line 3562 * is used for LPI 3563 */ 3564 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3565 int_name = priv->int_name_lpi; 3566 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3567 ret = request_irq(priv->lpi_irq, 3568 stmmac_mac_interrupt, 3569 0, int_name, dev); 3570 if (unlikely(ret < 0)) { 3571 netdev_err(priv->dev, 3572 "%s: alloc lpi MSI %d (error: %d)\n", 3573 __func__, priv->lpi_irq, ret); 3574 irq_err = REQ_IRQ_ERR_LPI; 3575 goto irq_error; 3576 } 3577 } 3578 3579 /* Request the Safety Feature Correctible Error line in 3580 * case of another line is used 3581 */ 3582 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3583 int_name = priv->int_name_sfty_ce; 3584 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3585 ret = request_irq(priv->sfty_ce_irq, 3586 stmmac_safety_interrupt, 3587 0, int_name, dev); 3588 if (unlikely(ret < 0)) { 3589 netdev_err(priv->dev, 3590 "%s: alloc sfty ce MSI %d (error: %d)\n", 3591 __func__, priv->sfty_ce_irq, ret); 3592 irq_err = REQ_IRQ_ERR_SFTY_CE; 3593 goto irq_error; 3594 } 3595 } 3596 3597 /* Request the Safety Feature Uncorrectible Error line in 3598 * case of another line is used 3599 */ 3600 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3601 int_name = priv->int_name_sfty_ue; 3602 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3603 ret = request_irq(priv->sfty_ue_irq, 3604 stmmac_safety_interrupt, 3605 0, int_name, dev); 3606 if (unlikely(ret < 0)) { 3607 netdev_err(priv->dev, 3608 "%s: alloc sfty ue MSI %d (error: %d)\n", 3609 __func__, priv->sfty_ue_irq, ret); 3610 irq_err = REQ_IRQ_ERR_SFTY_UE; 3611 goto irq_error; 3612 } 3613 } 3614 3615 /* Request Rx MSI irq */ 3616 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3617 if (i >= MTL_MAX_RX_QUEUES) 3618 break; 3619 if (priv->rx_irq[i] == 0) 3620 continue; 3621 3622 int_name = priv->int_name_rx_irq[i]; 3623 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3624 ret = request_irq(priv->rx_irq[i], 3625 stmmac_msi_intr_rx, 3626 0, int_name, &priv->dma_conf.rx_queue[i]); 3627 if (unlikely(ret < 0)) { 3628 netdev_err(priv->dev, 3629 "%s: alloc rx-%d MSI %d (error: %d)\n", 3630 __func__, i, priv->rx_irq[i], ret); 3631 irq_err = REQ_IRQ_ERR_RX; 3632 irq_idx = i; 3633 goto irq_error; 3634 } 3635 cpumask_clear(&cpu_mask); 3636 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3637 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3638 } 3639 3640 /* Request Tx MSI irq */ 3641 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3642 if (i >= MTL_MAX_TX_QUEUES) 3643 break; 3644 if (priv->tx_irq[i] == 0) 3645 continue; 3646 3647 int_name = priv->int_name_tx_irq[i]; 3648 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3649 ret = request_irq(priv->tx_irq[i], 3650 stmmac_msi_intr_tx, 3651 0, int_name, &priv->dma_conf.tx_queue[i]); 3652 if (unlikely(ret < 0)) { 3653 netdev_err(priv->dev, 3654 "%s: alloc tx-%d MSI %d (error: %d)\n", 3655 __func__, i, priv->tx_irq[i], ret); 3656 irq_err = REQ_IRQ_ERR_TX; 3657 irq_idx = i; 3658 goto irq_error; 3659 } 3660 cpumask_clear(&cpu_mask); 3661 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3662 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3663 } 3664 3665 return 0; 3666 3667 irq_error: 3668 stmmac_free_irq(dev, irq_err, irq_idx); 3669 return ret; 3670 } 3671 3672 static int stmmac_request_irq_single(struct net_device *dev) 3673 { 3674 struct stmmac_priv *priv = netdev_priv(dev); 3675 enum request_irq_err irq_err; 3676 int ret; 3677 3678 ret = request_irq(dev->irq, stmmac_interrupt, 3679 IRQF_SHARED, dev->name, dev); 3680 if (unlikely(ret < 0)) { 3681 netdev_err(priv->dev, 3682 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3683 __func__, dev->irq, ret); 3684 irq_err = REQ_IRQ_ERR_MAC; 3685 goto irq_error; 3686 } 3687 3688 /* Request the Wake IRQ in case of another line 3689 * is used for WoL 3690 */ 3691 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3692 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3693 IRQF_SHARED, dev->name, dev); 3694 if (unlikely(ret < 0)) { 3695 netdev_err(priv->dev, 3696 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3697 __func__, priv->wol_irq, ret); 3698 irq_err = REQ_IRQ_ERR_WOL; 3699 goto irq_error; 3700 } 3701 } 3702 3703 /* Request the IRQ lines */ 3704 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3705 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3706 IRQF_SHARED, dev->name, dev); 3707 if (unlikely(ret < 0)) { 3708 netdev_err(priv->dev, 3709 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3710 __func__, priv->lpi_irq, ret); 3711 irq_err = REQ_IRQ_ERR_LPI; 3712 goto irq_error; 3713 } 3714 } 3715 3716 return 0; 3717 3718 irq_error: 3719 stmmac_free_irq(dev, irq_err, 0); 3720 return ret; 3721 } 3722 3723 static int stmmac_request_irq(struct net_device *dev) 3724 { 3725 struct stmmac_priv *priv = netdev_priv(dev); 3726 int ret; 3727 3728 /* Request the IRQ lines */ 3729 if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN) 3730 ret = stmmac_request_irq_multi_msi(dev); 3731 else 3732 ret = stmmac_request_irq_single(dev); 3733 3734 return ret; 3735 } 3736 3737 /** 3738 * stmmac_setup_dma_desc - Generate a dma_conf and allocate DMA queue 3739 * @priv: driver private structure 3740 * @mtu: MTU to setup the dma queue and buf with 3741 * Description: Allocate and generate a dma_conf based on the provided MTU. 3742 * Allocate the Tx/Rx DMA queue and init them. 3743 * Return value: 3744 * the dma_conf allocated struct on success and an appropriate ERR_PTR on failure. 3745 */ 3746 static struct stmmac_dma_conf * 3747 stmmac_setup_dma_desc(struct stmmac_priv *priv, unsigned int mtu) 3748 { 3749 struct stmmac_dma_conf *dma_conf; 3750 int chan, bfsize, ret; 3751 3752 dma_conf = kzalloc(sizeof(*dma_conf), GFP_KERNEL); 3753 if (!dma_conf) { 3754 netdev_err(priv->dev, "%s: DMA conf allocation failed\n", 3755 __func__); 3756 return ERR_PTR(-ENOMEM); 3757 } 3758 3759 bfsize = stmmac_set_16kib_bfsize(priv, mtu); 3760 if (bfsize < 0) 3761 bfsize = 0; 3762 3763 if (bfsize < BUF_SIZE_16KiB) 3764 bfsize = stmmac_set_bfsize(mtu, 0); 3765 3766 dma_conf->dma_buf_sz = bfsize; 3767 /* Chose the tx/rx size from the already defined one in the 3768 * priv struct. (if defined) 3769 */ 3770 dma_conf->dma_tx_size = priv->dma_conf.dma_tx_size; 3771 dma_conf->dma_rx_size = priv->dma_conf.dma_rx_size; 3772 3773 if (!dma_conf->dma_tx_size) 3774 dma_conf->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3775 if (!dma_conf->dma_rx_size) 3776 dma_conf->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3777 3778 /* Earlier check for TBS */ 3779 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3780 struct stmmac_tx_queue *tx_q = &dma_conf->tx_queue[chan]; 3781 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3782 3783 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3784 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3785 } 3786 3787 ret = alloc_dma_desc_resources(priv, dma_conf); 3788 if (ret < 0) { 3789 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3790 __func__); 3791 goto alloc_error; 3792 } 3793 3794 ret = init_dma_desc_rings(priv->dev, dma_conf, GFP_KERNEL); 3795 if (ret < 0) { 3796 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3797 __func__); 3798 goto init_error; 3799 } 3800 3801 return dma_conf; 3802 3803 init_error: 3804 free_dma_desc_resources(priv, dma_conf); 3805 alloc_error: 3806 kfree(dma_conf); 3807 return ERR_PTR(ret); 3808 } 3809 3810 /** 3811 * __stmmac_open - open entry point of the driver 3812 * @dev : pointer to the device structure. 3813 * @dma_conf : structure to take the dma data 3814 * Description: 3815 * This function is the open entry point of the driver. 3816 * Return value: 3817 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3818 * file on failure. 3819 */ 3820 static int __stmmac_open(struct net_device *dev, 3821 struct stmmac_dma_conf *dma_conf) 3822 { 3823 struct stmmac_priv *priv = netdev_priv(dev); 3824 int mode = priv->plat->phy_interface; 3825 u32 chan; 3826 int ret; 3827 3828 ret = pm_runtime_resume_and_get(priv->device); 3829 if (ret < 0) 3830 return ret; 3831 3832 if (priv->hw->pcs != STMMAC_PCS_TBI && 3833 priv->hw->pcs != STMMAC_PCS_RTBI && 3834 (!priv->hw->xpcs || 3835 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73) && 3836 !priv->hw->lynx_pcs) { 3837 ret = stmmac_init_phy(dev); 3838 if (ret) { 3839 netdev_err(priv->dev, 3840 "%s: Cannot attach to PHY (error: %d)\n", 3841 __func__, ret); 3842 goto init_phy_error; 3843 } 3844 } 3845 3846 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3847 3848 buf_sz = dma_conf->dma_buf_sz; 3849 memcpy(&priv->dma_conf, dma_conf, sizeof(*dma_conf)); 3850 3851 stmmac_reset_queues_param(priv); 3852 3853 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && 3854 priv->plat->serdes_powerup) { 3855 ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv); 3856 if (ret < 0) { 3857 netdev_err(priv->dev, "%s: Serdes powerup failed\n", 3858 __func__); 3859 goto init_error; 3860 } 3861 } 3862 3863 ret = stmmac_hw_setup(dev, true); 3864 if (ret < 0) { 3865 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3866 goto init_error; 3867 } 3868 3869 stmmac_init_coalesce(priv); 3870 3871 phylink_start(priv->phylink); 3872 /* We may have called phylink_speed_down before */ 3873 phylink_speed_up(priv->phylink); 3874 3875 ret = stmmac_request_irq(dev); 3876 if (ret) 3877 goto irq_error; 3878 3879 stmmac_enable_all_queues(priv); 3880 netif_tx_start_all_queues(priv->dev); 3881 stmmac_enable_all_dma_irq(priv); 3882 3883 return 0; 3884 3885 irq_error: 3886 phylink_stop(priv->phylink); 3887 3888 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3889 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3890 3891 stmmac_hw_teardown(dev); 3892 init_error: 3893 phylink_disconnect_phy(priv->phylink); 3894 init_phy_error: 3895 pm_runtime_put(priv->device); 3896 return ret; 3897 } 3898 3899 static int stmmac_open(struct net_device *dev) 3900 { 3901 struct stmmac_priv *priv = netdev_priv(dev); 3902 struct stmmac_dma_conf *dma_conf; 3903 int ret; 3904 3905 dma_conf = stmmac_setup_dma_desc(priv, dev->mtu); 3906 if (IS_ERR(dma_conf)) 3907 return PTR_ERR(dma_conf); 3908 3909 ret = __stmmac_open(dev, dma_conf); 3910 if (ret) 3911 free_dma_desc_resources(priv, dma_conf); 3912 3913 kfree(dma_conf); 3914 return ret; 3915 } 3916 3917 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3918 { 3919 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3920 3921 if (priv->fpe_wq) 3922 destroy_workqueue(priv->fpe_wq); 3923 3924 netdev_info(priv->dev, "FPE workqueue stop"); 3925 } 3926 3927 /** 3928 * stmmac_release - close entry point of the driver 3929 * @dev : device pointer. 3930 * Description: 3931 * This is the stop entry point of the driver. 3932 */ 3933 static int stmmac_release(struct net_device *dev) 3934 { 3935 struct stmmac_priv *priv = netdev_priv(dev); 3936 u32 chan; 3937 3938 if (device_may_wakeup(priv->device)) 3939 phylink_speed_down(priv->phylink, false); 3940 /* Stop and disconnect the PHY */ 3941 phylink_stop(priv->phylink); 3942 phylink_disconnect_phy(priv->phylink); 3943 3944 stmmac_disable_all_queues(priv); 3945 3946 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3947 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 3948 3949 netif_tx_disable(dev); 3950 3951 /* Free the IRQ lines */ 3952 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3953 3954 if (priv->eee_enabled) { 3955 priv->tx_path_in_lpi_mode = false; 3956 del_timer_sync(&priv->eee_ctrl_timer); 3957 } 3958 3959 /* Stop TX/RX DMA and clear the descriptors */ 3960 stmmac_stop_all_dma(priv); 3961 3962 /* Release and free the Rx/Tx resources */ 3963 free_dma_desc_resources(priv, &priv->dma_conf); 3964 3965 /* Disable the MAC Rx/Tx */ 3966 stmmac_mac_set(priv, priv->ioaddr, false); 3967 3968 /* Powerdown Serdes if there is */ 3969 if (priv->plat->serdes_powerdown) 3970 priv->plat->serdes_powerdown(dev, priv->plat->bsp_priv); 3971 3972 netif_carrier_off(dev); 3973 3974 stmmac_release_ptp(priv); 3975 3976 pm_runtime_put(priv->device); 3977 3978 if (priv->dma_cap.fpesel) 3979 stmmac_fpe_stop_wq(priv); 3980 3981 return 0; 3982 } 3983 3984 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3985 struct stmmac_tx_queue *tx_q) 3986 { 3987 u16 tag = 0x0, inner_tag = 0x0; 3988 u32 inner_type = 0x0; 3989 struct dma_desc *p; 3990 3991 if (!priv->dma_cap.vlins) 3992 return false; 3993 if (!skb_vlan_tag_present(skb)) 3994 return false; 3995 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3996 inner_tag = skb_vlan_tag_get(skb); 3997 inner_type = STMMAC_VLAN_INSERT; 3998 } 3999 4000 tag = skb_vlan_tag_get(skb); 4001 4002 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4003 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 4004 else 4005 p = &tx_q->dma_tx[tx_q->cur_tx]; 4006 4007 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 4008 return false; 4009 4010 stmmac_set_tx_owner(priv, p); 4011 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4012 return true; 4013 } 4014 4015 /** 4016 * stmmac_tso_allocator - close entry point of the driver 4017 * @priv: driver private structure 4018 * @des: buffer start address 4019 * @total_len: total length to fill in descriptors 4020 * @last_segment: condition for the last descriptor 4021 * @queue: TX queue index 4022 * Description: 4023 * This function fills descriptor and request new descriptors according to 4024 * buffer length to fill 4025 */ 4026 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 4027 int total_len, bool last_segment, u32 queue) 4028 { 4029 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4030 struct dma_desc *desc; 4031 u32 buff_size; 4032 int tmp_len; 4033 4034 tmp_len = total_len; 4035 4036 while (tmp_len > 0) { 4037 dma_addr_t curr_addr; 4038 4039 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4040 priv->dma_conf.dma_tx_size); 4041 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4042 4043 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4044 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4045 else 4046 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4047 4048 curr_addr = des + (total_len - tmp_len); 4049 if (priv->dma_cap.addr64 <= 32) 4050 desc->des0 = cpu_to_le32(curr_addr); 4051 else 4052 stmmac_set_desc_addr(priv, desc, curr_addr); 4053 4054 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 4055 TSO_MAX_BUFF_SIZE : tmp_len; 4056 4057 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 4058 0, 1, 4059 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 4060 0, 0); 4061 4062 tmp_len -= TSO_MAX_BUFF_SIZE; 4063 } 4064 } 4065 4066 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 4067 { 4068 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4069 int desc_size; 4070 4071 if (likely(priv->extend_desc)) 4072 desc_size = sizeof(struct dma_extended_desc); 4073 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4074 desc_size = sizeof(struct dma_edesc); 4075 else 4076 desc_size = sizeof(struct dma_desc); 4077 4078 /* The own bit must be the latest setting done when prepare the 4079 * descriptor and then barrier is needed to make sure that 4080 * all is coherent before granting the DMA engine. 4081 */ 4082 wmb(); 4083 4084 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 4085 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 4086 } 4087 4088 /** 4089 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 4090 * @skb : the socket buffer 4091 * @dev : device pointer 4092 * Description: this is the transmit function that is called on TSO frames 4093 * (support available on GMAC4 and newer chips). 4094 * Diagram below show the ring programming in case of TSO frames: 4095 * 4096 * First Descriptor 4097 * -------- 4098 * | DES0 |---> buffer1 = L2/L3/L4 header 4099 * | DES1 |---> TCP Payload (can continue on next descr...) 4100 * | DES2 |---> buffer 1 and 2 len 4101 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 4102 * -------- 4103 * | 4104 * ... 4105 * | 4106 * -------- 4107 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 4108 * | DES1 | --| 4109 * | DES2 | --> buffer 1 and 2 len 4110 * | DES3 | 4111 * -------- 4112 * 4113 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 4114 */ 4115 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 4116 { 4117 struct dma_desc *desc, *first, *mss_desc = NULL; 4118 struct stmmac_priv *priv = netdev_priv(dev); 4119 int nfrags = skb_shinfo(skb)->nr_frags; 4120 u32 queue = skb_get_queue_mapping(skb); 4121 unsigned int first_entry, tx_packets; 4122 int tmp_pay_len = 0, first_tx; 4123 struct stmmac_tx_queue *tx_q; 4124 bool has_vlan, set_ic; 4125 u8 proto_hdr_len, hdr; 4126 unsigned long flags; 4127 u32 pay_len, mss; 4128 dma_addr_t des; 4129 int i; 4130 4131 tx_q = &priv->dma_conf.tx_queue[queue]; 4132 first_tx = tx_q->cur_tx; 4133 4134 /* Compute header lengths */ 4135 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 4136 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 4137 hdr = sizeof(struct udphdr); 4138 } else { 4139 proto_hdr_len = skb_tcp_all_headers(skb); 4140 hdr = tcp_hdrlen(skb); 4141 } 4142 4143 /* Desc availability based on threshold should be enough safe */ 4144 if (unlikely(stmmac_tx_avail(priv, queue) < 4145 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 4146 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4147 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4148 queue)); 4149 /* This is a hard error, log it. */ 4150 netdev_err(priv->dev, 4151 "%s: Tx Ring full when queue awake\n", 4152 __func__); 4153 } 4154 return NETDEV_TX_BUSY; 4155 } 4156 4157 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 4158 4159 mss = skb_shinfo(skb)->gso_size; 4160 4161 /* set new MSS value if needed */ 4162 if (mss != tx_q->mss) { 4163 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4164 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4165 else 4166 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 4167 4168 stmmac_set_mss(priv, mss_desc, mss); 4169 tx_q->mss = mss; 4170 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 4171 priv->dma_conf.dma_tx_size); 4172 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 4173 } 4174 4175 if (netif_msg_tx_queued(priv)) { 4176 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 4177 __func__, hdr, proto_hdr_len, pay_len, mss); 4178 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 4179 skb->data_len); 4180 } 4181 4182 /* Check if VLAN can be inserted by HW */ 4183 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4184 4185 first_entry = tx_q->cur_tx; 4186 WARN_ON(tx_q->tx_skbuff[first_entry]); 4187 4188 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4189 desc = &tx_q->dma_entx[first_entry].basic; 4190 else 4191 desc = &tx_q->dma_tx[first_entry]; 4192 first = desc; 4193 4194 if (has_vlan) 4195 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4196 4197 /* first descriptor: fill Headers on Buf1 */ 4198 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4199 DMA_TO_DEVICE); 4200 if (dma_mapping_error(priv->device, des)) 4201 goto dma_map_err; 4202 4203 tx_q->tx_skbuff_dma[first_entry].buf = des; 4204 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4205 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4206 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4207 4208 if (priv->dma_cap.addr64 <= 32) { 4209 first->des0 = cpu_to_le32(des); 4210 4211 /* Fill start of payload in buff2 of first descriptor */ 4212 if (pay_len) 4213 first->des1 = cpu_to_le32(des + proto_hdr_len); 4214 4215 /* If needed take extra descriptors to fill the remaining payload */ 4216 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4217 } else { 4218 stmmac_set_desc_addr(priv, first, des); 4219 tmp_pay_len = pay_len; 4220 des += proto_hdr_len; 4221 pay_len = 0; 4222 } 4223 4224 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4225 4226 /* Prepare fragments */ 4227 for (i = 0; i < nfrags; i++) { 4228 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4229 4230 des = skb_frag_dma_map(priv->device, frag, 0, 4231 skb_frag_size(frag), 4232 DMA_TO_DEVICE); 4233 if (dma_mapping_error(priv->device, des)) 4234 goto dma_map_err; 4235 4236 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4237 (i == nfrags - 1), queue); 4238 4239 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4240 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4241 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4242 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4243 } 4244 4245 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4246 4247 /* Only the last descriptor gets to point to the skb. */ 4248 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4249 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4250 4251 /* Manage tx mitigation */ 4252 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4253 tx_q->tx_count_frames += tx_packets; 4254 4255 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4256 set_ic = true; 4257 else if (!priv->tx_coal_frames[queue]) 4258 set_ic = false; 4259 else if (tx_packets > priv->tx_coal_frames[queue]) 4260 set_ic = true; 4261 else if ((tx_q->tx_count_frames % 4262 priv->tx_coal_frames[queue]) < tx_packets) 4263 set_ic = true; 4264 else 4265 set_ic = false; 4266 4267 if (set_ic) { 4268 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4269 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4270 else 4271 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4272 4273 tx_q->tx_count_frames = 0; 4274 stmmac_set_tx_ic(priv, desc); 4275 } 4276 4277 /* We've used all descriptors we need for this skb, however, 4278 * advance cur_tx so that it references a fresh descriptor. 4279 * ndo_start_xmit will fill this descriptor the next time it's 4280 * called and stmmac_tx_clean may clean up to this descriptor. 4281 */ 4282 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_conf.dma_tx_size); 4283 4284 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4285 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4286 __func__); 4287 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4288 } 4289 4290 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 4291 tx_q->txq_stats.tx_bytes += skb->len; 4292 tx_q->txq_stats.tx_tso_frames++; 4293 tx_q->txq_stats.tx_tso_nfrags += nfrags; 4294 if (set_ic) 4295 tx_q->txq_stats.tx_set_ic_bit++; 4296 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 4297 4298 if (priv->sarc_type) 4299 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4300 4301 skb_tx_timestamp(skb); 4302 4303 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4304 priv->hwts_tx_en)) { 4305 /* declare that device is doing timestamping */ 4306 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4307 stmmac_enable_tx_timestamp(priv, first); 4308 } 4309 4310 /* Complete the first descriptor before granting the DMA */ 4311 stmmac_prepare_tso_tx_desc(priv, first, 1, 4312 proto_hdr_len, 4313 pay_len, 4314 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4315 hdr / 4, (skb->len - proto_hdr_len)); 4316 4317 /* If context desc is used to change MSS */ 4318 if (mss_desc) { 4319 /* Make sure that first descriptor has been completely 4320 * written, including its own bit. This is because MSS is 4321 * actually before first descriptor, so we need to make 4322 * sure that MSS's own bit is the last thing written. 4323 */ 4324 dma_wmb(); 4325 stmmac_set_tx_owner(priv, mss_desc); 4326 } 4327 4328 if (netif_msg_pktdata(priv)) { 4329 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4330 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4331 tx_q->cur_tx, first, nfrags); 4332 pr_info(">>> frame to be transmitted: "); 4333 print_pkt(skb->data, skb_headlen(skb)); 4334 } 4335 4336 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4337 4338 stmmac_flush_tx_descriptors(priv, queue); 4339 stmmac_tx_timer_arm(priv, queue); 4340 4341 return NETDEV_TX_OK; 4342 4343 dma_map_err: 4344 dev_err(priv->device, "Tx dma map failed\n"); 4345 dev_kfree_skb(skb); 4346 priv->xstats.tx_dropped++; 4347 return NETDEV_TX_OK; 4348 } 4349 4350 /** 4351 * stmmac_xmit - Tx entry point of the driver 4352 * @skb : the socket buffer 4353 * @dev : device pointer 4354 * Description : this is the tx entry point of the driver. 4355 * It programs the chain or the ring and supports oversized frames 4356 * and SG feature. 4357 */ 4358 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4359 { 4360 unsigned int first_entry, tx_packets, enh_desc; 4361 struct stmmac_priv *priv = netdev_priv(dev); 4362 unsigned int nopaged_len = skb_headlen(skb); 4363 int i, csum_insertion = 0, is_jumbo = 0; 4364 u32 queue = skb_get_queue_mapping(skb); 4365 int nfrags = skb_shinfo(skb)->nr_frags; 4366 int gso = skb_shinfo(skb)->gso_type; 4367 struct dma_edesc *tbs_desc = NULL; 4368 struct dma_desc *desc, *first; 4369 struct stmmac_tx_queue *tx_q; 4370 bool has_vlan, set_ic; 4371 int entry, first_tx; 4372 unsigned long flags; 4373 dma_addr_t des; 4374 4375 tx_q = &priv->dma_conf.tx_queue[queue]; 4376 first_tx = tx_q->cur_tx; 4377 4378 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4379 stmmac_disable_eee_mode(priv); 4380 4381 /* Manage oversized TCP frames for GMAC4 device */ 4382 if (skb_is_gso(skb) && priv->tso) { 4383 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4384 return stmmac_tso_xmit(skb, dev); 4385 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4386 return stmmac_tso_xmit(skb, dev); 4387 } 4388 4389 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4390 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4391 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4392 queue)); 4393 /* This is a hard error, log it. */ 4394 netdev_err(priv->dev, 4395 "%s: Tx Ring full when queue awake\n", 4396 __func__); 4397 } 4398 return NETDEV_TX_BUSY; 4399 } 4400 4401 /* Check if VLAN can be inserted by HW */ 4402 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4403 4404 entry = tx_q->cur_tx; 4405 first_entry = entry; 4406 WARN_ON(tx_q->tx_skbuff[first_entry]); 4407 4408 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4409 4410 if (likely(priv->extend_desc)) 4411 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4412 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4413 desc = &tx_q->dma_entx[entry].basic; 4414 else 4415 desc = tx_q->dma_tx + entry; 4416 4417 first = desc; 4418 4419 if (has_vlan) 4420 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4421 4422 enh_desc = priv->plat->enh_desc; 4423 /* To program the descriptors according to the size of the frame */ 4424 if (enh_desc) 4425 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4426 4427 if (unlikely(is_jumbo)) { 4428 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4429 if (unlikely(entry < 0) && (entry != -EINVAL)) 4430 goto dma_map_err; 4431 } 4432 4433 for (i = 0; i < nfrags; i++) { 4434 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4435 int len = skb_frag_size(frag); 4436 bool last_segment = (i == (nfrags - 1)); 4437 4438 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4439 WARN_ON(tx_q->tx_skbuff[entry]); 4440 4441 if (likely(priv->extend_desc)) 4442 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4443 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4444 desc = &tx_q->dma_entx[entry].basic; 4445 else 4446 desc = tx_q->dma_tx + entry; 4447 4448 des = skb_frag_dma_map(priv->device, frag, 0, len, 4449 DMA_TO_DEVICE); 4450 if (dma_mapping_error(priv->device, des)) 4451 goto dma_map_err; /* should reuse desc w/o issues */ 4452 4453 tx_q->tx_skbuff_dma[entry].buf = des; 4454 4455 stmmac_set_desc_addr(priv, desc, des); 4456 4457 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4458 tx_q->tx_skbuff_dma[entry].len = len; 4459 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4460 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4461 4462 /* Prepare the descriptor and set the own bit too */ 4463 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4464 priv->mode, 1, last_segment, skb->len); 4465 } 4466 4467 /* Only the last descriptor gets to point to the skb. */ 4468 tx_q->tx_skbuff[entry] = skb; 4469 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4470 4471 /* According to the coalesce parameter the IC bit for the latest 4472 * segment is reset and the timer re-started to clean the tx status. 4473 * This approach takes care about the fragments: desc is the first 4474 * element in case of no SG. 4475 */ 4476 tx_packets = (entry + 1) - first_tx; 4477 tx_q->tx_count_frames += tx_packets; 4478 4479 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4480 set_ic = true; 4481 else if (!priv->tx_coal_frames[queue]) 4482 set_ic = false; 4483 else if (tx_packets > priv->tx_coal_frames[queue]) 4484 set_ic = true; 4485 else if ((tx_q->tx_count_frames % 4486 priv->tx_coal_frames[queue]) < tx_packets) 4487 set_ic = true; 4488 else 4489 set_ic = false; 4490 4491 if (set_ic) { 4492 if (likely(priv->extend_desc)) 4493 desc = &tx_q->dma_etx[entry].basic; 4494 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4495 desc = &tx_q->dma_entx[entry].basic; 4496 else 4497 desc = &tx_q->dma_tx[entry]; 4498 4499 tx_q->tx_count_frames = 0; 4500 stmmac_set_tx_ic(priv, desc); 4501 } 4502 4503 /* We've used all descriptors we need for this skb, however, 4504 * advance cur_tx so that it references a fresh descriptor. 4505 * ndo_start_xmit will fill this descriptor the next time it's 4506 * called and stmmac_tx_clean may clean up to this descriptor. 4507 */ 4508 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4509 tx_q->cur_tx = entry; 4510 4511 if (netif_msg_pktdata(priv)) { 4512 netdev_dbg(priv->dev, 4513 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4514 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4515 entry, first, nfrags); 4516 4517 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4518 print_pkt(skb->data, skb->len); 4519 } 4520 4521 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4522 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4523 __func__); 4524 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4525 } 4526 4527 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 4528 tx_q->txq_stats.tx_bytes += skb->len; 4529 if (set_ic) 4530 tx_q->txq_stats.tx_set_ic_bit++; 4531 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 4532 4533 if (priv->sarc_type) 4534 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4535 4536 skb_tx_timestamp(skb); 4537 4538 /* Ready to fill the first descriptor and set the OWN bit w/o any 4539 * problems because all the descriptors are actually ready to be 4540 * passed to the DMA engine. 4541 */ 4542 if (likely(!is_jumbo)) { 4543 bool last_segment = (nfrags == 0); 4544 4545 des = dma_map_single(priv->device, skb->data, 4546 nopaged_len, DMA_TO_DEVICE); 4547 if (dma_mapping_error(priv->device, des)) 4548 goto dma_map_err; 4549 4550 tx_q->tx_skbuff_dma[first_entry].buf = des; 4551 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4552 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4553 4554 stmmac_set_desc_addr(priv, first, des); 4555 4556 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4557 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4558 4559 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4560 priv->hwts_tx_en)) { 4561 /* declare that device is doing timestamping */ 4562 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4563 stmmac_enable_tx_timestamp(priv, first); 4564 } 4565 4566 /* Prepare the first descriptor setting the OWN bit too */ 4567 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4568 csum_insertion, priv->mode, 0, last_segment, 4569 skb->len); 4570 } 4571 4572 if (tx_q->tbs & STMMAC_TBS_EN) { 4573 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4574 4575 tbs_desc = &tx_q->dma_entx[first_entry]; 4576 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4577 } 4578 4579 stmmac_set_tx_owner(priv, first); 4580 4581 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4582 4583 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4584 4585 stmmac_flush_tx_descriptors(priv, queue); 4586 stmmac_tx_timer_arm(priv, queue); 4587 4588 return NETDEV_TX_OK; 4589 4590 dma_map_err: 4591 netdev_err(priv->dev, "Tx DMA map failed\n"); 4592 dev_kfree_skb(skb); 4593 priv->xstats.tx_dropped++; 4594 return NETDEV_TX_OK; 4595 } 4596 4597 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4598 { 4599 struct vlan_ethhdr *veth = skb_vlan_eth_hdr(skb); 4600 __be16 vlan_proto = veth->h_vlan_proto; 4601 u16 vlanid; 4602 4603 if ((vlan_proto == htons(ETH_P_8021Q) && 4604 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4605 (vlan_proto == htons(ETH_P_8021AD) && 4606 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4607 /* pop the vlan tag */ 4608 vlanid = ntohs(veth->h_vlan_TCI); 4609 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4610 skb_pull(skb, VLAN_HLEN); 4611 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4612 } 4613 } 4614 4615 /** 4616 * stmmac_rx_refill - refill used skb preallocated buffers 4617 * @priv: driver private structure 4618 * @queue: RX queue index 4619 * Description : this is to reallocate the skb for the reception process 4620 * that is based on zero-copy. 4621 */ 4622 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4623 { 4624 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4625 int dirty = stmmac_rx_dirty(priv, queue); 4626 unsigned int entry = rx_q->dirty_rx; 4627 gfp_t gfp = (GFP_ATOMIC | __GFP_NOWARN); 4628 4629 if (priv->dma_cap.host_dma_width <= 32) 4630 gfp |= GFP_DMA32; 4631 4632 while (dirty-- > 0) { 4633 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4634 struct dma_desc *p; 4635 bool use_rx_wd; 4636 4637 if (priv->extend_desc) 4638 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4639 else 4640 p = rx_q->dma_rx + entry; 4641 4642 if (!buf->page) { 4643 buf->page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4644 if (!buf->page) 4645 break; 4646 } 4647 4648 if (priv->sph && !buf->sec_page) { 4649 buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); 4650 if (!buf->sec_page) 4651 break; 4652 4653 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4654 } 4655 4656 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4657 4658 stmmac_set_desc_addr(priv, p, buf->addr); 4659 if (priv->sph) 4660 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4661 else 4662 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4663 stmmac_refill_desc3(priv, rx_q, p); 4664 4665 rx_q->rx_count_frames++; 4666 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4667 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4668 rx_q->rx_count_frames = 0; 4669 4670 use_rx_wd = !priv->rx_coal_frames[queue]; 4671 use_rx_wd |= rx_q->rx_count_frames > 0; 4672 if (!priv->use_riwt) 4673 use_rx_wd = false; 4674 4675 dma_wmb(); 4676 stmmac_set_rx_owner(priv, p, use_rx_wd); 4677 4678 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 4679 } 4680 rx_q->dirty_rx = entry; 4681 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4682 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4683 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4684 } 4685 4686 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4687 struct dma_desc *p, 4688 int status, unsigned int len) 4689 { 4690 unsigned int plen = 0, hlen = 0; 4691 int coe = priv->hw->rx_csum; 4692 4693 /* Not first descriptor, buffer is always zero */ 4694 if (priv->sph && len) 4695 return 0; 4696 4697 /* First descriptor, get split header length */ 4698 stmmac_get_rx_header_len(priv, p, &hlen); 4699 if (priv->sph && hlen) { 4700 priv->xstats.rx_split_hdr_pkt_n++; 4701 return hlen; 4702 } 4703 4704 /* First descriptor, not last descriptor and not split header */ 4705 if (status & rx_not_ls) 4706 return priv->dma_conf.dma_buf_sz; 4707 4708 plen = stmmac_get_rx_frame_len(priv, p, coe); 4709 4710 /* First descriptor and last descriptor and not split header */ 4711 return min_t(unsigned int, priv->dma_conf.dma_buf_sz, plen); 4712 } 4713 4714 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4715 struct dma_desc *p, 4716 int status, unsigned int len) 4717 { 4718 int coe = priv->hw->rx_csum; 4719 unsigned int plen = 0; 4720 4721 /* Not split header, buffer is not available */ 4722 if (!priv->sph) 4723 return 0; 4724 4725 /* Not last descriptor */ 4726 if (status & rx_not_ls) 4727 return priv->dma_conf.dma_buf_sz; 4728 4729 plen = stmmac_get_rx_frame_len(priv, p, coe); 4730 4731 /* Last descriptor */ 4732 return plen - len; 4733 } 4734 4735 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4736 struct xdp_frame *xdpf, bool dma_map) 4737 { 4738 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 4739 unsigned int entry = tx_q->cur_tx; 4740 struct dma_desc *tx_desc; 4741 dma_addr_t dma_addr; 4742 bool set_ic; 4743 4744 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4745 return STMMAC_XDP_CONSUMED; 4746 4747 if (likely(priv->extend_desc)) 4748 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4749 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4750 tx_desc = &tx_q->dma_entx[entry].basic; 4751 else 4752 tx_desc = tx_q->dma_tx + entry; 4753 4754 if (dma_map) { 4755 dma_addr = dma_map_single(priv->device, xdpf->data, 4756 xdpf->len, DMA_TO_DEVICE); 4757 if (dma_mapping_error(priv->device, dma_addr)) 4758 return STMMAC_XDP_CONSUMED; 4759 4760 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4761 } else { 4762 struct page *page = virt_to_page(xdpf->data); 4763 4764 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4765 xdpf->headroom; 4766 dma_sync_single_for_device(priv->device, dma_addr, 4767 xdpf->len, DMA_BIDIRECTIONAL); 4768 4769 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4770 } 4771 4772 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4773 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4774 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4775 tx_q->tx_skbuff_dma[entry].last_segment = true; 4776 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4777 4778 tx_q->xdpf[entry] = xdpf; 4779 4780 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4781 4782 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4783 true, priv->mode, true, true, 4784 xdpf->len); 4785 4786 tx_q->tx_count_frames++; 4787 4788 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4789 set_ic = true; 4790 else 4791 set_ic = false; 4792 4793 if (set_ic) { 4794 unsigned long flags; 4795 tx_q->tx_count_frames = 0; 4796 stmmac_set_tx_ic(priv, tx_desc); 4797 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 4798 tx_q->txq_stats.tx_set_ic_bit++; 4799 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 4800 } 4801 4802 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4803 4804 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_tx_size); 4805 tx_q->cur_tx = entry; 4806 4807 return STMMAC_XDP_TX; 4808 } 4809 4810 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4811 int cpu) 4812 { 4813 int index = cpu; 4814 4815 if (unlikely(index < 0)) 4816 index = 0; 4817 4818 while (index >= priv->plat->tx_queues_to_use) 4819 index -= priv->plat->tx_queues_to_use; 4820 4821 return index; 4822 } 4823 4824 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4825 struct xdp_buff *xdp) 4826 { 4827 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4828 int cpu = smp_processor_id(); 4829 struct netdev_queue *nq; 4830 int queue; 4831 int res; 4832 4833 if (unlikely(!xdpf)) 4834 return STMMAC_XDP_CONSUMED; 4835 4836 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4837 nq = netdev_get_tx_queue(priv->dev, queue); 4838 4839 __netif_tx_lock(nq, cpu); 4840 /* Avoids TX time-out as we are sharing with slow path */ 4841 txq_trans_cond_update(nq); 4842 4843 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4844 if (res == STMMAC_XDP_TX) 4845 stmmac_flush_tx_descriptors(priv, queue); 4846 4847 __netif_tx_unlock(nq); 4848 4849 return res; 4850 } 4851 4852 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4853 struct bpf_prog *prog, 4854 struct xdp_buff *xdp) 4855 { 4856 u32 act; 4857 int res; 4858 4859 act = bpf_prog_run_xdp(prog, xdp); 4860 switch (act) { 4861 case XDP_PASS: 4862 res = STMMAC_XDP_PASS; 4863 break; 4864 case XDP_TX: 4865 res = stmmac_xdp_xmit_back(priv, xdp); 4866 break; 4867 case XDP_REDIRECT: 4868 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4869 res = STMMAC_XDP_CONSUMED; 4870 else 4871 res = STMMAC_XDP_REDIRECT; 4872 break; 4873 default: 4874 bpf_warn_invalid_xdp_action(priv->dev, prog, act); 4875 fallthrough; 4876 case XDP_ABORTED: 4877 trace_xdp_exception(priv->dev, prog, act); 4878 fallthrough; 4879 case XDP_DROP: 4880 res = STMMAC_XDP_CONSUMED; 4881 break; 4882 } 4883 4884 return res; 4885 } 4886 4887 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4888 struct xdp_buff *xdp) 4889 { 4890 struct bpf_prog *prog; 4891 int res; 4892 4893 prog = READ_ONCE(priv->xdp_prog); 4894 if (!prog) { 4895 res = STMMAC_XDP_PASS; 4896 goto out; 4897 } 4898 4899 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4900 out: 4901 return ERR_PTR(-res); 4902 } 4903 4904 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4905 int xdp_status) 4906 { 4907 int cpu = smp_processor_id(); 4908 int queue; 4909 4910 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4911 4912 if (xdp_status & STMMAC_XDP_TX) 4913 stmmac_tx_timer_arm(priv, queue); 4914 4915 if (xdp_status & STMMAC_XDP_REDIRECT) 4916 xdp_do_flush(); 4917 } 4918 4919 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4920 struct xdp_buff *xdp) 4921 { 4922 unsigned int metasize = xdp->data - xdp->data_meta; 4923 unsigned int datasize = xdp->data_end - xdp->data; 4924 struct sk_buff *skb; 4925 4926 skb = __napi_alloc_skb(&ch->rxtx_napi, 4927 xdp->data_end - xdp->data_hard_start, 4928 GFP_ATOMIC | __GFP_NOWARN); 4929 if (unlikely(!skb)) 4930 return NULL; 4931 4932 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4933 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4934 if (metasize) 4935 skb_metadata_set(skb, metasize); 4936 4937 return skb; 4938 } 4939 4940 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4941 struct dma_desc *p, struct dma_desc *np, 4942 struct xdp_buff *xdp) 4943 { 4944 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4945 struct stmmac_channel *ch = &priv->channel[queue]; 4946 unsigned int len = xdp->data_end - xdp->data; 4947 enum pkt_hash_types hash_type; 4948 int coe = priv->hw->rx_csum; 4949 unsigned long flags; 4950 struct sk_buff *skb; 4951 u32 hash; 4952 4953 skb = stmmac_construct_skb_zc(ch, xdp); 4954 if (!skb) { 4955 priv->xstats.rx_dropped++; 4956 return; 4957 } 4958 4959 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4960 stmmac_rx_vlan(priv->dev, skb); 4961 skb->protocol = eth_type_trans(skb, priv->dev); 4962 4963 if (unlikely(!coe)) 4964 skb_checksum_none_assert(skb); 4965 else 4966 skb->ip_summed = CHECKSUM_UNNECESSARY; 4967 4968 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4969 skb_set_hash(skb, hash, hash_type); 4970 4971 skb_record_rx_queue(skb, queue); 4972 napi_gro_receive(&ch->rxtx_napi, skb); 4973 4974 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 4975 rx_q->rxq_stats.rx_pkt_n++; 4976 rx_q->rxq_stats.rx_bytes += len; 4977 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 4978 } 4979 4980 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4981 { 4982 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 4983 unsigned int entry = rx_q->dirty_rx; 4984 struct dma_desc *rx_desc = NULL; 4985 bool ret = true; 4986 4987 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4988 4989 while (budget-- > 0 && entry != rx_q->cur_rx) { 4990 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4991 dma_addr_t dma_addr; 4992 bool use_rx_wd; 4993 4994 if (!buf->xdp) { 4995 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4996 if (!buf->xdp) { 4997 ret = false; 4998 break; 4999 } 5000 } 5001 5002 if (priv->extend_desc) 5003 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 5004 else 5005 rx_desc = rx_q->dma_rx + entry; 5006 5007 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 5008 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 5009 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 5010 stmmac_refill_desc3(priv, rx_q, rx_desc); 5011 5012 rx_q->rx_count_frames++; 5013 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 5014 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 5015 rx_q->rx_count_frames = 0; 5016 5017 use_rx_wd = !priv->rx_coal_frames[queue]; 5018 use_rx_wd |= rx_q->rx_count_frames > 0; 5019 if (!priv->use_riwt) 5020 use_rx_wd = false; 5021 5022 dma_wmb(); 5023 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 5024 5025 entry = STMMAC_GET_ENTRY(entry, priv->dma_conf.dma_rx_size); 5026 } 5027 5028 if (rx_desc) { 5029 rx_q->dirty_rx = entry; 5030 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 5031 (rx_q->dirty_rx * sizeof(struct dma_desc)); 5032 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 5033 } 5034 5035 return ret; 5036 } 5037 5038 static struct stmmac_xdp_buff *xsk_buff_to_stmmac_ctx(struct xdp_buff *xdp) 5039 { 5040 /* In XDP zero copy data path, xdp field in struct xdp_buff_xsk is used 5041 * to represent incoming packet, whereas cb field in the same structure 5042 * is used to store driver specific info. Thus, struct stmmac_xdp_buff 5043 * is laid on top of xdp and cb fields of struct xdp_buff_xsk. 5044 */ 5045 return (struct stmmac_xdp_buff *)xdp; 5046 } 5047 5048 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 5049 { 5050 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5051 unsigned int count = 0, error = 0, len = 0; 5052 int dirty = stmmac_rx_dirty(priv, queue); 5053 unsigned int next_entry = rx_q->cur_rx; 5054 u32 rx_errors = 0, rx_dropped = 0; 5055 unsigned int desc_size; 5056 struct bpf_prog *prog; 5057 bool failure = false; 5058 unsigned long flags; 5059 int xdp_status = 0; 5060 int status = 0; 5061 5062 if (netif_msg_rx_status(priv)) { 5063 void *rx_head; 5064 5065 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5066 if (priv->extend_desc) { 5067 rx_head = (void *)rx_q->dma_erx; 5068 desc_size = sizeof(struct dma_extended_desc); 5069 } else { 5070 rx_head = (void *)rx_q->dma_rx; 5071 desc_size = sizeof(struct dma_desc); 5072 } 5073 5074 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5075 rx_q->dma_rx_phy, desc_size); 5076 } 5077 while (count < limit) { 5078 struct stmmac_rx_buffer *buf; 5079 struct stmmac_xdp_buff *ctx; 5080 unsigned int buf1_len = 0; 5081 struct dma_desc *np, *p; 5082 int entry; 5083 int res; 5084 5085 if (!count && rx_q->state_saved) { 5086 error = rx_q->state.error; 5087 len = rx_q->state.len; 5088 } else { 5089 rx_q->state_saved = false; 5090 error = 0; 5091 len = 0; 5092 } 5093 5094 if (count >= limit) 5095 break; 5096 5097 read_again: 5098 buf1_len = 0; 5099 entry = next_entry; 5100 buf = &rx_q->buf_pool[entry]; 5101 5102 if (dirty >= STMMAC_RX_FILL_BATCH) { 5103 failure = failure || 5104 !stmmac_rx_refill_zc(priv, queue, dirty); 5105 dirty = 0; 5106 } 5107 5108 if (priv->extend_desc) 5109 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5110 else 5111 p = rx_q->dma_rx + entry; 5112 5113 /* read the status of the incoming frame */ 5114 status = stmmac_rx_status(priv, &priv->xstats, p); 5115 /* check if managed by the DMA otherwise go ahead */ 5116 if (unlikely(status & dma_own)) 5117 break; 5118 5119 /* Prefetch the next RX descriptor */ 5120 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5121 priv->dma_conf.dma_rx_size); 5122 next_entry = rx_q->cur_rx; 5123 5124 if (priv->extend_desc) 5125 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5126 else 5127 np = rx_q->dma_rx + next_entry; 5128 5129 prefetch(np); 5130 5131 /* Ensure a valid XSK buffer before proceed */ 5132 if (!buf->xdp) 5133 break; 5134 5135 if (priv->extend_desc) 5136 stmmac_rx_extended_status(priv, &priv->xstats, 5137 rx_q->dma_erx + entry); 5138 if (unlikely(status == discard_frame)) { 5139 xsk_buff_free(buf->xdp); 5140 buf->xdp = NULL; 5141 dirty++; 5142 error = 1; 5143 if (!priv->hwts_rx_en) 5144 rx_errors++; 5145 } 5146 5147 if (unlikely(error && (status & rx_not_ls))) 5148 goto read_again; 5149 if (unlikely(error)) { 5150 count++; 5151 continue; 5152 } 5153 5154 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 5155 if (likely(status & rx_not_ls)) { 5156 xsk_buff_free(buf->xdp); 5157 buf->xdp = NULL; 5158 dirty++; 5159 count++; 5160 goto read_again; 5161 } 5162 5163 ctx = xsk_buff_to_stmmac_ctx(buf->xdp); 5164 ctx->priv = priv; 5165 ctx->desc = p; 5166 ctx->ndesc = np; 5167 5168 /* XDP ZC Frame only support primary buffers for now */ 5169 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5170 len += buf1_len; 5171 5172 /* ACS is disabled; strip manually. */ 5173 if (likely(!(status & rx_not_ls))) { 5174 buf1_len -= ETH_FCS_LEN; 5175 len -= ETH_FCS_LEN; 5176 } 5177 5178 /* RX buffer is good and fit into a XSK pool buffer */ 5179 buf->xdp->data_end = buf->xdp->data + buf1_len; 5180 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 5181 5182 prog = READ_ONCE(priv->xdp_prog); 5183 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 5184 5185 switch (res) { 5186 case STMMAC_XDP_PASS: 5187 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 5188 xsk_buff_free(buf->xdp); 5189 break; 5190 case STMMAC_XDP_CONSUMED: 5191 xsk_buff_free(buf->xdp); 5192 rx_dropped++; 5193 break; 5194 case STMMAC_XDP_TX: 5195 case STMMAC_XDP_REDIRECT: 5196 xdp_status |= res; 5197 break; 5198 } 5199 5200 buf->xdp = NULL; 5201 dirty++; 5202 count++; 5203 } 5204 5205 if (status & rx_not_ls) { 5206 rx_q->state_saved = true; 5207 rx_q->state.error = error; 5208 rx_q->state.len = len; 5209 } 5210 5211 stmmac_finalize_xdp_rx(priv, xdp_status); 5212 5213 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5214 rx_q->rxq_stats.rx_pkt_n += count; 5215 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5216 5217 priv->xstats.rx_dropped += rx_dropped; 5218 priv->xstats.rx_errors += rx_errors; 5219 5220 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5221 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5222 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5223 else 5224 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5225 5226 return (int)count; 5227 } 5228 5229 return failure ? limit : (int)count; 5230 } 5231 5232 /** 5233 * stmmac_rx - manage the receive process 5234 * @priv: driver private structure 5235 * @limit: napi bugget 5236 * @queue: RX queue index. 5237 * Description : this the function called by the napi poll method. 5238 * It gets all the frames inside the ring. 5239 */ 5240 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5241 { 5242 u32 rx_errors = 0, rx_dropped = 0, rx_bytes = 0, rx_packets = 0; 5243 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 5244 struct stmmac_channel *ch = &priv->channel[queue]; 5245 unsigned int count = 0, error = 0, len = 0; 5246 int status = 0, coe = priv->hw->rx_csum; 5247 unsigned int next_entry = rx_q->cur_rx; 5248 enum dma_data_direction dma_dir; 5249 unsigned int desc_size; 5250 struct sk_buff *skb = NULL; 5251 struct stmmac_xdp_buff ctx; 5252 unsigned long flags; 5253 int xdp_status = 0; 5254 int buf_sz; 5255 5256 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5257 buf_sz = DIV_ROUND_UP(priv->dma_conf.dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5258 5259 if (netif_msg_rx_status(priv)) { 5260 void *rx_head; 5261 5262 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5263 if (priv->extend_desc) { 5264 rx_head = (void *)rx_q->dma_erx; 5265 desc_size = sizeof(struct dma_extended_desc); 5266 } else { 5267 rx_head = (void *)rx_q->dma_rx; 5268 desc_size = sizeof(struct dma_desc); 5269 } 5270 5271 stmmac_display_ring(priv, rx_head, priv->dma_conf.dma_rx_size, true, 5272 rx_q->dma_rx_phy, desc_size); 5273 } 5274 while (count < limit) { 5275 unsigned int buf1_len = 0, buf2_len = 0; 5276 enum pkt_hash_types hash_type; 5277 struct stmmac_rx_buffer *buf; 5278 struct dma_desc *np, *p; 5279 int entry; 5280 u32 hash; 5281 5282 if (!count && rx_q->state_saved) { 5283 skb = rx_q->state.skb; 5284 error = rx_q->state.error; 5285 len = rx_q->state.len; 5286 } else { 5287 rx_q->state_saved = false; 5288 skb = NULL; 5289 error = 0; 5290 len = 0; 5291 } 5292 5293 if (count >= limit) 5294 break; 5295 5296 read_again: 5297 buf1_len = 0; 5298 buf2_len = 0; 5299 entry = next_entry; 5300 buf = &rx_q->buf_pool[entry]; 5301 5302 if (priv->extend_desc) 5303 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5304 else 5305 p = rx_q->dma_rx + entry; 5306 5307 /* read the status of the incoming frame */ 5308 status = stmmac_rx_status(priv, &priv->xstats, p); 5309 /* check if managed by the DMA otherwise go ahead */ 5310 if (unlikely(status & dma_own)) 5311 break; 5312 5313 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5314 priv->dma_conf.dma_rx_size); 5315 next_entry = rx_q->cur_rx; 5316 5317 if (priv->extend_desc) 5318 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5319 else 5320 np = rx_q->dma_rx + next_entry; 5321 5322 prefetch(np); 5323 5324 if (priv->extend_desc) 5325 stmmac_rx_extended_status(priv, &priv->xstats, rx_q->dma_erx + entry); 5326 if (unlikely(status == discard_frame)) { 5327 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5328 buf->page = NULL; 5329 error = 1; 5330 if (!priv->hwts_rx_en) 5331 rx_errors++; 5332 } 5333 5334 if (unlikely(error && (status & rx_not_ls))) 5335 goto read_again; 5336 if (unlikely(error)) { 5337 dev_kfree_skb(skb); 5338 skb = NULL; 5339 count++; 5340 continue; 5341 } 5342 5343 /* Buffer is good. Go on. */ 5344 5345 prefetch(page_address(buf->page) + buf->page_offset); 5346 if (buf->sec_page) 5347 prefetch(page_address(buf->sec_page)); 5348 5349 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5350 len += buf1_len; 5351 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5352 len += buf2_len; 5353 5354 /* ACS is disabled; strip manually. */ 5355 if (likely(!(status & rx_not_ls))) { 5356 if (buf2_len) { 5357 buf2_len -= ETH_FCS_LEN; 5358 len -= ETH_FCS_LEN; 5359 } else if (buf1_len) { 5360 buf1_len -= ETH_FCS_LEN; 5361 len -= ETH_FCS_LEN; 5362 } 5363 } 5364 5365 if (!skb) { 5366 unsigned int pre_len, sync_len; 5367 5368 dma_sync_single_for_cpu(priv->device, buf->addr, 5369 buf1_len, dma_dir); 5370 5371 xdp_init_buff(&ctx.xdp, buf_sz, &rx_q->xdp_rxq); 5372 xdp_prepare_buff(&ctx.xdp, page_address(buf->page), 5373 buf->page_offset, buf1_len, true); 5374 5375 pre_len = ctx.xdp.data_end - ctx.xdp.data_hard_start - 5376 buf->page_offset; 5377 5378 ctx.priv = priv; 5379 ctx.desc = p; 5380 ctx.ndesc = np; 5381 5382 skb = stmmac_xdp_run_prog(priv, &ctx.xdp); 5383 /* Due xdp_adjust_tail: DMA sync for_device 5384 * cover max len CPU touch 5385 */ 5386 sync_len = ctx.xdp.data_end - ctx.xdp.data_hard_start - 5387 buf->page_offset; 5388 sync_len = max(sync_len, pre_len); 5389 5390 /* For Not XDP_PASS verdict */ 5391 if (IS_ERR(skb)) { 5392 unsigned int xdp_res = -PTR_ERR(skb); 5393 5394 if (xdp_res & STMMAC_XDP_CONSUMED) { 5395 page_pool_put_page(rx_q->page_pool, 5396 virt_to_head_page(ctx.xdp.data), 5397 sync_len, true); 5398 buf->page = NULL; 5399 rx_dropped++; 5400 5401 /* Clear skb as it was set as 5402 * status by XDP program. 5403 */ 5404 skb = NULL; 5405 5406 if (unlikely((status & rx_not_ls))) 5407 goto read_again; 5408 5409 count++; 5410 continue; 5411 } else if (xdp_res & (STMMAC_XDP_TX | 5412 STMMAC_XDP_REDIRECT)) { 5413 xdp_status |= xdp_res; 5414 buf->page = NULL; 5415 skb = NULL; 5416 count++; 5417 continue; 5418 } 5419 } 5420 } 5421 5422 if (!skb) { 5423 /* XDP program may expand or reduce tail */ 5424 buf1_len = ctx.xdp.data_end - ctx.xdp.data; 5425 5426 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5427 if (!skb) { 5428 rx_dropped++; 5429 count++; 5430 goto drain_data; 5431 } 5432 5433 /* XDP program may adjust header */ 5434 skb_copy_to_linear_data(skb, ctx.xdp.data, buf1_len); 5435 skb_put(skb, buf1_len); 5436 5437 /* Data payload copied into SKB, page ready for recycle */ 5438 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5439 buf->page = NULL; 5440 } else if (buf1_len) { 5441 dma_sync_single_for_cpu(priv->device, buf->addr, 5442 buf1_len, dma_dir); 5443 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5444 buf->page, buf->page_offset, buf1_len, 5445 priv->dma_conf.dma_buf_sz); 5446 5447 /* Data payload appended into SKB */ 5448 skb_mark_for_recycle(skb); 5449 buf->page = NULL; 5450 } 5451 5452 if (buf2_len) { 5453 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5454 buf2_len, dma_dir); 5455 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5456 buf->sec_page, 0, buf2_len, 5457 priv->dma_conf.dma_buf_sz); 5458 5459 /* Data payload appended into SKB */ 5460 skb_mark_for_recycle(skb); 5461 buf->sec_page = NULL; 5462 } 5463 5464 drain_data: 5465 if (likely(status & rx_not_ls)) 5466 goto read_again; 5467 if (!skb) 5468 continue; 5469 5470 /* Got entire packet into SKB. Finish it. */ 5471 5472 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5473 stmmac_rx_vlan(priv->dev, skb); 5474 skb->protocol = eth_type_trans(skb, priv->dev); 5475 5476 if (unlikely(!coe)) 5477 skb_checksum_none_assert(skb); 5478 else 5479 skb->ip_summed = CHECKSUM_UNNECESSARY; 5480 5481 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5482 skb_set_hash(skb, hash, hash_type); 5483 5484 skb_record_rx_queue(skb, queue); 5485 napi_gro_receive(&ch->rx_napi, skb); 5486 skb = NULL; 5487 5488 rx_packets++; 5489 rx_bytes += len; 5490 count++; 5491 } 5492 5493 if (status & rx_not_ls || skb) { 5494 rx_q->state_saved = true; 5495 rx_q->state.skb = skb; 5496 rx_q->state.error = error; 5497 rx_q->state.len = len; 5498 } 5499 5500 stmmac_finalize_xdp_rx(priv, xdp_status); 5501 5502 stmmac_rx_refill(priv, queue); 5503 5504 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5505 rx_q->rxq_stats.rx_packets += rx_packets; 5506 rx_q->rxq_stats.rx_bytes += rx_bytes; 5507 rx_q->rxq_stats.rx_pkt_n += count; 5508 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5509 5510 priv->xstats.rx_dropped += rx_dropped; 5511 priv->xstats.rx_errors += rx_errors; 5512 5513 return count; 5514 } 5515 5516 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5517 { 5518 struct stmmac_channel *ch = 5519 container_of(napi, struct stmmac_channel, rx_napi); 5520 struct stmmac_priv *priv = ch->priv_data; 5521 struct stmmac_rx_queue *rx_q; 5522 u32 chan = ch->index; 5523 unsigned long flags; 5524 int work_done; 5525 5526 rx_q = &priv->dma_conf.rx_queue[chan]; 5527 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5528 rx_q->rxq_stats.napi_poll++; 5529 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5530 5531 work_done = stmmac_rx(priv, budget, chan); 5532 if (work_done < budget && napi_complete_done(napi, work_done)) { 5533 unsigned long flags; 5534 5535 spin_lock_irqsave(&ch->lock, flags); 5536 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5537 spin_unlock_irqrestore(&ch->lock, flags); 5538 } 5539 5540 return work_done; 5541 } 5542 5543 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5544 { 5545 struct stmmac_channel *ch = 5546 container_of(napi, struct stmmac_channel, tx_napi); 5547 struct stmmac_priv *priv = ch->priv_data; 5548 struct stmmac_tx_queue *tx_q; 5549 u32 chan = ch->index; 5550 unsigned long flags; 5551 int work_done; 5552 5553 tx_q = &priv->dma_conf.tx_queue[chan]; 5554 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 5555 tx_q->txq_stats.napi_poll++; 5556 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 5557 5558 work_done = stmmac_tx_clean(priv, budget, chan); 5559 work_done = min(work_done, budget); 5560 5561 if (work_done < budget && napi_complete_done(napi, work_done)) { 5562 unsigned long flags; 5563 5564 spin_lock_irqsave(&ch->lock, flags); 5565 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5566 spin_unlock_irqrestore(&ch->lock, flags); 5567 } 5568 5569 return work_done; 5570 } 5571 5572 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5573 { 5574 struct stmmac_channel *ch = 5575 container_of(napi, struct stmmac_channel, rxtx_napi); 5576 struct stmmac_priv *priv = ch->priv_data; 5577 int rx_done, tx_done, rxtx_done; 5578 struct stmmac_rx_queue *rx_q; 5579 struct stmmac_tx_queue *tx_q; 5580 u32 chan = ch->index; 5581 unsigned long flags; 5582 5583 rx_q = &priv->dma_conf.rx_queue[chan]; 5584 flags = u64_stats_update_begin_irqsave(&rx_q->rxq_stats.syncp); 5585 rx_q->rxq_stats.napi_poll++; 5586 u64_stats_update_end_irqrestore(&rx_q->rxq_stats.syncp, flags); 5587 5588 tx_q = &priv->dma_conf.tx_queue[chan]; 5589 flags = u64_stats_update_begin_irqsave(&tx_q->txq_stats.syncp); 5590 tx_q->txq_stats.napi_poll++; 5591 u64_stats_update_end_irqrestore(&tx_q->txq_stats.syncp, flags); 5592 5593 tx_done = stmmac_tx_clean(priv, budget, chan); 5594 tx_done = min(tx_done, budget); 5595 5596 rx_done = stmmac_rx_zc(priv, budget, chan); 5597 5598 rxtx_done = max(tx_done, rx_done); 5599 5600 /* If either TX or RX work is not complete, return budget 5601 * and keep pooling 5602 */ 5603 if (rxtx_done >= budget) 5604 return budget; 5605 5606 /* all work done, exit the polling mode */ 5607 if (napi_complete_done(napi, rxtx_done)) { 5608 unsigned long flags; 5609 5610 spin_lock_irqsave(&ch->lock, flags); 5611 /* Both RX and TX work done are compelte, 5612 * so enable both RX & TX IRQs. 5613 */ 5614 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5615 spin_unlock_irqrestore(&ch->lock, flags); 5616 } 5617 5618 return min(rxtx_done, budget - 1); 5619 } 5620 5621 /** 5622 * stmmac_tx_timeout 5623 * @dev : Pointer to net device structure 5624 * @txqueue: the index of the hanging transmit queue 5625 * Description: this function is called when a packet transmission fails to 5626 * complete within a reasonable time. The driver will mark the error in the 5627 * netdev structure and arrange for the device to be reset to a sane state 5628 * in order to transmit a new packet. 5629 */ 5630 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5631 { 5632 struct stmmac_priv *priv = netdev_priv(dev); 5633 5634 stmmac_global_err(priv); 5635 } 5636 5637 /** 5638 * stmmac_set_rx_mode - entry point for multicast addressing 5639 * @dev : pointer to the device structure 5640 * Description: 5641 * This function is a driver entry point which gets called by the kernel 5642 * whenever multicast addresses must be enabled/disabled. 5643 * Return value: 5644 * void. 5645 */ 5646 static void stmmac_set_rx_mode(struct net_device *dev) 5647 { 5648 struct stmmac_priv *priv = netdev_priv(dev); 5649 5650 stmmac_set_filter(priv, priv->hw, dev); 5651 } 5652 5653 /** 5654 * stmmac_change_mtu - entry point to change MTU size for the device. 5655 * @dev : device pointer. 5656 * @new_mtu : the new MTU size for the device. 5657 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5658 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5659 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5660 * Return value: 5661 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5662 * file on failure. 5663 */ 5664 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5665 { 5666 struct stmmac_priv *priv = netdev_priv(dev); 5667 int txfifosz = priv->plat->tx_fifo_size; 5668 struct stmmac_dma_conf *dma_conf; 5669 const int mtu = new_mtu; 5670 int ret; 5671 5672 if (txfifosz == 0) 5673 txfifosz = priv->dma_cap.tx_fifo_size; 5674 5675 txfifosz /= priv->plat->tx_queues_to_use; 5676 5677 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5678 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5679 return -EINVAL; 5680 } 5681 5682 new_mtu = STMMAC_ALIGN(new_mtu); 5683 5684 /* If condition true, FIFO is too small or MTU too large */ 5685 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5686 return -EINVAL; 5687 5688 if (netif_running(dev)) { 5689 netdev_dbg(priv->dev, "restarting interface to change its MTU\n"); 5690 /* Try to allocate the new DMA conf with the new mtu */ 5691 dma_conf = stmmac_setup_dma_desc(priv, mtu); 5692 if (IS_ERR(dma_conf)) { 5693 netdev_err(priv->dev, "failed allocating new dma conf for new MTU %d\n", 5694 mtu); 5695 return PTR_ERR(dma_conf); 5696 } 5697 5698 stmmac_release(dev); 5699 5700 ret = __stmmac_open(dev, dma_conf); 5701 if (ret) { 5702 free_dma_desc_resources(priv, dma_conf); 5703 kfree(dma_conf); 5704 netdev_err(priv->dev, "failed reopening the interface after MTU change\n"); 5705 return ret; 5706 } 5707 5708 kfree(dma_conf); 5709 5710 stmmac_set_rx_mode(dev); 5711 } 5712 5713 dev->mtu = mtu; 5714 netdev_update_features(dev); 5715 5716 return 0; 5717 } 5718 5719 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5720 netdev_features_t features) 5721 { 5722 struct stmmac_priv *priv = netdev_priv(dev); 5723 5724 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5725 features &= ~NETIF_F_RXCSUM; 5726 5727 if (!priv->plat->tx_coe) 5728 features &= ~NETIF_F_CSUM_MASK; 5729 5730 /* Some GMAC devices have a bugged Jumbo frame support that 5731 * needs to have the Tx COE disabled for oversized frames 5732 * (due to limited buffer sizes). In this case we disable 5733 * the TX csum insertion in the TDES and not use SF. 5734 */ 5735 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5736 features &= ~NETIF_F_CSUM_MASK; 5737 5738 /* Disable tso if asked by ethtool */ 5739 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) { 5740 if (features & NETIF_F_TSO) 5741 priv->tso = true; 5742 else 5743 priv->tso = false; 5744 } 5745 5746 return features; 5747 } 5748 5749 static int stmmac_set_features(struct net_device *netdev, 5750 netdev_features_t features) 5751 { 5752 struct stmmac_priv *priv = netdev_priv(netdev); 5753 5754 /* Keep the COE Type in case of csum is supporting */ 5755 if (features & NETIF_F_RXCSUM) 5756 priv->hw->rx_csum = priv->plat->rx_coe; 5757 else 5758 priv->hw->rx_csum = 0; 5759 /* No check needed because rx_coe has been set before and it will be 5760 * fixed in case of issue. 5761 */ 5762 stmmac_rx_ipc(priv, priv->hw); 5763 5764 if (priv->sph_cap) { 5765 bool sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5766 u32 chan; 5767 5768 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5769 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5770 } 5771 5772 return 0; 5773 } 5774 5775 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5776 { 5777 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5778 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5779 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5780 bool *hs_enable = &fpe_cfg->hs_enable; 5781 5782 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5783 return; 5784 5785 /* If LP has sent verify mPacket, LP is FPE capable */ 5786 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5787 if (*lp_state < FPE_STATE_CAPABLE) 5788 *lp_state = FPE_STATE_CAPABLE; 5789 5790 /* If user has requested FPE enable, quickly response */ 5791 if (*hs_enable) 5792 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5793 MPACKET_RESPONSE); 5794 } 5795 5796 /* If Local has sent verify mPacket, Local is FPE capable */ 5797 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5798 if (*lo_state < FPE_STATE_CAPABLE) 5799 *lo_state = FPE_STATE_CAPABLE; 5800 } 5801 5802 /* If LP has sent response mPacket, LP is entering FPE ON */ 5803 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5804 *lp_state = FPE_STATE_ENTERING_ON; 5805 5806 /* If Local has sent response mPacket, Local is entering FPE ON */ 5807 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5808 *lo_state = FPE_STATE_ENTERING_ON; 5809 5810 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5811 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5812 priv->fpe_wq) { 5813 queue_work(priv->fpe_wq, &priv->fpe_task); 5814 } 5815 } 5816 5817 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5818 { 5819 u32 rx_cnt = priv->plat->rx_queues_to_use; 5820 u32 tx_cnt = priv->plat->tx_queues_to_use; 5821 u32 queues_count; 5822 u32 queue; 5823 bool xmac; 5824 5825 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5826 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5827 5828 if (priv->irq_wake) 5829 pm_wakeup_event(priv->device, 0); 5830 5831 if (priv->dma_cap.estsel) 5832 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5833 &priv->xstats, tx_cnt); 5834 5835 if (priv->dma_cap.fpesel) { 5836 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5837 priv->dev); 5838 5839 stmmac_fpe_event_status(priv, status); 5840 } 5841 5842 /* To handle GMAC own interrupts */ 5843 if ((priv->plat->has_gmac) || xmac) { 5844 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5845 5846 if (unlikely(status)) { 5847 /* For LPI we need to save the tx status */ 5848 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5849 priv->tx_path_in_lpi_mode = true; 5850 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5851 priv->tx_path_in_lpi_mode = false; 5852 } 5853 5854 for (queue = 0; queue < queues_count; queue++) { 5855 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5856 queue); 5857 } 5858 5859 /* PCS link status */ 5860 if (priv->hw->pcs && 5861 !(priv->plat->flags & STMMAC_FLAG_HAS_INTEGRATED_PCS)) { 5862 if (priv->xstats.pcs_link) 5863 netif_carrier_on(priv->dev); 5864 else 5865 netif_carrier_off(priv->dev); 5866 } 5867 5868 stmmac_timestamp_interrupt(priv, priv); 5869 } 5870 } 5871 5872 /** 5873 * stmmac_interrupt - main ISR 5874 * @irq: interrupt number. 5875 * @dev_id: to pass the net device pointer. 5876 * Description: this is the main driver interrupt service routine. 5877 * It can call: 5878 * o DMA service routine (to manage incoming frame reception and transmission 5879 * status) 5880 * o Core interrupts to manage: remote wake-up, management counter, LPI 5881 * interrupts. 5882 */ 5883 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5884 { 5885 struct net_device *dev = (struct net_device *)dev_id; 5886 struct stmmac_priv *priv = netdev_priv(dev); 5887 5888 /* Check if adapter is up */ 5889 if (test_bit(STMMAC_DOWN, &priv->state)) 5890 return IRQ_HANDLED; 5891 5892 /* Check if a fatal error happened */ 5893 if (stmmac_safety_feat_interrupt(priv)) 5894 return IRQ_HANDLED; 5895 5896 /* To handle Common interrupts */ 5897 stmmac_common_interrupt(priv); 5898 5899 /* To handle DMA interrupts */ 5900 stmmac_dma_interrupt(priv); 5901 5902 return IRQ_HANDLED; 5903 } 5904 5905 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5906 { 5907 struct net_device *dev = (struct net_device *)dev_id; 5908 struct stmmac_priv *priv = netdev_priv(dev); 5909 5910 if (unlikely(!dev)) { 5911 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5912 return IRQ_NONE; 5913 } 5914 5915 /* Check if adapter is up */ 5916 if (test_bit(STMMAC_DOWN, &priv->state)) 5917 return IRQ_HANDLED; 5918 5919 /* To handle Common interrupts */ 5920 stmmac_common_interrupt(priv); 5921 5922 return IRQ_HANDLED; 5923 } 5924 5925 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5926 { 5927 struct net_device *dev = (struct net_device *)dev_id; 5928 struct stmmac_priv *priv = netdev_priv(dev); 5929 5930 if (unlikely(!dev)) { 5931 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5932 return IRQ_NONE; 5933 } 5934 5935 /* Check if adapter is up */ 5936 if (test_bit(STMMAC_DOWN, &priv->state)) 5937 return IRQ_HANDLED; 5938 5939 /* Check if a fatal error happened */ 5940 stmmac_safety_feat_interrupt(priv); 5941 5942 return IRQ_HANDLED; 5943 } 5944 5945 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5946 { 5947 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5948 struct stmmac_dma_conf *dma_conf; 5949 int chan = tx_q->queue_index; 5950 struct stmmac_priv *priv; 5951 int status; 5952 5953 dma_conf = container_of(tx_q, struct stmmac_dma_conf, tx_queue[chan]); 5954 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5955 5956 if (unlikely(!data)) { 5957 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5958 return IRQ_NONE; 5959 } 5960 5961 /* Check if adapter is up */ 5962 if (test_bit(STMMAC_DOWN, &priv->state)) 5963 return IRQ_HANDLED; 5964 5965 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5966 5967 if (unlikely(status & tx_hard_error_bump_tc)) { 5968 /* Try to bump up the dma threshold on this failure */ 5969 stmmac_bump_dma_threshold(priv, chan); 5970 } else if (unlikely(status == tx_hard_error)) { 5971 stmmac_tx_err(priv, chan); 5972 } 5973 5974 return IRQ_HANDLED; 5975 } 5976 5977 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5978 { 5979 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5980 struct stmmac_dma_conf *dma_conf; 5981 int chan = rx_q->queue_index; 5982 struct stmmac_priv *priv; 5983 5984 dma_conf = container_of(rx_q, struct stmmac_dma_conf, rx_queue[chan]); 5985 priv = container_of(dma_conf, struct stmmac_priv, dma_conf); 5986 5987 if (unlikely(!data)) { 5988 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5989 return IRQ_NONE; 5990 } 5991 5992 /* Check if adapter is up */ 5993 if (test_bit(STMMAC_DOWN, &priv->state)) 5994 return IRQ_HANDLED; 5995 5996 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5997 5998 return IRQ_HANDLED; 5999 } 6000 6001 #ifdef CONFIG_NET_POLL_CONTROLLER 6002 /* Polling receive - used by NETCONSOLE and other diagnostic tools 6003 * to allow network I/O with interrupts disabled. 6004 */ 6005 static void stmmac_poll_controller(struct net_device *dev) 6006 { 6007 struct stmmac_priv *priv = netdev_priv(dev); 6008 int i; 6009 6010 /* If adapter is down, do nothing */ 6011 if (test_bit(STMMAC_DOWN, &priv->state)) 6012 return; 6013 6014 if (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN) { 6015 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 6016 stmmac_msi_intr_rx(0, &priv->dma_conf.rx_queue[i]); 6017 6018 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 6019 stmmac_msi_intr_tx(0, &priv->dma_conf.tx_queue[i]); 6020 } else { 6021 disable_irq(dev->irq); 6022 stmmac_interrupt(dev->irq, dev); 6023 enable_irq(dev->irq); 6024 } 6025 } 6026 #endif 6027 6028 /** 6029 * stmmac_ioctl - Entry point for the Ioctl 6030 * @dev: Device pointer. 6031 * @rq: An IOCTL specefic structure, that can contain a pointer to 6032 * a proprietary structure used to pass information to the driver. 6033 * @cmd: IOCTL command 6034 * Description: 6035 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 6036 */ 6037 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 6038 { 6039 struct stmmac_priv *priv = netdev_priv (dev); 6040 int ret = -EOPNOTSUPP; 6041 6042 if (!netif_running(dev)) 6043 return -EINVAL; 6044 6045 switch (cmd) { 6046 case SIOCGMIIPHY: 6047 case SIOCGMIIREG: 6048 case SIOCSMIIREG: 6049 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 6050 break; 6051 case SIOCSHWTSTAMP: 6052 ret = stmmac_hwtstamp_set(dev, rq); 6053 break; 6054 case SIOCGHWTSTAMP: 6055 ret = stmmac_hwtstamp_get(dev, rq); 6056 break; 6057 default: 6058 break; 6059 } 6060 6061 return ret; 6062 } 6063 6064 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 6065 void *cb_priv) 6066 { 6067 struct stmmac_priv *priv = cb_priv; 6068 int ret = -EOPNOTSUPP; 6069 6070 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 6071 return ret; 6072 6073 __stmmac_disable_all_queues(priv); 6074 6075 switch (type) { 6076 case TC_SETUP_CLSU32: 6077 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 6078 break; 6079 case TC_SETUP_CLSFLOWER: 6080 ret = stmmac_tc_setup_cls(priv, priv, type_data); 6081 break; 6082 default: 6083 break; 6084 } 6085 6086 stmmac_enable_all_queues(priv); 6087 return ret; 6088 } 6089 6090 static LIST_HEAD(stmmac_block_cb_list); 6091 6092 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 6093 void *type_data) 6094 { 6095 struct stmmac_priv *priv = netdev_priv(ndev); 6096 6097 switch (type) { 6098 case TC_QUERY_CAPS: 6099 return stmmac_tc_query_caps(priv, priv, type_data); 6100 case TC_SETUP_BLOCK: 6101 return flow_block_cb_setup_simple(type_data, 6102 &stmmac_block_cb_list, 6103 stmmac_setup_tc_block_cb, 6104 priv, priv, true); 6105 case TC_SETUP_QDISC_CBS: 6106 return stmmac_tc_setup_cbs(priv, priv, type_data); 6107 case TC_SETUP_QDISC_TAPRIO: 6108 return stmmac_tc_setup_taprio(priv, priv, type_data); 6109 case TC_SETUP_QDISC_ETF: 6110 return stmmac_tc_setup_etf(priv, priv, type_data); 6111 default: 6112 return -EOPNOTSUPP; 6113 } 6114 } 6115 6116 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 6117 struct net_device *sb_dev) 6118 { 6119 int gso = skb_shinfo(skb)->gso_type; 6120 6121 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 6122 /* 6123 * There is no way to determine the number of TSO/USO 6124 * capable Queues. Let's use always the Queue 0 6125 * because if TSO/USO is supported then at least this 6126 * one will be capable. 6127 */ 6128 return 0; 6129 } 6130 6131 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 6132 } 6133 6134 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 6135 { 6136 struct stmmac_priv *priv = netdev_priv(ndev); 6137 int ret = 0; 6138 6139 ret = pm_runtime_resume_and_get(priv->device); 6140 if (ret < 0) 6141 return ret; 6142 6143 ret = eth_mac_addr(ndev, addr); 6144 if (ret) 6145 goto set_mac_error; 6146 6147 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 6148 6149 set_mac_error: 6150 pm_runtime_put(priv->device); 6151 6152 return ret; 6153 } 6154 6155 #ifdef CONFIG_DEBUG_FS 6156 static struct dentry *stmmac_fs_dir; 6157 6158 static void sysfs_display_ring(void *head, int size, int extend_desc, 6159 struct seq_file *seq, dma_addr_t dma_phy_addr) 6160 { 6161 int i; 6162 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 6163 struct dma_desc *p = (struct dma_desc *)head; 6164 dma_addr_t dma_addr; 6165 6166 for (i = 0; i < size; i++) { 6167 if (extend_desc) { 6168 dma_addr = dma_phy_addr + i * sizeof(*ep); 6169 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6170 i, &dma_addr, 6171 le32_to_cpu(ep->basic.des0), 6172 le32_to_cpu(ep->basic.des1), 6173 le32_to_cpu(ep->basic.des2), 6174 le32_to_cpu(ep->basic.des3)); 6175 ep++; 6176 } else { 6177 dma_addr = dma_phy_addr + i * sizeof(*p); 6178 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 6179 i, &dma_addr, 6180 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 6181 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 6182 p++; 6183 } 6184 seq_printf(seq, "\n"); 6185 } 6186 } 6187 6188 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 6189 { 6190 struct net_device *dev = seq->private; 6191 struct stmmac_priv *priv = netdev_priv(dev); 6192 u32 rx_count = priv->plat->rx_queues_to_use; 6193 u32 tx_count = priv->plat->tx_queues_to_use; 6194 u32 queue; 6195 6196 if ((dev->flags & IFF_UP) == 0) 6197 return 0; 6198 6199 for (queue = 0; queue < rx_count; queue++) { 6200 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6201 6202 seq_printf(seq, "RX Queue %d:\n", queue); 6203 6204 if (priv->extend_desc) { 6205 seq_printf(seq, "Extended descriptor ring:\n"); 6206 sysfs_display_ring((void *)rx_q->dma_erx, 6207 priv->dma_conf.dma_rx_size, 1, seq, rx_q->dma_rx_phy); 6208 } else { 6209 seq_printf(seq, "Descriptor ring:\n"); 6210 sysfs_display_ring((void *)rx_q->dma_rx, 6211 priv->dma_conf.dma_rx_size, 0, seq, rx_q->dma_rx_phy); 6212 } 6213 } 6214 6215 for (queue = 0; queue < tx_count; queue++) { 6216 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6217 6218 seq_printf(seq, "TX Queue %d:\n", queue); 6219 6220 if (priv->extend_desc) { 6221 seq_printf(seq, "Extended descriptor ring:\n"); 6222 sysfs_display_ring((void *)tx_q->dma_etx, 6223 priv->dma_conf.dma_tx_size, 1, seq, tx_q->dma_tx_phy); 6224 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 6225 seq_printf(seq, "Descriptor ring:\n"); 6226 sysfs_display_ring((void *)tx_q->dma_tx, 6227 priv->dma_conf.dma_tx_size, 0, seq, tx_q->dma_tx_phy); 6228 } 6229 } 6230 6231 return 0; 6232 } 6233 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 6234 6235 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 6236 { 6237 struct net_device *dev = seq->private; 6238 struct stmmac_priv *priv = netdev_priv(dev); 6239 6240 if (!priv->hw_cap_support) { 6241 seq_printf(seq, "DMA HW features not supported\n"); 6242 return 0; 6243 } 6244 6245 seq_printf(seq, "==============================\n"); 6246 seq_printf(seq, "\tDMA HW features\n"); 6247 seq_printf(seq, "==============================\n"); 6248 6249 seq_printf(seq, "\t10/100 Mbps: %s\n", 6250 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6251 seq_printf(seq, "\t1000 Mbps: %s\n", 6252 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6253 seq_printf(seq, "\tHalf duplex: %s\n", 6254 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6255 seq_printf(seq, "\tHash Filter: %s\n", 6256 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6257 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6258 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6259 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6260 (priv->dma_cap.pcs) ? "Y" : "N"); 6261 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6262 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6263 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6264 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6265 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6266 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6267 seq_printf(seq, "\tRMON module: %s\n", 6268 (priv->dma_cap.rmon) ? "Y" : "N"); 6269 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6270 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6271 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6272 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6273 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6274 (priv->dma_cap.eee) ? "Y" : "N"); 6275 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6276 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6277 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6278 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6279 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6280 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6281 } else { 6282 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6283 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6284 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6285 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6286 } 6287 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6288 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6289 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6290 priv->dma_cap.number_rx_channel); 6291 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6292 priv->dma_cap.number_tx_channel); 6293 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6294 priv->dma_cap.number_rx_queues); 6295 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6296 priv->dma_cap.number_tx_queues); 6297 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6298 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6299 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6300 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6301 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6302 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6303 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6304 priv->dma_cap.pps_out_num); 6305 seq_printf(seq, "\tSafety Features: %s\n", 6306 priv->dma_cap.asp ? "Y" : "N"); 6307 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6308 priv->dma_cap.frpsel ? "Y" : "N"); 6309 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6310 priv->dma_cap.host_dma_width); 6311 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6312 priv->dma_cap.rssen ? "Y" : "N"); 6313 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6314 priv->dma_cap.vlhash ? "Y" : "N"); 6315 seq_printf(seq, "\tSplit Header: %s\n", 6316 priv->dma_cap.sphen ? "Y" : "N"); 6317 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6318 priv->dma_cap.vlins ? "Y" : "N"); 6319 seq_printf(seq, "\tDouble VLAN: %s\n", 6320 priv->dma_cap.dvlan ? "Y" : "N"); 6321 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6322 priv->dma_cap.l3l4fnum); 6323 seq_printf(seq, "\tARP Offloading: %s\n", 6324 priv->dma_cap.arpoffsel ? "Y" : "N"); 6325 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6326 priv->dma_cap.estsel ? "Y" : "N"); 6327 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6328 priv->dma_cap.fpesel ? "Y" : "N"); 6329 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6330 priv->dma_cap.tbssel ? "Y" : "N"); 6331 return 0; 6332 } 6333 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6334 6335 /* Use network device events to rename debugfs file entries. 6336 */ 6337 static int stmmac_device_event(struct notifier_block *unused, 6338 unsigned long event, void *ptr) 6339 { 6340 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6341 struct stmmac_priv *priv = netdev_priv(dev); 6342 6343 if (dev->netdev_ops != &stmmac_netdev_ops) 6344 goto done; 6345 6346 switch (event) { 6347 case NETDEV_CHANGENAME: 6348 if (priv->dbgfs_dir) 6349 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6350 priv->dbgfs_dir, 6351 stmmac_fs_dir, 6352 dev->name); 6353 break; 6354 } 6355 done: 6356 return NOTIFY_DONE; 6357 } 6358 6359 static struct notifier_block stmmac_notifier = { 6360 .notifier_call = stmmac_device_event, 6361 }; 6362 6363 static void stmmac_init_fs(struct net_device *dev) 6364 { 6365 struct stmmac_priv *priv = netdev_priv(dev); 6366 6367 rtnl_lock(); 6368 6369 /* Create per netdev entries */ 6370 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6371 6372 /* Entry to report DMA RX/TX rings */ 6373 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6374 &stmmac_rings_status_fops); 6375 6376 /* Entry to report the DMA HW features */ 6377 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6378 &stmmac_dma_cap_fops); 6379 6380 rtnl_unlock(); 6381 } 6382 6383 static void stmmac_exit_fs(struct net_device *dev) 6384 { 6385 struct stmmac_priv *priv = netdev_priv(dev); 6386 6387 debugfs_remove_recursive(priv->dbgfs_dir); 6388 } 6389 #endif /* CONFIG_DEBUG_FS */ 6390 6391 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6392 { 6393 unsigned char *data = (unsigned char *)&vid_le; 6394 unsigned char data_byte = 0; 6395 u32 crc = ~0x0; 6396 u32 temp = 0; 6397 int i, bits; 6398 6399 bits = get_bitmask_order(VLAN_VID_MASK); 6400 for (i = 0; i < bits; i++) { 6401 if ((i % 8) == 0) 6402 data_byte = data[i / 8]; 6403 6404 temp = ((crc & 1) ^ data_byte) & 1; 6405 crc >>= 1; 6406 data_byte >>= 1; 6407 6408 if (temp) 6409 crc ^= 0xedb88320; 6410 } 6411 6412 return crc; 6413 } 6414 6415 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6416 { 6417 u32 crc, hash = 0; 6418 __le16 pmatch = 0; 6419 int count = 0; 6420 u16 vid = 0; 6421 6422 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6423 __le16 vid_le = cpu_to_le16(vid); 6424 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6425 hash |= (1 << crc); 6426 count++; 6427 } 6428 6429 if (!priv->dma_cap.vlhash) { 6430 if (count > 2) /* VID = 0 always passes filter */ 6431 return -EOPNOTSUPP; 6432 6433 pmatch = cpu_to_le16(vid); 6434 hash = 0; 6435 } 6436 6437 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6438 } 6439 6440 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6441 { 6442 struct stmmac_priv *priv = netdev_priv(ndev); 6443 bool is_double = false; 6444 int ret; 6445 6446 ret = pm_runtime_resume_and_get(priv->device); 6447 if (ret < 0) 6448 return ret; 6449 6450 if (be16_to_cpu(proto) == ETH_P_8021AD) 6451 is_double = true; 6452 6453 set_bit(vid, priv->active_vlans); 6454 ret = stmmac_vlan_update(priv, is_double); 6455 if (ret) { 6456 clear_bit(vid, priv->active_vlans); 6457 goto err_pm_put; 6458 } 6459 6460 if (priv->hw->num_vlan) { 6461 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6462 if (ret) 6463 goto err_pm_put; 6464 } 6465 err_pm_put: 6466 pm_runtime_put(priv->device); 6467 6468 return ret; 6469 } 6470 6471 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6472 { 6473 struct stmmac_priv *priv = netdev_priv(ndev); 6474 bool is_double = false; 6475 int ret; 6476 6477 ret = pm_runtime_resume_and_get(priv->device); 6478 if (ret < 0) 6479 return ret; 6480 6481 if (be16_to_cpu(proto) == ETH_P_8021AD) 6482 is_double = true; 6483 6484 clear_bit(vid, priv->active_vlans); 6485 6486 if (priv->hw->num_vlan) { 6487 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6488 if (ret) 6489 goto del_vlan_error; 6490 } 6491 6492 ret = stmmac_vlan_update(priv, is_double); 6493 6494 del_vlan_error: 6495 pm_runtime_put(priv->device); 6496 6497 return ret; 6498 } 6499 6500 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6501 { 6502 struct stmmac_priv *priv = netdev_priv(dev); 6503 6504 switch (bpf->command) { 6505 case XDP_SETUP_PROG: 6506 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6507 case XDP_SETUP_XSK_POOL: 6508 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6509 bpf->xsk.queue_id); 6510 default: 6511 return -EOPNOTSUPP; 6512 } 6513 } 6514 6515 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6516 struct xdp_frame **frames, u32 flags) 6517 { 6518 struct stmmac_priv *priv = netdev_priv(dev); 6519 int cpu = smp_processor_id(); 6520 struct netdev_queue *nq; 6521 int i, nxmit = 0; 6522 int queue; 6523 6524 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6525 return -ENETDOWN; 6526 6527 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6528 return -EINVAL; 6529 6530 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6531 nq = netdev_get_tx_queue(priv->dev, queue); 6532 6533 __netif_tx_lock(nq, cpu); 6534 /* Avoids TX time-out as we are sharing with slow path */ 6535 txq_trans_cond_update(nq); 6536 6537 for (i = 0; i < num_frames; i++) { 6538 int res; 6539 6540 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6541 if (res == STMMAC_XDP_CONSUMED) 6542 break; 6543 6544 nxmit++; 6545 } 6546 6547 if (flags & XDP_XMIT_FLUSH) { 6548 stmmac_flush_tx_descriptors(priv, queue); 6549 stmmac_tx_timer_arm(priv, queue); 6550 } 6551 6552 __netif_tx_unlock(nq); 6553 6554 return nxmit; 6555 } 6556 6557 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6558 { 6559 struct stmmac_channel *ch = &priv->channel[queue]; 6560 unsigned long flags; 6561 6562 spin_lock_irqsave(&ch->lock, flags); 6563 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6564 spin_unlock_irqrestore(&ch->lock, flags); 6565 6566 stmmac_stop_rx_dma(priv, queue); 6567 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6568 } 6569 6570 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6571 { 6572 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 6573 struct stmmac_channel *ch = &priv->channel[queue]; 6574 unsigned long flags; 6575 u32 buf_size; 6576 int ret; 6577 6578 ret = __alloc_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6579 if (ret) { 6580 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6581 return; 6582 } 6583 6584 ret = __init_dma_rx_desc_rings(priv, &priv->dma_conf, queue, GFP_KERNEL); 6585 if (ret) { 6586 __free_dma_rx_desc_resources(priv, &priv->dma_conf, queue); 6587 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6588 return; 6589 } 6590 6591 stmmac_reset_rx_queue(priv, queue); 6592 stmmac_clear_rx_descriptors(priv, &priv->dma_conf, queue); 6593 6594 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6595 rx_q->dma_rx_phy, rx_q->queue_index); 6596 6597 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6598 sizeof(struct dma_desc)); 6599 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6600 rx_q->rx_tail_addr, rx_q->queue_index); 6601 6602 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6603 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6604 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6605 buf_size, 6606 rx_q->queue_index); 6607 } else { 6608 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6609 priv->dma_conf.dma_buf_sz, 6610 rx_q->queue_index); 6611 } 6612 6613 stmmac_start_rx_dma(priv, queue); 6614 6615 spin_lock_irqsave(&ch->lock, flags); 6616 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6617 spin_unlock_irqrestore(&ch->lock, flags); 6618 } 6619 6620 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6621 { 6622 struct stmmac_channel *ch = &priv->channel[queue]; 6623 unsigned long flags; 6624 6625 spin_lock_irqsave(&ch->lock, flags); 6626 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6627 spin_unlock_irqrestore(&ch->lock, flags); 6628 6629 stmmac_stop_tx_dma(priv, queue); 6630 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6631 } 6632 6633 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6634 { 6635 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 6636 struct stmmac_channel *ch = &priv->channel[queue]; 6637 unsigned long flags; 6638 int ret; 6639 6640 ret = __alloc_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6641 if (ret) { 6642 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6643 return; 6644 } 6645 6646 ret = __init_dma_tx_desc_rings(priv, &priv->dma_conf, queue); 6647 if (ret) { 6648 __free_dma_tx_desc_resources(priv, &priv->dma_conf, queue); 6649 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6650 return; 6651 } 6652 6653 stmmac_reset_tx_queue(priv, queue); 6654 stmmac_clear_tx_descriptors(priv, &priv->dma_conf, queue); 6655 6656 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6657 tx_q->dma_tx_phy, tx_q->queue_index); 6658 6659 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6660 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6661 6662 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6663 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6664 tx_q->tx_tail_addr, tx_q->queue_index); 6665 6666 stmmac_start_tx_dma(priv, queue); 6667 6668 spin_lock_irqsave(&ch->lock, flags); 6669 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6670 spin_unlock_irqrestore(&ch->lock, flags); 6671 } 6672 6673 void stmmac_xdp_release(struct net_device *dev) 6674 { 6675 struct stmmac_priv *priv = netdev_priv(dev); 6676 u32 chan; 6677 6678 /* Ensure tx function is not running */ 6679 netif_tx_disable(dev); 6680 6681 /* Disable NAPI process */ 6682 stmmac_disable_all_queues(priv); 6683 6684 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6685 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6686 6687 /* Free the IRQ lines */ 6688 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 6689 6690 /* Stop TX/RX DMA channels */ 6691 stmmac_stop_all_dma(priv); 6692 6693 /* Release and free the Rx/Tx resources */ 6694 free_dma_desc_resources(priv, &priv->dma_conf); 6695 6696 /* Disable the MAC Rx/Tx */ 6697 stmmac_mac_set(priv, priv->ioaddr, false); 6698 6699 /* set trans_start so we don't get spurious 6700 * watchdogs during reset 6701 */ 6702 netif_trans_update(dev); 6703 netif_carrier_off(dev); 6704 } 6705 6706 int stmmac_xdp_open(struct net_device *dev) 6707 { 6708 struct stmmac_priv *priv = netdev_priv(dev); 6709 u32 rx_cnt = priv->plat->rx_queues_to_use; 6710 u32 tx_cnt = priv->plat->tx_queues_to_use; 6711 u32 dma_csr_ch = max(rx_cnt, tx_cnt); 6712 struct stmmac_rx_queue *rx_q; 6713 struct stmmac_tx_queue *tx_q; 6714 u32 buf_size; 6715 bool sph_en; 6716 u32 chan; 6717 int ret; 6718 6719 ret = alloc_dma_desc_resources(priv, &priv->dma_conf); 6720 if (ret < 0) { 6721 netdev_err(dev, "%s: DMA descriptors allocation failed\n", 6722 __func__); 6723 goto dma_desc_error; 6724 } 6725 6726 ret = init_dma_desc_rings(dev, &priv->dma_conf, GFP_KERNEL); 6727 if (ret < 0) { 6728 netdev_err(dev, "%s: DMA descriptors initialization failed\n", 6729 __func__); 6730 goto init_error; 6731 } 6732 6733 stmmac_reset_queues_param(priv); 6734 6735 /* DMA CSR Channel configuration */ 6736 for (chan = 0; chan < dma_csr_ch; chan++) { 6737 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 6738 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 6739 } 6740 6741 /* Adjust Split header */ 6742 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 6743 6744 /* DMA RX Channel Configuration */ 6745 for (chan = 0; chan < rx_cnt; chan++) { 6746 rx_q = &priv->dma_conf.rx_queue[chan]; 6747 6748 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6749 rx_q->dma_rx_phy, chan); 6750 6751 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 6752 (rx_q->buf_alloc_num * 6753 sizeof(struct dma_desc)); 6754 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6755 rx_q->rx_tail_addr, chan); 6756 6757 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6758 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6759 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6760 buf_size, 6761 rx_q->queue_index); 6762 } else { 6763 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6764 priv->dma_conf.dma_buf_sz, 6765 rx_q->queue_index); 6766 } 6767 6768 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 6769 } 6770 6771 /* DMA TX Channel Configuration */ 6772 for (chan = 0; chan < tx_cnt; chan++) { 6773 tx_q = &priv->dma_conf.tx_queue[chan]; 6774 6775 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6776 tx_q->dma_tx_phy, chan); 6777 6778 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6779 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6780 tx_q->tx_tail_addr, chan); 6781 6782 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 6783 tx_q->txtimer.function = stmmac_tx_timer; 6784 } 6785 6786 /* Enable the MAC Rx/Tx */ 6787 stmmac_mac_set(priv, priv->ioaddr, true); 6788 6789 /* Start Rx & Tx DMA Channels */ 6790 stmmac_start_all_dma(priv); 6791 6792 ret = stmmac_request_irq(dev); 6793 if (ret) 6794 goto irq_error; 6795 6796 /* Enable NAPI process*/ 6797 stmmac_enable_all_queues(priv); 6798 netif_carrier_on(dev); 6799 netif_tx_start_all_queues(dev); 6800 stmmac_enable_all_dma_irq(priv); 6801 6802 return 0; 6803 6804 irq_error: 6805 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 6806 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 6807 6808 stmmac_hw_teardown(dev); 6809 init_error: 6810 free_dma_desc_resources(priv, &priv->dma_conf); 6811 dma_desc_error: 6812 return ret; 6813 } 6814 6815 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6816 { 6817 struct stmmac_priv *priv = netdev_priv(dev); 6818 struct stmmac_rx_queue *rx_q; 6819 struct stmmac_tx_queue *tx_q; 6820 struct stmmac_channel *ch; 6821 6822 if (test_bit(STMMAC_DOWN, &priv->state) || 6823 !netif_carrier_ok(priv->dev)) 6824 return -ENETDOWN; 6825 6826 if (!stmmac_xdp_is_enabled(priv)) 6827 return -EINVAL; 6828 6829 if (queue >= priv->plat->rx_queues_to_use || 6830 queue >= priv->plat->tx_queues_to_use) 6831 return -EINVAL; 6832 6833 rx_q = &priv->dma_conf.rx_queue[queue]; 6834 tx_q = &priv->dma_conf.tx_queue[queue]; 6835 ch = &priv->channel[queue]; 6836 6837 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6838 return -EINVAL; 6839 6840 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6841 /* EQoS does not have per-DMA channel SW interrupt, 6842 * so we schedule RX Napi straight-away. 6843 */ 6844 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6845 __napi_schedule(&ch->rxtx_napi); 6846 } 6847 6848 return 0; 6849 } 6850 6851 static void stmmac_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 6852 { 6853 struct stmmac_priv *priv = netdev_priv(dev); 6854 u32 tx_cnt = priv->plat->tx_queues_to_use; 6855 u32 rx_cnt = priv->plat->rx_queues_to_use; 6856 unsigned int start; 6857 int q; 6858 6859 for (q = 0; q < tx_cnt; q++) { 6860 struct stmmac_txq_stats *txq_stats = &priv->dma_conf.tx_queue[q].txq_stats; 6861 u64 tx_packets; 6862 u64 tx_bytes; 6863 6864 do { 6865 start = u64_stats_fetch_begin(&txq_stats->syncp); 6866 tx_packets = txq_stats->tx_packets; 6867 tx_bytes = txq_stats->tx_bytes; 6868 } while (u64_stats_fetch_retry(&txq_stats->syncp, start)); 6869 6870 stats->tx_packets += tx_packets; 6871 stats->tx_bytes += tx_bytes; 6872 } 6873 6874 for (q = 0; q < rx_cnt; q++) { 6875 struct stmmac_rxq_stats *rxq_stats = &priv->dma_conf.rx_queue[q].rxq_stats; 6876 u64 rx_packets; 6877 u64 rx_bytes; 6878 6879 do { 6880 start = u64_stats_fetch_begin(&rxq_stats->syncp); 6881 rx_packets = rxq_stats->rx_packets; 6882 rx_bytes = rxq_stats->rx_bytes; 6883 } while (u64_stats_fetch_retry(&rxq_stats->syncp, start)); 6884 6885 stats->rx_packets += rx_packets; 6886 stats->rx_bytes += rx_bytes; 6887 } 6888 6889 stats->rx_dropped = priv->xstats.rx_dropped; 6890 stats->rx_errors = priv->xstats.rx_errors; 6891 stats->tx_dropped = priv->xstats.tx_dropped; 6892 stats->tx_errors = priv->xstats.tx_errors; 6893 stats->tx_carrier_errors = priv->xstats.tx_losscarrier + priv->xstats.tx_carrier; 6894 stats->collisions = priv->xstats.tx_collision + priv->xstats.rx_collision; 6895 stats->rx_length_errors = priv->xstats.rx_length; 6896 stats->rx_crc_errors = priv->xstats.rx_crc_errors; 6897 stats->rx_over_errors = priv->xstats.rx_overflow_cntr; 6898 stats->rx_missed_errors = priv->xstats.rx_missed_cntr; 6899 } 6900 6901 static const struct net_device_ops stmmac_netdev_ops = { 6902 .ndo_open = stmmac_open, 6903 .ndo_start_xmit = stmmac_xmit, 6904 .ndo_stop = stmmac_release, 6905 .ndo_change_mtu = stmmac_change_mtu, 6906 .ndo_fix_features = stmmac_fix_features, 6907 .ndo_set_features = stmmac_set_features, 6908 .ndo_set_rx_mode = stmmac_set_rx_mode, 6909 .ndo_tx_timeout = stmmac_tx_timeout, 6910 .ndo_eth_ioctl = stmmac_ioctl, 6911 .ndo_get_stats64 = stmmac_get_stats64, 6912 .ndo_setup_tc = stmmac_setup_tc, 6913 .ndo_select_queue = stmmac_select_queue, 6914 #ifdef CONFIG_NET_POLL_CONTROLLER 6915 .ndo_poll_controller = stmmac_poll_controller, 6916 #endif 6917 .ndo_set_mac_address = stmmac_set_mac_address, 6918 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6919 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6920 .ndo_bpf = stmmac_bpf, 6921 .ndo_xdp_xmit = stmmac_xdp_xmit, 6922 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6923 }; 6924 6925 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6926 { 6927 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6928 return; 6929 if (test_bit(STMMAC_DOWN, &priv->state)) 6930 return; 6931 6932 netdev_err(priv->dev, "Reset adapter.\n"); 6933 6934 rtnl_lock(); 6935 netif_trans_update(priv->dev); 6936 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6937 usleep_range(1000, 2000); 6938 6939 set_bit(STMMAC_DOWN, &priv->state); 6940 dev_close(priv->dev); 6941 dev_open(priv->dev, NULL); 6942 clear_bit(STMMAC_DOWN, &priv->state); 6943 clear_bit(STMMAC_RESETING, &priv->state); 6944 rtnl_unlock(); 6945 } 6946 6947 static void stmmac_service_task(struct work_struct *work) 6948 { 6949 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6950 service_task); 6951 6952 stmmac_reset_subtask(priv); 6953 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6954 } 6955 6956 /** 6957 * stmmac_hw_init - Init the MAC device 6958 * @priv: driver private structure 6959 * Description: this function is to configure the MAC device according to 6960 * some platform parameters or the HW capability register. It prepares the 6961 * driver to use either ring or chain modes and to setup either enhanced or 6962 * normal descriptors. 6963 */ 6964 static int stmmac_hw_init(struct stmmac_priv *priv) 6965 { 6966 int ret; 6967 6968 /* dwmac-sun8i only work in chain mode */ 6969 if (priv->plat->flags & STMMAC_FLAG_HAS_SUN8I) 6970 chain_mode = 1; 6971 priv->chain_mode = chain_mode; 6972 6973 /* Initialize HW Interface */ 6974 ret = stmmac_hwif_init(priv); 6975 if (ret) 6976 return ret; 6977 6978 /* Get the HW capability (new GMAC newer than 3.50a) */ 6979 priv->hw_cap_support = stmmac_get_hw_features(priv); 6980 if (priv->hw_cap_support) { 6981 dev_info(priv->device, "DMA HW capability register supported\n"); 6982 6983 /* We can override some gmac/dma configuration fields: e.g. 6984 * enh_desc, tx_coe (e.g. that are passed through the 6985 * platform) with the values from the HW capability 6986 * register (if supported). 6987 */ 6988 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6989 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up && 6990 !(priv->plat->flags & STMMAC_FLAG_USE_PHY_WOL); 6991 priv->hw->pmt = priv->plat->pmt; 6992 if (priv->dma_cap.hash_tb_sz) { 6993 priv->hw->multicast_filter_bins = 6994 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6995 priv->hw->mcast_bits_log2 = 6996 ilog2(priv->hw->multicast_filter_bins); 6997 } 6998 6999 /* TXCOE doesn't work in thresh DMA mode */ 7000 if (priv->plat->force_thresh_dma_mode) 7001 priv->plat->tx_coe = 0; 7002 else 7003 priv->plat->tx_coe = priv->dma_cap.tx_coe; 7004 7005 /* In case of GMAC4 rx_coe is from HW cap register. */ 7006 priv->plat->rx_coe = priv->dma_cap.rx_coe; 7007 7008 if (priv->dma_cap.rx_coe_type2) 7009 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 7010 else if (priv->dma_cap.rx_coe_type1) 7011 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 7012 7013 } else { 7014 dev_info(priv->device, "No HW DMA feature register supported\n"); 7015 } 7016 7017 if (priv->plat->rx_coe) { 7018 priv->hw->rx_csum = priv->plat->rx_coe; 7019 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 7020 if (priv->synopsys_id < DWMAC_CORE_4_00) 7021 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 7022 } 7023 if (priv->plat->tx_coe) 7024 dev_info(priv->device, "TX Checksum insertion supported\n"); 7025 7026 if (priv->plat->pmt) { 7027 dev_info(priv->device, "Wake-Up On Lan supported\n"); 7028 device_set_wakeup_capable(priv->device, 1); 7029 } 7030 7031 if (priv->dma_cap.tsoen) 7032 dev_info(priv->device, "TSO supported\n"); 7033 7034 priv->hw->vlan_fail_q_en = 7035 (priv->plat->flags & STMMAC_FLAG_VLAN_FAIL_Q_EN); 7036 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 7037 7038 /* Run HW quirks, if any */ 7039 if (priv->hwif_quirks) { 7040 ret = priv->hwif_quirks(priv); 7041 if (ret) 7042 return ret; 7043 } 7044 7045 /* Rx Watchdog is available in the COREs newer than the 3.40. 7046 * In some case, for example on bugged HW this feature 7047 * has to be disable and this can be done by passing the 7048 * riwt_off field from the platform. 7049 */ 7050 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 7051 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 7052 priv->use_riwt = 1; 7053 dev_info(priv->device, 7054 "Enable RX Mitigation via HW Watchdog Timer\n"); 7055 } 7056 7057 return 0; 7058 } 7059 7060 static void stmmac_napi_add(struct net_device *dev) 7061 { 7062 struct stmmac_priv *priv = netdev_priv(dev); 7063 u32 queue, maxq; 7064 7065 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 7066 7067 for (queue = 0; queue < maxq; queue++) { 7068 struct stmmac_channel *ch = &priv->channel[queue]; 7069 7070 ch->priv_data = priv; 7071 ch->index = queue; 7072 spin_lock_init(&ch->lock); 7073 7074 if (queue < priv->plat->rx_queues_to_use) { 7075 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx); 7076 } 7077 if (queue < priv->plat->tx_queues_to_use) { 7078 netif_napi_add_tx(dev, &ch->tx_napi, 7079 stmmac_napi_poll_tx); 7080 } 7081 if (queue < priv->plat->rx_queues_to_use && 7082 queue < priv->plat->tx_queues_to_use) { 7083 netif_napi_add(dev, &ch->rxtx_napi, 7084 stmmac_napi_poll_rxtx); 7085 } 7086 } 7087 } 7088 7089 static void stmmac_napi_del(struct net_device *dev) 7090 { 7091 struct stmmac_priv *priv = netdev_priv(dev); 7092 u32 queue, maxq; 7093 7094 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 7095 7096 for (queue = 0; queue < maxq; queue++) { 7097 struct stmmac_channel *ch = &priv->channel[queue]; 7098 7099 if (queue < priv->plat->rx_queues_to_use) 7100 netif_napi_del(&ch->rx_napi); 7101 if (queue < priv->plat->tx_queues_to_use) 7102 netif_napi_del(&ch->tx_napi); 7103 if (queue < priv->plat->rx_queues_to_use && 7104 queue < priv->plat->tx_queues_to_use) { 7105 netif_napi_del(&ch->rxtx_napi); 7106 } 7107 } 7108 } 7109 7110 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 7111 { 7112 struct stmmac_priv *priv = netdev_priv(dev); 7113 int ret = 0, i; 7114 7115 if (netif_running(dev)) 7116 stmmac_release(dev); 7117 7118 stmmac_napi_del(dev); 7119 7120 priv->plat->rx_queues_to_use = rx_cnt; 7121 priv->plat->tx_queues_to_use = tx_cnt; 7122 if (!netif_is_rxfh_configured(dev)) 7123 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7124 priv->rss.table[i] = ethtool_rxfh_indir_default(i, 7125 rx_cnt); 7126 7127 stmmac_napi_add(dev); 7128 7129 if (netif_running(dev)) 7130 ret = stmmac_open(dev); 7131 7132 return ret; 7133 } 7134 7135 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 7136 { 7137 struct stmmac_priv *priv = netdev_priv(dev); 7138 int ret = 0; 7139 7140 if (netif_running(dev)) 7141 stmmac_release(dev); 7142 7143 priv->dma_conf.dma_rx_size = rx_size; 7144 priv->dma_conf.dma_tx_size = tx_size; 7145 7146 if (netif_running(dev)) 7147 ret = stmmac_open(dev); 7148 7149 return ret; 7150 } 7151 7152 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 7153 static void stmmac_fpe_lp_task(struct work_struct *work) 7154 { 7155 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 7156 fpe_task); 7157 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 7158 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 7159 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 7160 bool *hs_enable = &fpe_cfg->hs_enable; 7161 bool *enable = &fpe_cfg->enable; 7162 int retries = 20; 7163 7164 while (retries-- > 0) { 7165 /* Bail out immediately if FPE handshake is OFF */ 7166 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 7167 break; 7168 7169 if (*lo_state == FPE_STATE_ENTERING_ON && 7170 *lp_state == FPE_STATE_ENTERING_ON) { 7171 stmmac_fpe_configure(priv, priv->ioaddr, 7172 priv->plat->tx_queues_to_use, 7173 priv->plat->rx_queues_to_use, 7174 *enable); 7175 7176 netdev_info(priv->dev, "configured FPE\n"); 7177 7178 *lo_state = FPE_STATE_ON; 7179 *lp_state = FPE_STATE_ON; 7180 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 7181 break; 7182 } 7183 7184 if ((*lo_state == FPE_STATE_CAPABLE || 7185 *lo_state == FPE_STATE_ENTERING_ON) && 7186 *lp_state != FPE_STATE_ON) { 7187 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 7188 *lo_state, *lp_state); 7189 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7190 MPACKET_VERIFY); 7191 } 7192 /* Sleep then retry */ 7193 msleep(500); 7194 } 7195 7196 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 7197 } 7198 7199 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 7200 { 7201 if (priv->plat->fpe_cfg->hs_enable != enable) { 7202 if (enable) { 7203 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 7204 MPACKET_VERIFY); 7205 } else { 7206 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 7207 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 7208 } 7209 7210 priv->plat->fpe_cfg->hs_enable = enable; 7211 } 7212 } 7213 7214 static int stmmac_xdp_rx_timestamp(const struct xdp_md *_ctx, u64 *timestamp) 7215 { 7216 const struct stmmac_xdp_buff *ctx = (void *)_ctx; 7217 struct dma_desc *desc_contains_ts = ctx->desc; 7218 struct stmmac_priv *priv = ctx->priv; 7219 struct dma_desc *ndesc = ctx->ndesc; 7220 struct dma_desc *desc = ctx->desc; 7221 u64 ns = 0; 7222 7223 if (!priv->hwts_rx_en) 7224 return -ENODATA; 7225 7226 /* For GMAC4, the valid timestamp is from CTX next desc. */ 7227 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 7228 desc_contains_ts = ndesc; 7229 7230 /* Check if timestamp is available */ 7231 if (stmmac_get_rx_timestamp_status(priv, desc, ndesc, priv->adv_ts)) { 7232 stmmac_get_timestamp(priv, desc_contains_ts, priv->adv_ts, &ns); 7233 ns -= priv->plat->cdc_error_adj; 7234 *timestamp = ns_to_ktime(ns); 7235 return 0; 7236 } 7237 7238 return -ENODATA; 7239 } 7240 7241 static const struct xdp_metadata_ops stmmac_xdp_metadata_ops = { 7242 .xmo_rx_timestamp = stmmac_xdp_rx_timestamp, 7243 }; 7244 7245 /** 7246 * stmmac_dvr_probe 7247 * @device: device pointer 7248 * @plat_dat: platform data pointer 7249 * @res: stmmac resource pointer 7250 * Description: this is the main probe function used to 7251 * call the alloc_etherdev, allocate the priv structure. 7252 * Return: 7253 * returns 0 on success, otherwise errno. 7254 */ 7255 int stmmac_dvr_probe(struct device *device, 7256 struct plat_stmmacenet_data *plat_dat, 7257 struct stmmac_resources *res) 7258 { 7259 struct net_device *ndev = NULL; 7260 struct stmmac_priv *priv; 7261 u32 rxq; 7262 int i, ret = 0; 7263 7264 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 7265 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 7266 if (!ndev) 7267 return -ENOMEM; 7268 7269 SET_NETDEV_DEV(ndev, device); 7270 7271 priv = netdev_priv(ndev); 7272 priv->device = device; 7273 priv->dev = ndev; 7274 7275 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7276 u64_stats_init(&priv->dma_conf.rx_queue[i].rxq_stats.syncp); 7277 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7278 u64_stats_init(&priv->dma_conf.tx_queue[i].txq_stats.syncp); 7279 7280 stmmac_set_ethtool_ops(ndev); 7281 priv->pause = pause; 7282 priv->plat = plat_dat; 7283 priv->ioaddr = res->addr; 7284 priv->dev->base_addr = (unsigned long)res->addr; 7285 priv->plat->dma_cfg->multi_msi_en = 7286 (priv->plat->flags & STMMAC_FLAG_MULTI_MSI_EN); 7287 7288 priv->dev->irq = res->irq; 7289 priv->wol_irq = res->wol_irq; 7290 priv->lpi_irq = res->lpi_irq; 7291 priv->sfty_ce_irq = res->sfty_ce_irq; 7292 priv->sfty_ue_irq = res->sfty_ue_irq; 7293 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 7294 priv->rx_irq[i] = res->rx_irq[i]; 7295 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 7296 priv->tx_irq[i] = res->tx_irq[i]; 7297 7298 if (!is_zero_ether_addr(res->mac)) 7299 eth_hw_addr_set(priv->dev, res->mac); 7300 7301 dev_set_drvdata(device, priv->dev); 7302 7303 /* Verify driver arguments */ 7304 stmmac_verify_args(); 7305 7306 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 7307 if (!priv->af_xdp_zc_qps) 7308 return -ENOMEM; 7309 7310 /* Allocate workqueue */ 7311 priv->wq = create_singlethread_workqueue("stmmac_wq"); 7312 if (!priv->wq) { 7313 dev_err(priv->device, "failed to create workqueue\n"); 7314 ret = -ENOMEM; 7315 goto error_wq_init; 7316 } 7317 7318 INIT_WORK(&priv->service_task, stmmac_service_task); 7319 7320 /* Initialize Link Partner FPE workqueue */ 7321 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 7322 7323 /* Override with kernel parameters if supplied XXX CRS XXX 7324 * this needs to have multiple instances 7325 */ 7326 if ((phyaddr >= 0) && (phyaddr <= 31)) 7327 priv->plat->phy_addr = phyaddr; 7328 7329 if (priv->plat->stmmac_rst) { 7330 ret = reset_control_assert(priv->plat->stmmac_rst); 7331 reset_control_deassert(priv->plat->stmmac_rst); 7332 /* Some reset controllers have only reset callback instead of 7333 * assert + deassert callbacks pair. 7334 */ 7335 if (ret == -ENOTSUPP) 7336 reset_control_reset(priv->plat->stmmac_rst); 7337 } 7338 7339 ret = reset_control_deassert(priv->plat->stmmac_ahb_rst); 7340 if (ret == -ENOTSUPP) 7341 dev_err(priv->device, "unable to bring out of ahb reset: %pe\n", 7342 ERR_PTR(ret)); 7343 7344 /* Init MAC and get the capabilities */ 7345 ret = stmmac_hw_init(priv); 7346 if (ret) 7347 goto error_hw_init; 7348 7349 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 7350 */ 7351 if (priv->synopsys_id < DWMAC_CORE_5_20) 7352 priv->plat->dma_cfg->dche = false; 7353 7354 stmmac_check_ether_addr(priv); 7355 7356 ndev->netdev_ops = &stmmac_netdev_ops; 7357 7358 ndev->xdp_metadata_ops = &stmmac_xdp_metadata_ops; 7359 7360 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 7361 NETIF_F_RXCSUM; 7362 ndev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 7363 NETDEV_XDP_ACT_XSK_ZEROCOPY; 7364 7365 ret = stmmac_tc_init(priv, priv); 7366 if (!ret) { 7367 ndev->hw_features |= NETIF_F_HW_TC; 7368 } 7369 7370 if ((priv->plat->flags & STMMAC_FLAG_TSO_EN) && (priv->dma_cap.tsoen)) { 7371 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 7372 if (priv->plat->has_gmac4) 7373 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 7374 priv->tso = true; 7375 dev_info(priv->device, "TSO feature enabled\n"); 7376 } 7377 7378 if (priv->dma_cap.sphen && 7379 !(priv->plat->flags & STMMAC_FLAG_SPH_DISABLE)) { 7380 ndev->hw_features |= NETIF_F_GRO; 7381 priv->sph_cap = true; 7382 priv->sph = priv->sph_cap; 7383 dev_info(priv->device, "SPH feature enabled\n"); 7384 } 7385 7386 /* Ideally our host DMA address width is the same as for the 7387 * device. However, it may differ and then we have to use our 7388 * host DMA width for allocation and the device DMA width for 7389 * register handling. 7390 */ 7391 if (priv->plat->host_dma_width) 7392 priv->dma_cap.host_dma_width = priv->plat->host_dma_width; 7393 else 7394 priv->dma_cap.host_dma_width = priv->dma_cap.addr64; 7395 7396 if (priv->dma_cap.host_dma_width) { 7397 ret = dma_set_mask_and_coherent(device, 7398 DMA_BIT_MASK(priv->dma_cap.host_dma_width)); 7399 if (!ret) { 7400 dev_info(priv->device, "Using %d/%d bits DMA host/device width\n", 7401 priv->dma_cap.host_dma_width, priv->dma_cap.addr64); 7402 7403 /* 7404 * If more than 32 bits can be addressed, make sure to 7405 * enable enhanced addressing mode. 7406 */ 7407 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 7408 priv->plat->dma_cfg->eame = true; 7409 } else { 7410 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 7411 if (ret) { 7412 dev_err(priv->device, "Failed to set DMA Mask\n"); 7413 goto error_hw_init; 7414 } 7415 7416 priv->dma_cap.host_dma_width = 32; 7417 } 7418 } 7419 7420 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 7421 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 7422 #ifdef STMMAC_VLAN_TAG_USED 7423 /* Both mac100 and gmac support receive VLAN tag detection */ 7424 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 7425 if (priv->dma_cap.vlhash) { 7426 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 7427 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 7428 } 7429 if (priv->dma_cap.vlins) { 7430 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 7431 if (priv->dma_cap.dvlan) 7432 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 7433 } 7434 #endif 7435 priv->msg_enable = netif_msg_init(debug, default_msg_level); 7436 7437 priv->xstats.threshold = tc; 7438 7439 /* Initialize RSS */ 7440 rxq = priv->plat->rx_queues_to_use; 7441 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 7442 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 7443 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 7444 7445 if (priv->dma_cap.rssen && priv->plat->rss_en) 7446 ndev->features |= NETIF_F_RXHASH; 7447 7448 ndev->vlan_features |= ndev->features; 7449 /* TSO doesn't work on VLANs yet */ 7450 ndev->vlan_features &= ~NETIF_F_TSO; 7451 7452 /* MTU range: 46 - hw-specific max */ 7453 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 7454 if (priv->plat->has_xgmac) 7455 ndev->max_mtu = XGMAC_JUMBO_LEN; 7456 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 7457 ndev->max_mtu = JUMBO_LEN; 7458 else 7459 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 7460 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 7461 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 7462 */ 7463 if ((priv->plat->maxmtu < ndev->max_mtu) && 7464 (priv->plat->maxmtu >= ndev->min_mtu)) 7465 ndev->max_mtu = priv->plat->maxmtu; 7466 else if (priv->plat->maxmtu < ndev->min_mtu) 7467 dev_warn(priv->device, 7468 "%s: warning: maxmtu having invalid value (%d)\n", 7469 __func__, priv->plat->maxmtu); 7470 7471 if (flow_ctrl) 7472 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 7473 7474 ndev->priv_flags |= IFF_LIVE_ADDR_CHANGE; 7475 7476 /* Setup channels NAPI */ 7477 stmmac_napi_add(ndev); 7478 7479 mutex_init(&priv->lock); 7480 7481 /* If a specific clk_csr value is passed from the platform 7482 * this means that the CSR Clock Range selection cannot be 7483 * changed at run-time and it is fixed. Viceversa the driver'll try to 7484 * set the MDC clock dynamically according to the csr actual 7485 * clock input. 7486 */ 7487 if (priv->plat->clk_csr >= 0) 7488 priv->clk_csr = priv->plat->clk_csr; 7489 else 7490 stmmac_clk_csr_set(priv); 7491 7492 stmmac_check_pcs_mode(priv); 7493 7494 pm_runtime_get_noresume(device); 7495 pm_runtime_set_active(device); 7496 if (!pm_runtime_enabled(device)) 7497 pm_runtime_enable(device); 7498 7499 if (priv->hw->pcs != STMMAC_PCS_TBI && 7500 priv->hw->pcs != STMMAC_PCS_RTBI) { 7501 /* MDIO bus Registration */ 7502 ret = stmmac_mdio_register(ndev); 7503 if (ret < 0) { 7504 dev_err_probe(priv->device, ret, 7505 "%s: MDIO bus (id: %d) registration failed\n", 7506 __func__, priv->plat->bus_id); 7507 goto error_mdio_register; 7508 } 7509 } 7510 7511 if (priv->plat->speed_mode_2500) 7512 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7513 7514 if (priv->plat->mdio_bus_data && priv->plat->mdio_bus_data->has_xpcs) { 7515 ret = stmmac_xpcs_setup(priv->mii); 7516 if (ret) 7517 goto error_xpcs_setup; 7518 } 7519 7520 ret = stmmac_phy_setup(priv); 7521 if (ret) { 7522 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7523 goto error_phy_setup; 7524 } 7525 7526 ret = register_netdev(ndev); 7527 if (ret) { 7528 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7529 __func__, ret); 7530 goto error_netdev_register; 7531 } 7532 7533 #ifdef CONFIG_DEBUG_FS 7534 stmmac_init_fs(ndev); 7535 #endif 7536 7537 if (priv->plat->dump_debug_regs) 7538 priv->plat->dump_debug_regs(priv->plat->bsp_priv); 7539 7540 /* Let pm_runtime_put() disable the clocks. 7541 * If CONFIG_PM is not enabled, the clocks will stay powered. 7542 */ 7543 pm_runtime_put(device); 7544 7545 return ret; 7546 7547 error_netdev_register: 7548 phylink_destroy(priv->phylink); 7549 error_xpcs_setup: 7550 error_phy_setup: 7551 if (priv->hw->pcs != STMMAC_PCS_TBI && 7552 priv->hw->pcs != STMMAC_PCS_RTBI) 7553 stmmac_mdio_unregister(ndev); 7554 error_mdio_register: 7555 stmmac_napi_del(ndev); 7556 error_hw_init: 7557 destroy_workqueue(priv->wq); 7558 error_wq_init: 7559 bitmap_free(priv->af_xdp_zc_qps); 7560 7561 return ret; 7562 } 7563 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7564 7565 /** 7566 * stmmac_dvr_remove 7567 * @dev: device pointer 7568 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7569 * changes the link status, releases the DMA descriptor rings. 7570 */ 7571 void stmmac_dvr_remove(struct device *dev) 7572 { 7573 struct net_device *ndev = dev_get_drvdata(dev); 7574 struct stmmac_priv *priv = netdev_priv(ndev); 7575 7576 netdev_info(priv->dev, "%s: removing driver", __func__); 7577 7578 pm_runtime_get_sync(dev); 7579 7580 stmmac_stop_all_dma(priv); 7581 stmmac_mac_set(priv, priv->ioaddr, false); 7582 netif_carrier_off(ndev); 7583 unregister_netdev(ndev); 7584 7585 #ifdef CONFIG_DEBUG_FS 7586 stmmac_exit_fs(ndev); 7587 #endif 7588 phylink_destroy(priv->phylink); 7589 if (priv->plat->stmmac_rst) 7590 reset_control_assert(priv->plat->stmmac_rst); 7591 reset_control_assert(priv->plat->stmmac_ahb_rst); 7592 if (priv->hw->pcs != STMMAC_PCS_TBI && 7593 priv->hw->pcs != STMMAC_PCS_RTBI) 7594 stmmac_mdio_unregister(ndev); 7595 destroy_workqueue(priv->wq); 7596 mutex_destroy(&priv->lock); 7597 bitmap_free(priv->af_xdp_zc_qps); 7598 7599 pm_runtime_disable(dev); 7600 pm_runtime_put_noidle(dev); 7601 } 7602 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7603 7604 /** 7605 * stmmac_suspend - suspend callback 7606 * @dev: device pointer 7607 * Description: this is the function to suspend the device and it is called 7608 * by the platform driver to stop the network queue, release the resources, 7609 * program the PMT register (for WoL), clean and release driver resources. 7610 */ 7611 int stmmac_suspend(struct device *dev) 7612 { 7613 struct net_device *ndev = dev_get_drvdata(dev); 7614 struct stmmac_priv *priv = netdev_priv(ndev); 7615 u32 chan; 7616 7617 if (!ndev || !netif_running(ndev)) 7618 return 0; 7619 7620 mutex_lock(&priv->lock); 7621 7622 netif_device_detach(ndev); 7623 7624 stmmac_disable_all_queues(priv); 7625 7626 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7627 hrtimer_cancel(&priv->dma_conf.tx_queue[chan].txtimer); 7628 7629 if (priv->eee_enabled) { 7630 priv->tx_path_in_lpi_mode = false; 7631 del_timer_sync(&priv->eee_ctrl_timer); 7632 } 7633 7634 /* Stop TX/RX DMA */ 7635 stmmac_stop_all_dma(priv); 7636 7637 if (priv->plat->serdes_powerdown) 7638 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7639 7640 /* Enable Power down mode by programming the PMT regs */ 7641 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7642 stmmac_pmt(priv, priv->hw, priv->wolopts); 7643 priv->irq_wake = 1; 7644 } else { 7645 stmmac_mac_set(priv, priv->ioaddr, false); 7646 pinctrl_pm_select_sleep_state(priv->device); 7647 } 7648 7649 mutex_unlock(&priv->lock); 7650 7651 rtnl_lock(); 7652 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7653 phylink_suspend(priv->phylink, true); 7654 } else { 7655 if (device_may_wakeup(priv->device)) 7656 phylink_speed_down(priv->phylink, false); 7657 phylink_suspend(priv->phylink, false); 7658 } 7659 rtnl_unlock(); 7660 7661 if (priv->dma_cap.fpesel) { 7662 /* Disable FPE */ 7663 stmmac_fpe_configure(priv, priv->ioaddr, 7664 priv->plat->tx_queues_to_use, 7665 priv->plat->rx_queues_to_use, false); 7666 7667 stmmac_fpe_handshake(priv, false); 7668 stmmac_fpe_stop_wq(priv); 7669 } 7670 7671 priv->speed = SPEED_UNKNOWN; 7672 return 0; 7673 } 7674 EXPORT_SYMBOL_GPL(stmmac_suspend); 7675 7676 static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) 7677 { 7678 struct stmmac_rx_queue *rx_q = &priv->dma_conf.rx_queue[queue]; 7679 7680 rx_q->cur_rx = 0; 7681 rx_q->dirty_rx = 0; 7682 } 7683 7684 static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) 7685 { 7686 struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; 7687 7688 tx_q->cur_tx = 0; 7689 tx_q->dirty_tx = 0; 7690 tx_q->mss = 0; 7691 7692 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7693 } 7694 7695 /** 7696 * stmmac_reset_queues_param - reset queue parameters 7697 * @priv: device pointer 7698 */ 7699 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7700 { 7701 u32 rx_cnt = priv->plat->rx_queues_to_use; 7702 u32 tx_cnt = priv->plat->tx_queues_to_use; 7703 u32 queue; 7704 7705 for (queue = 0; queue < rx_cnt; queue++) 7706 stmmac_reset_rx_queue(priv, queue); 7707 7708 for (queue = 0; queue < tx_cnt; queue++) 7709 stmmac_reset_tx_queue(priv, queue); 7710 } 7711 7712 /** 7713 * stmmac_resume - resume callback 7714 * @dev: device pointer 7715 * Description: when resume this function is invoked to setup the DMA and CORE 7716 * in a usable state. 7717 */ 7718 int stmmac_resume(struct device *dev) 7719 { 7720 struct net_device *ndev = dev_get_drvdata(dev); 7721 struct stmmac_priv *priv = netdev_priv(ndev); 7722 int ret; 7723 7724 if (!netif_running(ndev)) 7725 return 0; 7726 7727 /* Power Down bit, into the PM register, is cleared 7728 * automatically as soon as a magic packet or a Wake-up frame 7729 * is received. Anyway, it's better to manually clear 7730 * this bit because it can generate problems while resuming 7731 * from another devices (e.g. serial console). 7732 */ 7733 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7734 mutex_lock(&priv->lock); 7735 stmmac_pmt(priv, priv->hw, 0); 7736 mutex_unlock(&priv->lock); 7737 priv->irq_wake = 0; 7738 } else { 7739 pinctrl_pm_select_default_state(priv->device); 7740 /* reset the phy so that it's ready */ 7741 if (priv->mii) 7742 stmmac_mdio_reset(priv->mii); 7743 } 7744 7745 if (!(priv->plat->flags & STMMAC_FLAG_SERDES_UP_AFTER_PHY_LINKUP) && 7746 priv->plat->serdes_powerup) { 7747 ret = priv->plat->serdes_powerup(ndev, 7748 priv->plat->bsp_priv); 7749 7750 if (ret < 0) 7751 return ret; 7752 } 7753 7754 rtnl_lock(); 7755 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7756 phylink_resume(priv->phylink); 7757 } else { 7758 phylink_resume(priv->phylink); 7759 if (device_may_wakeup(priv->device)) 7760 phylink_speed_up(priv->phylink); 7761 } 7762 rtnl_unlock(); 7763 7764 rtnl_lock(); 7765 mutex_lock(&priv->lock); 7766 7767 stmmac_reset_queues_param(priv); 7768 7769 stmmac_free_tx_skbufs(priv); 7770 stmmac_clear_descriptors(priv, &priv->dma_conf); 7771 7772 stmmac_hw_setup(ndev, false); 7773 stmmac_init_coalesce(priv); 7774 stmmac_set_rx_mode(ndev); 7775 7776 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7777 7778 stmmac_enable_all_queues(priv); 7779 stmmac_enable_all_dma_irq(priv); 7780 7781 mutex_unlock(&priv->lock); 7782 rtnl_unlock(); 7783 7784 netif_device_attach(ndev); 7785 7786 return 0; 7787 } 7788 EXPORT_SYMBOL_GPL(stmmac_resume); 7789 7790 #ifndef MODULE 7791 static int __init stmmac_cmdline_opt(char *str) 7792 { 7793 char *opt; 7794 7795 if (!str || !*str) 7796 return 1; 7797 while ((opt = strsep(&str, ",")) != NULL) { 7798 if (!strncmp(opt, "debug:", 6)) { 7799 if (kstrtoint(opt + 6, 0, &debug)) 7800 goto err; 7801 } else if (!strncmp(opt, "phyaddr:", 8)) { 7802 if (kstrtoint(opt + 8, 0, &phyaddr)) 7803 goto err; 7804 } else if (!strncmp(opt, "buf_sz:", 7)) { 7805 if (kstrtoint(opt + 7, 0, &buf_sz)) 7806 goto err; 7807 } else if (!strncmp(opt, "tc:", 3)) { 7808 if (kstrtoint(opt + 3, 0, &tc)) 7809 goto err; 7810 } else if (!strncmp(opt, "watchdog:", 9)) { 7811 if (kstrtoint(opt + 9, 0, &watchdog)) 7812 goto err; 7813 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7814 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7815 goto err; 7816 } else if (!strncmp(opt, "pause:", 6)) { 7817 if (kstrtoint(opt + 6, 0, &pause)) 7818 goto err; 7819 } else if (!strncmp(opt, "eee_timer:", 10)) { 7820 if (kstrtoint(opt + 10, 0, &eee_timer)) 7821 goto err; 7822 } else if (!strncmp(opt, "chain_mode:", 11)) { 7823 if (kstrtoint(opt + 11, 0, &chain_mode)) 7824 goto err; 7825 } 7826 } 7827 return 1; 7828 7829 err: 7830 pr_err("%s: ERROR broken module parameter conversion", __func__); 7831 return 1; 7832 } 7833 7834 __setup("stmmaceth=", stmmac_cmdline_opt); 7835 #endif /* MODULE */ 7836 7837 static int __init stmmac_init(void) 7838 { 7839 #ifdef CONFIG_DEBUG_FS 7840 /* Create debugfs main directory if it doesn't exist yet */ 7841 if (!stmmac_fs_dir) 7842 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7843 register_netdevice_notifier(&stmmac_notifier); 7844 #endif 7845 7846 return 0; 7847 } 7848 7849 static void __exit stmmac_exit(void) 7850 { 7851 #ifdef CONFIG_DEBUG_FS 7852 unregister_netdevice_notifier(&stmmac_notifier); 7853 debugfs_remove_recursive(stmmac_fs_dir); 7854 #endif 7855 } 7856 7857 module_init(stmmac_init) 7858 module_exit(stmmac_exit) 7859 7860 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7861 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7862 MODULE_LICENSE("GPL"); 7863