1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/prefetch.h> 33 #include <linux/pinctrl/consumer.h> 34 #ifdef CONFIG_DEBUG_FS 35 #include <linux/debugfs.h> 36 #include <linux/seq_file.h> 37 #endif /* CONFIG_DEBUG_FS */ 38 #include <linux/net_tstamp.h> 39 #include <linux/phylink.h> 40 #include <linux/udp.h> 41 #include <linux/bpf_trace.h> 42 #include <net/pkt_cls.h> 43 #include <net/xdp_sock_drv.h> 44 #include "stmmac_ptp.h" 45 #include "stmmac.h" 46 #include "stmmac_xdp.h" 47 #include <linux/reset.h> 48 #include <linux/of_mdio.h> 49 #include "dwmac1000.h" 50 #include "dwxgmac2.h" 51 #include "hwif.h" 52 53 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 54 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 55 56 /* Module parameters */ 57 #define TX_TIMEO 5000 58 static int watchdog = TX_TIMEO; 59 module_param(watchdog, int, 0644); 60 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 61 62 static int debug = -1; 63 module_param(debug, int, 0644); 64 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 65 66 static int phyaddr = -1; 67 module_param(phyaddr, int, 0444); 68 MODULE_PARM_DESC(phyaddr, "Physical device address"); 69 70 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 71 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 72 73 /* Limit to make sure XDP TX and slow path can coexist */ 74 #define STMMAC_XSK_TX_BUDGET_MAX 256 75 #define STMMAC_TX_XSK_AVAIL 16 76 #define STMMAC_RX_FILL_BATCH 16 77 78 #define STMMAC_XDP_PASS 0 79 #define STMMAC_XDP_CONSUMED BIT(0) 80 #define STMMAC_XDP_TX BIT(1) 81 #define STMMAC_XDP_REDIRECT BIT(2) 82 83 static int flow_ctrl = FLOW_AUTO; 84 module_param(flow_ctrl, int, 0644); 85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 86 87 static int pause = PAUSE_TIME; 88 module_param(pause, int, 0644); 89 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 90 91 #define TC_DEFAULT 64 92 static int tc = TC_DEFAULT; 93 module_param(tc, int, 0644); 94 MODULE_PARM_DESC(tc, "DMA threshold control value"); 95 96 #define DEFAULT_BUFSIZE 1536 97 static int buf_sz = DEFAULT_BUFSIZE; 98 module_param(buf_sz, int, 0644); 99 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 100 101 #define STMMAC_RX_COPYBREAK 256 102 103 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 104 NETIF_MSG_LINK | NETIF_MSG_IFUP | 105 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 106 107 #define STMMAC_DEFAULT_LPI_TIMER 1000 108 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 109 module_param(eee_timer, int, 0644); 110 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 111 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 112 113 /* By default the driver will use the ring mode to manage tx and rx descriptors, 114 * but allow user to force to use the chain instead of the ring 115 */ 116 static unsigned int chain_mode; 117 module_param(chain_mode, int, 0444); 118 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 119 120 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 121 /* For MSI interrupts handling */ 122 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id); 123 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id); 124 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data); 125 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data); 126 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue); 127 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue); 128 129 #ifdef CONFIG_DEBUG_FS 130 static const struct net_device_ops stmmac_netdev_ops; 131 static void stmmac_init_fs(struct net_device *dev); 132 static void stmmac_exit_fs(struct net_device *dev); 133 #endif 134 135 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 136 137 int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled) 138 { 139 int ret = 0; 140 141 if (enabled) { 142 ret = clk_prepare_enable(priv->plat->stmmac_clk); 143 if (ret) 144 return ret; 145 ret = clk_prepare_enable(priv->plat->pclk); 146 if (ret) { 147 clk_disable_unprepare(priv->plat->stmmac_clk); 148 return ret; 149 } 150 if (priv->plat->clks_config) { 151 ret = priv->plat->clks_config(priv->plat->bsp_priv, enabled); 152 if (ret) { 153 clk_disable_unprepare(priv->plat->stmmac_clk); 154 clk_disable_unprepare(priv->plat->pclk); 155 return ret; 156 } 157 } 158 } else { 159 clk_disable_unprepare(priv->plat->stmmac_clk); 160 clk_disable_unprepare(priv->plat->pclk); 161 if (priv->plat->clks_config) 162 priv->plat->clks_config(priv->plat->bsp_priv, enabled); 163 } 164 165 return ret; 166 } 167 EXPORT_SYMBOL_GPL(stmmac_bus_clks_config); 168 169 /** 170 * stmmac_verify_args - verify the driver parameters. 171 * Description: it checks the driver parameters and set a default in case of 172 * errors. 173 */ 174 static void stmmac_verify_args(void) 175 { 176 if (unlikely(watchdog < 0)) 177 watchdog = TX_TIMEO; 178 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 179 buf_sz = DEFAULT_BUFSIZE; 180 if (unlikely(flow_ctrl > 1)) 181 flow_ctrl = FLOW_AUTO; 182 else if (likely(flow_ctrl < 0)) 183 flow_ctrl = FLOW_OFF; 184 if (unlikely((pause < 0) || (pause > 0xffff))) 185 pause = PAUSE_TIME; 186 if (eee_timer < 0) 187 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 188 } 189 190 static void __stmmac_disable_all_queues(struct stmmac_priv *priv) 191 { 192 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 193 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 194 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 195 u32 queue; 196 197 for (queue = 0; queue < maxq; queue++) { 198 struct stmmac_channel *ch = &priv->channel[queue]; 199 200 if (stmmac_xdp_is_enabled(priv) && 201 test_bit(queue, priv->af_xdp_zc_qps)) { 202 napi_disable(&ch->rxtx_napi); 203 continue; 204 } 205 206 if (queue < rx_queues_cnt) 207 napi_disable(&ch->rx_napi); 208 if (queue < tx_queues_cnt) 209 napi_disable(&ch->tx_napi); 210 } 211 } 212 213 /** 214 * stmmac_disable_all_queues - Disable all queues 215 * @priv: driver private structure 216 */ 217 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 218 { 219 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 220 struct stmmac_rx_queue *rx_q; 221 u32 queue; 222 223 /* synchronize_rcu() needed for pending XDP buffers to drain */ 224 for (queue = 0; queue < rx_queues_cnt; queue++) { 225 rx_q = &priv->rx_queue[queue]; 226 if (rx_q->xsk_pool) { 227 synchronize_rcu(); 228 break; 229 } 230 } 231 232 __stmmac_disable_all_queues(priv); 233 } 234 235 /** 236 * stmmac_enable_all_queues - Enable all queues 237 * @priv: driver private structure 238 */ 239 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 240 { 241 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 242 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 243 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 244 u32 queue; 245 246 for (queue = 0; queue < maxq; queue++) { 247 struct stmmac_channel *ch = &priv->channel[queue]; 248 249 if (stmmac_xdp_is_enabled(priv) && 250 test_bit(queue, priv->af_xdp_zc_qps)) { 251 napi_enable(&ch->rxtx_napi); 252 continue; 253 } 254 255 if (queue < rx_queues_cnt) 256 napi_enable(&ch->rx_napi); 257 if (queue < tx_queues_cnt) 258 napi_enable(&ch->tx_napi); 259 } 260 } 261 262 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 263 { 264 if (!test_bit(STMMAC_DOWN, &priv->state) && 265 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 266 queue_work(priv->wq, &priv->service_task); 267 } 268 269 static void stmmac_global_err(struct stmmac_priv *priv) 270 { 271 netif_carrier_off(priv->dev); 272 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 273 stmmac_service_event_schedule(priv); 274 } 275 276 /** 277 * stmmac_clk_csr_set - dynamically set the MDC clock 278 * @priv: driver private structure 279 * Description: this is to dynamically set the MDC clock according to the csr 280 * clock input. 281 * Note: 282 * If a specific clk_csr value is passed from the platform 283 * this means that the CSR Clock Range selection cannot be 284 * changed at run-time and it is fixed (as reported in the driver 285 * documentation). Viceversa the driver will try to set the MDC 286 * clock dynamically according to the actual clock input. 287 */ 288 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 289 { 290 u32 clk_rate; 291 292 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 293 294 /* Platform provided default clk_csr would be assumed valid 295 * for all other cases except for the below mentioned ones. 296 * For values higher than the IEEE 802.3 specified frequency 297 * we can not estimate the proper divider as it is not known 298 * the frequency of clk_csr_i. So we do not change the default 299 * divider. 300 */ 301 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 302 if (clk_rate < CSR_F_35M) 303 priv->clk_csr = STMMAC_CSR_20_35M; 304 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 305 priv->clk_csr = STMMAC_CSR_35_60M; 306 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 307 priv->clk_csr = STMMAC_CSR_60_100M; 308 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 309 priv->clk_csr = STMMAC_CSR_100_150M; 310 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 311 priv->clk_csr = STMMAC_CSR_150_250M; 312 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 313 priv->clk_csr = STMMAC_CSR_250_300M; 314 } 315 316 if (priv->plat->has_sun8i) { 317 if (clk_rate > 160000000) 318 priv->clk_csr = 0x03; 319 else if (clk_rate > 80000000) 320 priv->clk_csr = 0x02; 321 else if (clk_rate > 40000000) 322 priv->clk_csr = 0x01; 323 else 324 priv->clk_csr = 0; 325 } 326 327 if (priv->plat->has_xgmac) { 328 if (clk_rate > 400000000) 329 priv->clk_csr = 0x5; 330 else if (clk_rate > 350000000) 331 priv->clk_csr = 0x4; 332 else if (clk_rate > 300000000) 333 priv->clk_csr = 0x3; 334 else if (clk_rate > 250000000) 335 priv->clk_csr = 0x2; 336 else if (clk_rate > 150000000) 337 priv->clk_csr = 0x1; 338 else 339 priv->clk_csr = 0x0; 340 } 341 } 342 343 static void print_pkt(unsigned char *buf, int len) 344 { 345 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 346 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 347 } 348 349 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 350 { 351 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 352 u32 avail; 353 354 if (tx_q->dirty_tx > tx_q->cur_tx) 355 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 356 else 357 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 358 359 return avail; 360 } 361 362 /** 363 * stmmac_rx_dirty - Get RX queue dirty 364 * @priv: driver private structure 365 * @queue: RX queue index 366 */ 367 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 368 { 369 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 370 u32 dirty; 371 372 if (rx_q->dirty_rx <= rx_q->cur_rx) 373 dirty = rx_q->cur_rx - rx_q->dirty_rx; 374 else 375 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 376 377 return dirty; 378 } 379 380 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 381 { 382 int tx_lpi_timer; 383 384 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 385 priv->eee_sw_timer_en = en ? 0 : 1; 386 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 387 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 388 } 389 390 /** 391 * stmmac_enable_eee_mode - check and enter in LPI mode 392 * @priv: driver private structure 393 * Description: this function is to verify and enter in LPI mode in case of 394 * EEE. 395 */ 396 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 397 { 398 u32 tx_cnt = priv->plat->tx_queues_to_use; 399 u32 queue; 400 401 /* check if all TX queues have the work finished */ 402 for (queue = 0; queue < tx_cnt; queue++) { 403 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 404 405 if (tx_q->dirty_tx != tx_q->cur_tx) 406 return; /* still unfinished work */ 407 } 408 409 /* Check and enter in LPI mode */ 410 if (!priv->tx_path_in_lpi_mode) 411 stmmac_set_eee_mode(priv, priv->hw, 412 priv->plat->en_tx_lpi_clockgating); 413 } 414 415 /** 416 * stmmac_disable_eee_mode - disable and exit from LPI mode 417 * @priv: driver private structure 418 * Description: this function is to exit and disable EEE in case of 419 * LPI state is true. This is called by the xmit. 420 */ 421 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 422 { 423 if (!priv->eee_sw_timer_en) { 424 stmmac_lpi_entry_timer_config(priv, 0); 425 return; 426 } 427 428 stmmac_reset_eee_mode(priv, priv->hw); 429 del_timer_sync(&priv->eee_ctrl_timer); 430 priv->tx_path_in_lpi_mode = false; 431 } 432 433 /** 434 * stmmac_eee_ctrl_timer - EEE TX SW timer. 435 * @t: timer_list struct containing private info 436 * Description: 437 * if there is no data transfer and if we are not in LPI state, 438 * then MAC Transmitter can be moved to LPI state. 439 */ 440 static void stmmac_eee_ctrl_timer(struct timer_list *t) 441 { 442 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 443 444 stmmac_enable_eee_mode(priv); 445 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 446 } 447 448 /** 449 * stmmac_eee_init - init EEE 450 * @priv: driver private structure 451 * Description: 452 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 453 * can also manage EEE, this function enable the LPI state and start related 454 * timer. 455 */ 456 bool stmmac_eee_init(struct stmmac_priv *priv) 457 { 458 int eee_tw_timer = priv->eee_tw_timer; 459 460 /* Using PCS we cannot dial with the phy registers at this stage 461 * so we do not support extra feature like EEE. 462 */ 463 if (priv->hw->pcs == STMMAC_PCS_TBI || 464 priv->hw->pcs == STMMAC_PCS_RTBI) 465 return false; 466 467 /* Check if MAC core supports the EEE feature. */ 468 if (!priv->dma_cap.eee) 469 return false; 470 471 mutex_lock(&priv->lock); 472 473 /* Check if it needs to be deactivated */ 474 if (!priv->eee_active) { 475 if (priv->eee_enabled) { 476 netdev_dbg(priv->dev, "disable EEE\n"); 477 stmmac_lpi_entry_timer_config(priv, 0); 478 del_timer_sync(&priv->eee_ctrl_timer); 479 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 480 } 481 mutex_unlock(&priv->lock); 482 return false; 483 } 484 485 if (priv->eee_active && !priv->eee_enabled) { 486 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 487 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 488 eee_tw_timer); 489 } 490 491 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 492 del_timer_sync(&priv->eee_ctrl_timer); 493 priv->tx_path_in_lpi_mode = false; 494 stmmac_lpi_entry_timer_config(priv, 1); 495 } else { 496 stmmac_lpi_entry_timer_config(priv, 0); 497 mod_timer(&priv->eee_ctrl_timer, 498 STMMAC_LPI_T(priv->tx_lpi_timer)); 499 } 500 501 mutex_unlock(&priv->lock); 502 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 503 return true; 504 } 505 506 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 507 * @priv: driver private structure 508 * @p : descriptor pointer 509 * @skb : the socket buffer 510 * Description : 511 * This function will read timestamp from the descriptor & pass it to stack. 512 * and also perform some sanity checks. 513 */ 514 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 515 struct dma_desc *p, struct sk_buff *skb) 516 { 517 struct skb_shared_hwtstamps shhwtstamp; 518 bool found = false; 519 s64 adjust = 0; 520 u64 ns = 0; 521 522 if (!priv->hwts_tx_en) 523 return; 524 525 /* exit if skb doesn't support hw tstamp */ 526 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 527 return; 528 529 /* check tx tstamp status */ 530 if (stmmac_get_tx_timestamp_status(priv, p)) { 531 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 532 found = true; 533 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 534 found = true; 535 } 536 537 if (found) { 538 /* Correct the clk domain crossing(CDC) error */ 539 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) { 540 adjust += -(2 * (NSEC_PER_SEC / 541 priv->plat->clk_ptp_rate)); 542 ns += adjust; 543 } 544 545 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 546 shhwtstamp.hwtstamp = ns_to_ktime(ns); 547 548 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 549 /* pass tstamp to stack */ 550 skb_tstamp_tx(skb, &shhwtstamp); 551 } 552 } 553 554 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 555 * @priv: driver private structure 556 * @p : descriptor pointer 557 * @np : next descriptor pointer 558 * @skb : the socket buffer 559 * Description : 560 * This function will read received packet's timestamp from the descriptor 561 * and pass it to stack. It also perform some sanity checks. 562 */ 563 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 564 struct dma_desc *np, struct sk_buff *skb) 565 { 566 struct skb_shared_hwtstamps *shhwtstamp = NULL; 567 struct dma_desc *desc = p; 568 u64 adjust = 0; 569 u64 ns = 0; 570 571 if (!priv->hwts_rx_en) 572 return; 573 /* For GMAC4, the valid timestamp is from CTX next desc. */ 574 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 575 desc = np; 576 577 /* Check if timestamp is available */ 578 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 579 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 580 581 /* Correct the clk domain crossing(CDC) error */ 582 if (priv->plat->has_gmac4 && priv->plat->clk_ptp_rate) { 583 adjust += 2 * (NSEC_PER_SEC / priv->plat->clk_ptp_rate); 584 ns -= adjust; 585 } 586 587 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 588 shhwtstamp = skb_hwtstamps(skb); 589 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 590 shhwtstamp->hwtstamp = ns_to_ktime(ns); 591 } else { 592 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 593 } 594 } 595 596 /** 597 * stmmac_hwtstamp_set - control hardware timestamping. 598 * @dev: device pointer. 599 * @ifr: An IOCTL specific structure, that can contain a pointer to 600 * a proprietary structure used to pass information to the driver. 601 * Description: 602 * This function configures the MAC to enable/disable both outgoing(TX) 603 * and incoming(RX) packets time stamping based on user input. 604 * Return Value: 605 * 0 on success and an appropriate -ve integer on failure. 606 */ 607 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 608 { 609 struct stmmac_priv *priv = netdev_priv(dev); 610 struct hwtstamp_config config; 611 struct timespec64 now; 612 u64 temp = 0; 613 u32 ptp_v2 = 0; 614 u32 tstamp_all = 0; 615 u32 ptp_over_ipv4_udp = 0; 616 u32 ptp_over_ipv6_udp = 0; 617 u32 ptp_over_ethernet = 0; 618 u32 snap_type_sel = 0; 619 u32 ts_master_en = 0; 620 u32 ts_event_en = 0; 621 u32 sec_inc = 0; 622 u32 value = 0; 623 bool xmac; 624 625 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 626 627 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 628 netdev_alert(priv->dev, "No support for HW time stamping\n"); 629 priv->hwts_tx_en = 0; 630 priv->hwts_rx_en = 0; 631 632 return -EOPNOTSUPP; 633 } 634 635 if (copy_from_user(&config, ifr->ifr_data, 636 sizeof(config))) 637 return -EFAULT; 638 639 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 640 __func__, config.flags, config.tx_type, config.rx_filter); 641 642 /* reserved for future extensions */ 643 if (config.flags) 644 return -EINVAL; 645 646 if (config.tx_type != HWTSTAMP_TX_OFF && 647 config.tx_type != HWTSTAMP_TX_ON) 648 return -ERANGE; 649 650 if (priv->adv_ts) { 651 switch (config.rx_filter) { 652 case HWTSTAMP_FILTER_NONE: 653 /* time stamp no incoming packet at all */ 654 config.rx_filter = HWTSTAMP_FILTER_NONE; 655 break; 656 657 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 658 /* PTP v1, UDP, any kind of event packet */ 659 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 660 /* 'xmac' hardware can support Sync, Pdelay_Req and 661 * Pdelay_resp by setting bit14 and bits17/16 to 01 662 * This leaves Delay_Req timestamps out. 663 * Enable all events *and* general purpose message 664 * timestamping 665 */ 666 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 667 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 668 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 669 break; 670 671 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 672 /* PTP v1, UDP, Sync packet */ 673 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 674 /* take time stamp for SYNC messages only */ 675 ts_event_en = PTP_TCR_TSEVNTENA; 676 677 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 678 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 679 break; 680 681 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 682 /* PTP v1, UDP, Delay_req packet */ 683 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 684 /* take time stamp for Delay_Req messages only */ 685 ts_master_en = PTP_TCR_TSMSTRENA; 686 ts_event_en = PTP_TCR_TSEVNTENA; 687 688 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 689 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 690 break; 691 692 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 693 /* PTP v2, UDP, any kind of event packet */ 694 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 695 ptp_v2 = PTP_TCR_TSVER2ENA; 696 /* take time stamp for all event messages */ 697 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 698 699 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 700 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 701 break; 702 703 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 704 /* PTP v2, UDP, Sync packet */ 705 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 706 ptp_v2 = PTP_TCR_TSVER2ENA; 707 /* take time stamp for SYNC messages only */ 708 ts_event_en = PTP_TCR_TSEVNTENA; 709 710 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 711 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 712 break; 713 714 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 715 /* PTP v2, UDP, Delay_req packet */ 716 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 717 ptp_v2 = PTP_TCR_TSVER2ENA; 718 /* take time stamp for Delay_Req messages only */ 719 ts_master_en = PTP_TCR_TSMSTRENA; 720 ts_event_en = PTP_TCR_TSEVNTENA; 721 722 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 723 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 724 break; 725 726 case HWTSTAMP_FILTER_PTP_V2_EVENT: 727 /* PTP v2/802.AS1 any layer, any kind of event packet */ 728 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 729 ptp_v2 = PTP_TCR_TSVER2ENA; 730 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 731 if (priv->synopsys_id != DWMAC_CORE_5_10) 732 ts_event_en = PTP_TCR_TSEVNTENA; 733 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 734 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 735 ptp_over_ethernet = PTP_TCR_TSIPENA; 736 break; 737 738 case HWTSTAMP_FILTER_PTP_V2_SYNC: 739 /* PTP v2/802.AS1, any layer, Sync packet */ 740 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 741 ptp_v2 = PTP_TCR_TSVER2ENA; 742 /* take time stamp for SYNC messages only */ 743 ts_event_en = PTP_TCR_TSEVNTENA; 744 745 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 746 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 747 ptp_over_ethernet = PTP_TCR_TSIPENA; 748 break; 749 750 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 751 /* PTP v2/802.AS1, any layer, Delay_req packet */ 752 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 753 ptp_v2 = PTP_TCR_TSVER2ENA; 754 /* take time stamp for Delay_Req messages only */ 755 ts_master_en = PTP_TCR_TSMSTRENA; 756 ts_event_en = PTP_TCR_TSEVNTENA; 757 758 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 759 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 760 ptp_over_ethernet = PTP_TCR_TSIPENA; 761 break; 762 763 case HWTSTAMP_FILTER_NTP_ALL: 764 case HWTSTAMP_FILTER_ALL: 765 /* time stamp any incoming packet */ 766 config.rx_filter = HWTSTAMP_FILTER_ALL; 767 tstamp_all = PTP_TCR_TSENALL; 768 break; 769 770 default: 771 return -ERANGE; 772 } 773 } else { 774 switch (config.rx_filter) { 775 case HWTSTAMP_FILTER_NONE: 776 config.rx_filter = HWTSTAMP_FILTER_NONE; 777 break; 778 default: 779 /* PTP v1, UDP, any kind of event packet */ 780 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 781 break; 782 } 783 } 784 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 785 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 786 787 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 788 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 789 else { 790 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 791 tstamp_all | ptp_v2 | ptp_over_ethernet | 792 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 793 ts_master_en | snap_type_sel); 794 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 795 796 /* program Sub Second Increment reg */ 797 stmmac_config_sub_second_increment(priv, 798 priv->ptpaddr, priv->plat->clk_ptp_rate, 799 xmac, &sec_inc); 800 temp = div_u64(1000000000ULL, sec_inc); 801 802 /* Store sub second increment and flags for later use */ 803 priv->sub_second_inc = sec_inc; 804 priv->systime_flags = value; 805 806 /* calculate default added value: 807 * formula is : 808 * addend = (2^32)/freq_div_ratio; 809 * where, freq_div_ratio = 1e9ns/sec_inc 810 */ 811 temp = (u64)(temp << 32); 812 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 813 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 814 815 /* initialize system time */ 816 ktime_get_real_ts64(&now); 817 818 /* lower 32 bits of tv_sec are safe until y2106 */ 819 stmmac_init_systime(priv, priv->ptpaddr, 820 (u32)now.tv_sec, now.tv_nsec); 821 } 822 823 memcpy(&priv->tstamp_config, &config, sizeof(config)); 824 825 return copy_to_user(ifr->ifr_data, &config, 826 sizeof(config)) ? -EFAULT : 0; 827 } 828 829 /** 830 * stmmac_hwtstamp_get - read hardware timestamping. 831 * @dev: device pointer. 832 * @ifr: An IOCTL specific structure, that can contain a pointer to 833 * a proprietary structure used to pass information to the driver. 834 * Description: 835 * This function obtain the current hardware timestamping settings 836 * as requested. 837 */ 838 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 839 { 840 struct stmmac_priv *priv = netdev_priv(dev); 841 struct hwtstamp_config *config = &priv->tstamp_config; 842 843 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 844 return -EOPNOTSUPP; 845 846 return copy_to_user(ifr->ifr_data, config, 847 sizeof(*config)) ? -EFAULT : 0; 848 } 849 850 /** 851 * stmmac_init_ptp - init PTP 852 * @priv: driver private structure 853 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 854 * This is done by looking at the HW cap. register. 855 * This function also registers the ptp driver. 856 */ 857 static int stmmac_init_ptp(struct stmmac_priv *priv) 858 { 859 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 860 861 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 862 return -EOPNOTSUPP; 863 864 priv->adv_ts = 0; 865 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 866 if (xmac && priv->dma_cap.atime_stamp) 867 priv->adv_ts = 1; 868 /* Dwmac 3.x core with extend_desc can support adv_ts */ 869 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 870 priv->adv_ts = 1; 871 872 if (priv->dma_cap.time_stamp) 873 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 874 875 if (priv->adv_ts) 876 netdev_info(priv->dev, 877 "IEEE 1588-2008 Advanced Timestamp supported\n"); 878 879 priv->hwts_tx_en = 0; 880 priv->hwts_rx_en = 0; 881 882 stmmac_ptp_register(priv); 883 884 return 0; 885 } 886 887 static void stmmac_release_ptp(struct stmmac_priv *priv) 888 { 889 clk_disable_unprepare(priv->plat->clk_ptp_ref); 890 stmmac_ptp_unregister(priv); 891 } 892 893 /** 894 * stmmac_mac_flow_ctrl - Configure flow control in all queues 895 * @priv: driver private structure 896 * @duplex: duplex passed to the next function 897 * Description: It is used for configuring the flow control in all queues 898 */ 899 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 900 { 901 u32 tx_cnt = priv->plat->tx_queues_to_use; 902 903 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 904 priv->pause, tx_cnt); 905 } 906 907 static void stmmac_validate(struct phylink_config *config, 908 unsigned long *supported, 909 struct phylink_link_state *state) 910 { 911 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 912 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 913 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 914 int tx_cnt = priv->plat->tx_queues_to_use; 915 int max_speed = priv->plat->max_speed; 916 917 phylink_set(mac_supported, 10baseT_Half); 918 phylink_set(mac_supported, 10baseT_Full); 919 phylink_set(mac_supported, 100baseT_Half); 920 phylink_set(mac_supported, 100baseT_Full); 921 phylink_set(mac_supported, 1000baseT_Half); 922 phylink_set(mac_supported, 1000baseT_Full); 923 phylink_set(mac_supported, 1000baseKX_Full); 924 925 phylink_set(mac_supported, Autoneg); 926 phylink_set(mac_supported, Pause); 927 phylink_set(mac_supported, Asym_Pause); 928 phylink_set_port_modes(mac_supported); 929 930 /* Cut down 1G if asked to */ 931 if ((max_speed > 0) && (max_speed < 1000)) { 932 phylink_set(mask, 1000baseT_Full); 933 phylink_set(mask, 1000baseX_Full); 934 } else if (priv->plat->has_gmac4) { 935 if (!max_speed || max_speed >= 2500) 936 phylink_set(mac_supported, 2500baseT_Full); 937 phylink_set(mac_supported, 2500baseX_Full); 938 } else if (priv->plat->has_xgmac) { 939 if (!max_speed || (max_speed >= 2500)) { 940 phylink_set(mac_supported, 2500baseT_Full); 941 phylink_set(mac_supported, 2500baseX_Full); 942 } 943 if (!max_speed || (max_speed >= 5000)) { 944 phylink_set(mac_supported, 5000baseT_Full); 945 } 946 if (!max_speed || (max_speed >= 10000)) { 947 phylink_set(mac_supported, 10000baseSR_Full); 948 phylink_set(mac_supported, 10000baseLR_Full); 949 phylink_set(mac_supported, 10000baseER_Full); 950 phylink_set(mac_supported, 10000baseLRM_Full); 951 phylink_set(mac_supported, 10000baseT_Full); 952 phylink_set(mac_supported, 10000baseKX4_Full); 953 phylink_set(mac_supported, 10000baseKR_Full); 954 } 955 if (!max_speed || (max_speed >= 25000)) { 956 phylink_set(mac_supported, 25000baseCR_Full); 957 phylink_set(mac_supported, 25000baseKR_Full); 958 phylink_set(mac_supported, 25000baseSR_Full); 959 } 960 if (!max_speed || (max_speed >= 40000)) { 961 phylink_set(mac_supported, 40000baseKR4_Full); 962 phylink_set(mac_supported, 40000baseCR4_Full); 963 phylink_set(mac_supported, 40000baseSR4_Full); 964 phylink_set(mac_supported, 40000baseLR4_Full); 965 } 966 if (!max_speed || (max_speed >= 50000)) { 967 phylink_set(mac_supported, 50000baseCR2_Full); 968 phylink_set(mac_supported, 50000baseKR2_Full); 969 phylink_set(mac_supported, 50000baseSR2_Full); 970 phylink_set(mac_supported, 50000baseKR_Full); 971 phylink_set(mac_supported, 50000baseSR_Full); 972 phylink_set(mac_supported, 50000baseCR_Full); 973 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 974 phylink_set(mac_supported, 50000baseDR_Full); 975 } 976 if (!max_speed || (max_speed >= 100000)) { 977 phylink_set(mac_supported, 100000baseKR4_Full); 978 phylink_set(mac_supported, 100000baseSR4_Full); 979 phylink_set(mac_supported, 100000baseCR4_Full); 980 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 981 phylink_set(mac_supported, 100000baseKR2_Full); 982 phylink_set(mac_supported, 100000baseSR2_Full); 983 phylink_set(mac_supported, 100000baseCR2_Full); 984 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 985 phylink_set(mac_supported, 100000baseDR2_Full); 986 } 987 } 988 989 /* Half-Duplex can only work with single queue */ 990 if (tx_cnt > 1) { 991 phylink_set(mask, 10baseT_Half); 992 phylink_set(mask, 100baseT_Half); 993 phylink_set(mask, 1000baseT_Half); 994 } 995 996 linkmode_and(supported, supported, mac_supported); 997 linkmode_andnot(supported, supported, mask); 998 999 linkmode_and(state->advertising, state->advertising, mac_supported); 1000 linkmode_andnot(state->advertising, state->advertising, mask); 1001 1002 /* If PCS is supported, check which modes it supports. */ 1003 if (priv->hw->xpcs) 1004 xpcs_validate(priv->hw->xpcs, supported, state); 1005 } 1006 1007 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 1008 const struct phylink_link_state *state) 1009 { 1010 /* Nothing to do, xpcs_config() handles everything */ 1011 } 1012 1013 static void stmmac_fpe_link_state_handle(struct stmmac_priv *priv, bool is_up) 1014 { 1015 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 1016 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 1017 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 1018 bool *hs_enable = &fpe_cfg->hs_enable; 1019 1020 if (is_up && *hs_enable) { 1021 stmmac_fpe_send_mpacket(priv, priv->ioaddr, MPACKET_VERIFY); 1022 } else { 1023 *lo_state = FPE_EVENT_UNKNOWN; 1024 *lp_state = FPE_EVENT_UNKNOWN; 1025 } 1026 } 1027 1028 static void stmmac_mac_link_down(struct phylink_config *config, 1029 unsigned int mode, phy_interface_t interface) 1030 { 1031 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1032 1033 stmmac_mac_set(priv, priv->ioaddr, false); 1034 priv->eee_active = false; 1035 priv->tx_lpi_enabled = false; 1036 stmmac_eee_init(priv); 1037 stmmac_set_eee_pls(priv, priv->hw, false); 1038 1039 if (priv->dma_cap.fpesel) 1040 stmmac_fpe_link_state_handle(priv, false); 1041 } 1042 1043 static void stmmac_mac_link_up(struct phylink_config *config, 1044 struct phy_device *phy, 1045 unsigned int mode, phy_interface_t interface, 1046 int speed, int duplex, 1047 bool tx_pause, bool rx_pause) 1048 { 1049 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 1050 u32 ctrl; 1051 1052 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 1053 ctrl &= ~priv->hw->link.speed_mask; 1054 1055 if (interface == PHY_INTERFACE_MODE_USXGMII) { 1056 switch (speed) { 1057 case SPEED_10000: 1058 ctrl |= priv->hw->link.xgmii.speed10000; 1059 break; 1060 case SPEED_5000: 1061 ctrl |= priv->hw->link.xgmii.speed5000; 1062 break; 1063 case SPEED_2500: 1064 ctrl |= priv->hw->link.xgmii.speed2500; 1065 break; 1066 default: 1067 return; 1068 } 1069 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 1070 switch (speed) { 1071 case SPEED_100000: 1072 ctrl |= priv->hw->link.xlgmii.speed100000; 1073 break; 1074 case SPEED_50000: 1075 ctrl |= priv->hw->link.xlgmii.speed50000; 1076 break; 1077 case SPEED_40000: 1078 ctrl |= priv->hw->link.xlgmii.speed40000; 1079 break; 1080 case SPEED_25000: 1081 ctrl |= priv->hw->link.xlgmii.speed25000; 1082 break; 1083 case SPEED_10000: 1084 ctrl |= priv->hw->link.xgmii.speed10000; 1085 break; 1086 case SPEED_2500: 1087 ctrl |= priv->hw->link.speed2500; 1088 break; 1089 case SPEED_1000: 1090 ctrl |= priv->hw->link.speed1000; 1091 break; 1092 default: 1093 return; 1094 } 1095 } else { 1096 switch (speed) { 1097 case SPEED_2500: 1098 ctrl |= priv->hw->link.speed2500; 1099 break; 1100 case SPEED_1000: 1101 ctrl |= priv->hw->link.speed1000; 1102 break; 1103 case SPEED_100: 1104 ctrl |= priv->hw->link.speed100; 1105 break; 1106 case SPEED_10: 1107 ctrl |= priv->hw->link.speed10; 1108 break; 1109 default: 1110 return; 1111 } 1112 } 1113 1114 priv->speed = speed; 1115 1116 if (priv->plat->fix_mac_speed) 1117 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1118 1119 if (!duplex) 1120 ctrl &= ~priv->hw->link.duplex; 1121 else 1122 ctrl |= priv->hw->link.duplex; 1123 1124 /* Flow Control operation */ 1125 if (tx_pause && rx_pause) 1126 stmmac_mac_flow_ctrl(priv, duplex); 1127 1128 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1129 1130 stmmac_mac_set(priv, priv->ioaddr, true); 1131 if (phy && priv->dma_cap.eee) { 1132 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1133 priv->eee_enabled = stmmac_eee_init(priv); 1134 priv->tx_lpi_enabled = priv->eee_enabled; 1135 stmmac_set_eee_pls(priv, priv->hw, true); 1136 } 1137 1138 if (priv->dma_cap.fpesel) 1139 stmmac_fpe_link_state_handle(priv, true); 1140 } 1141 1142 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1143 .validate = stmmac_validate, 1144 .mac_config = stmmac_mac_config, 1145 .mac_link_down = stmmac_mac_link_down, 1146 .mac_link_up = stmmac_mac_link_up, 1147 }; 1148 1149 /** 1150 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1151 * @priv: driver private structure 1152 * Description: this is to verify if the HW supports the PCS. 1153 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1154 * configured for the TBI, RTBI, or SGMII PHY interface. 1155 */ 1156 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1157 { 1158 int interface = priv->plat->interface; 1159 1160 if (priv->dma_cap.pcs) { 1161 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1162 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1163 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1164 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1165 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1166 priv->hw->pcs = STMMAC_PCS_RGMII; 1167 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1168 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1169 priv->hw->pcs = STMMAC_PCS_SGMII; 1170 } 1171 } 1172 } 1173 1174 /** 1175 * stmmac_init_phy - PHY initialization 1176 * @dev: net device structure 1177 * Description: it initializes the driver's PHY state, and attaches the PHY 1178 * to the mac driver. 1179 * Return value: 1180 * 0 on success 1181 */ 1182 static int stmmac_init_phy(struct net_device *dev) 1183 { 1184 struct stmmac_priv *priv = netdev_priv(dev); 1185 struct device_node *node; 1186 int ret; 1187 1188 node = priv->plat->phylink_node; 1189 1190 if (node) 1191 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1192 1193 /* Some DT bindings do not set-up the PHY handle. Let's try to 1194 * manually parse it 1195 */ 1196 if (!node || ret) { 1197 int addr = priv->plat->phy_addr; 1198 struct phy_device *phydev; 1199 1200 phydev = mdiobus_get_phy(priv->mii, addr); 1201 if (!phydev) { 1202 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1203 return -ENODEV; 1204 } 1205 1206 ret = phylink_connect_phy(priv->phylink, phydev); 1207 } 1208 1209 if (!priv->plat->pmt) { 1210 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1211 1212 phylink_ethtool_get_wol(priv->phylink, &wol); 1213 device_set_wakeup_capable(priv->device, !!wol.supported); 1214 } 1215 1216 return ret; 1217 } 1218 1219 static int stmmac_phy_setup(struct stmmac_priv *priv) 1220 { 1221 struct stmmac_mdio_bus_data *mdio_bus_data = priv->plat->mdio_bus_data; 1222 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1223 int mode = priv->plat->phy_interface; 1224 struct phylink *phylink; 1225 1226 priv->phylink_config.dev = &priv->dev->dev; 1227 priv->phylink_config.type = PHYLINK_NETDEV; 1228 priv->phylink_config.pcs_poll = true; 1229 if (priv->plat->mdio_bus_data) 1230 priv->phylink_config.ovr_an_inband = 1231 mdio_bus_data->xpcs_an_inband; 1232 1233 if (!fwnode) 1234 fwnode = dev_fwnode(priv->device); 1235 1236 phylink = phylink_create(&priv->phylink_config, fwnode, 1237 mode, &stmmac_phylink_mac_ops); 1238 if (IS_ERR(phylink)) 1239 return PTR_ERR(phylink); 1240 1241 if (mdio_bus_data->has_xpcs) { 1242 struct mdio_xpcs_args *xpcs = priv->hw->xpcs; 1243 1244 phylink_set_pcs(phylink, &xpcs->pcs); 1245 } 1246 1247 priv->phylink = phylink; 1248 return 0; 1249 } 1250 1251 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1252 { 1253 u32 rx_cnt = priv->plat->rx_queues_to_use; 1254 unsigned int desc_size; 1255 void *head_rx; 1256 u32 queue; 1257 1258 /* Display RX rings */ 1259 for (queue = 0; queue < rx_cnt; queue++) { 1260 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1261 1262 pr_info("\tRX Queue %u rings\n", queue); 1263 1264 if (priv->extend_desc) { 1265 head_rx = (void *)rx_q->dma_erx; 1266 desc_size = sizeof(struct dma_extended_desc); 1267 } else { 1268 head_rx = (void *)rx_q->dma_rx; 1269 desc_size = sizeof(struct dma_desc); 1270 } 1271 1272 /* Display RX ring */ 1273 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true, 1274 rx_q->dma_rx_phy, desc_size); 1275 } 1276 } 1277 1278 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1279 { 1280 u32 tx_cnt = priv->plat->tx_queues_to_use; 1281 unsigned int desc_size; 1282 void *head_tx; 1283 u32 queue; 1284 1285 /* Display TX rings */ 1286 for (queue = 0; queue < tx_cnt; queue++) { 1287 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1288 1289 pr_info("\tTX Queue %d rings\n", queue); 1290 1291 if (priv->extend_desc) { 1292 head_tx = (void *)tx_q->dma_etx; 1293 desc_size = sizeof(struct dma_extended_desc); 1294 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1295 head_tx = (void *)tx_q->dma_entx; 1296 desc_size = sizeof(struct dma_edesc); 1297 } else { 1298 head_tx = (void *)tx_q->dma_tx; 1299 desc_size = sizeof(struct dma_desc); 1300 } 1301 1302 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false, 1303 tx_q->dma_tx_phy, desc_size); 1304 } 1305 } 1306 1307 static void stmmac_display_rings(struct stmmac_priv *priv) 1308 { 1309 /* Display RX ring */ 1310 stmmac_display_rx_rings(priv); 1311 1312 /* Display TX ring */ 1313 stmmac_display_tx_rings(priv); 1314 } 1315 1316 static int stmmac_set_bfsize(int mtu, int bufsize) 1317 { 1318 int ret = bufsize; 1319 1320 if (mtu >= BUF_SIZE_8KiB) 1321 ret = BUF_SIZE_16KiB; 1322 else if (mtu >= BUF_SIZE_4KiB) 1323 ret = BUF_SIZE_8KiB; 1324 else if (mtu >= BUF_SIZE_2KiB) 1325 ret = BUF_SIZE_4KiB; 1326 else if (mtu > DEFAULT_BUFSIZE) 1327 ret = BUF_SIZE_2KiB; 1328 else 1329 ret = DEFAULT_BUFSIZE; 1330 1331 return ret; 1332 } 1333 1334 /** 1335 * stmmac_clear_rx_descriptors - clear RX descriptors 1336 * @priv: driver private structure 1337 * @queue: RX queue index 1338 * Description: this function is called to clear the RX descriptors 1339 * in case of both basic and extended descriptors are used. 1340 */ 1341 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1342 { 1343 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1344 int i; 1345 1346 /* Clear the RX descriptors */ 1347 for (i = 0; i < priv->dma_rx_size; i++) 1348 if (priv->extend_desc) 1349 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1350 priv->use_riwt, priv->mode, 1351 (i == priv->dma_rx_size - 1), 1352 priv->dma_buf_sz); 1353 else 1354 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1355 priv->use_riwt, priv->mode, 1356 (i == priv->dma_rx_size - 1), 1357 priv->dma_buf_sz); 1358 } 1359 1360 /** 1361 * stmmac_clear_tx_descriptors - clear tx descriptors 1362 * @priv: driver private structure 1363 * @queue: TX queue index. 1364 * Description: this function is called to clear the TX descriptors 1365 * in case of both basic and extended descriptors are used. 1366 */ 1367 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1368 { 1369 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1370 int i; 1371 1372 /* Clear the TX descriptors */ 1373 for (i = 0; i < priv->dma_tx_size; i++) { 1374 int last = (i == (priv->dma_tx_size - 1)); 1375 struct dma_desc *p; 1376 1377 if (priv->extend_desc) 1378 p = &tx_q->dma_etx[i].basic; 1379 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1380 p = &tx_q->dma_entx[i].basic; 1381 else 1382 p = &tx_q->dma_tx[i]; 1383 1384 stmmac_init_tx_desc(priv, p, priv->mode, last); 1385 } 1386 } 1387 1388 /** 1389 * stmmac_clear_descriptors - clear descriptors 1390 * @priv: driver private structure 1391 * Description: this function is called to clear the TX and RX descriptors 1392 * in case of both basic and extended descriptors are used. 1393 */ 1394 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1395 { 1396 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1397 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1398 u32 queue; 1399 1400 /* Clear the RX descriptors */ 1401 for (queue = 0; queue < rx_queue_cnt; queue++) 1402 stmmac_clear_rx_descriptors(priv, queue); 1403 1404 /* Clear the TX descriptors */ 1405 for (queue = 0; queue < tx_queue_cnt; queue++) 1406 stmmac_clear_tx_descriptors(priv, queue); 1407 } 1408 1409 /** 1410 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1411 * @priv: driver private structure 1412 * @p: descriptor pointer 1413 * @i: descriptor index 1414 * @flags: gfp flag 1415 * @queue: RX queue index 1416 * Description: this function is called to allocate a receive buffer, perform 1417 * the DMA mapping and init the descriptor. 1418 */ 1419 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1420 int i, gfp_t flags, u32 queue) 1421 { 1422 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1423 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1424 1425 if (!buf->page) { 1426 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1427 if (!buf->page) 1428 return -ENOMEM; 1429 buf->page_offset = stmmac_rx_offset(priv); 1430 } 1431 1432 if (priv->sph && !buf->sec_page) { 1433 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1434 if (!buf->sec_page) 1435 return -ENOMEM; 1436 1437 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1438 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 1439 } else { 1440 buf->sec_page = NULL; 1441 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 1442 } 1443 1444 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 1445 1446 stmmac_set_desc_addr(priv, p, buf->addr); 1447 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1448 stmmac_init_desc3(priv, p); 1449 1450 return 0; 1451 } 1452 1453 /** 1454 * stmmac_free_rx_buffer - free RX dma buffers 1455 * @priv: private structure 1456 * @queue: RX queue index 1457 * @i: buffer index. 1458 */ 1459 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1460 { 1461 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1462 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1463 1464 if (buf->page) 1465 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1466 buf->page = NULL; 1467 1468 if (buf->sec_page) 1469 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1470 buf->sec_page = NULL; 1471 } 1472 1473 /** 1474 * stmmac_free_tx_buffer - free RX dma buffers 1475 * @priv: private structure 1476 * @queue: RX queue index 1477 * @i: buffer index. 1478 */ 1479 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1480 { 1481 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1482 1483 if (tx_q->tx_skbuff_dma[i].buf && 1484 tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) { 1485 if (tx_q->tx_skbuff_dma[i].map_as_page) 1486 dma_unmap_page(priv->device, 1487 tx_q->tx_skbuff_dma[i].buf, 1488 tx_q->tx_skbuff_dma[i].len, 1489 DMA_TO_DEVICE); 1490 else 1491 dma_unmap_single(priv->device, 1492 tx_q->tx_skbuff_dma[i].buf, 1493 tx_q->tx_skbuff_dma[i].len, 1494 DMA_TO_DEVICE); 1495 } 1496 1497 if (tx_q->xdpf[i] && 1498 (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_TX || 1499 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XDP_NDO)) { 1500 xdp_return_frame(tx_q->xdpf[i]); 1501 tx_q->xdpf[i] = NULL; 1502 } 1503 1504 if (tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_XSK_TX) 1505 tx_q->xsk_frames_done++; 1506 1507 if (tx_q->tx_skbuff[i] && 1508 tx_q->tx_skbuff_dma[i].buf_type == STMMAC_TXBUF_T_SKB) { 1509 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1510 tx_q->tx_skbuff[i] = NULL; 1511 } 1512 1513 tx_q->tx_skbuff_dma[i].buf = 0; 1514 tx_q->tx_skbuff_dma[i].map_as_page = false; 1515 } 1516 1517 /** 1518 * dma_free_rx_skbufs - free RX dma buffers 1519 * @priv: private structure 1520 * @queue: RX queue index 1521 */ 1522 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1523 { 1524 int i; 1525 1526 for (i = 0; i < priv->dma_rx_size; i++) 1527 stmmac_free_rx_buffer(priv, queue, i); 1528 } 1529 1530 static int stmmac_alloc_rx_buffers(struct stmmac_priv *priv, u32 queue, 1531 gfp_t flags) 1532 { 1533 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1534 int i; 1535 1536 for (i = 0; i < priv->dma_rx_size; i++) { 1537 struct dma_desc *p; 1538 int ret; 1539 1540 if (priv->extend_desc) 1541 p = &((rx_q->dma_erx + i)->basic); 1542 else 1543 p = rx_q->dma_rx + i; 1544 1545 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1546 queue); 1547 if (ret) 1548 return ret; 1549 1550 rx_q->buf_alloc_num++; 1551 } 1552 1553 return 0; 1554 } 1555 1556 /** 1557 * dma_free_rx_xskbufs - free RX dma buffers from XSK pool 1558 * @priv: private structure 1559 * @queue: RX queue index 1560 */ 1561 static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue) 1562 { 1563 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1564 int i; 1565 1566 for (i = 0; i < priv->dma_rx_size; i++) { 1567 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1568 1569 if (!buf->xdp) 1570 continue; 1571 1572 xsk_buff_free(buf->xdp); 1573 buf->xdp = NULL; 1574 } 1575 } 1576 1577 static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue) 1578 { 1579 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1580 int i; 1581 1582 for (i = 0; i < priv->dma_rx_size; i++) { 1583 struct stmmac_rx_buffer *buf; 1584 dma_addr_t dma_addr; 1585 struct dma_desc *p; 1586 1587 if (priv->extend_desc) 1588 p = (struct dma_desc *)(rx_q->dma_erx + i); 1589 else 1590 p = rx_q->dma_rx + i; 1591 1592 buf = &rx_q->buf_pool[i]; 1593 1594 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 1595 if (!buf->xdp) 1596 return -ENOMEM; 1597 1598 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 1599 stmmac_set_desc_addr(priv, p, dma_addr); 1600 rx_q->buf_alloc_num++; 1601 } 1602 1603 return 0; 1604 } 1605 1606 static struct xsk_buff_pool *stmmac_get_xsk_pool(struct stmmac_priv *priv, u32 queue) 1607 { 1608 if (!stmmac_xdp_is_enabled(priv) || !test_bit(queue, priv->af_xdp_zc_qps)) 1609 return NULL; 1610 1611 return xsk_get_pool_from_qid(priv->dev, queue); 1612 } 1613 1614 /** 1615 * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue) 1616 * @priv: driver private structure 1617 * @queue: RX queue index 1618 * @flags: gfp flag. 1619 * Description: this function initializes the DMA RX descriptors 1620 * and allocates the socket buffers. It supports the chained and ring 1621 * modes. 1622 */ 1623 static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags) 1624 { 1625 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1626 int ret; 1627 1628 netif_dbg(priv, probe, priv->dev, 1629 "(%s) dma_rx_phy=0x%08x\n", __func__, 1630 (u32)rx_q->dma_rx_phy); 1631 1632 stmmac_clear_rx_descriptors(priv, queue); 1633 1634 xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq); 1635 1636 rx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1637 1638 if (rx_q->xsk_pool) { 1639 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1640 MEM_TYPE_XSK_BUFF_POOL, 1641 NULL)); 1642 netdev_info(priv->dev, 1643 "Register MEM_TYPE_XSK_BUFF_POOL RxQ-%d\n", 1644 rx_q->queue_index); 1645 xsk_pool_set_rxq_info(rx_q->xsk_pool, &rx_q->xdp_rxq); 1646 } else { 1647 WARN_ON(xdp_rxq_info_reg_mem_model(&rx_q->xdp_rxq, 1648 MEM_TYPE_PAGE_POOL, 1649 rx_q->page_pool)); 1650 netdev_info(priv->dev, 1651 "Register MEM_TYPE_PAGE_POOL RxQ-%d\n", 1652 rx_q->queue_index); 1653 } 1654 1655 if (rx_q->xsk_pool) { 1656 /* RX XDP ZC buffer pool may not be populated, e.g. 1657 * xdpsock TX-only. 1658 */ 1659 stmmac_alloc_rx_buffers_zc(priv, queue); 1660 } else { 1661 ret = stmmac_alloc_rx_buffers(priv, queue, flags); 1662 if (ret < 0) 1663 return -ENOMEM; 1664 } 1665 1666 rx_q->cur_rx = 0; 1667 rx_q->dirty_rx = 0; 1668 1669 /* Setup the chained descriptor addresses */ 1670 if (priv->mode == STMMAC_CHAIN_MODE) { 1671 if (priv->extend_desc) 1672 stmmac_mode_init(priv, rx_q->dma_erx, 1673 rx_q->dma_rx_phy, 1674 priv->dma_rx_size, 1); 1675 else 1676 stmmac_mode_init(priv, rx_q->dma_rx, 1677 rx_q->dma_rx_phy, 1678 priv->dma_rx_size, 0); 1679 } 1680 1681 return 0; 1682 } 1683 1684 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1685 { 1686 struct stmmac_priv *priv = netdev_priv(dev); 1687 u32 rx_count = priv->plat->rx_queues_to_use; 1688 u32 queue; 1689 int ret; 1690 1691 /* RX INITIALIZATION */ 1692 netif_dbg(priv, probe, priv->dev, 1693 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1694 1695 for (queue = 0; queue < rx_count; queue++) { 1696 ret = __init_dma_rx_desc_rings(priv, queue, flags); 1697 if (ret) 1698 goto err_init_rx_buffers; 1699 } 1700 1701 return 0; 1702 1703 err_init_rx_buffers: 1704 while (queue >= 0) { 1705 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1706 1707 if (rx_q->xsk_pool) 1708 dma_free_rx_xskbufs(priv, queue); 1709 else 1710 dma_free_rx_skbufs(priv, queue); 1711 1712 rx_q->buf_alloc_num = 0; 1713 rx_q->xsk_pool = NULL; 1714 1715 if (queue == 0) 1716 break; 1717 1718 queue--; 1719 } 1720 1721 return ret; 1722 } 1723 1724 /** 1725 * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue) 1726 * @priv: driver private structure 1727 * @queue : TX queue index 1728 * Description: this function initializes the DMA TX descriptors 1729 * and allocates the socket buffers. It supports the chained and ring 1730 * modes. 1731 */ 1732 static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue) 1733 { 1734 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1735 int i; 1736 1737 netif_dbg(priv, probe, priv->dev, 1738 "(%s) dma_tx_phy=0x%08x\n", __func__, 1739 (u32)tx_q->dma_tx_phy); 1740 1741 /* Setup the chained descriptor addresses */ 1742 if (priv->mode == STMMAC_CHAIN_MODE) { 1743 if (priv->extend_desc) 1744 stmmac_mode_init(priv, tx_q->dma_etx, 1745 tx_q->dma_tx_phy, 1746 priv->dma_tx_size, 1); 1747 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1748 stmmac_mode_init(priv, tx_q->dma_tx, 1749 tx_q->dma_tx_phy, 1750 priv->dma_tx_size, 0); 1751 } 1752 1753 tx_q->xsk_pool = stmmac_get_xsk_pool(priv, queue); 1754 1755 for (i = 0; i < priv->dma_tx_size; i++) { 1756 struct dma_desc *p; 1757 1758 if (priv->extend_desc) 1759 p = &((tx_q->dma_etx + i)->basic); 1760 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1761 p = &((tx_q->dma_entx + i)->basic); 1762 else 1763 p = tx_q->dma_tx + i; 1764 1765 stmmac_clear_desc(priv, p); 1766 1767 tx_q->tx_skbuff_dma[i].buf = 0; 1768 tx_q->tx_skbuff_dma[i].map_as_page = false; 1769 tx_q->tx_skbuff_dma[i].len = 0; 1770 tx_q->tx_skbuff_dma[i].last_segment = false; 1771 tx_q->tx_skbuff[i] = NULL; 1772 } 1773 1774 tx_q->dirty_tx = 0; 1775 tx_q->cur_tx = 0; 1776 tx_q->mss = 0; 1777 1778 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1779 1780 return 0; 1781 } 1782 1783 static int init_dma_tx_desc_rings(struct net_device *dev) 1784 { 1785 struct stmmac_priv *priv = netdev_priv(dev); 1786 u32 tx_queue_cnt; 1787 u32 queue; 1788 1789 tx_queue_cnt = priv->plat->tx_queues_to_use; 1790 1791 for (queue = 0; queue < tx_queue_cnt; queue++) 1792 __init_dma_tx_desc_rings(priv, queue); 1793 1794 return 0; 1795 } 1796 1797 /** 1798 * init_dma_desc_rings - init the RX/TX descriptor rings 1799 * @dev: net device structure 1800 * @flags: gfp flag. 1801 * Description: this function initializes the DMA RX/TX descriptors 1802 * and allocates the socket buffers. It supports the chained and ring 1803 * modes. 1804 */ 1805 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1806 { 1807 struct stmmac_priv *priv = netdev_priv(dev); 1808 int ret; 1809 1810 ret = init_dma_rx_desc_rings(dev, flags); 1811 if (ret) 1812 return ret; 1813 1814 ret = init_dma_tx_desc_rings(dev); 1815 1816 stmmac_clear_descriptors(priv); 1817 1818 if (netif_msg_hw(priv)) 1819 stmmac_display_rings(priv); 1820 1821 return ret; 1822 } 1823 1824 /** 1825 * dma_free_tx_skbufs - free TX dma buffers 1826 * @priv: private structure 1827 * @queue: TX queue index 1828 */ 1829 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1830 { 1831 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1832 int i; 1833 1834 tx_q->xsk_frames_done = 0; 1835 1836 for (i = 0; i < priv->dma_tx_size; i++) 1837 stmmac_free_tx_buffer(priv, queue, i); 1838 1839 if (tx_q->xsk_pool && tx_q->xsk_frames_done) { 1840 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 1841 tx_q->xsk_frames_done = 0; 1842 tx_q->xsk_pool = NULL; 1843 } 1844 } 1845 1846 /** 1847 * stmmac_free_tx_skbufs - free TX skb buffers 1848 * @priv: private structure 1849 */ 1850 static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) 1851 { 1852 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1853 u32 queue; 1854 1855 for (queue = 0; queue < tx_queue_cnt; queue++) 1856 dma_free_tx_skbufs(priv, queue); 1857 } 1858 1859 /** 1860 * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) 1861 * @priv: private structure 1862 * @queue: RX queue index 1863 */ 1864 static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1865 { 1866 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1867 1868 /* Release the DMA RX socket buffers */ 1869 if (rx_q->xsk_pool) 1870 dma_free_rx_xskbufs(priv, queue); 1871 else 1872 dma_free_rx_skbufs(priv, queue); 1873 1874 rx_q->buf_alloc_num = 0; 1875 rx_q->xsk_pool = NULL; 1876 1877 /* Free DMA regions of consistent memory previously allocated */ 1878 if (!priv->extend_desc) 1879 dma_free_coherent(priv->device, priv->dma_rx_size * 1880 sizeof(struct dma_desc), 1881 rx_q->dma_rx, rx_q->dma_rx_phy); 1882 else 1883 dma_free_coherent(priv->device, priv->dma_rx_size * 1884 sizeof(struct dma_extended_desc), 1885 rx_q->dma_erx, rx_q->dma_rx_phy); 1886 1887 if (xdp_rxq_info_is_reg(&rx_q->xdp_rxq)) 1888 xdp_rxq_info_unreg(&rx_q->xdp_rxq); 1889 1890 kfree(rx_q->buf_pool); 1891 if (rx_q->page_pool) 1892 page_pool_destroy(rx_q->page_pool); 1893 } 1894 1895 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1896 { 1897 u32 rx_count = priv->plat->rx_queues_to_use; 1898 u32 queue; 1899 1900 /* Free RX queue resources */ 1901 for (queue = 0; queue < rx_count; queue++) 1902 __free_dma_rx_desc_resources(priv, queue); 1903 } 1904 1905 /** 1906 * __free_dma_tx_desc_resources - free TX dma desc resources (per queue) 1907 * @priv: private structure 1908 * @queue: TX queue index 1909 */ 1910 static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 1911 { 1912 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1913 size_t size; 1914 void *addr; 1915 1916 /* Release the DMA TX socket buffers */ 1917 dma_free_tx_skbufs(priv, queue); 1918 1919 if (priv->extend_desc) { 1920 size = sizeof(struct dma_extended_desc); 1921 addr = tx_q->dma_etx; 1922 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1923 size = sizeof(struct dma_edesc); 1924 addr = tx_q->dma_entx; 1925 } else { 1926 size = sizeof(struct dma_desc); 1927 addr = tx_q->dma_tx; 1928 } 1929 1930 size *= priv->dma_tx_size; 1931 1932 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1933 1934 kfree(tx_q->tx_skbuff_dma); 1935 kfree(tx_q->tx_skbuff); 1936 } 1937 1938 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1939 { 1940 u32 tx_count = priv->plat->tx_queues_to_use; 1941 u32 queue; 1942 1943 /* Free TX queue resources */ 1944 for (queue = 0; queue < tx_count; queue++) 1945 __free_dma_tx_desc_resources(priv, queue); 1946 } 1947 1948 /** 1949 * __alloc_dma_rx_desc_resources - alloc RX resources (per queue). 1950 * @priv: private structure 1951 * @queue: RX queue index 1952 * Description: according to which descriptor can be used (extend or basic) 1953 * this function allocates the resources for TX and RX paths. In case of 1954 * reception, for example, it pre-allocated the RX socket buffer in order to 1955 * allow zero-copy mechanism. 1956 */ 1957 static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue) 1958 { 1959 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1960 struct stmmac_channel *ch = &priv->channel[queue]; 1961 bool xdp_prog = stmmac_xdp_is_enabled(priv); 1962 struct page_pool_params pp_params = { 0 }; 1963 unsigned int num_pages; 1964 unsigned int napi_id; 1965 int ret; 1966 1967 rx_q->queue_index = queue; 1968 rx_q->priv_data = priv; 1969 1970 pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV; 1971 pp_params.pool_size = priv->dma_rx_size; 1972 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1973 pp_params.order = ilog2(num_pages); 1974 pp_params.nid = dev_to_node(priv->device); 1975 pp_params.dev = priv->device; 1976 pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; 1977 pp_params.offset = stmmac_rx_offset(priv); 1978 pp_params.max_len = STMMAC_MAX_RX_BUF_SIZE(num_pages); 1979 1980 rx_q->page_pool = page_pool_create(&pp_params); 1981 if (IS_ERR(rx_q->page_pool)) { 1982 ret = PTR_ERR(rx_q->page_pool); 1983 rx_q->page_pool = NULL; 1984 return ret; 1985 } 1986 1987 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1988 sizeof(*rx_q->buf_pool), 1989 GFP_KERNEL); 1990 if (!rx_q->buf_pool) 1991 return -ENOMEM; 1992 1993 if (priv->extend_desc) { 1994 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1995 priv->dma_rx_size * 1996 sizeof(struct dma_extended_desc), 1997 &rx_q->dma_rx_phy, 1998 GFP_KERNEL); 1999 if (!rx_q->dma_erx) 2000 return -ENOMEM; 2001 2002 } else { 2003 rx_q->dma_rx = dma_alloc_coherent(priv->device, 2004 priv->dma_rx_size * 2005 sizeof(struct dma_desc), 2006 &rx_q->dma_rx_phy, 2007 GFP_KERNEL); 2008 if (!rx_q->dma_rx) 2009 return -ENOMEM; 2010 } 2011 2012 if (stmmac_xdp_is_enabled(priv) && 2013 test_bit(queue, priv->af_xdp_zc_qps)) 2014 napi_id = ch->rxtx_napi.napi_id; 2015 else 2016 napi_id = ch->rx_napi.napi_id; 2017 2018 ret = xdp_rxq_info_reg(&rx_q->xdp_rxq, priv->dev, 2019 rx_q->queue_index, 2020 napi_id); 2021 if (ret) { 2022 netdev_err(priv->dev, "Failed to register xdp rxq info\n"); 2023 return -EINVAL; 2024 } 2025 2026 return 0; 2027 } 2028 2029 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 2030 { 2031 u32 rx_count = priv->plat->rx_queues_to_use; 2032 u32 queue; 2033 int ret; 2034 2035 /* RX queues buffers and DMA */ 2036 for (queue = 0; queue < rx_count; queue++) { 2037 ret = __alloc_dma_rx_desc_resources(priv, queue); 2038 if (ret) 2039 goto err_dma; 2040 } 2041 2042 return 0; 2043 2044 err_dma: 2045 free_dma_rx_desc_resources(priv); 2046 2047 return ret; 2048 } 2049 2050 /** 2051 * __alloc_dma_tx_desc_resources - alloc TX resources (per queue). 2052 * @priv: private structure 2053 * @queue: TX queue index 2054 * Description: according to which descriptor can be used (extend or basic) 2055 * this function allocates the resources for TX and RX paths. In case of 2056 * reception, for example, it pre-allocated the RX socket buffer in order to 2057 * allow zero-copy mechanism. 2058 */ 2059 static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue) 2060 { 2061 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2062 size_t size; 2063 void *addr; 2064 2065 tx_q->queue_index = queue; 2066 tx_q->priv_data = priv; 2067 2068 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 2069 sizeof(*tx_q->tx_skbuff_dma), 2070 GFP_KERNEL); 2071 if (!tx_q->tx_skbuff_dma) 2072 return -ENOMEM; 2073 2074 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 2075 sizeof(struct sk_buff *), 2076 GFP_KERNEL); 2077 if (!tx_q->tx_skbuff) 2078 return -ENOMEM; 2079 2080 if (priv->extend_desc) 2081 size = sizeof(struct dma_extended_desc); 2082 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2083 size = sizeof(struct dma_edesc); 2084 else 2085 size = sizeof(struct dma_desc); 2086 2087 size *= priv->dma_tx_size; 2088 2089 addr = dma_alloc_coherent(priv->device, size, 2090 &tx_q->dma_tx_phy, GFP_KERNEL); 2091 if (!addr) 2092 return -ENOMEM; 2093 2094 if (priv->extend_desc) 2095 tx_q->dma_etx = addr; 2096 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2097 tx_q->dma_entx = addr; 2098 else 2099 tx_q->dma_tx = addr; 2100 2101 return 0; 2102 } 2103 2104 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 2105 { 2106 u32 tx_count = priv->plat->tx_queues_to_use; 2107 u32 queue; 2108 int ret; 2109 2110 /* TX queues buffers and DMA */ 2111 for (queue = 0; queue < tx_count; queue++) { 2112 ret = __alloc_dma_tx_desc_resources(priv, queue); 2113 if (ret) 2114 goto err_dma; 2115 } 2116 2117 return 0; 2118 2119 err_dma: 2120 free_dma_tx_desc_resources(priv); 2121 return ret; 2122 } 2123 2124 /** 2125 * alloc_dma_desc_resources - alloc TX/RX resources. 2126 * @priv: private structure 2127 * Description: according to which descriptor can be used (extend or basic) 2128 * this function allocates the resources for TX and RX paths. In case of 2129 * reception, for example, it pre-allocated the RX socket buffer in order to 2130 * allow zero-copy mechanism. 2131 */ 2132 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 2133 { 2134 /* RX Allocation */ 2135 int ret = alloc_dma_rx_desc_resources(priv); 2136 2137 if (ret) 2138 return ret; 2139 2140 ret = alloc_dma_tx_desc_resources(priv); 2141 2142 return ret; 2143 } 2144 2145 /** 2146 * free_dma_desc_resources - free dma desc resources 2147 * @priv: private structure 2148 */ 2149 static void free_dma_desc_resources(struct stmmac_priv *priv) 2150 { 2151 /* Release the DMA TX socket buffers */ 2152 free_dma_tx_desc_resources(priv); 2153 2154 /* Release the DMA RX socket buffers later 2155 * to ensure all pending XDP_TX buffers are returned. 2156 */ 2157 free_dma_rx_desc_resources(priv); 2158 } 2159 2160 /** 2161 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 2162 * @priv: driver private structure 2163 * Description: It is used for enabling the rx queues in the MAC 2164 */ 2165 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 2166 { 2167 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2168 int queue; 2169 u8 mode; 2170 2171 for (queue = 0; queue < rx_queues_count; queue++) { 2172 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 2173 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 2174 } 2175 } 2176 2177 /** 2178 * stmmac_start_rx_dma - start RX DMA channel 2179 * @priv: driver private structure 2180 * @chan: RX channel index 2181 * Description: 2182 * This starts a RX DMA channel 2183 */ 2184 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 2185 { 2186 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 2187 stmmac_start_rx(priv, priv->ioaddr, chan); 2188 } 2189 2190 /** 2191 * stmmac_start_tx_dma - start TX DMA channel 2192 * @priv: driver private structure 2193 * @chan: TX channel index 2194 * Description: 2195 * This starts a TX DMA channel 2196 */ 2197 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 2198 { 2199 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 2200 stmmac_start_tx(priv, priv->ioaddr, chan); 2201 } 2202 2203 /** 2204 * stmmac_stop_rx_dma - stop RX DMA channel 2205 * @priv: driver private structure 2206 * @chan: RX channel index 2207 * Description: 2208 * This stops a RX DMA channel 2209 */ 2210 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 2211 { 2212 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 2213 stmmac_stop_rx(priv, priv->ioaddr, chan); 2214 } 2215 2216 /** 2217 * stmmac_stop_tx_dma - stop TX DMA channel 2218 * @priv: driver private structure 2219 * @chan: TX channel index 2220 * Description: 2221 * This stops a TX DMA channel 2222 */ 2223 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 2224 { 2225 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 2226 stmmac_stop_tx(priv, priv->ioaddr, chan); 2227 } 2228 2229 /** 2230 * stmmac_start_all_dma - start all RX and TX DMA channels 2231 * @priv: driver private structure 2232 * Description: 2233 * This starts all the RX and TX DMA channels 2234 */ 2235 static void stmmac_start_all_dma(struct stmmac_priv *priv) 2236 { 2237 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2238 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2239 u32 chan = 0; 2240 2241 for (chan = 0; chan < rx_channels_count; chan++) 2242 stmmac_start_rx_dma(priv, chan); 2243 2244 for (chan = 0; chan < tx_channels_count; chan++) 2245 stmmac_start_tx_dma(priv, chan); 2246 } 2247 2248 /** 2249 * stmmac_stop_all_dma - stop all RX and TX DMA channels 2250 * @priv: driver private structure 2251 * Description: 2252 * This stops the RX and TX DMA channels 2253 */ 2254 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 2255 { 2256 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2257 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2258 u32 chan = 0; 2259 2260 for (chan = 0; chan < rx_channels_count; chan++) 2261 stmmac_stop_rx_dma(priv, chan); 2262 2263 for (chan = 0; chan < tx_channels_count; chan++) 2264 stmmac_stop_tx_dma(priv, chan); 2265 } 2266 2267 /** 2268 * stmmac_dma_operation_mode - HW DMA operation mode 2269 * @priv: driver private structure 2270 * Description: it is used for configuring the DMA operation mode register in 2271 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 2272 */ 2273 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 2274 { 2275 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2276 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2277 int rxfifosz = priv->plat->rx_fifo_size; 2278 int txfifosz = priv->plat->tx_fifo_size; 2279 u32 txmode = 0; 2280 u32 rxmode = 0; 2281 u32 chan = 0; 2282 u8 qmode = 0; 2283 2284 if (rxfifosz == 0) 2285 rxfifosz = priv->dma_cap.rx_fifo_size; 2286 if (txfifosz == 0) 2287 txfifosz = priv->dma_cap.tx_fifo_size; 2288 2289 /* Adjust for real per queue fifo size */ 2290 rxfifosz /= rx_channels_count; 2291 txfifosz /= tx_channels_count; 2292 2293 if (priv->plat->force_thresh_dma_mode) { 2294 txmode = tc; 2295 rxmode = tc; 2296 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 2297 /* 2298 * In case of GMAC, SF mode can be enabled 2299 * to perform the TX COE in HW. This depends on: 2300 * 1) TX COE if actually supported 2301 * 2) There is no bugged Jumbo frame support 2302 * that needs to not insert csum in the TDES. 2303 */ 2304 txmode = SF_DMA_MODE; 2305 rxmode = SF_DMA_MODE; 2306 priv->xstats.threshold = SF_DMA_MODE; 2307 } else { 2308 txmode = tc; 2309 rxmode = SF_DMA_MODE; 2310 } 2311 2312 /* configure all channels */ 2313 for (chan = 0; chan < rx_channels_count; chan++) { 2314 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2315 u32 buf_size; 2316 2317 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2318 2319 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 2320 rxfifosz, qmode); 2321 2322 if (rx_q->xsk_pool) { 2323 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 2324 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2325 buf_size, 2326 chan); 2327 } else { 2328 stmmac_set_dma_bfsize(priv, priv->ioaddr, 2329 priv->dma_buf_sz, 2330 chan); 2331 } 2332 } 2333 2334 for (chan = 0; chan < tx_channels_count; chan++) { 2335 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2336 2337 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 2338 txfifosz, qmode); 2339 } 2340 } 2341 2342 static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 2343 { 2344 struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue); 2345 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2346 struct xsk_buff_pool *pool = tx_q->xsk_pool; 2347 unsigned int entry = tx_q->cur_tx; 2348 struct dma_desc *tx_desc = NULL; 2349 struct xdp_desc xdp_desc; 2350 bool work_done = true; 2351 2352 /* Avoids TX time-out as we are sharing with slow path */ 2353 nq->trans_start = jiffies; 2354 2355 budget = min(budget, stmmac_tx_avail(priv, queue)); 2356 2357 while (budget-- > 0) { 2358 dma_addr_t dma_addr; 2359 bool set_ic; 2360 2361 /* We are sharing with slow path and stop XSK TX desc submission when 2362 * available TX ring is less than threshold. 2363 */ 2364 if (unlikely(stmmac_tx_avail(priv, queue) < STMMAC_TX_XSK_AVAIL) || 2365 !netif_carrier_ok(priv->dev)) { 2366 work_done = false; 2367 break; 2368 } 2369 2370 if (!xsk_tx_peek_desc(pool, &xdp_desc)) 2371 break; 2372 2373 if (likely(priv->extend_desc)) 2374 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 2375 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2376 tx_desc = &tx_q->dma_entx[entry].basic; 2377 else 2378 tx_desc = tx_q->dma_tx + entry; 2379 2380 dma_addr = xsk_buff_raw_get_dma(pool, xdp_desc.addr); 2381 xsk_buff_raw_dma_sync_for_device(pool, dma_addr, xdp_desc.len); 2382 2383 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XSK_TX; 2384 2385 /* To return XDP buffer to XSK pool, we simple call 2386 * xsk_tx_completed(), so we don't need to fill up 2387 * 'buf' and 'xdpf'. 2388 */ 2389 tx_q->tx_skbuff_dma[entry].buf = 0; 2390 tx_q->xdpf[entry] = NULL; 2391 2392 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2393 tx_q->tx_skbuff_dma[entry].len = xdp_desc.len; 2394 tx_q->tx_skbuff_dma[entry].last_segment = true; 2395 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2396 2397 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 2398 2399 tx_q->tx_count_frames++; 2400 2401 if (!priv->tx_coal_frames[queue]) 2402 set_ic = false; 2403 else if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 2404 set_ic = true; 2405 else 2406 set_ic = false; 2407 2408 if (set_ic) { 2409 tx_q->tx_count_frames = 0; 2410 stmmac_set_tx_ic(priv, tx_desc); 2411 priv->xstats.tx_set_ic_bit++; 2412 } 2413 2414 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdp_desc.len, 2415 true, priv->mode, true, true, 2416 xdp_desc.len); 2417 2418 stmmac_enable_dma_transmission(priv, priv->ioaddr); 2419 2420 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 2421 entry = tx_q->cur_tx; 2422 } 2423 2424 if (tx_desc) { 2425 stmmac_flush_tx_descriptors(priv, queue); 2426 xsk_tx_release(pool); 2427 } 2428 2429 /* Return true if all of the 3 conditions are met 2430 * a) TX Budget is still available 2431 * b) work_done = true when XSK TX desc peek is empty (no more 2432 * pending XSK TX for transmission) 2433 */ 2434 return !!budget && work_done; 2435 } 2436 2437 /** 2438 * stmmac_tx_clean - to manage the transmission completion 2439 * @priv: driver private structure 2440 * @budget: napi budget limiting this functions packet handling 2441 * @queue: TX queue index 2442 * Description: it reclaims the transmit resources after transmission completes. 2443 */ 2444 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 2445 { 2446 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2447 unsigned int bytes_compl = 0, pkts_compl = 0; 2448 unsigned int entry, xmits = 0, count = 0; 2449 2450 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 2451 2452 priv->xstats.tx_clean++; 2453 2454 tx_q->xsk_frames_done = 0; 2455 2456 entry = tx_q->dirty_tx; 2457 2458 /* Try to clean all TX complete frame in 1 shot */ 2459 while ((entry != tx_q->cur_tx) && count < priv->dma_tx_size) { 2460 struct xdp_frame *xdpf; 2461 struct sk_buff *skb; 2462 struct dma_desc *p; 2463 int status; 2464 2465 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX || 2466 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2467 xdpf = tx_q->xdpf[entry]; 2468 skb = NULL; 2469 } else if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2470 xdpf = NULL; 2471 skb = tx_q->tx_skbuff[entry]; 2472 } else { 2473 xdpf = NULL; 2474 skb = NULL; 2475 } 2476 2477 if (priv->extend_desc) 2478 p = (struct dma_desc *)(tx_q->dma_etx + entry); 2479 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 2480 p = &tx_q->dma_entx[entry].basic; 2481 else 2482 p = tx_q->dma_tx + entry; 2483 2484 status = stmmac_tx_status(priv, &priv->dev->stats, 2485 &priv->xstats, p, priv->ioaddr); 2486 /* Check if the descriptor is owned by the DMA */ 2487 if (unlikely(status & tx_dma_own)) 2488 break; 2489 2490 count++; 2491 2492 /* Make sure descriptor fields are read after reading 2493 * the own bit. 2494 */ 2495 dma_rmb(); 2496 2497 /* Just consider the last segment and ...*/ 2498 if (likely(!(status & tx_not_ls))) { 2499 /* ... verify the status error condition */ 2500 if (unlikely(status & tx_err)) { 2501 priv->dev->stats.tx_errors++; 2502 } else { 2503 priv->dev->stats.tx_packets++; 2504 priv->xstats.tx_pkt_n++; 2505 } 2506 if (skb) 2507 stmmac_get_tx_hwtstamp(priv, p, skb); 2508 } 2509 2510 if (likely(tx_q->tx_skbuff_dma[entry].buf && 2511 tx_q->tx_skbuff_dma[entry].buf_type != STMMAC_TXBUF_T_XDP_TX)) { 2512 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2513 dma_unmap_page(priv->device, 2514 tx_q->tx_skbuff_dma[entry].buf, 2515 tx_q->tx_skbuff_dma[entry].len, 2516 DMA_TO_DEVICE); 2517 else 2518 dma_unmap_single(priv->device, 2519 tx_q->tx_skbuff_dma[entry].buf, 2520 tx_q->tx_skbuff_dma[entry].len, 2521 DMA_TO_DEVICE); 2522 tx_q->tx_skbuff_dma[entry].buf = 0; 2523 tx_q->tx_skbuff_dma[entry].len = 0; 2524 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2525 } 2526 2527 stmmac_clean_desc3(priv, tx_q, p); 2528 2529 tx_q->tx_skbuff_dma[entry].last_segment = false; 2530 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2531 2532 if (xdpf && 2533 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_TX) { 2534 xdp_return_frame_rx_napi(xdpf); 2535 tx_q->xdpf[entry] = NULL; 2536 } 2537 2538 if (xdpf && 2539 tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XDP_NDO) { 2540 xdp_return_frame(xdpf); 2541 tx_q->xdpf[entry] = NULL; 2542 } 2543 2544 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_XSK_TX) 2545 tx_q->xsk_frames_done++; 2546 2547 if (tx_q->tx_skbuff_dma[entry].buf_type == STMMAC_TXBUF_T_SKB) { 2548 if (likely(skb)) { 2549 pkts_compl++; 2550 bytes_compl += skb->len; 2551 dev_consume_skb_any(skb); 2552 tx_q->tx_skbuff[entry] = NULL; 2553 } 2554 } 2555 2556 stmmac_release_tx_desc(priv, p, priv->mode); 2557 2558 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2559 } 2560 tx_q->dirty_tx = entry; 2561 2562 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2563 pkts_compl, bytes_compl); 2564 2565 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2566 queue))) && 2567 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2568 2569 netif_dbg(priv, tx_done, priv->dev, 2570 "%s: restart transmit\n", __func__); 2571 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2572 } 2573 2574 if (tx_q->xsk_pool) { 2575 bool work_done; 2576 2577 if (tx_q->xsk_frames_done) 2578 xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done); 2579 2580 if (xsk_uses_need_wakeup(tx_q->xsk_pool)) 2581 xsk_set_tx_need_wakeup(tx_q->xsk_pool); 2582 2583 /* For XSK TX, we try to send as many as possible. 2584 * If XSK work done (XSK TX desc empty and budget still 2585 * available), return "budget - 1" to reenable TX IRQ. 2586 * Else, return "budget" to make NAPI continue polling. 2587 */ 2588 work_done = stmmac_xdp_xmit_zc(priv, queue, 2589 STMMAC_XSK_TX_BUDGET_MAX); 2590 if (work_done) 2591 xmits = budget - 1; 2592 else 2593 xmits = budget; 2594 } 2595 2596 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2597 priv->eee_sw_timer_en) { 2598 stmmac_enable_eee_mode(priv); 2599 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2600 } 2601 2602 /* We still have pending packets, let's call for a new scheduling */ 2603 if (tx_q->dirty_tx != tx_q->cur_tx) 2604 hrtimer_start(&tx_q->txtimer, 2605 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2606 HRTIMER_MODE_REL); 2607 2608 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2609 2610 /* Combine decisions from TX clean and XSK TX */ 2611 return max(count, xmits); 2612 } 2613 2614 /** 2615 * stmmac_tx_err - to manage the tx error 2616 * @priv: driver private structure 2617 * @chan: channel index 2618 * Description: it cleans the descriptors and restarts the transmission 2619 * in case of transmission errors. 2620 */ 2621 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2622 { 2623 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2624 2625 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2626 2627 stmmac_stop_tx_dma(priv, chan); 2628 dma_free_tx_skbufs(priv, chan); 2629 stmmac_clear_tx_descriptors(priv, chan); 2630 tx_q->dirty_tx = 0; 2631 tx_q->cur_tx = 0; 2632 tx_q->mss = 0; 2633 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2634 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2635 tx_q->dma_tx_phy, chan); 2636 stmmac_start_tx_dma(priv, chan); 2637 2638 priv->dev->stats.tx_errors++; 2639 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2640 } 2641 2642 /** 2643 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2644 * @priv: driver private structure 2645 * @txmode: TX operating mode 2646 * @rxmode: RX operating mode 2647 * @chan: channel index 2648 * Description: it is used for configuring of the DMA operation mode in 2649 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2650 * mode. 2651 */ 2652 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2653 u32 rxmode, u32 chan) 2654 { 2655 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2656 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2657 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2658 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2659 int rxfifosz = priv->plat->rx_fifo_size; 2660 int txfifosz = priv->plat->tx_fifo_size; 2661 2662 if (rxfifosz == 0) 2663 rxfifosz = priv->dma_cap.rx_fifo_size; 2664 if (txfifosz == 0) 2665 txfifosz = priv->dma_cap.tx_fifo_size; 2666 2667 /* Adjust for real per queue fifo size */ 2668 rxfifosz /= rx_channels_count; 2669 txfifosz /= tx_channels_count; 2670 2671 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2672 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2673 } 2674 2675 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2676 { 2677 int ret; 2678 2679 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2680 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2681 if (ret && (ret != -EINVAL)) { 2682 stmmac_global_err(priv); 2683 return true; 2684 } 2685 2686 return false; 2687 } 2688 2689 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan, u32 dir) 2690 { 2691 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2692 &priv->xstats, chan, dir); 2693 struct stmmac_rx_queue *rx_q = &priv->rx_queue[chan]; 2694 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2695 struct stmmac_channel *ch = &priv->channel[chan]; 2696 struct napi_struct *rx_napi; 2697 struct napi_struct *tx_napi; 2698 unsigned long flags; 2699 2700 rx_napi = rx_q->xsk_pool ? &ch->rxtx_napi : &ch->rx_napi; 2701 tx_napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2702 2703 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2704 if (napi_schedule_prep(rx_napi)) { 2705 spin_lock_irqsave(&ch->lock, flags); 2706 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2707 spin_unlock_irqrestore(&ch->lock, flags); 2708 __napi_schedule(rx_napi); 2709 } 2710 } 2711 2712 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2713 if (napi_schedule_prep(tx_napi)) { 2714 spin_lock_irqsave(&ch->lock, flags); 2715 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2716 spin_unlock_irqrestore(&ch->lock, flags); 2717 __napi_schedule(tx_napi); 2718 } 2719 } 2720 2721 return status; 2722 } 2723 2724 /** 2725 * stmmac_dma_interrupt - DMA ISR 2726 * @priv: driver private structure 2727 * Description: this is the DMA ISR. It is called by the main ISR. 2728 * It calls the dwmac dma routine and schedule poll method in case of some 2729 * work can be done. 2730 */ 2731 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2732 { 2733 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2734 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2735 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2736 tx_channel_count : rx_channel_count; 2737 u32 chan; 2738 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2739 2740 /* Make sure we never check beyond our status buffer. */ 2741 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2742 channels_to_check = ARRAY_SIZE(status); 2743 2744 for (chan = 0; chan < channels_to_check; chan++) 2745 status[chan] = stmmac_napi_check(priv, chan, 2746 DMA_DIR_RXTX); 2747 2748 for (chan = 0; chan < tx_channel_count; chan++) { 2749 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2750 /* Try to bump up the dma threshold on this failure */ 2751 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2752 (tc <= 256)) { 2753 tc += 64; 2754 if (priv->plat->force_thresh_dma_mode) 2755 stmmac_set_dma_operation_mode(priv, 2756 tc, 2757 tc, 2758 chan); 2759 else 2760 stmmac_set_dma_operation_mode(priv, 2761 tc, 2762 SF_DMA_MODE, 2763 chan); 2764 priv->xstats.threshold = tc; 2765 } 2766 } else if (unlikely(status[chan] == tx_hard_error)) { 2767 stmmac_tx_err(priv, chan); 2768 } 2769 } 2770 } 2771 2772 /** 2773 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2774 * @priv: driver private structure 2775 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2776 */ 2777 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2778 { 2779 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2780 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2781 2782 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2783 2784 if (priv->dma_cap.rmon) { 2785 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2786 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2787 } else 2788 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2789 } 2790 2791 /** 2792 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2793 * @priv: driver private structure 2794 * Description: 2795 * new GMAC chip generations have a new register to indicate the 2796 * presence of the optional feature/functions. 2797 * This can be also used to override the value passed through the 2798 * platform and necessary for old MAC10/100 and GMAC chips. 2799 */ 2800 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2801 { 2802 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2803 } 2804 2805 /** 2806 * stmmac_check_ether_addr - check if the MAC addr is valid 2807 * @priv: driver private structure 2808 * Description: 2809 * it is to verify if the MAC address is valid, in case of failures it 2810 * generates a random MAC address 2811 */ 2812 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2813 { 2814 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2815 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2816 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2817 eth_hw_addr_random(priv->dev); 2818 dev_info(priv->device, "device MAC address %pM\n", 2819 priv->dev->dev_addr); 2820 } 2821 } 2822 2823 /** 2824 * stmmac_init_dma_engine - DMA init. 2825 * @priv: driver private structure 2826 * Description: 2827 * It inits the DMA invoking the specific MAC/GMAC callback. 2828 * Some DMA parameters can be passed from the platform; 2829 * in case of these are not passed a default is kept for the MAC or GMAC. 2830 */ 2831 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2832 { 2833 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2834 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2835 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2836 struct stmmac_rx_queue *rx_q; 2837 struct stmmac_tx_queue *tx_q; 2838 u32 chan = 0; 2839 int atds = 0; 2840 int ret = 0; 2841 2842 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2843 dev_err(priv->device, "Invalid DMA configuration\n"); 2844 return -EINVAL; 2845 } 2846 2847 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2848 atds = 1; 2849 2850 ret = stmmac_reset(priv, priv->ioaddr); 2851 if (ret) { 2852 dev_err(priv->device, "Failed to reset the dma\n"); 2853 return ret; 2854 } 2855 2856 /* DMA Configuration */ 2857 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2858 2859 if (priv->plat->axi) 2860 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2861 2862 /* DMA CSR Channel configuration */ 2863 for (chan = 0; chan < dma_csr_ch; chan++) 2864 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2865 2866 /* DMA RX Channel Configuration */ 2867 for (chan = 0; chan < rx_channels_count; chan++) { 2868 rx_q = &priv->rx_queue[chan]; 2869 2870 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2871 rx_q->dma_rx_phy, chan); 2872 2873 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2874 (rx_q->buf_alloc_num * 2875 sizeof(struct dma_desc)); 2876 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2877 rx_q->rx_tail_addr, chan); 2878 } 2879 2880 /* DMA TX Channel Configuration */ 2881 for (chan = 0; chan < tx_channels_count; chan++) { 2882 tx_q = &priv->tx_queue[chan]; 2883 2884 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2885 tx_q->dma_tx_phy, chan); 2886 2887 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2888 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2889 tx_q->tx_tail_addr, chan); 2890 } 2891 2892 return ret; 2893 } 2894 2895 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2896 { 2897 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2898 2899 hrtimer_start(&tx_q->txtimer, 2900 STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]), 2901 HRTIMER_MODE_REL); 2902 } 2903 2904 /** 2905 * stmmac_tx_timer - mitigation sw timer for tx. 2906 * @t: data pointer 2907 * Description: 2908 * This is the timer handler to directly invoke the stmmac_tx_clean. 2909 */ 2910 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2911 { 2912 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2913 struct stmmac_priv *priv = tx_q->priv_data; 2914 struct stmmac_channel *ch; 2915 struct napi_struct *napi; 2916 2917 ch = &priv->channel[tx_q->queue_index]; 2918 napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi; 2919 2920 if (likely(napi_schedule_prep(napi))) { 2921 unsigned long flags; 2922 2923 spin_lock_irqsave(&ch->lock, flags); 2924 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2925 spin_unlock_irqrestore(&ch->lock, flags); 2926 __napi_schedule(napi); 2927 } 2928 2929 return HRTIMER_NORESTART; 2930 } 2931 2932 /** 2933 * stmmac_init_coalesce - init mitigation options. 2934 * @priv: driver private structure 2935 * Description: 2936 * This inits the coalesce parameters: i.e. timer rate, 2937 * timer handler and default threshold used for enabling the 2938 * interrupt on completion bit. 2939 */ 2940 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2941 { 2942 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2943 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2944 u32 chan; 2945 2946 for (chan = 0; chan < tx_channel_count; chan++) { 2947 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2948 2949 priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES; 2950 priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER; 2951 2952 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2953 tx_q->txtimer.function = stmmac_tx_timer; 2954 } 2955 2956 for (chan = 0; chan < rx_channel_count; chan++) 2957 priv->rx_coal_frames[chan] = STMMAC_RX_FRAMES; 2958 } 2959 2960 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2961 { 2962 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2963 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2964 u32 chan; 2965 2966 /* set TX ring length */ 2967 for (chan = 0; chan < tx_channels_count; chan++) 2968 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2969 (priv->dma_tx_size - 1), chan); 2970 2971 /* set RX ring length */ 2972 for (chan = 0; chan < rx_channels_count; chan++) 2973 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2974 (priv->dma_rx_size - 1), chan); 2975 } 2976 2977 /** 2978 * stmmac_set_tx_queue_weight - Set TX queue weight 2979 * @priv: driver private structure 2980 * Description: It is used for setting TX queues weight 2981 */ 2982 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2983 { 2984 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2985 u32 weight; 2986 u32 queue; 2987 2988 for (queue = 0; queue < tx_queues_count; queue++) { 2989 weight = priv->plat->tx_queues_cfg[queue].weight; 2990 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2991 } 2992 } 2993 2994 /** 2995 * stmmac_configure_cbs - Configure CBS in TX queue 2996 * @priv: driver private structure 2997 * Description: It is used for configuring CBS in AVB TX queues 2998 */ 2999 static void stmmac_configure_cbs(struct stmmac_priv *priv) 3000 { 3001 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3002 u32 mode_to_use; 3003 u32 queue; 3004 3005 /* queue 0 is reserved for legacy traffic */ 3006 for (queue = 1; queue < tx_queues_count; queue++) { 3007 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 3008 if (mode_to_use == MTL_QUEUE_DCB) 3009 continue; 3010 3011 stmmac_config_cbs(priv, priv->hw, 3012 priv->plat->tx_queues_cfg[queue].send_slope, 3013 priv->plat->tx_queues_cfg[queue].idle_slope, 3014 priv->plat->tx_queues_cfg[queue].high_credit, 3015 priv->plat->tx_queues_cfg[queue].low_credit, 3016 queue); 3017 } 3018 } 3019 3020 /** 3021 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 3022 * @priv: driver private structure 3023 * Description: It is used for mapping RX queues to RX dma channels 3024 */ 3025 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 3026 { 3027 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3028 u32 queue; 3029 u32 chan; 3030 3031 for (queue = 0; queue < rx_queues_count; queue++) { 3032 chan = priv->plat->rx_queues_cfg[queue].chan; 3033 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 3034 } 3035 } 3036 3037 /** 3038 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 3039 * @priv: driver private structure 3040 * Description: It is used for configuring the RX Queue Priority 3041 */ 3042 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 3043 { 3044 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3045 u32 queue; 3046 u32 prio; 3047 3048 for (queue = 0; queue < rx_queues_count; queue++) { 3049 if (!priv->plat->rx_queues_cfg[queue].use_prio) 3050 continue; 3051 3052 prio = priv->plat->rx_queues_cfg[queue].prio; 3053 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 3054 } 3055 } 3056 3057 /** 3058 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 3059 * @priv: driver private structure 3060 * Description: It is used for configuring the TX Queue Priority 3061 */ 3062 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 3063 { 3064 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3065 u32 queue; 3066 u32 prio; 3067 3068 for (queue = 0; queue < tx_queues_count; queue++) { 3069 if (!priv->plat->tx_queues_cfg[queue].use_prio) 3070 continue; 3071 3072 prio = priv->plat->tx_queues_cfg[queue].prio; 3073 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 3074 } 3075 } 3076 3077 /** 3078 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 3079 * @priv: driver private structure 3080 * Description: It is used for configuring the RX queue routing 3081 */ 3082 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 3083 { 3084 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3085 u32 queue; 3086 u8 packet; 3087 3088 for (queue = 0; queue < rx_queues_count; queue++) { 3089 /* no specific packet type routing specified for the queue */ 3090 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 3091 continue; 3092 3093 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 3094 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 3095 } 3096 } 3097 3098 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 3099 { 3100 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 3101 priv->rss.enable = false; 3102 return; 3103 } 3104 3105 if (priv->dev->features & NETIF_F_RXHASH) 3106 priv->rss.enable = true; 3107 else 3108 priv->rss.enable = false; 3109 3110 stmmac_rss_configure(priv, priv->hw, &priv->rss, 3111 priv->plat->rx_queues_to_use); 3112 } 3113 3114 /** 3115 * stmmac_mtl_configuration - Configure MTL 3116 * @priv: driver private structure 3117 * Description: It is used for configurring MTL 3118 */ 3119 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 3120 { 3121 u32 rx_queues_count = priv->plat->rx_queues_to_use; 3122 u32 tx_queues_count = priv->plat->tx_queues_to_use; 3123 3124 if (tx_queues_count > 1) 3125 stmmac_set_tx_queue_weight(priv); 3126 3127 /* Configure MTL RX algorithms */ 3128 if (rx_queues_count > 1) 3129 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 3130 priv->plat->rx_sched_algorithm); 3131 3132 /* Configure MTL TX algorithms */ 3133 if (tx_queues_count > 1) 3134 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 3135 priv->plat->tx_sched_algorithm); 3136 3137 /* Configure CBS in AVB TX queues */ 3138 if (tx_queues_count > 1) 3139 stmmac_configure_cbs(priv); 3140 3141 /* Map RX MTL to DMA channels */ 3142 stmmac_rx_queue_dma_chan_map(priv); 3143 3144 /* Enable MAC RX Queues */ 3145 stmmac_mac_enable_rx_queues(priv); 3146 3147 /* Set RX priorities */ 3148 if (rx_queues_count > 1) 3149 stmmac_mac_config_rx_queues_prio(priv); 3150 3151 /* Set TX priorities */ 3152 if (tx_queues_count > 1) 3153 stmmac_mac_config_tx_queues_prio(priv); 3154 3155 /* Set RX routing */ 3156 if (rx_queues_count > 1) 3157 stmmac_mac_config_rx_queues_routing(priv); 3158 3159 /* Receive Side Scaling */ 3160 if (rx_queues_count > 1) 3161 stmmac_mac_config_rss(priv); 3162 } 3163 3164 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 3165 { 3166 if (priv->dma_cap.asp) { 3167 netdev_info(priv->dev, "Enabling Safety Features\n"); 3168 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp, 3169 priv->plat->safety_feat_cfg); 3170 } else { 3171 netdev_info(priv->dev, "No Safety Features support found\n"); 3172 } 3173 } 3174 3175 static int stmmac_fpe_start_wq(struct stmmac_priv *priv) 3176 { 3177 char *name; 3178 3179 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 3180 clear_bit(__FPE_REMOVING, &priv->fpe_task_state); 3181 3182 name = priv->wq_name; 3183 sprintf(name, "%s-fpe", priv->dev->name); 3184 3185 priv->fpe_wq = create_singlethread_workqueue(name); 3186 if (!priv->fpe_wq) { 3187 netdev_err(priv->dev, "%s: Failed to create workqueue\n", name); 3188 3189 return -ENOMEM; 3190 } 3191 netdev_info(priv->dev, "FPE workqueue start"); 3192 3193 return 0; 3194 } 3195 3196 /** 3197 * stmmac_hw_setup - setup mac in a usable state. 3198 * @dev : pointer to the device structure. 3199 * @init_ptp: initialize PTP if set 3200 * Description: 3201 * this is the main function to setup the HW in a usable state because the 3202 * dma engine is reset, the core registers are configured (e.g. AXI, 3203 * Checksum features, timers). The DMA is ready to start receiving and 3204 * transmitting. 3205 * Return value: 3206 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3207 * file on failure. 3208 */ 3209 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 3210 { 3211 struct stmmac_priv *priv = netdev_priv(dev); 3212 u32 rx_cnt = priv->plat->rx_queues_to_use; 3213 u32 tx_cnt = priv->plat->tx_queues_to_use; 3214 bool sph_en; 3215 u32 chan; 3216 int ret; 3217 3218 /* DMA initialization and SW reset */ 3219 ret = stmmac_init_dma_engine(priv); 3220 if (ret < 0) { 3221 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 3222 __func__); 3223 return ret; 3224 } 3225 3226 /* Copy the MAC addr into the HW */ 3227 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 3228 3229 /* PS and related bits will be programmed according to the speed */ 3230 if (priv->hw->pcs) { 3231 int speed = priv->plat->mac_port_sel_speed; 3232 3233 if ((speed == SPEED_10) || (speed == SPEED_100) || 3234 (speed == SPEED_1000)) { 3235 priv->hw->ps = speed; 3236 } else { 3237 dev_warn(priv->device, "invalid port speed\n"); 3238 priv->hw->ps = 0; 3239 } 3240 } 3241 3242 /* Initialize the MAC Core */ 3243 stmmac_core_init(priv, priv->hw, dev); 3244 3245 /* Initialize MTL*/ 3246 stmmac_mtl_configuration(priv); 3247 3248 /* Initialize Safety Features */ 3249 stmmac_safety_feat_configuration(priv); 3250 3251 ret = stmmac_rx_ipc(priv, priv->hw); 3252 if (!ret) { 3253 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 3254 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 3255 priv->hw->rx_csum = 0; 3256 } 3257 3258 /* Enable the MAC Rx/Tx */ 3259 stmmac_mac_set(priv, priv->ioaddr, true); 3260 3261 /* Set the HW DMA mode and the COE */ 3262 stmmac_dma_operation_mode(priv); 3263 3264 stmmac_mmc_setup(priv); 3265 3266 if (init_ptp) { 3267 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 3268 if (ret < 0) 3269 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 3270 3271 ret = stmmac_init_ptp(priv); 3272 if (ret == -EOPNOTSUPP) 3273 netdev_warn(priv->dev, "PTP not supported by HW\n"); 3274 else if (ret) 3275 netdev_warn(priv->dev, "PTP init failed\n"); 3276 } 3277 3278 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 3279 3280 /* Convert the timer from msec to usec */ 3281 if (!priv->tx_lpi_timer) 3282 priv->tx_lpi_timer = eee_timer * 1000; 3283 3284 if (priv->use_riwt) { 3285 u32 queue; 3286 3287 for (queue = 0; queue < rx_cnt; queue++) { 3288 if (!priv->rx_riwt[queue]) 3289 priv->rx_riwt[queue] = DEF_DMA_RIWT; 3290 3291 stmmac_rx_watchdog(priv, priv->ioaddr, 3292 priv->rx_riwt[queue], queue); 3293 } 3294 } 3295 3296 if (priv->hw->pcs) 3297 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 3298 3299 /* set TX and RX rings length */ 3300 stmmac_set_rings_length(priv); 3301 3302 /* Enable TSO */ 3303 if (priv->tso) { 3304 for (chan = 0; chan < tx_cnt; chan++) { 3305 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3306 3307 /* TSO and TBS cannot co-exist */ 3308 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3309 continue; 3310 3311 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 3312 } 3313 } 3314 3315 /* Enable Split Header */ 3316 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3317 for (chan = 0; chan < rx_cnt; chan++) 3318 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3319 3320 3321 /* VLAN Tag Insertion */ 3322 if (priv->dma_cap.vlins) 3323 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 3324 3325 /* TBS */ 3326 for (chan = 0; chan < tx_cnt; chan++) { 3327 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3328 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 3329 3330 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 3331 } 3332 3333 /* Configure real RX and TX queues */ 3334 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 3335 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 3336 3337 /* Start the ball rolling... */ 3338 stmmac_start_all_dma(priv); 3339 3340 if (priv->dma_cap.fpesel) { 3341 stmmac_fpe_start_wq(priv); 3342 3343 if (priv->plat->fpe_cfg->enable) 3344 stmmac_fpe_handshake(priv, true); 3345 } 3346 3347 return 0; 3348 } 3349 3350 static void stmmac_hw_teardown(struct net_device *dev) 3351 { 3352 struct stmmac_priv *priv = netdev_priv(dev); 3353 3354 clk_disable_unprepare(priv->plat->clk_ptp_ref); 3355 } 3356 3357 static void stmmac_free_irq(struct net_device *dev, 3358 enum request_irq_err irq_err, int irq_idx) 3359 { 3360 struct stmmac_priv *priv = netdev_priv(dev); 3361 int j; 3362 3363 switch (irq_err) { 3364 case REQ_IRQ_ERR_ALL: 3365 irq_idx = priv->plat->tx_queues_to_use; 3366 fallthrough; 3367 case REQ_IRQ_ERR_TX: 3368 for (j = irq_idx - 1; j >= 0; j--) { 3369 if (priv->tx_irq[j] > 0) { 3370 irq_set_affinity_hint(priv->tx_irq[j], NULL); 3371 free_irq(priv->tx_irq[j], &priv->tx_queue[j]); 3372 } 3373 } 3374 irq_idx = priv->plat->rx_queues_to_use; 3375 fallthrough; 3376 case REQ_IRQ_ERR_RX: 3377 for (j = irq_idx - 1; j >= 0; j--) { 3378 if (priv->rx_irq[j] > 0) { 3379 irq_set_affinity_hint(priv->rx_irq[j], NULL); 3380 free_irq(priv->rx_irq[j], &priv->rx_queue[j]); 3381 } 3382 } 3383 3384 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) 3385 free_irq(priv->sfty_ue_irq, dev); 3386 fallthrough; 3387 case REQ_IRQ_ERR_SFTY_UE: 3388 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) 3389 free_irq(priv->sfty_ce_irq, dev); 3390 fallthrough; 3391 case REQ_IRQ_ERR_SFTY_CE: 3392 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) 3393 free_irq(priv->lpi_irq, dev); 3394 fallthrough; 3395 case REQ_IRQ_ERR_LPI: 3396 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) 3397 free_irq(priv->wol_irq, dev); 3398 fallthrough; 3399 case REQ_IRQ_ERR_WOL: 3400 free_irq(dev->irq, dev); 3401 fallthrough; 3402 case REQ_IRQ_ERR_MAC: 3403 case REQ_IRQ_ERR_NO: 3404 /* If MAC IRQ request error, no more IRQ to free */ 3405 break; 3406 } 3407 } 3408 3409 static int stmmac_request_irq_multi_msi(struct net_device *dev) 3410 { 3411 enum request_irq_err irq_err = REQ_IRQ_ERR_NO; 3412 struct stmmac_priv *priv = netdev_priv(dev); 3413 cpumask_t cpu_mask; 3414 int irq_idx = 0; 3415 char *int_name; 3416 int ret; 3417 int i; 3418 3419 /* For common interrupt */ 3420 int_name = priv->int_name_mac; 3421 sprintf(int_name, "%s:%s", dev->name, "mac"); 3422 ret = request_irq(dev->irq, stmmac_mac_interrupt, 3423 0, int_name, dev); 3424 if (unlikely(ret < 0)) { 3425 netdev_err(priv->dev, 3426 "%s: alloc mac MSI %d (error: %d)\n", 3427 __func__, dev->irq, ret); 3428 irq_err = REQ_IRQ_ERR_MAC; 3429 goto irq_error; 3430 } 3431 3432 /* Request the Wake IRQ in case of another line 3433 * is used for WoL 3434 */ 3435 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3436 int_name = priv->int_name_wol; 3437 sprintf(int_name, "%s:%s", dev->name, "wol"); 3438 ret = request_irq(priv->wol_irq, 3439 stmmac_mac_interrupt, 3440 0, int_name, dev); 3441 if (unlikely(ret < 0)) { 3442 netdev_err(priv->dev, 3443 "%s: alloc wol MSI %d (error: %d)\n", 3444 __func__, priv->wol_irq, ret); 3445 irq_err = REQ_IRQ_ERR_WOL; 3446 goto irq_error; 3447 } 3448 } 3449 3450 /* Request the LPI IRQ in case of another line 3451 * is used for LPI 3452 */ 3453 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3454 int_name = priv->int_name_lpi; 3455 sprintf(int_name, "%s:%s", dev->name, "lpi"); 3456 ret = request_irq(priv->lpi_irq, 3457 stmmac_mac_interrupt, 3458 0, int_name, dev); 3459 if (unlikely(ret < 0)) { 3460 netdev_err(priv->dev, 3461 "%s: alloc lpi MSI %d (error: %d)\n", 3462 __func__, priv->lpi_irq, ret); 3463 irq_err = REQ_IRQ_ERR_LPI; 3464 goto irq_error; 3465 } 3466 } 3467 3468 /* Request the Safety Feature Correctible Error line in 3469 * case of another line is used 3470 */ 3471 if (priv->sfty_ce_irq > 0 && priv->sfty_ce_irq != dev->irq) { 3472 int_name = priv->int_name_sfty_ce; 3473 sprintf(int_name, "%s:%s", dev->name, "safety-ce"); 3474 ret = request_irq(priv->sfty_ce_irq, 3475 stmmac_safety_interrupt, 3476 0, int_name, dev); 3477 if (unlikely(ret < 0)) { 3478 netdev_err(priv->dev, 3479 "%s: alloc sfty ce MSI %d (error: %d)\n", 3480 __func__, priv->sfty_ce_irq, ret); 3481 irq_err = REQ_IRQ_ERR_SFTY_CE; 3482 goto irq_error; 3483 } 3484 } 3485 3486 /* Request the Safety Feature Uncorrectible Error line in 3487 * case of another line is used 3488 */ 3489 if (priv->sfty_ue_irq > 0 && priv->sfty_ue_irq != dev->irq) { 3490 int_name = priv->int_name_sfty_ue; 3491 sprintf(int_name, "%s:%s", dev->name, "safety-ue"); 3492 ret = request_irq(priv->sfty_ue_irq, 3493 stmmac_safety_interrupt, 3494 0, int_name, dev); 3495 if (unlikely(ret < 0)) { 3496 netdev_err(priv->dev, 3497 "%s: alloc sfty ue MSI %d (error: %d)\n", 3498 __func__, priv->sfty_ue_irq, ret); 3499 irq_err = REQ_IRQ_ERR_SFTY_UE; 3500 goto irq_error; 3501 } 3502 } 3503 3504 /* Request Rx MSI irq */ 3505 for (i = 0; i < priv->plat->rx_queues_to_use; i++) { 3506 if (priv->rx_irq[i] == 0) 3507 continue; 3508 3509 int_name = priv->int_name_rx_irq[i]; 3510 sprintf(int_name, "%s:%s-%d", dev->name, "rx", i); 3511 ret = request_irq(priv->rx_irq[i], 3512 stmmac_msi_intr_rx, 3513 0, int_name, &priv->rx_queue[i]); 3514 if (unlikely(ret < 0)) { 3515 netdev_err(priv->dev, 3516 "%s: alloc rx-%d MSI %d (error: %d)\n", 3517 __func__, i, priv->rx_irq[i], ret); 3518 irq_err = REQ_IRQ_ERR_RX; 3519 irq_idx = i; 3520 goto irq_error; 3521 } 3522 cpumask_clear(&cpu_mask); 3523 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3524 irq_set_affinity_hint(priv->rx_irq[i], &cpu_mask); 3525 } 3526 3527 /* Request Tx MSI irq */ 3528 for (i = 0; i < priv->plat->tx_queues_to_use; i++) { 3529 if (priv->tx_irq[i] == 0) 3530 continue; 3531 3532 int_name = priv->int_name_tx_irq[i]; 3533 sprintf(int_name, "%s:%s-%d", dev->name, "tx", i); 3534 ret = request_irq(priv->tx_irq[i], 3535 stmmac_msi_intr_tx, 3536 0, int_name, &priv->tx_queue[i]); 3537 if (unlikely(ret < 0)) { 3538 netdev_err(priv->dev, 3539 "%s: alloc tx-%d MSI %d (error: %d)\n", 3540 __func__, i, priv->tx_irq[i], ret); 3541 irq_err = REQ_IRQ_ERR_TX; 3542 irq_idx = i; 3543 goto irq_error; 3544 } 3545 cpumask_clear(&cpu_mask); 3546 cpumask_set_cpu(i % num_online_cpus(), &cpu_mask); 3547 irq_set_affinity_hint(priv->tx_irq[i], &cpu_mask); 3548 } 3549 3550 return 0; 3551 3552 irq_error: 3553 stmmac_free_irq(dev, irq_err, irq_idx); 3554 return ret; 3555 } 3556 3557 static int stmmac_request_irq_single(struct net_device *dev) 3558 { 3559 enum request_irq_err irq_err = REQ_IRQ_ERR_NO; 3560 struct stmmac_priv *priv = netdev_priv(dev); 3561 int ret; 3562 3563 ret = request_irq(dev->irq, stmmac_interrupt, 3564 IRQF_SHARED, dev->name, dev); 3565 if (unlikely(ret < 0)) { 3566 netdev_err(priv->dev, 3567 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 3568 __func__, dev->irq, ret); 3569 irq_err = REQ_IRQ_ERR_MAC; 3570 return ret; 3571 } 3572 3573 /* Request the Wake IRQ in case of another line 3574 * is used for WoL 3575 */ 3576 if (priv->wol_irq > 0 && priv->wol_irq != dev->irq) { 3577 ret = request_irq(priv->wol_irq, stmmac_interrupt, 3578 IRQF_SHARED, dev->name, dev); 3579 if (unlikely(ret < 0)) { 3580 netdev_err(priv->dev, 3581 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 3582 __func__, priv->wol_irq, ret); 3583 irq_err = REQ_IRQ_ERR_WOL; 3584 return ret; 3585 } 3586 } 3587 3588 /* Request the IRQ lines */ 3589 if (priv->lpi_irq > 0 && priv->lpi_irq != dev->irq) { 3590 ret = request_irq(priv->lpi_irq, stmmac_interrupt, 3591 IRQF_SHARED, dev->name, dev); 3592 if (unlikely(ret < 0)) { 3593 netdev_err(priv->dev, 3594 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 3595 __func__, priv->lpi_irq, ret); 3596 irq_err = REQ_IRQ_ERR_LPI; 3597 goto irq_error; 3598 } 3599 } 3600 3601 return 0; 3602 3603 irq_error: 3604 stmmac_free_irq(dev, irq_err, 0); 3605 return ret; 3606 } 3607 3608 static int stmmac_request_irq(struct net_device *dev) 3609 { 3610 struct stmmac_priv *priv = netdev_priv(dev); 3611 int ret; 3612 3613 /* Request the IRQ lines */ 3614 if (priv->plat->multi_msi_en) 3615 ret = stmmac_request_irq_multi_msi(dev); 3616 else 3617 ret = stmmac_request_irq_single(dev); 3618 3619 return ret; 3620 } 3621 3622 /** 3623 * stmmac_open - open entry point of the driver 3624 * @dev : pointer to the device structure. 3625 * Description: 3626 * This function is the open entry point of the driver. 3627 * Return value: 3628 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3629 * file on failure. 3630 */ 3631 int stmmac_open(struct net_device *dev) 3632 { 3633 struct stmmac_priv *priv = netdev_priv(dev); 3634 int mode = priv->plat->phy_interface; 3635 int bfsize = 0; 3636 u32 chan; 3637 int ret; 3638 3639 ret = pm_runtime_get_sync(priv->device); 3640 if (ret < 0) { 3641 pm_runtime_put_noidle(priv->device); 3642 return ret; 3643 } 3644 3645 if (priv->hw->pcs != STMMAC_PCS_TBI && 3646 priv->hw->pcs != STMMAC_PCS_RTBI && 3647 (!priv->hw->xpcs || 3648 xpcs_get_an_mode(priv->hw->xpcs, mode) != DW_AN_C73)) { 3649 ret = stmmac_init_phy(dev); 3650 if (ret) { 3651 netdev_err(priv->dev, 3652 "%s: Cannot attach to PHY (error: %d)\n", 3653 __func__, ret); 3654 goto init_phy_error; 3655 } 3656 } 3657 3658 /* Extra statistics */ 3659 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 3660 priv->xstats.threshold = tc; 3661 3662 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 3663 if (bfsize < 0) 3664 bfsize = 0; 3665 3666 if (bfsize < BUF_SIZE_16KiB) 3667 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 3668 3669 priv->dma_buf_sz = bfsize; 3670 buf_sz = bfsize; 3671 3672 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 3673 3674 if (!priv->dma_tx_size) 3675 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 3676 if (!priv->dma_rx_size) 3677 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 3678 3679 /* Earlier check for TBS */ 3680 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 3681 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 3682 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 3683 3684 /* Setup per-TXQ tbs flag before TX descriptor alloc */ 3685 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 3686 } 3687 3688 ret = alloc_dma_desc_resources(priv); 3689 if (ret < 0) { 3690 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 3691 __func__); 3692 goto dma_desc_error; 3693 } 3694 3695 ret = init_dma_desc_rings(dev, GFP_KERNEL); 3696 if (ret < 0) { 3697 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 3698 __func__); 3699 goto init_error; 3700 } 3701 3702 ret = stmmac_hw_setup(dev, true); 3703 if (ret < 0) { 3704 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 3705 goto init_error; 3706 } 3707 3708 stmmac_init_coalesce(priv); 3709 3710 phylink_start(priv->phylink); 3711 /* We may have called phylink_speed_down before */ 3712 phylink_speed_up(priv->phylink); 3713 3714 ret = stmmac_request_irq(dev); 3715 if (ret) 3716 goto irq_error; 3717 3718 stmmac_enable_all_queues(priv); 3719 netif_tx_start_all_queues(priv->dev); 3720 3721 return 0; 3722 3723 irq_error: 3724 phylink_stop(priv->phylink); 3725 3726 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3727 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3728 3729 stmmac_hw_teardown(dev); 3730 init_error: 3731 free_dma_desc_resources(priv); 3732 dma_desc_error: 3733 phylink_disconnect_phy(priv->phylink); 3734 init_phy_error: 3735 pm_runtime_put(priv->device); 3736 return ret; 3737 } 3738 3739 static void stmmac_fpe_stop_wq(struct stmmac_priv *priv) 3740 { 3741 set_bit(__FPE_REMOVING, &priv->fpe_task_state); 3742 3743 if (priv->fpe_wq) 3744 destroy_workqueue(priv->fpe_wq); 3745 3746 netdev_info(priv->dev, "FPE workqueue stop"); 3747 } 3748 3749 /** 3750 * stmmac_release - close entry point of the driver 3751 * @dev : device pointer. 3752 * Description: 3753 * This is the stop entry point of the driver. 3754 */ 3755 int stmmac_release(struct net_device *dev) 3756 { 3757 struct stmmac_priv *priv = netdev_priv(dev); 3758 u32 chan; 3759 3760 if (device_may_wakeup(priv->device)) 3761 phylink_speed_down(priv->phylink, false); 3762 /* Stop and disconnect the PHY */ 3763 phylink_stop(priv->phylink); 3764 phylink_disconnect_phy(priv->phylink); 3765 3766 stmmac_disable_all_queues(priv); 3767 3768 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 3769 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 3770 3771 /* Free the IRQ lines */ 3772 stmmac_free_irq(dev, REQ_IRQ_ERR_ALL, 0); 3773 3774 if (priv->eee_enabled) { 3775 priv->tx_path_in_lpi_mode = false; 3776 del_timer_sync(&priv->eee_ctrl_timer); 3777 } 3778 3779 /* Stop TX/RX DMA and clear the descriptors */ 3780 stmmac_stop_all_dma(priv); 3781 3782 /* Release and free the Rx/Tx resources */ 3783 free_dma_desc_resources(priv); 3784 3785 /* Disable the MAC Rx/Tx */ 3786 stmmac_mac_set(priv, priv->ioaddr, false); 3787 3788 netif_carrier_off(dev); 3789 3790 stmmac_release_ptp(priv); 3791 3792 pm_runtime_put(priv->device); 3793 3794 if (priv->dma_cap.fpesel) 3795 stmmac_fpe_stop_wq(priv); 3796 3797 return 0; 3798 } 3799 3800 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 3801 struct stmmac_tx_queue *tx_q) 3802 { 3803 u16 tag = 0x0, inner_tag = 0x0; 3804 u32 inner_type = 0x0; 3805 struct dma_desc *p; 3806 3807 if (!priv->dma_cap.vlins) 3808 return false; 3809 if (!skb_vlan_tag_present(skb)) 3810 return false; 3811 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 3812 inner_tag = skb_vlan_tag_get(skb); 3813 inner_type = STMMAC_VLAN_INSERT; 3814 } 3815 3816 tag = skb_vlan_tag_get(skb); 3817 3818 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3819 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 3820 else 3821 p = &tx_q->dma_tx[tx_q->cur_tx]; 3822 3823 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 3824 return false; 3825 3826 stmmac_set_tx_owner(priv, p); 3827 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3828 return true; 3829 } 3830 3831 /** 3832 * stmmac_tso_allocator - close entry point of the driver 3833 * @priv: driver private structure 3834 * @des: buffer start address 3835 * @total_len: total length to fill in descriptors 3836 * @last_segment: condition for the last descriptor 3837 * @queue: TX queue index 3838 * Description: 3839 * This function fills descriptor and request new descriptors according to 3840 * buffer length to fill 3841 */ 3842 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3843 int total_len, bool last_segment, u32 queue) 3844 { 3845 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3846 struct dma_desc *desc; 3847 u32 buff_size; 3848 int tmp_len; 3849 3850 tmp_len = total_len; 3851 3852 while (tmp_len > 0) { 3853 dma_addr_t curr_addr; 3854 3855 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3856 priv->dma_tx_size); 3857 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3858 3859 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3860 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3861 else 3862 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3863 3864 curr_addr = des + (total_len - tmp_len); 3865 if (priv->dma_cap.addr64 <= 32) 3866 desc->des0 = cpu_to_le32(curr_addr); 3867 else 3868 stmmac_set_desc_addr(priv, desc, curr_addr); 3869 3870 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3871 TSO_MAX_BUFF_SIZE : tmp_len; 3872 3873 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3874 0, 1, 3875 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3876 0, 0); 3877 3878 tmp_len -= TSO_MAX_BUFF_SIZE; 3879 } 3880 } 3881 3882 static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue) 3883 { 3884 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3885 int desc_size; 3886 3887 if (likely(priv->extend_desc)) 3888 desc_size = sizeof(struct dma_extended_desc); 3889 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3890 desc_size = sizeof(struct dma_edesc); 3891 else 3892 desc_size = sizeof(struct dma_desc); 3893 3894 /* The own bit must be the latest setting done when prepare the 3895 * descriptor and then barrier is needed to make sure that 3896 * all is coherent before granting the DMA engine. 3897 */ 3898 wmb(); 3899 3900 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3901 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3902 } 3903 3904 /** 3905 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3906 * @skb : the socket buffer 3907 * @dev : device pointer 3908 * Description: this is the transmit function that is called on TSO frames 3909 * (support available on GMAC4 and newer chips). 3910 * Diagram below show the ring programming in case of TSO frames: 3911 * 3912 * First Descriptor 3913 * -------- 3914 * | DES0 |---> buffer1 = L2/L3/L4 header 3915 * | DES1 |---> TCP Payload (can continue on next descr...) 3916 * | DES2 |---> buffer 1 and 2 len 3917 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3918 * -------- 3919 * | 3920 * ... 3921 * | 3922 * -------- 3923 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3924 * | DES1 | --| 3925 * | DES2 | --> buffer 1 and 2 len 3926 * | DES3 | 3927 * -------- 3928 * 3929 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3930 */ 3931 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3932 { 3933 struct dma_desc *desc, *first, *mss_desc = NULL; 3934 struct stmmac_priv *priv = netdev_priv(dev); 3935 int nfrags = skb_shinfo(skb)->nr_frags; 3936 u32 queue = skb_get_queue_mapping(skb); 3937 unsigned int first_entry, tx_packets; 3938 int tmp_pay_len = 0, first_tx; 3939 struct stmmac_tx_queue *tx_q; 3940 bool has_vlan, set_ic; 3941 u8 proto_hdr_len, hdr; 3942 u32 pay_len, mss; 3943 dma_addr_t des; 3944 int i; 3945 3946 tx_q = &priv->tx_queue[queue]; 3947 first_tx = tx_q->cur_tx; 3948 3949 /* Compute header lengths */ 3950 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3951 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3952 hdr = sizeof(struct udphdr); 3953 } else { 3954 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3955 hdr = tcp_hdrlen(skb); 3956 } 3957 3958 /* Desc availability based on threshold should be enough safe */ 3959 if (unlikely(stmmac_tx_avail(priv, queue) < 3960 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3961 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3962 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3963 queue)); 3964 /* This is a hard error, log it. */ 3965 netdev_err(priv->dev, 3966 "%s: Tx Ring full when queue awake\n", 3967 __func__); 3968 } 3969 return NETDEV_TX_BUSY; 3970 } 3971 3972 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3973 3974 mss = skb_shinfo(skb)->gso_size; 3975 3976 /* set new MSS value if needed */ 3977 if (mss != tx_q->mss) { 3978 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3979 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3980 else 3981 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3982 3983 stmmac_set_mss(priv, mss_desc, mss); 3984 tx_q->mss = mss; 3985 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3986 priv->dma_tx_size); 3987 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3988 } 3989 3990 if (netif_msg_tx_queued(priv)) { 3991 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3992 __func__, hdr, proto_hdr_len, pay_len, mss); 3993 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3994 skb->data_len); 3995 } 3996 3997 /* Check if VLAN can be inserted by HW */ 3998 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3999 4000 first_entry = tx_q->cur_tx; 4001 WARN_ON(tx_q->tx_skbuff[first_entry]); 4002 4003 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4004 desc = &tx_q->dma_entx[first_entry].basic; 4005 else 4006 desc = &tx_q->dma_tx[first_entry]; 4007 first = desc; 4008 4009 if (has_vlan) 4010 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4011 4012 /* first descriptor: fill Headers on Buf1 */ 4013 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 4014 DMA_TO_DEVICE); 4015 if (dma_mapping_error(priv->device, des)) 4016 goto dma_map_err; 4017 4018 tx_q->tx_skbuff_dma[first_entry].buf = des; 4019 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 4020 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4021 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4022 4023 if (priv->dma_cap.addr64 <= 32) { 4024 first->des0 = cpu_to_le32(des); 4025 4026 /* Fill start of payload in buff2 of first descriptor */ 4027 if (pay_len) 4028 first->des1 = cpu_to_le32(des + proto_hdr_len); 4029 4030 /* If needed take extra descriptors to fill the remaining payload */ 4031 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 4032 } else { 4033 stmmac_set_desc_addr(priv, first, des); 4034 tmp_pay_len = pay_len; 4035 des += proto_hdr_len; 4036 pay_len = 0; 4037 } 4038 4039 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 4040 4041 /* Prepare fragments */ 4042 for (i = 0; i < nfrags; i++) { 4043 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4044 4045 des = skb_frag_dma_map(priv->device, frag, 0, 4046 skb_frag_size(frag), 4047 DMA_TO_DEVICE); 4048 if (dma_mapping_error(priv->device, des)) 4049 goto dma_map_err; 4050 4051 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 4052 (i == nfrags - 1), queue); 4053 4054 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 4055 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 4056 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 4057 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4058 } 4059 4060 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 4061 4062 /* Only the last descriptor gets to point to the skb. */ 4063 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 4064 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf_type = STMMAC_TXBUF_T_SKB; 4065 4066 /* Manage tx mitigation */ 4067 tx_packets = (tx_q->cur_tx + 1) - first_tx; 4068 tx_q->tx_count_frames += tx_packets; 4069 4070 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4071 set_ic = true; 4072 else if (!priv->tx_coal_frames[queue]) 4073 set_ic = false; 4074 else if (tx_packets > priv->tx_coal_frames[queue]) 4075 set_ic = true; 4076 else if ((tx_q->tx_count_frames % 4077 priv->tx_coal_frames[queue]) < tx_packets) 4078 set_ic = true; 4079 else 4080 set_ic = false; 4081 4082 if (set_ic) { 4083 if (tx_q->tbs & STMMAC_TBS_AVAIL) 4084 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 4085 else 4086 desc = &tx_q->dma_tx[tx_q->cur_tx]; 4087 4088 tx_q->tx_count_frames = 0; 4089 stmmac_set_tx_ic(priv, desc); 4090 priv->xstats.tx_set_ic_bit++; 4091 } 4092 4093 /* We've used all descriptors we need for this skb, however, 4094 * advance cur_tx so that it references a fresh descriptor. 4095 * ndo_start_xmit will fill this descriptor the next time it's 4096 * called and stmmac_tx_clean may clean up to this descriptor. 4097 */ 4098 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 4099 4100 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4101 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4102 __func__); 4103 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4104 } 4105 4106 dev->stats.tx_bytes += skb->len; 4107 priv->xstats.tx_tso_frames++; 4108 priv->xstats.tx_tso_nfrags += nfrags; 4109 4110 if (priv->sarc_type) 4111 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4112 4113 skb_tx_timestamp(skb); 4114 4115 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4116 priv->hwts_tx_en)) { 4117 /* declare that device is doing timestamping */ 4118 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4119 stmmac_enable_tx_timestamp(priv, first); 4120 } 4121 4122 /* Complete the first descriptor before granting the DMA */ 4123 stmmac_prepare_tso_tx_desc(priv, first, 1, 4124 proto_hdr_len, 4125 pay_len, 4126 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 4127 hdr / 4, (skb->len - proto_hdr_len)); 4128 4129 /* If context desc is used to change MSS */ 4130 if (mss_desc) { 4131 /* Make sure that first descriptor has been completely 4132 * written, including its own bit. This is because MSS is 4133 * actually before first descriptor, so we need to make 4134 * sure that MSS's own bit is the last thing written. 4135 */ 4136 dma_wmb(); 4137 stmmac_set_tx_owner(priv, mss_desc); 4138 } 4139 4140 if (netif_msg_pktdata(priv)) { 4141 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 4142 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4143 tx_q->cur_tx, first, nfrags); 4144 pr_info(">>> frame to be transmitted: "); 4145 print_pkt(skb->data, skb_headlen(skb)); 4146 } 4147 4148 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4149 4150 stmmac_flush_tx_descriptors(priv, queue); 4151 stmmac_tx_timer_arm(priv, queue); 4152 4153 return NETDEV_TX_OK; 4154 4155 dma_map_err: 4156 dev_err(priv->device, "Tx dma map failed\n"); 4157 dev_kfree_skb(skb); 4158 priv->dev->stats.tx_dropped++; 4159 return NETDEV_TX_OK; 4160 } 4161 4162 /** 4163 * stmmac_xmit - Tx entry point of the driver 4164 * @skb : the socket buffer 4165 * @dev : device pointer 4166 * Description : this is the tx entry point of the driver. 4167 * It programs the chain or the ring and supports oversized frames 4168 * and SG feature. 4169 */ 4170 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 4171 { 4172 unsigned int first_entry, tx_packets, enh_desc; 4173 struct stmmac_priv *priv = netdev_priv(dev); 4174 unsigned int nopaged_len = skb_headlen(skb); 4175 int i, csum_insertion = 0, is_jumbo = 0; 4176 u32 queue = skb_get_queue_mapping(skb); 4177 int nfrags = skb_shinfo(skb)->nr_frags; 4178 int gso = skb_shinfo(skb)->gso_type; 4179 struct dma_edesc *tbs_desc = NULL; 4180 struct dma_desc *desc, *first; 4181 struct stmmac_tx_queue *tx_q; 4182 bool has_vlan, set_ic; 4183 int entry, first_tx; 4184 dma_addr_t des; 4185 4186 tx_q = &priv->tx_queue[queue]; 4187 first_tx = tx_q->cur_tx; 4188 4189 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 4190 stmmac_disable_eee_mode(priv); 4191 4192 /* Manage oversized TCP frames for GMAC4 device */ 4193 if (skb_is_gso(skb) && priv->tso) { 4194 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 4195 return stmmac_tso_xmit(skb, dev); 4196 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 4197 return stmmac_tso_xmit(skb, dev); 4198 } 4199 4200 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 4201 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 4202 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 4203 queue)); 4204 /* This is a hard error, log it. */ 4205 netdev_err(priv->dev, 4206 "%s: Tx Ring full when queue awake\n", 4207 __func__); 4208 } 4209 return NETDEV_TX_BUSY; 4210 } 4211 4212 /* Check if VLAN can be inserted by HW */ 4213 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 4214 4215 entry = tx_q->cur_tx; 4216 first_entry = entry; 4217 WARN_ON(tx_q->tx_skbuff[first_entry]); 4218 4219 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 4220 4221 if (likely(priv->extend_desc)) 4222 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4223 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4224 desc = &tx_q->dma_entx[entry].basic; 4225 else 4226 desc = tx_q->dma_tx + entry; 4227 4228 first = desc; 4229 4230 if (has_vlan) 4231 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 4232 4233 enh_desc = priv->plat->enh_desc; 4234 /* To program the descriptors according to the size of the frame */ 4235 if (enh_desc) 4236 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 4237 4238 if (unlikely(is_jumbo)) { 4239 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 4240 if (unlikely(entry < 0) && (entry != -EINVAL)) 4241 goto dma_map_err; 4242 } 4243 4244 for (i = 0; i < nfrags; i++) { 4245 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 4246 int len = skb_frag_size(frag); 4247 bool last_segment = (i == (nfrags - 1)); 4248 4249 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4250 WARN_ON(tx_q->tx_skbuff[entry]); 4251 4252 if (likely(priv->extend_desc)) 4253 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4254 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4255 desc = &tx_q->dma_entx[entry].basic; 4256 else 4257 desc = tx_q->dma_tx + entry; 4258 4259 des = skb_frag_dma_map(priv->device, frag, 0, len, 4260 DMA_TO_DEVICE); 4261 if (dma_mapping_error(priv->device, des)) 4262 goto dma_map_err; /* should reuse desc w/o issues */ 4263 4264 tx_q->tx_skbuff_dma[entry].buf = des; 4265 4266 stmmac_set_desc_addr(priv, desc, des); 4267 4268 tx_q->tx_skbuff_dma[entry].map_as_page = true; 4269 tx_q->tx_skbuff_dma[entry].len = len; 4270 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 4271 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4272 4273 /* Prepare the descriptor and set the own bit too */ 4274 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 4275 priv->mode, 1, last_segment, skb->len); 4276 } 4277 4278 /* Only the last descriptor gets to point to the skb. */ 4279 tx_q->tx_skbuff[entry] = skb; 4280 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_SKB; 4281 4282 /* According to the coalesce parameter the IC bit for the latest 4283 * segment is reset and the timer re-started to clean the tx status. 4284 * This approach takes care about the fragments: desc is the first 4285 * element in case of no SG. 4286 */ 4287 tx_packets = (entry + 1) - first_tx; 4288 tx_q->tx_count_frames += tx_packets; 4289 4290 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 4291 set_ic = true; 4292 else if (!priv->tx_coal_frames[queue]) 4293 set_ic = false; 4294 else if (tx_packets > priv->tx_coal_frames[queue]) 4295 set_ic = true; 4296 else if ((tx_q->tx_count_frames % 4297 priv->tx_coal_frames[queue]) < tx_packets) 4298 set_ic = true; 4299 else 4300 set_ic = false; 4301 4302 if (set_ic) { 4303 if (likely(priv->extend_desc)) 4304 desc = &tx_q->dma_etx[entry].basic; 4305 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4306 desc = &tx_q->dma_entx[entry].basic; 4307 else 4308 desc = &tx_q->dma_tx[entry]; 4309 4310 tx_q->tx_count_frames = 0; 4311 stmmac_set_tx_ic(priv, desc); 4312 priv->xstats.tx_set_ic_bit++; 4313 } 4314 4315 /* We've used all descriptors we need for this skb, however, 4316 * advance cur_tx so that it references a fresh descriptor. 4317 * ndo_start_xmit will fill this descriptor the next time it's 4318 * called and stmmac_tx_clean may clean up to this descriptor. 4319 */ 4320 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4321 tx_q->cur_tx = entry; 4322 4323 if (netif_msg_pktdata(priv)) { 4324 netdev_dbg(priv->dev, 4325 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 4326 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 4327 entry, first, nfrags); 4328 4329 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 4330 print_pkt(skb->data, skb->len); 4331 } 4332 4333 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 4334 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 4335 __func__); 4336 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 4337 } 4338 4339 dev->stats.tx_bytes += skb->len; 4340 4341 if (priv->sarc_type) 4342 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 4343 4344 skb_tx_timestamp(skb); 4345 4346 /* Ready to fill the first descriptor and set the OWN bit w/o any 4347 * problems because all the descriptors are actually ready to be 4348 * passed to the DMA engine. 4349 */ 4350 if (likely(!is_jumbo)) { 4351 bool last_segment = (nfrags == 0); 4352 4353 des = dma_map_single(priv->device, skb->data, 4354 nopaged_len, DMA_TO_DEVICE); 4355 if (dma_mapping_error(priv->device, des)) 4356 goto dma_map_err; 4357 4358 tx_q->tx_skbuff_dma[first_entry].buf = des; 4359 tx_q->tx_skbuff_dma[first_entry].buf_type = STMMAC_TXBUF_T_SKB; 4360 tx_q->tx_skbuff_dma[first_entry].map_as_page = false; 4361 4362 stmmac_set_desc_addr(priv, first, des); 4363 4364 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 4365 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 4366 4367 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 4368 priv->hwts_tx_en)) { 4369 /* declare that device is doing timestamping */ 4370 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 4371 stmmac_enable_tx_timestamp(priv, first); 4372 } 4373 4374 /* Prepare the first descriptor setting the OWN bit too */ 4375 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 4376 csum_insertion, priv->mode, 0, last_segment, 4377 skb->len); 4378 } 4379 4380 if (tx_q->tbs & STMMAC_TBS_EN) { 4381 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 4382 4383 tbs_desc = &tx_q->dma_entx[first_entry]; 4384 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 4385 } 4386 4387 stmmac_set_tx_owner(priv, first); 4388 4389 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 4390 4391 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4392 4393 stmmac_flush_tx_descriptors(priv, queue); 4394 stmmac_tx_timer_arm(priv, queue); 4395 4396 return NETDEV_TX_OK; 4397 4398 dma_map_err: 4399 netdev_err(priv->dev, "Tx DMA map failed\n"); 4400 dev_kfree_skb(skb); 4401 priv->dev->stats.tx_dropped++; 4402 return NETDEV_TX_OK; 4403 } 4404 4405 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 4406 { 4407 struct vlan_ethhdr *veth; 4408 __be16 vlan_proto; 4409 u16 vlanid; 4410 4411 veth = (struct vlan_ethhdr *)skb->data; 4412 vlan_proto = veth->h_vlan_proto; 4413 4414 if ((vlan_proto == htons(ETH_P_8021Q) && 4415 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 4416 (vlan_proto == htons(ETH_P_8021AD) && 4417 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 4418 /* pop the vlan tag */ 4419 vlanid = ntohs(veth->h_vlan_TCI); 4420 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 4421 skb_pull(skb, VLAN_HLEN); 4422 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 4423 } 4424 } 4425 4426 /** 4427 * stmmac_rx_refill - refill used skb preallocated buffers 4428 * @priv: driver private structure 4429 * @queue: RX queue index 4430 * Description : this is to reallocate the skb for the reception process 4431 * that is based on zero-copy. 4432 */ 4433 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 4434 { 4435 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4436 int dirty = stmmac_rx_dirty(priv, queue); 4437 unsigned int entry = rx_q->dirty_rx; 4438 4439 while (dirty-- > 0) { 4440 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4441 struct dma_desc *p; 4442 bool use_rx_wd; 4443 4444 if (priv->extend_desc) 4445 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4446 else 4447 p = rx_q->dma_rx + entry; 4448 4449 if (!buf->page) { 4450 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 4451 if (!buf->page) 4452 break; 4453 } 4454 4455 if (priv->sph && !buf->sec_page) { 4456 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 4457 if (!buf->sec_page) 4458 break; 4459 4460 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 4461 } 4462 4463 buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset; 4464 4465 stmmac_set_desc_addr(priv, p, buf->addr); 4466 if (priv->sph) 4467 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, true); 4468 else 4469 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr, false); 4470 stmmac_refill_desc3(priv, rx_q, p); 4471 4472 rx_q->rx_count_frames++; 4473 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4474 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4475 rx_q->rx_count_frames = 0; 4476 4477 use_rx_wd = !priv->rx_coal_frames[queue]; 4478 use_rx_wd |= rx_q->rx_count_frames > 0; 4479 if (!priv->use_riwt) 4480 use_rx_wd = false; 4481 4482 dma_wmb(); 4483 stmmac_set_rx_owner(priv, p, use_rx_wd); 4484 4485 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4486 } 4487 rx_q->dirty_rx = entry; 4488 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4489 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4490 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4491 } 4492 4493 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 4494 struct dma_desc *p, 4495 int status, unsigned int len) 4496 { 4497 unsigned int plen = 0, hlen = 0; 4498 int coe = priv->hw->rx_csum; 4499 4500 /* Not first descriptor, buffer is always zero */ 4501 if (priv->sph && len) 4502 return 0; 4503 4504 /* First descriptor, get split header length */ 4505 stmmac_get_rx_header_len(priv, p, &hlen); 4506 if (priv->sph && hlen) { 4507 priv->xstats.rx_split_hdr_pkt_n++; 4508 return hlen; 4509 } 4510 4511 /* First descriptor, not last descriptor and not split header */ 4512 if (status & rx_not_ls) 4513 return priv->dma_buf_sz; 4514 4515 plen = stmmac_get_rx_frame_len(priv, p, coe); 4516 4517 /* First descriptor and last descriptor and not split header */ 4518 return min_t(unsigned int, priv->dma_buf_sz, plen); 4519 } 4520 4521 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 4522 struct dma_desc *p, 4523 int status, unsigned int len) 4524 { 4525 int coe = priv->hw->rx_csum; 4526 unsigned int plen = 0; 4527 4528 /* Not split header, buffer is not available */ 4529 if (!priv->sph) 4530 return 0; 4531 4532 /* Not last descriptor */ 4533 if (status & rx_not_ls) 4534 return priv->dma_buf_sz; 4535 4536 plen = stmmac_get_rx_frame_len(priv, p, coe); 4537 4538 /* Last descriptor */ 4539 return plen - len; 4540 } 4541 4542 static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue, 4543 struct xdp_frame *xdpf, bool dma_map) 4544 { 4545 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4546 unsigned int entry = tx_q->cur_tx; 4547 struct dma_desc *tx_desc; 4548 dma_addr_t dma_addr; 4549 bool set_ic; 4550 4551 if (stmmac_tx_avail(priv, queue) < STMMAC_TX_THRESH(priv)) 4552 return STMMAC_XDP_CONSUMED; 4553 4554 if (likely(priv->extend_desc)) 4555 tx_desc = (struct dma_desc *)(tx_q->dma_etx + entry); 4556 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 4557 tx_desc = &tx_q->dma_entx[entry].basic; 4558 else 4559 tx_desc = tx_q->dma_tx + entry; 4560 4561 if (dma_map) { 4562 dma_addr = dma_map_single(priv->device, xdpf->data, 4563 xdpf->len, DMA_TO_DEVICE); 4564 if (dma_mapping_error(priv->device, dma_addr)) 4565 return STMMAC_XDP_CONSUMED; 4566 4567 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_NDO; 4568 } else { 4569 struct page *page = virt_to_page(xdpf->data); 4570 4571 dma_addr = page_pool_get_dma_addr(page) + sizeof(*xdpf) + 4572 xdpf->headroom; 4573 dma_sync_single_for_device(priv->device, dma_addr, 4574 xdpf->len, DMA_BIDIRECTIONAL); 4575 4576 tx_q->tx_skbuff_dma[entry].buf_type = STMMAC_TXBUF_T_XDP_TX; 4577 } 4578 4579 tx_q->tx_skbuff_dma[entry].buf = dma_addr; 4580 tx_q->tx_skbuff_dma[entry].map_as_page = false; 4581 tx_q->tx_skbuff_dma[entry].len = xdpf->len; 4582 tx_q->tx_skbuff_dma[entry].last_segment = true; 4583 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 4584 4585 tx_q->xdpf[entry] = xdpf; 4586 4587 stmmac_set_desc_addr(priv, tx_desc, dma_addr); 4588 4589 stmmac_prepare_tx_desc(priv, tx_desc, 1, xdpf->len, 4590 true, priv->mode, true, true, 4591 xdpf->len); 4592 4593 tx_q->tx_count_frames++; 4594 4595 if (tx_q->tx_count_frames % priv->tx_coal_frames[queue] == 0) 4596 set_ic = true; 4597 else 4598 set_ic = false; 4599 4600 if (set_ic) { 4601 tx_q->tx_count_frames = 0; 4602 stmmac_set_tx_ic(priv, tx_desc); 4603 priv->xstats.tx_set_ic_bit++; 4604 } 4605 4606 stmmac_enable_dma_transmission(priv, priv->ioaddr); 4607 4608 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 4609 tx_q->cur_tx = entry; 4610 4611 return STMMAC_XDP_TX; 4612 } 4613 4614 static int stmmac_xdp_get_tx_queue(struct stmmac_priv *priv, 4615 int cpu) 4616 { 4617 int index = cpu; 4618 4619 if (unlikely(index < 0)) 4620 index = 0; 4621 4622 while (index >= priv->plat->tx_queues_to_use) 4623 index -= priv->plat->tx_queues_to_use; 4624 4625 return index; 4626 } 4627 4628 static int stmmac_xdp_xmit_back(struct stmmac_priv *priv, 4629 struct xdp_buff *xdp) 4630 { 4631 struct xdp_frame *xdpf = xdp_convert_buff_to_frame(xdp); 4632 int cpu = smp_processor_id(); 4633 struct netdev_queue *nq; 4634 int queue; 4635 int res; 4636 4637 if (unlikely(!xdpf)) 4638 return STMMAC_XDP_CONSUMED; 4639 4640 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4641 nq = netdev_get_tx_queue(priv->dev, queue); 4642 4643 __netif_tx_lock(nq, cpu); 4644 /* Avoids TX time-out as we are sharing with slow path */ 4645 nq->trans_start = jiffies; 4646 4647 res = stmmac_xdp_xmit_xdpf(priv, queue, xdpf, false); 4648 if (res == STMMAC_XDP_TX) 4649 stmmac_flush_tx_descriptors(priv, queue); 4650 4651 __netif_tx_unlock(nq); 4652 4653 return res; 4654 } 4655 4656 /* This function assumes rcu_read_lock() is held by the caller. */ 4657 static int __stmmac_xdp_run_prog(struct stmmac_priv *priv, 4658 struct bpf_prog *prog, 4659 struct xdp_buff *xdp) 4660 { 4661 u32 act; 4662 int res; 4663 4664 act = bpf_prog_run_xdp(prog, xdp); 4665 switch (act) { 4666 case XDP_PASS: 4667 res = STMMAC_XDP_PASS; 4668 break; 4669 case XDP_TX: 4670 res = stmmac_xdp_xmit_back(priv, xdp); 4671 break; 4672 case XDP_REDIRECT: 4673 if (xdp_do_redirect(priv->dev, xdp, prog) < 0) 4674 res = STMMAC_XDP_CONSUMED; 4675 else 4676 res = STMMAC_XDP_REDIRECT; 4677 break; 4678 default: 4679 bpf_warn_invalid_xdp_action(act); 4680 fallthrough; 4681 case XDP_ABORTED: 4682 trace_xdp_exception(priv->dev, prog, act); 4683 fallthrough; 4684 case XDP_DROP: 4685 res = STMMAC_XDP_CONSUMED; 4686 break; 4687 } 4688 4689 return res; 4690 } 4691 4692 static struct sk_buff *stmmac_xdp_run_prog(struct stmmac_priv *priv, 4693 struct xdp_buff *xdp) 4694 { 4695 struct bpf_prog *prog; 4696 int res; 4697 4698 rcu_read_lock(); 4699 4700 prog = READ_ONCE(priv->xdp_prog); 4701 if (!prog) { 4702 res = STMMAC_XDP_PASS; 4703 goto unlock; 4704 } 4705 4706 res = __stmmac_xdp_run_prog(priv, prog, xdp); 4707 unlock: 4708 rcu_read_unlock(); 4709 return ERR_PTR(-res); 4710 } 4711 4712 static void stmmac_finalize_xdp_rx(struct stmmac_priv *priv, 4713 int xdp_status) 4714 { 4715 int cpu = smp_processor_id(); 4716 int queue; 4717 4718 queue = stmmac_xdp_get_tx_queue(priv, cpu); 4719 4720 if (xdp_status & STMMAC_XDP_TX) 4721 stmmac_tx_timer_arm(priv, queue); 4722 4723 if (xdp_status & STMMAC_XDP_REDIRECT) 4724 xdp_do_flush(); 4725 } 4726 4727 static struct sk_buff *stmmac_construct_skb_zc(struct stmmac_channel *ch, 4728 struct xdp_buff *xdp) 4729 { 4730 unsigned int metasize = xdp->data - xdp->data_meta; 4731 unsigned int datasize = xdp->data_end - xdp->data; 4732 struct sk_buff *skb; 4733 4734 skb = __napi_alloc_skb(&ch->rxtx_napi, 4735 xdp->data_end - xdp->data_hard_start, 4736 GFP_ATOMIC | __GFP_NOWARN); 4737 if (unlikely(!skb)) 4738 return NULL; 4739 4740 skb_reserve(skb, xdp->data - xdp->data_hard_start); 4741 memcpy(__skb_put(skb, datasize), xdp->data, datasize); 4742 if (metasize) 4743 skb_metadata_set(skb, metasize); 4744 4745 return skb; 4746 } 4747 4748 static void stmmac_dispatch_skb_zc(struct stmmac_priv *priv, u32 queue, 4749 struct dma_desc *p, struct dma_desc *np, 4750 struct xdp_buff *xdp) 4751 { 4752 struct stmmac_channel *ch = &priv->channel[queue]; 4753 unsigned int len = xdp->data_end - xdp->data; 4754 enum pkt_hash_types hash_type; 4755 int coe = priv->hw->rx_csum; 4756 struct sk_buff *skb; 4757 u32 hash; 4758 4759 skb = stmmac_construct_skb_zc(ch, xdp); 4760 if (!skb) { 4761 priv->dev->stats.rx_dropped++; 4762 return; 4763 } 4764 4765 stmmac_get_rx_hwtstamp(priv, p, np, skb); 4766 stmmac_rx_vlan(priv->dev, skb); 4767 skb->protocol = eth_type_trans(skb, priv->dev); 4768 4769 if (unlikely(!coe)) 4770 skb_checksum_none_assert(skb); 4771 else 4772 skb->ip_summed = CHECKSUM_UNNECESSARY; 4773 4774 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 4775 skb_set_hash(skb, hash, hash_type); 4776 4777 skb_record_rx_queue(skb, queue); 4778 napi_gro_receive(&ch->rxtx_napi, skb); 4779 4780 priv->dev->stats.rx_packets++; 4781 priv->dev->stats.rx_bytes += len; 4782 } 4783 4784 static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget) 4785 { 4786 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4787 unsigned int entry = rx_q->dirty_rx; 4788 struct dma_desc *rx_desc = NULL; 4789 bool ret = true; 4790 4791 budget = min(budget, stmmac_rx_dirty(priv, queue)); 4792 4793 while (budget-- > 0 && entry != rx_q->cur_rx) { 4794 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 4795 dma_addr_t dma_addr; 4796 bool use_rx_wd; 4797 4798 if (!buf->xdp) { 4799 buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); 4800 if (!buf->xdp) { 4801 ret = false; 4802 break; 4803 } 4804 } 4805 4806 if (priv->extend_desc) 4807 rx_desc = (struct dma_desc *)(rx_q->dma_erx + entry); 4808 else 4809 rx_desc = rx_q->dma_rx + entry; 4810 4811 dma_addr = xsk_buff_xdp_get_dma(buf->xdp); 4812 stmmac_set_desc_addr(priv, rx_desc, dma_addr); 4813 stmmac_set_desc_sec_addr(priv, rx_desc, 0, false); 4814 stmmac_refill_desc3(priv, rx_q, rx_desc); 4815 4816 rx_q->rx_count_frames++; 4817 rx_q->rx_count_frames += priv->rx_coal_frames[queue]; 4818 if (rx_q->rx_count_frames > priv->rx_coal_frames[queue]) 4819 rx_q->rx_count_frames = 0; 4820 4821 use_rx_wd = !priv->rx_coal_frames[queue]; 4822 use_rx_wd |= rx_q->rx_count_frames > 0; 4823 if (!priv->use_riwt) 4824 use_rx_wd = false; 4825 4826 dma_wmb(); 4827 stmmac_set_rx_owner(priv, rx_desc, use_rx_wd); 4828 4829 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 4830 } 4831 4832 if (rx_desc) { 4833 rx_q->dirty_rx = entry; 4834 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 4835 (rx_q->dirty_rx * sizeof(struct dma_desc)); 4836 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 4837 } 4838 4839 return ret; 4840 } 4841 4842 static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue) 4843 { 4844 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4845 unsigned int count = 0, error = 0, len = 0; 4846 int dirty = stmmac_rx_dirty(priv, queue); 4847 unsigned int next_entry = rx_q->cur_rx; 4848 unsigned int desc_size; 4849 struct bpf_prog *prog; 4850 bool failure = false; 4851 int xdp_status = 0; 4852 int status = 0; 4853 4854 if (netif_msg_rx_status(priv)) { 4855 void *rx_head; 4856 4857 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 4858 if (priv->extend_desc) { 4859 rx_head = (void *)rx_q->dma_erx; 4860 desc_size = sizeof(struct dma_extended_desc); 4861 } else { 4862 rx_head = (void *)rx_q->dma_rx; 4863 desc_size = sizeof(struct dma_desc); 4864 } 4865 4866 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 4867 rx_q->dma_rx_phy, desc_size); 4868 } 4869 while (count < limit) { 4870 struct stmmac_rx_buffer *buf; 4871 unsigned int buf1_len = 0; 4872 struct dma_desc *np, *p; 4873 int entry; 4874 int res; 4875 4876 if (!count && rx_q->state_saved) { 4877 error = rx_q->state.error; 4878 len = rx_q->state.len; 4879 } else { 4880 rx_q->state_saved = false; 4881 error = 0; 4882 len = 0; 4883 } 4884 4885 if (count >= limit) 4886 break; 4887 4888 read_again: 4889 buf1_len = 0; 4890 entry = next_entry; 4891 buf = &rx_q->buf_pool[entry]; 4892 4893 if (dirty >= STMMAC_RX_FILL_BATCH) { 4894 failure = failure || 4895 !stmmac_rx_refill_zc(priv, queue, dirty); 4896 dirty = 0; 4897 } 4898 4899 if (priv->extend_desc) 4900 p = (struct dma_desc *)(rx_q->dma_erx + entry); 4901 else 4902 p = rx_q->dma_rx + entry; 4903 4904 /* read the status of the incoming frame */ 4905 status = stmmac_rx_status(priv, &priv->dev->stats, 4906 &priv->xstats, p); 4907 /* check if managed by the DMA otherwise go ahead */ 4908 if (unlikely(status & dma_own)) 4909 break; 4910 4911 /* Prefetch the next RX descriptor */ 4912 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 4913 priv->dma_rx_size); 4914 next_entry = rx_q->cur_rx; 4915 4916 if (priv->extend_desc) 4917 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 4918 else 4919 np = rx_q->dma_rx + next_entry; 4920 4921 prefetch(np); 4922 4923 if (priv->extend_desc) 4924 stmmac_rx_extended_status(priv, &priv->dev->stats, 4925 &priv->xstats, 4926 rx_q->dma_erx + entry); 4927 if (unlikely(status == discard_frame)) { 4928 xsk_buff_free(buf->xdp); 4929 buf->xdp = NULL; 4930 dirty++; 4931 error = 1; 4932 if (!priv->hwts_rx_en) 4933 priv->dev->stats.rx_errors++; 4934 } 4935 4936 if (unlikely(error && (status & rx_not_ls))) 4937 goto read_again; 4938 if (unlikely(error)) { 4939 count++; 4940 continue; 4941 } 4942 4943 /* Ensure a valid XSK buffer before proceed */ 4944 if (!buf->xdp) 4945 break; 4946 4947 /* XSK pool expects RX frame 1:1 mapped to XSK buffer */ 4948 if (likely(status & rx_not_ls)) { 4949 xsk_buff_free(buf->xdp); 4950 buf->xdp = NULL; 4951 dirty++; 4952 count++; 4953 goto read_again; 4954 } 4955 4956 /* XDP ZC Frame only support primary buffers for now */ 4957 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 4958 len += buf1_len; 4959 4960 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 4961 * Type frames (LLC/LLC-SNAP) 4962 * 4963 * llc_snap is never checked in GMAC >= 4, so this ACS 4964 * feature is always disabled and packets need to be 4965 * stripped manually. 4966 */ 4967 if (likely(!(status & rx_not_ls)) && 4968 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 4969 unlikely(status != llc_snap))) { 4970 buf1_len -= ETH_FCS_LEN; 4971 len -= ETH_FCS_LEN; 4972 } 4973 4974 /* RX buffer is good and fit into a XSK pool buffer */ 4975 buf->xdp->data_end = buf->xdp->data + buf1_len; 4976 xsk_buff_dma_sync_for_cpu(buf->xdp, rx_q->xsk_pool); 4977 4978 rcu_read_lock(); 4979 prog = READ_ONCE(priv->xdp_prog); 4980 res = __stmmac_xdp_run_prog(priv, prog, buf->xdp); 4981 rcu_read_unlock(); 4982 4983 switch (res) { 4984 case STMMAC_XDP_PASS: 4985 stmmac_dispatch_skb_zc(priv, queue, p, np, buf->xdp); 4986 xsk_buff_free(buf->xdp); 4987 break; 4988 case STMMAC_XDP_CONSUMED: 4989 xsk_buff_free(buf->xdp); 4990 priv->dev->stats.rx_dropped++; 4991 break; 4992 case STMMAC_XDP_TX: 4993 case STMMAC_XDP_REDIRECT: 4994 xdp_status |= res; 4995 break; 4996 } 4997 4998 buf->xdp = NULL; 4999 dirty++; 5000 count++; 5001 } 5002 5003 if (status & rx_not_ls) { 5004 rx_q->state_saved = true; 5005 rx_q->state.error = error; 5006 rx_q->state.len = len; 5007 } 5008 5009 stmmac_finalize_xdp_rx(priv, xdp_status); 5010 5011 if (xsk_uses_need_wakeup(rx_q->xsk_pool)) { 5012 if (failure || stmmac_rx_dirty(priv, queue) > 0) 5013 xsk_set_rx_need_wakeup(rx_q->xsk_pool); 5014 else 5015 xsk_clear_rx_need_wakeup(rx_q->xsk_pool); 5016 5017 return (int)count; 5018 } 5019 5020 return failure ? limit : (int)count; 5021 } 5022 5023 /** 5024 * stmmac_rx - manage the receive process 5025 * @priv: driver private structure 5026 * @limit: napi bugget 5027 * @queue: RX queue index. 5028 * Description : this the function called by the napi poll method. 5029 * It gets all the frames inside the ring. 5030 */ 5031 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 5032 { 5033 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5034 struct stmmac_channel *ch = &priv->channel[queue]; 5035 unsigned int count = 0, error = 0, len = 0; 5036 int status = 0, coe = priv->hw->rx_csum; 5037 unsigned int next_entry = rx_q->cur_rx; 5038 enum dma_data_direction dma_dir; 5039 unsigned int desc_size; 5040 struct sk_buff *skb = NULL; 5041 struct xdp_buff xdp; 5042 int xdp_status = 0; 5043 int buf_sz; 5044 5045 dma_dir = page_pool_get_dma_dir(rx_q->page_pool); 5046 buf_sz = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 5047 5048 if (netif_msg_rx_status(priv)) { 5049 void *rx_head; 5050 5051 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 5052 if (priv->extend_desc) { 5053 rx_head = (void *)rx_q->dma_erx; 5054 desc_size = sizeof(struct dma_extended_desc); 5055 } else { 5056 rx_head = (void *)rx_q->dma_rx; 5057 desc_size = sizeof(struct dma_desc); 5058 } 5059 5060 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true, 5061 rx_q->dma_rx_phy, desc_size); 5062 } 5063 while (count < limit) { 5064 unsigned int buf1_len = 0, buf2_len = 0; 5065 enum pkt_hash_types hash_type; 5066 struct stmmac_rx_buffer *buf; 5067 struct dma_desc *np, *p; 5068 int entry; 5069 u32 hash; 5070 5071 if (!count && rx_q->state_saved) { 5072 skb = rx_q->state.skb; 5073 error = rx_q->state.error; 5074 len = rx_q->state.len; 5075 } else { 5076 rx_q->state_saved = false; 5077 skb = NULL; 5078 error = 0; 5079 len = 0; 5080 } 5081 5082 if (count >= limit) 5083 break; 5084 5085 read_again: 5086 buf1_len = 0; 5087 buf2_len = 0; 5088 entry = next_entry; 5089 buf = &rx_q->buf_pool[entry]; 5090 5091 if (priv->extend_desc) 5092 p = (struct dma_desc *)(rx_q->dma_erx + entry); 5093 else 5094 p = rx_q->dma_rx + entry; 5095 5096 /* read the status of the incoming frame */ 5097 status = stmmac_rx_status(priv, &priv->dev->stats, 5098 &priv->xstats, p); 5099 /* check if managed by the DMA otherwise go ahead */ 5100 if (unlikely(status & dma_own)) 5101 break; 5102 5103 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 5104 priv->dma_rx_size); 5105 next_entry = rx_q->cur_rx; 5106 5107 if (priv->extend_desc) 5108 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 5109 else 5110 np = rx_q->dma_rx + next_entry; 5111 5112 prefetch(np); 5113 5114 if (priv->extend_desc) 5115 stmmac_rx_extended_status(priv, &priv->dev->stats, 5116 &priv->xstats, rx_q->dma_erx + entry); 5117 if (unlikely(status == discard_frame)) { 5118 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5119 buf->page = NULL; 5120 error = 1; 5121 if (!priv->hwts_rx_en) 5122 priv->dev->stats.rx_errors++; 5123 } 5124 5125 if (unlikely(error && (status & rx_not_ls))) 5126 goto read_again; 5127 if (unlikely(error)) { 5128 dev_kfree_skb(skb); 5129 skb = NULL; 5130 count++; 5131 continue; 5132 } 5133 5134 /* Buffer is good. Go on. */ 5135 5136 prefetch(page_address(buf->page)); 5137 if (buf->sec_page) 5138 prefetch(page_address(buf->sec_page)); 5139 5140 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 5141 len += buf1_len; 5142 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 5143 len += buf2_len; 5144 5145 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 5146 * Type frames (LLC/LLC-SNAP) 5147 * 5148 * llc_snap is never checked in GMAC >= 4, so this ACS 5149 * feature is always disabled and packets need to be 5150 * stripped manually. 5151 */ 5152 if (likely(!(status & rx_not_ls)) && 5153 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 5154 unlikely(status != llc_snap))) { 5155 if (buf2_len) 5156 buf2_len -= ETH_FCS_LEN; 5157 else 5158 buf1_len -= ETH_FCS_LEN; 5159 5160 len -= ETH_FCS_LEN; 5161 } 5162 5163 if (!skb) { 5164 unsigned int pre_len, sync_len; 5165 5166 dma_sync_single_for_cpu(priv->device, buf->addr, 5167 buf1_len, dma_dir); 5168 5169 xdp_init_buff(&xdp, buf_sz, &rx_q->xdp_rxq); 5170 xdp_prepare_buff(&xdp, page_address(buf->page), 5171 buf->page_offset, buf1_len, false); 5172 5173 pre_len = xdp.data_end - xdp.data_hard_start - 5174 buf->page_offset; 5175 skb = stmmac_xdp_run_prog(priv, &xdp); 5176 /* Due xdp_adjust_tail: DMA sync for_device 5177 * cover max len CPU touch 5178 */ 5179 sync_len = xdp.data_end - xdp.data_hard_start - 5180 buf->page_offset; 5181 sync_len = max(sync_len, pre_len); 5182 5183 /* For Not XDP_PASS verdict */ 5184 if (IS_ERR(skb)) { 5185 unsigned int xdp_res = -PTR_ERR(skb); 5186 5187 if (xdp_res & STMMAC_XDP_CONSUMED) { 5188 page_pool_put_page(rx_q->page_pool, 5189 virt_to_head_page(xdp.data), 5190 sync_len, true); 5191 buf->page = NULL; 5192 priv->dev->stats.rx_dropped++; 5193 5194 /* Clear skb as it was set as 5195 * status by XDP program. 5196 */ 5197 skb = NULL; 5198 5199 if (unlikely((status & rx_not_ls))) 5200 goto read_again; 5201 5202 count++; 5203 continue; 5204 } else if (xdp_res & (STMMAC_XDP_TX | 5205 STMMAC_XDP_REDIRECT)) { 5206 xdp_status |= xdp_res; 5207 buf->page = NULL; 5208 skb = NULL; 5209 count++; 5210 continue; 5211 } 5212 } 5213 } 5214 5215 if (!skb) { 5216 /* XDP program may expand or reduce tail */ 5217 buf1_len = xdp.data_end - xdp.data; 5218 5219 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 5220 if (!skb) { 5221 priv->dev->stats.rx_dropped++; 5222 count++; 5223 goto drain_data; 5224 } 5225 5226 /* XDP program may adjust header */ 5227 skb_copy_to_linear_data(skb, xdp.data, buf1_len); 5228 skb_put(skb, buf1_len); 5229 5230 /* Data payload copied into SKB, page ready for recycle */ 5231 page_pool_recycle_direct(rx_q->page_pool, buf->page); 5232 buf->page = NULL; 5233 } else if (buf1_len) { 5234 dma_sync_single_for_cpu(priv->device, buf->addr, 5235 buf1_len, dma_dir); 5236 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5237 buf->page, buf->page_offset, buf1_len, 5238 priv->dma_buf_sz); 5239 5240 /* Data payload appended into SKB */ 5241 page_pool_release_page(rx_q->page_pool, buf->page); 5242 buf->page = NULL; 5243 } 5244 5245 if (buf2_len) { 5246 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 5247 buf2_len, dma_dir); 5248 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 5249 buf->sec_page, 0, buf2_len, 5250 priv->dma_buf_sz); 5251 5252 /* Data payload appended into SKB */ 5253 page_pool_release_page(rx_q->page_pool, buf->sec_page); 5254 buf->sec_page = NULL; 5255 } 5256 5257 drain_data: 5258 if (likely(status & rx_not_ls)) 5259 goto read_again; 5260 if (!skb) 5261 continue; 5262 5263 /* Got entire packet into SKB. Finish it. */ 5264 5265 stmmac_get_rx_hwtstamp(priv, p, np, skb); 5266 stmmac_rx_vlan(priv->dev, skb); 5267 skb->protocol = eth_type_trans(skb, priv->dev); 5268 5269 if (unlikely(!coe)) 5270 skb_checksum_none_assert(skb); 5271 else 5272 skb->ip_summed = CHECKSUM_UNNECESSARY; 5273 5274 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 5275 skb_set_hash(skb, hash, hash_type); 5276 5277 skb_record_rx_queue(skb, queue); 5278 napi_gro_receive(&ch->rx_napi, skb); 5279 skb = NULL; 5280 5281 priv->dev->stats.rx_packets++; 5282 priv->dev->stats.rx_bytes += len; 5283 count++; 5284 } 5285 5286 if (status & rx_not_ls || skb) { 5287 rx_q->state_saved = true; 5288 rx_q->state.skb = skb; 5289 rx_q->state.error = error; 5290 rx_q->state.len = len; 5291 } 5292 5293 stmmac_finalize_xdp_rx(priv, xdp_status); 5294 5295 stmmac_rx_refill(priv, queue); 5296 5297 priv->xstats.rx_pkt_n += count; 5298 5299 return count; 5300 } 5301 5302 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 5303 { 5304 struct stmmac_channel *ch = 5305 container_of(napi, struct stmmac_channel, rx_napi); 5306 struct stmmac_priv *priv = ch->priv_data; 5307 u32 chan = ch->index; 5308 int work_done; 5309 5310 priv->xstats.napi_poll++; 5311 5312 work_done = stmmac_rx(priv, budget, chan); 5313 if (work_done < budget && napi_complete_done(napi, work_done)) { 5314 unsigned long flags; 5315 5316 spin_lock_irqsave(&ch->lock, flags); 5317 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 5318 spin_unlock_irqrestore(&ch->lock, flags); 5319 } 5320 5321 return work_done; 5322 } 5323 5324 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 5325 { 5326 struct stmmac_channel *ch = 5327 container_of(napi, struct stmmac_channel, tx_napi); 5328 struct stmmac_priv *priv = ch->priv_data; 5329 u32 chan = ch->index; 5330 int work_done; 5331 5332 priv->xstats.napi_poll++; 5333 5334 work_done = stmmac_tx_clean(priv, budget, chan); 5335 work_done = min(work_done, budget); 5336 5337 if (work_done < budget && napi_complete_done(napi, work_done)) { 5338 unsigned long flags; 5339 5340 spin_lock_irqsave(&ch->lock, flags); 5341 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 5342 spin_unlock_irqrestore(&ch->lock, flags); 5343 } 5344 5345 return work_done; 5346 } 5347 5348 static int stmmac_napi_poll_rxtx(struct napi_struct *napi, int budget) 5349 { 5350 struct stmmac_channel *ch = 5351 container_of(napi, struct stmmac_channel, rxtx_napi); 5352 struct stmmac_priv *priv = ch->priv_data; 5353 int rx_done, tx_done; 5354 u32 chan = ch->index; 5355 5356 priv->xstats.napi_poll++; 5357 5358 tx_done = stmmac_tx_clean(priv, budget, chan); 5359 tx_done = min(tx_done, budget); 5360 5361 rx_done = stmmac_rx_zc(priv, budget, chan); 5362 5363 /* If either TX or RX work is not complete, return budget 5364 * and keep pooling 5365 */ 5366 if (tx_done >= budget || rx_done >= budget) 5367 return budget; 5368 5369 /* all work done, exit the polling mode */ 5370 if (napi_complete_done(napi, rx_done)) { 5371 unsigned long flags; 5372 5373 spin_lock_irqsave(&ch->lock, flags); 5374 /* Both RX and TX work done are compelte, 5375 * so enable both RX & TX IRQs. 5376 */ 5377 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 1); 5378 spin_unlock_irqrestore(&ch->lock, flags); 5379 } 5380 5381 return min(rx_done, budget - 1); 5382 } 5383 5384 /** 5385 * stmmac_tx_timeout 5386 * @dev : Pointer to net device structure 5387 * @txqueue: the index of the hanging transmit queue 5388 * Description: this function is called when a packet transmission fails to 5389 * complete within a reasonable time. The driver will mark the error in the 5390 * netdev structure and arrange for the device to be reset to a sane state 5391 * in order to transmit a new packet. 5392 */ 5393 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 5394 { 5395 struct stmmac_priv *priv = netdev_priv(dev); 5396 5397 stmmac_global_err(priv); 5398 } 5399 5400 /** 5401 * stmmac_set_rx_mode - entry point for multicast addressing 5402 * @dev : pointer to the device structure 5403 * Description: 5404 * This function is a driver entry point which gets called by the kernel 5405 * whenever multicast addresses must be enabled/disabled. 5406 * Return value: 5407 * void. 5408 */ 5409 static void stmmac_set_rx_mode(struct net_device *dev) 5410 { 5411 struct stmmac_priv *priv = netdev_priv(dev); 5412 5413 stmmac_set_filter(priv, priv->hw, dev); 5414 } 5415 5416 /** 5417 * stmmac_change_mtu - entry point to change MTU size for the device. 5418 * @dev : device pointer. 5419 * @new_mtu : the new MTU size for the device. 5420 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 5421 * to drive packet transmission. Ethernet has an MTU of 1500 octets 5422 * (ETH_DATA_LEN). This value can be changed with ifconfig. 5423 * Return value: 5424 * 0 on success and an appropriate (-)ve integer as defined in errno.h 5425 * file on failure. 5426 */ 5427 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 5428 { 5429 struct stmmac_priv *priv = netdev_priv(dev); 5430 int txfifosz = priv->plat->tx_fifo_size; 5431 const int mtu = new_mtu; 5432 5433 if (txfifosz == 0) 5434 txfifosz = priv->dma_cap.tx_fifo_size; 5435 5436 txfifosz /= priv->plat->tx_queues_to_use; 5437 5438 if (netif_running(dev)) { 5439 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 5440 return -EBUSY; 5441 } 5442 5443 if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) { 5444 netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n"); 5445 return -EINVAL; 5446 } 5447 5448 new_mtu = STMMAC_ALIGN(new_mtu); 5449 5450 /* If condition true, FIFO is too small or MTU too large */ 5451 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 5452 return -EINVAL; 5453 5454 dev->mtu = mtu; 5455 5456 netdev_update_features(dev); 5457 5458 return 0; 5459 } 5460 5461 static netdev_features_t stmmac_fix_features(struct net_device *dev, 5462 netdev_features_t features) 5463 { 5464 struct stmmac_priv *priv = netdev_priv(dev); 5465 5466 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 5467 features &= ~NETIF_F_RXCSUM; 5468 5469 if (!priv->plat->tx_coe) 5470 features &= ~NETIF_F_CSUM_MASK; 5471 5472 /* Some GMAC devices have a bugged Jumbo frame support that 5473 * needs to have the Tx COE disabled for oversized frames 5474 * (due to limited buffer sizes). In this case we disable 5475 * the TX csum insertion in the TDES and not use SF. 5476 */ 5477 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 5478 features &= ~NETIF_F_CSUM_MASK; 5479 5480 /* Disable tso if asked by ethtool */ 5481 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 5482 if (features & NETIF_F_TSO) 5483 priv->tso = true; 5484 else 5485 priv->tso = false; 5486 } 5487 5488 return features; 5489 } 5490 5491 static int stmmac_set_features(struct net_device *netdev, 5492 netdev_features_t features) 5493 { 5494 struct stmmac_priv *priv = netdev_priv(netdev); 5495 bool sph_en; 5496 u32 chan; 5497 5498 /* Keep the COE Type in case of csum is supporting */ 5499 if (features & NETIF_F_RXCSUM) 5500 priv->hw->rx_csum = priv->plat->rx_coe; 5501 else 5502 priv->hw->rx_csum = 0; 5503 /* No check needed because rx_coe has been set before and it will be 5504 * fixed in case of issue. 5505 */ 5506 stmmac_rx_ipc(priv, priv->hw); 5507 5508 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 5509 5510 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 5511 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 5512 5513 return 0; 5514 } 5515 5516 static void stmmac_fpe_event_status(struct stmmac_priv *priv, int status) 5517 { 5518 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 5519 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 5520 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 5521 bool *hs_enable = &fpe_cfg->hs_enable; 5522 5523 if (status == FPE_EVENT_UNKNOWN || !*hs_enable) 5524 return; 5525 5526 /* If LP has sent verify mPacket, LP is FPE capable */ 5527 if ((status & FPE_EVENT_RVER) == FPE_EVENT_RVER) { 5528 if (*lp_state < FPE_STATE_CAPABLE) 5529 *lp_state = FPE_STATE_CAPABLE; 5530 5531 /* If user has requested FPE enable, quickly response */ 5532 if (*hs_enable) 5533 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 5534 MPACKET_RESPONSE); 5535 } 5536 5537 /* If Local has sent verify mPacket, Local is FPE capable */ 5538 if ((status & FPE_EVENT_TVER) == FPE_EVENT_TVER) { 5539 if (*lo_state < FPE_STATE_CAPABLE) 5540 *lo_state = FPE_STATE_CAPABLE; 5541 } 5542 5543 /* If LP has sent response mPacket, LP is entering FPE ON */ 5544 if ((status & FPE_EVENT_RRSP) == FPE_EVENT_RRSP) 5545 *lp_state = FPE_STATE_ENTERING_ON; 5546 5547 /* If Local has sent response mPacket, Local is entering FPE ON */ 5548 if ((status & FPE_EVENT_TRSP) == FPE_EVENT_TRSP) 5549 *lo_state = FPE_STATE_ENTERING_ON; 5550 5551 if (!test_bit(__FPE_REMOVING, &priv->fpe_task_state) && 5552 !test_and_set_bit(__FPE_TASK_SCHED, &priv->fpe_task_state) && 5553 priv->fpe_wq) { 5554 queue_work(priv->fpe_wq, &priv->fpe_task); 5555 } 5556 } 5557 5558 static void stmmac_common_interrupt(struct stmmac_priv *priv) 5559 { 5560 u32 rx_cnt = priv->plat->rx_queues_to_use; 5561 u32 tx_cnt = priv->plat->tx_queues_to_use; 5562 u32 queues_count; 5563 u32 queue; 5564 bool xmac; 5565 5566 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 5567 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 5568 5569 if (priv->irq_wake) 5570 pm_wakeup_event(priv->device, 0); 5571 5572 if (priv->dma_cap.estsel) 5573 stmmac_est_irq_status(priv, priv->ioaddr, priv->dev, 5574 &priv->xstats, tx_cnt); 5575 5576 if (priv->dma_cap.fpesel) { 5577 int status = stmmac_fpe_irq_status(priv, priv->ioaddr, 5578 priv->dev); 5579 5580 stmmac_fpe_event_status(priv, status); 5581 } 5582 5583 /* To handle GMAC own interrupts */ 5584 if ((priv->plat->has_gmac) || xmac) { 5585 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 5586 5587 if (unlikely(status)) { 5588 /* For LPI we need to save the tx status */ 5589 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 5590 priv->tx_path_in_lpi_mode = true; 5591 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 5592 priv->tx_path_in_lpi_mode = false; 5593 } 5594 5595 for (queue = 0; queue < queues_count; queue++) { 5596 status = stmmac_host_mtl_irq_status(priv, priv->hw, 5597 queue); 5598 } 5599 5600 /* PCS link status */ 5601 if (priv->hw->pcs) { 5602 if (priv->xstats.pcs_link) 5603 netif_carrier_on(priv->dev); 5604 else 5605 netif_carrier_off(priv->dev); 5606 } 5607 5608 stmmac_timestamp_interrupt(priv, priv); 5609 } 5610 } 5611 5612 /** 5613 * stmmac_interrupt - main ISR 5614 * @irq: interrupt number. 5615 * @dev_id: to pass the net device pointer. 5616 * Description: this is the main driver interrupt service routine. 5617 * It can call: 5618 * o DMA service routine (to manage incoming frame reception and transmission 5619 * status) 5620 * o Core interrupts to manage: remote wake-up, management counter, LPI 5621 * interrupts. 5622 */ 5623 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 5624 { 5625 struct net_device *dev = (struct net_device *)dev_id; 5626 struct stmmac_priv *priv = netdev_priv(dev); 5627 5628 /* Check if adapter is up */ 5629 if (test_bit(STMMAC_DOWN, &priv->state)) 5630 return IRQ_HANDLED; 5631 5632 /* Check if a fatal error happened */ 5633 if (stmmac_safety_feat_interrupt(priv)) 5634 return IRQ_HANDLED; 5635 5636 /* To handle Common interrupts */ 5637 stmmac_common_interrupt(priv); 5638 5639 /* To handle DMA interrupts */ 5640 stmmac_dma_interrupt(priv); 5641 5642 return IRQ_HANDLED; 5643 } 5644 5645 static irqreturn_t stmmac_mac_interrupt(int irq, void *dev_id) 5646 { 5647 struct net_device *dev = (struct net_device *)dev_id; 5648 struct stmmac_priv *priv = netdev_priv(dev); 5649 5650 if (unlikely(!dev)) { 5651 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5652 return IRQ_NONE; 5653 } 5654 5655 /* Check if adapter is up */ 5656 if (test_bit(STMMAC_DOWN, &priv->state)) 5657 return IRQ_HANDLED; 5658 5659 /* To handle Common interrupts */ 5660 stmmac_common_interrupt(priv); 5661 5662 return IRQ_HANDLED; 5663 } 5664 5665 static irqreturn_t stmmac_safety_interrupt(int irq, void *dev_id) 5666 { 5667 struct net_device *dev = (struct net_device *)dev_id; 5668 struct stmmac_priv *priv = netdev_priv(dev); 5669 5670 if (unlikely(!dev)) { 5671 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5672 return IRQ_NONE; 5673 } 5674 5675 /* Check if adapter is up */ 5676 if (test_bit(STMMAC_DOWN, &priv->state)) 5677 return IRQ_HANDLED; 5678 5679 /* Check if a fatal error happened */ 5680 stmmac_safety_feat_interrupt(priv); 5681 5682 return IRQ_HANDLED; 5683 } 5684 5685 static irqreturn_t stmmac_msi_intr_tx(int irq, void *data) 5686 { 5687 struct stmmac_tx_queue *tx_q = (struct stmmac_tx_queue *)data; 5688 int chan = tx_q->queue_index; 5689 struct stmmac_priv *priv; 5690 int status; 5691 5692 priv = container_of(tx_q, struct stmmac_priv, tx_queue[chan]); 5693 5694 if (unlikely(!data)) { 5695 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5696 return IRQ_NONE; 5697 } 5698 5699 /* Check if adapter is up */ 5700 if (test_bit(STMMAC_DOWN, &priv->state)) 5701 return IRQ_HANDLED; 5702 5703 status = stmmac_napi_check(priv, chan, DMA_DIR_TX); 5704 5705 if (unlikely(status & tx_hard_error_bump_tc)) { 5706 /* Try to bump up the dma threshold on this failure */ 5707 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 5708 tc <= 256) { 5709 tc += 64; 5710 if (priv->plat->force_thresh_dma_mode) 5711 stmmac_set_dma_operation_mode(priv, 5712 tc, 5713 tc, 5714 chan); 5715 else 5716 stmmac_set_dma_operation_mode(priv, 5717 tc, 5718 SF_DMA_MODE, 5719 chan); 5720 priv->xstats.threshold = tc; 5721 } 5722 } else if (unlikely(status == tx_hard_error)) { 5723 stmmac_tx_err(priv, chan); 5724 } 5725 5726 return IRQ_HANDLED; 5727 } 5728 5729 static irqreturn_t stmmac_msi_intr_rx(int irq, void *data) 5730 { 5731 struct stmmac_rx_queue *rx_q = (struct stmmac_rx_queue *)data; 5732 int chan = rx_q->queue_index; 5733 struct stmmac_priv *priv; 5734 5735 priv = container_of(rx_q, struct stmmac_priv, rx_queue[chan]); 5736 5737 if (unlikely(!data)) { 5738 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 5739 return IRQ_NONE; 5740 } 5741 5742 /* Check if adapter is up */ 5743 if (test_bit(STMMAC_DOWN, &priv->state)) 5744 return IRQ_HANDLED; 5745 5746 stmmac_napi_check(priv, chan, DMA_DIR_RX); 5747 5748 return IRQ_HANDLED; 5749 } 5750 5751 #ifdef CONFIG_NET_POLL_CONTROLLER 5752 /* Polling receive - used by NETCONSOLE and other diagnostic tools 5753 * to allow network I/O with interrupts disabled. 5754 */ 5755 static void stmmac_poll_controller(struct net_device *dev) 5756 { 5757 struct stmmac_priv *priv = netdev_priv(dev); 5758 int i; 5759 5760 /* If adapter is down, do nothing */ 5761 if (test_bit(STMMAC_DOWN, &priv->state)) 5762 return; 5763 5764 if (priv->plat->multi_msi_en) { 5765 for (i = 0; i < priv->plat->rx_queues_to_use; i++) 5766 stmmac_msi_intr_rx(0, &priv->rx_queue[i]); 5767 5768 for (i = 0; i < priv->plat->tx_queues_to_use; i++) 5769 stmmac_msi_intr_tx(0, &priv->tx_queue[i]); 5770 } else { 5771 disable_irq(dev->irq); 5772 stmmac_interrupt(dev->irq, dev); 5773 enable_irq(dev->irq); 5774 } 5775 } 5776 #endif 5777 5778 /** 5779 * stmmac_ioctl - Entry point for the Ioctl 5780 * @dev: Device pointer. 5781 * @rq: An IOCTL specefic structure, that can contain a pointer to 5782 * a proprietary structure used to pass information to the driver. 5783 * @cmd: IOCTL command 5784 * Description: 5785 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 5786 */ 5787 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 5788 { 5789 struct stmmac_priv *priv = netdev_priv (dev); 5790 int ret = -EOPNOTSUPP; 5791 5792 if (!netif_running(dev)) 5793 return -EINVAL; 5794 5795 switch (cmd) { 5796 case SIOCGMIIPHY: 5797 case SIOCGMIIREG: 5798 case SIOCSMIIREG: 5799 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 5800 break; 5801 case SIOCSHWTSTAMP: 5802 ret = stmmac_hwtstamp_set(dev, rq); 5803 break; 5804 case SIOCGHWTSTAMP: 5805 ret = stmmac_hwtstamp_get(dev, rq); 5806 break; 5807 default: 5808 break; 5809 } 5810 5811 return ret; 5812 } 5813 5814 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 5815 void *cb_priv) 5816 { 5817 struct stmmac_priv *priv = cb_priv; 5818 int ret = -EOPNOTSUPP; 5819 5820 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 5821 return ret; 5822 5823 __stmmac_disable_all_queues(priv); 5824 5825 switch (type) { 5826 case TC_SETUP_CLSU32: 5827 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 5828 break; 5829 case TC_SETUP_CLSFLOWER: 5830 ret = stmmac_tc_setup_cls(priv, priv, type_data); 5831 break; 5832 default: 5833 break; 5834 } 5835 5836 stmmac_enable_all_queues(priv); 5837 return ret; 5838 } 5839 5840 static LIST_HEAD(stmmac_block_cb_list); 5841 5842 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 5843 void *type_data) 5844 { 5845 struct stmmac_priv *priv = netdev_priv(ndev); 5846 5847 switch (type) { 5848 case TC_SETUP_BLOCK: 5849 return flow_block_cb_setup_simple(type_data, 5850 &stmmac_block_cb_list, 5851 stmmac_setup_tc_block_cb, 5852 priv, priv, true); 5853 case TC_SETUP_QDISC_CBS: 5854 return stmmac_tc_setup_cbs(priv, priv, type_data); 5855 case TC_SETUP_QDISC_TAPRIO: 5856 return stmmac_tc_setup_taprio(priv, priv, type_data); 5857 case TC_SETUP_QDISC_ETF: 5858 return stmmac_tc_setup_etf(priv, priv, type_data); 5859 default: 5860 return -EOPNOTSUPP; 5861 } 5862 } 5863 5864 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 5865 struct net_device *sb_dev) 5866 { 5867 int gso = skb_shinfo(skb)->gso_type; 5868 5869 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 5870 /* 5871 * There is no way to determine the number of TSO/USO 5872 * capable Queues. Let's use always the Queue 0 5873 * because if TSO/USO is supported then at least this 5874 * one will be capable. 5875 */ 5876 return 0; 5877 } 5878 5879 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 5880 } 5881 5882 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 5883 { 5884 struct stmmac_priv *priv = netdev_priv(ndev); 5885 int ret = 0; 5886 5887 ret = pm_runtime_get_sync(priv->device); 5888 if (ret < 0) { 5889 pm_runtime_put_noidle(priv->device); 5890 return ret; 5891 } 5892 5893 ret = eth_mac_addr(ndev, addr); 5894 if (ret) 5895 goto set_mac_error; 5896 5897 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 5898 5899 set_mac_error: 5900 pm_runtime_put(priv->device); 5901 5902 return ret; 5903 } 5904 5905 #ifdef CONFIG_DEBUG_FS 5906 static struct dentry *stmmac_fs_dir; 5907 5908 static void sysfs_display_ring(void *head, int size, int extend_desc, 5909 struct seq_file *seq, dma_addr_t dma_phy_addr) 5910 { 5911 int i; 5912 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 5913 struct dma_desc *p = (struct dma_desc *)head; 5914 dma_addr_t dma_addr; 5915 5916 for (i = 0; i < size; i++) { 5917 if (extend_desc) { 5918 dma_addr = dma_phy_addr + i * sizeof(*ep); 5919 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5920 i, &dma_addr, 5921 le32_to_cpu(ep->basic.des0), 5922 le32_to_cpu(ep->basic.des1), 5923 le32_to_cpu(ep->basic.des2), 5924 le32_to_cpu(ep->basic.des3)); 5925 ep++; 5926 } else { 5927 dma_addr = dma_phy_addr + i * sizeof(*p); 5928 seq_printf(seq, "%d [%pad]: 0x%x 0x%x 0x%x 0x%x\n", 5929 i, &dma_addr, 5930 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 5931 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 5932 p++; 5933 } 5934 seq_printf(seq, "\n"); 5935 } 5936 } 5937 5938 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 5939 { 5940 struct net_device *dev = seq->private; 5941 struct stmmac_priv *priv = netdev_priv(dev); 5942 u32 rx_count = priv->plat->rx_queues_to_use; 5943 u32 tx_count = priv->plat->tx_queues_to_use; 5944 u32 queue; 5945 5946 if ((dev->flags & IFF_UP) == 0) 5947 return 0; 5948 5949 for (queue = 0; queue < rx_count; queue++) { 5950 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5951 5952 seq_printf(seq, "RX Queue %d:\n", queue); 5953 5954 if (priv->extend_desc) { 5955 seq_printf(seq, "Extended descriptor ring:\n"); 5956 sysfs_display_ring((void *)rx_q->dma_erx, 5957 priv->dma_rx_size, 1, seq, rx_q->dma_rx_phy); 5958 } else { 5959 seq_printf(seq, "Descriptor ring:\n"); 5960 sysfs_display_ring((void *)rx_q->dma_rx, 5961 priv->dma_rx_size, 0, seq, rx_q->dma_rx_phy); 5962 } 5963 } 5964 5965 for (queue = 0; queue < tx_count; queue++) { 5966 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5967 5968 seq_printf(seq, "TX Queue %d:\n", queue); 5969 5970 if (priv->extend_desc) { 5971 seq_printf(seq, "Extended descriptor ring:\n"); 5972 sysfs_display_ring((void *)tx_q->dma_etx, 5973 priv->dma_tx_size, 1, seq, tx_q->dma_tx_phy); 5974 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 5975 seq_printf(seq, "Descriptor ring:\n"); 5976 sysfs_display_ring((void *)tx_q->dma_tx, 5977 priv->dma_tx_size, 0, seq, tx_q->dma_tx_phy); 5978 } 5979 } 5980 5981 return 0; 5982 } 5983 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 5984 5985 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 5986 { 5987 struct net_device *dev = seq->private; 5988 struct stmmac_priv *priv = netdev_priv(dev); 5989 5990 if (!priv->hw_cap_support) { 5991 seq_printf(seq, "DMA HW features not supported\n"); 5992 return 0; 5993 } 5994 5995 seq_printf(seq, "==============================\n"); 5996 seq_printf(seq, "\tDMA HW features\n"); 5997 seq_printf(seq, "==============================\n"); 5998 5999 seq_printf(seq, "\t10/100 Mbps: %s\n", 6000 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 6001 seq_printf(seq, "\t1000 Mbps: %s\n", 6002 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 6003 seq_printf(seq, "\tHalf duplex: %s\n", 6004 (priv->dma_cap.half_duplex) ? "Y" : "N"); 6005 seq_printf(seq, "\tHash Filter: %s\n", 6006 (priv->dma_cap.hash_filter) ? "Y" : "N"); 6007 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 6008 (priv->dma_cap.multi_addr) ? "Y" : "N"); 6009 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 6010 (priv->dma_cap.pcs) ? "Y" : "N"); 6011 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 6012 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 6013 seq_printf(seq, "\tPMT Remote wake up: %s\n", 6014 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 6015 seq_printf(seq, "\tPMT Magic Frame: %s\n", 6016 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 6017 seq_printf(seq, "\tRMON module: %s\n", 6018 (priv->dma_cap.rmon) ? "Y" : "N"); 6019 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 6020 (priv->dma_cap.time_stamp) ? "Y" : "N"); 6021 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 6022 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 6023 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 6024 (priv->dma_cap.eee) ? "Y" : "N"); 6025 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 6026 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 6027 (priv->dma_cap.tx_coe) ? "Y" : "N"); 6028 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 6029 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 6030 (priv->dma_cap.rx_coe) ? "Y" : "N"); 6031 } else { 6032 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 6033 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 6034 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 6035 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 6036 } 6037 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 6038 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 6039 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 6040 priv->dma_cap.number_rx_channel); 6041 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 6042 priv->dma_cap.number_tx_channel); 6043 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 6044 priv->dma_cap.number_rx_queues); 6045 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 6046 priv->dma_cap.number_tx_queues); 6047 seq_printf(seq, "\tEnhanced descriptors: %s\n", 6048 (priv->dma_cap.enh_desc) ? "Y" : "N"); 6049 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 6050 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 6051 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 6052 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 6053 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 6054 priv->dma_cap.pps_out_num); 6055 seq_printf(seq, "\tSafety Features: %s\n", 6056 priv->dma_cap.asp ? "Y" : "N"); 6057 seq_printf(seq, "\tFlexible RX Parser: %s\n", 6058 priv->dma_cap.frpsel ? "Y" : "N"); 6059 seq_printf(seq, "\tEnhanced Addressing: %d\n", 6060 priv->dma_cap.addr64); 6061 seq_printf(seq, "\tReceive Side Scaling: %s\n", 6062 priv->dma_cap.rssen ? "Y" : "N"); 6063 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 6064 priv->dma_cap.vlhash ? "Y" : "N"); 6065 seq_printf(seq, "\tSplit Header: %s\n", 6066 priv->dma_cap.sphen ? "Y" : "N"); 6067 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 6068 priv->dma_cap.vlins ? "Y" : "N"); 6069 seq_printf(seq, "\tDouble VLAN: %s\n", 6070 priv->dma_cap.dvlan ? "Y" : "N"); 6071 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 6072 priv->dma_cap.l3l4fnum); 6073 seq_printf(seq, "\tARP Offloading: %s\n", 6074 priv->dma_cap.arpoffsel ? "Y" : "N"); 6075 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 6076 priv->dma_cap.estsel ? "Y" : "N"); 6077 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 6078 priv->dma_cap.fpesel ? "Y" : "N"); 6079 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 6080 priv->dma_cap.tbssel ? "Y" : "N"); 6081 return 0; 6082 } 6083 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 6084 6085 /* Use network device events to rename debugfs file entries. 6086 */ 6087 static int stmmac_device_event(struct notifier_block *unused, 6088 unsigned long event, void *ptr) 6089 { 6090 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 6091 struct stmmac_priv *priv = netdev_priv(dev); 6092 6093 if (dev->netdev_ops != &stmmac_netdev_ops) 6094 goto done; 6095 6096 switch (event) { 6097 case NETDEV_CHANGENAME: 6098 if (priv->dbgfs_dir) 6099 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 6100 priv->dbgfs_dir, 6101 stmmac_fs_dir, 6102 dev->name); 6103 break; 6104 } 6105 done: 6106 return NOTIFY_DONE; 6107 } 6108 6109 static struct notifier_block stmmac_notifier = { 6110 .notifier_call = stmmac_device_event, 6111 }; 6112 6113 static void stmmac_init_fs(struct net_device *dev) 6114 { 6115 struct stmmac_priv *priv = netdev_priv(dev); 6116 6117 rtnl_lock(); 6118 6119 /* Create per netdev entries */ 6120 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 6121 6122 /* Entry to report DMA RX/TX rings */ 6123 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 6124 &stmmac_rings_status_fops); 6125 6126 /* Entry to report the DMA HW features */ 6127 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 6128 &stmmac_dma_cap_fops); 6129 6130 rtnl_unlock(); 6131 } 6132 6133 static void stmmac_exit_fs(struct net_device *dev) 6134 { 6135 struct stmmac_priv *priv = netdev_priv(dev); 6136 6137 debugfs_remove_recursive(priv->dbgfs_dir); 6138 } 6139 #endif /* CONFIG_DEBUG_FS */ 6140 6141 static u32 stmmac_vid_crc32_le(__le16 vid_le) 6142 { 6143 unsigned char *data = (unsigned char *)&vid_le; 6144 unsigned char data_byte = 0; 6145 u32 crc = ~0x0; 6146 u32 temp = 0; 6147 int i, bits; 6148 6149 bits = get_bitmask_order(VLAN_VID_MASK); 6150 for (i = 0; i < bits; i++) { 6151 if ((i % 8) == 0) 6152 data_byte = data[i / 8]; 6153 6154 temp = ((crc & 1) ^ data_byte) & 1; 6155 crc >>= 1; 6156 data_byte >>= 1; 6157 6158 if (temp) 6159 crc ^= 0xedb88320; 6160 } 6161 6162 return crc; 6163 } 6164 6165 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 6166 { 6167 u32 crc, hash = 0; 6168 __le16 pmatch = 0; 6169 int count = 0; 6170 u16 vid = 0; 6171 6172 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 6173 __le16 vid_le = cpu_to_le16(vid); 6174 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 6175 hash |= (1 << crc); 6176 count++; 6177 } 6178 6179 if (!priv->dma_cap.vlhash) { 6180 if (count > 2) /* VID = 0 always passes filter */ 6181 return -EOPNOTSUPP; 6182 6183 pmatch = cpu_to_le16(vid); 6184 hash = 0; 6185 } 6186 6187 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 6188 } 6189 6190 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 6191 { 6192 struct stmmac_priv *priv = netdev_priv(ndev); 6193 bool is_double = false; 6194 int ret; 6195 6196 if (be16_to_cpu(proto) == ETH_P_8021AD) 6197 is_double = true; 6198 6199 set_bit(vid, priv->active_vlans); 6200 ret = stmmac_vlan_update(priv, is_double); 6201 if (ret) { 6202 clear_bit(vid, priv->active_vlans); 6203 return ret; 6204 } 6205 6206 if (priv->hw->num_vlan) { 6207 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6208 if (ret) 6209 return ret; 6210 } 6211 6212 return 0; 6213 } 6214 6215 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 6216 { 6217 struct stmmac_priv *priv = netdev_priv(ndev); 6218 bool is_double = false; 6219 int ret; 6220 6221 ret = pm_runtime_get_sync(priv->device); 6222 if (ret < 0) { 6223 pm_runtime_put_noidle(priv->device); 6224 return ret; 6225 } 6226 6227 if (be16_to_cpu(proto) == ETH_P_8021AD) 6228 is_double = true; 6229 6230 clear_bit(vid, priv->active_vlans); 6231 6232 if (priv->hw->num_vlan) { 6233 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 6234 if (ret) 6235 goto del_vlan_error; 6236 } 6237 6238 ret = stmmac_vlan_update(priv, is_double); 6239 6240 del_vlan_error: 6241 pm_runtime_put(priv->device); 6242 6243 return ret; 6244 } 6245 6246 static int stmmac_bpf(struct net_device *dev, struct netdev_bpf *bpf) 6247 { 6248 struct stmmac_priv *priv = netdev_priv(dev); 6249 6250 switch (bpf->command) { 6251 case XDP_SETUP_PROG: 6252 return stmmac_xdp_set_prog(priv, bpf->prog, bpf->extack); 6253 case XDP_SETUP_XSK_POOL: 6254 return stmmac_xdp_setup_pool(priv, bpf->xsk.pool, 6255 bpf->xsk.queue_id); 6256 default: 6257 return -EOPNOTSUPP; 6258 } 6259 } 6260 6261 static int stmmac_xdp_xmit(struct net_device *dev, int num_frames, 6262 struct xdp_frame **frames, u32 flags) 6263 { 6264 struct stmmac_priv *priv = netdev_priv(dev); 6265 int cpu = smp_processor_id(); 6266 struct netdev_queue *nq; 6267 int i, nxmit = 0; 6268 int queue; 6269 6270 if (unlikely(test_bit(STMMAC_DOWN, &priv->state))) 6271 return -ENETDOWN; 6272 6273 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 6274 return -EINVAL; 6275 6276 queue = stmmac_xdp_get_tx_queue(priv, cpu); 6277 nq = netdev_get_tx_queue(priv->dev, queue); 6278 6279 __netif_tx_lock(nq, cpu); 6280 /* Avoids TX time-out as we are sharing with slow path */ 6281 nq->trans_start = jiffies; 6282 6283 for (i = 0; i < num_frames; i++) { 6284 int res; 6285 6286 res = stmmac_xdp_xmit_xdpf(priv, queue, frames[i], true); 6287 if (res == STMMAC_XDP_CONSUMED) 6288 break; 6289 6290 nxmit++; 6291 } 6292 6293 if (flags & XDP_XMIT_FLUSH) { 6294 stmmac_flush_tx_descriptors(priv, queue); 6295 stmmac_tx_timer_arm(priv, queue); 6296 } 6297 6298 __netif_tx_unlock(nq); 6299 6300 return nxmit; 6301 } 6302 6303 void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue) 6304 { 6305 struct stmmac_channel *ch = &priv->channel[queue]; 6306 unsigned long flags; 6307 6308 spin_lock_irqsave(&ch->lock, flags); 6309 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6310 spin_unlock_irqrestore(&ch->lock, flags); 6311 6312 stmmac_stop_rx_dma(priv, queue); 6313 __free_dma_rx_desc_resources(priv, queue); 6314 } 6315 6316 void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue) 6317 { 6318 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 6319 struct stmmac_channel *ch = &priv->channel[queue]; 6320 unsigned long flags; 6321 u32 buf_size; 6322 int ret; 6323 6324 ret = __alloc_dma_rx_desc_resources(priv, queue); 6325 if (ret) { 6326 netdev_err(priv->dev, "Failed to alloc RX desc.\n"); 6327 return; 6328 } 6329 6330 ret = __init_dma_rx_desc_rings(priv, queue, GFP_KERNEL); 6331 if (ret) { 6332 __free_dma_rx_desc_resources(priv, queue); 6333 netdev_err(priv->dev, "Failed to init RX desc.\n"); 6334 return; 6335 } 6336 6337 stmmac_clear_rx_descriptors(priv, queue); 6338 6339 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6340 rx_q->dma_rx_phy, rx_q->queue_index); 6341 6342 rx_q->rx_tail_addr = rx_q->dma_rx_phy + (rx_q->buf_alloc_num * 6343 sizeof(struct dma_desc)); 6344 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 6345 rx_q->rx_tail_addr, rx_q->queue_index); 6346 6347 if (rx_q->xsk_pool && rx_q->buf_alloc_num) { 6348 buf_size = xsk_pool_get_rx_frame_size(rx_q->xsk_pool); 6349 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6350 buf_size, 6351 rx_q->queue_index); 6352 } else { 6353 stmmac_set_dma_bfsize(priv, priv->ioaddr, 6354 priv->dma_buf_sz, 6355 rx_q->queue_index); 6356 } 6357 6358 stmmac_start_rx_dma(priv, queue); 6359 6360 spin_lock_irqsave(&ch->lock, flags); 6361 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 1, 0); 6362 spin_unlock_irqrestore(&ch->lock, flags); 6363 } 6364 6365 void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue) 6366 { 6367 struct stmmac_channel *ch = &priv->channel[queue]; 6368 unsigned long flags; 6369 6370 spin_lock_irqsave(&ch->lock, flags); 6371 stmmac_disable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6372 spin_unlock_irqrestore(&ch->lock, flags); 6373 6374 stmmac_stop_tx_dma(priv, queue); 6375 __free_dma_tx_desc_resources(priv, queue); 6376 } 6377 6378 void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue) 6379 { 6380 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 6381 struct stmmac_channel *ch = &priv->channel[queue]; 6382 unsigned long flags; 6383 int ret; 6384 6385 ret = __alloc_dma_tx_desc_resources(priv, queue); 6386 if (ret) { 6387 netdev_err(priv->dev, "Failed to alloc TX desc.\n"); 6388 return; 6389 } 6390 6391 ret = __init_dma_tx_desc_rings(priv, queue); 6392 if (ret) { 6393 __free_dma_tx_desc_resources(priv, queue); 6394 netdev_err(priv->dev, "Failed to init TX desc.\n"); 6395 return; 6396 } 6397 6398 stmmac_clear_tx_descriptors(priv, queue); 6399 6400 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 6401 tx_q->dma_tx_phy, tx_q->queue_index); 6402 6403 if (tx_q->tbs & STMMAC_TBS_AVAIL) 6404 stmmac_enable_tbs(priv, priv->ioaddr, 1, tx_q->queue_index); 6405 6406 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 6407 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 6408 tx_q->tx_tail_addr, tx_q->queue_index); 6409 6410 stmmac_start_tx_dma(priv, queue); 6411 6412 spin_lock_irqsave(&ch->lock, flags); 6413 stmmac_enable_dma_irq(priv, priv->ioaddr, queue, 0, 1); 6414 spin_unlock_irqrestore(&ch->lock, flags); 6415 } 6416 6417 int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags) 6418 { 6419 struct stmmac_priv *priv = netdev_priv(dev); 6420 struct stmmac_rx_queue *rx_q; 6421 struct stmmac_tx_queue *tx_q; 6422 struct stmmac_channel *ch; 6423 6424 if (test_bit(STMMAC_DOWN, &priv->state) || 6425 !netif_carrier_ok(priv->dev)) 6426 return -ENETDOWN; 6427 6428 if (!stmmac_xdp_is_enabled(priv)) 6429 return -ENXIO; 6430 6431 if (queue >= priv->plat->rx_queues_to_use || 6432 queue >= priv->plat->tx_queues_to_use) 6433 return -EINVAL; 6434 6435 rx_q = &priv->rx_queue[queue]; 6436 tx_q = &priv->tx_queue[queue]; 6437 ch = &priv->channel[queue]; 6438 6439 if (!rx_q->xsk_pool && !tx_q->xsk_pool) 6440 return -ENXIO; 6441 6442 if (!napi_if_scheduled_mark_missed(&ch->rxtx_napi)) { 6443 /* EQoS does not have per-DMA channel SW interrupt, 6444 * so we schedule RX Napi straight-away. 6445 */ 6446 if (likely(napi_schedule_prep(&ch->rxtx_napi))) 6447 __napi_schedule(&ch->rxtx_napi); 6448 } 6449 6450 return 0; 6451 } 6452 6453 static const struct net_device_ops stmmac_netdev_ops = { 6454 .ndo_open = stmmac_open, 6455 .ndo_start_xmit = stmmac_xmit, 6456 .ndo_stop = stmmac_release, 6457 .ndo_change_mtu = stmmac_change_mtu, 6458 .ndo_fix_features = stmmac_fix_features, 6459 .ndo_set_features = stmmac_set_features, 6460 .ndo_set_rx_mode = stmmac_set_rx_mode, 6461 .ndo_tx_timeout = stmmac_tx_timeout, 6462 .ndo_do_ioctl = stmmac_ioctl, 6463 .ndo_setup_tc = stmmac_setup_tc, 6464 .ndo_select_queue = stmmac_select_queue, 6465 #ifdef CONFIG_NET_POLL_CONTROLLER 6466 .ndo_poll_controller = stmmac_poll_controller, 6467 #endif 6468 .ndo_set_mac_address = stmmac_set_mac_address, 6469 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 6470 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 6471 .ndo_bpf = stmmac_bpf, 6472 .ndo_xdp_xmit = stmmac_xdp_xmit, 6473 .ndo_xsk_wakeup = stmmac_xsk_wakeup, 6474 }; 6475 6476 static void stmmac_reset_subtask(struct stmmac_priv *priv) 6477 { 6478 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 6479 return; 6480 if (test_bit(STMMAC_DOWN, &priv->state)) 6481 return; 6482 6483 netdev_err(priv->dev, "Reset adapter.\n"); 6484 6485 rtnl_lock(); 6486 netif_trans_update(priv->dev); 6487 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 6488 usleep_range(1000, 2000); 6489 6490 set_bit(STMMAC_DOWN, &priv->state); 6491 dev_close(priv->dev); 6492 dev_open(priv->dev, NULL); 6493 clear_bit(STMMAC_DOWN, &priv->state); 6494 clear_bit(STMMAC_RESETING, &priv->state); 6495 rtnl_unlock(); 6496 } 6497 6498 static void stmmac_service_task(struct work_struct *work) 6499 { 6500 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6501 service_task); 6502 6503 stmmac_reset_subtask(priv); 6504 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 6505 } 6506 6507 /** 6508 * stmmac_hw_init - Init the MAC device 6509 * @priv: driver private structure 6510 * Description: this function is to configure the MAC device according to 6511 * some platform parameters or the HW capability register. It prepares the 6512 * driver to use either ring or chain modes and to setup either enhanced or 6513 * normal descriptors. 6514 */ 6515 static int stmmac_hw_init(struct stmmac_priv *priv) 6516 { 6517 int ret; 6518 6519 /* dwmac-sun8i only work in chain mode */ 6520 if (priv->plat->has_sun8i) 6521 chain_mode = 1; 6522 priv->chain_mode = chain_mode; 6523 6524 /* Initialize HW Interface */ 6525 ret = stmmac_hwif_init(priv); 6526 if (ret) 6527 return ret; 6528 6529 /* Get the HW capability (new GMAC newer than 3.50a) */ 6530 priv->hw_cap_support = stmmac_get_hw_features(priv); 6531 if (priv->hw_cap_support) { 6532 dev_info(priv->device, "DMA HW capability register supported\n"); 6533 6534 /* We can override some gmac/dma configuration fields: e.g. 6535 * enh_desc, tx_coe (e.g. that are passed through the 6536 * platform) with the values from the HW capability 6537 * register (if supported). 6538 */ 6539 priv->plat->enh_desc = priv->dma_cap.enh_desc; 6540 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 6541 priv->hw->pmt = priv->plat->pmt; 6542 if (priv->dma_cap.hash_tb_sz) { 6543 priv->hw->multicast_filter_bins = 6544 (BIT(priv->dma_cap.hash_tb_sz) << 5); 6545 priv->hw->mcast_bits_log2 = 6546 ilog2(priv->hw->multicast_filter_bins); 6547 } 6548 6549 /* TXCOE doesn't work in thresh DMA mode */ 6550 if (priv->plat->force_thresh_dma_mode) 6551 priv->plat->tx_coe = 0; 6552 else 6553 priv->plat->tx_coe = priv->dma_cap.tx_coe; 6554 6555 /* In case of GMAC4 rx_coe is from HW cap register. */ 6556 priv->plat->rx_coe = priv->dma_cap.rx_coe; 6557 6558 if (priv->dma_cap.rx_coe_type2) 6559 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 6560 else if (priv->dma_cap.rx_coe_type1) 6561 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 6562 6563 } else { 6564 dev_info(priv->device, "No HW DMA feature register supported\n"); 6565 } 6566 6567 if (priv->plat->rx_coe) { 6568 priv->hw->rx_csum = priv->plat->rx_coe; 6569 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 6570 if (priv->synopsys_id < DWMAC_CORE_4_00) 6571 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 6572 } 6573 if (priv->plat->tx_coe) 6574 dev_info(priv->device, "TX Checksum insertion supported\n"); 6575 6576 if (priv->plat->pmt) { 6577 dev_info(priv->device, "Wake-Up On Lan supported\n"); 6578 device_set_wakeup_capable(priv->device, 1); 6579 } 6580 6581 if (priv->dma_cap.tsoen) 6582 dev_info(priv->device, "TSO supported\n"); 6583 6584 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 6585 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 6586 6587 /* Run HW quirks, if any */ 6588 if (priv->hwif_quirks) { 6589 ret = priv->hwif_quirks(priv); 6590 if (ret) 6591 return ret; 6592 } 6593 6594 /* Rx Watchdog is available in the COREs newer than the 3.40. 6595 * In some case, for example on bugged HW this feature 6596 * has to be disable and this can be done by passing the 6597 * riwt_off field from the platform. 6598 */ 6599 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 6600 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 6601 priv->use_riwt = 1; 6602 dev_info(priv->device, 6603 "Enable RX Mitigation via HW Watchdog Timer\n"); 6604 } 6605 6606 return 0; 6607 } 6608 6609 static void stmmac_napi_add(struct net_device *dev) 6610 { 6611 struct stmmac_priv *priv = netdev_priv(dev); 6612 u32 queue, maxq; 6613 6614 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6615 6616 for (queue = 0; queue < maxq; queue++) { 6617 struct stmmac_channel *ch = &priv->channel[queue]; 6618 6619 ch->priv_data = priv; 6620 ch->index = queue; 6621 spin_lock_init(&ch->lock); 6622 6623 if (queue < priv->plat->rx_queues_to_use) { 6624 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 6625 NAPI_POLL_WEIGHT); 6626 } 6627 if (queue < priv->plat->tx_queues_to_use) { 6628 netif_tx_napi_add(dev, &ch->tx_napi, 6629 stmmac_napi_poll_tx, 6630 NAPI_POLL_WEIGHT); 6631 } 6632 if (queue < priv->plat->rx_queues_to_use && 6633 queue < priv->plat->tx_queues_to_use) { 6634 netif_napi_add(dev, &ch->rxtx_napi, 6635 stmmac_napi_poll_rxtx, 6636 NAPI_POLL_WEIGHT); 6637 } 6638 } 6639 } 6640 6641 static void stmmac_napi_del(struct net_device *dev) 6642 { 6643 struct stmmac_priv *priv = netdev_priv(dev); 6644 u32 queue, maxq; 6645 6646 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 6647 6648 for (queue = 0; queue < maxq; queue++) { 6649 struct stmmac_channel *ch = &priv->channel[queue]; 6650 6651 if (queue < priv->plat->rx_queues_to_use) 6652 netif_napi_del(&ch->rx_napi); 6653 if (queue < priv->plat->tx_queues_to_use) 6654 netif_napi_del(&ch->tx_napi); 6655 if (queue < priv->plat->rx_queues_to_use && 6656 queue < priv->plat->tx_queues_to_use) { 6657 netif_napi_del(&ch->rxtx_napi); 6658 } 6659 } 6660 } 6661 6662 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 6663 { 6664 struct stmmac_priv *priv = netdev_priv(dev); 6665 int ret = 0; 6666 6667 if (netif_running(dev)) 6668 stmmac_release(dev); 6669 6670 stmmac_napi_del(dev); 6671 6672 priv->plat->rx_queues_to_use = rx_cnt; 6673 priv->plat->tx_queues_to_use = tx_cnt; 6674 6675 stmmac_napi_add(dev); 6676 6677 if (netif_running(dev)) 6678 ret = stmmac_open(dev); 6679 6680 return ret; 6681 } 6682 6683 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 6684 { 6685 struct stmmac_priv *priv = netdev_priv(dev); 6686 int ret = 0; 6687 6688 if (netif_running(dev)) 6689 stmmac_release(dev); 6690 6691 priv->dma_rx_size = rx_size; 6692 priv->dma_tx_size = tx_size; 6693 6694 if (netif_running(dev)) 6695 ret = stmmac_open(dev); 6696 6697 return ret; 6698 } 6699 6700 #define SEND_VERIFY_MPAKCET_FMT "Send Verify mPacket lo_state=%d lp_state=%d\n" 6701 static void stmmac_fpe_lp_task(struct work_struct *work) 6702 { 6703 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 6704 fpe_task); 6705 struct stmmac_fpe_cfg *fpe_cfg = priv->plat->fpe_cfg; 6706 enum stmmac_fpe_state *lo_state = &fpe_cfg->lo_fpe_state; 6707 enum stmmac_fpe_state *lp_state = &fpe_cfg->lp_fpe_state; 6708 bool *hs_enable = &fpe_cfg->hs_enable; 6709 bool *enable = &fpe_cfg->enable; 6710 int retries = 20; 6711 6712 while (retries-- > 0) { 6713 /* Bail out immediately if FPE handshake is OFF */ 6714 if (*lo_state == FPE_STATE_OFF || !*hs_enable) 6715 break; 6716 6717 if (*lo_state == FPE_STATE_ENTERING_ON && 6718 *lp_state == FPE_STATE_ENTERING_ON) { 6719 stmmac_fpe_configure(priv, priv->ioaddr, 6720 priv->plat->tx_queues_to_use, 6721 priv->plat->rx_queues_to_use, 6722 *enable); 6723 6724 netdev_info(priv->dev, "configured FPE\n"); 6725 6726 *lo_state = FPE_STATE_ON; 6727 *lp_state = FPE_STATE_ON; 6728 netdev_info(priv->dev, "!!! BOTH FPE stations ON\n"); 6729 break; 6730 } 6731 6732 if ((*lo_state == FPE_STATE_CAPABLE || 6733 *lo_state == FPE_STATE_ENTERING_ON) && 6734 *lp_state != FPE_STATE_ON) { 6735 netdev_info(priv->dev, SEND_VERIFY_MPAKCET_FMT, 6736 *lo_state, *lp_state); 6737 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6738 MPACKET_VERIFY); 6739 } 6740 /* Sleep then retry */ 6741 msleep(500); 6742 } 6743 6744 clear_bit(__FPE_TASK_SCHED, &priv->fpe_task_state); 6745 } 6746 6747 void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable) 6748 { 6749 if (priv->plat->fpe_cfg->hs_enable != enable) { 6750 if (enable) { 6751 stmmac_fpe_send_mpacket(priv, priv->ioaddr, 6752 MPACKET_VERIFY); 6753 } else { 6754 priv->plat->fpe_cfg->lo_fpe_state = FPE_STATE_OFF; 6755 priv->plat->fpe_cfg->lp_fpe_state = FPE_STATE_OFF; 6756 } 6757 6758 priv->plat->fpe_cfg->hs_enable = enable; 6759 } 6760 } 6761 6762 /** 6763 * stmmac_dvr_probe 6764 * @device: device pointer 6765 * @plat_dat: platform data pointer 6766 * @res: stmmac resource pointer 6767 * Description: this is the main probe function used to 6768 * call the alloc_etherdev, allocate the priv structure. 6769 * Return: 6770 * returns 0 on success, otherwise errno. 6771 */ 6772 int stmmac_dvr_probe(struct device *device, 6773 struct plat_stmmacenet_data *plat_dat, 6774 struct stmmac_resources *res) 6775 { 6776 struct net_device *ndev = NULL; 6777 struct stmmac_priv *priv; 6778 u32 rxq; 6779 int i, ret = 0; 6780 6781 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 6782 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 6783 if (!ndev) 6784 return -ENOMEM; 6785 6786 SET_NETDEV_DEV(ndev, device); 6787 6788 priv = netdev_priv(ndev); 6789 priv->device = device; 6790 priv->dev = ndev; 6791 6792 stmmac_set_ethtool_ops(ndev); 6793 priv->pause = pause; 6794 priv->plat = plat_dat; 6795 priv->ioaddr = res->addr; 6796 priv->dev->base_addr = (unsigned long)res->addr; 6797 priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en; 6798 6799 priv->dev->irq = res->irq; 6800 priv->wol_irq = res->wol_irq; 6801 priv->lpi_irq = res->lpi_irq; 6802 priv->sfty_ce_irq = res->sfty_ce_irq; 6803 priv->sfty_ue_irq = res->sfty_ue_irq; 6804 for (i = 0; i < MTL_MAX_RX_QUEUES; i++) 6805 priv->rx_irq[i] = res->rx_irq[i]; 6806 for (i = 0; i < MTL_MAX_TX_QUEUES; i++) 6807 priv->tx_irq[i] = res->tx_irq[i]; 6808 6809 if (!is_zero_ether_addr(res->mac)) 6810 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 6811 6812 dev_set_drvdata(device, priv->dev); 6813 6814 /* Verify driver arguments */ 6815 stmmac_verify_args(); 6816 6817 priv->af_xdp_zc_qps = bitmap_zalloc(MTL_MAX_TX_QUEUES, GFP_KERNEL); 6818 if (!priv->af_xdp_zc_qps) 6819 return -ENOMEM; 6820 6821 /* Allocate workqueue */ 6822 priv->wq = create_singlethread_workqueue("stmmac_wq"); 6823 if (!priv->wq) { 6824 dev_err(priv->device, "failed to create workqueue\n"); 6825 return -ENOMEM; 6826 } 6827 6828 INIT_WORK(&priv->service_task, stmmac_service_task); 6829 6830 /* Initialize Link Partner FPE workqueue */ 6831 INIT_WORK(&priv->fpe_task, stmmac_fpe_lp_task); 6832 6833 /* Override with kernel parameters if supplied XXX CRS XXX 6834 * this needs to have multiple instances 6835 */ 6836 if ((phyaddr >= 0) && (phyaddr <= 31)) 6837 priv->plat->phy_addr = phyaddr; 6838 6839 if (priv->plat->stmmac_rst) { 6840 ret = reset_control_assert(priv->plat->stmmac_rst); 6841 reset_control_deassert(priv->plat->stmmac_rst); 6842 /* Some reset controllers have only reset callback instead of 6843 * assert + deassert callbacks pair. 6844 */ 6845 if (ret == -ENOTSUPP) 6846 reset_control_reset(priv->plat->stmmac_rst); 6847 } 6848 6849 /* Init MAC and get the capabilities */ 6850 ret = stmmac_hw_init(priv); 6851 if (ret) 6852 goto error_hw_init; 6853 6854 /* Only DWMAC core version 5.20 onwards supports HW descriptor prefetch. 6855 */ 6856 if (priv->synopsys_id < DWMAC_CORE_5_20) 6857 priv->plat->dma_cfg->dche = false; 6858 6859 stmmac_check_ether_addr(priv); 6860 6861 ndev->netdev_ops = &stmmac_netdev_ops; 6862 6863 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 6864 NETIF_F_RXCSUM; 6865 6866 ret = stmmac_tc_init(priv, priv); 6867 if (!ret) { 6868 ndev->hw_features |= NETIF_F_HW_TC; 6869 } 6870 6871 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 6872 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 6873 if (priv->plat->has_gmac4) 6874 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 6875 priv->tso = true; 6876 dev_info(priv->device, "TSO feature enabled\n"); 6877 } 6878 6879 if (priv->dma_cap.sphen) { 6880 ndev->hw_features |= NETIF_F_GRO; 6881 priv->sph_cap = true; 6882 priv->sph = priv->sph_cap; 6883 dev_info(priv->device, "SPH feature enabled\n"); 6884 } 6885 6886 /* The current IP register MAC_HW_Feature1[ADDR64] only define 6887 * 32/40/64 bit width, but some SOC support others like i.MX8MP 6888 * support 34 bits but it map to 40 bits width in MAC_HW_Feature1[ADDR64]. 6889 * So overwrite dma_cap.addr64 according to HW real design. 6890 */ 6891 if (priv->plat->addr64) 6892 priv->dma_cap.addr64 = priv->plat->addr64; 6893 6894 if (priv->dma_cap.addr64) { 6895 ret = dma_set_mask_and_coherent(device, 6896 DMA_BIT_MASK(priv->dma_cap.addr64)); 6897 if (!ret) { 6898 dev_info(priv->device, "Using %d bits DMA width\n", 6899 priv->dma_cap.addr64); 6900 6901 /* 6902 * If more than 32 bits can be addressed, make sure to 6903 * enable enhanced addressing mode. 6904 */ 6905 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 6906 priv->plat->dma_cfg->eame = true; 6907 } else { 6908 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 6909 if (ret) { 6910 dev_err(priv->device, "Failed to set DMA Mask\n"); 6911 goto error_hw_init; 6912 } 6913 6914 priv->dma_cap.addr64 = 32; 6915 } 6916 } 6917 6918 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 6919 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 6920 #ifdef STMMAC_VLAN_TAG_USED 6921 /* Both mac100 and gmac support receive VLAN tag detection */ 6922 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 6923 if (priv->dma_cap.vlhash) { 6924 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 6925 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 6926 } 6927 if (priv->dma_cap.vlins) { 6928 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 6929 if (priv->dma_cap.dvlan) 6930 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 6931 } 6932 #endif 6933 priv->msg_enable = netif_msg_init(debug, default_msg_level); 6934 6935 /* Initialize RSS */ 6936 rxq = priv->plat->rx_queues_to_use; 6937 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 6938 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 6939 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 6940 6941 if (priv->dma_cap.rssen && priv->plat->rss_en) 6942 ndev->features |= NETIF_F_RXHASH; 6943 6944 /* MTU range: 46 - hw-specific max */ 6945 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 6946 if (priv->plat->has_xgmac) 6947 ndev->max_mtu = XGMAC_JUMBO_LEN; 6948 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 6949 ndev->max_mtu = JUMBO_LEN; 6950 else 6951 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 6952 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 6953 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 6954 */ 6955 if ((priv->plat->maxmtu < ndev->max_mtu) && 6956 (priv->plat->maxmtu >= ndev->min_mtu)) 6957 ndev->max_mtu = priv->plat->maxmtu; 6958 else if (priv->plat->maxmtu < ndev->min_mtu) 6959 dev_warn(priv->device, 6960 "%s: warning: maxmtu having invalid value (%d)\n", 6961 __func__, priv->plat->maxmtu); 6962 6963 if (flow_ctrl) 6964 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 6965 6966 /* Setup channels NAPI */ 6967 stmmac_napi_add(ndev); 6968 6969 mutex_init(&priv->lock); 6970 6971 /* If a specific clk_csr value is passed from the platform 6972 * this means that the CSR Clock Range selection cannot be 6973 * changed at run-time and it is fixed. Viceversa the driver'll try to 6974 * set the MDC clock dynamically according to the csr actual 6975 * clock input. 6976 */ 6977 if (priv->plat->clk_csr >= 0) 6978 priv->clk_csr = priv->plat->clk_csr; 6979 else 6980 stmmac_clk_csr_set(priv); 6981 6982 stmmac_check_pcs_mode(priv); 6983 6984 pm_runtime_get_noresume(device); 6985 pm_runtime_set_active(device); 6986 pm_runtime_enable(device); 6987 6988 if (priv->hw->pcs != STMMAC_PCS_TBI && 6989 priv->hw->pcs != STMMAC_PCS_RTBI) { 6990 /* MDIO bus Registration */ 6991 ret = stmmac_mdio_register(ndev); 6992 if (ret < 0) { 6993 dev_err(priv->device, 6994 "%s: MDIO bus (id: %d) registration failed", 6995 __func__, priv->plat->bus_id); 6996 goto error_mdio_register; 6997 } 6998 } 6999 7000 if (priv->plat->speed_mode_2500) 7001 priv->plat->speed_mode_2500(ndev, priv->plat->bsp_priv); 7002 7003 if (priv->plat->mdio_bus_data) { 7004 if (priv->plat->mdio_bus_data->has_xpcs) { 7005 ret = stmmac_xpcs_setup(priv->mii); 7006 if (ret) 7007 goto error_xpcs_setup; 7008 } 7009 } 7010 7011 ret = stmmac_phy_setup(priv); 7012 if (ret) { 7013 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 7014 goto error_phy_setup; 7015 } 7016 7017 ret = register_netdev(ndev); 7018 if (ret) { 7019 dev_err(priv->device, "%s: ERROR %i registering the device\n", 7020 __func__, ret); 7021 goto error_netdev_register; 7022 } 7023 7024 if (priv->plat->serdes_powerup) { 7025 ret = priv->plat->serdes_powerup(ndev, 7026 priv->plat->bsp_priv); 7027 7028 if (ret < 0) 7029 goto error_serdes_powerup; 7030 } 7031 7032 #ifdef CONFIG_DEBUG_FS 7033 stmmac_init_fs(ndev); 7034 #endif 7035 7036 /* Let pm_runtime_put() disable the clocks. 7037 * If CONFIG_PM is not enabled, the clocks will stay powered. 7038 */ 7039 pm_runtime_put(device); 7040 7041 return ret; 7042 7043 error_serdes_powerup: 7044 unregister_netdev(ndev); 7045 error_netdev_register: 7046 phylink_destroy(priv->phylink); 7047 error_xpcs_setup: 7048 error_phy_setup: 7049 if (priv->hw->pcs != STMMAC_PCS_TBI && 7050 priv->hw->pcs != STMMAC_PCS_RTBI) 7051 stmmac_mdio_unregister(ndev); 7052 error_mdio_register: 7053 stmmac_napi_del(ndev); 7054 error_hw_init: 7055 destroy_workqueue(priv->wq); 7056 bitmap_free(priv->af_xdp_zc_qps); 7057 7058 return ret; 7059 } 7060 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 7061 7062 /** 7063 * stmmac_dvr_remove 7064 * @dev: device pointer 7065 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 7066 * changes the link status, releases the DMA descriptor rings. 7067 */ 7068 int stmmac_dvr_remove(struct device *dev) 7069 { 7070 struct net_device *ndev = dev_get_drvdata(dev); 7071 struct stmmac_priv *priv = netdev_priv(ndev); 7072 7073 netdev_info(priv->dev, "%s: removing driver", __func__); 7074 7075 stmmac_stop_all_dma(priv); 7076 stmmac_mac_set(priv, priv->ioaddr, false); 7077 netif_carrier_off(ndev); 7078 unregister_netdev(ndev); 7079 7080 /* Serdes power down needs to happen after VLAN filter 7081 * is deleted that is triggered by unregister_netdev(). 7082 */ 7083 if (priv->plat->serdes_powerdown) 7084 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7085 7086 #ifdef CONFIG_DEBUG_FS 7087 stmmac_exit_fs(ndev); 7088 #endif 7089 phylink_destroy(priv->phylink); 7090 if (priv->plat->stmmac_rst) 7091 reset_control_assert(priv->plat->stmmac_rst); 7092 pm_runtime_put(dev); 7093 pm_runtime_disable(dev); 7094 if (priv->hw->pcs != STMMAC_PCS_TBI && 7095 priv->hw->pcs != STMMAC_PCS_RTBI) 7096 stmmac_mdio_unregister(ndev); 7097 destroy_workqueue(priv->wq); 7098 mutex_destroy(&priv->lock); 7099 bitmap_free(priv->af_xdp_zc_qps); 7100 7101 return 0; 7102 } 7103 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 7104 7105 /** 7106 * stmmac_suspend - suspend callback 7107 * @dev: device pointer 7108 * Description: this is the function to suspend the device and it is called 7109 * by the platform driver to stop the network queue, release the resources, 7110 * program the PMT register (for WoL), clean and release driver resources. 7111 */ 7112 int stmmac_suspend(struct device *dev) 7113 { 7114 struct net_device *ndev = dev_get_drvdata(dev); 7115 struct stmmac_priv *priv = netdev_priv(ndev); 7116 u32 chan; 7117 int ret; 7118 7119 if (!ndev || !netif_running(ndev)) 7120 return 0; 7121 7122 phylink_mac_change(priv->phylink, false); 7123 7124 mutex_lock(&priv->lock); 7125 7126 netif_device_detach(ndev); 7127 7128 stmmac_disable_all_queues(priv); 7129 7130 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 7131 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 7132 7133 if (priv->eee_enabled) { 7134 priv->tx_path_in_lpi_mode = false; 7135 del_timer_sync(&priv->eee_ctrl_timer); 7136 } 7137 7138 /* Stop TX/RX DMA */ 7139 stmmac_stop_all_dma(priv); 7140 7141 if (priv->plat->serdes_powerdown) 7142 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 7143 7144 /* Enable Power down mode by programming the PMT regs */ 7145 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7146 stmmac_pmt(priv, priv->hw, priv->wolopts); 7147 priv->irq_wake = 1; 7148 } else { 7149 mutex_unlock(&priv->lock); 7150 rtnl_lock(); 7151 if (device_may_wakeup(priv->device)) 7152 phylink_speed_down(priv->phylink, false); 7153 phylink_stop(priv->phylink); 7154 rtnl_unlock(); 7155 mutex_lock(&priv->lock); 7156 7157 stmmac_mac_set(priv, priv->ioaddr, false); 7158 pinctrl_pm_select_sleep_state(priv->device); 7159 /* Disable clock in case of PWM is off */ 7160 clk_disable_unprepare(priv->plat->clk_ptp_ref); 7161 ret = pm_runtime_force_suspend(dev); 7162 if (ret) { 7163 mutex_unlock(&priv->lock); 7164 return ret; 7165 } 7166 } 7167 7168 mutex_unlock(&priv->lock); 7169 7170 if (priv->dma_cap.fpesel) { 7171 /* Disable FPE */ 7172 stmmac_fpe_configure(priv, priv->ioaddr, 7173 priv->plat->tx_queues_to_use, 7174 priv->plat->rx_queues_to_use, false); 7175 7176 stmmac_fpe_handshake(priv, false); 7177 } 7178 7179 priv->speed = SPEED_UNKNOWN; 7180 return 0; 7181 } 7182 EXPORT_SYMBOL_GPL(stmmac_suspend); 7183 7184 /** 7185 * stmmac_reset_queues_param - reset queue parameters 7186 * @priv: device pointer 7187 */ 7188 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 7189 { 7190 u32 rx_cnt = priv->plat->rx_queues_to_use; 7191 u32 tx_cnt = priv->plat->tx_queues_to_use; 7192 u32 queue; 7193 7194 for (queue = 0; queue < rx_cnt; queue++) { 7195 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 7196 7197 rx_q->cur_rx = 0; 7198 rx_q->dirty_rx = 0; 7199 } 7200 7201 for (queue = 0; queue < tx_cnt; queue++) { 7202 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 7203 7204 tx_q->cur_tx = 0; 7205 tx_q->dirty_tx = 0; 7206 tx_q->mss = 0; 7207 7208 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 7209 } 7210 } 7211 7212 /** 7213 * stmmac_resume - resume callback 7214 * @dev: device pointer 7215 * Description: when resume this function is invoked to setup the DMA and CORE 7216 * in a usable state. 7217 */ 7218 int stmmac_resume(struct device *dev) 7219 { 7220 struct net_device *ndev = dev_get_drvdata(dev); 7221 struct stmmac_priv *priv = netdev_priv(ndev); 7222 int ret; 7223 7224 if (!netif_running(ndev)) 7225 return 0; 7226 7227 /* Power Down bit, into the PM register, is cleared 7228 * automatically as soon as a magic packet or a Wake-up frame 7229 * is received. Anyway, it's better to manually clear 7230 * this bit because it can generate problems while resuming 7231 * from another devices (e.g. serial console). 7232 */ 7233 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 7234 mutex_lock(&priv->lock); 7235 stmmac_pmt(priv, priv->hw, 0); 7236 mutex_unlock(&priv->lock); 7237 priv->irq_wake = 0; 7238 } else { 7239 pinctrl_pm_select_default_state(priv->device); 7240 /* enable the clk previously disabled */ 7241 ret = pm_runtime_force_resume(dev); 7242 if (ret) 7243 return ret; 7244 if (priv->plat->clk_ptp_ref) 7245 clk_prepare_enable(priv->plat->clk_ptp_ref); 7246 /* reset the phy so that it's ready */ 7247 if (priv->mii) 7248 stmmac_mdio_reset(priv->mii); 7249 } 7250 7251 if (priv->plat->serdes_powerup) { 7252 ret = priv->plat->serdes_powerup(ndev, 7253 priv->plat->bsp_priv); 7254 7255 if (ret < 0) 7256 return ret; 7257 } 7258 7259 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 7260 rtnl_lock(); 7261 phylink_start(priv->phylink); 7262 /* We may have called phylink_speed_down before */ 7263 phylink_speed_up(priv->phylink); 7264 rtnl_unlock(); 7265 } 7266 7267 rtnl_lock(); 7268 mutex_lock(&priv->lock); 7269 7270 stmmac_reset_queues_param(priv); 7271 7272 stmmac_free_tx_skbufs(priv); 7273 stmmac_clear_descriptors(priv); 7274 7275 stmmac_hw_setup(ndev, false); 7276 stmmac_init_coalesce(priv); 7277 stmmac_set_rx_mode(ndev); 7278 7279 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 7280 7281 stmmac_enable_all_queues(priv); 7282 7283 mutex_unlock(&priv->lock); 7284 rtnl_unlock(); 7285 7286 phylink_mac_change(priv->phylink, true); 7287 7288 netif_device_attach(ndev); 7289 7290 return 0; 7291 } 7292 EXPORT_SYMBOL_GPL(stmmac_resume); 7293 7294 #ifndef MODULE 7295 static int __init stmmac_cmdline_opt(char *str) 7296 { 7297 char *opt; 7298 7299 if (!str || !*str) 7300 return -EINVAL; 7301 while ((opt = strsep(&str, ",")) != NULL) { 7302 if (!strncmp(opt, "debug:", 6)) { 7303 if (kstrtoint(opt + 6, 0, &debug)) 7304 goto err; 7305 } else if (!strncmp(opt, "phyaddr:", 8)) { 7306 if (kstrtoint(opt + 8, 0, &phyaddr)) 7307 goto err; 7308 } else if (!strncmp(opt, "buf_sz:", 7)) { 7309 if (kstrtoint(opt + 7, 0, &buf_sz)) 7310 goto err; 7311 } else if (!strncmp(opt, "tc:", 3)) { 7312 if (kstrtoint(opt + 3, 0, &tc)) 7313 goto err; 7314 } else if (!strncmp(opt, "watchdog:", 9)) { 7315 if (kstrtoint(opt + 9, 0, &watchdog)) 7316 goto err; 7317 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 7318 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 7319 goto err; 7320 } else if (!strncmp(opt, "pause:", 6)) { 7321 if (kstrtoint(opt + 6, 0, &pause)) 7322 goto err; 7323 } else if (!strncmp(opt, "eee_timer:", 10)) { 7324 if (kstrtoint(opt + 10, 0, &eee_timer)) 7325 goto err; 7326 } else if (!strncmp(opt, "chain_mode:", 11)) { 7327 if (kstrtoint(opt + 11, 0, &chain_mode)) 7328 goto err; 7329 } 7330 } 7331 return 0; 7332 7333 err: 7334 pr_err("%s: ERROR broken module parameter conversion", __func__); 7335 return -EINVAL; 7336 } 7337 7338 __setup("stmmaceth=", stmmac_cmdline_opt); 7339 #endif /* MODULE */ 7340 7341 static int __init stmmac_init(void) 7342 { 7343 #ifdef CONFIG_DEBUG_FS 7344 /* Create debugfs main directory if it doesn't exist yet */ 7345 if (!stmmac_fs_dir) 7346 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 7347 register_netdevice_notifier(&stmmac_notifier); 7348 #endif 7349 7350 return 0; 7351 } 7352 7353 static void __exit stmmac_exit(void) 7354 { 7355 #ifdef CONFIG_DEBUG_FS 7356 unregister_netdevice_notifier(&stmmac_notifier); 7357 debugfs_remove_recursive(stmmac_fs_dir); 7358 #endif 7359 } 7360 7361 module_init(stmmac_init) 7362 module_exit(stmmac_exit) 7363 7364 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 7365 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 7366 MODULE_LICENSE("GPL"); 7367