1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #ifdef CONFIG_STMMAC_DEBUG_FS 47 #include <linux/debugfs.h> 48 #include <linux/seq_file.h> 49 #endif 50 #include "stmmac.h" 51 52 #undef STMMAC_DEBUG 53 /*#define STMMAC_DEBUG*/ 54 #ifdef STMMAC_DEBUG 55 #define DBG(nlevel, klevel, fmt, args...) \ 56 ((void)(netif_msg_##nlevel(priv) && \ 57 printk(KERN_##klevel fmt, ## args))) 58 #else 59 #define DBG(nlevel, klevel, fmt, args...) do { } while (0) 60 #endif 61 62 #undef STMMAC_RX_DEBUG 63 /*#define STMMAC_RX_DEBUG*/ 64 #ifdef STMMAC_RX_DEBUG 65 #define RX_DBG(fmt, args...) printk(fmt, ## args) 66 #else 67 #define RX_DBG(fmt, args...) do { } while (0) 68 #endif 69 70 #undef STMMAC_XMIT_DEBUG 71 /*#define STMMAC_XMIT_DEBUG*/ 72 #ifdef STMMAC_XMIT_DEBUG 73 #define TX_DBG(fmt, args...) printk(fmt, ## args) 74 #else 75 #define TX_DBG(fmt, args...) do { } while (0) 76 #endif 77 78 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 79 #define JUMBO_LEN 9000 80 81 /* Module parameters */ 82 #define TX_TIMEO 5000 /* default 5 seconds */ 83 static int watchdog = TX_TIMEO; 84 module_param(watchdog, int, S_IRUGO | S_IWUSR); 85 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); 86 87 static int debug = -1; /* -1: default, 0: no output, 16: all */ 88 module_param(debug, int, S_IRUGO | S_IWUSR); 89 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); 90 91 int phyaddr = -1; 92 module_param(phyaddr, int, S_IRUGO); 93 MODULE_PARM_DESC(phyaddr, "Physical device address"); 94 95 #define DMA_TX_SIZE 256 96 static int dma_txsize = DMA_TX_SIZE; 97 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 98 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 99 100 #define DMA_RX_SIZE 256 101 static int dma_rxsize = DMA_RX_SIZE; 102 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 103 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 104 105 static int flow_ctrl = FLOW_OFF; 106 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 107 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 108 109 static int pause = PAUSE_TIME; 110 module_param(pause, int, S_IRUGO | S_IWUSR); 111 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 112 113 #define TC_DEFAULT 64 114 static int tc = TC_DEFAULT; 115 module_param(tc, int, S_IRUGO | S_IWUSR); 116 MODULE_PARM_DESC(tc, "DMA threshold control value"); 117 118 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB 119 static int buf_sz = DMA_BUFFER_SIZE; 120 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 121 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 122 123 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 124 NETIF_MSG_LINK | NETIF_MSG_IFUP | 125 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 126 127 #define STMMAC_DEFAULT_LPI_TIMER 1000 128 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 129 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 130 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 131 #define STMMAC_LPI_TIMER(x) (jiffies + msecs_to_jiffies(x)) 132 133 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 134 135 #ifdef CONFIG_STMMAC_DEBUG_FS 136 static int stmmac_init_fs(struct net_device *dev); 137 static void stmmac_exit_fs(void); 138 #endif 139 140 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 141 142 /** 143 * stmmac_verify_args - verify the driver parameters. 144 * Description: it verifies if some wrong parameter is passed to the driver. 145 * Note that wrong parameters are replaced with the default values. 146 */ 147 static void stmmac_verify_args(void) 148 { 149 if (unlikely(watchdog < 0)) 150 watchdog = TX_TIMEO; 151 if (unlikely(dma_rxsize < 0)) 152 dma_rxsize = DMA_RX_SIZE; 153 if (unlikely(dma_txsize < 0)) 154 dma_txsize = DMA_TX_SIZE; 155 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) 156 buf_sz = DMA_BUFFER_SIZE; 157 if (unlikely(flow_ctrl > 1)) 158 flow_ctrl = FLOW_AUTO; 159 else if (likely(flow_ctrl < 0)) 160 flow_ctrl = FLOW_OFF; 161 if (unlikely((pause < 0) || (pause > 0xffff))) 162 pause = PAUSE_TIME; 163 if (eee_timer < 0) 164 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 165 } 166 167 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 168 { 169 u32 clk_rate; 170 171 clk_rate = clk_get_rate(priv->stmmac_clk); 172 173 /* Platform provided default clk_csr would be assumed valid 174 * for all other cases except for the below mentioned ones. */ 175 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 176 if (clk_rate < CSR_F_35M) 177 priv->clk_csr = STMMAC_CSR_20_35M; 178 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 179 priv->clk_csr = STMMAC_CSR_35_60M; 180 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 181 priv->clk_csr = STMMAC_CSR_60_100M; 182 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 183 priv->clk_csr = STMMAC_CSR_100_150M; 184 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 185 priv->clk_csr = STMMAC_CSR_150_250M; 186 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 187 priv->clk_csr = STMMAC_CSR_250_300M; 188 } /* For values higher than the IEEE 802.3 specified frequency 189 * we can not estimate the proper divider as it is not known 190 * the frequency of clk_csr_i. So we do not change the default 191 * divider. */ 192 } 193 194 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) 195 static void print_pkt(unsigned char *buf, int len) 196 { 197 int j; 198 pr_info("len = %d byte, buf addr: 0x%p", len, buf); 199 for (j = 0; j < len; j++) { 200 if ((j % 16) == 0) 201 pr_info("\n %03x:", j); 202 pr_info(" %02x", buf[j]); 203 } 204 pr_info("\n"); 205 } 206 #endif 207 208 /* minimum number of free TX descriptors required to wake up TX process */ 209 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 210 211 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 212 { 213 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 214 } 215 216 /* On some ST platforms, some HW system configuraton registers have to be 217 * set according to the link speed negotiated. 218 */ 219 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 220 { 221 struct phy_device *phydev = priv->phydev; 222 223 if (likely(priv->plat->fix_mac_speed)) 224 priv->plat->fix_mac_speed(priv->plat->bsp_priv, 225 phydev->speed); 226 } 227 228 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 229 { 230 /* Check and enter in LPI mode */ 231 if ((priv->dirty_tx == priv->cur_tx) && 232 (priv->tx_path_in_lpi_mode == false)) 233 priv->hw->mac->set_eee_mode(priv->ioaddr); 234 } 235 236 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 237 { 238 /* Exit and disable EEE in case of we are are in LPI state. */ 239 priv->hw->mac->reset_eee_mode(priv->ioaddr); 240 del_timer_sync(&priv->eee_ctrl_timer); 241 priv->tx_path_in_lpi_mode = false; 242 } 243 244 /** 245 * stmmac_eee_ctrl_timer 246 * @arg : data hook 247 * Description: 248 * If there is no data transfer and if we are not in LPI state, 249 * then MAC Transmitter can be moved to LPI state. 250 */ 251 static void stmmac_eee_ctrl_timer(unsigned long arg) 252 { 253 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 254 255 stmmac_enable_eee_mode(priv); 256 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer)); 257 } 258 259 /** 260 * stmmac_eee_init 261 * @priv: private device pointer 262 * Description: 263 * If the EEE support has been enabled while configuring the driver, 264 * if the GMAC actually supports the EEE (from the HW cap reg) and the 265 * phy can also manage EEE, so enable the LPI state and start the timer 266 * to verify if the tx path can enter in LPI state. 267 */ 268 bool stmmac_eee_init(struct stmmac_priv *priv) 269 { 270 bool ret = false; 271 272 /* MAC core supports the EEE feature. */ 273 if (priv->dma_cap.eee) { 274 /* Check if the PHY supports EEE */ 275 if (phy_init_eee(priv->phydev, 1)) 276 goto out; 277 278 priv->eee_active = 1; 279 init_timer(&priv->eee_ctrl_timer); 280 priv->eee_ctrl_timer.function = stmmac_eee_ctrl_timer; 281 priv->eee_ctrl_timer.data = (unsigned long)priv; 282 priv->eee_ctrl_timer.expires = STMMAC_LPI_TIMER(eee_timer); 283 add_timer(&priv->eee_ctrl_timer); 284 285 priv->hw->mac->set_eee_timer(priv->ioaddr, 286 STMMAC_DEFAULT_LIT_LS_TIMER, 287 priv->tx_lpi_timer); 288 289 pr_info("stmmac: Energy-Efficient Ethernet initialized\n"); 290 291 ret = true; 292 } 293 out: 294 return ret; 295 } 296 297 static void stmmac_eee_adjust(struct stmmac_priv *priv) 298 { 299 /* When the EEE has been already initialised we have to 300 * modify the PLS bit in the LPI ctrl & status reg according 301 * to the PHY link status. For this reason. 302 */ 303 if (priv->eee_enabled) 304 priv->hw->mac->set_eee_pls(priv->ioaddr, priv->phydev->link); 305 } 306 307 /** 308 * stmmac_adjust_link 309 * @dev: net device structure 310 * Description: it adjusts the link parameters. 311 */ 312 static void stmmac_adjust_link(struct net_device *dev) 313 { 314 struct stmmac_priv *priv = netdev_priv(dev); 315 struct phy_device *phydev = priv->phydev; 316 unsigned long flags; 317 int new_state = 0; 318 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 319 320 if (phydev == NULL) 321 return; 322 323 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", 324 phydev->addr, phydev->link); 325 326 spin_lock_irqsave(&priv->lock, flags); 327 328 if (phydev->link) { 329 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 330 331 /* Now we make sure that we can be in full duplex mode. 332 * If not, we operate in half-duplex mode. */ 333 if (phydev->duplex != priv->oldduplex) { 334 new_state = 1; 335 if (!(phydev->duplex)) 336 ctrl &= ~priv->hw->link.duplex; 337 else 338 ctrl |= priv->hw->link.duplex; 339 priv->oldduplex = phydev->duplex; 340 } 341 /* Flow Control operation */ 342 if (phydev->pause) 343 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, 344 fc, pause_time); 345 346 if (phydev->speed != priv->speed) { 347 new_state = 1; 348 switch (phydev->speed) { 349 case 1000: 350 if (likely(priv->plat->has_gmac)) 351 ctrl &= ~priv->hw->link.port; 352 stmmac_hw_fix_mac_speed(priv); 353 break; 354 case 100: 355 case 10: 356 if (priv->plat->has_gmac) { 357 ctrl |= priv->hw->link.port; 358 if (phydev->speed == SPEED_100) { 359 ctrl |= priv->hw->link.speed; 360 } else { 361 ctrl &= ~(priv->hw->link.speed); 362 } 363 } else { 364 ctrl &= ~priv->hw->link.port; 365 } 366 stmmac_hw_fix_mac_speed(priv); 367 break; 368 default: 369 if (netif_msg_link(priv)) 370 pr_warning("%s: Speed (%d) is not 10" 371 " or 100!\n", dev->name, phydev->speed); 372 break; 373 } 374 375 priv->speed = phydev->speed; 376 } 377 378 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 379 380 if (!priv->oldlink) { 381 new_state = 1; 382 priv->oldlink = 1; 383 } 384 } else if (priv->oldlink) { 385 new_state = 1; 386 priv->oldlink = 0; 387 priv->speed = 0; 388 priv->oldduplex = -1; 389 } 390 391 if (new_state && netif_msg_link(priv)) 392 phy_print_status(phydev); 393 394 stmmac_eee_adjust(priv); 395 396 spin_unlock_irqrestore(&priv->lock, flags); 397 398 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); 399 } 400 401 /** 402 * stmmac_init_phy - PHY initialization 403 * @dev: net device structure 404 * Description: it initializes the driver's PHY state, and attaches the PHY 405 * to the mac driver. 406 * Return value: 407 * 0 on success 408 */ 409 static int stmmac_init_phy(struct net_device *dev) 410 { 411 struct stmmac_priv *priv = netdev_priv(dev); 412 struct phy_device *phydev; 413 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 414 char bus_id[MII_BUS_ID_SIZE]; 415 int interface = priv->plat->interface; 416 priv->oldlink = 0; 417 priv->speed = 0; 418 priv->oldduplex = -1; 419 420 if (priv->plat->phy_bus_name) 421 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 422 priv->plat->phy_bus_name, priv->plat->bus_id); 423 else 424 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 425 priv->plat->bus_id); 426 427 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 428 priv->plat->phy_addr); 429 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id_fmt); 430 431 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 0, 432 interface); 433 434 if (IS_ERR(phydev)) { 435 pr_err("%s: Could not attach to PHY\n", dev->name); 436 return PTR_ERR(phydev); 437 } 438 439 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 440 if ((interface == PHY_INTERFACE_MODE_MII) || 441 (interface == PHY_INTERFACE_MODE_RMII)) 442 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 443 SUPPORTED_1000baseT_Full); 444 445 /* 446 * Broken HW is sometimes missing the pull-up resistor on the 447 * MDIO line, which results in reads to non-existent devices returning 448 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 449 * device as well. 450 * Note: phydev->phy_id is the result of reading the UID PHY registers. 451 */ 452 if (phydev->phy_id == 0) { 453 phy_disconnect(phydev); 454 return -ENODEV; 455 } 456 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 457 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 458 459 priv->phydev = phydev; 460 461 return 0; 462 } 463 464 /** 465 * display_ring 466 * @p: pointer to the ring. 467 * @size: size of the ring. 468 * Description: display all the descriptors within the ring. 469 */ 470 static void display_ring(struct dma_desc *p, int size) 471 { 472 struct tmp_s { 473 u64 a; 474 unsigned int b; 475 unsigned int c; 476 }; 477 int i; 478 for (i = 0; i < size; i++) { 479 struct tmp_s *x = (struct tmp_s *)(p + i); 480 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 481 i, (unsigned int)virt_to_phys(&p[i]), 482 (unsigned int)(x->a), (unsigned int)((x->a) >> 32), 483 x->b, x->c); 484 pr_info("\n"); 485 } 486 } 487 488 static int stmmac_set_bfsize(int mtu, int bufsize) 489 { 490 int ret = bufsize; 491 492 if (mtu >= BUF_SIZE_4KiB) 493 ret = BUF_SIZE_8KiB; 494 else if (mtu >= BUF_SIZE_2KiB) 495 ret = BUF_SIZE_4KiB; 496 else if (mtu >= DMA_BUFFER_SIZE) 497 ret = BUF_SIZE_2KiB; 498 else 499 ret = DMA_BUFFER_SIZE; 500 501 return ret; 502 } 503 504 /** 505 * init_dma_desc_rings - init the RX/TX descriptor rings 506 * @dev: net device structure 507 * Description: this function initializes the DMA RX/TX descriptors 508 * and allocates the socket buffers. It suppors the chained and ring 509 * modes. 510 */ 511 static void init_dma_desc_rings(struct net_device *dev) 512 { 513 int i; 514 struct stmmac_priv *priv = netdev_priv(dev); 515 struct sk_buff *skb; 516 unsigned int txsize = priv->dma_tx_size; 517 unsigned int rxsize = priv->dma_rx_size; 518 unsigned int bfsize; 519 int dis_ic = 0; 520 int des3_as_data_buf = 0; 521 522 /* Set the max buffer size according to the DESC mode 523 * and the MTU. Note that RING mode allows 16KiB bsize. */ 524 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); 525 526 if (bfsize == BUF_SIZE_16KiB) 527 des3_as_data_buf = 1; 528 else 529 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 530 531 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", 532 txsize, rxsize, bfsize); 533 534 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); 535 priv->rx_skbuff = 536 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); 537 priv->dma_rx = 538 (struct dma_desc *)dma_alloc_coherent(priv->device, 539 rxsize * 540 sizeof(struct dma_desc), 541 &priv->dma_rx_phy, 542 GFP_KERNEL); 543 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, 544 GFP_KERNEL); 545 priv->dma_tx = 546 (struct dma_desc *)dma_alloc_coherent(priv->device, 547 txsize * 548 sizeof(struct dma_desc), 549 &priv->dma_tx_phy, 550 GFP_KERNEL); 551 552 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { 553 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); 554 return; 555 } 556 557 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " 558 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", 559 dev->name, priv->dma_rx, priv->dma_tx, 560 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); 561 562 /* RX INITIALIZATION */ 563 DBG(probe, INFO, "stmmac: SKB addresses:\n" 564 "skb\t\tskb data\tdma data\n"); 565 566 for (i = 0; i < rxsize; i++) { 567 struct dma_desc *p = priv->dma_rx + i; 568 569 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, 570 GFP_KERNEL); 571 if (unlikely(skb == NULL)) { 572 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 573 break; 574 } 575 skb_reserve(skb, NET_IP_ALIGN); 576 priv->rx_skbuff[i] = skb; 577 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 578 bfsize, DMA_FROM_DEVICE); 579 580 p->des2 = priv->rx_skbuff_dma[i]; 581 582 priv->hw->ring->init_desc3(des3_as_data_buf, p); 583 584 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 585 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); 586 } 587 priv->cur_rx = 0; 588 priv->dirty_rx = (unsigned int)(i - rxsize); 589 priv->dma_buf_sz = bfsize; 590 buf_sz = bfsize; 591 592 /* TX INITIALIZATION */ 593 for (i = 0; i < txsize; i++) { 594 priv->tx_skbuff[i] = NULL; 595 priv->dma_tx[i].des2 = 0; 596 } 597 598 /* In case of Chained mode this sets the des3 to the next 599 * element in the chain */ 600 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); 601 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); 602 603 priv->dirty_tx = 0; 604 priv->cur_tx = 0; 605 606 if (priv->use_riwt) 607 dis_ic = 1; 608 /* Clear the Rx/Tx descriptors */ 609 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); 610 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); 611 612 if (netif_msg_hw(priv)) { 613 pr_info("RX descriptor ring:\n"); 614 display_ring(priv->dma_rx, rxsize); 615 pr_info("TX descriptor ring:\n"); 616 display_ring(priv->dma_tx, txsize); 617 } 618 } 619 620 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 621 { 622 int i; 623 624 for (i = 0; i < priv->dma_rx_size; i++) { 625 if (priv->rx_skbuff[i]) { 626 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 627 priv->dma_buf_sz, DMA_FROM_DEVICE); 628 dev_kfree_skb_any(priv->rx_skbuff[i]); 629 } 630 priv->rx_skbuff[i] = NULL; 631 } 632 } 633 634 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 635 { 636 int i; 637 638 for (i = 0; i < priv->dma_tx_size; i++) { 639 if (priv->tx_skbuff[i] != NULL) { 640 struct dma_desc *p = priv->dma_tx + i; 641 if (p->des2) 642 dma_unmap_single(priv->device, p->des2, 643 priv->hw->desc->get_tx_len(p), 644 DMA_TO_DEVICE); 645 dev_kfree_skb_any(priv->tx_skbuff[i]); 646 priv->tx_skbuff[i] = NULL; 647 } 648 } 649 } 650 651 static void free_dma_desc_resources(struct stmmac_priv *priv) 652 { 653 /* Release the DMA TX/RX socket buffers */ 654 dma_free_rx_skbufs(priv); 655 dma_free_tx_skbufs(priv); 656 657 /* Free the region of consistent memory previously allocated for 658 * the DMA */ 659 dma_free_coherent(priv->device, 660 priv->dma_tx_size * sizeof(struct dma_desc), 661 priv->dma_tx, priv->dma_tx_phy); 662 dma_free_coherent(priv->device, 663 priv->dma_rx_size * sizeof(struct dma_desc), 664 priv->dma_rx, priv->dma_rx_phy); 665 kfree(priv->rx_skbuff_dma); 666 kfree(priv->rx_skbuff); 667 kfree(priv->tx_skbuff); 668 } 669 670 /** 671 * stmmac_dma_operation_mode - HW DMA operation mode 672 * @priv : pointer to the private device structure. 673 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 674 * or Store-And-Forward capability. 675 */ 676 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 677 { 678 if (likely(priv->plat->force_sf_dma_mode || 679 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { 680 /* 681 * In case of GMAC, SF mode can be enabled 682 * to perform the TX COE in HW. This depends on: 683 * 1) TX COE if actually supported 684 * 2) There is no bugged Jumbo frame support 685 * that needs to not insert csum in the TDES. 686 */ 687 priv->hw->dma->dma_mode(priv->ioaddr, 688 SF_DMA_MODE, SF_DMA_MODE); 689 tc = SF_DMA_MODE; 690 } else 691 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 692 } 693 694 /** 695 * stmmac_tx_clean: 696 * @priv: private data pointer 697 * Description: it reclaims resources after transmission completes. 698 */ 699 static void stmmac_tx_clean(struct stmmac_priv *priv) 700 { 701 unsigned int txsize = priv->dma_tx_size; 702 703 spin_lock(&priv->tx_lock); 704 705 priv->xstats.tx_clean++; 706 707 while (priv->dirty_tx != priv->cur_tx) { 708 int last; 709 unsigned int entry = priv->dirty_tx % txsize; 710 struct sk_buff *skb = priv->tx_skbuff[entry]; 711 struct dma_desc *p = priv->dma_tx + entry; 712 713 /* Check if the descriptor is owned by the DMA. */ 714 if (priv->hw->desc->get_tx_owner(p)) 715 break; 716 717 /* Verify tx error by looking at the last segment */ 718 last = priv->hw->desc->get_tx_ls(p); 719 if (likely(last)) { 720 int tx_error = 721 priv->hw->desc->tx_status(&priv->dev->stats, 722 &priv->xstats, p, 723 priv->ioaddr); 724 if (likely(tx_error == 0)) { 725 priv->dev->stats.tx_packets++; 726 priv->xstats.tx_pkt_n++; 727 } else 728 priv->dev->stats.tx_errors++; 729 } 730 TX_DBG("%s: curr %d, dirty %d\n", __func__, 731 priv->cur_tx, priv->dirty_tx); 732 733 if (likely(p->des2)) 734 dma_unmap_single(priv->device, p->des2, 735 priv->hw->desc->get_tx_len(p), 736 DMA_TO_DEVICE); 737 priv->hw->ring->clean_desc3(p); 738 739 if (likely(skb != NULL)) { 740 dev_kfree_skb(skb); 741 priv->tx_skbuff[entry] = NULL; 742 } 743 744 priv->hw->desc->release_tx_desc(p); 745 746 priv->dirty_tx++; 747 } 748 if (unlikely(netif_queue_stopped(priv->dev) && 749 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 750 netif_tx_lock(priv->dev); 751 if (netif_queue_stopped(priv->dev) && 752 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 753 TX_DBG("%s: restart transmit\n", __func__); 754 netif_wake_queue(priv->dev); 755 } 756 netif_tx_unlock(priv->dev); 757 } 758 759 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 760 stmmac_enable_eee_mode(priv); 761 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_TIMER(eee_timer)); 762 } 763 spin_unlock(&priv->tx_lock); 764 } 765 766 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 767 { 768 priv->hw->dma->enable_dma_irq(priv->ioaddr); 769 } 770 771 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 772 { 773 priv->hw->dma->disable_dma_irq(priv->ioaddr); 774 } 775 776 777 /** 778 * stmmac_tx_err: 779 * @priv: pointer to the private device structure 780 * Description: it cleans the descriptors and restarts the transmission 781 * in case of errors. 782 */ 783 static void stmmac_tx_err(struct stmmac_priv *priv) 784 { 785 netif_stop_queue(priv->dev); 786 787 priv->hw->dma->stop_tx(priv->ioaddr); 788 dma_free_tx_skbufs(priv); 789 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 790 priv->dirty_tx = 0; 791 priv->cur_tx = 0; 792 priv->hw->dma->start_tx(priv->ioaddr); 793 794 priv->dev->stats.tx_errors++; 795 netif_wake_queue(priv->dev); 796 } 797 798 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 799 { 800 int status; 801 802 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 803 if (likely((status & handle_rx)) || (status & handle_tx)) { 804 if (likely(napi_schedule_prep(&priv->napi))) { 805 stmmac_disable_dma_irq(priv); 806 __napi_schedule(&priv->napi); 807 } 808 } 809 if (unlikely(status & tx_hard_error_bump_tc)) { 810 /* Try to bump up the dma threshold on this failure */ 811 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 812 tc += 64; 813 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 814 priv->xstats.threshold = tc; 815 } 816 } else if (unlikely(status == tx_hard_error)) 817 stmmac_tx_err(priv); 818 } 819 820 static void stmmac_mmc_setup(struct stmmac_priv *priv) 821 { 822 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 823 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 824 825 /* Mask MMC irq, counters are managed in SW and registers 826 * are cleared on each READ eventually. */ 827 dwmac_mmc_intr_all_mask(priv->ioaddr); 828 829 if (priv->dma_cap.rmon) { 830 dwmac_mmc_ctrl(priv->ioaddr, mode); 831 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 832 } else 833 pr_info(" No MAC Management Counters available\n"); 834 } 835 836 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 837 { 838 u32 hwid = priv->hw->synopsys_uid; 839 840 /* Only check valid Synopsys Id because old MAC chips 841 * have no HW registers where get the ID */ 842 if (likely(hwid)) { 843 u32 uid = ((hwid & 0x0000ff00) >> 8); 844 u32 synid = (hwid & 0x000000ff); 845 846 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 847 uid, synid); 848 849 return synid; 850 } 851 return 0; 852 } 853 854 /** 855 * stmmac_selec_desc_mode 856 * @priv : private structure 857 * Description: select the Enhanced/Alternate or Normal descriptors 858 */ 859 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 860 { 861 if (priv->plat->enh_desc) { 862 pr_info(" Enhanced/Alternate descriptors\n"); 863 priv->hw->desc = &enh_desc_ops; 864 } else { 865 pr_info(" Normal descriptors\n"); 866 priv->hw->desc = &ndesc_ops; 867 } 868 } 869 870 /** 871 * stmmac_get_hw_features 872 * @priv : private device pointer 873 * Description: 874 * new GMAC chip generations have a new register to indicate the 875 * presence of the optional feature/functions. 876 * This can be also used to override the value passed through the 877 * platform and necessary for old MAC10/100 and GMAC chips. 878 */ 879 static int stmmac_get_hw_features(struct stmmac_priv *priv) 880 { 881 u32 hw_cap = 0; 882 883 if (priv->hw->dma->get_hw_feature) { 884 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 885 886 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 887 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 888 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 889 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 890 priv->dma_cap.multi_addr = 891 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; 892 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 893 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 894 priv->dma_cap.pmt_remote_wake_up = 895 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 896 priv->dma_cap.pmt_magic_frame = 897 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 898 /* MMC */ 899 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 900 /* IEEE 1588-2002*/ 901 priv->dma_cap.time_stamp = 902 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 903 /* IEEE 1588-2008*/ 904 priv->dma_cap.atime_stamp = 905 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 906 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 907 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 908 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 909 /* TX and RX csum */ 910 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 911 priv->dma_cap.rx_coe_type1 = 912 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 913 priv->dma_cap.rx_coe_type2 = 914 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 915 priv->dma_cap.rxfifo_over_2048 = 916 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 917 /* TX and RX number of channels */ 918 priv->dma_cap.number_rx_channel = 919 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 920 priv->dma_cap.number_tx_channel = 921 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 922 /* Alternate (enhanced) DESC mode*/ 923 priv->dma_cap.enh_desc = 924 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 925 } 926 927 return hw_cap; 928 } 929 930 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 931 { 932 /* verify if the MAC address is valid, in case of failures it 933 * generates a random MAC address */ 934 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 935 priv->hw->mac->get_umac_addr((void __iomem *) 936 priv->dev->base_addr, 937 priv->dev->dev_addr, 0); 938 if (!is_valid_ether_addr(priv->dev->dev_addr)) 939 eth_hw_addr_random(priv->dev); 940 } 941 pr_warning("%s: device MAC address %pM\n", priv->dev->name, 942 priv->dev->dev_addr); 943 } 944 945 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 946 { 947 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 948 int mixed_burst = 0; 949 950 /* Some DMA parameters can be passed from the platform; 951 * in case of these are not passed we keep a default 952 * (good for all the chips) and init the DMA! */ 953 if (priv->plat->dma_cfg) { 954 pbl = priv->plat->dma_cfg->pbl; 955 fixed_burst = priv->plat->dma_cfg->fixed_burst; 956 mixed_burst = priv->plat->dma_cfg->mixed_burst; 957 burst_len = priv->plat->dma_cfg->burst_len; 958 } 959 960 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 961 burst_len, priv->dma_tx_phy, 962 priv->dma_rx_phy); 963 } 964 965 /** 966 * stmmac_tx_timer: 967 * @data: data pointer 968 * Description: 969 * This is the timer handler to directly invoke the stmmac_tx_clean. 970 */ 971 static void stmmac_tx_timer(unsigned long data) 972 { 973 struct stmmac_priv *priv = (struct stmmac_priv *)data; 974 975 stmmac_tx_clean(priv); 976 } 977 978 /** 979 * stmmac_tx_timer: 980 * @priv: private data structure 981 * Description: 982 * This inits the transmit coalesce parameters: i.e. timer rate, 983 * timer handler and default threshold used for enabling the 984 * interrupt on completion bit. 985 */ 986 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 987 { 988 priv->tx_coal_frames = STMMAC_TX_FRAMES; 989 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 990 init_timer(&priv->txtimer); 991 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 992 priv->txtimer.data = (unsigned long)priv; 993 priv->txtimer.function = stmmac_tx_timer; 994 add_timer(&priv->txtimer); 995 } 996 997 /** 998 * stmmac_open - open entry point of the driver 999 * @dev : pointer to the device structure. 1000 * Description: 1001 * This function is the open entry point of the driver. 1002 * Return value: 1003 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1004 * file on failure. 1005 */ 1006 static int stmmac_open(struct net_device *dev) 1007 { 1008 struct stmmac_priv *priv = netdev_priv(dev); 1009 int ret; 1010 1011 clk_prepare_enable(priv->stmmac_clk); 1012 1013 stmmac_check_ether_addr(priv); 1014 1015 ret = stmmac_init_phy(dev); 1016 if (unlikely(ret)) { 1017 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); 1018 goto open_error; 1019 } 1020 1021 /* Create and initialize the TX/RX descriptors chains. */ 1022 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1023 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1024 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1025 init_dma_desc_rings(dev); 1026 1027 /* DMA initialization and SW reset */ 1028 ret = stmmac_init_dma_engine(priv); 1029 if (ret < 0) { 1030 pr_err("%s: DMA initialization failed\n", __func__); 1031 goto open_error; 1032 } 1033 1034 /* Copy the MAC addr into the HW */ 1035 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); 1036 1037 /* If required, perform hw setup of the bus. */ 1038 if (priv->plat->bus_setup) 1039 priv->plat->bus_setup(priv->ioaddr); 1040 1041 /* Initialize the MAC Core */ 1042 priv->hw->mac->core_init(priv->ioaddr); 1043 1044 /* Request the IRQ lines */ 1045 ret = request_irq(dev->irq, stmmac_interrupt, 1046 IRQF_SHARED, dev->name, dev); 1047 if (unlikely(ret < 0)) { 1048 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1049 __func__, dev->irq, ret); 1050 goto open_error; 1051 } 1052 1053 /* Request the Wake IRQ in case of another line is used for WoL */ 1054 if (priv->wol_irq != dev->irq) { 1055 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1056 IRQF_SHARED, dev->name, dev); 1057 if (unlikely(ret < 0)) { 1058 pr_err("%s: ERROR: allocating the ext WoL IRQ %d " 1059 "(error: %d)\n", __func__, priv->wol_irq, ret); 1060 goto open_error_wolirq; 1061 } 1062 } 1063 1064 /* Request the IRQ lines */ 1065 if (priv->lpi_irq != -ENXIO) { 1066 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1067 dev->name, dev); 1068 if (unlikely(ret < 0)) { 1069 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1070 __func__, priv->lpi_irq, ret); 1071 goto open_error_lpiirq; 1072 } 1073 } 1074 1075 /* Enable the MAC Rx/Tx */ 1076 stmmac_set_mac(priv->ioaddr, true); 1077 1078 /* Set the HW DMA mode and the COE */ 1079 stmmac_dma_operation_mode(priv); 1080 1081 /* Extra statistics */ 1082 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1083 priv->xstats.threshold = tc; 1084 1085 stmmac_mmc_setup(priv); 1086 1087 #ifdef CONFIG_STMMAC_DEBUG_FS 1088 ret = stmmac_init_fs(dev); 1089 if (ret < 0) 1090 pr_warning("%s: failed debugFS registration\n", __func__); 1091 #endif 1092 /* Start the ball rolling... */ 1093 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); 1094 priv->hw->dma->start_tx(priv->ioaddr); 1095 priv->hw->dma->start_rx(priv->ioaddr); 1096 1097 /* Dump DMA/MAC registers */ 1098 if (netif_msg_hw(priv)) { 1099 priv->hw->mac->dump_regs(priv->ioaddr); 1100 priv->hw->dma->dump_regs(priv->ioaddr); 1101 } 1102 1103 if (priv->phydev) 1104 phy_start(priv->phydev); 1105 1106 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS_TIMER; 1107 priv->eee_enabled = stmmac_eee_init(priv); 1108 1109 stmmac_init_tx_coalesce(priv); 1110 1111 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1112 priv->rx_riwt = MAX_DMA_RIWT; 1113 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1114 } 1115 1116 napi_enable(&priv->napi); 1117 netif_start_queue(dev); 1118 1119 return 0; 1120 1121 open_error_lpiirq: 1122 if (priv->wol_irq != dev->irq) 1123 free_irq(priv->wol_irq, dev); 1124 1125 open_error_wolirq: 1126 free_irq(dev->irq, dev); 1127 1128 open_error: 1129 if (priv->phydev) 1130 phy_disconnect(priv->phydev); 1131 1132 clk_disable_unprepare(priv->stmmac_clk); 1133 1134 return ret; 1135 } 1136 1137 /** 1138 * stmmac_release - close entry point of the driver 1139 * @dev : device pointer. 1140 * Description: 1141 * This is the stop entry point of the driver. 1142 */ 1143 static int stmmac_release(struct net_device *dev) 1144 { 1145 struct stmmac_priv *priv = netdev_priv(dev); 1146 1147 if (priv->eee_enabled) 1148 del_timer_sync(&priv->eee_ctrl_timer); 1149 1150 /* Stop and disconnect the PHY */ 1151 if (priv->phydev) { 1152 phy_stop(priv->phydev); 1153 phy_disconnect(priv->phydev); 1154 priv->phydev = NULL; 1155 } 1156 1157 netif_stop_queue(dev); 1158 1159 napi_disable(&priv->napi); 1160 1161 del_timer_sync(&priv->txtimer); 1162 1163 /* Free the IRQ lines */ 1164 free_irq(dev->irq, dev); 1165 if (priv->wol_irq != dev->irq) 1166 free_irq(priv->wol_irq, dev); 1167 if (priv->lpi_irq != -ENXIO) 1168 free_irq(priv->lpi_irq, dev); 1169 1170 /* Stop TX/RX DMA and clear the descriptors */ 1171 priv->hw->dma->stop_tx(priv->ioaddr); 1172 priv->hw->dma->stop_rx(priv->ioaddr); 1173 1174 /* Release and free the Rx/Tx resources */ 1175 free_dma_desc_resources(priv); 1176 1177 /* Disable the MAC Rx/Tx */ 1178 stmmac_set_mac(priv->ioaddr, false); 1179 1180 netif_carrier_off(dev); 1181 1182 #ifdef CONFIG_STMMAC_DEBUG_FS 1183 stmmac_exit_fs(); 1184 #endif 1185 clk_disable_unprepare(priv->stmmac_clk); 1186 1187 return 0; 1188 } 1189 1190 /** 1191 * stmmac_xmit: 1192 * @skb : the socket buffer 1193 * @dev : device pointer 1194 * Description : Tx entry point of the driver. 1195 */ 1196 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1197 { 1198 struct stmmac_priv *priv = netdev_priv(dev); 1199 unsigned int txsize = priv->dma_tx_size; 1200 unsigned int entry; 1201 int i, csum_insertion = 0; 1202 int nfrags = skb_shinfo(skb)->nr_frags; 1203 struct dma_desc *desc, *first; 1204 unsigned int nopaged_len = skb_headlen(skb); 1205 1206 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1207 if (!netif_queue_stopped(dev)) { 1208 netif_stop_queue(dev); 1209 /* This is a hard error, log it. */ 1210 pr_err("%s: BUG! Tx Ring full when queue awake\n", 1211 __func__); 1212 } 1213 return NETDEV_TX_BUSY; 1214 } 1215 1216 spin_lock(&priv->tx_lock); 1217 1218 if (priv->tx_path_in_lpi_mode) 1219 stmmac_disable_eee_mode(priv); 1220 1221 entry = priv->cur_tx % txsize; 1222 1223 #ifdef STMMAC_XMIT_DEBUG 1224 if ((skb->len > ETH_FRAME_LEN) || nfrags) 1225 pr_debug("stmmac xmit: [entry %d]\n" 1226 "\tskb addr %p - len: %d - nopaged_len: %d\n" 1227 "\tn_frags: %d - ip_summed: %d - %s gso\n" 1228 "\ttx_count_frames %d\n", entry, 1229 skb, skb->len, nopaged_len, nfrags, skb->ip_summed, 1230 !skb_is_gso(skb) ? "isn't" : "is", 1231 priv->tx_count_frames); 1232 #endif 1233 1234 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1235 1236 desc = priv->dma_tx + entry; 1237 first = desc; 1238 1239 #ifdef STMMAC_XMIT_DEBUG 1240 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) 1241 pr_debug("\tskb len: %d, nopaged_len: %d,\n" 1242 "\t\tn_frags: %d, ip_summed: %d\n", 1243 skb->len, nopaged_len, nfrags, skb->ip_summed); 1244 #endif 1245 priv->tx_skbuff[entry] = skb; 1246 1247 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { 1248 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); 1249 desc = priv->dma_tx + entry; 1250 } else { 1251 desc->des2 = dma_map_single(priv->device, skb->data, 1252 nopaged_len, DMA_TO_DEVICE); 1253 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1254 csum_insertion); 1255 } 1256 1257 for (i = 0; i < nfrags; i++) { 1258 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1259 int len = skb_frag_size(frag); 1260 1261 entry = (++priv->cur_tx) % txsize; 1262 desc = priv->dma_tx + entry; 1263 1264 TX_DBG("\t[entry %d] segment len: %d\n", entry, len); 1265 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1266 DMA_TO_DEVICE); 1267 priv->tx_skbuff[entry] = NULL; 1268 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); 1269 wmb(); 1270 priv->hw->desc->set_tx_owner(desc); 1271 wmb(); 1272 } 1273 1274 /* Finalize the latest segment. */ 1275 priv->hw->desc->close_tx_desc(desc); 1276 1277 wmb(); 1278 /* According to the coalesce parameter the IC bit for the latest 1279 * segment could be reset and the timer re-started to invoke the 1280 * stmmac_tx function. This approach takes care about the fragments. 1281 */ 1282 priv->tx_count_frames += nfrags + 1; 1283 if (priv->tx_coal_frames > priv->tx_count_frames) { 1284 priv->hw->desc->clear_tx_ic(desc); 1285 priv->xstats.tx_reset_ic_bit++; 1286 TX_DBG("\t[entry %d]: tx_count_frames %d\n", entry, 1287 priv->tx_count_frames); 1288 mod_timer(&priv->txtimer, 1289 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 1290 } else 1291 priv->tx_count_frames = 0; 1292 1293 /* To avoid raise condition */ 1294 priv->hw->desc->set_tx_owner(first); 1295 wmb(); 1296 1297 priv->cur_tx++; 1298 1299 #ifdef STMMAC_XMIT_DEBUG 1300 if (netif_msg_pktdata(priv)) { 1301 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " 1302 "first=%p, nfrags=%d\n", 1303 (priv->cur_tx % txsize), (priv->dirty_tx % txsize), 1304 entry, first, nfrags); 1305 display_ring(priv->dma_tx, txsize); 1306 pr_info(">>> frame to be transmitted: "); 1307 print_pkt(skb->data, skb->len); 1308 } 1309 #endif 1310 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 1311 TX_DBG("%s: stop transmitted packets\n", __func__); 1312 netif_stop_queue(dev); 1313 } 1314 1315 dev->stats.tx_bytes += skb->len; 1316 1317 skb_tx_timestamp(skb); 1318 1319 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 1320 1321 spin_unlock(&priv->tx_lock); 1322 1323 return NETDEV_TX_OK; 1324 } 1325 1326 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 1327 { 1328 unsigned int rxsize = priv->dma_rx_size; 1329 int bfsize = priv->dma_buf_sz; 1330 struct dma_desc *p = priv->dma_rx; 1331 1332 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 1333 unsigned int entry = priv->dirty_rx % rxsize; 1334 if (likely(priv->rx_skbuff[entry] == NULL)) { 1335 struct sk_buff *skb; 1336 1337 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 1338 1339 if (unlikely(skb == NULL)) 1340 break; 1341 1342 priv->rx_skbuff[entry] = skb; 1343 priv->rx_skbuff_dma[entry] = 1344 dma_map_single(priv->device, skb->data, bfsize, 1345 DMA_FROM_DEVICE); 1346 1347 (p + entry)->des2 = priv->rx_skbuff_dma[entry]; 1348 1349 if (unlikely(priv->plat->has_gmac)) 1350 priv->hw->ring->refill_desc3(bfsize, p + entry); 1351 1352 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); 1353 } 1354 wmb(); 1355 priv->hw->desc->set_rx_owner(p + entry); 1356 wmb(); 1357 } 1358 } 1359 1360 static int stmmac_rx(struct stmmac_priv *priv, int limit) 1361 { 1362 unsigned int rxsize = priv->dma_rx_size; 1363 unsigned int entry = priv->cur_rx % rxsize; 1364 unsigned int next_entry; 1365 unsigned int count = 0; 1366 struct dma_desc *p = priv->dma_rx + entry; 1367 struct dma_desc *p_next; 1368 1369 #ifdef STMMAC_RX_DEBUG 1370 if (netif_msg_hw(priv)) { 1371 pr_debug(">>> stmmac_rx: descriptor ring:\n"); 1372 display_ring(priv->dma_rx, rxsize); 1373 } 1374 #endif 1375 while (!priv->hw->desc->get_rx_owner(p)) { 1376 int status; 1377 1378 if (count >= limit) 1379 break; 1380 1381 count++; 1382 1383 next_entry = (++priv->cur_rx) % rxsize; 1384 p_next = priv->dma_rx + next_entry; 1385 prefetch(p_next); 1386 1387 /* read the status of the incoming frame */ 1388 status = (priv->hw->desc->rx_status(&priv->dev->stats, 1389 &priv->xstats, p)); 1390 if (unlikely(status == discard_frame)) 1391 priv->dev->stats.rx_errors++; 1392 else { 1393 struct sk_buff *skb; 1394 int frame_len; 1395 1396 frame_len = priv->hw->desc->get_rx_frame_len(p, 1397 priv->plat->rx_coe); 1398 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 1399 * Type frames (LLC/LLC-SNAP) */ 1400 if (unlikely(status != llc_snap)) 1401 frame_len -= ETH_FCS_LEN; 1402 #ifdef STMMAC_RX_DEBUG 1403 if (frame_len > ETH_FRAME_LEN) 1404 pr_debug("\tRX frame size %d, COE status: %d\n", 1405 frame_len, status); 1406 1407 if (netif_msg_hw(priv)) 1408 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 1409 p, entry, p->des2); 1410 #endif 1411 skb = priv->rx_skbuff[entry]; 1412 if (unlikely(!skb)) { 1413 pr_err("%s: Inconsistent Rx descriptor chain\n", 1414 priv->dev->name); 1415 priv->dev->stats.rx_dropped++; 1416 break; 1417 } 1418 prefetch(skb->data - NET_IP_ALIGN); 1419 priv->rx_skbuff[entry] = NULL; 1420 1421 skb_put(skb, frame_len); 1422 dma_unmap_single(priv->device, 1423 priv->rx_skbuff_dma[entry], 1424 priv->dma_buf_sz, DMA_FROM_DEVICE); 1425 #ifdef STMMAC_RX_DEBUG 1426 if (netif_msg_pktdata(priv)) { 1427 pr_info(" frame received (%dbytes)", frame_len); 1428 print_pkt(skb->data, frame_len); 1429 } 1430 #endif 1431 skb->protocol = eth_type_trans(skb, priv->dev); 1432 1433 if (unlikely(!priv->plat->rx_coe)) 1434 skb_checksum_none_assert(skb); 1435 else 1436 skb->ip_summed = CHECKSUM_UNNECESSARY; 1437 1438 napi_gro_receive(&priv->napi, skb); 1439 1440 priv->dev->stats.rx_packets++; 1441 priv->dev->stats.rx_bytes += frame_len; 1442 } 1443 entry = next_entry; 1444 p = p_next; /* use prefetched values */ 1445 } 1446 1447 stmmac_rx_refill(priv); 1448 1449 priv->xstats.rx_pkt_n += count; 1450 1451 return count; 1452 } 1453 1454 /** 1455 * stmmac_poll - stmmac poll method (NAPI) 1456 * @napi : pointer to the napi structure. 1457 * @budget : maximum number of packets that the current CPU can receive from 1458 * all interfaces. 1459 * Description : 1460 * To look at the incoming frames and clear the tx resources. 1461 */ 1462 static int stmmac_poll(struct napi_struct *napi, int budget) 1463 { 1464 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 1465 int work_done = 0; 1466 1467 priv->xstats.napi_poll++; 1468 stmmac_tx_clean(priv); 1469 1470 work_done = stmmac_rx(priv, budget); 1471 if (work_done < budget) { 1472 napi_complete(napi); 1473 stmmac_enable_dma_irq(priv); 1474 } 1475 return work_done; 1476 } 1477 1478 /** 1479 * stmmac_tx_timeout 1480 * @dev : Pointer to net device structure 1481 * Description: this function is called when a packet transmission fails to 1482 * complete within a reasonable time. The driver will mark the error in the 1483 * netdev structure and arrange for the device to be reset to a sane state 1484 * in order to transmit a new packet. 1485 */ 1486 static void stmmac_tx_timeout(struct net_device *dev) 1487 { 1488 struct stmmac_priv *priv = netdev_priv(dev); 1489 1490 /* Clear Tx resources and restart transmitting again */ 1491 stmmac_tx_err(priv); 1492 } 1493 1494 /* Configuration changes (passed on by ifconfig) */ 1495 static int stmmac_config(struct net_device *dev, struct ifmap *map) 1496 { 1497 if (dev->flags & IFF_UP) /* can't act on a running interface */ 1498 return -EBUSY; 1499 1500 /* Don't allow changing the I/O address */ 1501 if (map->base_addr != dev->base_addr) { 1502 pr_warning("%s: can't change I/O address\n", dev->name); 1503 return -EOPNOTSUPP; 1504 } 1505 1506 /* Don't allow changing the IRQ */ 1507 if (map->irq != dev->irq) { 1508 pr_warning("%s: can't change IRQ number %d\n", 1509 dev->name, dev->irq); 1510 return -EOPNOTSUPP; 1511 } 1512 1513 /* ignore other fields */ 1514 return 0; 1515 } 1516 1517 /** 1518 * stmmac_set_rx_mode - entry point for multicast addressing 1519 * @dev : pointer to the device structure 1520 * Description: 1521 * This function is a driver entry point which gets called by the kernel 1522 * whenever multicast addresses must be enabled/disabled. 1523 * Return value: 1524 * void. 1525 */ 1526 static void stmmac_set_rx_mode(struct net_device *dev) 1527 { 1528 struct stmmac_priv *priv = netdev_priv(dev); 1529 1530 spin_lock(&priv->lock); 1531 priv->hw->mac->set_filter(dev, priv->synopsys_id); 1532 spin_unlock(&priv->lock); 1533 } 1534 1535 /** 1536 * stmmac_change_mtu - entry point to change MTU size for the device. 1537 * @dev : device pointer. 1538 * @new_mtu : the new MTU size for the device. 1539 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 1540 * to drive packet transmission. Ethernet has an MTU of 1500 octets 1541 * (ETH_DATA_LEN). This value can be changed with ifconfig. 1542 * Return value: 1543 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1544 * file on failure. 1545 */ 1546 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 1547 { 1548 struct stmmac_priv *priv = netdev_priv(dev); 1549 int max_mtu; 1550 1551 if (netif_running(dev)) { 1552 pr_err("%s: must be stopped to change its MTU\n", dev->name); 1553 return -EBUSY; 1554 } 1555 1556 if (priv->plat->enh_desc) 1557 max_mtu = JUMBO_LEN; 1558 else 1559 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 1560 1561 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 1562 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 1563 return -EINVAL; 1564 } 1565 1566 dev->mtu = new_mtu; 1567 netdev_update_features(dev); 1568 1569 return 0; 1570 } 1571 1572 static netdev_features_t stmmac_fix_features(struct net_device *dev, 1573 netdev_features_t features) 1574 { 1575 struct stmmac_priv *priv = netdev_priv(dev); 1576 1577 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 1578 features &= ~NETIF_F_RXCSUM; 1579 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) 1580 features &= ~NETIF_F_IPV6_CSUM; 1581 if (!priv->plat->tx_coe) 1582 features &= ~NETIF_F_ALL_CSUM; 1583 1584 /* Some GMAC devices have a bugged Jumbo frame support that 1585 * needs to have the Tx COE disabled for oversized frames 1586 * (due to limited buffer sizes). In this case we disable 1587 * the TX csum insertionin the TDES and not use SF. */ 1588 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 1589 features &= ~NETIF_F_ALL_CSUM; 1590 1591 return features; 1592 } 1593 1594 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 1595 { 1596 struct net_device *dev = (struct net_device *)dev_id; 1597 struct stmmac_priv *priv = netdev_priv(dev); 1598 1599 if (unlikely(!dev)) { 1600 pr_err("%s: invalid dev pointer\n", __func__); 1601 return IRQ_NONE; 1602 } 1603 1604 /* To handle GMAC own interrupts */ 1605 if (priv->plat->has_gmac) { 1606 int status = priv->hw->mac->host_irq_status((void __iomem *) 1607 dev->base_addr); 1608 if (unlikely(status)) { 1609 if (status & core_mmc_tx_irq) 1610 priv->xstats.mmc_tx_irq_n++; 1611 if (status & core_mmc_rx_irq) 1612 priv->xstats.mmc_rx_irq_n++; 1613 if (status & core_mmc_rx_csum_offload_irq) 1614 priv->xstats.mmc_rx_csum_offload_irq_n++; 1615 if (status & core_irq_receive_pmt_irq) 1616 priv->xstats.irq_receive_pmt_irq_n++; 1617 1618 /* For LPI we need to save the tx status */ 1619 if (status & core_irq_tx_path_in_lpi_mode) { 1620 priv->xstats.irq_tx_path_in_lpi_mode_n++; 1621 priv->tx_path_in_lpi_mode = true; 1622 } 1623 if (status & core_irq_tx_path_exit_lpi_mode) { 1624 priv->xstats.irq_tx_path_exit_lpi_mode_n++; 1625 priv->tx_path_in_lpi_mode = false; 1626 } 1627 if (status & core_irq_rx_path_in_lpi_mode) 1628 priv->xstats.irq_rx_path_in_lpi_mode_n++; 1629 if (status & core_irq_rx_path_exit_lpi_mode) 1630 priv->xstats.irq_rx_path_exit_lpi_mode_n++; 1631 } 1632 } 1633 1634 /* To handle DMA interrupts */ 1635 stmmac_dma_interrupt(priv); 1636 1637 return IRQ_HANDLED; 1638 } 1639 1640 #ifdef CONFIG_NET_POLL_CONTROLLER 1641 /* Polling receive - used by NETCONSOLE and other diagnostic tools 1642 * to allow network I/O with interrupts disabled. */ 1643 static void stmmac_poll_controller(struct net_device *dev) 1644 { 1645 disable_irq(dev->irq); 1646 stmmac_interrupt(dev->irq, dev); 1647 enable_irq(dev->irq); 1648 } 1649 #endif 1650 1651 /** 1652 * stmmac_ioctl - Entry point for the Ioctl 1653 * @dev: Device pointer. 1654 * @rq: An IOCTL specefic structure, that can contain a pointer to 1655 * a proprietary structure used to pass information to the driver. 1656 * @cmd: IOCTL command 1657 * Description: 1658 * Currently there are no special functionality supported in IOCTL, just the 1659 * phy_mii_ioctl(...) can be invoked. 1660 */ 1661 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1662 { 1663 struct stmmac_priv *priv = netdev_priv(dev); 1664 int ret; 1665 1666 if (!netif_running(dev)) 1667 return -EINVAL; 1668 1669 if (!priv->phydev) 1670 return -EINVAL; 1671 1672 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 1673 1674 return ret; 1675 } 1676 1677 #ifdef CONFIG_STMMAC_DEBUG_FS 1678 static struct dentry *stmmac_fs_dir; 1679 static struct dentry *stmmac_rings_status; 1680 static struct dentry *stmmac_dma_cap; 1681 1682 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 1683 { 1684 struct tmp_s { 1685 u64 a; 1686 unsigned int b; 1687 unsigned int c; 1688 }; 1689 int i; 1690 struct net_device *dev = seq->private; 1691 struct stmmac_priv *priv = netdev_priv(dev); 1692 1693 seq_printf(seq, "=======================\n"); 1694 seq_printf(seq, " RX descriptor ring\n"); 1695 seq_printf(seq, "=======================\n"); 1696 1697 for (i = 0; i < priv->dma_rx_size; i++) { 1698 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); 1699 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 1700 i, (unsigned int)(x->a), 1701 (unsigned int)((x->a) >> 32), x->b, x->c); 1702 seq_printf(seq, "\n"); 1703 } 1704 1705 seq_printf(seq, "\n"); 1706 seq_printf(seq, "=======================\n"); 1707 seq_printf(seq, " TX descriptor ring\n"); 1708 seq_printf(seq, "=======================\n"); 1709 1710 for (i = 0; i < priv->dma_tx_size; i++) { 1711 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); 1712 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 1713 i, (unsigned int)(x->a), 1714 (unsigned int)((x->a) >> 32), x->b, x->c); 1715 seq_printf(seq, "\n"); 1716 } 1717 1718 return 0; 1719 } 1720 1721 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 1722 { 1723 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 1724 } 1725 1726 static const struct file_operations stmmac_rings_status_fops = { 1727 .owner = THIS_MODULE, 1728 .open = stmmac_sysfs_ring_open, 1729 .read = seq_read, 1730 .llseek = seq_lseek, 1731 .release = single_release, 1732 }; 1733 1734 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 1735 { 1736 struct net_device *dev = seq->private; 1737 struct stmmac_priv *priv = netdev_priv(dev); 1738 1739 if (!priv->hw_cap_support) { 1740 seq_printf(seq, "DMA HW features not supported\n"); 1741 return 0; 1742 } 1743 1744 seq_printf(seq, "==============================\n"); 1745 seq_printf(seq, "\tDMA HW features\n"); 1746 seq_printf(seq, "==============================\n"); 1747 1748 seq_printf(seq, "\t10/100 Mbps %s\n", 1749 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 1750 seq_printf(seq, "\t1000 Mbps %s\n", 1751 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 1752 seq_printf(seq, "\tHalf duple %s\n", 1753 (priv->dma_cap.half_duplex) ? "Y" : "N"); 1754 seq_printf(seq, "\tHash Filter: %s\n", 1755 (priv->dma_cap.hash_filter) ? "Y" : "N"); 1756 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 1757 (priv->dma_cap.multi_addr) ? "Y" : "N"); 1758 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 1759 (priv->dma_cap.pcs) ? "Y" : "N"); 1760 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 1761 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 1762 seq_printf(seq, "\tPMT Remote wake up: %s\n", 1763 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 1764 seq_printf(seq, "\tPMT Magic Frame: %s\n", 1765 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 1766 seq_printf(seq, "\tRMON module: %s\n", 1767 (priv->dma_cap.rmon) ? "Y" : "N"); 1768 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 1769 (priv->dma_cap.time_stamp) ? "Y" : "N"); 1770 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 1771 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 1772 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 1773 (priv->dma_cap.eee) ? "Y" : "N"); 1774 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 1775 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 1776 (priv->dma_cap.tx_coe) ? "Y" : "N"); 1777 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 1778 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 1779 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 1780 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 1781 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 1782 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 1783 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 1784 priv->dma_cap.number_rx_channel); 1785 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 1786 priv->dma_cap.number_tx_channel); 1787 seq_printf(seq, "\tEnhanced descriptors: %s\n", 1788 (priv->dma_cap.enh_desc) ? "Y" : "N"); 1789 1790 return 0; 1791 } 1792 1793 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 1794 { 1795 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 1796 } 1797 1798 static const struct file_operations stmmac_dma_cap_fops = { 1799 .owner = THIS_MODULE, 1800 .open = stmmac_sysfs_dma_cap_open, 1801 .read = seq_read, 1802 .llseek = seq_lseek, 1803 .release = single_release, 1804 }; 1805 1806 static int stmmac_init_fs(struct net_device *dev) 1807 { 1808 /* Create debugfs entries */ 1809 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 1810 1811 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 1812 pr_err("ERROR %s, debugfs create directory failed\n", 1813 STMMAC_RESOURCE_NAME); 1814 1815 return -ENOMEM; 1816 } 1817 1818 /* Entry to report DMA RX/TX rings */ 1819 stmmac_rings_status = debugfs_create_file("descriptors_status", 1820 S_IRUGO, stmmac_fs_dir, dev, 1821 &stmmac_rings_status_fops); 1822 1823 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 1824 pr_info("ERROR creating stmmac ring debugfs file\n"); 1825 debugfs_remove(stmmac_fs_dir); 1826 1827 return -ENOMEM; 1828 } 1829 1830 /* Entry to report the DMA HW features */ 1831 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 1832 dev, &stmmac_dma_cap_fops); 1833 1834 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 1835 pr_info("ERROR creating stmmac MMC debugfs file\n"); 1836 debugfs_remove(stmmac_rings_status); 1837 debugfs_remove(stmmac_fs_dir); 1838 1839 return -ENOMEM; 1840 } 1841 1842 return 0; 1843 } 1844 1845 static void stmmac_exit_fs(void) 1846 { 1847 debugfs_remove(stmmac_rings_status); 1848 debugfs_remove(stmmac_dma_cap); 1849 debugfs_remove(stmmac_fs_dir); 1850 } 1851 #endif /* CONFIG_STMMAC_DEBUG_FS */ 1852 1853 static const struct net_device_ops stmmac_netdev_ops = { 1854 .ndo_open = stmmac_open, 1855 .ndo_start_xmit = stmmac_xmit, 1856 .ndo_stop = stmmac_release, 1857 .ndo_change_mtu = stmmac_change_mtu, 1858 .ndo_fix_features = stmmac_fix_features, 1859 .ndo_set_rx_mode = stmmac_set_rx_mode, 1860 .ndo_tx_timeout = stmmac_tx_timeout, 1861 .ndo_do_ioctl = stmmac_ioctl, 1862 .ndo_set_config = stmmac_config, 1863 #ifdef CONFIG_NET_POLL_CONTROLLER 1864 .ndo_poll_controller = stmmac_poll_controller, 1865 #endif 1866 .ndo_set_mac_address = eth_mac_addr, 1867 }; 1868 1869 /** 1870 * stmmac_hw_init - Init the MAC device 1871 * @priv : pointer to the private device structure. 1872 * Description: this function detects which MAC device 1873 * (GMAC/MAC10-100) has to attached, checks the HW capability 1874 * (if supported) and sets the driver's features (for example 1875 * to use the ring or chaine mode or support the normal/enh 1876 * descriptor structure). 1877 */ 1878 static int stmmac_hw_init(struct stmmac_priv *priv) 1879 { 1880 int ret = 0; 1881 struct mac_device_info *mac; 1882 1883 /* Identify the MAC HW device */ 1884 if (priv->plat->has_gmac) { 1885 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1886 mac = dwmac1000_setup(priv->ioaddr); 1887 } else { 1888 mac = dwmac100_setup(priv->ioaddr); 1889 } 1890 if (!mac) 1891 return -ENOMEM; 1892 1893 priv->hw = mac; 1894 1895 /* To use the chained or ring mode */ 1896 priv->hw->ring = &ring_mode_ops; 1897 1898 /* Get and dump the chip ID */ 1899 priv->synopsys_id = stmmac_get_synopsys_id(priv); 1900 1901 /* Get the HW capability (new GMAC newer than 3.50a) */ 1902 priv->hw_cap_support = stmmac_get_hw_features(priv); 1903 if (priv->hw_cap_support) { 1904 pr_info(" DMA HW capability register supported"); 1905 1906 /* We can override some gmac/dma configuration fields: e.g. 1907 * enh_desc, tx_coe (e.g. that are passed through the 1908 * platform) with the values from the HW capability 1909 * register (if supported). 1910 */ 1911 priv->plat->enh_desc = priv->dma_cap.enh_desc; 1912 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 1913 1914 priv->plat->tx_coe = priv->dma_cap.tx_coe; 1915 1916 if (priv->dma_cap.rx_coe_type2) 1917 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 1918 else if (priv->dma_cap.rx_coe_type1) 1919 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 1920 1921 } else 1922 pr_info(" No HW DMA feature register supported"); 1923 1924 /* Select the enhnaced/normal descriptor structures */ 1925 stmmac_selec_desc_mode(priv); 1926 1927 /* Enable the IPC (Checksum Offload) and check if the feature has been 1928 * enabled during the core configuration. */ 1929 ret = priv->hw->mac->rx_ipc(priv->ioaddr); 1930 if (!ret) { 1931 pr_warning(" RX IPC Checksum Offload not configured.\n"); 1932 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1933 } 1934 1935 if (priv->plat->rx_coe) 1936 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 1937 priv->plat->rx_coe); 1938 if (priv->plat->tx_coe) 1939 pr_info(" TX Checksum insertion supported\n"); 1940 1941 if (priv->plat->pmt) { 1942 pr_info(" Wake-Up On Lan supported\n"); 1943 device_set_wakeup_capable(priv->device, 1); 1944 } 1945 1946 return ret; 1947 } 1948 1949 /** 1950 * stmmac_dvr_probe 1951 * @device: device pointer 1952 * @plat_dat: platform data pointer 1953 * @addr: iobase memory address 1954 * Description: this is the main probe function used to 1955 * call the alloc_etherdev, allocate the priv structure. 1956 */ 1957 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 1958 struct plat_stmmacenet_data *plat_dat, 1959 void __iomem *addr) 1960 { 1961 int ret = 0; 1962 struct net_device *ndev = NULL; 1963 struct stmmac_priv *priv; 1964 1965 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 1966 if (!ndev) 1967 return NULL; 1968 1969 SET_NETDEV_DEV(ndev, device); 1970 1971 priv = netdev_priv(ndev); 1972 priv->device = device; 1973 priv->dev = ndev; 1974 1975 ether_setup(ndev); 1976 1977 stmmac_set_ethtool_ops(ndev); 1978 priv->pause = pause; 1979 priv->plat = plat_dat; 1980 priv->ioaddr = addr; 1981 priv->dev->base_addr = (unsigned long)addr; 1982 1983 /* Verify driver arguments */ 1984 stmmac_verify_args(); 1985 1986 /* Override with kernel parameters if supplied XXX CRS XXX 1987 * this needs to have multiple instances */ 1988 if ((phyaddr >= 0) && (phyaddr <= 31)) 1989 priv->plat->phy_addr = phyaddr; 1990 1991 /* Init MAC and get the capabilities */ 1992 stmmac_hw_init(priv); 1993 1994 ndev->netdev_ops = &stmmac_netdev_ops; 1995 1996 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1997 NETIF_F_RXCSUM; 1998 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 1999 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2000 #ifdef STMMAC_VLAN_TAG_USED 2001 /* Both mac100 and gmac support receive VLAN tag detection */ 2002 ndev->features |= NETIF_F_HW_VLAN_RX; 2003 #endif 2004 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2005 2006 if (flow_ctrl) 2007 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2008 2009 /* Rx Watchdog is available in the COREs newer than the 3.40. 2010 * In some case, for example on bugged HW this feature 2011 * has to be disable and this can be done by passing the 2012 * riwt_off field from the platform. 2013 */ 2014 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2015 priv->use_riwt = 1; 2016 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2017 } 2018 2019 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2020 2021 spin_lock_init(&priv->lock); 2022 spin_lock_init(&priv->tx_lock); 2023 2024 ret = register_netdev(ndev); 2025 if (ret) { 2026 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2027 goto error_netdev_register; 2028 } 2029 2030 priv->stmmac_clk = clk_get(priv->device, STMMAC_RESOURCE_NAME); 2031 if (IS_ERR(priv->stmmac_clk)) { 2032 pr_warning("%s: warning: cannot get CSR clock\n", __func__); 2033 goto error_clk_get; 2034 } 2035 2036 /* If a specific clk_csr value is passed from the platform 2037 * this means that the CSR Clock Range selection cannot be 2038 * changed at run-time and it is fixed. Viceversa the driver'll try to 2039 * set the MDC clock dynamically according to the csr actual 2040 * clock input. 2041 */ 2042 if (!priv->plat->clk_csr) 2043 stmmac_clk_csr_set(priv); 2044 else 2045 priv->clk_csr = priv->plat->clk_csr; 2046 2047 /* MDIO bus Registration */ 2048 ret = stmmac_mdio_register(ndev); 2049 if (ret < 0) { 2050 pr_debug("%s: MDIO bus (id: %d) registration failed", 2051 __func__, priv->plat->bus_id); 2052 goto error_mdio_register; 2053 } 2054 2055 return priv; 2056 2057 error_mdio_register: 2058 clk_put(priv->stmmac_clk); 2059 error_clk_get: 2060 unregister_netdev(ndev); 2061 error_netdev_register: 2062 netif_napi_del(&priv->napi); 2063 free_netdev(ndev); 2064 2065 return NULL; 2066 } 2067 2068 /** 2069 * stmmac_dvr_remove 2070 * @ndev: net device pointer 2071 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2072 * changes the link status, releases the DMA descriptor rings. 2073 */ 2074 int stmmac_dvr_remove(struct net_device *ndev) 2075 { 2076 struct stmmac_priv *priv = netdev_priv(ndev); 2077 2078 pr_info("%s:\n\tremoving driver", __func__); 2079 2080 priv->hw->dma->stop_rx(priv->ioaddr); 2081 priv->hw->dma->stop_tx(priv->ioaddr); 2082 2083 stmmac_set_mac(priv->ioaddr, false); 2084 stmmac_mdio_unregister(ndev); 2085 netif_carrier_off(ndev); 2086 unregister_netdev(ndev); 2087 free_netdev(ndev); 2088 2089 return 0; 2090 } 2091 2092 #ifdef CONFIG_PM 2093 int stmmac_suspend(struct net_device *ndev) 2094 { 2095 struct stmmac_priv *priv = netdev_priv(ndev); 2096 int dis_ic = 0; 2097 unsigned long flags; 2098 2099 if (!ndev || !netif_running(ndev)) 2100 return 0; 2101 2102 if (priv->phydev) 2103 phy_stop(priv->phydev); 2104 2105 spin_lock_irqsave(&priv->lock, flags); 2106 2107 netif_device_detach(ndev); 2108 netif_stop_queue(ndev); 2109 2110 if (priv->use_riwt) 2111 dis_ic = 1; 2112 2113 napi_disable(&priv->napi); 2114 2115 /* Stop TX/RX DMA */ 2116 priv->hw->dma->stop_tx(priv->ioaddr); 2117 priv->hw->dma->stop_rx(priv->ioaddr); 2118 /* Clear the Rx/Tx descriptors */ 2119 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, 2120 dis_ic); 2121 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 2122 2123 /* Enable Power down mode by programming the PMT regs */ 2124 if (device_may_wakeup(priv->device)) 2125 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); 2126 else { 2127 stmmac_set_mac(priv->ioaddr, false); 2128 /* Disable clock in case of PWM is off */ 2129 clk_disable_unprepare(priv->stmmac_clk); 2130 } 2131 spin_unlock_irqrestore(&priv->lock, flags); 2132 return 0; 2133 } 2134 2135 int stmmac_resume(struct net_device *ndev) 2136 { 2137 struct stmmac_priv *priv = netdev_priv(ndev); 2138 unsigned long flags; 2139 2140 if (!netif_running(ndev)) 2141 return 0; 2142 2143 spin_lock_irqsave(&priv->lock, flags); 2144 2145 /* Power Down bit, into the PM register, is cleared 2146 * automatically as soon as a magic packet or a Wake-up frame 2147 * is received. Anyway, it's better to manually clear 2148 * this bit because it can generate problems while resuming 2149 * from another devices (e.g. serial console). */ 2150 if (device_may_wakeup(priv->device)) 2151 priv->hw->mac->pmt(priv->ioaddr, 0); 2152 else 2153 /* enable the clk prevously disabled */ 2154 clk_prepare_enable(priv->stmmac_clk); 2155 2156 netif_device_attach(ndev); 2157 2158 /* Enable the MAC and DMA */ 2159 stmmac_set_mac(priv->ioaddr, true); 2160 priv->hw->dma->start_tx(priv->ioaddr); 2161 priv->hw->dma->start_rx(priv->ioaddr); 2162 2163 napi_enable(&priv->napi); 2164 2165 netif_start_queue(ndev); 2166 2167 spin_unlock_irqrestore(&priv->lock, flags); 2168 2169 if (priv->phydev) 2170 phy_start(priv->phydev); 2171 2172 return 0; 2173 } 2174 2175 int stmmac_freeze(struct net_device *ndev) 2176 { 2177 if (!ndev || !netif_running(ndev)) 2178 return 0; 2179 2180 return stmmac_release(ndev); 2181 } 2182 2183 int stmmac_restore(struct net_device *ndev) 2184 { 2185 if (!ndev || !netif_running(ndev)) 2186 return 0; 2187 2188 return stmmac_open(ndev); 2189 } 2190 #endif /* CONFIG_PM */ 2191 2192 /* Driver can be configured w/ and w/ both PCI and Platf drivers 2193 * depending on the configuration selected. 2194 */ 2195 static int __init stmmac_init(void) 2196 { 2197 int ret; 2198 2199 ret = stmmac_register_platform(); 2200 if (ret) 2201 goto err; 2202 ret = stmmac_register_pci(); 2203 if (ret) 2204 goto err_pci; 2205 return 0; 2206 err_pci: 2207 stmmac_unregister_platform(); 2208 err: 2209 pr_err("stmmac: driver registration failed\n"); 2210 return ret; 2211 } 2212 2213 static void __exit stmmac_exit(void) 2214 { 2215 stmmac_unregister_platform(); 2216 stmmac_unregister_pci(); 2217 } 2218 2219 module_init(stmmac_init); 2220 module_exit(stmmac_exit); 2221 2222 #ifndef MODULE 2223 static int __init stmmac_cmdline_opt(char *str) 2224 { 2225 char *opt; 2226 2227 if (!str || !*str) 2228 return -EINVAL; 2229 while ((opt = strsep(&str, ",")) != NULL) { 2230 if (!strncmp(opt, "debug:", 6)) { 2231 if (kstrtoint(opt + 6, 0, &debug)) 2232 goto err; 2233 } else if (!strncmp(opt, "phyaddr:", 8)) { 2234 if (kstrtoint(opt + 8, 0, &phyaddr)) 2235 goto err; 2236 } else if (!strncmp(opt, "dma_txsize:", 11)) { 2237 if (kstrtoint(opt + 11, 0, &dma_txsize)) 2238 goto err; 2239 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 2240 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 2241 goto err; 2242 } else if (!strncmp(opt, "buf_sz:", 7)) { 2243 if (kstrtoint(opt + 7, 0, &buf_sz)) 2244 goto err; 2245 } else if (!strncmp(opt, "tc:", 3)) { 2246 if (kstrtoint(opt + 3, 0, &tc)) 2247 goto err; 2248 } else if (!strncmp(opt, "watchdog:", 9)) { 2249 if (kstrtoint(opt + 9, 0, &watchdog)) 2250 goto err; 2251 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 2252 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 2253 goto err; 2254 } else if (!strncmp(opt, "pause:", 6)) { 2255 if (kstrtoint(opt + 6, 0, &pause)) 2256 goto err; 2257 } else if (!strncmp(opt, "eee_timer:", 6)) { 2258 if (kstrtoint(opt + 10, 0, &eee_timer)) 2259 goto err; 2260 } 2261 } 2262 return 0; 2263 2264 err: 2265 pr_err("%s: ERROR broken module parameter conversion", __func__); 2266 return -EINVAL; 2267 } 2268 2269 __setup("stmmaceth=", stmmac_cmdline_opt); 2270 #endif 2271 2272 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 2273 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 2274 MODULE_LICENSE("GPL"); 2275