1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/clk.h> 32 #include <linux/kernel.h> 33 #include <linux/interrupt.h> 34 #include <linux/ip.h> 35 #include <linux/tcp.h> 36 #include <linux/skbuff.h> 37 #include <linux/ethtool.h> 38 #include <linux/if_ether.h> 39 #include <linux/crc32.h> 40 #include <linux/mii.h> 41 #include <linux/if.h> 42 #include <linux/if_vlan.h> 43 #include <linux/dma-mapping.h> 44 #include <linux/slab.h> 45 #include <linux/prefetch.h> 46 #include <linux/pinctrl/consumer.h> 47 #ifdef CONFIG_DEBUG_FS 48 #include <linux/debugfs.h> 49 #include <linux/seq_file.h> 50 #endif /* CONFIG_DEBUG_FS */ 51 #include <linux/net_tstamp.h> 52 #include "stmmac_ptp.h" 53 #include "stmmac.h" 54 #include <linux/reset.h> 55 #include <linux/of_mdio.h> 56 57 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 58 59 /* Module parameters */ 60 #define TX_TIMEO 5000 61 static int watchdog = TX_TIMEO; 62 module_param(watchdog, int, S_IRUGO | S_IWUSR); 63 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 64 65 static int debug = -1; 66 module_param(debug, int, S_IRUGO | S_IWUSR); 67 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 68 69 static int phyaddr = -1; 70 module_param(phyaddr, int, S_IRUGO); 71 MODULE_PARM_DESC(phyaddr, "Physical device address"); 72 73 #define DMA_TX_SIZE 256 74 static int dma_txsize = DMA_TX_SIZE; 75 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 76 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 77 78 #define DMA_RX_SIZE 256 79 static int dma_rxsize = DMA_RX_SIZE; 80 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 81 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 82 83 static int flow_ctrl = FLOW_OFF; 84 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 85 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 86 87 static int pause = PAUSE_TIME; 88 module_param(pause, int, S_IRUGO | S_IWUSR); 89 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 90 91 #define TC_DEFAULT 64 92 static int tc = TC_DEFAULT; 93 module_param(tc, int, S_IRUGO | S_IWUSR); 94 MODULE_PARM_DESC(tc, "DMA threshold control value"); 95 96 #define DEFAULT_BUFSIZE 1536 97 static int buf_sz = DEFAULT_BUFSIZE; 98 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 99 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 100 101 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 102 NETIF_MSG_LINK | NETIF_MSG_IFUP | 103 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 104 105 #define STMMAC_DEFAULT_LPI_TIMER 1000 106 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 107 module_param(eee_timer, int, S_IRUGO | S_IWUSR); 108 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 109 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 110 111 /* By default the driver will use the ring mode to manage tx and rx descriptors 112 * but passing this value so user can force to use the chain instead of the ring 113 */ 114 static unsigned int chain_mode; 115 module_param(chain_mode, int, S_IRUGO); 116 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 117 118 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 119 120 #ifdef CONFIG_DEBUG_FS 121 static int stmmac_init_fs(struct net_device *dev); 122 static void stmmac_exit_fs(struct net_device *dev); 123 #endif 124 125 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 126 127 /** 128 * stmmac_verify_args - verify the driver parameters. 129 * Description: it checks the driver parameters and set a default in case of 130 * errors. 131 */ 132 static void stmmac_verify_args(void) 133 { 134 if (unlikely(watchdog < 0)) 135 watchdog = TX_TIMEO; 136 if (unlikely(dma_rxsize < 0)) 137 dma_rxsize = DMA_RX_SIZE; 138 if (unlikely(dma_txsize < 0)) 139 dma_txsize = DMA_TX_SIZE; 140 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 141 buf_sz = DEFAULT_BUFSIZE; 142 if (unlikely(flow_ctrl > 1)) 143 flow_ctrl = FLOW_AUTO; 144 else if (likely(flow_ctrl < 0)) 145 flow_ctrl = FLOW_OFF; 146 if (unlikely((pause < 0) || (pause > 0xffff))) 147 pause = PAUSE_TIME; 148 if (eee_timer < 0) 149 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 150 } 151 152 /** 153 * stmmac_clk_csr_set - dynamically set the MDC clock 154 * @priv: driver private structure 155 * Description: this is to dynamically set the MDC clock according to the csr 156 * clock input. 157 * Note: 158 * If a specific clk_csr value is passed from the platform 159 * this means that the CSR Clock Range selection cannot be 160 * changed at run-time and it is fixed (as reported in the driver 161 * documentation). Viceversa the driver will try to set the MDC 162 * clock dynamically according to the actual clock input. 163 */ 164 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 165 { 166 u32 clk_rate; 167 168 clk_rate = clk_get_rate(priv->stmmac_clk); 169 170 /* Platform provided default clk_csr would be assumed valid 171 * for all other cases except for the below mentioned ones. 172 * For values higher than the IEEE 802.3 specified frequency 173 * we can not estimate the proper divider as it is not known 174 * the frequency of clk_csr_i. So we do not change the default 175 * divider. 176 */ 177 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 178 if (clk_rate < CSR_F_35M) 179 priv->clk_csr = STMMAC_CSR_20_35M; 180 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 181 priv->clk_csr = STMMAC_CSR_35_60M; 182 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 183 priv->clk_csr = STMMAC_CSR_60_100M; 184 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 185 priv->clk_csr = STMMAC_CSR_100_150M; 186 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 187 priv->clk_csr = STMMAC_CSR_150_250M; 188 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 189 priv->clk_csr = STMMAC_CSR_250_300M; 190 } 191 } 192 193 static void print_pkt(unsigned char *buf, int len) 194 { 195 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 196 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 197 } 198 199 /* minimum number of free TX descriptors required to wake up TX process */ 200 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 201 202 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 203 { 204 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 205 } 206 207 /** 208 * stmmac_hw_fix_mac_speed - callback for speed selection 209 * @priv: driver private structure 210 * Description: on some platforms (e.g. ST), some HW system configuraton 211 * registers have to be set according to the link speed negotiated. 212 */ 213 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 214 { 215 struct phy_device *phydev = priv->phydev; 216 217 if (likely(priv->plat->fix_mac_speed)) 218 priv->plat->fix_mac_speed(priv->plat->bsp_priv, phydev->speed); 219 } 220 221 /** 222 * stmmac_enable_eee_mode - check and enter in LPI mode 223 * @priv: driver private structure 224 * Description: this function is to verify and enter in LPI mode in case of 225 * EEE. 226 */ 227 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 228 { 229 /* Check and enter in LPI mode */ 230 if ((priv->dirty_tx == priv->cur_tx) && 231 (priv->tx_path_in_lpi_mode == false)) 232 priv->hw->mac->set_eee_mode(priv->hw); 233 } 234 235 /** 236 * stmmac_disable_eee_mode - disable and exit from LPI mode 237 * @priv: driver private structure 238 * Description: this function is to exit and disable EEE in case of 239 * LPI state is true. This is called by the xmit. 240 */ 241 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 242 { 243 priv->hw->mac->reset_eee_mode(priv->hw); 244 del_timer_sync(&priv->eee_ctrl_timer); 245 priv->tx_path_in_lpi_mode = false; 246 } 247 248 /** 249 * stmmac_eee_ctrl_timer - EEE TX SW timer. 250 * @arg : data hook 251 * Description: 252 * if there is no data transfer and if we are not in LPI state, 253 * then MAC Transmitter can be moved to LPI state. 254 */ 255 static void stmmac_eee_ctrl_timer(unsigned long arg) 256 { 257 struct stmmac_priv *priv = (struct stmmac_priv *)arg; 258 259 stmmac_enable_eee_mode(priv); 260 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 261 } 262 263 /** 264 * stmmac_eee_init - init EEE 265 * @priv: driver private structure 266 * Description: 267 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 268 * can also manage EEE, this function enable the LPI state and start related 269 * timer. 270 */ 271 bool stmmac_eee_init(struct stmmac_priv *priv) 272 { 273 char *phy_bus_name = priv->plat->phy_bus_name; 274 unsigned long flags; 275 bool ret = false; 276 277 /* Using PCS we cannot dial with the phy registers at this stage 278 * so we do not support extra feature like EEE. 279 */ 280 if ((priv->pcs == STMMAC_PCS_RGMII) || (priv->pcs == STMMAC_PCS_TBI) || 281 (priv->pcs == STMMAC_PCS_RTBI)) 282 goto out; 283 284 /* Never init EEE in case of a switch is attached */ 285 if (phy_bus_name && (!strcmp(phy_bus_name, "fixed"))) 286 goto out; 287 288 /* MAC core supports the EEE feature. */ 289 if (priv->dma_cap.eee) { 290 int tx_lpi_timer = priv->tx_lpi_timer; 291 292 /* Check if the PHY supports EEE */ 293 if (phy_init_eee(priv->phydev, 1)) { 294 /* To manage at run-time if the EEE cannot be supported 295 * anymore (for example because the lp caps have been 296 * changed). 297 * In that case the driver disable own timers. 298 */ 299 spin_lock_irqsave(&priv->lock, flags); 300 if (priv->eee_active) { 301 pr_debug("stmmac: disable EEE\n"); 302 del_timer_sync(&priv->eee_ctrl_timer); 303 priv->hw->mac->set_eee_timer(priv->hw, 0, 304 tx_lpi_timer); 305 } 306 priv->eee_active = 0; 307 spin_unlock_irqrestore(&priv->lock, flags); 308 goto out; 309 } 310 /* Activate the EEE and start timers */ 311 spin_lock_irqsave(&priv->lock, flags); 312 if (!priv->eee_active) { 313 priv->eee_active = 1; 314 setup_timer(&priv->eee_ctrl_timer, 315 stmmac_eee_ctrl_timer, 316 (unsigned long)priv); 317 mod_timer(&priv->eee_ctrl_timer, 318 STMMAC_LPI_T(eee_timer)); 319 320 priv->hw->mac->set_eee_timer(priv->hw, 321 STMMAC_DEFAULT_LIT_LS, 322 tx_lpi_timer); 323 } 324 /* Set HW EEE according to the speed */ 325 priv->hw->mac->set_eee_pls(priv->hw, priv->phydev->link); 326 327 ret = true; 328 spin_unlock_irqrestore(&priv->lock, flags); 329 330 pr_debug("stmmac: Energy-Efficient Ethernet initialized\n"); 331 } 332 out: 333 return ret; 334 } 335 336 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 337 * @priv: driver private structure 338 * @entry : descriptor index to be used. 339 * @skb : the socket buffer 340 * Description : 341 * This function will read timestamp from the descriptor & pass it to stack. 342 * and also perform some sanity checks. 343 */ 344 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 345 unsigned int entry, struct sk_buff *skb) 346 { 347 struct skb_shared_hwtstamps shhwtstamp; 348 u64 ns; 349 void *desc = NULL; 350 351 if (!priv->hwts_tx_en) 352 return; 353 354 /* exit if skb doesn't support hw tstamp */ 355 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 356 return; 357 358 if (priv->adv_ts) 359 desc = (priv->dma_etx + entry); 360 else 361 desc = (priv->dma_tx + entry); 362 363 /* check tx tstamp status */ 364 if (!priv->hw->desc->get_tx_timestamp_status((struct dma_desc *)desc)) 365 return; 366 367 /* get the valid tstamp */ 368 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 369 370 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 371 shhwtstamp.hwtstamp = ns_to_ktime(ns); 372 /* pass tstamp to stack */ 373 skb_tstamp_tx(skb, &shhwtstamp); 374 375 return; 376 } 377 378 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 379 * @priv: driver private structure 380 * @entry : descriptor index to be used. 381 * @skb : the socket buffer 382 * Description : 383 * This function will read received packet's timestamp from the descriptor 384 * and pass it to stack. It also perform some sanity checks. 385 */ 386 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, 387 unsigned int entry, struct sk_buff *skb) 388 { 389 struct skb_shared_hwtstamps *shhwtstamp = NULL; 390 u64 ns; 391 void *desc = NULL; 392 393 if (!priv->hwts_rx_en) 394 return; 395 396 if (priv->adv_ts) 397 desc = (priv->dma_erx + entry); 398 else 399 desc = (priv->dma_rx + entry); 400 401 /* exit if rx tstamp is not valid */ 402 if (!priv->hw->desc->get_rx_timestamp_status(desc, priv->adv_ts)) 403 return; 404 405 /* get valid tstamp */ 406 ns = priv->hw->desc->get_timestamp(desc, priv->adv_ts); 407 shhwtstamp = skb_hwtstamps(skb); 408 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 409 shhwtstamp->hwtstamp = ns_to_ktime(ns); 410 } 411 412 /** 413 * stmmac_hwtstamp_ioctl - control hardware timestamping. 414 * @dev: device pointer. 415 * @ifr: An IOCTL specefic structure, that can contain a pointer to 416 * a proprietary structure used to pass information to the driver. 417 * Description: 418 * This function configures the MAC to enable/disable both outgoing(TX) 419 * and incoming(RX) packets time stamping based on user input. 420 * Return Value: 421 * 0 on success and an appropriate -ve integer on failure. 422 */ 423 static int stmmac_hwtstamp_ioctl(struct net_device *dev, struct ifreq *ifr) 424 { 425 struct stmmac_priv *priv = netdev_priv(dev); 426 struct hwtstamp_config config; 427 struct timespec now; 428 u64 temp = 0; 429 u32 ptp_v2 = 0; 430 u32 tstamp_all = 0; 431 u32 ptp_over_ipv4_udp = 0; 432 u32 ptp_over_ipv6_udp = 0; 433 u32 ptp_over_ethernet = 0; 434 u32 snap_type_sel = 0; 435 u32 ts_master_en = 0; 436 u32 ts_event_en = 0; 437 u32 value = 0; 438 439 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 440 netdev_alert(priv->dev, "No support for HW time stamping\n"); 441 priv->hwts_tx_en = 0; 442 priv->hwts_rx_en = 0; 443 444 return -EOPNOTSUPP; 445 } 446 447 if (copy_from_user(&config, ifr->ifr_data, 448 sizeof(struct hwtstamp_config))) 449 return -EFAULT; 450 451 pr_debug("%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 452 __func__, config.flags, config.tx_type, config.rx_filter); 453 454 /* reserved for future extensions */ 455 if (config.flags) 456 return -EINVAL; 457 458 if (config.tx_type != HWTSTAMP_TX_OFF && 459 config.tx_type != HWTSTAMP_TX_ON) 460 return -ERANGE; 461 462 if (priv->adv_ts) { 463 switch (config.rx_filter) { 464 case HWTSTAMP_FILTER_NONE: 465 /* time stamp no incoming packet at all */ 466 config.rx_filter = HWTSTAMP_FILTER_NONE; 467 break; 468 469 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 470 /* PTP v1, UDP, any kind of event packet */ 471 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 472 /* take time stamp for all event messages */ 473 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 474 475 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 476 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 477 break; 478 479 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 480 /* PTP v1, UDP, Sync packet */ 481 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 482 /* take time stamp for SYNC messages only */ 483 ts_event_en = PTP_TCR_TSEVNTENA; 484 485 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 486 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 487 break; 488 489 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 490 /* PTP v1, UDP, Delay_req packet */ 491 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 492 /* take time stamp for Delay_Req messages only */ 493 ts_master_en = PTP_TCR_TSMSTRENA; 494 ts_event_en = PTP_TCR_TSEVNTENA; 495 496 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 497 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 498 break; 499 500 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 501 /* PTP v2, UDP, any kind of event packet */ 502 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 503 ptp_v2 = PTP_TCR_TSVER2ENA; 504 /* take time stamp for all event messages */ 505 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 506 507 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 508 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 509 break; 510 511 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 512 /* PTP v2, UDP, Sync packet */ 513 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 514 ptp_v2 = PTP_TCR_TSVER2ENA; 515 /* take time stamp for SYNC messages only */ 516 ts_event_en = PTP_TCR_TSEVNTENA; 517 518 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 519 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 520 break; 521 522 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 523 /* PTP v2, UDP, Delay_req packet */ 524 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 525 ptp_v2 = PTP_TCR_TSVER2ENA; 526 /* take time stamp for Delay_Req messages only */ 527 ts_master_en = PTP_TCR_TSMSTRENA; 528 ts_event_en = PTP_TCR_TSEVNTENA; 529 530 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 531 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 532 break; 533 534 case HWTSTAMP_FILTER_PTP_V2_EVENT: 535 /* PTP v2/802.AS1 any layer, any kind of event packet */ 536 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 537 ptp_v2 = PTP_TCR_TSVER2ENA; 538 /* take time stamp for all event messages */ 539 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 540 541 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 542 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 543 ptp_over_ethernet = PTP_TCR_TSIPENA; 544 break; 545 546 case HWTSTAMP_FILTER_PTP_V2_SYNC: 547 /* PTP v2/802.AS1, any layer, Sync packet */ 548 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 549 ptp_v2 = PTP_TCR_TSVER2ENA; 550 /* take time stamp for SYNC messages only */ 551 ts_event_en = PTP_TCR_TSEVNTENA; 552 553 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 554 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 555 ptp_over_ethernet = PTP_TCR_TSIPENA; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 559 /* PTP v2/802.AS1, any layer, Delay_req packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 561 ptp_v2 = PTP_TCR_TSVER2ENA; 562 /* take time stamp for Delay_Req messages only */ 563 ts_master_en = PTP_TCR_TSMSTRENA; 564 ts_event_en = PTP_TCR_TSEVNTENA; 565 566 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 567 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 568 ptp_over_ethernet = PTP_TCR_TSIPENA; 569 break; 570 571 case HWTSTAMP_FILTER_ALL: 572 /* time stamp any incoming packet */ 573 config.rx_filter = HWTSTAMP_FILTER_ALL; 574 tstamp_all = PTP_TCR_TSENALL; 575 break; 576 577 default: 578 return -ERANGE; 579 } 580 } else { 581 switch (config.rx_filter) { 582 case HWTSTAMP_FILTER_NONE: 583 config.rx_filter = HWTSTAMP_FILTER_NONE; 584 break; 585 default: 586 /* PTP v1, UDP, any kind of event packet */ 587 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 588 break; 589 } 590 } 591 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 592 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 593 594 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 595 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, 0); 596 else { 597 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 598 tstamp_all | ptp_v2 | ptp_over_ethernet | 599 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 600 ts_master_en | snap_type_sel); 601 602 priv->hw->ptp->config_hw_tstamping(priv->ioaddr, value); 603 604 /* program Sub Second Increment reg */ 605 priv->hw->ptp->config_sub_second_increment(priv->ioaddr); 606 607 /* calculate default added value: 608 * formula is : 609 * addend = (2^32)/freq_div_ratio; 610 * where, freq_div_ratio = clk_ptp_ref_i/50MHz 611 * hence, addend = ((2^32) * 50MHz)/clk_ptp_ref_i; 612 * NOTE: clk_ptp_ref_i should be >= 50MHz to 613 * achieve 20ns accuracy. 614 * 615 * 2^x * y == (y << x), hence 616 * 2^32 * 50000000 ==> (50000000 << 32) 617 */ 618 temp = (u64) (50000000ULL << 32); 619 priv->default_addend = div_u64(temp, priv->clk_ptp_rate); 620 priv->hw->ptp->config_addend(priv->ioaddr, 621 priv->default_addend); 622 623 /* initialize system time */ 624 getnstimeofday(&now); 625 priv->hw->ptp->init_systime(priv->ioaddr, now.tv_sec, 626 now.tv_nsec); 627 } 628 629 return copy_to_user(ifr->ifr_data, &config, 630 sizeof(struct hwtstamp_config)) ? -EFAULT : 0; 631 } 632 633 /** 634 * stmmac_init_ptp - init PTP 635 * @priv: driver private structure 636 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 637 * This is done by looking at the HW cap. register. 638 * This function also registers the ptp driver. 639 */ 640 static int stmmac_init_ptp(struct stmmac_priv *priv) 641 { 642 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 643 return -EOPNOTSUPP; 644 645 /* Fall-back to main clock in case of no PTP ref is passed */ 646 priv->clk_ptp_ref = devm_clk_get(priv->device, "clk_ptp_ref"); 647 if (IS_ERR(priv->clk_ptp_ref)) { 648 priv->clk_ptp_rate = clk_get_rate(priv->stmmac_clk); 649 priv->clk_ptp_ref = NULL; 650 } else { 651 clk_prepare_enable(priv->clk_ptp_ref); 652 priv->clk_ptp_rate = clk_get_rate(priv->clk_ptp_ref); 653 } 654 655 priv->adv_ts = 0; 656 if (priv->dma_cap.atime_stamp && priv->extend_desc) 657 priv->adv_ts = 1; 658 659 if (netif_msg_hw(priv) && priv->dma_cap.time_stamp) 660 pr_debug("IEEE 1588-2002 Time Stamp supported\n"); 661 662 if (netif_msg_hw(priv) && priv->adv_ts) 663 pr_debug("IEEE 1588-2008 Advanced Time Stamp supported\n"); 664 665 priv->hw->ptp = &stmmac_ptp; 666 priv->hwts_tx_en = 0; 667 priv->hwts_rx_en = 0; 668 669 return stmmac_ptp_register(priv); 670 } 671 672 static void stmmac_release_ptp(struct stmmac_priv *priv) 673 { 674 if (priv->clk_ptp_ref) 675 clk_disable_unprepare(priv->clk_ptp_ref); 676 stmmac_ptp_unregister(priv); 677 } 678 679 /** 680 * stmmac_adjust_link - adjusts the link parameters 681 * @dev: net device structure 682 * Description: this is the helper called by the physical abstraction layer 683 * drivers to communicate the phy link status. According the speed and duplex 684 * this driver can invoke registered glue-logic as well. 685 * It also invoke the eee initialization because it could happen when switch 686 * on different networks (that are eee capable). 687 */ 688 static void stmmac_adjust_link(struct net_device *dev) 689 { 690 struct stmmac_priv *priv = netdev_priv(dev); 691 struct phy_device *phydev = priv->phydev; 692 unsigned long flags; 693 int new_state = 0; 694 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 695 696 if (phydev == NULL) 697 return; 698 699 spin_lock_irqsave(&priv->lock, flags); 700 701 if (phydev->link) { 702 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 703 704 /* Now we make sure that we can be in full duplex mode. 705 * If not, we operate in half-duplex mode. */ 706 if (phydev->duplex != priv->oldduplex) { 707 new_state = 1; 708 if (!(phydev->duplex)) 709 ctrl &= ~priv->hw->link.duplex; 710 else 711 ctrl |= priv->hw->link.duplex; 712 priv->oldduplex = phydev->duplex; 713 } 714 /* Flow Control operation */ 715 if (phydev->pause) 716 priv->hw->mac->flow_ctrl(priv->hw, phydev->duplex, 717 fc, pause_time); 718 719 if (phydev->speed != priv->speed) { 720 new_state = 1; 721 switch (phydev->speed) { 722 case 1000: 723 if (likely(priv->plat->has_gmac)) 724 ctrl &= ~priv->hw->link.port; 725 stmmac_hw_fix_mac_speed(priv); 726 break; 727 case 100: 728 case 10: 729 if (priv->plat->has_gmac) { 730 ctrl |= priv->hw->link.port; 731 if (phydev->speed == SPEED_100) { 732 ctrl |= priv->hw->link.speed; 733 } else { 734 ctrl &= ~(priv->hw->link.speed); 735 } 736 } else { 737 ctrl &= ~priv->hw->link.port; 738 } 739 stmmac_hw_fix_mac_speed(priv); 740 break; 741 default: 742 if (netif_msg_link(priv)) 743 pr_warn("%s: Speed (%d) not 10/100\n", 744 dev->name, phydev->speed); 745 break; 746 } 747 748 priv->speed = phydev->speed; 749 } 750 751 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 752 753 if (!priv->oldlink) { 754 new_state = 1; 755 priv->oldlink = 1; 756 } 757 } else if (priv->oldlink) { 758 new_state = 1; 759 priv->oldlink = 0; 760 priv->speed = 0; 761 priv->oldduplex = -1; 762 } 763 764 if (new_state && netif_msg_link(priv)) 765 phy_print_status(phydev); 766 767 spin_unlock_irqrestore(&priv->lock, flags); 768 769 /* At this stage, it could be needed to setup the EEE or adjust some 770 * MAC related HW registers. 771 */ 772 priv->eee_enabled = stmmac_eee_init(priv); 773 } 774 775 /** 776 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 777 * @priv: driver private structure 778 * Description: this is to verify if the HW supports the PCS. 779 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 780 * configured for the TBI, RTBI, or SGMII PHY interface. 781 */ 782 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 783 { 784 int interface = priv->plat->interface; 785 786 if (priv->dma_cap.pcs) { 787 if ((interface == PHY_INTERFACE_MODE_RGMII) || 788 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 789 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 790 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 791 pr_debug("STMMAC: PCS RGMII support enable\n"); 792 priv->pcs = STMMAC_PCS_RGMII; 793 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 794 pr_debug("STMMAC: PCS SGMII support enable\n"); 795 priv->pcs = STMMAC_PCS_SGMII; 796 } 797 } 798 } 799 800 /** 801 * stmmac_init_phy - PHY initialization 802 * @dev: net device structure 803 * Description: it initializes the driver's PHY state, and attaches the PHY 804 * to the mac driver. 805 * Return value: 806 * 0 on success 807 */ 808 static int stmmac_init_phy(struct net_device *dev) 809 { 810 struct stmmac_priv *priv = netdev_priv(dev); 811 struct phy_device *phydev; 812 char phy_id_fmt[MII_BUS_ID_SIZE + 3]; 813 char bus_id[MII_BUS_ID_SIZE]; 814 int interface = priv->plat->interface; 815 int max_speed = priv->plat->max_speed; 816 priv->oldlink = 0; 817 priv->speed = 0; 818 priv->oldduplex = -1; 819 820 if (priv->plat->phy_node) { 821 phydev = of_phy_connect(dev, priv->plat->phy_node, 822 &stmmac_adjust_link, 0, interface); 823 } else { 824 if (priv->plat->phy_bus_name) 825 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 826 priv->plat->phy_bus_name, priv->plat->bus_id); 827 else 828 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 829 priv->plat->bus_id); 830 831 snprintf(phy_id_fmt, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 832 priv->plat->phy_addr); 833 pr_debug("stmmac_init_phy: trying to attach to %s\n", 834 phy_id_fmt); 835 836 phydev = phy_connect(dev, phy_id_fmt, &stmmac_adjust_link, 837 interface); 838 } 839 840 if (IS_ERR_OR_NULL(phydev)) { 841 pr_err("%s: Could not attach to PHY\n", dev->name); 842 if (!phydev) 843 return -ENODEV; 844 845 return PTR_ERR(phydev); 846 } 847 848 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 849 if ((interface == PHY_INTERFACE_MODE_MII) || 850 (interface == PHY_INTERFACE_MODE_RMII) || 851 (max_speed < 1000 && max_speed > 0)) 852 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 853 SUPPORTED_1000baseT_Full); 854 855 /* 856 * Broken HW is sometimes missing the pull-up resistor on the 857 * MDIO line, which results in reads to non-existent devices returning 858 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 859 * device as well. 860 * Note: phydev->phy_id is the result of reading the UID PHY registers. 861 */ 862 if (!priv->plat->phy_node && phydev->phy_id == 0) { 863 phy_disconnect(phydev); 864 return -ENODEV; 865 } 866 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 867 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 868 869 priv->phydev = phydev; 870 871 return 0; 872 } 873 874 /** 875 * stmmac_display_ring - display ring 876 * @head: pointer to the head of the ring passed. 877 * @size: size of the ring. 878 * @extend_desc: to verify if extended descriptors are used. 879 * Description: display the control/status and buffer descriptors. 880 */ 881 static void stmmac_display_ring(void *head, int size, int extend_desc) 882 { 883 int i; 884 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 885 struct dma_desc *p = (struct dma_desc *)head; 886 887 for (i = 0; i < size; i++) { 888 u64 x; 889 if (extend_desc) { 890 x = *(u64 *) ep; 891 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 892 i, (unsigned int)virt_to_phys(ep), 893 (unsigned int)x, (unsigned int)(x >> 32), 894 ep->basic.des2, ep->basic.des3); 895 ep++; 896 } else { 897 x = *(u64 *) p; 898 pr_info("%d [0x%x]: 0x%x 0x%x 0x%x 0x%x", 899 i, (unsigned int)virt_to_phys(p), 900 (unsigned int)x, (unsigned int)(x >> 32), 901 p->des2, p->des3); 902 p++; 903 } 904 pr_info("\n"); 905 } 906 } 907 908 static void stmmac_display_rings(struct stmmac_priv *priv) 909 { 910 unsigned int txsize = priv->dma_tx_size; 911 unsigned int rxsize = priv->dma_rx_size; 912 913 if (priv->extend_desc) { 914 pr_info("Extended RX descriptor ring:\n"); 915 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 916 pr_info("Extended TX descriptor ring:\n"); 917 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 918 } else { 919 pr_info("RX descriptor ring:\n"); 920 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 921 pr_info("TX descriptor ring:\n"); 922 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 923 } 924 } 925 926 static int stmmac_set_bfsize(int mtu, int bufsize) 927 { 928 int ret = bufsize; 929 930 if (mtu >= BUF_SIZE_4KiB) 931 ret = BUF_SIZE_8KiB; 932 else if (mtu >= BUF_SIZE_2KiB) 933 ret = BUF_SIZE_4KiB; 934 else if (mtu > DEFAULT_BUFSIZE) 935 ret = BUF_SIZE_2KiB; 936 else 937 ret = DEFAULT_BUFSIZE; 938 939 return ret; 940 } 941 942 /** 943 * stmmac_clear_descriptors - clear descriptors 944 * @priv: driver private structure 945 * Description: this function is called to clear the tx and rx descriptors 946 * in case of both basic and extended descriptors are used. 947 */ 948 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 949 { 950 int i; 951 unsigned int txsize = priv->dma_tx_size; 952 unsigned int rxsize = priv->dma_rx_size; 953 954 /* Clear the Rx/Tx descriptors */ 955 for (i = 0; i < rxsize; i++) 956 if (priv->extend_desc) 957 priv->hw->desc->init_rx_desc(&priv->dma_erx[i].basic, 958 priv->use_riwt, priv->mode, 959 (i == rxsize - 1)); 960 else 961 priv->hw->desc->init_rx_desc(&priv->dma_rx[i], 962 priv->use_riwt, priv->mode, 963 (i == rxsize - 1)); 964 for (i = 0; i < txsize; i++) 965 if (priv->extend_desc) 966 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 967 priv->mode, 968 (i == txsize - 1)); 969 else 970 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 971 priv->mode, 972 (i == txsize - 1)); 973 } 974 975 /** 976 * stmmac_init_rx_buffers - init the RX descriptor buffer. 977 * @priv: driver private structure 978 * @p: descriptor pointer 979 * @i: descriptor index 980 * @flags: gfp flag. 981 * Description: this function is called to allocate a receive buffer, perform 982 * the DMA mapping and init the descriptor. 983 */ 984 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 985 int i, gfp_t flags) 986 { 987 struct sk_buff *skb; 988 989 skb = __netdev_alloc_skb_ip_align(priv->dev, priv->dma_buf_sz, flags); 990 if (!skb) { 991 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 992 return -ENOMEM; 993 } 994 priv->rx_skbuff[i] = skb; 995 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 996 priv->dma_buf_sz, 997 DMA_FROM_DEVICE); 998 if (dma_mapping_error(priv->device, priv->rx_skbuff_dma[i])) { 999 pr_err("%s: DMA mapping error\n", __func__); 1000 dev_kfree_skb_any(skb); 1001 return -EINVAL; 1002 } 1003 1004 p->des2 = priv->rx_skbuff_dma[i]; 1005 1006 if ((priv->hw->mode->init_desc3) && 1007 (priv->dma_buf_sz == BUF_SIZE_16KiB)) 1008 priv->hw->mode->init_desc3(p); 1009 1010 return 0; 1011 } 1012 1013 static void stmmac_free_rx_buffers(struct stmmac_priv *priv, int i) 1014 { 1015 if (priv->rx_skbuff[i]) { 1016 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 1017 priv->dma_buf_sz, DMA_FROM_DEVICE); 1018 dev_kfree_skb_any(priv->rx_skbuff[i]); 1019 } 1020 priv->rx_skbuff[i] = NULL; 1021 } 1022 1023 /** 1024 * init_dma_desc_rings - init the RX/TX descriptor rings 1025 * @dev: net device structure 1026 * @flags: gfp flag. 1027 * Description: this function initializes the DMA RX/TX descriptors 1028 * and allocates the socket buffers. It suppors the chained and ring 1029 * modes. 1030 */ 1031 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1032 { 1033 int i; 1034 struct stmmac_priv *priv = netdev_priv(dev); 1035 unsigned int txsize = priv->dma_tx_size; 1036 unsigned int rxsize = priv->dma_rx_size; 1037 unsigned int bfsize = 0; 1038 int ret = -ENOMEM; 1039 1040 if (priv->hw->mode->set_16kib_bfsize) 1041 bfsize = priv->hw->mode->set_16kib_bfsize(dev->mtu); 1042 1043 if (bfsize < BUF_SIZE_16KiB) 1044 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1045 1046 priv->dma_buf_sz = bfsize; 1047 1048 if (netif_msg_probe(priv)) 1049 pr_debug("%s: txsize %d, rxsize %d, bfsize %d\n", __func__, 1050 txsize, rxsize, bfsize); 1051 1052 if (netif_msg_probe(priv)) { 1053 pr_debug("(%s) dma_rx_phy=0x%08x dma_tx_phy=0x%08x\n", __func__, 1054 (u32) priv->dma_rx_phy, (u32) priv->dma_tx_phy); 1055 1056 /* RX INITIALIZATION */ 1057 pr_debug("\tSKB addresses:\nskb\t\tskb data\tdma data\n"); 1058 } 1059 for (i = 0; i < rxsize; i++) { 1060 struct dma_desc *p; 1061 if (priv->extend_desc) 1062 p = &((priv->dma_erx + i)->basic); 1063 else 1064 p = priv->dma_rx + i; 1065 1066 ret = stmmac_init_rx_buffers(priv, p, i, flags); 1067 if (ret) 1068 goto err_init_rx_buffers; 1069 1070 if (netif_msg_probe(priv)) 1071 pr_debug("[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 1072 priv->rx_skbuff[i]->data, 1073 (unsigned int)priv->rx_skbuff_dma[i]); 1074 } 1075 priv->cur_rx = 0; 1076 priv->dirty_rx = (unsigned int)(i - rxsize); 1077 buf_sz = bfsize; 1078 1079 /* Setup the chained descriptor addresses */ 1080 if (priv->mode == STMMAC_CHAIN_MODE) { 1081 if (priv->extend_desc) { 1082 priv->hw->mode->init(priv->dma_erx, priv->dma_rx_phy, 1083 rxsize, 1); 1084 priv->hw->mode->init(priv->dma_etx, priv->dma_tx_phy, 1085 txsize, 1); 1086 } else { 1087 priv->hw->mode->init(priv->dma_rx, priv->dma_rx_phy, 1088 rxsize, 0); 1089 priv->hw->mode->init(priv->dma_tx, priv->dma_tx_phy, 1090 txsize, 0); 1091 } 1092 } 1093 1094 /* TX INITIALIZATION */ 1095 for (i = 0; i < txsize; i++) { 1096 struct dma_desc *p; 1097 if (priv->extend_desc) 1098 p = &((priv->dma_etx + i)->basic); 1099 else 1100 p = priv->dma_tx + i; 1101 p->des2 = 0; 1102 priv->tx_skbuff_dma[i].buf = 0; 1103 priv->tx_skbuff_dma[i].map_as_page = false; 1104 priv->tx_skbuff[i] = NULL; 1105 } 1106 1107 priv->dirty_tx = 0; 1108 priv->cur_tx = 0; 1109 netdev_reset_queue(priv->dev); 1110 1111 stmmac_clear_descriptors(priv); 1112 1113 if (netif_msg_hw(priv)) 1114 stmmac_display_rings(priv); 1115 1116 return 0; 1117 err_init_rx_buffers: 1118 while (--i >= 0) 1119 stmmac_free_rx_buffers(priv, i); 1120 return ret; 1121 } 1122 1123 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 1124 { 1125 int i; 1126 1127 for (i = 0; i < priv->dma_rx_size; i++) 1128 stmmac_free_rx_buffers(priv, i); 1129 } 1130 1131 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 1132 { 1133 int i; 1134 1135 for (i = 0; i < priv->dma_tx_size; i++) { 1136 struct dma_desc *p; 1137 1138 if (priv->extend_desc) 1139 p = &((priv->dma_etx + i)->basic); 1140 else 1141 p = priv->dma_tx + i; 1142 1143 if (priv->tx_skbuff_dma[i].buf) { 1144 if (priv->tx_skbuff_dma[i].map_as_page) 1145 dma_unmap_page(priv->device, 1146 priv->tx_skbuff_dma[i].buf, 1147 priv->hw->desc->get_tx_len(p), 1148 DMA_TO_DEVICE); 1149 else 1150 dma_unmap_single(priv->device, 1151 priv->tx_skbuff_dma[i].buf, 1152 priv->hw->desc->get_tx_len(p), 1153 DMA_TO_DEVICE); 1154 } 1155 1156 if (priv->tx_skbuff[i] != NULL) { 1157 dev_kfree_skb_any(priv->tx_skbuff[i]); 1158 priv->tx_skbuff[i] = NULL; 1159 priv->tx_skbuff_dma[i].buf = 0; 1160 priv->tx_skbuff_dma[i].map_as_page = false; 1161 } 1162 } 1163 } 1164 1165 /** 1166 * alloc_dma_desc_resources - alloc TX/RX resources. 1167 * @priv: private structure 1168 * Description: according to which descriptor can be used (extend or basic) 1169 * this function allocates the resources for TX and RX paths. In case of 1170 * reception, for example, it pre-allocated the RX socket buffer in order to 1171 * allow zero-copy mechanism. 1172 */ 1173 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1174 { 1175 unsigned int txsize = priv->dma_tx_size; 1176 unsigned int rxsize = priv->dma_rx_size; 1177 int ret = -ENOMEM; 1178 1179 priv->rx_skbuff_dma = kmalloc_array(rxsize, sizeof(dma_addr_t), 1180 GFP_KERNEL); 1181 if (!priv->rx_skbuff_dma) 1182 return -ENOMEM; 1183 1184 priv->rx_skbuff = kmalloc_array(rxsize, sizeof(struct sk_buff *), 1185 GFP_KERNEL); 1186 if (!priv->rx_skbuff) 1187 goto err_rx_skbuff; 1188 1189 priv->tx_skbuff_dma = kmalloc_array(txsize, 1190 sizeof(*priv->tx_skbuff_dma), 1191 GFP_KERNEL); 1192 if (!priv->tx_skbuff_dma) 1193 goto err_tx_skbuff_dma; 1194 1195 priv->tx_skbuff = kmalloc_array(txsize, sizeof(struct sk_buff *), 1196 GFP_KERNEL); 1197 if (!priv->tx_skbuff) 1198 goto err_tx_skbuff; 1199 1200 if (priv->extend_desc) { 1201 priv->dma_erx = dma_zalloc_coherent(priv->device, rxsize * 1202 sizeof(struct 1203 dma_extended_desc), 1204 &priv->dma_rx_phy, 1205 GFP_KERNEL); 1206 if (!priv->dma_erx) 1207 goto err_dma; 1208 1209 priv->dma_etx = dma_zalloc_coherent(priv->device, txsize * 1210 sizeof(struct 1211 dma_extended_desc), 1212 &priv->dma_tx_phy, 1213 GFP_KERNEL); 1214 if (!priv->dma_etx) { 1215 dma_free_coherent(priv->device, priv->dma_rx_size * 1216 sizeof(struct dma_extended_desc), 1217 priv->dma_erx, priv->dma_rx_phy); 1218 goto err_dma; 1219 } 1220 } else { 1221 priv->dma_rx = dma_zalloc_coherent(priv->device, rxsize * 1222 sizeof(struct dma_desc), 1223 &priv->dma_rx_phy, 1224 GFP_KERNEL); 1225 if (!priv->dma_rx) 1226 goto err_dma; 1227 1228 priv->dma_tx = dma_zalloc_coherent(priv->device, txsize * 1229 sizeof(struct dma_desc), 1230 &priv->dma_tx_phy, 1231 GFP_KERNEL); 1232 if (!priv->dma_tx) { 1233 dma_free_coherent(priv->device, priv->dma_rx_size * 1234 sizeof(struct dma_desc), 1235 priv->dma_rx, priv->dma_rx_phy); 1236 goto err_dma; 1237 } 1238 } 1239 1240 return 0; 1241 1242 err_dma: 1243 kfree(priv->tx_skbuff); 1244 err_tx_skbuff: 1245 kfree(priv->tx_skbuff_dma); 1246 err_tx_skbuff_dma: 1247 kfree(priv->rx_skbuff); 1248 err_rx_skbuff: 1249 kfree(priv->rx_skbuff_dma); 1250 return ret; 1251 } 1252 1253 static void free_dma_desc_resources(struct stmmac_priv *priv) 1254 { 1255 /* Release the DMA TX/RX socket buffers */ 1256 dma_free_rx_skbufs(priv); 1257 dma_free_tx_skbufs(priv); 1258 1259 /* Free DMA regions of consistent memory previously allocated */ 1260 if (!priv->extend_desc) { 1261 dma_free_coherent(priv->device, 1262 priv->dma_tx_size * sizeof(struct dma_desc), 1263 priv->dma_tx, priv->dma_tx_phy); 1264 dma_free_coherent(priv->device, 1265 priv->dma_rx_size * sizeof(struct dma_desc), 1266 priv->dma_rx, priv->dma_rx_phy); 1267 } else { 1268 dma_free_coherent(priv->device, priv->dma_tx_size * 1269 sizeof(struct dma_extended_desc), 1270 priv->dma_etx, priv->dma_tx_phy); 1271 dma_free_coherent(priv->device, priv->dma_rx_size * 1272 sizeof(struct dma_extended_desc), 1273 priv->dma_erx, priv->dma_rx_phy); 1274 } 1275 kfree(priv->rx_skbuff_dma); 1276 kfree(priv->rx_skbuff); 1277 kfree(priv->tx_skbuff_dma); 1278 kfree(priv->tx_skbuff); 1279 } 1280 1281 /** 1282 * stmmac_dma_operation_mode - HW DMA operation mode 1283 * @priv: driver private structure 1284 * Description: it is used for configuring the DMA operation mode register in 1285 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1286 */ 1287 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1288 { 1289 int rxfifosz = priv->plat->rx_fifo_size; 1290 1291 if (priv->plat->force_thresh_dma_mode) 1292 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, rxfifosz); 1293 else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1294 /* 1295 * In case of GMAC, SF mode can be enabled 1296 * to perform the TX COE in HW. This depends on: 1297 * 1) TX COE if actually supported 1298 * 2) There is no bugged Jumbo frame support 1299 * that needs to not insert csum in the TDES. 1300 */ 1301 priv->hw->dma->dma_mode(priv->ioaddr, SF_DMA_MODE, SF_DMA_MODE, 1302 rxfifosz); 1303 priv->xstats.threshold = SF_DMA_MODE; 1304 } else 1305 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE, 1306 rxfifosz); 1307 } 1308 1309 /** 1310 * stmmac_tx_clean - to manage the transmission completion 1311 * @priv: driver private structure 1312 * Description: it reclaims the transmit resources after transmission completes. 1313 */ 1314 static void stmmac_tx_clean(struct stmmac_priv *priv) 1315 { 1316 unsigned int txsize = priv->dma_tx_size; 1317 unsigned int bytes_compl = 0, pkts_compl = 0; 1318 1319 spin_lock(&priv->tx_lock); 1320 1321 priv->xstats.tx_clean++; 1322 1323 while (priv->dirty_tx != priv->cur_tx) { 1324 int last; 1325 unsigned int entry = priv->dirty_tx % txsize; 1326 struct sk_buff *skb = priv->tx_skbuff[entry]; 1327 struct dma_desc *p; 1328 1329 if (priv->extend_desc) 1330 p = (struct dma_desc *)(priv->dma_etx + entry); 1331 else 1332 p = priv->dma_tx + entry; 1333 1334 /* Check if the descriptor is owned by the DMA. */ 1335 if (priv->hw->desc->get_tx_owner(p)) 1336 break; 1337 1338 /* Verify tx error by looking at the last segment. */ 1339 last = priv->hw->desc->get_tx_ls(p); 1340 if (likely(last)) { 1341 int tx_error = 1342 priv->hw->desc->tx_status(&priv->dev->stats, 1343 &priv->xstats, p, 1344 priv->ioaddr); 1345 if (likely(tx_error == 0)) { 1346 priv->dev->stats.tx_packets++; 1347 priv->xstats.tx_pkt_n++; 1348 } else 1349 priv->dev->stats.tx_errors++; 1350 1351 stmmac_get_tx_hwtstamp(priv, entry, skb); 1352 } 1353 if (netif_msg_tx_done(priv)) 1354 pr_debug("%s: curr %d, dirty %d\n", __func__, 1355 priv->cur_tx, priv->dirty_tx); 1356 1357 if (likely(priv->tx_skbuff_dma[entry].buf)) { 1358 if (priv->tx_skbuff_dma[entry].map_as_page) 1359 dma_unmap_page(priv->device, 1360 priv->tx_skbuff_dma[entry].buf, 1361 priv->hw->desc->get_tx_len(p), 1362 DMA_TO_DEVICE); 1363 else 1364 dma_unmap_single(priv->device, 1365 priv->tx_skbuff_dma[entry].buf, 1366 priv->hw->desc->get_tx_len(p), 1367 DMA_TO_DEVICE); 1368 priv->tx_skbuff_dma[entry].buf = 0; 1369 priv->tx_skbuff_dma[entry].map_as_page = false; 1370 } 1371 priv->hw->mode->clean_desc3(priv, p); 1372 1373 if (likely(skb != NULL)) { 1374 pkts_compl++; 1375 bytes_compl += skb->len; 1376 dev_consume_skb_any(skb); 1377 priv->tx_skbuff[entry] = NULL; 1378 } 1379 1380 priv->hw->desc->release_tx_desc(p, priv->mode); 1381 1382 priv->dirty_tx++; 1383 } 1384 1385 netdev_completed_queue(priv->dev, pkts_compl, bytes_compl); 1386 1387 if (unlikely(netif_queue_stopped(priv->dev) && 1388 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 1389 netif_tx_lock(priv->dev); 1390 if (netif_queue_stopped(priv->dev) && 1391 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 1392 if (netif_msg_tx_done(priv)) 1393 pr_debug("%s: restart transmit\n", __func__); 1394 netif_wake_queue(priv->dev); 1395 } 1396 netif_tx_unlock(priv->dev); 1397 } 1398 1399 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1400 stmmac_enable_eee_mode(priv); 1401 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1402 } 1403 spin_unlock(&priv->tx_lock); 1404 } 1405 1406 static inline void stmmac_enable_dma_irq(struct stmmac_priv *priv) 1407 { 1408 priv->hw->dma->enable_dma_irq(priv->ioaddr); 1409 } 1410 1411 static inline void stmmac_disable_dma_irq(struct stmmac_priv *priv) 1412 { 1413 priv->hw->dma->disable_dma_irq(priv->ioaddr); 1414 } 1415 1416 /** 1417 * stmmac_tx_err - to manage the tx error 1418 * @priv: driver private structure 1419 * Description: it cleans the descriptors and restarts the transmission 1420 * in case of transmission errors. 1421 */ 1422 static void stmmac_tx_err(struct stmmac_priv *priv) 1423 { 1424 int i; 1425 int txsize = priv->dma_tx_size; 1426 netif_stop_queue(priv->dev); 1427 1428 priv->hw->dma->stop_tx(priv->ioaddr); 1429 dma_free_tx_skbufs(priv); 1430 for (i = 0; i < txsize; i++) 1431 if (priv->extend_desc) 1432 priv->hw->desc->init_tx_desc(&priv->dma_etx[i].basic, 1433 priv->mode, 1434 (i == txsize - 1)); 1435 else 1436 priv->hw->desc->init_tx_desc(&priv->dma_tx[i], 1437 priv->mode, 1438 (i == txsize - 1)); 1439 priv->dirty_tx = 0; 1440 priv->cur_tx = 0; 1441 netdev_reset_queue(priv->dev); 1442 priv->hw->dma->start_tx(priv->ioaddr); 1443 1444 priv->dev->stats.tx_errors++; 1445 netif_wake_queue(priv->dev); 1446 } 1447 1448 /** 1449 * stmmac_dma_interrupt - DMA ISR 1450 * @priv: driver private structure 1451 * Description: this is the DMA ISR. It is called by the main ISR. 1452 * It calls the dwmac dma routine and schedule poll method in case of some 1453 * work can be done. 1454 */ 1455 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 1456 { 1457 int status; 1458 int rxfifosz = priv->plat->rx_fifo_size; 1459 1460 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 1461 if (likely((status & handle_rx)) || (status & handle_tx)) { 1462 if (likely(napi_schedule_prep(&priv->napi))) { 1463 stmmac_disable_dma_irq(priv); 1464 __napi_schedule(&priv->napi); 1465 } 1466 } 1467 if (unlikely(status & tx_hard_error_bump_tc)) { 1468 /* Try to bump up the dma threshold on this failure */ 1469 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 1470 (tc <= 256)) { 1471 tc += 64; 1472 if (priv->plat->force_thresh_dma_mode) 1473 priv->hw->dma->dma_mode(priv->ioaddr, tc, tc, 1474 rxfifosz); 1475 else 1476 priv->hw->dma->dma_mode(priv->ioaddr, tc, 1477 SF_DMA_MODE, rxfifosz); 1478 priv->xstats.threshold = tc; 1479 } 1480 } else if (unlikely(status == tx_hard_error)) 1481 stmmac_tx_err(priv); 1482 } 1483 1484 /** 1485 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 1486 * @priv: driver private structure 1487 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 1488 */ 1489 static void stmmac_mmc_setup(struct stmmac_priv *priv) 1490 { 1491 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 1492 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 1493 1494 dwmac_mmc_intr_all_mask(priv->ioaddr); 1495 1496 if (priv->dma_cap.rmon) { 1497 dwmac_mmc_ctrl(priv->ioaddr, mode); 1498 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 1499 } else 1500 pr_info(" No MAC Management Counters available\n"); 1501 } 1502 1503 /** 1504 * stmmac_get_synopsys_id - return the SYINID. 1505 * @priv: driver private structure 1506 * Description: this simple function is to decode and return the SYINID 1507 * starting from the HW core register. 1508 */ 1509 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 1510 { 1511 u32 hwid = priv->hw->synopsys_uid; 1512 1513 /* Check Synopsys Id (not available on old chips) */ 1514 if (likely(hwid)) { 1515 u32 uid = ((hwid & 0x0000ff00) >> 8); 1516 u32 synid = (hwid & 0x000000ff); 1517 1518 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 1519 uid, synid); 1520 1521 return synid; 1522 } 1523 return 0; 1524 } 1525 1526 /** 1527 * stmmac_selec_desc_mode - to select among: normal/alternate/extend descriptors 1528 * @priv: driver private structure 1529 * Description: select the Enhanced/Alternate or Normal descriptors. 1530 * In case of Enhanced/Alternate, it checks if the extended descriptors are 1531 * supported by the HW capability register. 1532 */ 1533 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 1534 { 1535 if (priv->plat->enh_desc) { 1536 pr_info(" Enhanced/Alternate descriptors\n"); 1537 1538 /* GMAC older than 3.50 has no extended descriptors */ 1539 if (priv->synopsys_id >= DWMAC_CORE_3_50) { 1540 pr_info("\tEnabled extended descriptors\n"); 1541 priv->extend_desc = 1; 1542 } else 1543 pr_warn("Extended descriptors not supported\n"); 1544 1545 priv->hw->desc = &enh_desc_ops; 1546 } else { 1547 pr_info(" Normal descriptors\n"); 1548 priv->hw->desc = &ndesc_ops; 1549 } 1550 } 1551 1552 /** 1553 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 1554 * @priv: driver private structure 1555 * Description: 1556 * new GMAC chip generations have a new register to indicate the 1557 * presence of the optional feature/functions. 1558 * This can be also used to override the value passed through the 1559 * platform and necessary for old MAC10/100 and GMAC chips. 1560 */ 1561 static int stmmac_get_hw_features(struct stmmac_priv *priv) 1562 { 1563 u32 hw_cap = 0; 1564 1565 if (priv->hw->dma->get_hw_feature) { 1566 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 1567 1568 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 1569 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 1570 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 1571 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 1572 priv->dma_cap.multi_addr = (hw_cap & DMA_HW_FEAT_ADDMAC) >> 5; 1573 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 1574 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 1575 priv->dma_cap.pmt_remote_wake_up = 1576 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 1577 priv->dma_cap.pmt_magic_frame = 1578 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 1579 /* MMC */ 1580 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 1581 /* IEEE 1588-2002 */ 1582 priv->dma_cap.time_stamp = 1583 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 1584 /* IEEE 1588-2008 */ 1585 priv->dma_cap.atime_stamp = 1586 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 1587 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 1588 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 1589 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 1590 /* TX and RX csum */ 1591 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 1592 priv->dma_cap.rx_coe_type1 = 1593 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 1594 priv->dma_cap.rx_coe_type2 = 1595 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 1596 priv->dma_cap.rxfifo_over_2048 = 1597 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 1598 /* TX and RX number of channels */ 1599 priv->dma_cap.number_rx_channel = 1600 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 1601 priv->dma_cap.number_tx_channel = 1602 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 1603 /* Alternate (enhanced) DESC mode */ 1604 priv->dma_cap.enh_desc = (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 1605 } 1606 1607 return hw_cap; 1608 } 1609 1610 /** 1611 * stmmac_check_ether_addr - check if the MAC addr is valid 1612 * @priv: driver private structure 1613 * Description: 1614 * it is to verify if the MAC address is valid, in case of failures it 1615 * generates a random MAC address 1616 */ 1617 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 1618 { 1619 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 1620 priv->hw->mac->get_umac_addr(priv->hw, 1621 priv->dev->dev_addr, 0); 1622 if (!is_valid_ether_addr(priv->dev->dev_addr)) 1623 eth_hw_addr_random(priv->dev); 1624 pr_info("%s: device MAC address %pM\n", priv->dev->name, 1625 priv->dev->dev_addr); 1626 } 1627 } 1628 1629 /** 1630 * stmmac_init_dma_engine - DMA init. 1631 * @priv: driver private structure 1632 * Description: 1633 * It inits the DMA invoking the specific MAC/GMAC callback. 1634 * Some DMA parameters can be passed from the platform; 1635 * in case of these are not passed a default is kept for the MAC or GMAC. 1636 */ 1637 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 1638 { 1639 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 1640 int mixed_burst = 0; 1641 int atds = 0; 1642 1643 if (priv->plat->dma_cfg) { 1644 pbl = priv->plat->dma_cfg->pbl; 1645 fixed_burst = priv->plat->dma_cfg->fixed_burst; 1646 mixed_burst = priv->plat->dma_cfg->mixed_burst; 1647 burst_len = priv->plat->dma_cfg->burst_len; 1648 } 1649 1650 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 1651 atds = 1; 1652 1653 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 1654 burst_len, priv->dma_tx_phy, 1655 priv->dma_rx_phy, atds); 1656 } 1657 1658 /** 1659 * stmmac_tx_timer - mitigation sw timer for tx. 1660 * @data: data pointer 1661 * Description: 1662 * This is the timer handler to directly invoke the stmmac_tx_clean. 1663 */ 1664 static void stmmac_tx_timer(unsigned long data) 1665 { 1666 struct stmmac_priv *priv = (struct stmmac_priv *)data; 1667 1668 stmmac_tx_clean(priv); 1669 } 1670 1671 /** 1672 * stmmac_init_tx_coalesce - init tx mitigation options. 1673 * @priv: driver private structure 1674 * Description: 1675 * This inits the transmit coalesce parameters: i.e. timer rate, 1676 * timer handler and default threshold used for enabling the 1677 * interrupt on completion bit. 1678 */ 1679 static void stmmac_init_tx_coalesce(struct stmmac_priv *priv) 1680 { 1681 priv->tx_coal_frames = STMMAC_TX_FRAMES; 1682 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 1683 init_timer(&priv->txtimer); 1684 priv->txtimer.expires = STMMAC_COAL_TIMER(priv->tx_coal_timer); 1685 priv->txtimer.data = (unsigned long)priv; 1686 priv->txtimer.function = stmmac_tx_timer; 1687 add_timer(&priv->txtimer); 1688 } 1689 1690 /** 1691 * stmmac_hw_setup - setup mac in a usable state. 1692 * @dev : pointer to the device structure. 1693 * Description: 1694 * this is the main function to setup the HW in a usable state because the 1695 * dma engine is reset, the core registers are configured (e.g. AXI, 1696 * Checksum features, timers). The DMA is ready to start receiving and 1697 * transmitting. 1698 * Return value: 1699 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1700 * file on failure. 1701 */ 1702 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 1703 { 1704 struct stmmac_priv *priv = netdev_priv(dev); 1705 int ret; 1706 1707 /* DMA initialization and SW reset */ 1708 ret = stmmac_init_dma_engine(priv); 1709 if (ret < 0) { 1710 pr_err("%s: DMA engine initialization failed\n", __func__); 1711 return ret; 1712 } 1713 1714 /* Copy the MAC addr into the HW */ 1715 priv->hw->mac->set_umac_addr(priv->hw, dev->dev_addr, 0); 1716 1717 /* If required, perform hw setup of the bus. */ 1718 if (priv->plat->bus_setup) 1719 priv->plat->bus_setup(priv->ioaddr); 1720 1721 /* Initialize the MAC Core */ 1722 priv->hw->mac->core_init(priv->hw, dev->mtu); 1723 1724 ret = priv->hw->mac->rx_ipc(priv->hw); 1725 if (!ret) { 1726 pr_warn(" RX IPC Checksum Offload disabled\n"); 1727 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1728 priv->hw->rx_csum = 0; 1729 } 1730 1731 /* Enable the MAC Rx/Tx */ 1732 stmmac_set_mac(priv->ioaddr, true); 1733 1734 /* Set the HW DMA mode and the COE */ 1735 stmmac_dma_operation_mode(priv); 1736 1737 stmmac_mmc_setup(priv); 1738 1739 if (init_ptp) { 1740 ret = stmmac_init_ptp(priv); 1741 if (ret && ret != -EOPNOTSUPP) 1742 pr_warn("%s: failed PTP initialisation\n", __func__); 1743 } 1744 1745 #ifdef CONFIG_DEBUG_FS 1746 ret = stmmac_init_fs(dev); 1747 if (ret < 0) 1748 pr_warn("%s: failed debugFS registration\n", __func__); 1749 #endif 1750 /* Start the ball rolling... */ 1751 pr_debug("%s: DMA RX/TX processes started...\n", dev->name); 1752 priv->hw->dma->start_tx(priv->ioaddr); 1753 priv->hw->dma->start_rx(priv->ioaddr); 1754 1755 /* Dump DMA/MAC registers */ 1756 if (netif_msg_hw(priv)) { 1757 priv->hw->mac->dump_regs(priv->hw); 1758 priv->hw->dma->dump_regs(priv->ioaddr); 1759 } 1760 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 1761 1762 if ((priv->use_riwt) && (priv->hw->dma->rx_watchdog)) { 1763 priv->rx_riwt = MAX_DMA_RIWT; 1764 priv->hw->dma->rx_watchdog(priv->ioaddr, MAX_DMA_RIWT); 1765 } 1766 1767 if (priv->pcs && priv->hw->mac->ctrl_ane) 1768 priv->hw->mac->ctrl_ane(priv->hw, 0); 1769 1770 return 0; 1771 } 1772 1773 /** 1774 * stmmac_open - open entry point of the driver 1775 * @dev : pointer to the device structure. 1776 * Description: 1777 * This function is the open entry point of the driver. 1778 * Return value: 1779 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1780 * file on failure. 1781 */ 1782 static int stmmac_open(struct net_device *dev) 1783 { 1784 struct stmmac_priv *priv = netdev_priv(dev); 1785 int ret; 1786 1787 stmmac_check_ether_addr(priv); 1788 1789 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 1790 priv->pcs != STMMAC_PCS_RTBI) { 1791 ret = stmmac_init_phy(dev); 1792 if (ret) { 1793 pr_err("%s: Cannot attach to PHY (error: %d)\n", 1794 __func__, ret); 1795 return ret; 1796 } 1797 } 1798 1799 /* Extra statistics */ 1800 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1801 priv->xstats.threshold = tc; 1802 1803 /* Create and initialize the TX/RX descriptors chains. */ 1804 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 1805 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 1806 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 1807 1808 ret = alloc_dma_desc_resources(priv); 1809 if (ret < 0) { 1810 pr_err("%s: DMA descriptors allocation failed\n", __func__); 1811 goto dma_desc_error; 1812 } 1813 1814 ret = init_dma_desc_rings(dev, GFP_KERNEL); 1815 if (ret < 0) { 1816 pr_err("%s: DMA descriptors initialization failed\n", __func__); 1817 goto init_error; 1818 } 1819 1820 ret = stmmac_hw_setup(dev, true); 1821 if (ret < 0) { 1822 pr_err("%s: Hw setup failed\n", __func__); 1823 goto init_error; 1824 } 1825 1826 stmmac_init_tx_coalesce(priv); 1827 1828 if (priv->phydev) 1829 phy_start(priv->phydev); 1830 1831 /* Request the IRQ lines */ 1832 ret = request_irq(dev->irq, stmmac_interrupt, 1833 IRQF_SHARED, dev->name, dev); 1834 if (unlikely(ret < 0)) { 1835 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1836 __func__, dev->irq, ret); 1837 goto init_error; 1838 } 1839 1840 /* Request the Wake IRQ in case of another line is used for WoL */ 1841 if (priv->wol_irq != dev->irq) { 1842 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1843 IRQF_SHARED, dev->name, dev); 1844 if (unlikely(ret < 0)) { 1845 pr_err("%s: ERROR: allocating the WoL IRQ %d (%d)\n", 1846 __func__, priv->wol_irq, ret); 1847 goto wolirq_error; 1848 } 1849 } 1850 1851 /* Request the IRQ lines */ 1852 if (priv->lpi_irq > 0) { 1853 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 1854 dev->name, dev); 1855 if (unlikely(ret < 0)) { 1856 pr_err("%s: ERROR: allocating the LPI IRQ %d (%d)\n", 1857 __func__, priv->lpi_irq, ret); 1858 goto lpiirq_error; 1859 } 1860 } 1861 1862 napi_enable(&priv->napi); 1863 netif_start_queue(dev); 1864 1865 return 0; 1866 1867 lpiirq_error: 1868 if (priv->wol_irq != dev->irq) 1869 free_irq(priv->wol_irq, dev); 1870 wolirq_error: 1871 free_irq(dev->irq, dev); 1872 1873 init_error: 1874 free_dma_desc_resources(priv); 1875 dma_desc_error: 1876 if (priv->phydev) 1877 phy_disconnect(priv->phydev); 1878 1879 return ret; 1880 } 1881 1882 /** 1883 * stmmac_release - close entry point of the driver 1884 * @dev : device pointer. 1885 * Description: 1886 * This is the stop entry point of the driver. 1887 */ 1888 static int stmmac_release(struct net_device *dev) 1889 { 1890 struct stmmac_priv *priv = netdev_priv(dev); 1891 1892 if (priv->eee_enabled) 1893 del_timer_sync(&priv->eee_ctrl_timer); 1894 1895 /* Stop and disconnect the PHY */ 1896 if (priv->phydev) { 1897 phy_stop(priv->phydev); 1898 phy_disconnect(priv->phydev); 1899 priv->phydev = NULL; 1900 } 1901 1902 netif_stop_queue(dev); 1903 1904 napi_disable(&priv->napi); 1905 1906 del_timer_sync(&priv->txtimer); 1907 1908 /* Free the IRQ lines */ 1909 free_irq(dev->irq, dev); 1910 if (priv->wol_irq != dev->irq) 1911 free_irq(priv->wol_irq, dev); 1912 if (priv->lpi_irq > 0) 1913 free_irq(priv->lpi_irq, dev); 1914 1915 /* Stop TX/RX DMA and clear the descriptors */ 1916 priv->hw->dma->stop_tx(priv->ioaddr); 1917 priv->hw->dma->stop_rx(priv->ioaddr); 1918 1919 /* Release and free the Rx/Tx resources */ 1920 free_dma_desc_resources(priv); 1921 1922 /* Disable the MAC Rx/Tx */ 1923 stmmac_set_mac(priv->ioaddr, false); 1924 1925 netif_carrier_off(dev); 1926 1927 #ifdef CONFIG_DEBUG_FS 1928 stmmac_exit_fs(dev); 1929 #endif 1930 1931 stmmac_release_ptp(priv); 1932 1933 return 0; 1934 } 1935 1936 /** 1937 * stmmac_xmit - Tx entry point of the driver 1938 * @skb : the socket buffer 1939 * @dev : device pointer 1940 * Description : this is the tx entry point of the driver. 1941 * It programs the chain or the ring and supports oversized frames 1942 * and SG feature. 1943 */ 1944 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1945 { 1946 struct stmmac_priv *priv = netdev_priv(dev); 1947 unsigned int txsize = priv->dma_tx_size; 1948 unsigned int entry; 1949 int i, csum_insertion = 0, is_jumbo = 0; 1950 int nfrags = skb_shinfo(skb)->nr_frags; 1951 struct dma_desc *desc, *first; 1952 unsigned int nopaged_len = skb_headlen(skb); 1953 unsigned int enh_desc = priv->plat->enh_desc; 1954 1955 spin_lock(&priv->tx_lock); 1956 1957 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1958 spin_unlock(&priv->tx_lock); 1959 if (!netif_queue_stopped(dev)) { 1960 netif_stop_queue(dev); 1961 /* This is a hard error, log it. */ 1962 pr_err("%s: Tx Ring full when queue awake\n", __func__); 1963 } 1964 return NETDEV_TX_BUSY; 1965 } 1966 1967 if (priv->tx_path_in_lpi_mode) 1968 stmmac_disable_eee_mode(priv); 1969 1970 entry = priv->cur_tx % txsize; 1971 1972 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1973 1974 if (priv->extend_desc) 1975 desc = (struct dma_desc *)(priv->dma_etx + entry); 1976 else 1977 desc = priv->dma_tx + entry; 1978 1979 first = desc; 1980 1981 /* To program the descriptors according to the size of the frame */ 1982 if (enh_desc) 1983 is_jumbo = priv->hw->mode->is_jumbo_frm(skb->len, enh_desc); 1984 1985 if (likely(!is_jumbo)) { 1986 desc->des2 = dma_map_single(priv->device, skb->data, 1987 nopaged_len, DMA_TO_DEVICE); 1988 if (dma_mapping_error(priv->device, desc->des2)) 1989 goto dma_map_err; 1990 priv->tx_skbuff_dma[entry].buf = desc->des2; 1991 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1992 csum_insertion, priv->mode); 1993 } else { 1994 desc = first; 1995 entry = priv->hw->mode->jumbo_frm(priv, skb, csum_insertion); 1996 if (unlikely(entry < 0)) 1997 goto dma_map_err; 1998 } 1999 2000 for (i = 0; i < nfrags; i++) { 2001 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2002 int len = skb_frag_size(frag); 2003 2004 priv->tx_skbuff[entry] = NULL; 2005 entry = (++priv->cur_tx) % txsize; 2006 if (priv->extend_desc) 2007 desc = (struct dma_desc *)(priv->dma_etx + entry); 2008 else 2009 desc = priv->dma_tx + entry; 2010 2011 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 2012 DMA_TO_DEVICE); 2013 if (dma_mapping_error(priv->device, desc->des2)) 2014 goto dma_map_err; /* should reuse desc w/o issues */ 2015 2016 priv->tx_skbuff_dma[entry].buf = desc->des2; 2017 priv->tx_skbuff_dma[entry].map_as_page = true; 2018 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion, 2019 priv->mode); 2020 wmb(); 2021 priv->hw->desc->set_tx_owner(desc); 2022 wmb(); 2023 } 2024 2025 priv->tx_skbuff[entry] = skb; 2026 2027 /* Finalize the latest segment. */ 2028 priv->hw->desc->close_tx_desc(desc); 2029 2030 wmb(); 2031 /* According to the coalesce parameter the IC bit for the latest 2032 * segment could be reset and the timer re-started to invoke the 2033 * stmmac_tx function. This approach takes care about the fragments. 2034 */ 2035 priv->tx_count_frames += nfrags + 1; 2036 if (priv->tx_coal_frames > priv->tx_count_frames) { 2037 priv->hw->desc->clear_tx_ic(desc); 2038 priv->xstats.tx_reset_ic_bit++; 2039 mod_timer(&priv->txtimer, 2040 STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2041 } else 2042 priv->tx_count_frames = 0; 2043 2044 /* To avoid raise condition */ 2045 priv->hw->desc->set_tx_owner(first); 2046 wmb(); 2047 2048 priv->cur_tx++; 2049 2050 if (netif_msg_pktdata(priv)) { 2051 pr_debug("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d", 2052 __func__, (priv->cur_tx % txsize), 2053 (priv->dirty_tx % txsize), entry, first, nfrags); 2054 2055 if (priv->extend_desc) 2056 stmmac_display_ring((void *)priv->dma_etx, txsize, 1); 2057 else 2058 stmmac_display_ring((void *)priv->dma_tx, txsize, 0); 2059 2060 pr_debug(">>> frame to be transmitted: "); 2061 print_pkt(skb->data, skb->len); 2062 } 2063 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 2064 if (netif_msg_hw(priv)) 2065 pr_debug("%s: stop transmitted packets\n", __func__); 2066 netif_stop_queue(dev); 2067 } 2068 2069 dev->stats.tx_bytes += skb->len; 2070 2071 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2072 priv->hwts_tx_en)) { 2073 /* declare that device is doing timestamping */ 2074 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2075 priv->hw->desc->enable_tx_timestamp(first); 2076 } 2077 2078 if (!priv->hwts_tx_en) 2079 skb_tx_timestamp(skb); 2080 2081 netdev_sent_queue(dev, skb->len); 2082 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 2083 2084 spin_unlock(&priv->tx_lock); 2085 return NETDEV_TX_OK; 2086 2087 dma_map_err: 2088 spin_unlock(&priv->tx_lock); 2089 dev_err(priv->device, "Tx dma map failed\n"); 2090 dev_kfree_skb(skb); 2091 priv->dev->stats.tx_dropped++; 2092 return NETDEV_TX_OK; 2093 } 2094 2095 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 2096 { 2097 struct ethhdr *ehdr; 2098 u16 vlanid; 2099 2100 if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) == 2101 NETIF_F_HW_VLAN_CTAG_RX && 2102 !__vlan_get_tag(skb, &vlanid)) { 2103 /* pop the vlan tag */ 2104 ehdr = (struct ethhdr *)skb->data; 2105 memmove(skb->data + VLAN_HLEN, ehdr, ETH_ALEN * 2); 2106 skb_pull(skb, VLAN_HLEN); 2107 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlanid); 2108 } 2109 } 2110 2111 2112 /** 2113 * stmmac_rx_refill - refill used skb preallocated buffers 2114 * @priv: driver private structure 2115 * Description : this is to reallocate the skb for the reception process 2116 * that is based on zero-copy. 2117 */ 2118 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 2119 { 2120 unsigned int rxsize = priv->dma_rx_size; 2121 int bfsize = priv->dma_buf_sz; 2122 2123 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 2124 unsigned int entry = priv->dirty_rx % rxsize; 2125 struct dma_desc *p; 2126 2127 if (priv->extend_desc) 2128 p = (struct dma_desc *)(priv->dma_erx + entry); 2129 else 2130 p = priv->dma_rx + entry; 2131 2132 if (likely(priv->rx_skbuff[entry] == NULL)) { 2133 struct sk_buff *skb; 2134 2135 skb = netdev_alloc_skb_ip_align(priv->dev, bfsize); 2136 2137 if (unlikely(skb == NULL)) 2138 break; 2139 2140 priv->rx_skbuff[entry] = skb; 2141 priv->rx_skbuff_dma[entry] = 2142 dma_map_single(priv->device, skb->data, bfsize, 2143 DMA_FROM_DEVICE); 2144 if (dma_mapping_error(priv->device, 2145 priv->rx_skbuff_dma[entry])) { 2146 dev_err(priv->device, "Rx dma map failed\n"); 2147 dev_kfree_skb(skb); 2148 break; 2149 } 2150 p->des2 = priv->rx_skbuff_dma[entry]; 2151 2152 priv->hw->mode->refill_desc3(priv, p); 2153 2154 if (netif_msg_rx_status(priv)) 2155 pr_debug("\trefill entry #%d\n", entry); 2156 } 2157 wmb(); 2158 priv->hw->desc->set_rx_owner(p); 2159 wmb(); 2160 } 2161 } 2162 2163 /** 2164 * stmmac_rx - manage the receive process 2165 * @priv: driver private structure 2166 * @limit: napi bugget. 2167 * Description : this the function called by the napi poll method. 2168 * It gets all the frames inside the ring. 2169 */ 2170 static int stmmac_rx(struct stmmac_priv *priv, int limit) 2171 { 2172 unsigned int rxsize = priv->dma_rx_size; 2173 unsigned int entry = priv->cur_rx % rxsize; 2174 unsigned int next_entry; 2175 unsigned int count = 0; 2176 int coe = priv->hw->rx_csum; 2177 2178 if (netif_msg_rx_status(priv)) { 2179 pr_debug("%s: descriptor ring:\n", __func__); 2180 if (priv->extend_desc) 2181 stmmac_display_ring((void *)priv->dma_erx, rxsize, 1); 2182 else 2183 stmmac_display_ring((void *)priv->dma_rx, rxsize, 0); 2184 } 2185 while (count < limit) { 2186 int status; 2187 struct dma_desc *p; 2188 2189 if (priv->extend_desc) 2190 p = (struct dma_desc *)(priv->dma_erx + entry); 2191 else 2192 p = priv->dma_rx + entry; 2193 2194 if (priv->hw->desc->get_rx_owner(p)) 2195 break; 2196 2197 count++; 2198 2199 next_entry = (++priv->cur_rx) % rxsize; 2200 if (priv->extend_desc) 2201 prefetch(priv->dma_erx + next_entry); 2202 else 2203 prefetch(priv->dma_rx + next_entry); 2204 2205 /* read the status of the incoming frame */ 2206 status = priv->hw->desc->rx_status(&priv->dev->stats, 2207 &priv->xstats, p); 2208 if ((priv->extend_desc) && (priv->hw->desc->rx_extended_status)) 2209 priv->hw->desc->rx_extended_status(&priv->dev->stats, 2210 &priv->xstats, 2211 priv->dma_erx + 2212 entry); 2213 if (unlikely(status == discard_frame)) { 2214 priv->dev->stats.rx_errors++; 2215 if (priv->hwts_rx_en && !priv->extend_desc) { 2216 /* DESC2 & DESC3 will be overwitten by device 2217 * with timestamp value, hence reinitialize 2218 * them in stmmac_rx_refill() function so that 2219 * device can reuse it. 2220 */ 2221 priv->rx_skbuff[entry] = NULL; 2222 dma_unmap_single(priv->device, 2223 priv->rx_skbuff_dma[entry], 2224 priv->dma_buf_sz, 2225 DMA_FROM_DEVICE); 2226 } 2227 } else { 2228 struct sk_buff *skb; 2229 int frame_len; 2230 2231 frame_len = priv->hw->desc->get_rx_frame_len(p, coe); 2232 2233 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 2234 * Type frames (LLC/LLC-SNAP) 2235 */ 2236 if (unlikely(status != llc_snap)) 2237 frame_len -= ETH_FCS_LEN; 2238 2239 if (netif_msg_rx_status(priv)) { 2240 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 2241 p, entry, p->des2); 2242 if (frame_len > ETH_FRAME_LEN) 2243 pr_debug("\tframe size %d, COE: %d\n", 2244 frame_len, status); 2245 } 2246 skb = priv->rx_skbuff[entry]; 2247 if (unlikely(!skb)) { 2248 pr_err("%s: Inconsistent Rx descriptor chain\n", 2249 priv->dev->name); 2250 priv->dev->stats.rx_dropped++; 2251 break; 2252 } 2253 prefetch(skb->data - NET_IP_ALIGN); 2254 priv->rx_skbuff[entry] = NULL; 2255 2256 stmmac_get_rx_hwtstamp(priv, entry, skb); 2257 2258 skb_put(skb, frame_len); 2259 dma_unmap_single(priv->device, 2260 priv->rx_skbuff_dma[entry], 2261 priv->dma_buf_sz, DMA_FROM_DEVICE); 2262 2263 if (netif_msg_pktdata(priv)) { 2264 pr_debug("frame received (%dbytes)", frame_len); 2265 print_pkt(skb->data, frame_len); 2266 } 2267 2268 stmmac_rx_vlan(priv->dev, skb); 2269 2270 skb->protocol = eth_type_trans(skb, priv->dev); 2271 2272 if (unlikely(!coe)) 2273 skb_checksum_none_assert(skb); 2274 else 2275 skb->ip_summed = CHECKSUM_UNNECESSARY; 2276 2277 napi_gro_receive(&priv->napi, skb); 2278 2279 priv->dev->stats.rx_packets++; 2280 priv->dev->stats.rx_bytes += frame_len; 2281 } 2282 entry = next_entry; 2283 } 2284 2285 stmmac_rx_refill(priv); 2286 2287 priv->xstats.rx_pkt_n += count; 2288 2289 return count; 2290 } 2291 2292 /** 2293 * stmmac_poll - stmmac poll method (NAPI) 2294 * @napi : pointer to the napi structure. 2295 * @budget : maximum number of packets that the current CPU can receive from 2296 * all interfaces. 2297 * Description : 2298 * To look at the incoming frames and clear the tx resources. 2299 */ 2300 static int stmmac_poll(struct napi_struct *napi, int budget) 2301 { 2302 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 2303 int work_done = 0; 2304 2305 priv->xstats.napi_poll++; 2306 stmmac_tx_clean(priv); 2307 2308 work_done = stmmac_rx(priv, budget); 2309 if (work_done < budget) { 2310 napi_complete(napi); 2311 stmmac_enable_dma_irq(priv); 2312 } 2313 return work_done; 2314 } 2315 2316 /** 2317 * stmmac_tx_timeout 2318 * @dev : Pointer to net device structure 2319 * Description: this function is called when a packet transmission fails to 2320 * complete within a reasonable time. The driver will mark the error in the 2321 * netdev structure and arrange for the device to be reset to a sane state 2322 * in order to transmit a new packet. 2323 */ 2324 static void stmmac_tx_timeout(struct net_device *dev) 2325 { 2326 struct stmmac_priv *priv = netdev_priv(dev); 2327 2328 /* Clear Tx resources and restart transmitting again */ 2329 stmmac_tx_err(priv); 2330 } 2331 2332 /** 2333 * stmmac_set_rx_mode - entry point for multicast addressing 2334 * @dev : pointer to the device structure 2335 * Description: 2336 * This function is a driver entry point which gets called by the kernel 2337 * whenever multicast addresses must be enabled/disabled. 2338 * Return value: 2339 * void. 2340 */ 2341 static void stmmac_set_rx_mode(struct net_device *dev) 2342 { 2343 struct stmmac_priv *priv = netdev_priv(dev); 2344 2345 priv->hw->mac->set_filter(priv->hw, dev); 2346 } 2347 2348 /** 2349 * stmmac_change_mtu - entry point to change MTU size for the device. 2350 * @dev : device pointer. 2351 * @new_mtu : the new MTU size for the device. 2352 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 2353 * to drive packet transmission. Ethernet has an MTU of 1500 octets 2354 * (ETH_DATA_LEN). This value can be changed with ifconfig. 2355 * Return value: 2356 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2357 * file on failure. 2358 */ 2359 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 2360 { 2361 struct stmmac_priv *priv = netdev_priv(dev); 2362 int max_mtu; 2363 2364 if (netif_running(dev)) { 2365 pr_err("%s: must be stopped to change its MTU\n", dev->name); 2366 return -EBUSY; 2367 } 2368 2369 if (priv->plat->enh_desc) 2370 max_mtu = JUMBO_LEN; 2371 else 2372 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 2373 2374 if (priv->plat->maxmtu < max_mtu) 2375 max_mtu = priv->plat->maxmtu; 2376 2377 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 2378 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 2379 return -EINVAL; 2380 } 2381 2382 dev->mtu = new_mtu; 2383 netdev_update_features(dev); 2384 2385 return 0; 2386 } 2387 2388 static netdev_features_t stmmac_fix_features(struct net_device *dev, 2389 netdev_features_t features) 2390 { 2391 struct stmmac_priv *priv = netdev_priv(dev); 2392 2393 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 2394 features &= ~NETIF_F_RXCSUM; 2395 2396 if (!priv->plat->tx_coe) 2397 features &= ~NETIF_F_ALL_CSUM; 2398 2399 /* Some GMAC devices have a bugged Jumbo frame support that 2400 * needs to have the Tx COE disabled for oversized frames 2401 * (due to limited buffer sizes). In this case we disable 2402 * the TX csum insertionin the TDES and not use SF. 2403 */ 2404 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 2405 features &= ~NETIF_F_ALL_CSUM; 2406 2407 return features; 2408 } 2409 2410 static int stmmac_set_features(struct net_device *netdev, 2411 netdev_features_t features) 2412 { 2413 struct stmmac_priv *priv = netdev_priv(netdev); 2414 2415 /* Keep the COE Type in case of csum is supporting */ 2416 if (features & NETIF_F_RXCSUM) 2417 priv->hw->rx_csum = priv->plat->rx_coe; 2418 else 2419 priv->hw->rx_csum = 0; 2420 /* No check needed because rx_coe has been set before and it will be 2421 * fixed in case of issue. 2422 */ 2423 priv->hw->mac->rx_ipc(priv->hw); 2424 2425 return 0; 2426 } 2427 2428 /** 2429 * stmmac_interrupt - main ISR 2430 * @irq: interrupt number. 2431 * @dev_id: to pass the net device pointer. 2432 * Description: this is the main driver interrupt service routine. 2433 * It can call: 2434 * o DMA service routine (to manage incoming frame reception and transmission 2435 * status) 2436 * o Core interrupts to manage: remote wake-up, management counter, LPI 2437 * interrupts. 2438 */ 2439 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 2440 { 2441 struct net_device *dev = (struct net_device *)dev_id; 2442 struct stmmac_priv *priv = netdev_priv(dev); 2443 2444 if (priv->irq_wake) 2445 pm_wakeup_event(priv->device, 0); 2446 2447 if (unlikely(!dev)) { 2448 pr_err("%s: invalid dev pointer\n", __func__); 2449 return IRQ_NONE; 2450 } 2451 2452 /* To handle GMAC own interrupts */ 2453 if (priv->plat->has_gmac) { 2454 int status = priv->hw->mac->host_irq_status(priv->hw, 2455 &priv->xstats); 2456 if (unlikely(status)) { 2457 /* For LPI we need to save the tx status */ 2458 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 2459 priv->tx_path_in_lpi_mode = true; 2460 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 2461 priv->tx_path_in_lpi_mode = false; 2462 } 2463 } 2464 2465 /* To handle DMA interrupts */ 2466 stmmac_dma_interrupt(priv); 2467 2468 return IRQ_HANDLED; 2469 } 2470 2471 #ifdef CONFIG_NET_POLL_CONTROLLER 2472 /* Polling receive - used by NETCONSOLE and other diagnostic tools 2473 * to allow network I/O with interrupts disabled. 2474 */ 2475 static void stmmac_poll_controller(struct net_device *dev) 2476 { 2477 disable_irq(dev->irq); 2478 stmmac_interrupt(dev->irq, dev); 2479 enable_irq(dev->irq); 2480 } 2481 #endif 2482 2483 /** 2484 * stmmac_ioctl - Entry point for the Ioctl 2485 * @dev: Device pointer. 2486 * @rq: An IOCTL specefic structure, that can contain a pointer to 2487 * a proprietary structure used to pass information to the driver. 2488 * @cmd: IOCTL command 2489 * Description: 2490 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 2491 */ 2492 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2493 { 2494 struct stmmac_priv *priv = netdev_priv(dev); 2495 int ret = -EOPNOTSUPP; 2496 2497 if (!netif_running(dev)) 2498 return -EINVAL; 2499 2500 switch (cmd) { 2501 case SIOCGMIIPHY: 2502 case SIOCGMIIREG: 2503 case SIOCSMIIREG: 2504 if (!priv->phydev) 2505 return -EINVAL; 2506 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 2507 break; 2508 case SIOCSHWTSTAMP: 2509 ret = stmmac_hwtstamp_ioctl(dev, rq); 2510 break; 2511 default: 2512 break; 2513 } 2514 2515 return ret; 2516 } 2517 2518 #ifdef CONFIG_DEBUG_FS 2519 static struct dentry *stmmac_fs_dir; 2520 2521 static void sysfs_display_ring(void *head, int size, int extend_desc, 2522 struct seq_file *seq) 2523 { 2524 int i; 2525 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 2526 struct dma_desc *p = (struct dma_desc *)head; 2527 2528 for (i = 0; i < size; i++) { 2529 u64 x; 2530 if (extend_desc) { 2531 x = *(u64 *) ep; 2532 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2533 i, (unsigned int)virt_to_phys(ep), 2534 (unsigned int)x, (unsigned int)(x >> 32), 2535 ep->basic.des2, ep->basic.des3); 2536 ep++; 2537 } else { 2538 x = *(u64 *) p; 2539 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 2540 i, (unsigned int)virt_to_phys(ep), 2541 (unsigned int)x, (unsigned int)(x >> 32), 2542 p->des2, p->des3); 2543 p++; 2544 } 2545 seq_printf(seq, "\n"); 2546 } 2547 } 2548 2549 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 2550 { 2551 struct net_device *dev = seq->private; 2552 struct stmmac_priv *priv = netdev_priv(dev); 2553 unsigned int txsize = priv->dma_tx_size; 2554 unsigned int rxsize = priv->dma_rx_size; 2555 2556 if (priv->extend_desc) { 2557 seq_printf(seq, "Extended RX descriptor ring:\n"); 2558 sysfs_display_ring((void *)priv->dma_erx, rxsize, 1, seq); 2559 seq_printf(seq, "Extended TX descriptor ring:\n"); 2560 sysfs_display_ring((void *)priv->dma_etx, txsize, 1, seq); 2561 } else { 2562 seq_printf(seq, "RX descriptor ring:\n"); 2563 sysfs_display_ring((void *)priv->dma_rx, rxsize, 0, seq); 2564 seq_printf(seq, "TX descriptor ring:\n"); 2565 sysfs_display_ring((void *)priv->dma_tx, txsize, 0, seq); 2566 } 2567 2568 return 0; 2569 } 2570 2571 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 2572 { 2573 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 2574 } 2575 2576 static const struct file_operations stmmac_rings_status_fops = { 2577 .owner = THIS_MODULE, 2578 .open = stmmac_sysfs_ring_open, 2579 .read = seq_read, 2580 .llseek = seq_lseek, 2581 .release = single_release, 2582 }; 2583 2584 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 2585 { 2586 struct net_device *dev = seq->private; 2587 struct stmmac_priv *priv = netdev_priv(dev); 2588 2589 if (!priv->hw_cap_support) { 2590 seq_printf(seq, "DMA HW features not supported\n"); 2591 return 0; 2592 } 2593 2594 seq_printf(seq, "==============================\n"); 2595 seq_printf(seq, "\tDMA HW features\n"); 2596 seq_printf(seq, "==============================\n"); 2597 2598 seq_printf(seq, "\t10/100 Mbps %s\n", 2599 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 2600 seq_printf(seq, "\t1000 Mbps %s\n", 2601 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 2602 seq_printf(seq, "\tHalf duple %s\n", 2603 (priv->dma_cap.half_duplex) ? "Y" : "N"); 2604 seq_printf(seq, "\tHash Filter: %s\n", 2605 (priv->dma_cap.hash_filter) ? "Y" : "N"); 2606 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 2607 (priv->dma_cap.multi_addr) ? "Y" : "N"); 2608 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 2609 (priv->dma_cap.pcs) ? "Y" : "N"); 2610 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 2611 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 2612 seq_printf(seq, "\tPMT Remote wake up: %s\n", 2613 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 2614 seq_printf(seq, "\tPMT Magic Frame: %s\n", 2615 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 2616 seq_printf(seq, "\tRMON module: %s\n", 2617 (priv->dma_cap.rmon) ? "Y" : "N"); 2618 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 2619 (priv->dma_cap.time_stamp) ? "Y" : "N"); 2620 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 2621 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 2622 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 2623 (priv->dma_cap.eee) ? "Y" : "N"); 2624 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 2625 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 2626 (priv->dma_cap.tx_coe) ? "Y" : "N"); 2627 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 2628 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 2629 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 2630 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 2631 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 2632 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 2633 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 2634 priv->dma_cap.number_rx_channel); 2635 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 2636 priv->dma_cap.number_tx_channel); 2637 seq_printf(seq, "\tEnhanced descriptors: %s\n", 2638 (priv->dma_cap.enh_desc) ? "Y" : "N"); 2639 2640 return 0; 2641 } 2642 2643 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 2644 { 2645 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 2646 } 2647 2648 static const struct file_operations stmmac_dma_cap_fops = { 2649 .owner = THIS_MODULE, 2650 .open = stmmac_sysfs_dma_cap_open, 2651 .read = seq_read, 2652 .llseek = seq_lseek, 2653 .release = single_release, 2654 }; 2655 2656 static int stmmac_init_fs(struct net_device *dev) 2657 { 2658 struct stmmac_priv *priv = netdev_priv(dev); 2659 2660 /* Create per netdev entries */ 2661 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 2662 2663 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { 2664 pr_err("ERROR %s/%s, debugfs create directory failed\n", 2665 STMMAC_RESOURCE_NAME, dev->name); 2666 2667 return -ENOMEM; 2668 } 2669 2670 /* Entry to report DMA RX/TX rings */ 2671 priv->dbgfs_rings_status = 2672 debugfs_create_file("descriptors_status", S_IRUGO, 2673 priv->dbgfs_dir, dev, 2674 &stmmac_rings_status_fops); 2675 2676 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { 2677 pr_info("ERROR creating stmmac ring debugfs file\n"); 2678 debugfs_remove_recursive(priv->dbgfs_dir); 2679 2680 return -ENOMEM; 2681 } 2682 2683 /* Entry to report the DMA HW features */ 2684 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, 2685 priv->dbgfs_dir, 2686 dev, &stmmac_dma_cap_fops); 2687 2688 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { 2689 pr_info("ERROR creating stmmac MMC debugfs file\n"); 2690 debugfs_remove_recursive(priv->dbgfs_dir); 2691 2692 return -ENOMEM; 2693 } 2694 2695 return 0; 2696 } 2697 2698 static void stmmac_exit_fs(struct net_device *dev) 2699 { 2700 struct stmmac_priv *priv = netdev_priv(dev); 2701 2702 debugfs_remove_recursive(priv->dbgfs_dir); 2703 } 2704 #endif /* CONFIG_DEBUG_FS */ 2705 2706 static const struct net_device_ops stmmac_netdev_ops = { 2707 .ndo_open = stmmac_open, 2708 .ndo_start_xmit = stmmac_xmit, 2709 .ndo_stop = stmmac_release, 2710 .ndo_change_mtu = stmmac_change_mtu, 2711 .ndo_fix_features = stmmac_fix_features, 2712 .ndo_set_features = stmmac_set_features, 2713 .ndo_set_rx_mode = stmmac_set_rx_mode, 2714 .ndo_tx_timeout = stmmac_tx_timeout, 2715 .ndo_do_ioctl = stmmac_ioctl, 2716 #ifdef CONFIG_NET_POLL_CONTROLLER 2717 .ndo_poll_controller = stmmac_poll_controller, 2718 #endif 2719 .ndo_set_mac_address = eth_mac_addr, 2720 }; 2721 2722 /** 2723 * stmmac_hw_init - Init the MAC device 2724 * @priv: driver private structure 2725 * Description: this function is to configure the MAC device according to 2726 * some platform parameters or the HW capability register. It prepares the 2727 * driver to use either ring or chain modes and to setup either enhanced or 2728 * normal descriptors. 2729 */ 2730 static int stmmac_hw_init(struct stmmac_priv *priv) 2731 { 2732 struct mac_device_info *mac; 2733 2734 /* Identify the MAC HW device */ 2735 if (priv->plat->has_gmac) { 2736 priv->dev->priv_flags |= IFF_UNICAST_FLT; 2737 mac = dwmac1000_setup(priv->ioaddr, 2738 priv->plat->multicast_filter_bins, 2739 priv->plat->unicast_filter_entries); 2740 } else { 2741 mac = dwmac100_setup(priv->ioaddr); 2742 } 2743 if (!mac) 2744 return -ENOMEM; 2745 2746 priv->hw = mac; 2747 2748 /* Get and dump the chip ID */ 2749 priv->synopsys_id = stmmac_get_synopsys_id(priv); 2750 2751 /* To use the chained or ring mode */ 2752 if (chain_mode) { 2753 priv->hw->mode = &chain_mode_ops; 2754 pr_info(" Chain mode enabled\n"); 2755 priv->mode = STMMAC_CHAIN_MODE; 2756 } else { 2757 priv->hw->mode = &ring_mode_ops; 2758 pr_info(" Ring mode enabled\n"); 2759 priv->mode = STMMAC_RING_MODE; 2760 } 2761 2762 /* Get the HW capability (new GMAC newer than 3.50a) */ 2763 priv->hw_cap_support = stmmac_get_hw_features(priv); 2764 if (priv->hw_cap_support) { 2765 pr_info(" DMA HW capability register supported"); 2766 2767 /* We can override some gmac/dma configuration fields: e.g. 2768 * enh_desc, tx_coe (e.g. that are passed through the 2769 * platform) with the values from the HW capability 2770 * register (if supported). 2771 */ 2772 priv->plat->enh_desc = priv->dma_cap.enh_desc; 2773 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 2774 2775 /* TXCOE doesn't work in thresh DMA mode */ 2776 if (priv->plat->force_thresh_dma_mode) 2777 priv->plat->tx_coe = 0; 2778 else 2779 priv->plat->tx_coe = priv->dma_cap.tx_coe; 2780 2781 if (priv->dma_cap.rx_coe_type2) 2782 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 2783 else if (priv->dma_cap.rx_coe_type1) 2784 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 2785 2786 } else 2787 pr_info(" No HW DMA feature register supported"); 2788 2789 /* To use alternate (extended) or normal descriptor structures */ 2790 stmmac_selec_desc_mode(priv); 2791 2792 if (priv->plat->rx_coe) { 2793 priv->hw->rx_csum = priv->plat->rx_coe; 2794 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 2795 priv->plat->rx_coe); 2796 } 2797 if (priv->plat->tx_coe) 2798 pr_info(" TX Checksum insertion supported\n"); 2799 2800 if (priv->plat->pmt) { 2801 pr_info(" Wake-Up On Lan supported\n"); 2802 device_set_wakeup_capable(priv->device, 1); 2803 } 2804 2805 return 0; 2806 } 2807 2808 /** 2809 * stmmac_dvr_probe 2810 * @device: device pointer 2811 * @plat_dat: platform data pointer 2812 * @res: stmmac resource pointer 2813 * Description: this is the main probe function used to 2814 * call the alloc_etherdev, allocate the priv structure. 2815 * Return: 2816 * returns 0 on success, otherwise errno. 2817 */ 2818 int stmmac_dvr_probe(struct device *device, 2819 struct plat_stmmacenet_data *plat_dat, 2820 struct stmmac_resources *res) 2821 { 2822 int ret = 0; 2823 struct net_device *ndev = NULL; 2824 struct stmmac_priv *priv; 2825 2826 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 2827 if (!ndev) 2828 return -ENOMEM; 2829 2830 SET_NETDEV_DEV(ndev, device); 2831 2832 priv = netdev_priv(ndev); 2833 priv->device = device; 2834 priv->dev = ndev; 2835 2836 stmmac_set_ethtool_ops(ndev); 2837 priv->pause = pause; 2838 priv->plat = plat_dat; 2839 priv->ioaddr = res->addr; 2840 priv->dev->base_addr = (unsigned long)res->addr; 2841 2842 priv->dev->irq = res->irq; 2843 priv->wol_irq = res->wol_irq; 2844 priv->lpi_irq = res->lpi_irq; 2845 2846 if (res->mac) 2847 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 2848 2849 dev_set_drvdata(device, priv->dev); 2850 2851 /* Verify driver arguments */ 2852 stmmac_verify_args(); 2853 2854 /* Override with kernel parameters if supplied XXX CRS XXX 2855 * this needs to have multiple instances 2856 */ 2857 if ((phyaddr >= 0) && (phyaddr <= 31)) 2858 priv->plat->phy_addr = phyaddr; 2859 2860 priv->stmmac_clk = devm_clk_get(priv->device, STMMAC_RESOURCE_NAME); 2861 if (IS_ERR(priv->stmmac_clk)) { 2862 dev_warn(priv->device, "%s: warning: cannot get CSR clock\n", 2863 __func__); 2864 /* If failed to obtain stmmac_clk and specific clk_csr value 2865 * is NOT passed from the platform, probe fail. 2866 */ 2867 if (!priv->plat->clk_csr) { 2868 ret = PTR_ERR(priv->stmmac_clk); 2869 goto error_clk_get; 2870 } else { 2871 priv->stmmac_clk = NULL; 2872 } 2873 } 2874 clk_prepare_enable(priv->stmmac_clk); 2875 2876 priv->pclk = devm_clk_get(priv->device, "pclk"); 2877 if (IS_ERR(priv->pclk)) { 2878 if (PTR_ERR(priv->pclk) == -EPROBE_DEFER) { 2879 ret = -EPROBE_DEFER; 2880 goto error_pclk_get; 2881 } 2882 priv->pclk = NULL; 2883 } 2884 clk_prepare_enable(priv->pclk); 2885 2886 priv->stmmac_rst = devm_reset_control_get(priv->device, 2887 STMMAC_RESOURCE_NAME); 2888 if (IS_ERR(priv->stmmac_rst)) { 2889 if (PTR_ERR(priv->stmmac_rst) == -EPROBE_DEFER) { 2890 ret = -EPROBE_DEFER; 2891 goto error_hw_init; 2892 } 2893 dev_info(priv->device, "no reset control found\n"); 2894 priv->stmmac_rst = NULL; 2895 } 2896 if (priv->stmmac_rst) 2897 reset_control_deassert(priv->stmmac_rst); 2898 2899 /* Init MAC and get the capabilities */ 2900 ret = stmmac_hw_init(priv); 2901 if (ret) 2902 goto error_hw_init; 2903 2904 ndev->netdev_ops = &stmmac_netdev_ops; 2905 2906 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 2907 NETIF_F_RXCSUM; 2908 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 2909 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 2910 #ifdef STMMAC_VLAN_TAG_USED 2911 /* Both mac100 and gmac support receive VLAN tag detection */ 2912 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX; 2913 #endif 2914 priv->msg_enable = netif_msg_init(debug, default_msg_level); 2915 2916 if (flow_ctrl) 2917 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 2918 2919 /* Rx Watchdog is available in the COREs newer than the 3.40. 2920 * In some case, for example on bugged HW this feature 2921 * has to be disable and this can be done by passing the 2922 * riwt_off field from the platform. 2923 */ 2924 if ((priv->synopsys_id >= DWMAC_CORE_3_50) && (!priv->plat->riwt_off)) { 2925 priv->use_riwt = 1; 2926 pr_info(" Enable RX Mitigation via HW Watchdog Timer\n"); 2927 } 2928 2929 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 2930 2931 spin_lock_init(&priv->lock); 2932 spin_lock_init(&priv->tx_lock); 2933 2934 ret = register_netdev(ndev); 2935 if (ret) { 2936 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 2937 goto error_netdev_register; 2938 } 2939 2940 /* If a specific clk_csr value is passed from the platform 2941 * this means that the CSR Clock Range selection cannot be 2942 * changed at run-time and it is fixed. Viceversa the driver'll try to 2943 * set the MDC clock dynamically according to the csr actual 2944 * clock input. 2945 */ 2946 if (!priv->plat->clk_csr) 2947 stmmac_clk_csr_set(priv); 2948 else 2949 priv->clk_csr = priv->plat->clk_csr; 2950 2951 stmmac_check_pcs_mode(priv); 2952 2953 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 2954 priv->pcs != STMMAC_PCS_RTBI) { 2955 /* MDIO bus Registration */ 2956 ret = stmmac_mdio_register(ndev); 2957 if (ret < 0) { 2958 pr_debug("%s: MDIO bus (id: %d) registration failed", 2959 __func__, priv->plat->bus_id); 2960 goto error_mdio_register; 2961 } 2962 } 2963 2964 return 0; 2965 2966 error_mdio_register: 2967 unregister_netdev(ndev); 2968 error_netdev_register: 2969 netif_napi_del(&priv->napi); 2970 error_hw_init: 2971 clk_disable_unprepare(priv->pclk); 2972 error_pclk_get: 2973 clk_disable_unprepare(priv->stmmac_clk); 2974 error_clk_get: 2975 free_netdev(ndev); 2976 2977 return ret; 2978 } 2979 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 2980 2981 /** 2982 * stmmac_dvr_remove 2983 * @ndev: net device pointer 2984 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 2985 * changes the link status, releases the DMA descriptor rings. 2986 */ 2987 int stmmac_dvr_remove(struct net_device *ndev) 2988 { 2989 struct stmmac_priv *priv = netdev_priv(ndev); 2990 2991 pr_info("%s:\n\tremoving driver", __func__); 2992 2993 priv->hw->dma->stop_rx(priv->ioaddr); 2994 priv->hw->dma->stop_tx(priv->ioaddr); 2995 2996 stmmac_set_mac(priv->ioaddr, false); 2997 netif_carrier_off(ndev); 2998 unregister_netdev(ndev); 2999 if (priv->stmmac_rst) 3000 reset_control_assert(priv->stmmac_rst); 3001 clk_disable_unprepare(priv->pclk); 3002 clk_disable_unprepare(priv->stmmac_clk); 3003 if (priv->pcs != STMMAC_PCS_RGMII && priv->pcs != STMMAC_PCS_TBI && 3004 priv->pcs != STMMAC_PCS_RTBI) 3005 stmmac_mdio_unregister(ndev); 3006 free_netdev(ndev); 3007 3008 return 0; 3009 } 3010 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 3011 3012 /** 3013 * stmmac_suspend - suspend callback 3014 * @ndev: net device pointer 3015 * Description: this is the function to suspend the device and it is called 3016 * by the platform driver to stop the network queue, release the resources, 3017 * program the PMT register (for WoL), clean and release driver resources. 3018 */ 3019 int stmmac_suspend(struct net_device *ndev) 3020 { 3021 struct stmmac_priv *priv = netdev_priv(ndev); 3022 unsigned long flags; 3023 3024 if (!ndev || !netif_running(ndev)) 3025 return 0; 3026 3027 if (priv->phydev) 3028 phy_stop(priv->phydev); 3029 3030 spin_lock_irqsave(&priv->lock, flags); 3031 3032 netif_device_detach(ndev); 3033 netif_stop_queue(ndev); 3034 3035 napi_disable(&priv->napi); 3036 3037 /* Stop TX/RX DMA */ 3038 priv->hw->dma->stop_tx(priv->ioaddr); 3039 priv->hw->dma->stop_rx(priv->ioaddr); 3040 3041 stmmac_clear_descriptors(priv); 3042 3043 /* Enable Power down mode by programming the PMT regs */ 3044 if (device_may_wakeup(priv->device)) { 3045 priv->hw->mac->pmt(priv->hw, priv->wolopts); 3046 priv->irq_wake = 1; 3047 } else { 3048 stmmac_set_mac(priv->ioaddr, false); 3049 pinctrl_pm_select_sleep_state(priv->device); 3050 /* Disable clock in case of PWM is off */ 3051 clk_disable(priv->pclk); 3052 clk_disable(priv->stmmac_clk); 3053 } 3054 spin_unlock_irqrestore(&priv->lock, flags); 3055 3056 priv->oldlink = 0; 3057 priv->speed = 0; 3058 priv->oldduplex = -1; 3059 return 0; 3060 } 3061 EXPORT_SYMBOL_GPL(stmmac_suspend); 3062 3063 /** 3064 * stmmac_resume - resume callback 3065 * @ndev: net device pointer 3066 * Description: when resume this function is invoked to setup the DMA and CORE 3067 * in a usable state. 3068 */ 3069 int stmmac_resume(struct net_device *ndev) 3070 { 3071 struct stmmac_priv *priv = netdev_priv(ndev); 3072 unsigned long flags; 3073 3074 if (!netif_running(ndev)) 3075 return 0; 3076 3077 spin_lock_irqsave(&priv->lock, flags); 3078 3079 /* Power Down bit, into the PM register, is cleared 3080 * automatically as soon as a magic packet or a Wake-up frame 3081 * is received. Anyway, it's better to manually clear 3082 * this bit because it can generate problems while resuming 3083 * from another devices (e.g. serial console). 3084 */ 3085 if (device_may_wakeup(priv->device)) { 3086 priv->hw->mac->pmt(priv->hw, 0); 3087 priv->irq_wake = 0; 3088 } else { 3089 pinctrl_pm_select_default_state(priv->device); 3090 /* enable the clk prevously disabled */ 3091 clk_enable(priv->stmmac_clk); 3092 clk_enable(priv->pclk); 3093 /* reset the phy so that it's ready */ 3094 if (priv->mii) 3095 stmmac_mdio_reset(priv->mii); 3096 } 3097 3098 netif_device_attach(ndev); 3099 3100 init_dma_desc_rings(ndev, GFP_ATOMIC); 3101 stmmac_hw_setup(ndev, false); 3102 stmmac_init_tx_coalesce(priv); 3103 3104 napi_enable(&priv->napi); 3105 3106 netif_start_queue(ndev); 3107 3108 spin_unlock_irqrestore(&priv->lock, flags); 3109 3110 if (priv->phydev) 3111 phy_start(priv->phydev); 3112 3113 return 0; 3114 } 3115 EXPORT_SYMBOL_GPL(stmmac_resume); 3116 3117 #ifndef MODULE 3118 static int __init stmmac_cmdline_opt(char *str) 3119 { 3120 char *opt; 3121 3122 if (!str || !*str) 3123 return -EINVAL; 3124 while ((opt = strsep(&str, ",")) != NULL) { 3125 if (!strncmp(opt, "debug:", 6)) { 3126 if (kstrtoint(opt + 6, 0, &debug)) 3127 goto err; 3128 } else if (!strncmp(opt, "phyaddr:", 8)) { 3129 if (kstrtoint(opt + 8, 0, &phyaddr)) 3130 goto err; 3131 } else if (!strncmp(opt, "dma_txsize:", 11)) { 3132 if (kstrtoint(opt + 11, 0, &dma_txsize)) 3133 goto err; 3134 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 3135 if (kstrtoint(opt + 11, 0, &dma_rxsize)) 3136 goto err; 3137 } else if (!strncmp(opt, "buf_sz:", 7)) { 3138 if (kstrtoint(opt + 7, 0, &buf_sz)) 3139 goto err; 3140 } else if (!strncmp(opt, "tc:", 3)) { 3141 if (kstrtoint(opt + 3, 0, &tc)) 3142 goto err; 3143 } else if (!strncmp(opt, "watchdog:", 9)) { 3144 if (kstrtoint(opt + 9, 0, &watchdog)) 3145 goto err; 3146 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 3147 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 3148 goto err; 3149 } else if (!strncmp(opt, "pause:", 6)) { 3150 if (kstrtoint(opt + 6, 0, &pause)) 3151 goto err; 3152 } else if (!strncmp(opt, "eee_timer:", 10)) { 3153 if (kstrtoint(opt + 10, 0, &eee_timer)) 3154 goto err; 3155 } else if (!strncmp(opt, "chain_mode:", 11)) { 3156 if (kstrtoint(opt + 11, 0, &chain_mode)) 3157 goto err; 3158 } 3159 } 3160 return 0; 3161 3162 err: 3163 pr_err("%s: ERROR broken module parameter conversion", __func__); 3164 return -EINVAL; 3165 } 3166 3167 __setup("stmmaceth=", stmmac_cmdline_opt); 3168 #endif /* MODULE */ 3169 3170 static int __init stmmac_init(void) 3171 { 3172 #ifdef CONFIG_DEBUG_FS 3173 /* Create debugfs main directory if it doesn't exist yet */ 3174 if (!stmmac_fs_dir) { 3175 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 3176 3177 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 3178 pr_err("ERROR %s, debugfs create directory failed\n", 3179 STMMAC_RESOURCE_NAME); 3180 3181 return -ENOMEM; 3182 } 3183 } 3184 #endif 3185 3186 return 0; 3187 } 3188 3189 static void __exit stmmac_exit(void) 3190 { 3191 #ifdef CONFIG_DEBUG_FS 3192 debugfs_remove_recursive(stmmac_fs_dir); 3193 #endif 3194 } 3195 3196 module_init(stmmac_init) 3197 module_exit(stmmac_exit) 3198 3199 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 3200 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 3201 MODULE_LICENSE("GPL"); 3202