1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <net/pkt_cls.h> 40 #include "stmmac_ptp.h" 41 #include "stmmac.h" 42 #include <linux/reset.h> 43 #include <linux/of_mdio.h> 44 #include "dwmac1000.h" 45 #include "dwxgmac2.h" 46 #include "hwif.h" 47 48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES) 49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 50 51 /* Module parameters */ 52 #define TX_TIMEO 5000 53 static int watchdog = TX_TIMEO; 54 module_param(watchdog, int, 0644); 55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 56 57 static int debug = -1; 58 module_param(debug, int, 0644); 59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 60 61 static int phyaddr = -1; 62 module_param(phyaddr, int, 0444); 63 MODULE_PARM_DESC(phyaddr, "Physical device address"); 64 65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 67 68 static int flow_ctrl = FLOW_AUTO; 69 module_param(flow_ctrl, int, 0644); 70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 71 72 static int pause = PAUSE_TIME; 73 module_param(pause, int, 0644); 74 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 75 76 #define TC_DEFAULT 64 77 static int tc = TC_DEFAULT; 78 module_param(tc, int, 0644); 79 MODULE_PARM_DESC(tc, "DMA threshold control value"); 80 81 #define DEFAULT_BUFSIZE 1536 82 static int buf_sz = DEFAULT_BUFSIZE; 83 module_param(buf_sz, int, 0644); 84 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 85 86 #define STMMAC_RX_COPYBREAK 256 87 88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 89 NETIF_MSG_LINK | NETIF_MSG_IFUP | 90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 91 92 #define STMMAC_DEFAULT_LPI_TIMER 1000 93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 94 module_param(eee_timer, int, 0644); 95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 97 98 /* By default the driver will use the ring mode to manage tx and rx descriptors, 99 * but allow user to force to use the chain instead of the ring 100 */ 101 static unsigned int chain_mode; 102 module_param(chain_mode, int, 0444); 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 104 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 106 107 #ifdef CONFIG_DEBUG_FS 108 static int stmmac_init_fs(struct net_device *dev); 109 static void stmmac_exit_fs(struct net_device *dev); 110 #endif 111 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 113 114 /** 115 * stmmac_verify_args - verify the driver parameters. 116 * Description: it checks the driver parameters and set a default in case of 117 * errors. 118 */ 119 static void stmmac_verify_args(void) 120 { 121 if (unlikely(watchdog < 0)) 122 watchdog = TX_TIMEO; 123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 124 buf_sz = DEFAULT_BUFSIZE; 125 if (unlikely(flow_ctrl > 1)) 126 flow_ctrl = FLOW_AUTO; 127 else if (likely(flow_ctrl < 0)) 128 flow_ctrl = FLOW_OFF; 129 if (unlikely((pause < 0) || (pause > 0xffff))) 130 pause = PAUSE_TIME; 131 if (eee_timer < 0) 132 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 133 } 134 135 /** 136 * stmmac_disable_all_queues - Disable all queues 137 * @priv: driver private structure 138 */ 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 140 { 141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 144 u32 queue; 145 146 for (queue = 0; queue < maxq; queue++) { 147 struct stmmac_channel *ch = &priv->channel[queue]; 148 149 if (queue < rx_queues_cnt) 150 napi_disable(&ch->rx_napi); 151 if (queue < tx_queues_cnt) 152 napi_disable(&ch->tx_napi); 153 } 154 } 155 156 /** 157 * stmmac_enable_all_queues - Enable all queues 158 * @priv: driver private structure 159 */ 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 161 { 162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 165 u32 queue; 166 167 for (queue = 0; queue < maxq; queue++) { 168 struct stmmac_channel *ch = &priv->channel[queue]; 169 170 if (queue < rx_queues_cnt) 171 napi_enable(&ch->rx_napi); 172 if (queue < tx_queues_cnt) 173 napi_enable(&ch->tx_napi); 174 } 175 } 176 177 /** 178 * stmmac_stop_all_queues - Stop all queues 179 * @priv: driver private structure 180 */ 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 182 { 183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 184 u32 queue; 185 186 for (queue = 0; queue < tx_queues_cnt; queue++) 187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 188 } 189 190 /** 191 * stmmac_start_all_queues - Start all queues 192 * @priv: driver private structure 193 */ 194 static void stmmac_start_all_queues(struct stmmac_priv *priv) 195 { 196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 197 u32 queue; 198 199 for (queue = 0; queue < tx_queues_cnt; queue++) 200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 201 } 202 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 204 { 205 if (!test_bit(STMMAC_DOWN, &priv->state) && 206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 207 queue_work(priv->wq, &priv->service_task); 208 } 209 210 static void stmmac_global_err(struct stmmac_priv *priv) 211 { 212 netif_carrier_off(priv->dev); 213 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 214 stmmac_service_event_schedule(priv); 215 } 216 217 /** 218 * stmmac_clk_csr_set - dynamically set the MDC clock 219 * @priv: driver private structure 220 * Description: this is to dynamically set the MDC clock according to the csr 221 * clock input. 222 * Note: 223 * If a specific clk_csr value is passed from the platform 224 * this means that the CSR Clock Range selection cannot be 225 * changed at run-time and it is fixed (as reported in the driver 226 * documentation). Viceversa the driver will try to set the MDC 227 * clock dynamically according to the actual clock input. 228 */ 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 230 { 231 u32 clk_rate; 232 233 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 234 235 /* Platform provided default clk_csr would be assumed valid 236 * for all other cases except for the below mentioned ones. 237 * For values higher than the IEEE 802.3 specified frequency 238 * we can not estimate the proper divider as it is not known 239 * the frequency of clk_csr_i. So we do not change the default 240 * divider. 241 */ 242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 243 if (clk_rate < CSR_F_35M) 244 priv->clk_csr = STMMAC_CSR_20_35M; 245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 246 priv->clk_csr = STMMAC_CSR_35_60M; 247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 248 priv->clk_csr = STMMAC_CSR_60_100M; 249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 250 priv->clk_csr = STMMAC_CSR_100_150M; 251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 252 priv->clk_csr = STMMAC_CSR_150_250M; 253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 254 priv->clk_csr = STMMAC_CSR_250_300M; 255 } 256 257 if (priv->plat->has_sun8i) { 258 if (clk_rate > 160000000) 259 priv->clk_csr = 0x03; 260 else if (clk_rate > 80000000) 261 priv->clk_csr = 0x02; 262 else if (clk_rate > 40000000) 263 priv->clk_csr = 0x01; 264 else 265 priv->clk_csr = 0; 266 } 267 268 if (priv->plat->has_xgmac) { 269 if (clk_rate > 400000000) 270 priv->clk_csr = 0x5; 271 else if (clk_rate > 350000000) 272 priv->clk_csr = 0x4; 273 else if (clk_rate > 300000000) 274 priv->clk_csr = 0x3; 275 else if (clk_rate > 250000000) 276 priv->clk_csr = 0x2; 277 else if (clk_rate > 150000000) 278 priv->clk_csr = 0x1; 279 else 280 priv->clk_csr = 0x0; 281 } 282 } 283 284 static void print_pkt(unsigned char *buf, int len) 285 { 286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 288 } 289 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 291 { 292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 293 u32 avail; 294 295 if (tx_q->dirty_tx > tx_q->cur_tx) 296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 297 else 298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 299 300 return avail; 301 } 302 303 /** 304 * stmmac_rx_dirty - Get RX queue dirty 305 * @priv: driver private structure 306 * @queue: RX queue index 307 */ 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 309 { 310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 311 u32 dirty; 312 313 if (rx_q->dirty_rx <= rx_q->cur_rx) 314 dirty = rx_q->cur_rx - rx_q->dirty_rx; 315 else 316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 317 318 return dirty; 319 } 320 321 /** 322 * stmmac_enable_eee_mode - check and enter in LPI mode 323 * @priv: driver private structure 324 * Description: this function is to verify and enter in LPI mode in case of 325 * EEE. 326 */ 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 328 { 329 u32 tx_cnt = priv->plat->tx_queues_to_use; 330 u32 queue; 331 332 /* check if all TX queues have the work finished */ 333 for (queue = 0; queue < tx_cnt; queue++) { 334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 335 336 if (tx_q->dirty_tx != tx_q->cur_tx) 337 return; /* still unfinished work */ 338 } 339 340 /* Check and enter in LPI mode */ 341 if (!priv->tx_path_in_lpi_mode) 342 stmmac_set_eee_mode(priv, priv->hw, 343 priv->plat->en_tx_lpi_clockgating); 344 } 345 346 /** 347 * stmmac_disable_eee_mode - disable and exit from LPI mode 348 * @priv: driver private structure 349 * Description: this function is to exit and disable EEE in case of 350 * LPI state is true. This is called by the xmit. 351 */ 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 353 { 354 stmmac_reset_eee_mode(priv, priv->hw); 355 del_timer_sync(&priv->eee_ctrl_timer); 356 priv->tx_path_in_lpi_mode = false; 357 } 358 359 /** 360 * stmmac_eee_ctrl_timer - EEE TX SW timer. 361 * @arg : data hook 362 * Description: 363 * if there is no data transfer and if we are not in LPI state, 364 * then MAC Transmitter can be moved to LPI state. 365 */ 366 static void stmmac_eee_ctrl_timer(struct timer_list *t) 367 { 368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 369 370 stmmac_enable_eee_mode(priv); 371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 372 } 373 374 /** 375 * stmmac_eee_init - init EEE 376 * @priv: driver private structure 377 * Description: 378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 379 * can also manage EEE, this function enable the LPI state and start related 380 * timer. 381 */ 382 bool stmmac_eee_init(struct stmmac_priv *priv) 383 { 384 int tx_lpi_timer = priv->tx_lpi_timer; 385 386 /* Using PCS we cannot dial with the phy registers at this stage 387 * so we do not support extra feature like EEE. 388 */ 389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 390 (priv->hw->pcs == STMMAC_PCS_TBI) || 391 (priv->hw->pcs == STMMAC_PCS_RTBI)) 392 return false; 393 394 /* Check if MAC core supports the EEE feature. */ 395 if (!priv->dma_cap.eee) 396 return false; 397 398 mutex_lock(&priv->lock); 399 400 /* Check if it needs to be deactivated */ 401 if (!priv->eee_active) { 402 if (priv->eee_enabled) { 403 netdev_dbg(priv->dev, "disable EEE\n"); 404 del_timer_sync(&priv->eee_ctrl_timer); 405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 406 } 407 mutex_unlock(&priv->lock); 408 return false; 409 } 410 411 if (priv->eee_active && !priv->eee_enabled) { 412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 415 tx_lpi_timer); 416 } 417 418 mutex_unlock(&priv->lock); 419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 420 return true; 421 } 422 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 424 * @priv: driver private structure 425 * @p : descriptor pointer 426 * @skb : the socket buffer 427 * Description : 428 * This function will read timestamp from the descriptor & pass it to stack. 429 * and also perform some sanity checks. 430 */ 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 432 struct dma_desc *p, struct sk_buff *skb) 433 { 434 struct skb_shared_hwtstamps shhwtstamp; 435 u64 ns = 0; 436 437 if (!priv->hwts_tx_en) 438 return; 439 440 /* exit if skb doesn't support hw tstamp */ 441 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 442 return; 443 444 /* check tx tstamp status */ 445 if (stmmac_get_tx_timestamp_status(priv, p)) { 446 /* get the valid tstamp */ 447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 448 449 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 450 shhwtstamp.hwtstamp = ns_to_ktime(ns); 451 452 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 453 /* pass tstamp to stack */ 454 skb_tstamp_tx(skb, &shhwtstamp); 455 } 456 457 return; 458 } 459 460 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 461 * @priv: driver private structure 462 * @p : descriptor pointer 463 * @np : next descriptor pointer 464 * @skb : the socket buffer 465 * Description : 466 * This function will read received packet's timestamp from the descriptor 467 * and pass it to stack. It also perform some sanity checks. 468 */ 469 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 470 struct dma_desc *np, struct sk_buff *skb) 471 { 472 struct skb_shared_hwtstamps *shhwtstamp = NULL; 473 struct dma_desc *desc = p; 474 u64 ns = 0; 475 476 if (!priv->hwts_rx_en) 477 return; 478 /* For GMAC4, the valid timestamp is from CTX next desc. */ 479 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 480 desc = np; 481 482 /* Check if timestamp is available */ 483 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 484 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 485 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 486 shhwtstamp = skb_hwtstamps(skb); 487 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 488 shhwtstamp->hwtstamp = ns_to_ktime(ns); 489 } else { 490 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 491 } 492 } 493 494 /** 495 * stmmac_hwtstamp_set - control hardware timestamping. 496 * @dev: device pointer. 497 * @ifr: An IOCTL specific structure, that can contain a pointer to 498 * a proprietary structure used to pass information to the driver. 499 * Description: 500 * This function configures the MAC to enable/disable both outgoing(TX) 501 * and incoming(RX) packets time stamping based on user input. 502 * Return Value: 503 * 0 on success and an appropriate -ve integer on failure. 504 */ 505 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 506 { 507 struct stmmac_priv *priv = netdev_priv(dev); 508 struct hwtstamp_config config; 509 struct timespec64 now; 510 u64 temp = 0; 511 u32 ptp_v2 = 0; 512 u32 tstamp_all = 0; 513 u32 ptp_over_ipv4_udp = 0; 514 u32 ptp_over_ipv6_udp = 0; 515 u32 ptp_over_ethernet = 0; 516 u32 snap_type_sel = 0; 517 u32 ts_master_en = 0; 518 u32 ts_event_en = 0; 519 u32 sec_inc = 0; 520 u32 value = 0; 521 bool xmac; 522 523 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 524 525 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 526 netdev_alert(priv->dev, "No support for HW time stamping\n"); 527 priv->hwts_tx_en = 0; 528 priv->hwts_rx_en = 0; 529 530 return -EOPNOTSUPP; 531 } 532 533 if (copy_from_user(&config, ifr->ifr_data, 534 sizeof(config))) 535 return -EFAULT; 536 537 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 538 __func__, config.flags, config.tx_type, config.rx_filter); 539 540 /* reserved for future extensions */ 541 if (config.flags) 542 return -EINVAL; 543 544 if (config.tx_type != HWTSTAMP_TX_OFF && 545 config.tx_type != HWTSTAMP_TX_ON) 546 return -ERANGE; 547 548 if (priv->adv_ts) { 549 switch (config.rx_filter) { 550 case HWTSTAMP_FILTER_NONE: 551 /* time stamp no incoming packet at all */ 552 config.rx_filter = HWTSTAMP_FILTER_NONE; 553 break; 554 555 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 556 /* PTP v1, UDP, any kind of event packet */ 557 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 558 /* 'xmac' hardware can support Sync, Pdelay_Req and 559 * Pdelay_resp by setting bit14 and bits17/16 to 01 560 * This leaves Delay_Req timestamps out. 561 * Enable all events *and* general purpose message 562 * timestamping 563 */ 564 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 565 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 566 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 567 break; 568 569 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 570 /* PTP v1, UDP, Sync packet */ 571 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 572 /* take time stamp for SYNC messages only */ 573 ts_event_en = PTP_TCR_TSEVNTENA; 574 575 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 576 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 577 break; 578 579 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 580 /* PTP v1, UDP, Delay_req packet */ 581 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 582 /* take time stamp for Delay_Req messages only */ 583 ts_master_en = PTP_TCR_TSMSTRENA; 584 ts_event_en = PTP_TCR_TSEVNTENA; 585 586 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 587 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 588 break; 589 590 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 591 /* PTP v2, UDP, any kind of event packet */ 592 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 593 ptp_v2 = PTP_TCR_TSVER2ENA; 594 /* take time stamp for all event messages */ 595 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 596 597 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 598 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 599 break; 600 601 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 602 /* PTP v2, UDP, Sync packet */ 603 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 604 ptp_v2 = PTP_TCR_TSVER2ENA; 605 /* take time stamp for SYNC messages only */ 606 ts_event_en = PTP_TCR_TSEVNTENA; 607 608 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 609 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 610 break; 611 612 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 613 /* PTP v2, UDP, Delay_req packet */ 614 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 615 ptp_v2 = PTP_TCR_TSVER2ENA; 616 /* take time stamp for Delay_Req messages only */ 617 ts_master_en = PTP_TCR_TSMSTRENA; 618 ts_event_en = PTP_TCR_TSEVNTENA; 619 620 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 621 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 622 break; 623 624 case HWTSTAMP_FILTER_PTP_V2_EVENT: 625 /* PTP v2/802.AS1 any layer, any kind of event packet */ 626 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 627 ptp_v2 = PTP_TCR_TSVER2ENA; 628 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 629 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 630 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 631 ptp_over_ethernet = PTP_TCR_TSIPENA; 632 break; 633 634 case HWTSTAMP_FILTER_PTP_V2_SYNC: 635 /* PTP v2/802.AS1, any layer, Sync packet */ 636 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 637 ptp_v2 = PTP_TCR_TSVER2ENA; 638 /* take time stamp for SYNC messages only */ 639 ts_event_en = PTP_TCR_TSEVNTENA; 640 641 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 642 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 643 ptp_over_ethernet = PTP_TCR_TSIPENA; 644 break; 645 646 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 647 /* PTP v2/802.AS1, any layer, Delay_req packet */ 648 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 649 ptp_v2 = PTP_TCR_TSVER2ENA; 650 /* take time stamp for Delay_Req messages only */ 651 ts_master_en = PTP_TCR_TSMSTRENA; 652 ts_event_en = PTP_TCR_TSEVNTENA; 653 654 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 655 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 656 ptp_over_ethernet = PTP_TCR_TSIPENA; 657 break; 658 659 case HWTSTAMP_FILTER_NTP_ALL: 660 case HWTSTAMP_FILTER_ALL: 661 /* time stamp any incoming packet */ 662 config.rx_filter = HWTSTAMP_FILTER_ALL; 663 tstamp_all = PTP_TCR_TSENALL; 664 break; 665 666 default: 667 return -ERANGE; 668 } 669 } else { 670 switch (config.rx_filter) { 671 case HWTSTAMP_FILTER_NONE: 672 config.rx_filter = HWTSTAMP_FILTER_NONE; 673 break; 674 default: 675 /* PTP v1, UDP, any kind of event packet */ 676 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 677 break; 678 } 679 } 680 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 681 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 682 683 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 684 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 685 else { 686 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 687 tstamp_all | ptp_v2 | ptp_over_ethernet | 688 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 689 ts_master_en | snap_type_sel); 690 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 691 692 /* program Sub Second Increment reg */ 693 stmmac_config_sub_second_increment(priv, 694 priv->ptpaddr, priv->plat->clk_ptp_rate, 695 xmac, &sec_inc); 696 temp = div_u64(1000000000ULL, sec_inc); 697 698 /* Store sub second increment and flags for later use */ 699 priv->sub_second_inc = sec_inc; 700 priv->systime_flags = value; 701 702 /* calculate default added value: 703 * formula is : 704 * addend = (2^32)/freq_div_ratio; 705 * where, freq_div_ratio = 1e9ns/sec_inc 706 */ 707 temp = (u64)(temp << 32); 708 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 709 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 710 711 /* initialize system time */ 712 ktime_get_real_ts64(&now); 713 714 /* lower 32 bits of tv_sec are safe until y2106 */ 715 stmmac_init_systime(priv, priv->ptpaddr, 716 (u32)now.tv_sec, now.tv_nsec); 717 } 718 719 memcpy(&priv->tstamp_config, &config, sizeof(config)); 720 721 return copy_to_user(ifr->ifr_data, &config, 722 sizeof(config)) ? -EFAULT : 0; 723 } 724 725 /** 726 * stmmac_hwtstamp_get - read hardware timestamping. 727 * @dev: device pointer. 728 * @ifr: An IOCTL specific structure, that can contain a pointer to 729 * a proprietary structure used to pass information to the driver. 730 * Description: 731 * This function obtain the current hardware timestamping settings 732 as requested. 733 */ 734 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 735 { 736 struct stmmac_priv *priv = netdev_priv(dev); 737 struct hwtstamp_config *config = &priv->tstamp_config; 738 739 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 740 return -EOPNOTSUPP; 741 742 return copy_to_user(ifr->ifr_data, config, 743 sizeof(*config)) ? -EFAULT : 0; 744 } 745 746 /** 747 * stmmac_init_ptp - init PTP 748 * @priv: driver private structure 749 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 750 * This is done by looking at the HW cap. register. 751 * This function also registers the ptp driver. 752 */ 753 static int stmmac_init_ptp(struct stmmac_priv *priv) 754 { 755 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 756 757 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 758 return -EOPNOTSUPP; 759 760 priv->adv_ts = 0; 761 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 762 if (xmac && priv->dma_cap.atime_stamp) 763 priv->adv_ts = 1; 764 /* Dwmac 3.x core with extend_desc can support adv_ts */ 765 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 766 priv->adv_ts = 1; 767 768 if (priv->dma_cap.time_stamp) 769 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 770 771 if (priv->adv_ts) 772 netdev_info(priv->dev, 773 "IEEE 1588-2008 Advanced Timestamp supported\n"); 774 775 priv->hwts_tx_en = 0; 776 priv->hwts_rx_en = 0; 777 778 stmmac_ptp_register(priv); 779 780 return 0; 781 } 782 783 static void stmmac_release_ptp(struct stmmac_priv *priv) 784 { 785 if (priv->plat->clk_ptp_ref) 786 clk_disable_unprepare(priv->plat->clk_ptp_ref); 787 stmmac_ptp_unregister(priv); 788 } 789 790 /** 791 * stmmac_mac_flow_ctrl - Configure flow control in all queues 792 * @priv: driver private structure 793 * Description: It is used for configuring the flow control in all queues 794 */ 795 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 796 { 797 u32 tx_cnt = priv->plat->tx_queues_to_use; 798 799 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 800 priv->pause, tx_cnt); 801 } 802 803 static void stmmac_validate(struct phylink_config *config, 804 unsigned long *supported, 805 struct phylink_link_state *state) 806 { 807 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 808 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 809 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 810 int tx_cnt = priv->plat->tx_queues_to_use; 811 int max_speed = priv->plat->max_speed; 812 813 phylink_set(mac_supported, 10baseT_Half); 814 phylink_set(mac_supported, 10baseT_Full); 815 phylink_set(mac_supported, 100baseT_Half); 816 phylink_set(mac_supported, 100baseT_Full); 817 818 phylink_set(mac_supported, Autoneg); 819 phylink_set(mac_supported, Pause); 820 phylink_set(mac_supported, Asym_Pause); 821 phylink_set_port_modes(mac_supported); 822 823 if (priv->plat->has_gmac || 824 priv->plat->has_gmac4 || 825 priv->plat->has_xgmac) { 826 phylink_set(mac_supported, 1000baseT_Half); 827 phylink_set(mac_supported, 1000baseT_Full); 828 phylink_set(mac_supported, 1000baseKX_Full); 829 } 830 831 /* Cut down 1G if asked to */ 832 if ((max_speed > 0) && (max_speed < 1000)) { 833 phylink_set(mask, 1000baseT_Full); 834 phylink_set(mask, 1000baseX_Full); 835 } else if (priv->plat->has_xgmac) { 836 phylink_set(mac_supported, 2500baseT_Full); 837 phylink_set(mac_supported, 5000baseT_Full); 838 phylink_set(mac_supported, 10000baseSR_Full); 839 phylink_set(mac_supported, 10000baseLR_Full); 840 phylink_set(mac_supported, 10000baseER_Full); 841 phylink_set(mac_supported, 10000baseLRM_Full); 842 phylink_set(mac_supported, 10000baseT_Full); 843 phylink_set(mac_supported, 10000baseKX4_Full); 844 phylink_set(mac_supported, 10000baseKR_Full); 845 } 846 847 /* Half-Duplex can only work with single queue */ 848 if (tx_cnt > 1) { 849 phylink_set(mask, 10baseT_Half); 850 phylink_set(mask, 100baseT_Half); 851 phylink_set(mask, 1000baseT_Half); 852 } 853 854 bitmap_and(supported, supported, mac_supported, 855 __ETHTOOL_LINK_MODE_MASK_NBITS); 856 bitmap_andnot(supported, supported, mask, 857 __ETHTOOL_LINK_MODE_MASK_NBITS); 858 bitmap_and(state->advertising, state->advertising, mac_supported, 859 __ETHTOOL_LINK_MODE_MASK_NBITS); 860 bitmap_andnot(state->advertising, state->advertising, mask, 861 __ETHTOOL_LINK_MODE_MASK_NBITS); 862 } 863 864 static int stmmac_mac_link_state(struct phylink_config *config, 865 struct phylink_link_state *state) 866 { 867 return -EOPNOTSUPP; 868 } 869 870 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 871 const struct phylink_link_state *state) 872 { 873 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 874 u32 ctrl; 875 876 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 877 ctrl &= ~priv->hw->link.speed_mask; 878 879 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 880 switch (state->speed) { 881 case SPEED_10000: 882 ctrl |= priv->hw->link.xgmii.speed10000; 883 break; 884 case SPEED_5000: 885 ctrl |= priv->hw->link.xgmii.speed5000; 886 break; 887 case SPEED_2500: 888 ctrl |= priv->hw->link.xgmii.speed2500; 889 break; 890 default: 891 return; 892 } 893 } else { 894 switch (state->speed) { 895 case SPEED_2500: 896 ctrl |= priv->hw->link.speed2500; 897 break; 898 case SPEED_1000: 899 ctrl |= priv->hw->link.speed1000; 900 break; 901 case SPEED_100: 902 ctrl |= priv->hw->link.speed100; 903 break; 904 case SPEED_10: 905 ctrl |= priv->hw->link.speed10; 906 break; 907 default: 908 return; 909 } 910 } 911 912 priv->speed = state->speed; 913 914 if (priv->plat->fix_mac_speed) 915 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed); 916 917 if (!state->duplex) 918 ctrl &= ~priv->hw->link.duplex; 919 else 920 ctrl |= priv->hw->link.duplex; 921 922 /* Flow Control operation */ 923 if (state->pause) 924 stmmac_mac_flow_ctrl(priv, state->duplex); 925 926 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 927 } 928 929 static void stmmac_mac_an_restart(struct phylink_config *config) 930 { 931 /* Not Supported */ 932 } 933 934 static void stmmac_mac_link_down(struct phylink_config *config, 935 unsigned int mode, phy_interface_t interface) 936 { 937 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 938 939 stmmac_mac_set(priv, priv->ioaddr, false); 940 priv->eee_active = false; 941 stmmac_eee_init(priv); 942 stmmac_set_eee_pls(priv, priv->hw, false); 943 } 944 945 static void stmmac_mac_link_up(struct phylink_config *config, 946 unsigned int mode, phy_interface_t interface, 947 struct phy_device *phy) 948 { 949 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 950 951 stmmac_mac_set(priv, priv->ioaddr, true); 952 if (phy && priv->dma_cap.eee) { 953 priv->eee_active = phy_init_eee(phy, 1) >= 0; 954 priv->eee_enabled = stmmac_eee_init(priv); 955 stmmac_set_eee_pls(priv, priv->hw, true); 956 } 957 } 958 959 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 960 .validate = stmmac_validate, 961 .mac_link_state = stmmac_mac_link_state, 962 .mac_config = stmmac_mac_config, 963 .mac_an_restart = stmmac_mac_an_restart, 964 .mac_link_down = stmmac_mac_link_down, 965 .mac_link_up = stmmac_mac_link_up, 966 }; 967 968 /** 969 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 970 * @priv: driver private structure 971 * Description: this is to verify if the HW supports the PCS. 972 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 973 * configured for the TBI, RTBI, or SGMII PHY interface. 974 */ 975 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 976 { 977 int interface = priv->plat->interface; 978 979 if (priv->dma_cap.pcs) { 980 if ((interface == PHY_INTERFACE_MODE_RGMII) || 981 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 982 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 983 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 984 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 985 priv->hw->pcs = STMMAC_PCS_RGMII; 986 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 987 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 988 priv->hw->pcs = STMMAC_PCS_SGMII; 989 } 990 } 991 } 992 993 /** 994 * stmmac_init_phy - PHY initialization 995 * @dev: net device structure 996 * Description: it initializes the driver's PHY state, and attaches the PHY 997 * to the mac driver. 998 * Return value: 999 * 0 on success 1000 */ 1001 static int stmmac_init_phy(struct net_device *dev) 1002 { 1003 struct stmmac_priv *priv = netdev_priv(dev); 1004 struct device_node *node; 1005 int ret; 1006 1007 node = priv->plat->phylink_node; 1008 1009 if (node) 1010 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1011 1012 /* Some DT bindings do not set-up the PHY handle. Let's try to 1013 * manually parse it 1014 */ 1015 if (!node || ret) { 1016 int addr = priv->plat->phy_addr; 1017 struct phy_device *phydev; 1018 1019 phydev = mdiobus_get_phy(priv->mii, addr); 1020 if (!phydev) { 1021 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1022 return -ENODEV; 1023 } 1024 1025 ret = phylink_connect_phy(priv->phylink, phydev); 1026 } 1027 1028 return ret; 1029 } 1030 1031 static int stmmac_phy_setup(struct stmmac_priv *priv) 1032 { 1033 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1034 int mode = priv->plat->interface; 1035 struct phylink *phylink; 1036 1037 priv->phylink_config.dev = &priv->dev->dev; 1038 priv->phylink_config.type = PHYLINK_NETDEV; 1039 1040 phylink = phylink_create(&priv->phylink_config, fwnode, 1041 mode, &stmmac_phylink_mac_ops); 1042 if (IS_ERR(phylink)) 1043 return PTR_ERR(phylink); 1044 1045 priv->phylink = phylink; 1046 return 0; 1047 } 1048 1049 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1050 { 1051 u32 rx_cnt = priv->plat->rx_queues_to_use; 1052 void *head_rx; 1053 u32 queue; 1054 1055 /* Display RX rings */ 1056 for (queue = 0; queue < rx_cnt; queue++) { 1057 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1058 1059 pr_info("\tRX Queue %u rings\n", queue); 1060 1061 if (priv->extend_desc) 1062 head_rx = (void *)rx_q->dma_erx; 1063 else 1064 head_rx = (void *)rx_q->dma_rx; 1065 1066 /* Display RX ring */ 1067 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1068 } 1069 } 1070 1071 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1072 { 1073 u32 tx_cnt = priv->plat->tx_queues_to_use; 1074 void *head_tx; 1075 u32 queue; 1076 1077 /* Display TX rings */ 1078 for (queue = 0; queue < tx_cnt; queue++) { 1079 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1080 1081 pr_info("\tTX Queue %d rings\n", queue); 1082 1083 if (priv->extend_desc) 1084 head_tx = (void *)tx_q->dma_etx; 1085 else 1086 head_tx = (void *)tx_q->dma_tx; 1087 1088 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1089 } 1090 } 1091 1092 static void stmmac_display_rings(struct stmmac_priv *priv) 1093 { 1094 /* Display RX ring */ 1095 stmmac_display_rx_rings(priv); 1096 1097 /* Display TX ring */ 1098 stmmac_display_tx_rings(priv); 1099 } 1100 1101 static int stmmac_set_bfsize(int mtu, int bufsize) 1102 { 1103 int ret = bufsize; 1104 1105 if (mtu >= BUF_SIZE_4KiB) 1106 ret = BUF_SIZE_8KiB; 1107 else if (mtu >= BUF_SIZE_2KiB) 1108 ret = BUF_SIZE_4KiB; 1109 else if (mtu > DEFAULT_BUFSIZE) 1110 ret = BUF_SIZE_2KiB; 1111 else 1112 ret = DEFAULT_BUFSIZE; 1113 1114 return ret; 1115 } 1116 1117 /** 1118 * stmmac_clear_rx_descriptors - clear RX descriptors 1119 * @priv: driver private structure 1120 * @queue: RX queue index 1121 * Description: this function is called to clear the RX descriptors 1122 * in case of both basic and extended descriptors are used. 1123 */ 1124 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1125 { 1126 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1127 int i; 1128 1129 /* Clear the RX descriptors */ 1130 for (i = 0; i < DMA_RX_SIZE; i++) 1131 if (priv->extend_desc) 1132 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1133 priv->use_riwt, priv->mode, 1134 (i == DMA_RX_SIZE - 1), 1135 priv->dma_buf_sz); 1136 else 1137 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1138 priv->use_riwt, priv->mode, 1139 (i == DMA_RX_SIZE - 1), 1140 priv->dma_buf_sz); 1141 } 1142 1143 /** 1144 * stmmac_clear_tx_descriptors - clear tx descriptors 1145 * @priv: driver private structure 1146 * @queue: TX queue index. 1147 * Description: this function is called to clear the TX descriptors 1148 * in case of both basic and extended descriptors are used. 1149 */ 1150 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1151 { 1152 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1153 int i; 1154 1155 /* Clear the TX descriptors */ 1156 for (i = 0; i < DMA_TX_SIZE; i++) 1157 if (priv->extend_desc) 1158 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1159 priv->mode, (i == DMA_TX_SIZE - 1)); 1160 else 1161 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1162 priv->mode, (i == DMA_TX_SIZE - 1)); 1163 } 1164 1165 /** 1166 * stmmac_clear_descriptors - clear descriptors 1167 * @priv: driver private structure 1168 * Description: this function is called to clear the TX and RX descriptors 1169 * in case of both basic and extended descriptors are used. 1170 */ 1171 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1172 { 1173 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1174 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1175 u32 queue; 1176 1177 /* Clear the RX descriptors */ 1178 for (queue = 0; queue < rx_queue_cnt; queue++) 1179 stmmac_clear_rx_descriptors(priv, queue); 1180 1181 /* Clear the TX descriptors */ 1182 for (queue = 0; queue < tx_queue_cnt; queue++) 1183 stmmac_clear_tx_descriptors(priv, queue); 1184 } 1185 1186 /** 1187 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1188 * @priv: driver private structure 1189 * @p: descriptor pointer 1190 * @i: descriptor index 1191 * @flags: gfp flag 1192 * @queue: RX queue index 1193 * Description: this function is called to allocate a receive buffer, perform 1194 * the DMA mapping and init the descriptor. 1195 */ 1196 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1197 int i, gfp_t flags, u32 queue) 1198 { 1199 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1200 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1201 1202 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1203 if (!buf->page) 1204 return -ENOMEM; 1205 1206 buf->addr = page_pool_get_dma_addr(buf->page); 1207 stmmac_set_desc_addr(priv, p, buf->addr); 1208 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1209 stmmac_init_desc3(priv, p); 1210 1211 return 0; 1212 } 1213 1214 /** 1215 * stmmac_free_rx_buffer - free RX dma buffers 1216 * @priv: private structure 1217 * @queue: RX queue index 1218 * @i: buffer index. 1219 */ 1220 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1221 { 1222 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1223 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1224 1225 if (buf->page) 1226 page_pool_put_page(rx_q->page_pool, buf->page, false); 1227 buf->page = NULL; 1228 } 1229 1230 /** 1231 * stmmac_free_tx_buffer - free RX dma buffers 1232 * @priv: private structure 1233 * @queue: RX queue index 1234 * @i: buffer index. 1235 */ 1236 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1237 { 1238 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1239 1240 if (tx_q->tx_skbuff_dma[i].buf) { 1241 if (tx_q->tx_skbuff_dma[i].map_as_page) 1242 dma_unmap_page(priv->device, 1243 tx_q->tx_skbuff_dma[i].buf, 1244 tx_q->tx_skbuff_dma[i].len, 1245 DMA_TO_DEVICE); 1246 else 1247 dma_unmap_single(priv->device, 1248 tx_q->tx_skbuff_dma[i].buf, 1249 tx_q->tx_skbuff_dma[i].len, 1250 DMA_TO_DEVICE); 1251 } 1252 1253 if (tx_q->tx_skbuff[i]) { 1254 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1255 tx_q->tx_skbuff[i] = NULL; 1256 tx_q->tx_skbuff_dma[i].buf = 0; 1257 tx_q->tx_skbuff_dma[i].map_as_page = false; 1258 } 1259 } 1260 1261 /** 1262 * init_dma_rx_desc_rings - init the RX descriptor rings 1263 * @dev: net device structure 1264 * @flags: gfp flag. 1265 * Description: this function initializes the DMA RX descriptors 1266 * and allocates the socket buffers. It supports the chained and ring 1267 * modes. 1268 */ 1269 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1270 { 1271 struct stmmac_priv *priv = netdev_priv(dev); 1272 u32 rx_count = priv->plat->rx_queues_to_use; 1273 int ret = -ENOMEM; 1274 int bfsize = 0; 1275 int queue; 1276 int i; 1277 1278 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 1279 if (bfsize < 0) 1280 bfsize = 0; 1281 1282 if (bfsize < BUF_SIZE_16KiB) 1283 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1284 1285 priv->dma_buf_sz = bfsize; 1286 1287 /* RX INITIALIZATION */ 1288 netif_dbg(priv, probe, priv->dev, 1289 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1290 1291 for (queue = 0; queue < rx_count; queue++) { 1292 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1293 1294 netif_dbg(priv, probe, priv->dev, 1295 "(%s) dma_rx_phy=0x%08x\n", __func__, 1296 (u32)rx_q->dma_rx_phy); 1297 1298 for (i = 0; i < DMA_RX_SIZE; i++) { 1299 struct dma_desc *p; 1300 1301 if (priv->extend_desc) 1302 p = &((rx_q->dma_erx + i)->basic); 1303 else 1304 p = rx_q->dma_rx + i; 1305 1306 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1307 queue); 1308 if (ret) 1309 goto err_init_rx_buffers; 1310 } 1311 1312 rx_q->cur_rx = 0; 1313 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1314 1315 stmmac_clear_rx_descriptors(priv, queue); 1316 1317 /* Setup the chained descriptor addresses */ 1318 if (priv->mode == STMMAC_CHAIN_MODE) { 1319 if (priv->extend_desc) 1320 stmmac_mode_init(priv, rx_q->dma_erx, 1321 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1322 else 1323 stmmac_mode_init(priv, rx_q->dma_rx, 1324 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1325 } 1326 } 1327 1328 buf_sz = bfsize; 1329 1330 return 0; 1331 1332 err_init_rx_buffers: 1333 while (queue >= 0) { 1334 while (--i >= 0) 1335 stmmac_free_rx_buffer(priv, queue, i); 1336 1337 if (queue == 0) 1338 break; 1339 1340 i = DMA_RX_SIZE; 1341 queue--; 1342 } 1343 1344 return ret; 1345 } 1346 1347 /** 1348 * init_dma_tx_desc_rings - init the TX descriptor rings 1349 * @dev: net device structure. 1350 * Description: this function initializes the DMA TX descriptors 1351 * and allocates the socket buffers. It supports the chained and ring 1352 * modes. 1353 */ 1354 static int init_dma_tx_desc_rings(struct net_device *dev) 1355 { 1356 struct stmmac_priv *priv = netdev_priv(dev); 1357 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1358 u32 queue; 1359 int i; 1360 1361 for (queue = 0; queue < tx_queue_cnt; queue++) { 1362 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1363 1364 netif_dbg(priv, probe, priv->dev, 1365 "(%s) dma_tx_phy=0x%08x\n", __func__, 1366 (u32)tx_q->dma_tx_phy); 1367 1368 /* Setup the chained descriptor addresses */ 1369 if (priv->mode == STMMAC_CHAIN_MODE) { 1370 if (priv->extend_desc) 1371 stmmac_mode_init(priv, tx_q->dma_etx, 1372 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1373 else 1374 stmmac_mode_init(priv, tx_q->dma_tx, 1375 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1376 } 1377 1378 for (i = 0; i < DMA_TX_SIZE; i++) { 1379 struct dma_desc *p; 1380 if (priv->extend_desc) 1381 p = &((tx_q->dma_etx + i)->basic); 1382 else 1383 p = tx_q->dma_tx + i; 1384 1385 stmmac_clear_desc(priv, p); 1386 1387 tx_q->tx_skbuff_dma[i].buf = 0; 1388 tx_q->tx_skbuff_dma[i].map_as_page = false; 1389 tx_q->tx_skbuff_dma[i].len = 0; 1390 tx_q->tx_skbuff_dma[i].last_segment = false; 1391 tx_q->tx_skbuff[i] = NULL; 1392 } 1393 1394 tx_q->dirty_tx = 0; 1395 tx_q->cur_tx = 0; 1396 tx_q->mss = 0; 1397 1398 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1399 } 1400 1401 return 0; 1402 } 1403 1404 /** 1405 * init_dma_desc_rings - init the RX/TX descriptor rings 1406 * @dev: net device structure 1407 * @flags: gfp flag. 1408 * Description: this function initializes the DMA RX/TX descriptors 1409 * and allocates the socket buffers. It supports the chained and ring 1410 * modes. 1411 */ 1412 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1413 { 1414 struct stmmac_priv *priv = netdev_priv(dev); 1415 int ret; 1416 1417 ret = init_dma_rx_desc_rings(dev, flags); 1418 if (ret) 1419 return ret; 1420 1421 ret = init_dma_tx_desc_rings(dev); 1422 1423 stmmac_clear_descriptors(priv); 1424 1425 if (netif_msg_hw(priv)) 1426 stmmac_display_rings(priv); 1427 1428 return ret; 1429 } 1430 1431 /** 1432 * dma_free_rx_skbufs - free RX dma buffers 1433 * @priv: private structure 1434 * @queue: RX queue index 1435 */ 1436 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1437 { 1438 int i; 1439 1440 for (i = 0; i < DMA_RX_SIZE; i++) 1441 stmmac_free_rx_buffer(priv, queue, i); 1442 } 1443 1444 /** 1445 * dma_free_tx_skbufs - free TX dma buffers 1446 * @priv: private structure 1447 * @queue: TX queue index 1448 */ 1449 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1450 { 1451 int i; 1452 1453 for (i = 0; i < DMA_TX_SIZE; i++) 1454 stmmac_free_tx_buffer(priv, queue, i); 1455 } 1456 1457 /** 1458 * free_dma_rx_desc_resources - free RX dma desc resources 1459 * @priv: private structure 1460 */ 1461 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1462 { 1463 u32 rx_count = priv->plat->rx_queues_to_use; 1464 u32 queue; 1465 1466 /* Free RX queue resources */ 1467 for (queue = 0; queue < rx_count; queue++) { 1468 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1469 1470 /* Release the DMA RX socket buffers */ 1471 dma_free_rx_skbufs(priv, queue); 1472 1473 /* Free DMA regions of consistent memory previously allocated */ 1474 if (!priv->extend_desc) 1475 dma_free_coherent(priv->device, 1476 DMA_RX_SIZE * sizeof(struct dma_desc), 1477 rx_q->dma_rx, rx_q->dma_rx_phy); 1478 else 1479 dma_free_coherent(priv->device, DMA_RX_SIZE * 1480 sizeof(struct dma_extended_desc), 1481 rx_q->dma_erx, rx_q->dma_rx_phy); 1482 1483 kfree(rx_q->buf_pool); 1484 if (rx_q->page_pool) { 1485 page_pool_request_shutdown(rx_q->page_pool); 1486 page_pool_destroy(rx_q->page_pool); 1487 } 1488 } 1489 } 1490 1491 /** 1492 * free_dma_tx_desc_resources - free TX dma desc resources 1493 * @priv: private structure 1494 */ 1495 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1496 { 1497 u32 tx_count = priv->plat->tx_queues_to_use; 1498 u32 queue; 1499 1500 /* Free TX queue resources */ 1501 for (queue = 0; queue < tx_count; queue++) { 1502 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1503 1504 /* Release the DMA TX socket buffers */ 1505 dma_free_tx_skbufs(priv, queue); 1506 1507 /* Free DMA regions of consistent memory previously allocated */ 1508 if (!priv->extend_desc) 1509 dma_free_coherent(priv->device, 1510 DMA_TX_SIZE * sizeof(struct dma_desc), 1511 tx_q->dma_tx, tx_q->dma_tx_phy); 1512 else 1513 dma_free_coherent(priv->device, DMA_TX_SIZE * 1514 sizeof(struct dma_extended_desc), 1515 tx_q->dma_etx, tx_q->dma_tx_phy); 1516 1517 kfree(tx_q->tx_skbuff_dma); 1518 kfree(tx_q->tx_skbuff); 1519 } 1520 } 1521 1522 /** 1523 * alloc_dma_rx_desc_resources - alloc RX resources. 1524 * @priv: private structure 1525 * Description: according to which descriptor can be used (extend or basic) 1526 * this function allocates the resources for TX and RX paths. In case of 1527 * reception, for example, it pre-allocated the RX socket buffer in order to 1528 * allow zero-copy mechanism. 1529 */ 1530 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1531 { 1532 u32 rx_count = priv->plat->rx_queues_to_use; 1533 int ret = -ENOMEM; 1534 u32 queue; 1535 1536 /* RX queues buffers and DMA */ 1537 for (queue = 0; queue < rx_count; queue++) { 1538 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1539 struct page_pool_params pp_params = { 0 }; 1540 1541 rx_q->queue_index = queue; 1542 rx_q->priv_data = priv; 1543 1544 pp_params.flags = PP_FLAG_DMA_MAP; 1545 pp_params.pool_size = DMA_RX_SIZE; 1546 pp_params.order = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1547 pp_params.nid = dev_to_node(priv->device); 1548 pp_params.dev = priv->device; 1549 pp_params.dma_dir = DMA_FROM_DEVICE; 1550 1551 rx_q->page_pool = page_pool_create(&pp_params); 1552 if (IS_ERR(rx_q->page_pool)) { 1553 ret = PTR_ERR(rx_q->page_pool); 1554 rx_q->page_pool = NULL; 1555 goto err_dma; 1556 } 1557 1558 rx_q->buf_pool = kmalloc_array(DMA_RX_SIZE, 1559 sizeof(*rx_q->buf_pool), 1560 GFP_KERNEL); 1561 if (!rx_q->buf_pool) 1562 goto err_dma; 1563 1564 if (priv->extend_desc) { 1565 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1566 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1567 &rx_q->dma_rx_phy, 1568 GFP_KERNEL); 1569 if (!rx_q->dma_erx) 1570 goto err_dma; 1571 1572 } else { 1573 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1574 DMA_RX_SIZE * sizeof(struct dma_desc), 1575 &rx_q->dma_rx_phy, 1576 GFP_KERNEL); 1577 if (!rx_q->dma_rx) 1578 goto err_dma; 1579 } 1580 } 1581 1582 return 0; 1583 1584 err_dma: 1585 free_dma_rx_desc_resources(priv); 1586 1587 return ret; 1588 } 1589 1590 /** 1591 * alloc_dma_tx_desc_resources - alloc TX resources. 1592 * @priv: private structure 1593 * Description: according to which descriptor can be used (extend or basic) 1594 * this function allocates the resources for TX and RX paths. In case of 1595 * reception, for example, it pre-allocated the RX socket buffer in order to 1596 * allow zero-copy mechanism. 1597 */ 1598 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1599 { 1600 u32 tx_count = priv->plat->tx_queues_to_use; 1601 int ret = -ENOMEM; 1602 u32 queue; 1603 1604 /* TX queues buffers and DMA */ 1605 for (queue = 0; queue < tx_count; queue++) { 1606 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1607 1608 tx_q->queue_index = queue; 1609 tx_q->priv_data = priv; 1610 1611 tx_q->tx_skbuff_dma = kmalloc_array(DMA_TX_SIZE, 1612 sizeof(*tx_q->tx_skbuff_dma), 1613 GFP_KERNEL); 1614 if (!tx_q->tx_skbuff_dma) 1615 goto err_dma; 1616 1617 tx_q->tx_skbuff = kmalloc_array(DMA_TX_SIZE, 1618 sizeof(struct sk_buff *), 1619 GFP_KERNEL); 1620 if (!tx_q->tx_skbuff) 1621 goto err_dma; 1622 1623 if (priv->extend_desc) { 1624 tx_q->dma_etx = dma_alloc_coherent(priv->device, 1625 DMA_TX_SIZE * sizeof(struct dma_extended_desc), 1626 &tx_q->dma_tx_phy, 1627 GFP_KERNEL); 1628 if (!tx_q->dma_etx) 1629 goto err_dma; 1630 } else { 1631 tx_q->dma_tx = dma_alloc_coherent(priv->device, 1632 DMA_TX_SIZE * sizeof(struct dma_desc), 1633 &tx_q->dma_tx_phy, 1634 GFP_KERNEL); 1635 if (!tx_q->dma_tx) 1636 goto err_dma; 1637 } 1638 } 1639 1640 return 0; 1641 1642 err_dma: 1643 free_dma_tx_desc_resources(priv); 1644 1645 return ret; 1646 } 1647 1648 /** 1649 * alloc_dma_desc_resources - alloc TX/RX resources. 1650 * @priv: private structure 1651 * Description: according to which descriptor can be used (extend or basic) 1652 * this function allocates the resources for TX and RX paths. In case of 1653 * reception, for example, it pre-allocated the RX socket buffer in order to 1654 * allow zero-copy mechanism. 1655 */ 1656 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1657 { 1658 /* RX Allocation */ 1659 int ret = alloc_dma_rx_desc_resources(priv); 1660 1661 if (ret) 1662 return ret; 1663 1664 ret = alloc_dma_tx_desc_resources(priv); 1665 1666 return ret; 1667 } 1668 1669 /** 1670 * free_dma_desc_resources - free dma desc resources 1671 * @priv: private structure 1672 */ 1673 static void free_dma_desc_resources(struct stmmac_priv *priv) 1674 { 1675 /* Release the DMA RX socket buffers */ 1676 free_dma_rx_desc_resources(priv); 1677 1678 /* Release the DMA TX socket buffers */ 1679 free_dma_tx_desc_resources(priv); 1680 } 1681 1682 /** 1683 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1684 * @priv: driver private structure 1685 * Description: It is used for enabling the rx queues in the MAC 1686 */ 1687 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1688 { 1689 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1690 int queue; 1691 u8 mode; 1692 1693 for (queue = 0; queue < rx_queues_count; queue++) { 1694 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1695 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1696 } 1697 } 1698 1699 /** 1700 * stmmac_start_rx_dma - start RX DMA channel 1701 * @priv: driver private structure 1702 * @chan: RX channel index 1703 * Description: 1704 * This starts a RX DMA channel 1705 */ 1706 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1707 { 1708 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1709 stmmac_start_rx(priv, priv->ioaddr, chan); 1710 } 1711 1712 /** 1713 * stmmac_start_tx_dma - start TX DMA channel 1714 * @priv: driver private structure 1715 * @chan: TX channel index 1716 * Description: 1717 * This starts a TX DMA channel 1718 */ 1719 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1720 { 1721 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1722 stmmac_start_tx(priv, priv->ioaddr, chan); 1723 } 1724 1725 /** 1726 * stmmac_stop_rx_dma - stop RX DMA channel 1727 * @priv: driver private structure 1728 * @chan: RX channel index 1729 * Description: 1730 * This stops a RX DMA channel 1731 */ 1732 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1733 { 1734 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1735 stmmac_stop_rx(priv, priv->ioaddr, chan); 1736 } 1737 1738 /** 1739 * stmmac_stop_tx_dma - stop TX DMA channel 1740 * @priv: driver private structure 1741 * @chan: TX channel index 1742 * Description: 1743 * This stops a TX DMA channel 1744 */ 1745 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1746 { 1747 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1748 stmmac_stop_tx(priv, priv->ioaddr, chan); 1749 } 1750 1751 /** 1752 * stmmac_start_all_dma - start all RX and TX DMA channels 1753 * @priv: driver private structure 1754 * Description: 1755 * This starts all the RX and TX DMA channels 1756 */ 1757 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1758 { 1759 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1760 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1761 u32 chan = 0; 1762 1763 for (chan = 0; chan < rx_channels_count; chan++) 1764 stmmac_start_rx_dma(priv, chan); 1765 1766 for (chan = 0; chan < tx_channels_count; chan++) 1767 stmmac_start_tx_dma(priv, chan); 1768 } 1769 1770 /** 1771 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1772 * @priv: driver private structure 1773 * Description: 1774 * This stops the RX and TX DMA channels 1775 */ 1776 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1777 { 1778 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1779 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1780 u32 chan = 0; 1781 1782 for (chan = 0; chan < rx_channels_count; chan++) 1783 stmmac_stop_rx_dma(priv, chan); 1784 1785 for (chan = 0; chan < tx_channels_count; chan++) 1786 stmmac_stop_tx_dma(priv, chan); 1787 } 1788 1789 /** 1790 * stmmac_dma_operation_mode - HW DMA operation mode 1791 * @priv: driver private structure 1792 * Description: it is used for configuring the DMA operation mode register in 1793 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1794 */ 1795 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1796 { 1797 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1798 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1799 int rxfifosz = priv->plat->rx_fifo_size; 1800 int txfifosz = priv->plat->tx_fifo_size; 1801 u32 txmode = 0; 1802 u32 rxmode = 0; 1803 u32 chan = 0; 1804 u8 qmode = 0; 1805 1806 if (rxfifosz == 0) 1807 rxfifosz = priv->dma_cap.rx_fifo_size; 1808 if (txfifosz == 0) 1809 txfifosz = priv->dma_cap.tx_fifo_size; 1810 1811 /* Adjust for real per queue fifo size */ 1812 rxfifosz /= rx_channels_count; 1813 txfifosz /= tx_channels_count; 1814 1815 if (priv->plat->force_thresh_dma_mode) { 1816 txmode = tc; 1817 rxmode = tc; 1818 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1819 /* 1820 * In case of GMAC, SF mode can be enabled 1821 * to perform the TX COE in HW. This depends on: 1822 * 1) TX COE if actually supported 1823 * 2) There is no bugged Jumbo frame support 1824 * that needs to not insert csum in the TDES. 1825 */ 1826 txmode = SF_DMA_MODE; 1827 rxmode = SF_DMA_MODE; 1828 priv->xstats.threshold = SF_DMA_MODE; 1829 } else { 1830 txmode = tc; 1831 rxmode = SF_DMA_MODE; 1832 } 1833 1834 /* configure all channels */ 1835 for (chan = 0; chan < rx_channels_count; chan++) { 1836 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1837 1838 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1839 rxfifosz, qmode); 1840 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1841 chan); 1842 } 1843 1844 for (chan = 0; chan < tx_channels_count; chan++) { 1845 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1846 1847 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1848 txfifosz, qmode); 1849 } 1850 } 1851 1852 /** 1853 * stmmac_tx_clean - to manage the transmission completion 1854 * @priv: driver private structure 1855 * @queue: TX queue index 1856 * Description: it reclaims the transmit resources after transmission completes. 1857 */ 1858 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1859 { 1860 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1861 unsigned int bytes_compl = 0, pkts_compl = 0; 1862 unsigned int entry, count = 0; 1863 1864 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1865 1866 priv->xstats.tx_clean++; 1867 1868 entry = tx_q->dirty_tx; 1869 while ((entry != tx_q->cur_tx) && (count < budget)) { 1870 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1871 struct dma_desc *p; 1872 int status; 1873 1874 if (priv->extend_desc) 1875 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1876 else 1877 p = tx_q->dma_tx + entry; 1878 1879 status = stmmac_tx_status(priv, &priv->dev->stats, 1880 &priv->xstats, p, priv->ioaddr); 1881 /* Check if the descriptor is owned by the DMA */ 1882 if (unlikely(status & tx_dma_own)) 1883 break; 1884 1885 count++; 1886 1887 /* Make sure descriptor fields are read after reading 1888 * the own bit. 1889 */ 1890 dma_rmb(); 1891 1892 /* Just consider the last segment and ...*/ 1893 if (likely(!(status & tx_not_ls))) { 1894 /* ... verify the status error condition */ 1895 if (unlikely(status & tx_err)) { 1896 priv->dev->stats.tx_errors++; 1897 } else { 1898 priv->dev->stats.tx_packets++; 1899 priv->xstats.tx_pkt_n++; 1900 } 1901 stmmac_get_tx_hwtstamp(priv, p, skb); 1902 } 1903 1904 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 1905 if (tx_q->tx_skbuff_dma[entry].map_as_page) 1906 dma_unmap_page(priv->device, 1907 tx_q->tx_skbuff_dma[entry].buf, 1908 tx_q->tx_skbuff_dma[entry].len, 1909 DMA_TO_DEVICE); 1910 else 1911 dma_unmap_single(priv->device, 1912 tx_q->tx_skbuff_dma[entry].buf, 1913 tx_q->tx_skbuff_dma[entry].len, 1914 DMA_TO_DEVICE); 1915 tx_q->tx_skbuff_dma[entry].buf = 0; 1916 tx_q->tx_skbuff_dma[entry].len = 0; 1917 tx_q->tx_skbuff_dma[entry].map_as_page = false; 1918 } 1919 1920 stmmac_clean_desc3(priv, tx_q, p); 1921 1922 tx_q->tx_skbuff_dma[entry].last_segment = false; 1923 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1924 1925 if (likely(skb != NULL)) { 1926 pkts_compl++; 1927 bytes_compl += skb->len; 1928 dev_consume_skb_any(skb); 1929 tx_q->tx_skbuff[entry] = NULL; 1930 } 1931 1932 stmmac_release_tx_desc(priv, p, priv->mode); 1933 1934 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1935 } 1936 tx_q->dirty_tx = entry; 1937 1938 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 1939 pkts_compl, bytes_compl); 1940 1941 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 1942 queue))) && 1943 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 1944 1945 netif_dbg(priv, tx_done, priv->dev, 1946 "%s: restart transmit\n", __func__); 1947 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 1948 } 1949 1950 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1951 stmmac_enable_eee_mode(priv); 1952 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1953 } 1954 1955 /* We still have pending packets, let's call for a new scheduling */ 1956 if (tx_q->dirty_tx != tx_q->cur_tx) 1957 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 1958 1959 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 1960 1961 return count; 1962 } 1963 1964 /** 1965 * stmmac_tx_err - to manage the tx error 1966 * @priv: driver private structure 1967 * @chan: channel index 1968 * Description: it cleans the descriptors and restarts the transmission 1969 * in case of transmission errors. 1970 */ 1971 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 1972 { 1973 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 1974 int i; 1975 1976 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 1977 1978 stmmac_stop_tx_dma(priv, chan); 1979 dma_free_tx_skbufs(priv, chan); 1980 for (i = 0; i < DMA_TX_SIZE; i++) 1981 if (priv->extend_desc) 1982 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1983 priv->mode, (i == DMA_TX_SIZE - 1)); 1984 else 1985 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1986 priv->mode, (i == DMA_TX_SIZE - 1)); 1987 tx_q->dirty_tx = 0; 1988 tx_q->cur_tx = 0; 1989 tx_q->mss = 0; 1990 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 1991 stmmac_start_tx_dma(priv, chan); 1992 1993 priv->dev->stats.tx_errors++; 1994 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 1995 } 1996 1997 /** 1998 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 1999 * @priv: driver private structure 2000 * @txmode: TX operating mode 2001 * @rxmode: RX operating mode 2002 * @chan: channel index 2003 * Description: it is used for configuring of the DMA operation mode in 2004 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2005 * mode. 2006 */ 2007 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2008 u32 rxmode, u32 chan) 2009 { 2010 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2011 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2012 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2013 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2014 int rxfifosz = priv->plat->rx_fifo_size; 2015 int txfifosz = priv->plat->tx_fifo_size; 2016 2017 if (rxfifosz == 0) 2018 rxfifosz = priv->dma_cap.rx_fifo_size; 2019 if (txfifosz == 0) 2020 txfifosz = priv->dma_cap.tx_fifo_size; 2021 2022 /* Adjust for real per queue fifo size */ 2023 rxfifosz /= rx_channels_count; 2024 txfifosz /= tx_channels_count; 2025 2026 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2027 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2028 } 2029 2030 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2031 { 2032 int ret; 2033 2034 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2035 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2036 if (ret && (ret != -EINVAL)) { 2037 stmmac_global_err(priv); 2038 return true; 2039 } 2040 2041 return false; 2042 } 2043 2044 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2045 { 2046 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2047 &priv->xstats, chan); 2048 struct stmmac_channel *ch = &priv->channel[chan]; 2049 2050 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2051 if (napi_schedule_prep(&ch->rx_napi)) { 2052 stmmac_disable_dma_irq(priv, priv->ioaddr, chan); 2053 __napi_schedule_irqoff(&ch->rx_napi); 2054 status |= handle_tx; 2055 } 2056 } 2057 2058 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) 2059 napi_schedule_irqoff(&ch->tx_napi); 2060 2061 return status; 2062 } 2063 2064 /** 2065 * stmmac_dma_interrupt - DMA ISR 2066 * @priv: driver private structure 2067 * Description: this is the DMA ISR. It is called by the main ISR. 2068 * It calls the dwmac dma routine and schedule poll method in case of some 2069 * work can be done. 2070 */ 2071 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2072 { 2073 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2074 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2075 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2076 tx_channel_count : rx_channel_count; 2077 u32 chan; 2078 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2079 2080 /* Make sure we never check beyond our status buffer. */ 2081 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2082 channels_to_check = ARRAY_SIZE(status); 2083 2084 for (chan = 0; chan < channels_to_check; chan++) 2085 status[chan] = stmmac_napi_check(priv, chan); 2086 2087 for (chan = 0; chan < tx_channel_count; chan++) { 2088 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2089 /* Try to bump up the dma threshold on this failure */ 2090 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2091 (tc <= 256)) { 2092 tc += 64; 2093 if (priv->plat->force_thresh_dma_mode) 2094 stmmac_set_dma_operation_mode(priv, 2095 tc, 2096 tc, 2097 chan); 2098 else 2099 stmmac_set_dma_operation_mode(priv, 2100 tc, 2101 SF_DMA_MODE, 2102 chan); 2103 priv->xstats.threshold = tc; 2104 } 2105 } else if (unlikely(status[chan] == tx_hard_error)) { 2106 stmmac_tx_err(priv, chan); 2107 } 2108 } 2109 } 2110 2111 /** 2112 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2113 * @priv: driver private structure 2114 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2115 */ 2116 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2117 { 2118 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2119 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2120 2121 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2122 2123 if (priv->dma_cap.rmon) { 2124 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2125 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2126 } else 2127 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2128 } 2129 2130 /** 2131 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2132 * @priv: driver private structure 2133 * Description: 2134 * new GMAC chip generations have a new register to indicate the 2135 * presence of the optional feature/functions. 2136 * This can be also used to override the value passed through the 2137 * platform and necessary for old MAC10/100 and GMAC chips. 2138 */ 2139 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2140 { 2141 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2142 } 2143 2144 /** 2145 * stmmac_check_ether_addr - check if the MAC addr is valid 2146 * @priv: driver private structure 2147 * Description: 2148 * it is to verify if the MAC address is valid, in case of failures it 2149 * generates a random MAC address 2150 */ 2151 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2152 { 2153 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2154 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2155 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2156 eth_hw_addr_random(priv->dev); 2157 dev_info(priv->device, "device MAC address %pM\n", 2158 priv->dev->dev_addr); 2159 } 2160 } 2161 2162 /** 2163 * stmmac_init_dma_engine - DMA init. 2164 * @priv: driver private structure 2165 * Description: 2166 * It inits the DMA invoking the specific MAC/GMAC callback. 2167 * Some DMA parameters can be passed from the platform; 2168 * in case of these are not passed a default is kept for the MAC or GMAC. 2169 */ 2170 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2171 { 2172 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2173 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2174 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2175 struct stmmac_rx_queue *rx_q; 2176 struct stmmac_tx_queue *tx_q; 2177 u32 chan = 0; 2178 int atds = 0; 2179 int ret = 0; 2180 2181 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2182 dev_err(priv->device, "Invalid DMA configuration\n"); 2183 return -EINVAL; 2184 } 2185 2186 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2187 atds = 1; 2188 2189 ret = stmmac_reset(priv, priv->ioaddr); 2190 if (ret) { 2191 dev_err(priv->device, "Failed to reset the dma\n"); 2192 return ret; 2193 } 2194 2195 /* DMA Configuration */ 2196 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2197 2198 if (priv->plat->axi) 2199 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2200 2201 /* DMA CSR Channel configuration */ 2202 for (chan = 0; chan < dma_csr_ch; chan++) 2203 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2204 2205 /* DMA RX Channel Configuration */ 2206 for (chan = 0; chan < rx_channels_count; chan++) { 2207 rx_q = &priv->rx_queue[chan]; 2208 2209 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2210 rx_q->dma_rx_phy, chan); 2211 2212 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2213 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2214 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2215 rx_q->rx_tail_addr, chan); 2216 } 2217 2218 /* DMA TX Channel Configuration */ 2219 for (chan = 0; chan < tx_channels_count; chan++) { 2220 tx_q = &priv->tx_queue[chan]; 2221 2222 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2223 tx_q->dma_tx_phy, chan); 2224 2225 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2226 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2227 tx_q->tx_tail_addr, chan); 2228 } 2229 2230 return ret; 2231 } 2232 2233 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2234 { 2235 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2236 2237 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2238 } 2239 2240 /** 2241 * stmmac_tx_timer - mitigation sw timer for tx. 2242 * @data: data pointer 2243 * Description: 2244 * This is the timer handler to directly invoke the stmmac_tx_clean. 2245 */ 2246 static void stmmac_tx_timer(struct timer_list *t) 2247 { 2248 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2249 struct stmmac_priv *priv = tx_q->priv_data; 2250 struct stmmac_channel *ch; 2251 2252 ch = &priv->channel[tx_q->queue_index]; 2253 2254 /* 2255 * If NAPI is already running we can miss some events. Let's rearm 2256 * the timer and try again. 2257 */ 2258 if (likely(napi_schedule_prep(&ch->tx_napi))) 2259 __napi_schedule(&ch->tx_napi); 2260 else 2261 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 2262 } 2263 2264 /** 2265 * stmmac_init_coalesce - init mitigation options. 2266 * @priv: driver private structure 2267 * Description: 2268 * This inits the coalesce parameters: i.e. timer rate, 2269 * timer handler and default threshold used for enabling the 2270 * interrupt on completion bit. 2271 */ 2272 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2273 { 2274 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2275 u32 chan; 2276 2277 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2278 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2279 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2280 2281 for (chan = 0; chan < tx_channel_count; chan++) { 2282 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2283 2284 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2285 } 2286 } 2287 2288 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2289 { 2290 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2291 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2292 u32 chan; 2293 2294 /* set TX ring length */ 2295 for (chan = 0; chan < tx_channels_count; chan++) 2296 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2297 (DMA_TX_SIZE - 1), chan); 2298 2299 /* set RX ring length */ 2300 for (chan = 0; chan < rx_channels_count; chan++) 2301 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2302 (DMA_RX_SIZE - 1), chan); 2303 } 2304 2305 /** 2306 * stmmac_set_tx_queue_weight - Set TX queue weight 2307 * @priv: driver private structure 2308 * Description: It is used for setting TX queues weight 2309 */ 2310 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2311 { 2312 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2313 u32 weight; 2314 u32 queue; 2315 2316 for (queue = 0; queue < tx_queues_count; queue++) { 2317 weight = priv->plat->tx_queues_cfg[queue].weight; 2318 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2319 } 2320 } 2321 2322 /** 2323 * stmmac_configure_cbs - Configure CBS in TX queue 2324 * @priv: driver private structure 2325 * Description: It is used for configuring CBS in AVB TX queues 2326 */ 2327 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2328 { 2329 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2330 u32 mode_to_use; 2331 u32 queue; 2332 2333 /* queue 0 is reserved for legacy traffic */ 2334 for (queue = 1; queue < tx_queues_count; queue++) { 2335 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2336 if (mode_to_use == MTL_QUEUE_DCB) 2337 continue; 2338 2339 stmmac_config_cbs(priv, priv->hw, 2340 priv->plat->tx_queues_cfg[queue].send_slope, 2341 priv->plat->tx_queues_cfg[queue].idle_slope, 2342 priv->plat->tx_queues_cfg[queue].high_credit, 2343 priv->plat->tx_queues_cfg[queue].low_credit, 2344 queue); 2345 } 2346 } 2347 2348 /** 2349 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2350 * @priv: driver private structure 2351 * Description: It is used for mapping RX queues to RX dma channels 2352 */ 2353 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2354 { 2355 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2356 u32 queue; 2357 u32 chan; 2358 2359 for (queue = 0; queue < rx_queues_count; queue++) { 2360 chan = priv->plat->rx_queues_cfg[queue].chan; 2361 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2362 } 2363 } 2364 2365 /** 2366 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2367 * @priv: driver private structure 2368 * Description: It is used for configuring the RX Queue Priority 2369 */ 2370 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2371 { 2372 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2373 u32 queue; 2374 u32 prio; 2375 2376 for (queue = 0; queue < rx_queues_count; queue++) { 2377 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2378 continue; 2379 2380 prio = priv->plat->rx_queues_cfg[queue].prio; 2381 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2382 } 2383 } 2384 2385 /** 2386 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2387 * @priv: driver private structure 2388 * Description: It is used for configuring the TX Queue Priority 2389 */ 2390 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2391 { 2392 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2393 u32 queue; 2394 u32 prio; 2395 2396 for (queue = 0; queue < tx_queues_count; queue++) { 2397 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2398 continue; 2399 2400 prio = priv->plat->tx_queues_cfg[queue].prio; 2401 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2402 } 2403 } 2404 2405 /** 2406 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2407 * @priv: driver private structure 2408 * Description: It is used for configuring the RX queue routing 2409 */ 2410 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2411 { 2412 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2413 u32 queue; 2414 u8 packet; 2415 2416 for (queue = 0; queue < rx_queues_count; queue++) { 2417 /* no specific packet type routing specified for the queue */ 2418 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2419 continue; 2420 2421 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2422 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2423 } 2424 } 2425 2426 /** 2427 * stmmac_mtl_configuration - Configure MTL 2428 * @priv: driver private structure 2429 * Description: It is used for configurring MTL 2430 */ 2431 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2432 { 2433 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2434 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2435 2436 if (tx_queues_count > 1) 2437 stmmac_set_tx_queue_weight(priv); 2438 2439 /* Configure MTL RX algorithms */ 2440 if (rx_queues_count > 1) 2441 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2442 priv->plat->rx_sched_algorithm); 2443 2444 /* Configure MTL TX algorithms */ 2445 if (tx_queues_count > 1) 2446 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2447 priv->plat->tx_sched_algorithm); 2448 2449 /* Configure CBS in AVB TX queues */ 2450 if (tx_queues_count > 1) 2451 stmmac_configure_cbs(priv); 2452 2453 /* Map RX MTL to DMA channels */ 2454 stmmac_rx_queue_dma_chan_map(priv); 2455 2456 /* Enable MAC RX Queues */ 2457 stmmac_mac_enable_rx_queues(priv); 2458 2459 /* Set RX priorities */ 2460 if (rx_queues_count > 1) 2461 stmmac_mac_config_rx_queues_prio(priv); 2462 2463 /* Set TX priorities */ 2464 if (tx_queues_count > 1) 2465 stmmac_mac_config_tx_queues_prio(priv); 2466 2467 /* Set RX routing */ 2468 if (rx_queues_count > 1) 2469 stmmac_mac_config_rx_queues_routing(priv); 2470 } 2471 2472 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2473 { 2474 if (priv->dma_cap.asp) { 2475 netdev_info(priv->dev, "Enabling Safety Features\n"); 2476 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2477 } else { 2478 netdev_info(priv->dev, "No Safety Features support found\n"); 2479 } 2480 } 2481 2482 /** 2483 * stmmac_hw_setup - setup mac in a usable state. 2484 * @dev : pointer to the device structure. 2485 * Description: 2486 * this is the main function to setup the HW in a usable state because the 2487 * dma engine is reset, the core registers are configured (e.g. AXI, 2488 * Checksum features, timers). The DMA is ready to start receiving and 2489 * transmitting. 2490 * Return value: 2491 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2492 * file on failure. 2493 */ 2494 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2495 { 2496 struct stmmac_priv *priv = netdev_priv(dev); 2497 u32 rx_cnt = priv->plat->rx_queues_to_use; 2498 u32 tx_cnt = priv->plat->tx_queues_to_use; 2499 u32 chan; 2500 int ret; 2501 2502 /* DMA initialization and SW reset */ 2503 ret = stmmac_init_dma_engine(priv); 2504 if (ret < 0) { 2505 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2506 __func__); 2507 return ret; 2508 } 2509 2510 /* Copy the MAC addr into the HW */ 2511 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2512 2513 /* PS and related bits will be programmed according to the speed */ 2514 if (priv->hw->pcs) { 2515 int speed = priv->plat->mac_port_sel_speed; 2516 2517 if ((speed == SPEED_10) || (speed == SPEED_100) || 2518 (speed == SPEED_1000)) { 2519 priv->hw->ps = speed; 2520 } else { 2521 dev_warn(priv->device, "invalid port speed\n"); 2522 priv->hw->ps = 0; 2523 } 2524 } 2525 2526 /* Initialize the MAC Core */ 2527 stmmac_core_init(priv, priv->hw, dev); 2528 2529 /* Initialize MTL*/ 2530 stmmac_mtl_configuration(priv); 2531 2532 /* Initialize Safety Features */ 2533 stmmac_safety_feat_configuration(priv); 2534 2535 ret = stmmac_rx_ipc(priv, priv->hw); 2536 if (!ret) { 2537 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2538 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2539 priv->hw->rx_csum = 0; 2540 } 2541 2542 /* Enable the MAC Rx/Tx */ 2543 stmmac_mac_set(priv, priv->ioaddr, true); 2544 2545 /* Set the HW DMA mode and the COE */ 2546 stmmac_dma_operation_mode(priv); 2547 2548 stmmac_mmc_setup(priv); 2549 2550 if (init_ptp) { 2551 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2552 if (ret < 0) 2553 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2554 2555 ret = stmmac_init_ptp(priv); 2556 if (ret == -EOPNOTSUPP) 2557 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2558 else if (ret) 2559 netdev_warn(priv->dev, "PTP init failed\n"); 2560 } 2561 2562 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2563 2564 if (priv->use_riwt) { 2565 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt); 2566 if (!ret) 2567 priv->rx_riwt = MIN_DMA_RIWT; 2568 } 2569 2570 if (priv->hw->pcs) 2571 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0); 2572 2573 /* set TX and RX rings length */ 2574 stmmac_set_rings_length(priv); 2575 2576 /* Enable TSO */ 2577 if (priv->tso) { 2578 for (chan = 0; chan < tx_cnt; chan++) 2579 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2580 } 2581 2582 /* Start the ball rolling... */ 2583 stmmac_start_all_dma(priv); 2584 2585 return 0; 2586 } 2587 2588 static void stmmac_hw_teardown(struct net_device *dev) 2589 { 2590 struct stmmac_priv *priv = netdev_priv(dev); 2591 2592 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2593 } 2594 2595 /** 2596 * stmmac_open - open entry point of the driver 2597 * @dev : pointer to the device structure. 2598 * Description: 2599 * This function is the open entry point of the driver. 2600 * Return value: 2601 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2602 * file on failure. 2603 */ 2604 static int stmmac_open(struct net_device *dev) 2605 { 2606 struct stmmac_priv *priv = netdev_priv(dev); 2607 u32 chan; 2608 int ret; 2609 2610 if (priv->hw->pcs != STMMAC_PCS_RGMII && 2611 priv->hw->pcs != STMMAC_PCS_TBI && 2612 priv->hw->pcs != STMMAC_PCS_RTBI) { 2613 ret = stmmac_init_phy(dev); 2614 if (ret) { 2615 netdev_err(priv->dev, 2616 "%s: Cannot attach to PHY (error: %d)\n", 2617 __func__, ret); 2618 return ret; 2619 } 2620 } 2621 2622 /* Extra statistics */ 2623 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2624 priv->xstats.threshold = tc; 2625 2626 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 2627 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2628 2629 ret = alloc_dma_desc_resources(priv); 2630 if (ret < 0) { 2631 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2632 __func__); 2633 goto dma_desc_error; 2634 } 2635 2636 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2637 if (ret < 0) { 2638 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2639 __func__); 2640 goto init_error; 2641 } 2642 2643 ret = stmmac_hw_setup(dev, true); 2644 if (ret < 0) { 2645 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2646 goto init_error; 2647 } 2648 2649 stmmac_init_coalesce(priv); 2650 2651 phylink_start(priv->phylink); 2652 2653 /* Request the IRQ lines */ 2654 ret = request_irq(dev->irq, stmmac_interrupt, 2655 IRQF_SHARED, dev->name, dev); 2656 if (unlikely(ret < 0)) { 2657 netdev_err(priv->dev, 2658 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2659 __func__, dev->irq, ret); 2660 goto irq_error; 2661 } 2662 2663 /* Request the Wake IRQ in case of another line is used for WoL */ 2664 if (priv->wol_irq != dev->irq) { 2665 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2666 IRQF_SHARED, dev->name, dev); 2667 if (unlikely(ret < 0)) { 2668 netdev_err(priv->dev, 2669 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2670 __func__, priv->wol_irq, ret); 2671 goto wolirq_error; 2672 } 2673 } 2674 2675 /* Request the IRQ lines */ 2676 if (priv->lpi_irq > 0) { 2677 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2678 dev->name, dev); 2679 if (unlikely(ret < 0)) { 2680 netdev_err(priv->dev, 2681 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2682 __func__, priv->lpi_irq, ret); 2683 goto lpiirq_error; 2684 } 2685 } 2686 2687 stmmac_enable_all_queues(priv); 2688 stmmac_start_all_queues(priv); 2689 2690 return 0; 2691 2692 lpiirq_error: 2693 if (priv->wol_irq != dev->irq) 2694 free_irq(priv->wol_irq, dev); 2695 wolirq_error: 2696 free_irq(dev->irq, dev); 2697 irq_error: 2698 phylink_stop(priv->phylink); 2699 2700 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2701 del_timer_sync(&priv->tx_queue[chan].txtimer); 2702 2703 stmmac_hw_teardown(dev); 2704 init_error: 2705 free_dma_desc_resources(priv); 2706 dma_desc_error: 2707 phylink_disconnect_phy(priv->phylink); 2708 return ret; 2709 } 2710 2711 /** 2712 * stmmac_release - close entry point of the driver 2713 * @dev : device pointer. 2714 * Description: 2715 * This is the stop entry point of the driver. 2716 */ 2717 static int stmmac_release(struct net_device *dev) 2718 { 2719 struct stmmac_priv *priv = netdev_priv(dev); 2720 u32 chan; 2721 2722 if (priv->eee_enabled) 2723 del_timer_sync(&priv->eee_ctrl_timer); 2724 2725 /* Stop and disconnect the PHY */ 2726 phylink_stop(priv->phylink); 2727 phylink_disconnect_phy(priv->phylink); 2728 2729 stmmac_stop_all_queues(priv); 2730 2731 stmmac_disable_all_queues(priv); 2732 2733 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2734 del_timer_sync(&priv->tx_queue[chan].txtimer); 2735 2736 /* Free the IRQ lines */ 2737 free_irq(dev->irq, dev); 2738 if (priv->wol_irq != dev->irq) 2739 free_irq(priv->wol_irq, dev); 2740 if (priv->lpi_irq > 0) 2741 free_irq(priv->lpi_irq, dev); 2742 2743 /* Stop TX/RX DMA and clear the descriptors */ 2744 stmmac_stop_all_dma(priv); 2745 2746 /* Release and free the Rx/Tx resources */ 2747 free_dma_desc_resources(priv); 2748 2749 /* Disable the MAC Rx/Tx */ 2750 stmmac_mac_set(priv, priv->ioaddr, false); 2751 2752 netif_carrier_off(dev); 2753 2754 stmmac_release_ptp(priv); 2755 2756 return 0; 2757 } 2758 2759 /** 2760 * stmmac_tso_allocator - close entry point of the driver 2761 * @priv: driver private structure 2762 * @des: buffer start address 2763 * @total_len: total length to fill in descriptors 2764 * @last_segmant: condition for the last descriptor 2765 * @queue: TX queue index 2766 * Description: 2767 * This function fills descriptor and request new descriptors according to 2768 * buffer length to fill 2769 */ 2770 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2771 int total_len, bool last_segment, u32 queue) 2772 { 2773 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2774 struct dma_desc *desc; 2775 u32 buff_size; 2776 int tmp_len; 2777 2778 tmp_len = total_len; 2779 2780 while (tmp_len > 0) { 2781 dma_addr_t curr_addr; 2782 2783 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2784 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2785 desc = tx_q->dma_tx + tx_q->cur_tx; 2786 2787 curr_addr = des + (total_len - tmp_len); 2788 if (priv->dma_cap.addr64 <= 32) 2789 desc->des0 = cpu_to_le32(curr_addr); 2790 else 2791 stmmac_set_desc_addr(priv, desc, curr_addr); 2792 2793 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2794 TSO_MAX_BUFF_SIZE : tmp_len; 2795 2796 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 2797 0, 1, 2798 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 2799 0, 0); 2800 2801 tmp_len -= TSO_MAX_BUFF_SIZE; 2802 } 2803 } 2804 2805 /** 2806 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 2807 * @skb : the socket buffer 2808 * @dev : device pointer 2809 * Description: this is the transmit function that is called on TSO frames 2810 * (support available on GMAC4 and newer chips). 2811 * Diagram below show the ring programming in case of TSO frames: 2812 * 2813 * First Descriptor 2814 * -------- 2815 * | DES0 |---> buffer1 = L2/L3/L4 header 2816 * | DES1 |---> TCP Payload (can continue on next descr...) 2817 * | DES2 |---> buffer 1 and 2 len 2818 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2819 * -------- 2820 * | 2821 * ... 2822 * | 2823 * -------- 2824 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2825 * | DES1 | --| 2826 * | DES2 | --> buffer 1 and 2 len 2827 * | DES3 | 2828 * -------- 2829 * 2830 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2831 */ 2832 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2833 { 2834 struct dma_desc *desc, *first, *mss_desc = NULL; 2835 struct stmmac_priv *priv = netdev_priv(dev); 2836 int nfrags = skb_shinfo(skb)->nr_frags; 2837 u32 queue = skb_get_queue_mapping(skb); 2838 unsigned int first_entry; 2839 struct stmmac_tx_queue *tx_q; 2840 int tmp_pay_len = 0; 2841 u32 pay_len, mss; 2842 u8 proto_hdr_len; 2843 dma_addr_t des; 2844 int i; 2845 2846 tx_q = &priv->tx_queue[queue]; 2847 2848 /* Compute header lengths */ 2849 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2850 2851 /* Desc availability based on threshold should be enough safe */ 2852 if (unlikely(stmmac_tx_avail(priv, queue) < 2853 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2854 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 2855 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 2856 queue)); 2857 /* This is a hard error, log it. */ 2858 netdev_err(priv->dev, 2859 "%s: Tx Ring full when queue awake\n", 2860 __func__); 2861 } 2862 return NETDEV_TX_BUSY; 2863 } 2864 2865 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2866 2867 mss = skb_shinfo(skb)->gso_size; 2868 2869 /* set new MSS value if needed */ 2870 if (mss != tx_q->mss) { 2871 mss_desc = tx_q->dma_tx + tx_q->cur_tx; 2872 stmmac_set_mss(priv, mss_desc, mss); 2873 tx_q->mss = mss; 2874 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2875 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2876 } 2877 2878 if (netif_msg_tx_queued(priv)) { 2879 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2880 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2881 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2882 skb->data_len); 2883 } 2884 2885 first_entry = tx_q->cur_tx; 2886 WARN_ON(tx_q->tx_skbuff[first_entry]); 2887 2888 desc = tx_q->dma_tx + first_entry; 2889 first = desc; 2890 2891 /* first descriptor: fill Headers on Buf1 */ 2892 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2893 DMA_TO_DEVICE); 2894 if (dma_mapping_error(priv->device, des)) 2895 goto dma_map_err; 2896 2897 tx_q->tx_skbuff_dma[first_entry].buf = des; 2898 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2899 2900 if (priv->dma_cap.addr64 <= 32) { 2901 first->des0 = cpu_to_le32(des); 2902 2903 /* Fill start of payload in buff2 of first descriptor */ 2904 if (pay_len) 2905 first->des1 = cpu_to_le32(des + proto_hdr_len); 2906 2907 /* If needed take extra descriptors to fill the remaining payload */ 2908 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2909 } else { 2910 stmmac_set_desc_addr(priv, first, des); 2911 tmp_pay_len = pay_len; 2912 } 2913 2914 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 2915 2916 /* Prepare fragments */ 2917 for (i = 0; i < nfrags; i++) { 2918 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 2919 2920 des = skb_frag_dma_map(priv->device, frag, 0, 2921 skb_frag_size(frag), 2922 DMA_TO_DEVICE); 2923 if (dma_mapping_error(priv->device, des)) 2924 goto dma_map_err; 2925 2926 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 2927 (i == nfrags - 1), queue); 2928 2929 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 2930 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 2931 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 2932 } 2933 2934 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 2935 2936 /* Only the last descriptor gets to point to the skb. */ 2937 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 2938 2939 /* We've used all descriptors we need for this skb, however, 2940 * advance cur_tx so that it references a fresh descriptor. 2941 * ndo_start_xmit will fill this descriptor the next time it's 2942 * called and stmmac_tx_clean may clean up to this descriptor. 2943 */ 2944 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2945 2946 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 2947 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 2948 __func__); 2949 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 2950 } 2951 2952 dev->stats.tx_bytes += skb->len; 2953 priv->xstats.tx_tso_frames++; 2954 priv->xstats.tx_tso_nfrags += nfrags; 2955 2956 /* Manage tx mitigation */ 2957 tx_q->tx_count_frames += nfrags + 1; 2958 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 2959 !(priv->synopsys_id >= DWMAC_CORE_4_00 && 2960 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2961 priv->hwts_tx_en)) { 2962 stmmac_tx_timer_arm(priv, queue); 2963 } else { 2964 tx_q->tx_count_frames = 0; 2965 stmmac_set_tx_ic(priv, desc); 2966 priv->xstats.tx_set_ic_bit++; 2967 } 2968 2969 skb_tx_timestamp(skb); 2970 2971 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 2972 priv->hwts_tx_en)) { 2973 /* declare that device is doing timestamping */ 2974 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 2975 stmmac_enable_tx_timestamp(priv, first); 2976 } 2977 2978 /* Complete the first descriptor before granting the DMA */ 2979 stmmac_prepare_tso_tx_desc(priv, first, 1, 2980 proto_hdr_len, 2981 pay_len, 2982 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 2983 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 2984 2985 /* If context desc is used to change MSS */ 2986 if (mss_desc) { 2987 /* Make sure that first descriptor has been completely 2988 * written, including its own bit. This is because MSS is 2989 * actually before first descriptor, so we need to make 2990 * sure that MSS's own bit is the last thing written. 2991 */ 2992 dma_wmb(); 2993 stmmac_set_tx_owner(priv, mss_desc); 2994 } 2995 2996 /* The own bit must be the latest setting done when prepare the 2997 * descriptor and then barrier is needed to make sure that 2998 * all is coherent before granting the DMA engine. 2999 */ 3000 wmb(); 3001 3002 if (netif_msg_pktdata(priv)) { 3003 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3004 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3005 tx_q->cur_tx, first, nfrags); 3006 3007 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0); 3008 3009 pr_info(">>> frame to be transmitted: "); 3010 print_pkt(skb->data, skb_headlen(skb)); 3011 } 3012 3013 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3014 3015 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3016 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3017 3018 return NETDEV_TX_OK; 3019 3020 dma_map_err: 3021 dev_err(priv->device, "Tx dma map failed\n"); 3022 dev_kfree_skb(skb); 3023 priv->dev->stats.tx_dropped++; 3024 return NETDEV_TX_OK; 3025 } 3026 3027 /** 3028 * stmmac_xmit - Tx entry point of the driver 3029 * @skb : the socket buffer 3030 * @dev : device pointer 3031 * Description : this is the tx entry point of the driver. 3032 * It programs the chain or the ring and supports oversized frames 3033 * and SG feature. 3034 */ 3035 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3036 { 3037 struct stmmac_priv *priv = netdev_priv(dev); 3038 unsigned int nopaged_len = skb_headlen(skb); 3039 int i, csum_insertion = 0, is_jumbo = 0; 3040 u32 queue = skb_get_queue_mapping(skb); 3041 int nfrags = skb_shinfo(skb)->nr_frags; 3042 struct dma_desc *desc, *first; 3043 struct stmmac_tx_queue *tx_q; 3044 unsigned int first_entry; 3045 unsigned int enh_desc; 3046 dma_addr_t des; 3047 int entry; 3048 3049 tx_q = &priv->tx_queue[queue]; 3050 3051 if (priv->tx_path_in_lpi_mode) 3052 stmmac_disable_eee_mode(priv); 3053 3054 /* Manage oversized TCP frames for GMAC4 device */ 3055 if (skb_is_gso(skb) && priv->tso) { 3056 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3057 return stmmac_tso_xmit(skb, dev); 3058 } 3059 3060 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3061 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3062 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3063 queue)); 3064 /* This is a hard error, log it. */ 3065 netdev_err(priv->dev, 3066 "%s: Tx Ring full when queue awake\n", 3067 __func__); 3068 } 3069 return NETDEV_TX_BUSY; 3070 } 3071 3072 entry = tx_q->cur_tx; 3073 first_entry = entry; 3074 WARN_ON(tx_q->tx_skbuff[first_entry]); 3075 3076 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3077 3078 if (likely(priv->extend_desc)) 3079 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3080 else 3081 desc = tx_q->dma_tx + entry; 3082 3083 first = desc; 3084 3085 enh_desc = priv->plat->enh_desc; 3086 /* To program the descriptors according to the size of the frame */ 3087 if (enh_desc) 3088 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3089 3090 if (unlikely(is_jumbo)) { 3091 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3092 if (unlikely(entry < 0) && (entry != -EINVAL)) 3093 goto dma_map_err; 3094 } 3095 3096 for (i = 0; i < nfrags; i++) { 3097 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3098 int len = skb_frag_size(frag); 3099 bool last_segment = (i == (nfrags - 1)); 3100 3101 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3102 WARN_ON(tx_q->tx_skbuff[entry]); 3103 3104 if (likely(priv->extend_desc)) 3105 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3106 else 3107 desc = tx_q->dma_tx + entry; 3108 3109 des = skb_frag_dma_map(priv->device, frag, 0, len, 3110 DMA_TO_DEVICE); 3111 if (dma_mapping_error(priv->device, des)) 3112 goto dma_map_err; /* should reuse desc w/o issues */ 3113 3114 tx_q->tx_skbuff_dma[entry].buf = des; 3115 3116 stmmac_set_desc_addr(priv, desc, des); 3117 3118 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3119 tx_q->tx_skbuff_dma[entry].len = len; 3120 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3121 3122 /* Prepare the descriptor and set the own bit too */ 3123 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3124 priv->mode, 1, last_segment, skb->len); 3125 } 3126 3127 /* Only the last descriptor gets to point to the skb. */ 3128 tx_q->tx_skbuff[entry] = skb; 3129 3130 /* We've used all descriptors we need for this skb, however, 3131 * advance cur_tx so that it references a fresh descriptor. 3132 * ndo_start_xmit will fill this descriptor the next time it's 3133 * called and stmmac_tx_clean may clean up to this descriptor. 3134 */ 3135 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3136 tx_q->cur_tx = entry; 3137 3138 if (netif_msg_pktdata(priv)) { 3139 void *tx_head; 3140 3141 netdev_dbg(priv->dev, 3142 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3143 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3144 entry, first, nfrags); 3145 3146 if (priv->extend_desc) 3147 tx_head = (void *)tx_q->dma_etx; 3148 else 3149 tx_head = (void *)tx_q->dma_tx; 3150 3151 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false); 3152 3153 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3154 print_pkt(skb->data, skb->len); 3155 } 3156 3157 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3158 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3159 __func__); 3160 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3161 } 3162 3163 dev->stats.tx_bytes += skb->len; 3164 3165 /* According to the coalesce parameter the IC bit for the latest 3166 * segment is reset and the timer re-started to clean the tx status. 3167 * This approach takes care about the fragments: desc is the first 3168 * element in case of no SG. 3169 */ 3170 tx_q->tx_count_frames += nfrags + 1; 3171 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 3172 !(priv->synopsys_id >= DWMAC_CORE_4_00 && 3173 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3174 priv->hwts_tx_en)) { 3175 stmmac_tx_timer_arm(priv, queue); 3176 } else { 3177 tx_q->tx_count_frames = 0; 3178 stmmac_set_tx_ic(priv, desc); 3179 priv->xstats.tx_set_ic_bit++; 3180 } 3181 3182 skb_tx_timestamp(skb); 3183 3184 /* Ready to fill the first descriptor and set the OWN bit w/o any 3185 * problems because all the descriptors are actually ready to be 3186 * passed to the DMA engine. 3187 */ 3188 if (likely(!is_jumbo)) { 3189 bool last_segment = (nfrags == 0); 3190 3191 des = dma_map_single(priv->device, skb->data, 3192 nopaged_len, DMA_TO_DEVICE); 3193 if (dma_mapping_error(priv->device, des)) 3194 goto dma_map_err; 3195 3196 tx_q->tx_skbuff_dma[first_entry].buf = des; 3197 3198 stmmac_set_desc_addr(priv, first, des); 3199 3200 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3201 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3202 3203 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3204 priv->hwts_tx_en)) { 3205 /* declare that device is doing timestamping */ 3206 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3207 stmmac_enable_tx_timestamp(priv, first); 3208 } 3209 3210 /* Prepare the first descriptor setting the OWN bit too */ 3211 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3212 csum_insertion, priv->mode, 1, last_segment, 3213 skb->len); 3214 } else { 3215 stmmac_set_tx_owner(priv, first); 3216 } 3217 3218 /* The own bit must be the latest setting done when prepare the 3219 * descriptor and then barrier is needed to make sure that 3220 * all is coherent before granting the DMA engine. 3221 */ 3222 wmb(); 3223 3224 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3225 3226 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3227 3228 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3229 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3230 3231 return NETDEV_TX_OK; 3232 3233 dma_map_err: 3234 netdev_err(priv->dev, "Tx DMA map failed\n"); 3235 dev_kfree_skb(skb); 3236 priv->dev->stats.tx_dropped++; 3237 return NETDEV_TX_OK; 3238 } 3239 3240 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3241 { 3242 struct vlan_ethhdr *veth; 3243 __be16 vlan_proto; 3244 u16 vlanid; 3245 3246 veth = (struct vlan_ethhdr *)skb->data; 3247 vlan_proto = veth->h_vlan_proto; 3248 3249 if ((vlan_proto == htons(ETH_P_8021Q) && 3250 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3251 (vlan_proto == htons(ETH_P_8021AD) && 3252 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3253 /* pop the vlan tag */ 3254 vlanid = ntohs(veth->h_vlan_TCI); 3255 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3256 skb_pull(skb, VLAN_HLEN); 3257 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3258 } 3259 } 3260 3261 3262 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q) 3263 { 3264 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH) 3265 return 0; 3266 3267 return 1; 3268 } 3269 3270 /** 3271 * stmmac_rx_refill - refill used skb preallocated buffers 3272 * @priv: driver private structure 3273 * @queue: RX queue index 3274 * Description : this is to reallocate the skb for the reception process 3275 * that is based on zero-copy. 3276 */ 3277 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3278 { 3279 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3280 int dirty = stmmac_rx_dirty(priv, queue); 3281 unsigned int entry = rx_q->dirty_rx; 3282 3283 while (dirty-- > 0) { 3284 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3285 struct dma_desc *p; 3286 bool use_rx_wd; 3287 3288 if (priv->extend_desc) 3289 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3290 else 3291 p = rx_q->dma_rx + entry; 3292 3293 if (!buf->page) { 3294 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3295 if (!buf->page) 3296 break; 3297 } 3298 3299 buf->addr = page_pool_get_dma_addr(buf->page); 3300 stmmac_set_desc_addr(priv, p, buf->addr); 3301 stmmac_refill_desc3(priv, rx_q, p); 3302 3303 rx_q->rx_count_frames++; 3304 rx_q->rx_count_frames %= priv->rx_coal_frames; 3305 use_rx_wd = priv->use_riwt && rx_q->rx_count_frames; 3306 3307 dma_wmb(); 3308 stmmac_set_rx_owner(priv, p, use_rx_wd); 3309 3310 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3311 } 3312 rx_q->dirty_rx = entry; 3313 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3314 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3315 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3316 } 3317 3318 /** 3319 * stmmac_rx - manage the receive process 3320 * @priv: driver private structure 3321 * @limit: napi bugget 3322 * @queue: RX queue index. 3323 * Description : this the function called by the napi poll method. 3324 * It gets all the frames inside the ring. 3325 */ 3326 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3327 { 3328 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3329 struct stmmac_channel *ch = &priv->channel[queue]; 3330 unsigned int next_entry = rx_q->cur_rx; 3331 int coe = priv->hw->rx_csum; 3332 unsigned int count = 0; 3333 3334 if (netif_msg_rx_status(priv)) { 3335 void *rx_head; 3336 3337 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3338 if (priv->extend_desc) 3339 rx_head = (void *)rx_q->dma_erx; 3340 else 3341 rx_head = (void *)rx_q->dma_rx; 3342 3343 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3344 } 3345 while (count < limit) { 3346 struct stmmac_rx_buffer *buf; 3347 struct dma_desc *np, *p; 3348 int entry, status; 3349 3350 entry = next_entry; 3351 buf = &rx_q->buf_pool[entry]; 3352 3353 if (priv->extend_desc) 3354 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3355 else 3356 p = rx_q->dma_rx + entry; 3357 3358 /* read the status of the incoming frame */ 3359 status = stmmac_rx_status(priv, &priv->dev->stats, 3360 &priv->xstats, p); 3361 /* check if managed by the DMA otherwise go ahead */ 3362 if (unlikely(status & dma_own)) 3363 break; 3364 3365 count++; 3366 3367 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3368 next_entry = rx_q->cur_rx; 3369 3370 if (priv->extend_desc) 3371 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3372 else 3373 np = rx_q->dma_rx + next_entry; 3374 3375 prefetch(np); 3376 3377 if (priv->extend_desc) 3378 stmmac_rx_extended_status(priv, &priv->dev->stats, 3379 &priv->xstats, rx_q->dma_erx + entry); 3380 if (unlikely(status == discard_frame)) { 3381 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3382 priv->dev->stats.rx_errors++; 3383 buf->page = NULL; 3384 } else { 3385 struct sk_buff *skb; 3386 int frame_len; 3387 unsigned int des; 3388 3389 stmmac_get_desc_addr(priv, p, &des); 3390 frame_len = stmmac_get_rx_frame_len(priv, p, coe); 3391 3392 /* If frame length is greater than skb buffer size 3393 * (preallocated during init) then the packet is 3394 * ignored 3395 */ 3396 if (frame_len > priv->dma_buf_sz) { 3397 if (net_ratelimit()) 3398 netdev_err(priv->dev, 3399 "len %d larger than size (%d)\n", 3400 frame_len, priv->dma_buf_sz); 3401 priv->dev->stats.rx_length_errors++; 3402 continue; 3403 } 3404 3405 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3406 * Type frames (LLC/LLC-SNAP) 3407 * 3408 * llc_snap is never checked in GMAC >= 4, so this ACS 3409 * feature is always disabled and packets need to be 3410 * stripped manually. 3411 */ 3412 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3413 unlikely(status != llc_snap)) 3414 frame_len -= ETH_FCS_LEN; 3415 3416 if (netif_msg_rx_status(priv)) { 3417 netdev_dbg(priv->dev, "\tdesc: %p [entry %d] buff=0x%x\n", 3418 p, entry, des); 3419 netdev_dbg(priv->dev, "frame size %d, COE: %d\n", 3420 frame_len, status); 3421 } 3422 3423 skb = netdev_alloc_skb_ip_align(priv->dev, frame_len); 3424 if (unlikely(!skb)) { 3425 priv->dev->stats.rx_dropped++; 3426 continue; 3427 } 3428 3429 dma_sync_single_for_cpu(priv->device, buf->addr, 3430 frame_len, DMA_FROM_DEVICE); 3431 skb_copy_to_linear_data(skb, page_address(buf->page), 3432 frame_len); 3433 skb_put(skb, frame_len); 3434 dma_sync_single_for_device(priv->device, buf->addr, 3435 frame_len, DMA_FROM_DEVICE); 3436 3437 if (netif_msg_pktdata(priv)) { 3438 netdev_dbg(priv->dev, "frame received (%dbytes)", 3439 frame_len); 3440 print_pkt(skb->data, frame_len); 3441 } 3442 3443 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3444 3445 stmmac_rx_vlan(priv->dev, skb); 3446 3447 skb->protocol = eth_type_trans(skb, priv->dev); 3448 3449 if (unlikely(!coe)) 3450 skb_checksum_none_assert(skb); 3451 else 3452 skb->ip_summed = CHECKSUM_UNNECESSARY; 3453 3454 napi_gro_receive(&ch->rx_napi, skb); 3455 3456 /* Data payload copied into SKB, page ready for recycle */ 3457 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3458 buf->page = NULL; 3459 3460 priv->dev->stats.rx_packets++; 3461 priv->dev->stats.rx_bytes += frame_len; 3462 } 3463 } 3464 3465 stmmac_rx_refill(priv, queue); 3466 3467 priv->xstats.rx_pkt_n += count; 3468 3469 return count; 3470 } 3471 3472 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3473 { 3474 struct stmmac_channel *ch = 3475 container_of(napi, struct stmmac_channel, rx_napi); 3476 struct stmmac_priv *priv = ch->priv_data; 3477 u32 chan = ch->index; 3478 int work_done; 3479 3480 priv->xstats.napi_poll++; 3481 3482 work_done = stmmac_rx(priv, budget, chan); 3483 if (work_done < budget && napi_complete_done(napi, work_done)) 3484 stmmac_enable_dma_irq(priv, priv->ioaddr, chan); 3485 return work_done; 3486 } 3487 3488 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3489 { 3490 struct stmmac_channel *ch = 3491 container_of(napi, struct stmmac_channel, tx_napi); 3492 struct stmmac_priv *priv = ch->priv_data; 3493 struct stmmac_tx_queue *tx_q; 3494 u32 chan = ch->index; 3495 int work_done; 3496 3497 priv->xstats.napi_poll++; 3498 3499 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3500 work_done = min(work_done, budget); 3501 3502 if (work_done < budget) 3503 napi_complete_done(napi, work_done); 3504 3505 /* Force transmission restart */ 3506 tx_q = &priv->tx_queue[chan]; 3507 if (tx_q->cur_tx != tx_q->dirty_tx) { 3508 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3509 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, 3510 chan); 3511 } 3512 3513 return work_done; 3514 } 3515 3516 /** 3517 * stmmac_tx_timeout 3518 * @dev : Pointer to net device structure 3519 * Description: this function is called when a packet transmission fails to 3520 * complete within a reasonable time. The driver will mark the error in the 3521 * netdev structure and arrange for the device to be reset to a sane state 3522 * in order to transmit a new packet. 3523 */ 3524 static void stmmac_tx_timeout(struct net_device *dev) 3525 { 3526 struct stmmac_priv *priv = netdev_priv(dev); 3527 3528 stmmac_global_err(priv); 3529 } 3530 3531 /** 3532 * stmmac_set_rx_mode - entry point for multicast addressing 3533 * @dev : pointer to the device structure 3534 * Description: 3535 * This function is a driver entry point which gets called by the kernel 3536 * whenever multicast addresses must be enabled/disabled. 3537 * Return value: 3538 * void. 3539 */ 3540 static void stmmac_set_rx_mode(struct net_device *dev) 3541 { 3542 struct stmmac_priv *priv = netdev_priv(dev); 3543 3544 stmmac_set_filter(priv, priv->hw, dev); 3545 } 3546 3547 /** 3548 * stmmac_change_mtu - entry point to change MTU size for the device. 3549 * @dev : device pointer. 3550 * @new_mtu : the new MTU size for the device. 3551 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3552 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3553 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3554 * Return value: 3555 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3556 * file on failure. 3557 */ 3558 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3559 { 3560 struct stmmac_priv *priv = netdev_priv(dev); 3561 3562 if (netif_running(dev)) { 3563 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3564 return -EBUSY; 3565 } 3566 3567 dev->mtu = new_mtu; 3568 3569 netdev_update_features(dev); 3570 3571 return 0; 3572 } 3573 3574 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3575 netdev_features_t features) 3576 { 3577 struct stmmac_priv *priv = netdev_priv(dev); 3578 3579 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 3580 features &= ~NETIF_F_RXCSUM; 3581 3582 if (!priv->plat->tx_coe) 3583 features &= ~NETIF_F_CSUM_MASK; 3584 3585 /* Some GMAC devices have a bugged Jumbo frame support that 3586 * needs to have the Tx COE disabled for oversized frames 3587 * (due to limited buffer sizes). In this case we disable 3588 * the TX csum insertion in the TDES and not use SF. 3589 */ 3590 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 3591 features &= ~NETIF_F_CSUM_MASK; 3592 3593 /* Disable tso if asked by ethtool */ 3594 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3595 if (features & NETIF_F_TSO) 3596 priv->tso = true; 3597 else 3598 priv->tso = false; 3599 } 3600 3601 return features; 3602 } 3603 3604 static int stmmac_set_features(struct net_device *netdev, 3605 netdev_features_t features) 3606 { 3607 struct stmmac_priv *priv = netdev_priv(netdev); 3608 3609 /* Keep the COE Type in case of csum is supporting */ 3610 if (features & NETIF_F_RXCSUM) 3611 priv->hw->rx_csum = priv->plat->rx_coe; 3612 else 3613 priv->hw->rx_csum = 0; 3614 /* No check needed because rx_coe has been set before and it will be 3615 * fixed in case of issue. 3616 */ 3617 stmmac_rx_ipc(priv, priv->hw); 3618 3619 return 0; 3620 } 3621 3622 /** 3623 * stmmac_interrupt - main ISR 3624 * @irq: interrupt number. 3625 * @dev_id: to pass the net device pointer. 3626 * Description: this is the main driver interrupt service routine. 3627 * It can call: 3628 * o DMA service routine (to manage incoming frame reception and transmission 3629 * status) 3630 * o Core interrupts to manage: remote wake-up, management counter, LPI 3631 * interrupts. 3632 */ 3633 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 3634 { 3635 struct net_device *dev = (struct net_device *)dev_id; 3636 struct stmmac_priv *priv = netdev_priv(dev); 3637 u32 rx_cnt = priv->plat->rx_queues_to_use; 3638 u32 tx_cnt = priv->plat->tx_queues_to_use; 3639 u32 queues_count; 3640 u32 queue; 3641 bool xmac; 3642 3643 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 3644 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 3645 3646 if (priv->irq_wake) 3647 pm_wakeup_event(priv->device, 0); 3648 3649 if (unlikely(!dev)) { 3650 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 3651 return IRQ_NONE; 3652 } 3653 3654 /* Check if adapter is up */ 3655 if (test_bit(STMMAC_DOWN, &priv->state)) 3656 return IRQ_HANDLED; 3657 /* Check if a fatal error happened */ 3658 if (stmmac_safety_feat_interrupt(priv)) 3659 return IRQ_HANDLED; 3660 3661 /* To handle GMAC own interrupts */ 3662 if ((priv->plat->has_gmac) || xmac) { 3663 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 3664 int mtl_status; 3665 3666 if (unlikely(status)) { 3667 /* For LPI we need to save the tx status */ 3668 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 3669 priv->tx_path_in_lpi_mode = true; 3670 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 3671 priv->tx_path_in_lpi_mode = false; 3672 } 3673 3674 for (queue = 0; queue < queues_count; queue++) { 3675 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3676 3677 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 3678 queue); 3679 if (mtl_status != -EINVAL) 3680 status |= mtl_status; 3681 3682 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 3683 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 3684 rx_q->rx_tail_addr, 3685 queue); 3686 } 3687 3688 /* PCS link status */ 3689 if (priv->hw->pcs) { 3690 if (priv->xstats.pcs_link) 3691 netif_carrier_on(dev); 3692 else 3693 netif_carrier_off(dev); 3694 } 3695 } 3696 3697 /* To handle DMA interrupts */ 3698 stmmac_dma_interrupt(priv); 3699 3700 return IRQ_HANDLED; 3701 } 3702 3703 #ifdef CONFIG_NET_POLL_CONTROLLER 3704 /* Polling receive - used by NETCONSOLE and other diagnostic tools 3705 * to allow network I/O with interrupts disabled. 3706 */ 3707 static void stmmac_poll_controller(struct net_device *dev) 3708 { 3709 disable_irq(dev->irq); 3710 stmmac_interrupt(dev->irq, dev); 3711 enable_irq(dev->irq); 3712 } 3713 #endif 3714 3715 /** 3716 * stmmac_ioctl - Entry point for the Ioctl 3717 * @dev: Device pointer. 3718 * @rq: An IOCTL specefic structure, that can contain a pointer to 3719 * a proprietary structure used to pass information to the driver. 3720 * @cmd: IOCTL command 3721 * Description: 3722 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 3723 */ 3724 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3725 { 3726 struct stmmac_priv *priv = netdev_priv (dev); 3727 int ret = -EOPNOTSUPP; 3728 3729 if (!netif_running(dev)) 3730 return -EINVAL; 3731 3732 switch (cmd) { 3733 case SIOCGMIIPHY: 3734 case SIOCGMIIREG: 3735 case SIOCSMIIREG: 3736 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 3737 break; 3738 case SIOCSHWTSTAMP: 3739 ret = stmmac_hwtstamp_set(dev, rq); 3740 break; 3741 case SIOCGHWTSTAMP: 3742 ret = stmmac_hwtstamp_get(dev, rq); 3743 break; 3744 default: 3745 break; 3746 } 3747 3748 return ret; 3749 } 3750 3751 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 3752 void *cb_priv) 3753 { 3754 struct stmmac_priv *priv = cb_priv; 3755 int ret = -EOPNOTSUPP; 3756 3757 stmmac_disable_all_queues(priv); 3758 3759 switch (type) { 3760 case TC_SETUP_CLSU32: 3761 if (tc_cls_can_offload_and_chain0(priv->dev, type_data)) 3762 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 3763 break; 3764 default: 3765 break; 3766 } 3767 3768 stmmac_enable_all_queues(priv); 3769 return ret; 3770 } 3771 3772 static LIST_HEAD(stmmac_block_cb_list); 3773 3774 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 3775 void *type_data) 3776 { 3777 struct stmmac_priv *priv = netdev_priv(ndev); 3778 3779 switch (type) { 3780 case TC_SETUP_BLOCK: 3781 return flow_block_cb_setup_simple(type_data, 3782 &stmmac_block_cb_list, 3783 stmmac_setup_tc_block_cb, 3784 priv, priv, true); 3785 case TC_SETUP_QDISC_CBS: 3786 return stmmac_tc_setup_cbs(priv, priv, type_data); 3787 default: 3788 return -EOPNOTSUPP; 3789 } 3790 } 3791 3792 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 3793 struct net_device *sb_dev) 3794 { 3795 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 3796 /* 3797 * There is no way to determine the number of TSO 3798 * capable Queues. Let's use always the Queue 0 3799 * because if TSO is supported then at least this 3800 * one will be capable. 3801 */ 3802 return 0; 3803 } 3804 3805 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 3806 } 3807 3808 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 3809 { 3810 struct stmmac_priv *priv = netdev_priv(ndev); 3811 int ret = 0; 3812 3813 ret = eth_mac_addr(ndev, addr); 3814 if (ret) 3815 return ret; 3816 3817 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 3818 3819 return ret; 3820 } 3821 3822 #ifdef CONFIG_DEBUG_FS 3823 static struct dentry *stmmac_fs_dir; 3824 3825 static void sysfs_display_ring(void *head, int size, int extend_desc, 3826 struct seq_file *seq) 3827 { 3828 int i; 3829 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 3830 struct dma_desc *p = (struct dma_desc *)head; 3831 3832 for (i = 0; i < size; i++) { 3833 if (extend_desc) { 3834 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 3835 i, (unsigned int)virt_to_phys(ep), 3836 le32_to_cpu(ep->basic.des0), 3837 le32_to_cpu(ep->basic.des1), 3838 le32_to_cpu(ep->basic.des2), 3839 le32_to_cpu(ep->basic.des3)); 3840 ep++; 3841 } else { 3842 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 3843 i, (unsigned int)virt_to_phys(p), 3844 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 3845 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 3846 p++; 3847 } 3848 seq_printf(seq, "\n"); 3849 } 3850 } 3851 3852 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 3853 { 3854 struct net_device *dev = seq->private; 3855 struct stmmac_priv *priv = netdev_priv(dev); 3856 u32 rx_count = priv->plat->rx_queues_to_use; 3857 u32 tx_count = priv->plat->tx_queues_to_use; 3858 u32 queue; 3859 3860 if ((dev->flags & IFF_UP) == 0) 3861 return 0; 3862 3863 for (queue = 0; queue < rx_count; queue++) { 3864 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3865 3866 seq_printf(seq, "RX Queue %d:\n", queue); 3867 3868 if (priv->extend_desc) { 3869 seq_printf(seq, "Extended descriptor ring:\n"); 3870 sysfs_display_ring((void *)rx_q->dma_erx, 3871 DMA_RX_SIZE, 1, seq); 3872 } else { 3873 seq_printf(seq, "Descriptor ring:\n"); 3874 sysfs_display_ring((void *)rx_q->dma_rx, 3875 DMA_RX_SIZE, 0, seq); 3876 } 3877 } 3878 3879 for (queue = 0; queue < tx_count; queue++) { 3880 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3881 3882 seq_printf(seq, "TX Queue %d:\n", queue); 3883 3884 if (priv->extend_desc) { 3885 seq_printf(seq, "Extended descriptor ring:\n"); 3886 sysfs_display_ring((void *)tx_q->dma_etx, 3887 DMA_TX_SIZE, 1, seq); 3888 } else { 3889 seq_printf(seq, "Descriptor ring:\n"); 3890 sysfs_display_ring((void *)tx_q->dma_tx, 3891 DMA_TX_SIZE, 0, seq); 3892 } 3893 } 3894 3895 return 0; 3896 } 3897 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 3898 3899 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 3900 { 3901 struct net_device *dev = seq->private; 3902 struct stmmac_priv *priv = netdev_priv(dev); 3903 3904 if (!priv->hw_cap_support) { 3905 seq_printf(seq, "DMA HW features not supported\n"); 3906 return 0; 3907 } 3908 3909 seq_printf(seq, "==============================\n"); 3910 seq_printf(seq, "\tDMA HW features\n"); 3911 seq_printf(seq, "==============================\n"); 3912 3913 seq_printf(seq, "\t10/100 Mbps: %s\n", 3914 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 3915 seq_printf(seq, "\t1000 Mbps: %s\n", 3916 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 3917 seq_printf(seq, "\tHalf duplex: %s\n", 3918 (priv->dma_cap.half_duplex) ? "Y" : "N"); 3919 seq_printf(seq, "\tHash Filter: %s\n", 3920 (priv->dma_cap.hash_filter) ? "Y" : "N"); 3921 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 3922 (priv->dma_cap.multi_addr) ? "Y" : "N"); 3923 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 3924 (priv->dma_cap.pcs) ? "Y" : "N"); 3925 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 3926 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 3927 seq_printf(seq, "\tPMT Remote wake up: %s\n", 3928 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 3929 seq_printf(seq, "\tPMT Magic Frame: %s\n", 3930 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 3931 seq_printf(seq, "\tRMON module: %s\n", 3932 (priv->dma_cap.rmon) ? "Y" : "N"); 3933 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 3934 (priv->dma_cap.time_stamp) ? "Y" : "N"); 3935 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 3936 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 3937 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 3938 (priv->dma_cap.eee) ? "Y" : "N"); 3939 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 3940 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 3941 (priv->dma_cap.tx_coe) ? "Y" : "N"); 3942 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 3943 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 3944 (priv->dma_cap.rx_coe) ? "Y" : "N"); 3945 } else { 3946 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 3947 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 3948 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 3949 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 3950 } 3951 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 3952 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 3953 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 3954 priv->dma_cap.number_rx_channel); 3955 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 3956 priv->dma_cap.number_tx_channel); 3957 seq_printf(seq, "\tEnhanced descriptors: %s\n", 3958 (priv->dma_cap.enh_desc) ? "Y" : "N"); 3959 3960 return 0; 3961 } 3962 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 3963 3964 static int stmmac_init_fs(struct net_device *dev) 3965 { 3966 struct stmmac_priv *priv = netdev_priv(dev); 3967 3968 /* Create per netdev entries */ 3969 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 3970 3971 if (!priv->dbgfs_dir || IS_ERR(priv->dbgfs_dir)) { 3972 netdev_err(priv->dev, "ERROR failed to create debugfs directory\n"); 3973 3974 return -ENOMEM; 3975 } 3976 3977 /* Entry to report DMA RX/TX rings */ 3978 priv->dbgfs_rings_status = 3979 debugfs_create_file("descriptors_status", 0444, 3980 priv->dbgfs_dir, dev, 3981 &stmmac_rings_status_fops); 3982 3983 if (!priv->dbgfs_rings_status || IS_ERR(priv->dbgfs_rings_status)) { 3984 netdev_err(priv->dev, "ERROR creating stmmac ring debugfs file\n"); 3985 debugfs_remove_recursive(priv->dbgfs_dir); 3986 3987 return -ENOMEM; 3988 } 3989 3990 /* Entry to report the DMA HW features */ 3991 priv->dbgfs_dma_cap = debugfs_create_file("dma_cap", 0444, 3992 priv->dbgfs_dir, 3993 dev, &stmmac_dma_cap_fops); 3994 3995 if (!priv->dbgfs_dma_cap || IS_ERR(priv->dbgfs_dma_cap)) { 3996 netdev_err(priv->dev, "ERROR creating stmmac MMC debugfs file\n"); 3997 debugfs_remove_recursive(priv->dbgfs_dir); 3998 3999 return -ENOMEM; 4000 } 4001 4002 return 0; 4003 } 4004 4005 static void stmmac_exit_fs(struct net_device *dev) 4006 { 4007 struct stmmac_priv *priv = netdev_priv(dev); 4008 4009 debugfs_remove_recursive(priv->dbgfs_dir); 4010 } 4011 #endif /* CONFIG_DEBUG_FS */ 4012 4013 static const struct net_device_ops stmmac_netdev_ops = { 4014 .ndo_open = stmmac_open, 4015 .ndo_start_xmit = stmmac_xmit, 4016 .ndo_stop = stmmac_release, 4017 .ndo_change_mtu = stmmac_change_mtu, 4018 .ndo_fix_features = stmmac_fix_features, 4019 .ndo_set_features = stmmac_set_features, 4020 .ndo_set_rx_mode = stmmac_set_rx_mode, 4021 .ndo_tx_timeout = stmmac_tx_timeout, 4022 .ndo_do_ioctl = stmmac_ioctl, 4023 .ndo_setup_tc = stmmac_setup_tc, 4024 .ndo_select_queue = stmmac_select_queue, 4025 #ifdef CONFIG_NET_POLL_CONTROLLER 4026 .ndo_poll_controller = stmmac_poll_controller, 4027 #endif 4028 .ndo_set_mac_address = stmmac_set_mac_address, 4029 }; 4030 4031 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4032 { 4033 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4034 return; 4035 if (test_bit(STMMAC_DOWN, &priv->state)) 4036 return; 4037 4038 netdev_err(priv->dev, "Reset adapter.\n"); 4039 4040 rtnl_lock(); 4041 netif_trans_update(priv->dev); 4042 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4043 usleep_range(1000, 2000); 4044 4045 set_bit(STMMAC_DOWN, &priv->state); 4046 dev_close(priv->dev); 4047 dev_open(priv->dev, NULL); 4048 clear_bit(STMMAC_DOWN, &priv->state); 4049 clear_bit(STMMAC_RESETING, &priv->state); 4050 rtnl_unlock(); 4051 } 4052 4053 static void stmmac_service_task(struct work_struct *work) 4054 { 4055 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4056 service_task); 4057 4058 stmmac_reset_subtask(priv); 4059 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4060 } 4061 4062 /** 4063 * stmmac_hw_init - Init the MAC device 4064 * @priv: driver private structure 4065 * Description: this function is to configure the MAC device according to 4066 * some platform parameters or the HW capability register. It prepares the 4067 * driver to use either ring or chain modes and to setup either enhanced or 4068 * normal descriptors. 4069 */ 4070 static int stmmac_hw_init(struct stmmac_priv *priv) 4071 { 4072 int ret; 4073 4074 /* dwmac-sun8i only work in chain mode */ 4075 if (priv->plat->has_sun8i) 4076 chain_mode = 1; 4077 priv->chain_mode = chain_mode; 4078 4079 /* Initialize HW Interface */ 4080 ret = stmmac_hwif_init(priv); 4081 if (ret) 4082 return ret; 4083 4084 /* Get the HW capability (new GMAC newer than 3.50a) */ 4085 priv->hw_cap_support = stmmac_get_hw_features(priv); 4086 if (priv->hw_cap_support) { 4087 dev_info(priv->device, "DMA HW capability register supported\n"); 4088 4089 /* We can override some gmac/dma configuration fields: e.g. 4090 * enh_desc, tx_coe (e.g. that are passed through the 4091 * platform) with the values from the HW capability 4092 * register (if supported). 4093 */ 4094 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4095 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4096 priv->hw->pmt = priv->plat->pmt; 4097 if (priv->dma_cap.hash_tb_sz) { 4098 priv->hw->multicast_filter_bins = 4099 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4100 priv->hw->mcast_bits_log2 = 4101 ilog2(priv->hw->multicast_filter_bins); 4102 } 4103 4104 /* TXCOE doesn't work in thresh DMA mode */ 4105 if (priv->plat->force_thresh_dma_mode) 4106 priv->plat->tx_coe = 0; 4107 else 4108 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4109 4110 /* In case of GMAC4 rx_coe is from HW cap register. */ 4111 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4112 4113 if (priv->dma_cap.rx_coe_type2) 4114 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4115 else if (priv->dma_cap.rx_coe_type1) 4116 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4117 4118 } else { 4119 dev_info(priv->device, "No HW DMA feature register supported\n"); 4120 } 4121 4122 if (priv->plat->rx_coe) { 4123 priv->hw->rx_csum = priv->plat->rx_coe; 4124 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4125 if (priv->synopsys_id < DWMAC_CORE_4_00) 4126 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4127 } 4128 if (priv->plat->tx_coe) 4129 dev_info(priv->device, "TX Checksum insertion supported\n"); 4130 4131 if (priv->plat->pmt) { 4132 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4133 device_set_wakeup_capable(priv->device, 1); 4134 } 4135 4136 if (priv->dma_cap.tsoen) 4137 dev_info(priv->device, "TSO supported\n"); 4138 4139 /* Run HW quirks, if any */ 4140 if (priv->hwif_quirks) { 4141 ret = priv->hwif_quirks(priv); 4142 if (ret) 4143 return ret; 4144 } 4145 4146 /* Rx Watchdog is available in the COREs newer than the 3.40. 4147 * In some case, for example on bugged HW this feature 4148 * has to be disable and this can be done by passing the 4149 * riwt_off field from the platform. 4150 */ 4151 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4152 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4153 priv->use_riwt = 1; 4154 dev_info(priv->device, 4155 "Enable RX Mitigation via HW Watchdog Timer\n"); 4156 } 4157 4158 return 0; 4159 } 4160 4161 /** 4162 * stmmac_dvr_probe 4163 * @device: device pointer 4164 * @plat_dat: platform data pointer 4165 * @res: stmmac resource pointer 4166 * Description: this is the main probe function used to 4167 * call the alloc_etherdev, allocate the priv structure. 4168 * Return: 4169 * returns 0 on success, otherwise errno. 4170 */ 4171 int stmmac_dvr_probe(struct device *device, 4172 struct plat_stmmacenet_data *plat_dat, 4173 struct stmmac_resources *res) 4174 { 4175 struct net_device *ndev = NULL; 4176 struct stmmac_priv *priv; 4177 u32 queue, maxq; 4178 int ret = 0; 4179 4180 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4181 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4182 if (!ndev) 4183 return -ENOMEM; 4184 4185 SET_NETDEV_DEV(ndev, device); 4186 4187 priv = netdev_priv(ndev); 4188 priv->device = device; 4189 priv->dev = ndev; 4190 4191 stmmac_set_ethtool_ops(ndev); 4192 priv->pause = pause; 4193 priv->plat = plat_dat; 4194 priv->ioaddr = res->addr; 4195 priv->dev->base_addr = (unsigned long)res->addr; 4196 4197 priv->dev->irq = res->irq; 4198 priv->wol_irq = res->wol_irq; 4199 priv->lpi_irq = res->lpi_irq; 4200 4201 if (!IS_ERR_OR_NULL(res->mac)) 4202 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4203 4204 dev_set_drvdata(device, priv->dev); 4205 4206 /* Verify driver arguments */ 4207 stmmac_verify_args(); 4208 4209 /* Allocate workqueue */ 4210 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4211 if (!priv->wq) { 4212 dev_err(priv->device, "failed to create workqueue\n"); 4213 return -ENOMEM; 4214 } 4215 4216 INIT_WORK(&priv->service_task, stmmac_service_task); 4217 4218 /* Override with kernel parameters if supplied XXX CRS XXX 4219 * this needs to have multiple instances 4220 */ 4221 if ((phyaddr >= 0) && (phyaddr <= 31)) 4222 priv->plat->phy_addr = phyaddr; 4223 4224 if (priv->plat->stmmac_rst) { 4225 ret = reset_control_assert(priv->plat->stmmac_rst); 4226 reset_control_deassert(priv->plat->stmmac_rst); 4227 /* Some reset controllers have only reset callback instead of 4228 * assert + deassert callbacks pair. 4229 */ 4230 if (ret == -ENOTSUPP) 4231 reset_control_reset(priv->plat->stmmac_rst); 4232 } 4233 4234 /* Init MAC and get the capabilities */ 4235 ret = stmmac_hw_init(priv); 4236 if (ret) 4237 goto error_hw_init; 4238 4239 stmmac_check_ether_addr(priv); 4240 4241 /* Configure real RX and TX queues */ 4242 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4243 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4244 4245 ndev->netdev_ops = &stmmac_netdev_ops; 4246 4247 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4248 NETIF_F_RXCSUM; 4249 4250 ret = stmmac_tc_init(priv, priv); 4251 if (!ret) { 4252 ndev->hw_features |= NETIF_F_HW_TC; 4253 } 4254 4255 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4256 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4257 priv->tso = true; 4258 dev_info(priv->device, "TSO feature enabled\n"); 4259 } 4260 4261 if (priv->dma_cap.addr64) { 4262 ret = dma_set_mask_and_coherent(device, 4263 DMA_BIT_MASK(priv->dma_cap.addr64)); 4264 if (!ret) { 4265 dev_info(priv->device, "Using %d bits DMA width\n", 4266 priv->dma_cap.addr64); 4267 } else { 4268 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4269 if (ret) { 4270 dev_err(priv->device, "Failed to set DMA Mask\n"); 4271 goto error_hw_init; 4272 } 4273 4274 priv->dma_cap.addr64 = 32; 4275 } 4276 } 4277 4278 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4279 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4280 #ifdef STMMAC_VLAN_TAG_USED 4281 /* Both mac100 and gmac support receive VLAN tag detection */ 4282 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4283 #endif 4284 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4285 4286 /* MTU range: 46 - hw-specific max */ 4287 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4288 if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4289 ndev->max_mtu = JUMBO_LEN; 4290 else if (priv->plat->has_xgmac) 4291 ndev->max_mtu = XGMAC_JUMBO_LEN; 4292 else 4293 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4294 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4295 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4296 */ 4297 if ((priv->plat->maxmtu < ndev->max_mtu) && 4298 (priv->plat->maxmtu >= ndev->min_mtu)) 4299 ndev->max_mtu = priv->plat->maxmtu; 4300 else if (priv->plat->maxmtu < ndev->min_mtu) 4301 dev_warn(priv->device, 4302 "%s: warning: maxmtu having invalid value (%d)\n", 4303 __func__, priv->plat->maxmtu); 4304 4305 if (flow_ctrl) 4306 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4307 4308 /* Setup channels NAPI */ 4309 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4310 4311 for (queue = 0; queue < maxq; queue++) { 4312 struct stmmac_channel *ch = &priv->channel[queue]; 4313 4314 ch->priv_data = priv; 4315 ch->index = queue; 4316 4317 if (queue < priv->plat->rx_queues_to_use) { 4318 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4319 NAPI_POLL_WEIGHT); 4320 } 4321 if (queue < priv->plat->tx_queues_to_use) { 4322 netif_napi_add(ndev, &ch->tx_napi, stmmac_napi_poll_tx, 4323 NAPI_POLL_WEIGHT); 4324 } 4325 } 4326 4327 mutex_init(&priv->lock); 4328 4329 /* If a specific clk_csr value is passed from the platform 4330 * this means that the CSR Clock Range selection cannot be 4331 * changed at run-time and it is fixed. Viceversa the driver'll try to 4332 * set the MDC clock dynamically according to the csr actual 4333 * clock input. 4334 */ 4335 if (priv->plat->clk_csr >= 0) 4336 priv->clk_csr = priv->plat->clk_csr; 4337 else 4338 stmmac_clk_csr_set(priv); 4339 4340 stmmac_check_pcs_mode(priv); 4341 4342 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4343 priv->hw->pcs != STMMAC_PCS_TBI && 4344 priv->hw->pcs != STMMAC_PCS_RTBI) { 4345 /* MDIO bus Registration */ 4346 ret = stmmac_mdio_register(ndev); 4347 if (ret < 0) { 4348 dev_err(priv->device, 4349 "%s: MDIO bus (id: %d) registration failed", 4350 __func__, priv->plat->bus_id); 4351 goto error_mdio_register; 4352 } 4353 } 4354 4355 ret = stmmac_phy_setup(priv); 4356 if (ret) { 4357 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4358 goto error_phy_setup; 4359 } 4360 4361 ret = register_netdev(ndev); 4362 if (ret) { 4363 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4364 __func__, ret); 4365 goto error_netdev_register; 4366 } 4367 4368 #ifdef CONFIG_DEBUG_FS 4369 ret = stmmac_init_fs(ndev); 4370 if (ret < 0) 4371 netdev_warn(priv->dev, "%s: failed debugFS registration\n", 4372 __func__); 4373 #endif 4374 4375 return ret; 4376 4377 error_netdev_register: 4378 phylink_destroy(priv->phylink); 4379 error_phy_setup: 4380 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4381 priv->hw->pcs != STMMAC_PCS_TBI && 4382 priv->hw->pcs != STMMAC_PCS_RTBI) 4383 stmmac_mdio_unregister(ndev); 4384 error_mdio_register: 4385 for (queue = 0; queue < maxq; queue++) { 4386 struct stmmac_channel *ch = &priv->channel[queue]; 4387 4388 if (queue < priv->plat->rx_queues_to_use) 4389 netif_napi_del(&ch->rx_napi); 4390 if (queue < priv->plat->tx_queues_to_use) 4391 netif_napi_del(&ch->tx_napi); 4392 } 4393 error_hw_init: 4394 destroy_workqueue(priv->wq); 4395 4396 return ret; 4397 } 4398 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 4399 4400 /** 4401 * stmmac_dvr_remove 4402 * @dev: device pointer 4403 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 4404 * changes the link status, releases the DMA descriptor rings. 4405 */ 4406 int stmmac_dvr_remove(struct device *dev) 4407 { 4408 struct net_device *ndev = dev_get_drvdata(dev); 4409 struct stmmac_priv *priv = netdev_priv(ndev); 4410 4411 netdev_info(priv->dev, "%s: removing driver", __func__); 4412 4413 #ifdef CONFIG_DEBUG_FS 4414 stmmac_exit_fs(ndev); 4415 #endif 4416 stmmac_stop_all_dma(priv); 4417 4418 stmmac_mac_set(priv, priv->ioaddr, false); 4419 netif_carrier_off(ndev); 4420 unregister_netdev(ndev); 4421 phylink_destroy(priv->phylink); 4422 if (priv->plat->stmmac_rst) 4423 reset_control_assert(priv->plat->stmmac_rst); 4424 clk_disable_unprepare(priv->plat->pclk); 4425 clk_disable_unprepare(priv->plat->stmmac_clk); 4426 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4427 priv->hw->pcs != STMMAC_PCS_TBI && 4428 priv->hw->pcs != STMMAC_PCS_RTBI) 4429 stmmac_mdio_unregister(ndev); 4430 destroy_workqueue(priv->wq); 4431 mutex_destroy(&priv->lock); 4432 4433 return 0; 4434 } 4435 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 4436 4437 /** 4438 * stmmac_suspend - suspend callback 4439 * @dev: device pointer 4440 * Description: this is the function to suspend the device and it is called 4441 * by the platform driver to stop the network queue, release the resources, 4442 * program the PMT register (for WoL), clean and release driver resources. 4443 */ 4444 int stmmac_suspend(struct device *dev) 4445 { 4446 struct net_device *ndev = dev_get_drvdata(dev); 4447 struct stmmac_priv *priv = netdev_priv(ndev); 4448 4449 if (!ndev || !netif_running(ndev)) 4450 return 0; 4451 4452 phylink_stop(priv->phylink); 4453 4454 mutex_lock(&priv->lock); 4455 4456 netif_device_detach(ndev); 4457 stmmac_stop_all_queues(priv); 4458 4459 stmmac_disable_all_queues(priv); 4460 4461 /* Stop TX/RX DMA */ 4462 stmmac_stop_all_dma(priv); 4463 4464 /* Enable Power down mode by programming the PMT regs */ 4465 if (device_may_wakeup(priv->device)) { 4466 stmmac_pmt(priv, priv->hw, priv->wolopts); 4467 priv->irq_wake = 1; 4468 } else { 4469 stmmac_mac_set(priv, priv->ioaddr, false); 4470 pinctrl_pm_select_sleep_state(priv->device); 4471 /* Disable clock in case of PWM is off */ 4472 clk_disable(priv->plat->pclk); 4473 clk_disable(priv->plat->stmmac_clk); 4474 } 4475 mutex_unlock(&priv->lock); 4476 4477 priv->speed = SPEED_UNKNOWN; 4478 return 0; 4479 } 4480 EXPORT_SYMBOL_GPL(stmmac_suspend); 4481 4482 /** 4483 * stmmac_reset_queues_param - reset queue parameters 4484 * @dev: device pointer 4485 */ 4486 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 4487 { 4488 u32 rx_cnt = priv->plat->rx_queues_to_use; 4489 u32 tx_cnt = priv->plat->tx_queues_to_use; 4490 u32 queue; 4491 4492 for (queue = 0; queue < rx_cnt; queue++) { 4493 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4494 4495 rx_q->cur_rx = 0; 4496 rx_q->dirty_rx = 0; 4497 } 4498 4499 for (queue = 0; queue < tx_cnt; queue++) { 4500 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4501 4502 tx_q->cur_tx = 0; 4503 tx_q->dirty_tx = 0; 4504 tx_q->mss = 0; 4505 } 4506 } 4507 4508 /** 4509 * stmmac_resume - resume callback 4510 * @dev: device pointer 4511 * Description: when resume this function is invoked to setup the DMA and CORE 4512 * in a usable state. 4513 */ 4514 int stmmac_resume(struct device *dev) 4515 { 4516 struct net_device *ndev = dev_get_drvdata(dev); 4517 struct stmmac_priv *priv = netdev_priv(ndev); 4518 4519 if (!netif_running(ndev)) 4520 return 0; 4521 4522 /* Power Down bit, into the PM register, is cleared 4523 * automatically as soon as a magic packet or a Wake-up frame 4524 * is received. Anyway, it's better to manually clear 4525 * this bit because it can generate problems while resuming 4526 * from another devices (e.g. serial console). 4527 */ 4528 if (device_may_wakeup(priv->device)) { 4529 mutex_lock(&priv->lock); 4530 stmmac_pmt(priv, priv->hw, 0); 4531 mutex_unlock(&priv->lock); 4532 priv->irq_wake = 0; 4533 } else { 4534 pinctrl_pm_select_default_state(priv->device); 4535 /* enable the clk previously disabled */ 4536 clk_enable(priv->plat->stmmac_clk); 4537 clk_enable(priv->plat->pclk); 4538 /* reset the phy so that it's ready */ 4539 if (priv->mii) 4540 stmmac_mdio_reset(priv->mii); 4541 } 4542 4543 netif_device_attach(ndev); 4544 4545 mutex_lock(&priv->lock); 4546 4547 stmmac_reset_queues_param(priv); 4548 4549 stmmac_clear_descriptors(priv); 4550 4551 stmmac_hw_setup(ndev, false); 4552 stmmac_init_coalesce(priv); 4553 stmmac_set_rx_mode(ndev); 4554 4555 stmmac_enable_all_queues(priv); 4556 4557 stmmac_start_all_queues(priv); 4558 4559 mutex_unlock(&priv->lock); 4560 4561 phylink_start(priv->phylink); 4562 4563 return 0; 4564 } 4565 EXPORT_SYMBOL_GPL(stmmac_resume); 4566 4567 #ifndef MODULE 4568 static int __init stmmac_cmdline_opt(char *str) 4569 { 4570 char *opt; 4571 4572 if (!str || !*str) 4573 return -EINVAL; 4574 while ((opt = strsep(&str, ",")) != NULL) { 4575 if (!strncmp(opt, "debug:", 6)) { 4576 if (kstrtoint(opt + 6, 0, &debug)) 4577 goto err; 4578 } else if (!strncmp(opt, "phyaddr:", 8)) { 4579 if (kstrtoint(opt + 8, 0, &phyaddr)) 4580 goto err; 4581 } else if (!strncmp(opt, "buf_sz:", 7)) { 4582 if (kstrtoint(opt + 7, 0, &buf_sz)) 4583 goto err; 4584 } else if (!strncmp(opt, "tc:", 3)) { 4585 if (kstrtoint(opt + 3, 0, &tc)) 4586 goto err; 4587 } else if (!strncmp(opt, "watchdog:", 9)) { 4588 if (kstrtoint(opt + 9, 0, &watchdog)) 4589 goto err; 4590 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 4591 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 4592 goto err; 4593 } else if (!strncmp(opt, "pause:", 6)) { 4594 if (kstrtoint(opt + 6, 0, &pause)) 4595 goto err; 4596 } else if (!strncmp(opt, "eee_timer:", 10)) { 4597 if (kstrtoint(opt + 10, 0, &eee_timer)) 4598 goto err; 4599 } else if (!strncmp(opt, "chain_mode:", 11)) { 4600 if (kstrtoint(opt + 11, 0, &chain_mode)) 4601 goto err; 4602 } 4603 } 4604 return 0; 4605 4606 err: 4607 pr_err("%s: ERROR broken module parameter conversion", __func__); 4608 return -EINVAL; 4609 } 4610 4611 __setup("stmmaceth=", stmmac_cmdline_opt); 4612 #endif /* MODULE */ 4613 4614 static int __init stmmac_init(void) 4615 { 4616 #ifdef CONFIG_DEBUG_FS 4617 /* Create debugfs main directory if it doesn't exist yet */ 4618 if (!stmmac_fs_dir) { 4619 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 4620 4621 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 4622 pr_err("ERROR %s, debugfs create directory failed\n", 4623 STMMAC_RESOURCE_NAME); 4624 4625 return -ENOMEM; 4626 } 4627 } 4628 #endif 4629 4630 return 0; 4631 } 4632 4633 static void __exit stmmac_exit(void) 4634 { 4635 #ifdef CONFIG_DEBUG_FS 4636 debugfs_remove_recursive(stmmac_fs_dir); 4637 #endif 4638 } 4639 4640 module_init(stmmac_init) 4641 module_exit(stmmac_exit) 4642 4643 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 4644 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 4645 MODULE_LICENSE("GPL"); 4646