1 /******************************************************************************* 2 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 3 ST Ethernet IPs are built around a Synopsys IP Core. 4 5 Copyright(C) 2007-2011 STMicroelectronics Ltd 6 7 This program is free software; you can redistribute it and/or modify it 8 under the terms and conditions of the GNU General Public License, 9 version 2, as published by the Free Software Foundation. 10 11 This program is distributed in the hope it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 more details. 15 16 You should have received a copy of the GNU General Public License along with 17 this program; if not, write to the Free Software Foundation, Inc., 18 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 19 20 The full GNU General Public License is included in this distribution in 21 the file called "COPYING". 22 23 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 24 25 Documentation available at: 26 http://www.stlinux.com 27 Support available at: 28 https://bugzilla.stlinux.com/ 29 *******************************************************************************/ 30 31 #include <linux/kernel.h> 32 #include <linux/interrupt.h> 33 #include <linux/ip.h> 34 #include <linux/tcp.h> 35 #include <linux/skbuff.h> 36 #include <linux/ethtool.h> 37 #include <linux/if_ether.h> 38 #include <linux/crc32.h> 39 #include <linux/mii.h> 40 #include <linux/if.h> 41 #include <linux/if_vlan.h> 42 #include <linux/dma-mapping.h> 43 #include <linux/slab.h> 44 #include <linux/prefetch.h> 45 #ifdef CONFIG_STMMAC_DEBUG_FS 46 #include <linux/debugfs.h> 47 #include <linux/seq_file.h> 48 #endif 49 #include "stmmac.h" 50 51 #undef STMMAC_DEBUG 52 /*#define STMMAC_DEBUG*/ 53 #ifdef STMMAC_DEBUG 54 #define DBG(nlevel, klevel, fmt, args...) \ 55 ((void)(netif_msg_##nlevel(priv) && \ 56 printk(KERN_##klevel fmt, ## args))) 57 #else 58 #define DBG(nlevel, klevel, fmt, args...) do { } while (0) 59 #endif 60 61 #undef STMMAC_RX_DEBUG 62 /*#define STMMAC_RX_DEBUG*/ 63 #ifdef STMMAC_RX_DEBUG 64 #define RX_DBG(fmt, args...) printk(fmt, ## args) 65 #else 66 #define RX_DBG(fmt, args...) do { } while (0) 67 #endif 68 69 #undef STMMAC_XMIT_DEBUG 70 /*#define STMMAC_XMIT_DEBUG*/ 71 #ifdef STMMAC_TX_DEBUG 72 #define TX_DBG(fmt, args...) printk(fmt, ## args) 73 #else 74 #define TX_DBG(fmt, args...) do { } while (0) 75 #endif 76 77 #define STMMAC_ALIGN(x) L1_CACHE_ALIGN(x) 78 #define JUMBO_LEN 9000 79 80 /* Module parameters */ 81 #define TX_TIMEO 5000 /* default 5 seconds */ 82 static int watchdog = TX_TIMEO; 83 module_param(watchdog, int, S_IRUGO | S_IWUSR); 84 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds"); 85 86 static int debug = -1; /* -1: default, 0: no output, 16: all */ 87 module_param(debug, int, S_IRUGO | S_IWUSR); 88 MODULE_PARM_DESC(debug, "Message Level (0: no output, 16: all)"); 89 90 int phyaddr = -1; 91 module_param(phyaddr, int, S_IRUGO); 92 MODULE_PARM_DESC(phyaddr, "Physical device address"); 93 94 #define DMA_TX_SIZE 256 95 static int dma_txsize = DMA_TX_SIZE; 96 module_param(dma_txsize, int, S_IRUGO | S_IWUSR); 97 MODULE_PARM_DESC(dma_txsize, "Number of descriptors in the TX list"); 98 99 #define DMA_RX_SIZE 256 100 static int dma_rxsize = DMA_RX_SIZE; 101 module_param(dma_rxsize, int, S_IRUGO | S_IWUSR); 102 MODULE_PARM_DESC(dma_rxsize, "Number of descriptors in the RX list"); 103 104 static int flow_ctrl = FLOW_OFF; 105 module_param(flow_ctrl, int, S_IRUGO | S_IWUSR); 106 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 107 108 static int pause = PAUSE_TIME; 109 module_param(pause, int, S_IRUGO | S_IWUSR); 110 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 111 112 #define TC_DEFAULT 64 113 static int tc = TC_DEFAULT; 114 module_param(tc, int, S_IRUGO | S_IWUSR); 115 MODULE_PARM_DESC(tc, "DMA threshold control value"); 116 117 /* Pay attention to tune this parameter; take care of both 118 * hardware capability and network stabitily/performance impact. 119 * Many tests showed that ~4ms latency seems to be good enough. */ 120 #ifdef CONFIG_STMMAC_TIMER 121 #define DEFAULT_PERIODIC_RATE 256 122 static int tmrate = DEFAULT_PERIODIC_RATE; 123 module_param(tmrate, int, S_IRUGO | S_IWUSR); 124 MODULE_PARM_DESC(tmrate, "External timer freq. (default: 256Hz)"); 125 #endif 126 127 #define DMA_BUFFER_SIZE BUF_SIZE_2KiB 128 static int buf_sz = DMA_BUFFER_SIZE; 129 module_param(buf_sz, int, S_IRUGO | S_IWUSR); 130 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 131 132 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 133 NETIF_MSG_LINK | NETIF_MSG_IFUP | 134 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 135 136 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 137 138 #ifdef CONFIG_STMMAC_DEBUG_FS 139 static int stmmac_init_fs(struct net_device *dev); 140 static void stmmac_exit_fs(void); 141 #endif 142 143 /** 144 * stmmac_verify_args - verify the driver parameters. 145 * Description: it verifies if some wrong parameter is passed to the driver. 146 * Note that wrong parameters are replaced with the default values. 147 */ 148 static void stmmac_verify_args(void) 149 { 150 if (unlikely(watchdog < 0)) 151 watchdog = TX_TIMEO; 152 if (unlikely(dma_rxsize < 0)) 153 dma_rxsize = DMA_RX_SIZE; 154 if (unlikely(dma_txsize < 0)) 155 dma_txsize = DMA_TX_SIZE; 156 if (unlikely((buf_sz < DMA_BUFFER_SIZE) || (buf_sz > BUF_SIZE_16KiB))) 157 buf_sz = DMA_BUFFER_SIZE; 158 if (unlikely(flow_ctrl > 1)) 159 flow_ctrl = FLOW_AUTO; 160 else if (likely(flow_ctrl < 0)) 161 flow_ctrl = FLOW_OFF; 162 if (unlikely((pause < 0) || (pause > 0xffff))) 163 pause = PAUSE_TIME; 164 } 165 166 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 167 { 168 #ifdef CONFIG_HAVE_CLK 169 u32 clk_rate; 170 171 if (IS_ERR(priv->stmmac_clk)) 172 return; 173 174 clk_rate = clk_get_rate(priv->stmmac_clk); 175 176 /* Platform provided default clk_csr would be assumed valid 177 * for all other cases except for the below mentioned ones. */ 178 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 179 if (clk_rate < CSR_F_35M) 180 priv->clk_csr = STMMAC_CSR_20_35M; 181 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 182 priv->clk_csr = STMMAC_CSR_35_60M; 183 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 184 priv->clk_csr = STMMAC_CSR_60_100M; 185 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 186 priv->clk_csr = STMMAC_CSR_100_150M; 187 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 188 priv->clk_csr = STMMAC_CSR_150_250M; 189 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 190 priv->clk_csr = STMMAC_CSR_250_300M; 191 } /* For values higher than the IEEE 802.3 specified frequency 192 * we can not estimate the proper divider as it is not known 193 * the frequency of clk_csr_i. So we do not change the default 194 * divider. */ 195 #endif 196 } 197 198 #if defined(STMMAC_XMIT_DEBUG) || defined(STMMAC_RX_DEBUG) 199 static void print_pkt(unsigned char *buf, int len) 200 { 201 int j; 202 pr_info("len = %d byte, buf addr: 0x%p", len, buf); 203 for (j = 0; j < len; j++) { 204 if ((j % 16) == 0) 205 pr_info("\n %03x:", j); 206 pr_info(" %02x", buf[j]); 207 } 208 pr_info("\n"); 209 } 210 #endif 211 212 /* minimum number of free TX descriptors required to wake up TX process */ 213 #define STMMAC_TX_THRESH(x) (x->dma_tx_size/4) 214 215 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv) 216 { 217 return priv->dirty_tx + priv->dma_tx_size - priv->cur_tx - 1; 218 } 219 220 /* On some ST platforms, some HW system configuraton registers have to be 221 * set according to the link speed negotiated. 222 */ 223 static inline void stmmac_hw_fix_mac_speed(struct stmmac_priv *priv) 224 { 225 struct phy_device *phydev = priv->phydev; 226 227 if (likely(priv->plat->fix_mac_speed)) 228 priv->plat->fix_mac_speed(priv->plat->bsp_priv, 229 phydev->speed); 230 } 231 232 /** 233 * stmmac_adjust_link 234 * @dev: net device structure 235 * Description: it adjusts the link parameters. 236 */ 237 static void stmmac_adjust_link(struct net_device *dev) 238 { 239 struct stmmac_priv *priv = netdev_priv(dev); 240 struct phy_device *phydev = priv->phydev; 241 unsigned long flags; 242 int new_state = 0; 243 unsigned int fc = priv->flow_ctrl, pause_time = priv->pause; 244 245 if (phydev == NULL) 246 return; 247 248 DBG(probe, DEBUG, "stmmac_adjust_link: called. address %d link %d\n", 249 phydev->addr, phydev->link); 250 251 spin_lock_irqsave(&priv->lock, flags); 252 if (phydev->link) { 253 u32 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 254 255 /* Now we make sure that we can be in full duplex mode. 256 * If not, we operate in half-duplex mode. */ 257 if (phydev->duplex != priv->oldduplex) { 258 new_state = 1; 259 if (!(phydev->duplex)) 260 ctrl &= ~priv->hw->link.duplex; 261 else 262 ctrl |= priv->hw->link.duplex; 263 priv->oldduplex = phydev->duplex; 264 } 265 /* Flow Control operation */ 266 if (phydev->pause) 267 priv->hw->mac->flow_ctrl(priv->ioaddr, phydev->duplex, 268 fc, pause_time); 269 270 if (phydev->speed != priv->speed) { 271 new_state = 1; 272 switch (phydev->speed) { 273 case 1000: 274 if (likely(priv->plat->has_gmac)) 275 ctrl &= ~priv->hw->link.port; 276 stmmac_hw_fix_mac_speed(priv); 277 break; 278 case 100: 279 case 10: 280 if (priv->plat->has_gmac) { 281 ctrl |= priv->hw->link.port; 282 if (phydev->speed == SPEED_100) { 283 ctrl |= priv->hw->link.speed; 284 } else { 285 ctrl &= ~(priv->hw->link.speed); 286 } 287 } else { 288 ctrl &= ~priv->hw->link.port; 289 } 290 stmmac_hw_fix_mac_speed(priv); 291 break; 292 default: 293 if (netif_msg_link(priv)) 294 pr_warning("%s: Speed (%d) is not 10" 295 " or 100!\n", dev->name, phydev->speed); 296 break; 297 } 298 299 priv->speed = phydev->speed; 300 } 301 302 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 303 304 if (!priv->oldlink) { 305 new_state = 1; 306 priv->oldlink = 1; 307 } 308 } else if (priv->oldlink) { 309 new_state = 1; 310 priv->oldlink = 0; 311 priv->speed = 0; 312 priv->oldduplex = -1; 313 } 314 315 if (new_state && netif_msg_link(priv)) 316 phy_print_status(phydev); 317 318 spin_unlock_irqrestore(&priv->lock, flags); 319 320 DBG(probe, DEBUG, "stmmac_adjust_link: exiting\n"); 321 } 322 323 /** 324 * stmmac_init_phy - PHY initialization 325 * @dev: net device structure 326 * Description: it initializes the driver's PHY state, and attaches the PHY 327 * to the mac driver. 328 * Return value: 329 * 0 on success 330 */ 331 static int stmmac_init_phy(struct net_device *dev) 332 { 333 struct stmmac_priv *priv = netdev_priv(dev); 334 struct phy_device *phydev; 335 char phy_id[MII_BUS_ID_SIZE + 3]; 336 char bus_id[MII_BUS_ID_SIZE]; 337 int interface = priv->plat->interface; 338 priv->oldlink = 0; 339 priv->speed = 0; 340 priv->oldduplex = -1; 341 342 if (priv->plat->phy_bus_name) 343 snprintf(bus_id, MII_BUS_ID_SIZE, "%s-%x", 344 priv->plat->phy_bus_name, priv->plat->bus_id); 345 else 346 snprintf(bus_id, MII_BUS_ID_SIZE, "stmmac-%x", 347 priv->plat->bus_id); 348 349 snprintf(phy_id, MII_BUS_ID_SIZE + 3, PHY_ID_FMT, bus_id, 350 priv->plat->phy_addr); 351 pr_debug("stmmac_init_phy: trying to attach to %s\n", phy_id); 352 353 phydev = phy_connect(dev, phy_id, &stmmac_adjust_link, 0, interface); 354 355 if (IS_ERR(phydev)) { 356 pr_err("%s: Could not attach to PHY\n", dev->name); 357 return PTR_ERR(phydev); 358 } 359 360 /* Stop Advertising 1000BASE Capability if interface is not GMII */ 361 if ((interface == PHY_INTERFACE_MODE_MII) || 362 (interface == PHY_INTERFACE_MODE_RMII)) 363 phydev->advertising &= ~(SUPPORTED_1000baseT_Half | 364 SUPPORTED_1000baseT_Full); 365 366 /* 367 * Broken HW is sometimes missing the pull-up resistor on the 368 * MDIO line, which results in reads to non-existent devices returning 369 * 0 rather than 0xffff. Catch this here and treat 0 as a non-existent 370 * device as well. 371 * Note: phydev->phy_id is the result of reading the UID PHY registers. 372 */ 373 if (phydev->phy_id == 0) { 374 phy_disconnect(phydev); 375 return -ENODEV; 376 } 377 pr_debug("stmmac_init_phy: %s: attached to PHY (UID 0x%x)" 378 " Link = %d\n", dev->name, phydev->phy_id, phydev->link); 379 380 priv->phydev = phydev; 381 382 return 0; 383 } 384 385 /** 386 * display_ring 387 * @p: pointer to the ring. 388 * @size: size of the ring. 389 * Description: display all the descriptors within the ring. 390 */ 391 static void display_ring(struct dma_desc *p, int size) 392 { 393 struct tmp_s { 394 u64 a; 395 unsigned int b; 396 unsigned int c; 397 }; 398 int i; 399 for (i = 0; i < size; i++) { 400 struct tmp_s *x = (struct tmp_s *)(p + i); 401 pr_info("\t%d [0x%x]: DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 402 i, (unsigned int)virt_to_phys(&p[i]), 403 (unsigned int)(x->a), (unsigned int)((x->a) >> 32), 404 x->b, x->c); 405 pr_info("\n"); 406 } 407 } 408 409 static int stmmac_set_bfsize(int mtu, int bufsize) 410 { 411 int ret = bufsize; 412 413 if (mtu >= BUF_SIZE_4KiB) 414 ret = BUF_SIZE_8KiB; 415 else if (mtu >= BUF_SIZE_2KiB) 416 ret = BUF_SIZE_4KiB; 417 else if (mtu >= DMA_BUFFER_SIZE) 418 ret = BUF_SIZE_2KiB; 419 else 420 ret = DMA_BUFFER_SIZE; 421 422 return ret; 423 } 424 425 /** 426 * init_dma_desc_rings - init the RX/TX descriptor rings 427 * @dev: net device structure 428 * Description: this function initializes the DMA RX/TX descriptors 429 * and allocates the socket buffers. It suppors the chained and ring 430 * modes. 431 */ 432 static void init_dma_desc_rings(struct net_device *dev) 433 { 434 int i; 435 struct stmmac_priv *priv = netdev_priv(dev); 436 struct sk_buff *skb; 437 unsigned int txsize = priv->dma_tx_size; 438 unsigned int rxsize = priv->dma_rx_size; 439 unsigned int bfsize; 440 int dis_ic = 0; 441 int des3_as_data_buf = 0; 442 443 /* Set the max buffer size according to the DESC mode 444 * and the MTU. Note that RING mode allows 16KiB bsize. */ 445 bfsize = priv->hw->ring->set_16kib_bfsize(dev->mtu); 446 447 if (bfsize == BUF_SIZE_16KiB) 448 des3_as_data_buf = 1; 449 else 450 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 451 452 #ifdef CONFIG_STMMAC_TIMER 453 /* Disable interrupts on completion for the reception if timer is on */ 454 if (likely(priv->tm->enable)) 455 dis_ic = 1; 456 #endif 457 458 DBG(probe, INFO, "stmmac: txsize %d, rxsize %d, bfsize %d\n", 459 txsize, rxsize, bfsize); 460 461 priv->rx_skbuff_dma = kmalloc(rxsize * sizeof(dma_addr_t), GFP_KERNEL); 462 priv->rx_skbuff = 463 kmalloc(sizeof(struct sk_buff *) * rxsize, GFP_KERNEL); 464 priv->dma_rx = 465 (struct dma_desc *)dma_alloc_coherent(priv->device, 466 rxsize * 467 sizeof(struct dma_desc), 468 &priv->dma_rx_phy, 469 GFP_KERNEL); 470 priv->tx_skbuff = kmalloc(sizeof(struct sk_buff *) * txsize, 471 GFP_KERNEL); 472 priv->dma_tx = 473 (struct dma_desc *)dma_alloc_coherent(priv->device, 474 txsize * 475 sizeof(struct dma_desc), 476 &priv->dma_tx_phy, 477 GFP_KERNEL); 478 479 if ((priv->dma_rx == NULL) || (priv->dma_tx == NULL)) { 480 pr_err("%s:ERROR allocating the DMA Tx/Rx desc\n", __func__); 481 return; 482 } 483 484 DBG(probe, INFO, "stmmac (%s) DMA desc: virt addr (Rx %p, " 485 "Tx %p)\n\tDMA phy addr (Rx 0x%08x, Tx 0x%08x)\n", 486 dev->name, priv->dma_rx, priv->dma_tx, 487 (unsigned int)priv->dma_rx_phy, (unsigned int)priv->dma_tx_phy); 488 489 /* RX INITIALIZATION */ 490 DBG(probe, INFO, "stmmac: SKB addresses:\n" 491 "skb\t\tskb data\tdma data\n"); 492 493 for (i = 0; i < rxsize; i++) { 494 struct dma_desc *p = priv->dma_rx + i; 495 496 skb = __netdev_alloc_skb(dev, bfsize + NET_IP_ALIGN, 497 GFP_KERNEL); 498 if (unlikely(skb == NULL)) { 499 pr_err("%s: Rx init fails; skb is NULL\n", __func__); 500 break; 501 } 502 skb_reserve(skb, NET_IP_ALIGN); 503 priv->rx_skbuff[i] = skb; 504 priv->rx_skbuff_dma[i] = dma_map_single(priv->device, skb->data, 505 bfsize, DMA_FROM_DEVICE); 506 507 p->des2 = priv->rx_skbuff_dma[i]; 508 509 priv->hw->ring->init_desc3(des3_as_data_buf, p); 510 511 DBG(probe, INFO, "[%p]\t[%p]\t[%x]\n", priv->rx_skbuff[i], 512 priv->rx_skbuff[i]->data, priv->rx_skbuff_dma[i]); 513 } 514 priv->cur_rx = 0; 515 priv->dirty_rx = (unsigned int)(i - rxsize); 516 priv->dma_buf_sz = bfsize; 517 buf_sz = bfsize; 518 519 /* TX INITIALIZATION */ 520 for (i = 0; i < txsize; i++) { 521 priv->tx_skbuff[i] = NULL; 522 priv->dma_tx[i].des2 = 0; 523 } 524 525 /* In case of Chained mode this sets the des3 to the next 526 * element in the chain */ 527 priv->hw->ring->init_dma_chain(priv->dma_rx, priv->dma_rx_phy, rxsize); 528 priv->hw->ring->init_dma_chain(priv->dma_tx, priv->dma_tx_phy, txsize); 529 530 priv->dirty_tx = 0; 531 priv->cur_tx = 0; 532 533 /* Clear the Rx/Tx descriptors */ 534 priv->hw->desc->init_rx_desc(priv->dma_rx, rxsize, dis_ic); 535 priv->hw->desc->init_tx_desc(priv->dma_tx, txsize); 536 537 if (netif_msg_hw(priv)) { 538 pr_info("RX descriptor ring:\n"); 539 display_ring(priv->dma_rx, rxsize); 540 pr_info("TX descriptor ring:\n"); 541 display_ring(priv->dma_tx, txsize); 542 } 543 } 544 545 static void dma_free_rx_skbufs(struct stmmac_priv *priv) 546 { 547 int i; 548 549 for (i = 0; i < priv->dma_rx_size; i++) { 550 if (priv->rx_skbuff[i]) { 551 dma_unmap_single(priv->device, priv->rx_skbuff_dma[i], 552 priv->dma_buf_sz, DMA_FROM_DEVICE); 553 dev_kfree_skb_any(priv->rx_skbuff[i]); 554 } 555 priv->rx_skbuff[i] = NULL; 556 } 557 } 558 559 static void dma_free_tx_skbufs(struct stmmac_priv *priv) 560 { 561 int i; 562 563 for (i = 0; i < priv->dma_tx_size; i++) { 564 if (priv->tx_skbuff[i] != NULL) { 565 struct dma_desc *p = priv->dma_tx + i; 566 if (p->des2) 567 dma_unmap_single(priv->device, p->des2, 568 priv->hw->desc->get_tx_len(p), 569 DMA_TO_DEVICE); 570 dev_kfree_skb_any(priv->tx_skbuff[i]); 571 priv->tx_skbuff[i] = NULL; 572 } 573 } 574 } 575 576 static void free_dma_desc_resources(struct stmmac_priv *priv) 577 { 578 /* Release the DMA TX/RX socket buffers */ 579 dma_free_rx_skbufs(priv); 580 dma_free_tx_skbufs(priv); 581 582 /* Free the region of consistent memory previously allocated for 583 * the DMA */ 584 dma_free_coherent(priv->device, 585 priv->dma_tx_size * sizeof(struct dma_desc), 586 priv->dma_tx, priv->dma_tx_phy); 587 dma_free_coherent(priv->device, 588 priv->dma_rx_size * sizeof(struct dma_desc), 589 priv->dma_rx, priv->dma_rx_phy); 590 kfree(priv->rx_skbuff_dma); 591 kfree(priv->rx_skbuff); 592 kfree(priv->tx_skbuff); 593 } 594 595 /** 596 * stmmac_dma_operation_mode - HW DMA operation mode 597 * @priv : pointer to the private device structure. 598 * Description: it sets the DMA operation mode: tx/rx DMA thresholds 599 * or Store-And-Forward capability. 600 */ 601 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 602 { 603 if (likely(priv->plat->force_sf_dma_mode || 604 ((priv->plat->tx_coe) && (!priv->no_csum_insertion)))) { 605 /* 606 * In case of GMAC, SF mode can be enabled 607 * to perform the TX COE in HW. This depends on: 608 * 1) TX COE if actually supported 609 * 2) There is no bugged Jumbo frame support 610 * that needs to not insert csum in the TDES. 611 */ 612 priv->hw->dma->dma_mode(priv->ioaddr, 613 SF_DMA_MODE, SF_DMA_MODE); 614 tc = SF_DMA_MODE; 615 } else 616 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 617 } 618 619 /** 620 * stmmac_tx: 621 * @priv: private driver structure 622 * Description: it reclaims resources after transmission completes. 623 */ 624 static void stmmac_tx(struct stmmac_priv *priv) 625 { 626 unsigned int txsize = priv->dma_tx_size; 627 628 spin_lock(&priv->tx_lock); 629 630 while (priv->dirty_tx != priv->cur_tx) { 631 int last; 632 unsigned int entry = priv->dirty_tx % txsize; 633 struct sk_buff *skb = priv->tx_skbuff[entry]; 634 struct dma_desc *p = priv->dma_tx + entry; 635 636 /* Check if the descriptor is owned by the DMA. */ 637 if (priv->hw->desc->get_tx_owner(p)) 638 break; 639 640 /* Verify tx error by looking at the last segment */ 641 last = priv->hw->desc->get_tx_ls(p); 642 if (likely(last)) { 643 int tx_error = 644 priv->hw->desc->tx_status(&priv->dev->stats, 645 &priv->xstats, p, 646 priv->ioaddr); 647 if (likely(tx_error == 0)) { 648 priv->dev->stats.tx_packets++; 649 priv->xstats.tx_pkt_n++; 650 } else 651 priv->dev->stats.tx_errors++; 652 } 653 TX_DBG("%s: curr %d, dirty %d\n", __func__, 654 priv->cur_tx, priv->dirty_tx); 655 656 if (likely(p->des2)) 657 dma_unmap_single(priv->device, p->des2, 658 priv->hw->desc->get_tx_len(p), 659 DMA_TO_DEVICE); 660 priv->hw->ring->clean_desc3(p); 661 662 if (likely(skb != NULL)) { 663 /* 664 * If there's room in the queue (limit it to size) 665 * we add this skb back into the pool, 666 * if it's the right size. 667 */ 668 if ((skb_queue_len(&priv->rx_recycle) < 669 priv->dma_rx_size) && 670 skb_recycle_check(skb, priv->dma_buf_sz)) 671 __skb_queue_head(&priv->rx_recycle, skb); 672 else 673 dev_kfree_skb(skb); 674 675 priv->tx_skbuff[entry] = NULL; 676 } 677 678 priv->hw->desc->release_tx_desc(p); 679 680 entry = (++priv->dirty_tx) % txsize; 681 } 682 if (unlikely(netif_queue_stopped(priv->dev) && 683 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv))) { 684 netif_tx_lock(priv->dev); 685 if (netif_queue_stopped(priv->dev) && 686 stmmac_tx_avail(priv) > STMMAC_TX_THRESH(priv)) { 687 TX_DBG("%s: restart transmit\n", __func__); 688 netif_wake_queue(priv->dev); 689 } 690 netif_tx_unlock(priv->dev); 691 } 692 spin_unlock(&priv->tx_lock); 693 } 694 695 static inline void stmmac_enable_irq(struct stmmac_priv *priv) 696 { 697 #ifdef CONFIG_STMMAC_TIMER 698 if (likely(priv->tm->enable)) 699 priv->tm->timer_start(tmrate); 700 else 701 #endif 702 priv->hw->dma->enable_dma_irq(priv->ioaddr); 703 } 704 705 static inline void stmmac_disable_irq(struct stmmac_priv *priv) 706 { 707 #ifdef CONFIG_STMMAC_TIMER 708 if (likely(priv->tm->enable)) 709 priv->tm->timer_stop(); 710 else 711 #endif 712 priv->hw->dma->disable_dma_irq(priv->ioaddr); 713 } 714 715 static int stmmac_has_work(struct stmmac_priv *priv) 716 { 717 unsigned int has_work = 0; 718 int rxret, tx_work = 0; 719 720 rxret = priv->hw->desc->get_rx_owner(priv->dma_rx + 721 (priv->cur_rx % priv->dma_rx_size)); 722 723 if (priv->dirty_tx != priv->cur_tx) 724 tx_work = 1; 725 726 if (likely(!rxret || tx_work)) 727 has_work = 1; 728 729 return has_work; 730 } 731 732 static inline void _stmmac_schedule(struct stmmac_priv *priv) 733 { 734 if (likely(stmmac_has_work(priv))) { 735 stmmac_disable_irq(priv); 736 napi_schedule(&priv->napi); 737 } 738 } 739 740 #ifdef CONFIG_STMMAC_TIMER 741 void stmmac_schedule(struct net_device *dev) 742 { 743 struct stmmac_priv *priv = netdev_priv(dev); 744 745 priv->xstats.sched_timer_n++; 746 747 _stmmac_schedule(priv); 748 } 749 750 static void stmmac_no_timer_started(unsigned int x) 751 {; 752 }; 753 754 static void stmmac_no_timer_stopped(void) 755 {; 756 }; 757 #endif 758 759 /** 760 * stmmac_tx_err: 761 * @priv: pointer to the private device structure 762 * Description: it cleans the descriptors and restarts the transmission 763 * in case of errors. 764 */ 765 static void stmmac_tx_err(struct stmmac_priv *priv) 766 { 767 netif_stop_queue(priv->dev); 768 769 priv->hw->dma->stop_tx(priv->ioaddr); 770 dma_free_tx_skbufs(priv); 771 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 772 priv->dirty_tx = 0; 773 priv->cur_tx = 0; 774 priv->hw->dma->start_tx(priv->ioaddr); 775 776 priv->dev->stats.tx_errors++; 777 netif_wake_queue(priv->dev); 778 } 779 780 781 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 782 { 783 int status; 784 785 status = priv->hw->dma->dma_interrupt(priv->ioaddr, &priv->xstats); 786 if (likely(status == handle_tx_rx)) 787 _stmmac_schedule(priv); 788 789 else if (unlikely(status == tx_hard_error_bump_tc)) { 790 /* Try to bump up the dma threshold on this failure */ 791 if (unlikely(tc != SF_DMA_MODE) && (tc <= 256)) { 792 tc += 64; 793 priv->hw->dma->dma_mode(priv->ioaddr, tc, SF_DMA_MODE); 794 priv->xstats.threshold = tc; 795 } 796 } else if (unlikely(status == tx_hard_error)) 797 stmmac_tx_err(priv); 798 } 799 800 static void stmmac_mmc_setup(struct stmmac_priv *priv) 801 { 802 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 803 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 804 805 /* Mask MMC irq, counters are managed in SW and registers 806 * are cleared on each READ eventually. */ 807 dwmac_mmc_intr_all_mask(priv->ioaddr); 808 809 if (priv->dma_cap.rmon) { 810 dwmac_mmc_ctrl(priv->ioaddr, mode); 811 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 812 } else 813 pr_info(" No MAC Management Counters available\n"); 814 } 815 816 static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv) 817 { 818 u32 hwid = priv->hw->synopsys_uid; 819 820 /* Only check valid Synopsys Id because old MAC chips 821 * have no HW registers where get the ID */ 822 if (likely(hwid)) { 823 u32 uid = ((hwid & 0x0000ff00) >> 8); 824 u32 synid = (hwid & 0x000000ff); 825 826 pr_info("stmmac - user ID: 0x%x, Synopsys ID: 0x%x\n", 827 uid, synid); 828 829 return synid; 830 } 831 return 0; 832 } 833 834 /** 835 * stmmac_selec_desc_mode 836 * @dev : device pointer 837 * Description: select the Enhanced/Alternate or Normal descriptors */ 838 static void stmmac_selec_desc_mode(struct stmmac_priv *priv) 839 { 840 if (priv->plat->enh_desc) { 841 pr_info(" Enhanced/Alternate descriptors\n"); 842 priv->hw->desc = &enh_desc_ops; 843 } else { 844 pr_info(" Normal descriptors\n"); 845 priv->hw->desc = &ndesc_ops; 846 } 847 } 848 849 /** 850 * stmmac_get_hw_features 851 * @priv : private device pointer 852 * Description: 853 * new GMAC chip generations have a new register to indicate the 854 * presence of the optional feature/functions. 855 * This can be also used to override the value passed through the 856 * platform and necessary for old MAC10/100 and GMAC chips. 857 */ 858 static int stmmac_get_hw_features(struct stmmac_priv *priv) 859 { 860 u32 hw_cap = 0; 861 862 if (priv->hw->dma->get_hw_feature) { 863 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 864 865 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 866 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 867 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 868 priv->dma_cap.hash_filter = (hw_cap & DMA_HW_FEAT_HASHSEL) >> 4; 869 priv->dma_cap.multi_addr = 870 (hw_cap & DMA_HW_FEAT_ADDMACADRSEL) >> 5; 871 priv->dma_cap.pcs = (hw_cap & DMA_HW_FEAT_PCSSEL) >> 6; 872 priv->dma_cap.sma_mdio = (hw_cap & DMA_HW_FEAT_SMASEL) >> 8; 873 priv->dma_cap.pmt_remote_wake_up = 874 (hw_cap & DMA_HW_FEAT_RWKSEL) >> 9; 875 priv->dma_cap.pmt_magic_frame = 876 (hw_cap & DMA_HW_FEAT_MGKSEL) >> 10; 877 /* MMC */ 878 priv->dma_cap.rmon = (hw_cap & DMA_HW_FEAT_MMCSEL) >> 11; 879 /* IEEE 1588-2002*/ 880 priv->dma_cap.time_stamp = 881 (hw_cap & DMA_HW_FEAT_TSVER1SEL) >> 12; 882 /* IEEE 1588-2008*/ 883 priv->dma_cap.atime_stamp = 884 (hw_cap & DMA_HW_FEAT_TSVER2SEL) >> 13; 885 /* 802.3az - Energy-Efficient Ethernet (EEE) */ 886 priv->dma_cap.eee = (hw_cap & DMA_HW_FEAT_EEESEL) >> 14; 887 priv->dma_cap.av = (hw_cap & DMA_HW_FEAT_AVSEL) >> 15; 888 /* TX and RX csum */ 889 priv->dma_cap.tx_coe = (hw_cap & DMA_HW_FEAT_TXCOESEL) >> 16; 890 priv->dma_cap.rx_coe_type1 = 891 (hw_cap & DMA_HW_FEAT_RXTYP1COE) >> 17; 892 priv->dma_cap.rx_coe_type2 = 893 (hw_cap & DMA_HW_FEAT_RXTYP2COE) >> 18; 894 priv->dma_cap.rxfifo_over_2048 = 895 (hw_cap & DMA_HW_FEAT_RXFIFOSIZE) >> 19; 896 /* TX and RX number of channels */ 897 priv->dma_cap.number_rx_channel = 898 (hw_cap & DMA_HW_FEAT_RXCHCNT) >> 20; 899 priv->dma_cap.number_tx_channel = 900 (hw_cap & DMA_HW_FEAT_TXCHCNT) >> 22; 901 /* Alternate (enhanced) DESC mode*/ 902 priv->dma_cap.enh_desc = 903 (hw_cap & DMA_HW_FEAT_ENHDESSEL) >> 24; 904 905 } 906 907 return hw_cap; 908 } 909 910 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 911 { 912 /* verify if the MAC address is valid, in case of failures it 913 * generates a random MAC address */ 914 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 915 priv->hw->mac->get_umac_addr((void __iomem *) 916 priv->dev->base_addr, 917 priv->dev->dev_addr, 0); 918 if (!is_valid_ether_addr(priv->dev->dev_addr)) 919 eth_hw_addr_random(priv->dev); 920 } 921 pr_warning("%s: device MAC address %pM\n", priv->dev->name, 922 priv->dev->dev_addr); 923 } 924 925 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 926 { 927 int pbl = DEFAULT_DMA_PBL, fixed_burst = 0, burst_len = 0; 928 int mixed_burst = 0; 929 930 /* Some DMA parameters can be passed from the platform; 931 * in case of these are not passed we keep a default 932 * (good for all the chips) and init the DMA! */ 933 if (priv->plat->dma_cfg) { 934 pbl = priv->plat->dma_cfg->pbl; 935 fixed_burst = priv->plat->dma_cfg->fixed_burst; 936 mixed_burst = priv->plat->dma_cfg->mixed_burst; 937 burst_len = priv->plat->dma_cfg->burst_len; 938 } 939 940 return priv->hw->dma->init(priv->ioaddr, pbl, fixed_burst, mixed_burst, 941 burst_len, priv->dma_tx_phy, 942 priv->dma_rx_phy); 943 } 944 945 /** 946 * stmmac_open - open entry point of the driver 947 * @dev : pointer to the device structure. 948 * Description: 949 * This function is the open entry point of the driver. 950 * Return value: 951 * 0 on success and an appropriate (-)ve integer as defined in errno.h 952 * file on failure. 953 */ 954 static int stmmac_open(struct net_device *dev) 955 { 956 struct stmmac_priv *priv = netdev_priv(dev); 957 int ret; 958 959 #ifdef CONFIG_STMMAC_TIMER 960 priv->tm = kzalloc(sizeof(struct stmmac_timer *), GFP_KERNEL); 961 if (unlikely(priv->tm == NULL)) 962 return -ENOMEM; 963 964 priv->tm->freq = tmrate; 965 966 /* Test if the external timer can be actually used. 967 * In case of failure continue without timer. */ 968 if (unlikely((stmmac_open_ext_timer(dev, priv->tm)) < 0)) { 969 pr_warning("stmmaceth: cannot attach the external timer.\n"); 970 priv->tm->freq = 0; 971 priv->tm->timer_start = stmmac_no_timer_started; 972 priv->tm->timer_stop = stmmac_no_timer_stopped; 973 } else 974 priv->tm->enable = 1; 975 #endif 976 stmmac_clk_enable(priv); 977 978 stmmac_check_ether_addr(priv); 979 980 ret = stmmac_init_phy(dev); 981 if (unlikely(ret)) { 982 pr_err("%s: Cannot attach to PHY (error: %d)\n", __func__, ret); 983 goto open_error; 984 } 985 986 /* Create and initialize the TX/RX descriptors chains. */ 987 priv->dma_tx_size = STMMAC_ALIGN(dma_txsize); 988 priv->dma_rx_size = STMMAC_ALIGN(dma_rxsize); 989 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 990 init_dma_desc_rings(dev); 991 992 /* DMA initialization and SW reset */ 993 ret = stmmac_init_dma_engine(priv); 994 if (ret < 0) { 995 pr_err("%s: DMA initialization failed\n", __func__); 996 goto open_error; 997 } 998 999 /* Copy the MAC addr into the HW */ 1000 priv->hw->mac->set_umac_addr(priv->ioaddr, dev->dev_addr, 0); 1001 1002 /* If required, perform hw setup of the bus. */ 1003 if (priv->plat->bus_setup) 1004 priv->plat->bus_setup(priv->ioaddr); 1005 1006 /* Initialize the MAC Core */ 1007 priv->hw->mac->core_init(priv->ioaddr); 1008 1009 /* Request the IRQ lines */ 1010 ret = request_irq(dev->irq, stmmac_interrupt, 1011 IRQF_SHARED, dev->name, dev); 1012 if (unlikely(ret < 0)) { 1013 pr_err("%s: ERROR: allocating the IRQ %d (error: %d)\n", 1014 __func__, dev->irq, ret); 1015 goto open_error; 1016 } 1017 1018 /* Request the Wake IRQ in case of another line is used for WoL */ 1019 if (priv->wol_irq != dev->irq) { 1020 ret = request_irq(priv->wol_irq, stmmac_interrupt, 1021 IRQF_SHARED, dev->name, dev); 1022 if (unlikely(ret < 0)) { 1023 pr_err("%s: ERROR: allocating the ext WoL IRQ %d " 1024 "(error: %d)\n", __func__, priv->wol_irq, ret); 1025 goto open_error_wolirq; 1026 } 1027 } 1028 1029 /* Enable the MAC Rx/Tx */ 1030 stmmac_set_mac(priv->ioaddr, true); 1031 1032 /* Set the HW DMA mode and the COE */ 1033 stmmac_dma_operation_mode(priv); 1034 1035 /* Extra statistics */ 1036 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 1037 priv->xstats.threshold = tc; 1038 1039 stmmac_mmc_setup(priv); 1040 1041 #ifdef CONFIG_STMMAC_DEBUG_FS 1042 ret = stmmac_init_fs(dev); 1043 if (ret < 0) 1044 pr_warning("%s: failed debugFS registration\n", __func__); 1045 #endif 1046 /* Start the ball rolling... */ 1047 DBG(probe, DEBUG, "%s: DMA RX/TX processes started...\n", dev->name); 1048 priv->hw->dma->start_tx(priv->ioaddr); 1049 priv->hw->dma->start_rx(priv->ioaddr); 1050 1051 #ifdef CONFIG_STMMAC_TIMER 1052 priv->tm->timer_start(tmrate); 1053 #endif 1054 1055 /* Dump DMA/MAC registers */ 1056 if (netif_msg_hw(priv)) { 1057 priv->hw->mac->dump_regs(priv->ioaddr); 1058 priv->hw->dma->dump_regs(priv->ioaddr); 1059 } 1060 1061 if (priv->phydev) 1062 phy_start(priv->phydev); 1063 1064 napi_enable(&priv->napi); 1065 skb_queue_head_init(&priv->rx_recycle); 1066 netif_start_queue(dev); 1067 1068 return 0; 1069 1070 open_error_wolirq: 1071 free_irq(dev->irq, dev); 1072 1073 open_error: 1074 #ifdef CONFIG_STMMAC_TIMER 1075 kfree(priv->tm); 1076 #endif 1077 if (priv->phydev) 1078 phy_disconnect(priv->phydev); 1079 1080 stmmac_clk_disable(priv); 1081 1082 return ret; 1083 } 1084 1085 /** 1086 * stmmac_release - close entry point of the driver 1087 * @dev : device pointer. 1088 * Description: 1089 * This is the stop entry point of the driver. 1090 */ 1091 static int stmmac_release(struct net_device *dev) 1092 { 1093 struct stmmac_priv *priv = netdev_priv(dev); 1094 1095 /* Stop and disconnect the PHY */ 1096 if (priv->phydev) { 1097 phy_stop(priv->phydev); 1098 phy_disconnect(priv->phydev); 1099 priv->phydev = NULL; 1100 } 1101 1102 netif_stop_queue(dev); 1103 1104 #ifdef CONFIG_STMMAC_TIMER 1105 /* Stop and release the timer */ 1106 stmmac_close_ext_timer(); 1107 if (priv->tm != NULL) 1108 kfree(priv->tm); 1109 #endif 1110 napi_disable(&priv->napi); 1111 skb_queue_purge(&priv->rx_recycle); 1112 1113 /* Free the IRQ lines */ 1114 free_irq(dev->irq, dev); 1115 if (priv->wol_irq != dev->irq) 1116 free_irq(priv->wol_irq, dev); 1117 1118 /* Stop TX/RX DMA and clear the descriptors */ 1119 priv->hw->dma->stop_tx(priv->ioaddr); 1120 priv->hw->dma->stop_rx(priv->ioaddr); 1121 1122 /* Release and free the Rx/Tx resources */ 1123 free_dma_desc_resources(priv); 1124 1125 /* Disable the MAC Rx/Tx */ 1126 stmmac_set_mac(priv->ioaddr, false); 1127 1128 netif_carrier_off(dev); 1129 1130 #ifdef CONFIG_STMMAC_DEBUG_FS 1131 stmmac_exit_fs(); 1132 #endif 1133 stmmac_clk_disable(priv); 1134 1135 return 0; 1136 } 1137 1138 /** 1139 * stmmac_xmit: 1140 * @skb : the socket buffer 1141 * @dev : device pointer 1142 * Description : Tx entry point of the driver. 1143 */ 1144 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 1145 { 1146 struct stmmac_priv *priv = netdev_priv(dev); 1147 unsigned int txsize = priv->dma_tx_size; 1148 unsigned int entry; 1149 int i, csum_insertion = 0; 1150 int nfrags = skb_shinfo(skb)->nr_frags; 1151 struct dma_desc *desc, *first; 1152 unsigned int nopaged_len = skb_headlen(skb); 1153 1154 if (unlikely(stmmac_tx_avail(priv) < nfrags + 1)) { 1155 if (!netif_queue_stopped(dev)) { 1156 netif_stop_queue(dev); 1157 /* This is a hard error, log it. */ 1158 pr_err("%s: BUG! Tx Ring full when queue awake\n", 1159 __func__); 1160 } 1161 return NETDEV_TX_BUSY; 1162 } 1163 1164 spin_lock(&priv->tx_lock); 1165 1166 entry = priv->cur_tx % txsize; 1167 1168 #ifdef STMMAC_XMIT_DEBUG 1169 if ((skb->len > ETH_FRAME_LEN) || nfrags) 1170 pr_info("stmmac xmit:\n" 1171 "\tskb addr %p - len: %d - nopaged_len: %d\n" 1172 "\tn_frags: %d - ip_summed: %d - %s gso\n", 1173 skb, skb->len, nopaged_len, nfrags, skb->ip_summed, 1174 !skb_is_gso(skb) ? "isn't" : "is"); 1175 #endif 1176 1177 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 1178 1179 desc = priv->dma_tx + entry; 1180 first = desc; 1181 1182 #ifdef STMMAC_XMIT_DEBUG 1183 if ((nfrags > 0) || (skb->len > ETH_FRAME_LEN)) 1184 pr_debug("stmmac xmit: skb len: %d, nopaged_len: %d,\n" 1185 "\t\tn_frags: %d, ip_summed: %d\n", 1186 skb->len, nopaged_len, nfrags, skb->ip_summed); 1187 #endif 1188 priv->tx_skbuff[entry] = skb; 1189 1190 if (priv->hw->ring->is_jumbo_frm(skb->len, priv->plat->enh_desc)) { 1191 entry = priv->hw->ring->jumbo_frm(priv, skb, csum_insertion); 1192 desc = priv->dma_tx + entry; 1193 } else { 1194 desc->des2 = dma_map_single(priv->device, skb->data, 1195 nopaged_len, DMA_TO_DEVICE); 1196 priv->hw->desc->prepare_tx_desc(desc, 1, nopaged_len, 1197 csum_insertion); 1198 } 1199 1200 for (i = 0; i < nfrags; i++) { 1201 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 1202 int len = skb_frag_size(frag); 1203 1204 entry = (++priv->cur_tx) % txsize; 1205 desc = priv->dma_tx + entry; 1206 1207 TX_DBG("\t[entry %d] segment len: %d\n", entry, len); 1208 desc->des2 = skb_frag_dma_map(priv->device, frag, 0, len, 1209 DMA_TO_DEVICE); 1210 priv->tx_skbuff[entry] = NULL; 1211 priv->hw->desc->prepare_tx_desc(desc, 0, len, csum_insertion); 1212 wmb(); 1213 priv->hw->desc->set_tx_owner(desc); 1214 } 1215 1216 /* Interrupt on completition only for the latest segment */ 1217 priv->hw->desc->close_tx_desc(desc); 1218 1219 #ifdef CONFIG_STMMAC_TIMER 1220 /* Clean IC while using timer */ 1221 if (likely(priv->tm->enable)) 1222 priv->hw->desc->clear_tx_ic(desc); 1223 #endif 1224 1225 wmb(); 1226 1227 /* To avoid raise condition */ 1228 priv->hw->desc->set_tx_owner(first); 1229 1230 priv->cur_tx++; 1231 1232 #ifdef STMMAC_XMIT_DEBUG 1233 if (netif_msg_pktdata(priv)) { 1234 pr_info("stmmac xmit: current=%d, dirty=%d, entry=%d, " 1235 "first=%p, nfrags=%d\n", 1236 (priv->cur_tx % txsize), (priv->dirty_tx % txsize), 1237 entry, first, nfrags); 1238 display_ring(priv->dma_tx, txsize); 1239 pr_info(">>> frame to be transmitted: "); 1240 print_pkt(skb->data, skb->len); 1241 } 1242 #endif 1243 if (unlikely(stmmac_tx_avail(priv) <= (MAX_SKB_FRAGS + 1))) { 1244 TX_DBG("%s: stop transmitted packets\n", __func__); 1245 netif_stop_queue(dev); 1246 } 1247 1248 dev->stats.tx_bytes += skb->len; 1249 1250 skb_tx_timestamp(skb); 1251 1252 priv->hw->dma->enable_dma_transmission(priv->ioaddr); 1253 1254 spin_unlock(&priv->tx_lock); 1255 1256 return NETDEV_TX_OK; 1257 } 1258 1259 static inline void stmmac_rx_refill(struct stmmac_priv *priv) 1260 { 1261 unsigned int rxsize = priv->dma_rx_size; 1262 int bfsize = priv->dma_buf_sz; 1263 struct dma_desc *p = priv->dma_rx; 1264 1265 for (; priv->cur_rx - priv->dirty_rx > 0; priv->dirty_rx++) { 1266 unsigned int entry = priv->dirty_rx % rxsize; 1267 if (likely(priv->rx_skbuff[entry] == NULL)) { 1268 struct sk_buff *skb; 1269 1270 skb = __skb_dequeue(&priv->rx_recycle); 1271 if (skb == NULL) 1272 skb = netdev_alloc_skb_ip_align(priv->dev, 1273 bfsize); 1274 1275 if (unlikely(skb == NULL)) 1276 break; 1277 1278 priv->rx_skbuff[entry] = skb; 1279 priv->rx_skbuff_dma[entry] = 1280 dma_map_single(priv->device, skb->data, bfsize, 1281 DMA_FROM_DEVICE); 1282 1283 (p + entry)->des2 = priv->rx_skbuff_dma[entry]; 1284 1285 if (unlikely(priv->plat->has_gmac)) 1286 priv->hw->ring->refill_desc3(bfsize, p + entry); 1287 1288 RX_DBG(KERN_INFO "\trefill entry #%d\n", entry); 1289 } 1290 wmb(); 1291 priv->hw->desc->set_rx_owner(p + entry); 1292 } 1293 } 1294 1295 static int stmmac_rx(struct stmmac_priv *priv, int limit) 1296 { 1297 unsigned int rxsize = priv->dma_rx_size; 1298 unsigned int entry = priv->cur_rx % rxsize; 1299 unsigned int next_entry; 1300 unsigned int count = 0; 1301 struct dma_desc *p = priv->dma_rx + entry; 1302 struct dma_desc *p_next; 1303 1304 #ifdef STMMAC_RX_DEBUG 1305 if (netif_msg_hw(priv)) { 1306 pr_debug(">>> stmmac_rx: descriptor ring:\n"); 1307 display_ring(priv->dma_rx, rxsize); 1308 } 1309 #endif 1310 count = 0; 1311 while (!priv->hw->desc->get_rx_owner(p)) { 1312 int status; 1313 1314 if (count >= limit) 1315 break; 1316 1317 count++; 1318 1319 next_entry = (++priv->cur_rx) % rxsize; 1320 p_next = priv->dma_rx + next_entry; 1321 prefetch(p_next); 1322 1323 /* read the status of the incoming frame */ 1324 status = (priv->hw->desc->rx_status(&priv->dev->stats, 1325 &priv->xstats, p)); 1326 if (unlikely(status == discard_frame)) 1327 priv->dev->stats.rx_errors++; 1328 else { 1329 struct sk_buff *skb; 1330 int frame_len; 1331 1332 frame_len = priv->hw->desc->get_rx_frame_len(p, 1333 priv->plat->rx_coe); 1334 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 1335 * Type frames (LLC/LLC-SNAP) */ 1336 if (unlikely(status != llc_snap)) 1337 frame_len -= ETH_FCS_LEN; 1338 #ifdef STMMAC_RX_DEBUG 1339 if (frame_len > ETH_FRAME_LEN) 1340 pr_debug("\tRX frame size %d, COE status: %d\n", 1341 frame_len, status); 1342 1343 if (netif_msg_hw(priv)) 1344 pr_debug("\tdesc: %p [entry %d] buff=0x%x\n", 1345 p, entry, p->des2); 1346 #endif 1347 skb = priv->rx_skbuff[entry]; 1348 if (unlikely(!skb)) { 1349 pr_err("%s: Inconsistent Rx descriptor chain\n", 1350 priv->dev->name); 1351 priv->dev->stats.rx_dropped++; 1352 break; 1353 } 1354 prefetch(skb->data - NET_IP_ALIGN); 1355 priv->rx_skbuff[entry] = NULL; 1356 1357 skb_put(skb, frame_len); 1358 dma_unmap_single(priv->device, 1359 priv->rx_skbuff_dma[entry], 1360 priv->dma_buf_sz, DMA_FROM_DEVICE); 1361 #ifdef STMMAC_RX_DEBUG 1362 if (netif_msg_pktdata(priv)) { 1363 pr_info(" frame received (%dbytes)", frame_len); 1364 print_pkt(skb->data, frame_len); 1365 } 1366 #endif 1367 skb->protocol = eth_type_trans(skb, priv->dev); 1368 1369 if (unlikely(!priv->plat->rx_coe)) { 1370 /* No RX COE for old mac10/100 devices */ 1371 skb_checksum_none_assert(skb); 1372 netif_receive_skb(skb); 1373 } else { 1374 skb->ip_summed = CHECKSUM_UNNECESSARY; 1375 napi_gro_receive(&priv->napi, skb); 1376 } 1377 1378 priv->dev->stats.rx_packets++; 1379 priv->dev->stats.rx_bytes += frame_len; 1380 } 1381 entry = next_entry; 1382 p = p_next; /* use prefetched values */ 1383 } 1384 1385 stmmac_rx_refill(priv); 1386 1387 priv->xstats.rx_pkt_n += count; 1388 1389 return count; 1390 } 1391 1392 /** 1393 * stmmac_poll - stmmac poll method (NAPI) 1394 * @napi : pointer to the napi structure. 1395 * @budget : maximum number of packets that the current CPU can receive from 1396 * all interfaces. 1397 * Description : 1398 * This function implements the the reception process. 1399 * Also it runs the TX completion thread 1400 */ 1401 static int stmmac_poll(struct napi_struct *napi, int budget) 1402 { 1403 struct stmmac_priv *priv = container_of(napi, struct stmmac_priv, napi); 1404 int work_done = 0; 1405 1406 priv->xstats.poll_n++; 1407 stmmac_tx(priv); 1408 work_done = stmmac_rx(priv, budget); 1409 1410 if (work_done < budget) { 1411 napi_complete(napi); 1412 stmmac_enable_irq(priv); 1413 } 1414 return work_done; 1415 } 1416 1417 /** 1418 * stmmac_tx_timeout 1419 * @dev : Pointer to net device structure 1420 * Description: this function is called when a packet transmission fails to 1421 * complete within a reasonable tmrate. The driver will mark the error in the 1422 * netdev structure and arrange for the device to be reset to a sane state 1423 * in order to transmit a new packet. 1424 */ 1425 static void stmmac_tx_timeout(struct net_device *dev) 1426 { 1427 struct stmmac_priv *priv = netdev_priv(dev); 1428 1429 /* Clear Tx resources and restart transmitting again */ 1430 stmmac_tx_err(priv); 1431 } 1432 1433 /* Configuration changes (passed on by ifconfig) */ 1434 static int stmmac_config(struct net_device *dev, struct ifmap *map) 1435 { 1436 if (dev->flags & IFF_UP) /* can't act on a running interface */ 1437 return -EBUSY; 1438 1439 /* Don't allow changing the I/O address */ 1440 if (map->base_addr != dev->base_addr) { 1441 pr_warning("%s: can't change I/O address\n", dev->name); 1442 return -EOPNOTSUPP; 1443 } 1444 1445 /* Don't allow changing the IRQ */ 1446 if (map->irq != dev->irq) { 1447 pr_warning("%s: can't change IRQ number %d\n", 1448 dev->name, dev->irq); 1449 return -EOPNOTSUPP; 1450 } 1451 1452 /* ignore other fields */ 1453 return 0; 1454 } 1455 1456 /** 1457 * stmmac_set_rx_mode - entry point for multicast addressing 1458 * @dev : pointer to the device structure 1459 * Description: 1460 * This function is a driver entry point which gets called by the kernel 1461 * whenever multicast addresses must be enabled/disabled. 1462 * Return value: 1463 * void. 1464 */ 1465 static void stmmac_set_rx_mode(struct net_device *dev) 1466 { 1467 struct stmmac_priv *priv = netdev_priv(dev); 1468 1469 spin_lock(&priv->lock); 1470 priv->hw->mac->set_filter(dev, priv->synopsys_id); 1471 spin_unlock(&priv->lock); 1472 } 1473 1474 /** 1475 * stmmac_change_mtu - entry point to change MTU size for the device. 1476 * @dev : device pointer. 1477 * @new_mtu : the new MTU size for the device. 1478 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 1479 * to drive packet transmission. Ethernet has an MTU of 1500 octets 1480 * (ETH_DATA_LEN). This value can be changed with ifconfig. 1481 * Return value: 1482 * 0 on success and an appropriate (-)ve integer as defined in errno.h 1483 * file on failure. 1484 */ 1485 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 1486 { 1487 struct stmmac_priv *priv = netdev_priv(dev); 1488 int max_mtu; 1489 1490 if (netif_running(dev)) { 1491 pr_err("%s: must be stopped to change its MTU\n", dev->name); 1492 return -EBUSY; 1493 } 1494 1495 if (priv->plat->enh_desc) 1496 max_mtu = JUMBO_LEN; 1497 else 1498 max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 1499 1500 if ((new_mtu < 46) || (new_mtu > max_mtu)) { 1501 pr_err("%s: invalid MTU, max MTU is: %d\n", dev->name, max_mtu); 1502 return -EINVAL; 1503 } 1504 1505 dev->mtu = new_mtu; 1506 netdev_update_features(dev); 1507 1508 return 0; 1509 } 1510 1511 static netdev_features_t stmmac_fix_features(struct net_device *dev, 1512 netdev_features_t features) 1513 { 1514 struct stmmac_priv *priv = netdev_priv(dev); 1515 1516 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 1517 features &= ~NETIF_F_RXCSUM; 1518 else if (priv->plat->rx_coe == STMMAC_RX_COE_TYPE1) 1519 features &= ~NETIF_F_IPV6_CSUM; 1520 if (!priv->plat->tx_coe) 1521 features &= ~NETIF_F_ALL_CSUM; 1522 1523 /* Some GMAC devices have a bugged Jumbo frame support that 1524 * needs to have the Tx COE disabled for oversized frames 1525 * (due to limited buffer sizes). In this case we disable 1526 * the TX csum insertionin the TDES and not use SF. */ 1527 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 1528 features &= ~NETIF_F_ALL_CSUM; 1529 1530 return features; 1531 } 1532 1533 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 1534 { 1535 struct net_device *dev = (struct net_device *)dev_id; 1536 struct stmmac_priv *priv = netdev_priv(dev); 1537 1538 if (unlikely(!dev)) { 1539 pr_err("%s: invalid dev pointer\n", __func__); 1540 return IRQ_NONE; 1541 } 1542 1543 if (priv->plat->has_gmac) 1544 /* To handle GMAC own interrupts */ 1545 priv->hw->mac->host_irq_status((void __iomem *) dev->base_addr); 1546 1547 stmmac_dma_interrupt(priv); 1548 1549 return IRQ_HANDLED; 1550 } 1551 1552 #ifdef CONFIG_NET_POLL_CONTROLLER 1553 /* Polling receive - used by NETCONSOLE and other diagnostic tools 1554 * to allow network I/O with interrupts disabled. */ 1555 static void stmmac_poll_controller(struct net_device *dev) 1556 { 1557 disable_irq(dev->irq); 1558 stmmac_interrupt(dev->irq, dev); 1559 enable_irq(dev->irq); 1560 } 1561 #endif 1562 1563 /** 1564 * stmmac_ioctl - Entry point for the Ioctl 1565 * @dev: Device pointer. 1566 * @rq: An IOCTL specefic structure, that can contain a pointer to 1567 * a proprietary structure used to pass information to the driver. 1568 * @cmd: IOCTL command 1569 * Description: 1570 * Currently there are no special functionality supported in IOCTL, just the 1571 * phy_mii_ioctl(...) can be invoked. 1572 */ 1573 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 1574 { 1575 struct stmmac_priv *priv = netdev_priv(dev); 1576 int ret; 1577 1578 if (!netif_running(dev)) 1579 return -EINVAL; 1580 1581 if (!priv->phydev) 1582 return -EINVAL; 1583 1584 ret = phy_mii_ioctl(priv->phydev, rq, cmd); 1585 1586 return ret; 1587 } 1588 1589 #ifdef CONFIG_STMMAC_DEBUG_FS 1590 static struct dentry *stmmac_fs_dir; 1591 static struct dentry *stmmac_rings_status; 1592 static struct dentry *stmmac_dma_cap; 1593 1594 static int stmmac_sysfs_ring_read(struct seq_file *seq, void *v) 1595 { 1596 struct tmp_s { 1597 u64 a; 1598 unsigned int b; 1599 unsigned int c; 1600 }; 1601 int i; 1602 struct net_device *dev = seq->private; 1603 struct stmmac_priv *priv = netdev_priv(dev); 1604 1605 seq_printf(seq, "=======================\n"); 1606 seq_printf(seq, " RX descriptor ring\n"); 1607 seq_printf(seq, "=======================\n"); 1608 1609 for (i = 0; i < priv->dma_rx_size; i++) { 1610 struct tmp_s *x = (struct tmp_s *)(priv->dma_rx + i); 1611 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 1612 i, (unsigned int)(x->a), 1613 (unsigned int)((x->a) >> 32), x->b, x->c); 1614 seq_printf(seq, "\n"); 1615 } 1616 1617 seq_printf(seq, "\n"); 1618 seq_printf(seq, "=======================\n"); 1619 seq_printf(seq, " TX descriptor ring\n"); 1620 seq_printf(seq, "=======================\n"); 1621 1622 for (i = 0; i < priv->dma_tx_size; i++) { 1623 struct tmp_s *x = (struct tmp_s *)(priv->dma_tx + i); 1624 seq_printf(seq, "[%d] DES0=0x%x DES1=0x%x BUF1=0x%x BUF2=0x%x", 1625 i, (unsigned int)(x->a), 1626 (unsigned int)((x->a) >> 32), x->b, x->c); 1627 seq_printf(seq, "\n"); 1628 } 1629 1630 return 0; 1631 } 1632 1633 static int stmmac_sysfs_ring_open(struct inode *inode, struct file *file) 1634 { 1635 return single_open(file, stmmac_sysfs_ring_read, inode->i_private); 1636 } 1637 1638 static const struct file_operations stmmac_rings_status_fops = { 1639 .owner = THIS_MODULE, 1640 .open = stmmac_sysfs_ring_open, 1641 .read = seq_read, 1642 .llseek = seq_lseek, 1643 .release = seq_release, 1644 }; 1645 1646 static int stmmac_sysfs_dma_cap_read(struct seq_file *seq, void *v) 1647 { 1648 struct net_device *dev = seq->private; 1649 struct stmmac_priv *priv = netdev_priv(dev); 1650 1651 if (!priv->hw_cap_support) { 1652 seq_printf(seq, "DMA HW features not supported\n"); 1653 return 0; 1654 } 1655 1656 seq_printf(seq, "==============================\n"); 1657 seq_printf(seq, "\tDMA HW features\n"); 1658 seq_printf(seq, "==============================\n"); 1659 1660 seq_printf(seq, "\t10/100 Mbps %s\n", 1661 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 1662 seq_printf(seq, "\t1000 Mbps %s\n", 1663 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 1664 seq_printf(seq, "\tHalf duple %s\n", 1665 (priv->dma_cap.half_duplex) ? "Y" : "N"); 1666 seq_printf(seq, "\tHash Filter: %s\n", 1667 (priv->dma_cap.hash_filter) ? "Y" : "N"); 1668 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 1669 (priv->dma_cap.multi_addr) ? "Y" : "N"); 1670 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfatces): %s\n", 1671 (priv->dma_cap.pcs) ? "Y" : "N"); 1672 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 1673 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 1674 seq_printf(seq, "\tPMT Remote wake up: %s\n", 1675 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 1676 seq_printf(seq, "\tPMT Magic Frame: %s\n", 1677 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 1678 seq_printf(seq, "\tRMON module: %s\n", 1679 (priv->dma_cap.rmon) ? "Y" : "N"); 1680 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 1681 (priv->dma_cap.time_stamp) ? "Y" : "N"); 1682 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp:%s\n", 1683 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 1684 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE) %s\n", 1685 (priv->dma_cap.eee) ? "Y" : "N"); 1686 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 1687 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 1688 (priv->dma_cap.tx_coe) ? "Y" : "N"); 1689 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 1690 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 1691 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 1692 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 1693 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 1694 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 1695 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 1696 priv->dma_cap.number_rx_channel); 1697 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 1698 priv->dma_cap.number_tx_channel); 1699 seq_printf(seq, "\tEnhanced descriptors: %s\n", 1700 (priv->dma_cap.enh_desc) ? "Y" : "N"); 1701 1702 return 0; 1703 } 1704 1705 static int stmmac_sysfs_dma_cap_open(struct inode *inode, struct file *file) 1706 { 1707 return single_open(file, stmmac_sysfs_dma_cap_read, inode->i_private); 1708 } 1709 1710 static const struct file_operations stmmac_dma_cap_fops = { 1711 .owner = THIS_MODULE, 1712 .open = stmmac_sysfs_dma_cap_open, 1713 .read = seq_read, 1714 .llseek = seq_lseek, 1715 .release = seq_release, 1716 }; 1717 1718 static int stmmac_init_fs(struct net_device *dev) 1719 { 1720 /* Create debugfs entries */ 1721 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 1722 1723 if (!stmmac_fs_dir || IS_ERR(stmmac_fs_dir)) { 1724 pr_err("ERROR %s, debugfs create directory failed\n", 1725 STMMAC_RESOURCE_NAME); 1726 1727 return -ENOMEM; 1728 } 1729 1730 /* Entry to report DMA RX/TX rings */ 1731 stmmac_rings_status = debugfs_create_file("descriptors_status", 1732 S_IRUGO, stmmac_fs_dir, dev, 1733 &stmmac_rings_status_fops); 1734 1735 if (!stmmac_rings_status || IS_ERR(stmmac_rings_status)) { 1736 pr_info("ERROR creating stmmac ring debugfs file\n"); 1737 debugfs_remove(stmmac_fs_dir); 1738 1739 return -ENOMEM; 1740 } 1741 1742 /* Entry to report the DMA HW features */ 1743 stmmac_dma_cap = debugfs_create_file("dma_cap", S_IRUGO, stmmac_fs_dir, 1744 dev, &stmmac_dma_cap_fops); 1745 1746 if (!stmmac_dma_cap || IS_ERR(stmmac_dma_cap)) { 1747 pr_info("ERROR creating stmmac MMC debugfs file\n"); 1748 debugfs_remove(stmmac_rings_status); 1749 debugfs_remove(stmmac_fs_dir); 1750 1751 return -ENOMEM; 1752 } 1753 1754 return 0; 1755 } 1756 1757 static void stmmac_exit_fs(void) 1758 { 1759 debugfs_remove(stmmac_rings_status); 1760 debugfs_remove(stmmac_dma_cap); 1761 debugfs_remove(stmmac_fs_dir); 1762 } 1763 #endif /* CONFIG_STMMAC_DEBUG_FS */ 1764 1765 static const struct net_device_ops stmmac_netdev_ops = { 1766 .ndo_open = stmmac_open, 1767 .ndo_start_xmit = stmmac_xmit, 1768 .ndo_stop = stmmac_release, 1769 .ndo_change_mtu = stmmac_change_mtu, 1770 .ndo_fix_features = stmmac_fix_features, 1771 .ndo_set_rx_mode = stmmac_set_rx_mode, 1772 .ndo_tx_timeout = stmmac_tx_timeout, 1773 .ndo_do_ioctl = stmmac_ioctl, 1774 .ndo_set_config = stmmac_config, 1775 #ifdef CONFIG_NET_POLL_CONTROLLER 1776 .ndo_poll_controller = stmmac_poll_controller, 1777 #endif 1778 .ndo_set_mac_address = eth_mac_addr, 1779 }; 1780 1781 /** 1782 * stmmac_hw_init - Init the MAC device 1783 * @priv : pointer to the private device structure. 1784 * Description: this function detects which MAC device 1785 * (GMAC/MAC10-100) has to attached, checks the HW capability 1786 * (if supported) and sets the driver's features (for example 1787 * to use the ring or chaine mode or support the normal/enh 1788 * descriptor structure). 1789 */ 1790 static int stmmac_hw_init(struct stmmac_priv *priv) 1791 { 1792 int ret = 0; 1793 struct mac_device_info *mac; 1794 1795 /* Identify the MAC HW device */ 1796 if (priv->plat->has_gmac) { 1797 priv->dev->priv_flags |= IFF_UNICAST_FLT; 1798 mac = dwmac1000_setup(priv->ioaddr); 1799 } else { 1800 mac = dwmac100_setup(priv->ioaddr); 1801 } 1802 if (!mac) 1803 return -ENOMEM; 1804 1805 priv->hw = mac; 1806 1807 /* To use the chained or ring mode */ 1808 priv->hw->ring = &ring_mode_ops; 1809 1810 /* Get and dump the chip ID */ 1811 priv->synopsys_id = stmmac_get_synopsys_id(priv); 1812 1813 /* Get the HW capability (new GMAC newer than 3.50a) */ 1814 priv->hw_cap_support = stmmac_get_hw_features(priv); 1815 if (priv->hw_cap_support) { 1816 pr_info(" DMA HW capability register supported"); 1817 1818 /* We can override some gmac/dma configuration fields: e.g. 1819 * enh_desc, tx_coe (e.g. that are passed through the 1820 * platform) with the values from the HW capability 1821 * register (if supported). 1822 */ 1823 priv->plat->enh_desc = priv->dma_cap.enh_desc; 1824 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 1825 1826 priv->plat->tx_coe = priv->dma_cap.tx_coe; 1827 1828 if (priv->dma_cap.rx_coe_type2) 1829 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 1830 else if (priv->dma_cap.rx_coe_type1) 1831 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 1832 1833 } else 1834 pr_info(" No HW DMA feature register supported"); 1835 1836 /* Select the enhnaced/normal descriptor structures */ 1837 stmmac_selec_desc_mode(priv); 1838 1839 /* Enable the IPC (Checksum Offload) and check if the feature has been 1840 * enabled during the core configuration. */ 1841 ret = priv->hw->mac->rx_ipc(priv->ioaddr); 1842 if (!ret) { 1843 pr_warning(" RX IPC Checksum Offload not configured.\n"); 1844 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 1845 } 1846 1847 if (priv->plat->rx_coe) 1848 pr_info(" RX Checksum Offload Engine supported (type %d)\n", 1849 priv->plat->rx_coe); 1850 if (priv->plat->tx_coe) 1851 pr_info(" TX Checksum insertion supported\n"); 1852 1853 if (priv->plat->pmt) { 1854 pr_info(" Wake-Up On Lan supported\n"); 1855 device_set_wakeup_capable(priv->device, 1); 1856 } 1857 1858 return ret; 1859 } 1860 1861 /** 1862 * stmmac_dvr_probe 1863 * @device: device pointer 1864 * Description: this is the main probe function used to 1865 * call the alloc_etherdev, allocate the priv structure. 1866 */ 1867 struct stmmac_priv *stmmac_dvr_probe(struct device *device, 1868 struct plat_stmmacenet_data *plat_dat, 1869 void __iomem *addr) 1870 { 1871 int ret = 0; 1872 struct net_device *ndev = NULL; 1873 struct stmmac_priv *priv; 1874 1875 ndev = alloc_etherdev(sizeof(struct stmmac_priv)); 1876 if (!ndev) 1877 return NULL; 1878 1879 SET_NETDEV_DEV(ndev, device); 1880 1881 priv = netdev_priv(ndev); 1882 priv->device = device; 1883 priv->dev = ndev; 1884 1885 ether_setup(ndev); 1886 1887 stmmac_set_ethtool_ops(ndev); 1888 priv->pause = pause; 1889 priv->plat = plat_dat; 1890 priv->ioaddr = addr; 1891 priv->dev->base_addr = (unsigned long)addr; 1892 1893 /* Verify driver arguments */ 1894 stmmac_verify_args(); 1895 1896 /* Override with kernel parameters if supplied XXX CRS XXX 1897 * this needs to have multiple instances */ 1898 if ((phyaddr >= 0) && (phyaddr <= 31)) 1899 priv->plat->phy_addr = phyaddr; 1900 1901 /* Init MAC and get the capabilities */ 1902 stmmac_hw_init(priv); 1903 1904 ndev->netdev_ops = &stmmac_netdev_ops; 1905 1906 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 1907 NETIF_F_RXCSUM; 1908 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 1909 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 1910 #ifdef STMMAC_VLAN_TAG_USED 1911 /* Both mac100 and gmac support receive VLAN tag detection */ 1912 ndev->features |= NETIF_F_HW_VLAN_RX; 1913 #endif 1914 priv->msg_enable = netif_msg_init(debug, default_msg_level); 1915 1916 if (flow_ctrl) 1917 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 1918 1919 netif_napi_add(ndev, &priv->napi, stmmac_poll, 64); 1920 1921 spin_lock_init(&priv->lock); 1922 spin_lock_init(&priv->tx_lock); 1923 1924 ret = register_netdev(ndev); 1925 if (ret) { 1926 pr_err("%s: ERROR %i registering the device\n", __func__, ret); 1927 goto error; 1928 } 1929 1930 if (stmmac_clk_get(priv)) 1931 pr_warning("%s: warning: cannot get CSR clock\n", __func__); 1932 1933 /* If a specific clk_csr value is passed from the platform 1934 * this means that the CSR Clock Range selection cannot be 1935 * changed at run-time and it is fixed. Viceversa the driver'll try to 1936 * set the MDC clock dynamically according to the csr actual 1937 * clock input. 1938 */ 1939 if (!priv->plat->clk_csr) 1940 stmmac_clk_csr_set(priv); 1941 else 1942 priv->clk_csr = priv->plat->clk_csr; 1943 1944 /* MDIO bus Registration */ 1945 ret = stmmac_mdio_register(ndev); 1946 if (ret < 0) { 1947 pr_debug("%s: MDIO bus (id: %d) registration failed", 1948 __func__, priv->plat->bus_id); 1949 goto error; 1950 } 1951 1952 return priv; 1953 1954 error: 1955 netif_napi_del(&priv->napi); 1956 1957 unregister_netdev(ndev); 1958 free_netdev(ndev); 1959 1960 return NULL; 1961 } 1962 1963 /** 1964 * stmmac_dvr_remove 1965 * @ndev: net device pointer 1966 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 1967 * changes the link status, releases the DMA descriptor rings. 1968 */ 1969 int stmmac_dvr_remove(struct net_device *ndev) 1970 { 1971 struct stmmac_priv *priv = netdev_priv(ndev); 1972 1973 pr_info("%s:\n\tremoving driver", __func__); 1974 1975 priv->hw->dma->stop_rx(priv->ioaddr); 1976 priv->hw->dma->stop_tx(priv->ioaddr); 1977 1978 stmmac_set_mac(priv->ioaddr, false); 1979 stmmac_mdio_unregister(ndev); 1980 netif_carrier_off(ndev); 1981 unregister_netdev(ndev); 1982 free_netdev(ndev); 1983 1984 return 0; 1985 } 1986 1987 #ifdef CONFIG_PM 1988 int stmmac_suspend(struct net_device *ndev) 1989 { 1990 struct stmmac_priv *priv = netdev_priv(ndev); 1991 int dis_ic = 0; 1992 unsigned long flags; 1993 1994 if (!ndev || !netif_running(ndev)) 1995 return 0; 1996 1997 if (priv->phydev) 1998 phy_stop(priv->phydev); 1999 2000 spin_lock_irqsave(&priv->lock, flags); 2001 2002 netif_device_detach(ndev); 2003 netif_stop_queue(ndev); 2004 2005 #ifdef CONFIG_STMMAC_TIMER 2006 priv->tm->timer_stop(); 2007 if (likely(priv->tm->enable)) 2008 dis_ic = 1; 2009 #endif 2010 napi_disable(&priv->napi); 2011 2012 /* Stop TX/RX DMA */ 2013 priv->hw->dma->stop_tx(priv->ioaddr); 2014 priv->hw->dma->stop_rx(priv->ioaddr); 2015 /* Clear the Rx/Tx descriptors */ 2016 priv->hw->desc->init_rx_desc(priv->dma_rx, priv->dma_rx_size, 2017 dis_ic); 2018 priv->hw->desc->init_tx_desc(priv->dma_tx, priv->dma_tx_size); 2019 2020 /* Enable Power down mode by programming the PMT regs */ 2021 if (device_may_wakeup(priv->device)) 2022 priv->hw->mac->pmt(priv->ioaddr, priv->wolopts); 2023 else { 2024 stmmac_set_mac(priv->ioaddr, false); 2025 /* Disable clock in case of PWM is off */ 2026 stmmac_clk_disable(priv); 2027 } 2028 spin_unlock_irqrestore(&priv->lock, flags); 2029 return 0; 2030 } 2031 2032 int stmmac_resume(struct net_device *ndev) 2033 { 2034 struct stmmac_priv *priv = netdev_priv(ndev); 2035 unsigned long flags; 2036 2037 if (!netif_running(ndev)) 2038 return 0; 2039 2040 spin_lock_irqsave(&priv->lock, flags); 2041 2042 /* Power Down bit, into the PM register, is cleared 2043 * automatically as soon as a magic packet or a Wake-up frame 2044 * is received. Anyway, it's better to manually clear 2045 * this bit because it can generate problems while resuming 2046 * from another devices (e.g. serial console). */ 2047 if (device_may_wakeup(priv->device)) 2048 priv->hw->mac->pmt(priv->ioaddr, 0); 2049 else 2050 /* enable the clk prevously disabled */ 2051 stmmac_clk_enable(priv); 2052 2053 netif_device_attach(ndev); 2054 2055 /* Enable the MAC and DMA */ 2056 stmmac_set_mac(priv->ioaddr, true); 2057 priv->hw->dma->start_tx(priv->ioaddr); 2058 priv->hw->dma->start_rx(priv->ioaddr); 2059 2060 #ifdef CONFIG_STMMAC_TIMER 2061 if (likely(priv->tm->enable)) 2062 priv->tm->timer_start(tmrate); 2063 #endif 2064 napi_enable(&priv->napi); 2065 2066 netif_start_queue(ndev); 2067 2068 spin_unlock_irqrestore(&priv->lock, flags); 2069 2070 if (priv->phydev) 2071 phy_start(priv->phydev); 2072 2073 return 0; 2074 } 2075 2076 int stmmac_freeze(struct net_device *ndev) 2077 { 2078 if (!ndev || !netif_running(ndev)) 2079 return 0; 2080 2081 return stmmac_release(ndev); 2082 } 2083 2084 int stmmac_restore(struct net_device *ndev) 2085 { 2086 if (!ndev || !netif_running(ndev)) 2087 return 0; 2088 2089 return stmmac_open(ndev); 2090 } 2091 #endif /* CONFIG_PM */ 2092 2093 #ifndef MODULE 2094 static int __init stmmac_cmdline_opt(char *str) 2095 { 2096 char *opt; 2097 2098 if (!str || !*str) 2099 return -EINVAL; 2100 while ((opt = strsep(&str, ",")) != NULL) { 2101 if (!strncmp(opt, "debug:", 6)) { 2102 if (strict_strtoul(opt + 6, 0, (unsigned long *)&debug)) 2103 goto err; 2104 } else if (!strncmp(opt, "phyaddr:", 8)) { 2105 if (strict_strtoul(opt + 8, 0, 2106 (unsigned long *)&phyaddr)) 2107 goto err; 2108 } else if (!strncmp(opt, "dma_txsize:", 11)) { 2109 if (strict_strtoul(opt + 11, 0, 2110 (unsigned long *)&dma_txsize)) 2111 goto err; 2112 } else if (!strncmp(opt, "dma_rxsize:", 11)) { 2113 if (strict_strtoul(opt + 11, 0, 2114 (unsigned long *)&dma_rxsize)) 2115 goto err; 2116 } else if (!strncmp(opt, "buf_sz:", 7)) { 2117 if (strict_strtoul(opt + 7, 0, 2118 (unsigned long *)&buf_sz)) 2119 goto err; 2120 } else if (!strncmp(opt, "tc:", 3)) { 2121 if (strict_strtoul(opt + 3, 0, (unsigned long *)&tc)) 2122 goto err; 2123 } else if (!strncmp(opt, "watchdog:", 9)) { 2124 if (strict_strtoul(opt + 9, 0, 2125 (unsigned long *)&watchdog)) 2126 goto err; 2127 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 2128 if (strict_strtoul(opt + 10, 0, 2129 (unsigned long *)&flow_ctrl)) 2130 goto err; 2131 } else if (!strncmp(opt, "pause:", 6)) { 2132 if (strict_strtoul(opt + 6, 0, (unsigned long *)&pause)) 2133 goto err; 2134 #ifdef CONFIG_STMMAC_TIMER 2135 } else if (!strncmp(opt, "tmrate:", 7)) { 2136 if (strict_strtoul(opt + 7, 0, 2137 (unsigned long *)&tmrate)) 2138 goto err; 2139 #endif 2140 } 2141 } 2142 return 0; 2143 2144 err: 2145 pr_err("%s: ERROR broken module parameter conversion", __func__); 2146 return -EINVAL; 2147 } 2148 2149 __setup("stmmaceth=", stmmac_cmdline_opt); 2150 #endif 2151 2152 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 2153 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 2154 MODULE_LICENSE("GPL"); 2155