1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <linux/udp.h> 40 #include <net/pkt_cls.h> 41 #include "stmmac_ptp.h" 42 #include "stmmac.h" 43 #include <linux/reset.h> 44 #include <linux/of_mdio.h> 45 #include "dwmac1000.h" 46 #include "dwxgmac2.h" 47 #include "hwif.h" 48 49 #define STMMAC_ALIGN(x) ALIGN(ALIGN(x, SMP_CACHE_BYTES), 16) 50 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 51 52 /* Module parameters */ 53 #define TX_TIMEO 5000 54 static int watchdog = TX_TIMEO; 55 module_param(watchdog, int, 0644); 56 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 57 58 static int debug = -1; 59 module_param(debug, int, 0644); 60 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 61 62 static int phyaddr = -1; 63 module_param(phyaddr, int, 0444); 64 MODULE_PARM_DESC(phyaddr, "Physical device address"); 65 66 #define STMMAC_TX_THRESH(x) ((x)->dma_tx_size / 4) 67 #define STMMAC_RX_THRESH(x) ((x)->dma_rx_size / 4) 68 69 static int flow_ctrl = FLOW_AUTO; 70 module_param(flow_ctrl, int, 0644); 71 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 72 73 static int pause = PAUSE_TIME; 74 module_param(pause, int, 0644); 75 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 76 77 #define TC_DEFAULT 64 78 static int tc = TC_DEFAULT; 79 module_param(tc, int, 0644); 80 MODULE_PARM_DESC(tc, "DMA threshold control value"); 81 82 #define DEFAULT_BUFSIZE 1536 83 static int buf_sz = DEFAULT_BUFSIZE; 84 module_param(buf_sz, int, 0644); 85 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 86 87 #define STMMAC_RX_COPYBREAK 256 88 89 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 90 NETIF_MSG_LINK | NETIF_MSG_IFUP | 91 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 92 93 #define STMMAC_DEFAULT_LPI_TIMER 1000 94 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 95 module_param(eee_timer, int, 0644); 96 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 97 #define STMMAC_LPI_T(x) (jiffies + usecs_to_jiffies(x)) 98 99 /* By default the driver will use the ring mode to manage tx and rx descriptors, 100 * but allow user to force to use the chain instead of the ring 101 */ 102 static unsigned int chain_mode; 103 module_param(chain_mode, int, 0444); 104 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 105 106 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 107 108 #ifdef CONFIG_DEBUG_FS 109 static const struct net_device_ops stmmac_netdev_ops; 110 static void stmmac_init_fs(struct net_device *dev); 111 static void stmmac_exit_fs(struct net_device *dev); 112 #endif 113 114 #define STMMAC_COAL_TIMER(x) (ns_to_ktime((x) * NSEC_PER_USEC)) 115 116 /** 117 * stmmac_verify_args - verify the driver parameters. 118 * Description: it checks the driver parameters and set a default in case of 119 * errors. 120 */ 121 static void stmmac_verify_args(void) 122 { 123 if (unlikely(watchdog < 0)) 124 watchdog = TX_TIMEO; 125 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 126 buf_sz = DEFAULT_BUFSIZE; 127 if (unlikely(flow_ctrl > 1)) 128 flow_ctrl = FLOW_AUTO; 129 else if (likely(flow_ctrl < 0)) 130 flow_ctrl = FLOW_OFF; 131 if (unlikely((pause < 0) || (pause > 0xffff))) 132 pause = PAUSE_TIME; 133 if (eee_timer < 0) 134 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 135 } 136 137 /** 138 * stmmac_disable_all_queues - Disable all queues 139 * @priv: driver private structure 140 */ 141 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 142 { 143 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 144 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 145 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 146 u32 queue; 147 148 for (queue = 0; queue < maxq; queue++) { 149 struct stmmac_channel *ch = &priv->channel[queue]; 150 151 if (queue < rx_queues_cnt) 152 napi_disable(&ch->rx_napi); 153 if (queue < tx_queues_cnt) 154 napi_disable(&ch->tx_napi); 155 } 156 } 157 158 /** 159 * stmmac_enable_all_queues - Enable all queues 160 * @priv: driver private structure 161 */ 162 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 163 { 164 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 165 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 166 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 167 u32 queue; 168 169 for (queue = 0; queue < maxq; queue++) { 170 struct stmmac_channel *ch = &priv->channel[queue]; 171 172 if (queue < rx_queues_cnt) 173 napi_enable(&ch->rx_napi); 174 if (queue < tx_queues_cnt) 175 napi_enable(&ch->tx_napi); 176 } 177 } 178 179 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 180 { 181 if (!test_bit(STMMAC_DOWN, &priv->state) && 182 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 183 queue_work(priv->wq, &priv->service_task); 184 } 185 186 static void stmmac_global_err(struct stmmac_priv *priv) 187 { 188 netif_carrier_off(priv->dev); 189 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 190 stmmac_service_event_schedule(priv); 191 } 192 193 /** 194 * stmmac_clk_csr_set - dynamically set the MDC clock 195 * @priv: driver private structure 196 * Description: this is to dynamically set the MDC clock according to the csr 197 * clock input. 198 * Note: 199 * If a specific clk_csr value is passed from the platform 200 * this means that the CSR Clock Range selection cannot be 201 * changed at run-time and it is fixed (as reported in the driver 202 * documentation). Viceversa the driver will try to set the MDC 203 * clock dynamically according to the actual clock input. 204 */ 205 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 206 { 207 u32 clk_rate; 208 209 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 210 211 /* Platform provided default clk_csr would be assumed valid 212 * for all other cases except for the below mentioned ones. 213 * For values higher than the IEEE 802.3 specified frequency 214 * we can not estimate the proper divider as it is not known 215 * the frequency of clk_csr_i. So we do not change the default 216 * divider. 217 */ 218 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 219 if (clk_rate < CSR_F_35M) 220 priv->clk_csr = STMMAC_CSR_20_35M; 221 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 222 priv->clk_csr = STMMAC_CSR_35_60M; 223 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 224 priv->clk_csr = STMMAC_CSR_60_100M; 225 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 226 priv->clk_csr = STMMAC_CSR_100_150M; 227 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 228 priv->clk_csr = STMMAC_CSR_150_250M; 229 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 230 priv->clk_csr = STMMAC_CSR_250_300M; 231 } 232 233 if (priv->plat->has_sun8i) { 234 if (clk_rate > 160000000) 235 priv->clk_csr = 0x03; 236 else if (clk_rate > 80000000) 237 priv->clk_csr = 0x02; 238 else if (clk_rate > 40000000) 239 priv->clk_csr = 0x01; 240 else 241 priv->clk_csr = 0; 242 } 243 244 if (priv->plat->has_xgmac) { 245 if (clk_rate > 400000000) 246 priv->clk_csr = 0x5; 247 else if (clk_rate > 350000000) 248 priv->clk_csr = 0x4; 249 else if (clk_rate > 300000000) 250 priv->clk_csr = 0x3; 251 else if (clk_rate > 250000000) 252 priv->clk_csr = 0x2; 253 else if (clk_rate > 150000000) 254 priv->clk_csr = 0x1; 255 else 256 priv->clk_csr = 0x0; 257 } 258 } 259 260 static void print_pkt(unsigned char *buf, int len) 261 { 262 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 263 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 264 } 265 266 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 267 { 268 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 269 u32 avail; 270 271 if (tx_q->dirty_tx > tx_q->cur_tx) 272 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 273 else 274 avail = priv->dma_tx_size - tx_q->cur_tx + tx_q->dirty_tx - 1; 275 276 return avail; 277 } 278 279 /** 280 * stmmac_rx_dirty - Get RX queue dirty 281 * @priv: driver private structure 282 * @queue: RX queue index 283 */ 284 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 285 { 286 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 287 u32 dirty; 288 289 if (rx_q->dirty_rx <= rx_q->cur_rx) 290 dirty = rx_q->cur_rx - rx_q->dirty_rx; 291 else 292 dirty = priv->dma_rx_size - rx_q->dirty_rx + rx_q->cur_rx; 293 294 return dirty; 295 } 296 297 static void stmmac_lpi_entry_timer_config(struct stmmac_priv *priv, bool en) 298 { 299 int tx_lpi_timer; 300 301 /* Clear/set the SW EEE timer flag based on LPI ET enablement */ 302 priv->eee_sw_timer_en = en ? 0 : 1; 303 tx_lpi_timer = en ? priv->tx_lpi_timer : 0; 304 stmmac_set_eee_lpi_timer(priv, priv->hw, tx_lpi_timer); 305 } 306 307 /** 308 * stmmac_enable_eee_mode - check and enter in LPI mode 309 * @priv: driver private structure 310 * Description: this function is to verify and enter in LPI mode in case of 311 * EEE. 312 */ 313 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 314 { 315 u32 tx_cnt = priv->plat->tx_queues_to_use; 316 u32 queue; 317 318 /* check if all TX queues have the work finished */ 319 for (queue = 0; queue < tx_cnt; queue++) { 320 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 321 322 if (tx_q->dirty_tx != tx_q->cur_tx) 323 return; /* still unfinished work */ 324 } 325 326 /* Check and enter in LPI mode */ 327 if (!priv->tx_path_in_lpi_mode) 328 stmmac_set_eee_mode(priv, priv->hw, 329 priv->plat->en_tx_lpi_clockgating); 330 } 331 332 /** 333 * stmmac_disable_eee_mode - disable and exit from LPI mode 334 * @priv: driver private structure 335 * Description: this function is to exit and disable EEE in case of 336 * LPI state is true. This is called by the xmit. 337 */ 338 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 339 { 340 if (!priv->eee_sw_timer_en) { 341 stmmac_lpi_entry_timer_config(priv, 0); 342 return; 343 } 344 345 stmmac_reset_eee_mode(priv, priv->hw); 346 del_timer_sync(&priv->eee_ctrl_timer); 347 priv->tx_path_in_lpi_mode = false; 348 } 349 350 /** 351 * stmmac_eee_ctrl_timer - EEE TX SW timer. 352 * @t: timer_list struct containing private info 353 * Description: 354 * if there is no data transfer and if we are not in LPI state, 355 * then MAC Transmitter can be moved to LPI state. 356 */ 357 static void stmmac_eee_ctrl_timer(struct timer_list *t) 358 { 359 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 360 361 stmmac_enable_eee_mode(priv); 362 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 363 } 364 365 /** 366 * stmmac_eee_init - init EEE 367 * @priv: driver private structure 368 * Description: 369 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 370 * can also manage EEE, this function enable the LPI state and start related 371 * timer. 372 */ 373 bool stmmac_eee_init(struct stmmac_priv *priv) 374 { 375 int eee_tw_timer = priv->eee_tw_timer; 376 377 /* Using PCS we cannot dial with the phy registers at this stage 378 * so we do not support extra feature like EEE. 379 */ 380 if (priv->hw->pcs == STMMAC_PCS_TBI || 381 priv->hw->pcs == STMMAC_PCS_RTBI) 382 return false; 383 384 /* Check if MAC core supports the EEE feature. */ 385 if (!priv->dma_cap.eee) 386 return false; 387 388 mutex_lock(&priv->lock); 389 390 /* Check if it needs to be deactivated */ 391 if (!priv->eee_active) { 392 if (priv->eee_enabled) { 393 netdev_dbg(priv->dev, "disable EEE\n"); 394 stmmac_lpi_entry_timer_config(priv, 0); 395 del_timer_sync(&priv->eee_ctrl_timer); 396 stmmac_set_eee_timer(priv, priv->hw, 0, eee_tw_timer); 397 } 398 mutex_unlock(&priv->lock); 399 return false; 400 } 401 402 if (priv->eee_active && !priv->eee_enabled) { 403 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 404 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 405 eee_tw_timer); 406 } 407 408 if (priv->plat->has_gmac4 && priv->tx_lpi_timer <= STMMAC_ET_MAX) { 409 del_timer_sync(&priv->eee_ctrl_timer); 410 priv->tx_path_in_lpi_mode = false; 411 stmmac_lpi_entry_timer_config(priv, 1); 412 } else { 413 stmmac_lpi_entry_timer_config(priv, 0); 414 mod_timer(&priv->eee_ctrl_timer, 415 STMMAC_LPI_T(priv->tx_lpi_timer)); 416 } 417 418 mutex_unlock(&priv->lock); 419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 420 return true; 421 } 422 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 424 * @priv: driver private structure 425 * @p : descriptor pointer 426 * @skb : the socket buffer 427 * Description : 428 * This function will read timestamp from the descriptor & pass it to stack. 429 * and also perform some sanity checks. 430 */ 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 432 struct dma_desc *p, struct sk_buff *skb) 433 { 434 struct skb_shared_hwtstamps shhwtstamp; 435 bool found = false; 436 u64 ns = 0; 437 438 if (!priv->hwts_tx_en) 439 return; 440 441 /* exit if skb doesn't support hw tstamp */ 442 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 443 return; 444 445 /* check tx tstamp status */ 446 if (stmmac_get_tx_timestamp_status(priv, p)) { 447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 448 found = true; 449 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 450 found = true; 451 } 452 453 if (found) { 454 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 455 shhwtstamp.hwtstamp = ns_to_ktime(ns); 456 457 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 458 /* pass tstamp to stack */ 459 skb_tstamp_tx(skb, &shhwtstamp); 460 } 461 } 462 463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 464 * @priv: driver private structure 465 * @p : descriptor pointer 466 * @np : next descriptor pointer 467 * @skb : the socket buffer 468 * Description : 469 * This function will read received packet's timestamp from the descriptor 470 * and pass it to stack. It also perform some sanity checks. 471 */ 472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 473 struct dma_desc *np, struct sk_buff *skb) 474 { 475 struct skb_shared_hwtstamps *shhwtstamp = NULL; 476 struct dma_desc *desc = p; 477 u64 ns = 0; 478 479 if (!priv->hwts_rx_en) 480 return; 481 /* For GMAC4, the valid timestamp is from CTX next desc. */ 482 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 483 desc = np; 484 485 /* Check if timestamp is available */ 486 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 487 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 488 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 489 shhwtstamp = skb_hwtstamps(skb); 490 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 491 shhwtstamp->hwtstamp = ns_to_ktime(ns); 492 } else { 493 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 494 } 495 } 496 497 /** 498 * stmmac_hwtstamp_set - control hardware timestamping. 499 * @dev: device pointer. 500 * @ifr: An IOCTL specific structure, that can contain a pointer to 501 * a proprietary structure used to pass information to the driver. 502 * Description: 503 * This function configures the MAC to enable/disable both outgoing(TX) 504 * and incoming(RX) packets time stamping based on user input. 505 * Return Value: 506 * 0 on success and an appropriate -ve integer on failure. 507 */ 508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 509 { 510 struct stmmac_priv *priv = netdev_priv(dev); 511 struct hwtstamp_config config; 512 struct timespec64 now; 513 u64 temp = 0; 514 u32 ptp_v2 = 0; 515 u32 tstamp_all = 0; 516 u32 ptp_over_ipv4_udp = 0; 517 u32 ptp_over_ipv6_udp = 0; 518 u32 ptp_over_ethernet = 0; 519 u32 snap_type_sel = 0; 520 u32 ts_master_en = 0; 521 u32 ts_event_en = 0; 522 u32 sec_inc = 0; 523 u32 value = 0; 524 bool xmac; 525 526 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 527 528 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 529 netdev_alert(priv->dev, "No support for HW time stamping\n"); 530 priv->hwts_tx_en = 0; 531 priv->hwts_rx_en = 0; 532 533 return -EOPNOTSUPP; 534 } 535 536 if (copy_from_user(&config, ifr->ifr_data, 537 sizeof(config))) 538 return -EFAULT; 539 540 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 541 __func__, config.flags, config.tx_type, config.rx_filter); 542 543 /* reserved for future extensions */ 544 if (config.flags) 545 return -EINVAL; 546 547 if (config.tx_type != HWTSTAMP_TX_OFF && 548 config.tx_type != HWTSTAMP_TX_ON) 549 return -ERANGE; 550 551 if (priv->adv_ts) { 552 switch (config.rx_filter) { 553 case HWTSTAMP_FILTER_NONE: 554 /* time stamp no incoming packet at all */ 555 config.rx_filter = HWTSTAMP_FILTER_NONE; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 559 /* PTP v1, UDP, any kind of event packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 561 /* 'xmac' hardware can support Sync, Pdelay_Req and 562 * Pdelay_resp by setting bit14 and bits17/16 to 01 563 * This leaves Delay_Req timestamps out. 564 * Enable all events *and* general purpose message 565 * timestamping 566 */ 567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 570 break; 571 572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 573 /* PTP v1, UDP, Sync packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 575 /* take time stamp for SYNC messages only */ 576 ts_event_en = PTP_TCR_TSEVNTENA; 577 578 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 579 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 580 break; 581 582 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 583 /* PTP v1, UDP, Delay_req packet */ 584 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 585 /* take time stamp for Delay_Req messages only */ 586 ts_master_en = PTP_TCR_TSMSTRENA; 587 ts_event_en = PTP_TCR_TSEVNTENA; 588 589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 591 break; 592 593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 594 /* PTP v2, UDP, any kind of event packet */ 595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 596 ptp_v2 = PTP_TCR_TSVER2ENA; 597 /* take time stamp for all event messages */ 598 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 599 600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 602 break; 603 604 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 605 /* PTP v2, UDP, Sync packet */ 606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 607 ptp_v2 = PTP_TCR_TSVER2ENA; 608 /* take time stamp for SYNC messages only */ 609 ts_event_en = PTP_TCR_TSEVNTENA; 610 611 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 612 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 613 break; 614 615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 616 /* PTP v2, UDP, Delay_req packet */ 617 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 618 ptp_v2 = PTP_TCR_TSVER2ENA; 619 /* take time stamp for Delay_Req messages only */ 620 ts_master_en = PTP_TCR_TSMSTRENA; 621 ts_event_en = PTP_TCR_TSEVNTENA; 622 623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 625 break; 626 627 case HWTSTAMP_FILTER_PTP_V2_EVENT: 628 /* PTP v2/802.AS1 any layer, any kind of event packet */ 629 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 630 ptp_v2 = PTP_TCR_TSVER2ENA; 631 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 632 if (priv->synopsys_id != DWMAC_CORE_5_10) 633 ts_event_en = PTP_TCR_TSEVNTENA; 634 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 635 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 636 ptp_over_ethernet = PTP_TCR_TSIPENA; 637 break; 638 639 case HWTSTAMP_FILTER_PTP_V2_SYNC: 640 /* PTP v2/802.AS1, any layer, Sync packet */ 641 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 642 ptp_v2 = PTP_TCR_TSVER2ENA; 643 /* take time stamp for SYNC messages only */ 644 ts_event_en = PTP_TCR_TSEVNTENA; 645 646 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 647 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 648 ptp_over_ethernet = PTP_TCR_TSIPENA; 649 break; 650 651 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 652 /* PTP v2/802.AS1, any layer, Delay_req packet */ 653 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 654 ptp_v2 = PTP_TCR_TSVER2ENA; 655 /* take time stamp for Delay_Req messages only */ 656 ts_master_en = PTP_TCR_TSMSTRENA; 657 ts_event_en = PTP_TCR_TSEVNTENA; 658 659 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 660 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 661 ptp_over_ethernet = PTP_TCR_TSIPENA; 662 break; 663 664 case HWTSTAMP_FILTER_NTP_ALL: 665 case HWTSTAMP_FILTER_ALL: 666 /* time stamp any incoming packet */ 667 config.rx_filter = HWTSTAMP_FILTER_ALL; 668 tstamp_all = PTP_TCR_TSENALL; 669 break; 670 671 default: 672 return -ERANGE; 673 } 674 } else { 675 switch (config.rx_filter) { 676 case HWTSTAMP_FILTER_NONE: 677 config.rx_filter = HWTSTAMP_FILTER_NONE; 678 break; 679 default: 680 /* PTP v1, UDP, any kind of event packet */ 681 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 682 break; 683 } 684 } 685 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 686 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 687 688 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 689 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 690 else { 691 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 692 tstamp_all | ptp_v2 | ptp_over_ethernet | 693 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 694 ts_master_en | snap_type_sel); 695 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 696 697 /* program Sub Second Increment reg */ 698 stmmac_config_sub_second_increment(priv, 699 priv->ptpaddr, priv->plat->clk_ptp_rate, 700 xmac, &sec_inc); 701 temp = div_u64(1000000000ULL, sec_inc); 702 703 /* Store sub second increment and flags for later use */ 704 priv->sub_second_inc = sec_inc; 705 priv->systime_flags = value; 706 707 /* calculate default added value: 708 * formula is : 709 * addend = (2^32)/freq_div_ratio; 710 * where, freq_div_ratio = 1e9ns/sec_inc 711 */ 712 temp = (u64)(temp << 32); 713 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 714 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 715 716 /* initialize system time */ 717 ktime_get_real_ts64(&now); 718 719 /* lower 32 bits of tv_sec are safe until y2106 */ 720 stmmac_init_systime(priv, priv->ptpaddr, 721 (u32)now.tv_sec, now.tv_nsec); 722 } 723 724 memcpy(&priv->tstamp_config, &config, sizeof(config)); 725 726 return copy_to_user(ifr->ifr_data, &config, 727 sizeof(config)) ? -EFAULT : 0; 728 } 729 730 /** 731 * stmmac_hwtstamp_get - read hardware timestamping. 732 * @dev: device pointer. 733 * @ifr: An IOCTL specific structure, that can contain a pointer to 734 * a proprietary structure used to pass information to the driver. 735 * Description: 736 * This function obtain the current hardware timestamping settings 737 * as requested. 738 */ 739 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 740 { 741 struct stmmac_priv *priv = netdev_priv(dev); 742 struct hwtstamp_config *config = &priv->tstamp_config; 743 744 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 745 return -EOPNOTSUPP; 746 747 return copy_to_user(ifr->ifr_data, config, 748 sizeof(*config)) ? -EFAULT : 0; 749 } 750 751 /** 752 * stmmac_init_ptp - init PTP 753 * @priv: driver private structure 754 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 755 * This is done by looking at the HW cap. register. 756 * This function also registers the ptp driver. 757 */ 758 static int stmmac_init_ptp(struct stmmac_priv *priv) 759 { 760 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 761 762 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 763 return -EOPNOTSUPP; 764 765 priv->adv_ts = 0; 766 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 767 if (xmac && priv->dma_cap.atime_stamp) 768 priv->adv_ts = 1; 769 /* Dwmac 3.x core with extend_desc can support adv_ts */ 770 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 771 priv->adv_ts = 1; 772 773 if (priv->dma_cap.time_stamp) 774 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 775 776 if (priv->adv_ts) 777 netdev_info(priv->dev, 778 "IEEE 1588-2008 Advanced Timestamp supported\n"); 779 780 priv->hwts_tx_en = 0; 781 priv->hwts_rx_en = 0; 782 783 stmmac_ptp_register(priv); 784 785 return 0; 786 } 787 788 static void stmmac_release_ptp(struct stmmac_priv *priv) 789 { 790 clk_disable_unprepare(priv->plat->clk_ptp_ref); 791 stmmac_ptp_unregister(priv); 792 } 793 794 /** 795 * stmmac_mac_flow_ctrl - Configure flow control in all queues 796 * @priv: driver private structure 797 * @duplex: duplex passed to the next function 798 * Description: It is used for configuring the flow control in all queues 799 */ 800 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 801 { 802 u32 tx_cnt = priv->plat->tx_queues_to_use; 803 804 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 805 priv->pause, tx_cnt); 806 } 807 808 static void stmmac_validate(struct phylink_config *config, 809 unsigned long *supported, 810 struct phylink_link_state *state) 811 { 812 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 813 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 814 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 815 int tx_cnt = priv->plat->tx_queues_to_use; 816 int max_speed = priv->plat->max_speed; 817 818 phylink_set(mac_supported, 10baseT_Half); 819 phylink_set(mac_supported, 10baseT_Full); 820 phylink_set(mac_supported, 100baseT_Half); 821 phylink_set(mac_supported, 100baseT_Full); 822 phylink_set(mac_supported, 1000baseT_Half); 823 phylink_set(mac_supported, 1000baseT_Full); 824 phylink_set(mac_supported, 1000baseKX_Full); 825 826 phylink_set(mac_supported, Autoneg); 827 phylink_set(mac_supported, Pause); 828 phylink_set(mac_supported, Asym_Pause); 829 phylink_set_port_modes(mac_supported); 830 831 /* Cut down 1G if asked to */ 832 if ((max_speed > 0) && (max_speed < 1000)) { 833 phylink_set(mask, 1000baseT_Full); 834 phylink_set(mask, 1000baseX_Full); 835 } else if (priv->plat->has_xgmac) { 836 if (!max_speed || (max_speed >= 2500)) { 837 phylink_set(mac_supported, 2500baseT_Full); 838 phylink_set(mac_supported, 2500baseX_Full); 839 } 840 if (!max_speed || (max_speed >= 5000)) { 841 phylink_set(mac_supported, 5000baseT_Full); 842 } 843 if (!max_speed || (max_speed >= 10000)) { 844 phylink_set(mac_supported, 10000baseSR_Full); 845 phylink_set(mac_supported, 10000baseLR_Full); 846 phylink_set(mac_supported, 10000baseER_Full); 847 phylink_set(mac_supported, 10000baseLRM_Full); 848 phylink_set(mac_supported, 10000baseT_Full); 849 phylink_set(mac_supported, 10000baseKX4_Full); 850 phylink_set(mac_supported, 10000baseKR_Full); 851 } 852 if (!max_speed || (max_speed >= 25000)) { 853 phylink_set(mac_supported, 25000baseCR_Full); 854 phylink_set(mac_supported, 25000baseKR_Full); 855 phylink_set(mac_supported, 25000baseSR_Full); 856 } 857 if (!max_speed || (max_speed >= 40000)) { 858 phylink_set(mac_supported, 40000baseKR4_Full); 859 phylink_set(mac_supported, 40000baseCR4_Full); 860 phylink_set(mac_supported, 40000baseSR4_Full); 861 phylink_set(mac_supported, 40000baseLR4_Full); 862 } 863 if (!max_speed || (max_speed >= 50000)) { 864 phylink_set(mac_supported, 50000baseCR2_Full); 865 phylink_set(mac_supported, 50000baseKR2_Full); 866 phylink_set(mac_supported, 50000baseSR2_Full); 867 phylink_set(mac_supported, 50000baseKR_Full); 868 phylink_set(mac_supported, 50000baseSR_Full); 869 phylink_set(mac_supported, 50000baseCR_Full); 870 phylink_set(mac_supported, 50000baseLR_ER_FR_Full); 871 phylink_set(mac_supported, 50000baseDR_Full); 872 } 873 if (!max_speed || (max_speed >= 100000)) { 874 phylink_set(mac_supported, 100000baseKR4_Full); 875 phylink_set(mac_supported, 100000baseSR4_Full); 876 phylink_set(mac_supported, 100000baseCR4_Full); 877 phylink_set(mac_supported, 100000baseLR4_ER4_Full); 878 phylink_set(mac_supported, 100000baseKR2_Full); 879 phylink_set(mac_supported, 100000baseSR2_Full); 880 phylink_set(mac_supported, 100000baseCR2_Full); 881 phylink_set(mac_supported, 100000baseLR2_ER2_FR2_Full); 882 phylink_set(mac_supported, 100000baseDR2_Full); 883 } 884 } 885 886 /* Half-Duplex can only work with single queue */ 887 if (tx_cnt > 1) { 888 phylink_set(mask, 10baseT_Half); 889 phylink_set(mask, 100baseT_Half); 890 phylink_set(mask, 1000baseT_Half); 891 } 892 893 linkmode_and(supported, supported, mac_supported); 894 linkmode_andnot(supported, supported, mask); 895 896 linkmode_and(state->advertising, state->advertising, mac_supported); 897 linkmode_andnot(state->advertising, state->advertising, mask); 898 899 /* If PCS is supported, check which modes it supports. */ 900 stmmac_xpcs_validate(priv, &priv->hw->xpcs_args, supported, state); 901 } 902 903 static void stmmac_mac_pcs_get_state(struct phylink_config *config, 904 struct phylink_link_state *state) 905 { 906 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 907 908 state->link = 0; 909 stmmac_xpcs_get_state(priv, &priv->hw->xpcs_args, state); 910 } 911 912 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 913 const struct phylink_link_state *state) 914 { 915 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 916 917 stmmac_xpcs_config(priv, &priv->hw->xpcs_args, state); 918 } 919 920 static void stmmac_mac_an_restart(struct phylink_config *config) 921 { 922 /* Not Supported */ 923 } 924 925 static void stmmac_mac_link_down(struct phylink_config *config, 926 unsigned int mode, phy_interface_t interface) 927 { 928 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 929 930 stmmac_mac_set(priv, priv->ioaddr, false); 931 priv->eee_active = false; 932 priv->tx_lpi_enabled = false; 933 stmmac_eee_init(priv); 934 stmmac_set_eee_pls(priv, priv->hw, false); 935 } 936 937 static void stmmac_mac_link_up(struct phylink_config *config, 938 struct phy_device *phy, 939 unsigned int mode, phy_interface_t interface, 940 int speed, int duplex, 941 bool tx_pause, bool rx_pause) 942 { 943 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 944 u32 ctrl; 945 946 stmmac_xpcs_link_up(priv, &priv->hw->xpcs_args, speed, interface); 947 948 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 949 ctrl &= ~priv->hw->link.speed_mask; 950 951 if (interface == PHY_INTERFACE_MODE_USXGMII) { 952 switch (speed) { 953 case SPEED_10000: 954 ctrl |= priv->hw->link.xgmii.speed10000; 955 break; 956 case SPEED_5000: 957 ctrl |= priv->hw->link.xgmii.speed5000; 958 break; 959 case SPEED_2500: 960 ctrl |= priv->hw->link.xgmii.speed2500; 961 break; 962 default: 963 return; 964 } 965 } else if (interface == PHY_INTERFACE_MODE_XLGMII) { 966 switch (speed) { 967 case SPEED_100000: 968 ctrl |= priv->hw->link.xlgmii.speed100000; 969 break; 970 case SPEED_50000: 971 ctrl |= priv->hw->link.xlgmii.speed50000; 972 break; 973 case SPEED_40000: 974 ctrl |= priv->hw->link.xlgmii.speed40000; 975 break; 976 case SPEED_25000: 977 ctrl |= priv->hw->link.xlgmii.speed25000; 978 break; 979 case SPEED_10000: 980 ctrl |= priv->hw->link.xgmii.speed10000; 981 break; 982 case SPEED_2500: 983 ctrl |= priv->hw->link.speed2500; 984 break; 985 case SPEED_1000: 986 ctrl |= priv->hw->link.speed1000; 987 break; 988 default: 989 return; 990 } 991 } else { 992 switch (speed) { 993 case SPEED_2500: 994 ctrl |= priv->hw->link.speed2500; 995 break; 996 case SPEED_1000: 997 ctrl |= priv->hw->link.speed1000; 998 break; 999 case SPEED_100: 1000 ctrl |= priv->hw->link.speed100; 1001 break; 1002 case SPEED_10: 1003 ctrl |= priv->hw->link.speed10; 1004 break; 1005 default: 1006 return; 1007 } 1008 } 1009 1010 priv->speed = speed; 1011 1012 if (priv->plat->fix_mac_speed) 1013 priv->plat->fix_mac_speed(priv->plat->bsp_priv, speed); 1014 1015 if (!duplex) 1016 ctrl &= ~priv->hw->link.duplex; 1017 else 1018 ctrl |= priv->hw->link.duplex; 1019 1020 /* Flow Control operation */ 1021 if (tx_pause && rx_pause) 1022 stmmac_mac_flow_ctrl(priv, duplex); 1023 1024 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 1025 1026 stmmac_mac_set(priv, priv->ioaddr, true); 1027 if (phy && priv->dma_cap.eee) { 1028 priv->eee_active = phy_init_eee(phy, 1) >= 0; 1029 priv->eee_enabled = stmmac_eee_init(priv); 1030 priv->tx_lpi_enabled = priv->eee_enabled; 1031 stmmac_set_eee_pls(priv, priv->hw, true); 1032 } 1033 } 1034 1035 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 1036 .validate = stmmac_validate, 1037 .mac_pcs_get_state = stmmac_mac_pcs_get_state, 1038 .mac_config = stmmac_mac_config, 1039 .mac_an_restart = stmmac_mac_an_restart, 1040 .mac_link_down = stmmac_mac_link_down, 1041 .mac_link_up = stmmac_mac_link_up, 1042 }; 1043 1044 /** 1045 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 1046 * @priv: driver private structure 1047 * Description: this is to verify if the HW supports the PCS. 1048 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 1049 * configured for the TBI, RTBI, or SGMII PHY interface. 1050 */ 1051 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 1052 { 1053 int interface = priv->plat->interface; 1054 1055 if (priv->dma_cap.pcs) { 1056 if ((interface == PHY_INTERFACE_MODE_RGMII) || 1057 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 1058 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 1059 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 1060 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 1061 priv->hw->pcs = STMMAC_PCS_RGMII; 1062 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 1063 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 1064 priv->hw->pcs = STMMAC_PCS_SGMII; 1065 } 1066 } 1067 } 1068 1069 /** 1070 * stmmac_init_phy - PHY initialization 1071 * @dev: net device structure 1072 * Description: it initializes the driver's PHY state, and attaches the PHY 1073 * to the mac driver. 1074 * Return value: 1075 * 0 on success 1076 */ 1077 static int stmmac_init_phy(struct net_device *dev) 1078 { 1079 struct ethtool_wolinfo wol = { .cmd = ETHTOOL_GWOL }; 1080 struct stmmac_priv *priv = netdev_priv(dev); 1081 struct device_node *node; 1082 int ret; 1083 1084 node = priv->plat->phylink_node; 1085 1086 if (node) 1087 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1088 1089 /* Some DT bindings do not set-up the PHY handle. Let's try to 1090 * manually parse it 1091 */ 1092 if (!node || ret) { 1093 int addr = priv->plat->phy_addr; 1094 struct phy_device *phydev; 1095 1096 phydev = mdiobus_get_phy(priv->mii, addr); 1097 if (!phydev) { 1098 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1099 return -ENODEV; 1100 } 1101 1102 ret = phylink_connect_phy(priv->phylink, phydev); 1103 } 1104 1105 phylink_ethtool_get_wol(priv->phylink, &wol); 1106 device_set_wakeup_capable(priv->device, !!wol.supported); 1107 1108 return ret; 1109 } 1110 1111 static int stmmac_phy_setup(struct stmmac_priv *priv) 1112 { 1113 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1114 int mode = priv->plat->phy_interface; 1115 struct phylink *phylink; 1116 1117 priv->phylink_config.dev = &priv->dev->dev; 1118 priv->phylink_config.type = PHYLINK_NETDEV; 1119 priv->phylink_config.pcs_poll = true; 1120 1121 if (!fwnode) 1122 fwnode = dev_fwnode(priv->device); 1123 1124 phylink = phylink_create(&priv->phylink_config, fwnode, 1125 mode, &stmmac_phylink_mac_ops); 1126 if (IS_ERR(phylink)) 1127 return PTR_ERR(phylink); 1128 1129 priv->phylink = phylink; 1130 return 0; 1131 } 1132 1133 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1134 { 1135 u32 rx_cnt = priv->plat->rx_queues_to_use; 1136 void *head_rx; 1137 u32 queue; 1138 1139 /* Display RX rings */ 1140 for (queue = 0; queue < rx_cnt; queue++) { 1141 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1142 1143 pr_info("\tRX Queue %u rings\n", queue); 1144 1145 if (priv->extend_desc) 1146 head_rx = (void *)rx_q->dma_erx; 1147 else 1148 head_rx = (void *)rx_q->dma_rx; 1149 1150 /* Display RX ring */ 1151 stmmac_display_ring(priv, head_rx, priv->dma_rx_size, true); 1152 } 1153 } 1154 1155 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1156 { 1157 u32 tx_cnt = priv->plat->tx_queues_to_use; 1158 void *head_tx; 1159 u32 queue; 1160 1161 /* Display TX rings */ 1162 for (queue = 0; queue < tx_cnt; queue++) { 1163 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1164 1165 pr_info("\tTX Queue %d rings\n", queue); 1166 1167 if (priv->extend_desc) 1168 head_tx = (void *)tx_q->dma_etx; 1169 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1170 head_tx = (void *)tx_q->dma_entx; 1171 else 1172 head_tx = (void *)tx_q->dma_tx; 1173 1174 stmmac_display_ring(priv, head_tx, priv->dma_tx_size, false); 1175 } 1176 } 1177 1178 static void stmmac_display_rings(struct stmmac_priv *priv) 1179 { 1180 /* Display RX ring */ 1181 stmmac_display_rx_rings(priv); 1182 1183 /* Display TX ring */ 1184 stmmac_display_tx_rings(priv); 1185 } 1186 1187 static int stmmac_set_bfsize(int mtu, int bufsize) 1188 { 1189 int ret = bufsize; 1190 1191 if (mtu >= BUF_SIZE_8KiB) 1192 ret = BUF_SIZE_16KiB; 1193 else if (mtu >= BUF_SIZE_4KiB) 1194 ret = BUF_SIZE_8KiB; 1195 else if (mtu >= BUF_SIZE_2KiB) 1196 ret = BUF_SIZE_4KiB; 1197 else if (mtu > DEFAULT_BUFSIZE) 1198 ret = BUF_SIZE_2KiB; 1199 else 1200 ret = DEFAULT_BUFSIZE; 1201 1202 return ret; 1203 } 1204 1205 /** 1206 * stmmac_clear_rx_descriptors - clear RX descriptors 1207 * @priv: driver private structure 1208 * @queue: RX queue index 1209 * Description: this function is called to clear the RX descriptors 1210 * in case of both basic and extended descriptors are used. 1211 */ 1212 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1213 { 1214 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1215 int i; 1216 1217 /* Clear the RX descriptors */ 1218 for (i = 0; i < priv->dma_rx_size; i++) 1219 if (priv->extend_desc) 1220 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1221 priv->use_riwt, priv->mode, 1222 (i == priv->dma_rx_size - 1), 1223 priv->dma_buf_sz); 1224 else 1225 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1226 priv->use_riwt, priv->mode, 1227 (i == priv->dma_rx_size - 1), 1228 priv->dma_buf_sz); 1229 } 1230 1231 /** 1232 * stmmac_clear_tx_descriptors - clear tx descriptors 1233 * @priv: driver private structure 1234 * @queue: TX queue index. 1235 * Description: this function is called to clear the TX descriptors 1236 * in case of both basic and extended descriptors are used. 1237 */ 1238 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1239 { 1240 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1241 int i; 1242 1243 /* Clear the TX descriptors */ 1244 for (i = 0; i < priv->dma_tx_size; i++) { 1245 int last = (i == (priv->dma_tx_size - 1)); 1246 struct dma_desc *p; 1247 1248 if (priv->extend_desc) 1249 p = &tx_q->dma_etx[i].basic; 1250 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1251 p = &tx_q->dma_entx[i].basic; 1252 else 1253 p = &tx_q->dma_tx[i]; 1254 1255 stmmac_init_tx_desc(priv, p, priv->mode, last); 1256 } 1257 } 1258 1259 /** 1260 * stmmac_clear_descriptors - clear descriptors 1261 * @priv: driver private structure 1262 * Description: this function is called to clear the TX and RX descriptors 1263 * in case of both basic and extended descriptors are used. 1264 */ 1265 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1266 { 1267 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1268 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1269 u32 queue; 1270 1271 /* Clear the RX descriptors */ 1272 for (queue = 0; queue < rx_queue_cnt; queue++) 1273 stmmac_clear_rx_descriptors(priv, queue); 1274 1275 /* Clear the TX descriptors */ 1276 for (queue = 0; queue < tx_queue_cnt; queue++) 1277 stmmac_clear_tx_descriptors(priv, queue); 1278 } 1279 1280 /** 1281 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1282 * @priv: driver private structure 1283 * @p: descriptor pointer 1284 * @i: descriptor index 1285 * @flags: gfp flag 1286 * @queue: RX queue index 1287 * Description: this function is called to allocate a receive buffer, perform 1288 * the DMA mapping and init the descriptor. 1289 */ 1290 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1291 int i, gfp_t flags, u32 queue) 1292 { 1293 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1294 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1295 1296 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1297 if (!buf->page) 1298 return -ENOMEM; 1299 1300 if (priv->sph) { 1301 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1302 if (!buf->sec_page) 1303 return -ENOMEM; 1304 1305 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1306 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1307 } else { 1308 buf->sec_page = NULL; 1309 } 1310 1311 buf->addr = page_pool_get_dma_addr(buf->page); 1312 stmmac_set_desc_addr(priv, p, buf->addr); 1313 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1314 stmmac_init_desc3(priv, p); 1315 1316 return 0; 1317 } 1318 1319 /** 1320 * stmmac_free_rx_buffer - free RX dma buffers 1321 * @priv: private structure 1322 * @queue: RX queue index 1323 * @i: buffer index. 1324 */ 1325 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1326 { 1327 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1328 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1329 1330 if (buf->page) 1331 page_pool_put_full_page(rx_q->page_pool, buf->page, false); 1332 buf->page = NULL; 1333 1334 if (buf->sec_page) 1335 page_pool_put_full_page(rx_q->page_pool, buf->sec_page, false); 1336 buf->sec_page = NULL; 1337 } 1338 1339 /** 1340 * stmmac_free_tx_buffer - free RX dma buffers 1341 * @priv: private structure 1342 * @queue: RX queue index 1343 * @i: buffer index. 1344 */ 1345 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1346 { 1347 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1348 1349 if (tx_q->tx_skbuff_dma[i].buf) { 1350 if (tx_q->tx_skbuff_dma[i].map_as_page) 1351 dma_unmap_page(priv->device, 1352 tx_q->tx_skbuff_dma[i].buf, 1353 tx_q->tx_skbuff_dma[i].len, 1354 DMA_TO_DEVICE); 1355 else 1356 dma_unmap_single(priv->device, 1357 tx_q->tx_skbuff_dma[i].buf, 1358 tx_q->tx_skbuff_dma[i].len, 1359 DMA_TO_DEVICE); 1360 } 1361 1362 if (tx_q->tx_skbuff[i]) { 1363 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1364 tx_q->tx_skbuff[i] = NULL; 1365 tx_q->tx_skbuff_dma[i].buf = 0; 1366 tx_q->tx_skbuff_dma[i].map_as_page = false; 1367 } 1368 } 1369 1370 /** 1371 * init_dma_rx_desc_rings - init the RX descriptor rings 1372 * @dev: net device structure 1373 * @flags: gfp flag. 1374 * Description: this function initializes the DMA RX descriptors 1375 * and allocates the socket buffers. It supports the chained and ring 1376 * modes. 1377 */ 1378 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1379 { 1380 struct stmmac_priv *priv = netdev_priv(dev); 1381 u32 rx_count = priv->plat->rx_queues_to_use; 1382 int ret = -ENOMEM; 1383 int queue; 1384 int i; 1385 1386 /* RX INITIALIZATION */ 1387 netif_dbg(priv, probe, priv->dev, 1388 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1389 1390 for (queue = 0; queue < rx_count; queue++) { 1391 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1392 1393 netif_dbg(priv, probe, priv->dev, 1394 "(%s) dma_rx_phy=0x%08x\n", __func__, 1395 (u32)rx_q->dma_rx_phy); 1396 1397 stmmac_clear_rx_descriptors(priv, queue); 1398 1399 for (i = 0; i < priv->dma_rx_size; i++) { 1400 struct dma_desc *p; 1401 1402 if (priv->extend_desc) 1403 p = &((rx_q->dma_erx + i)->basic); 1404 else 1405 p = rx_q->dma_rx + i; 1406 1407 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1408 queue); 1409 if (ret) 1410 goto err_init_rx_buffers; 1411 } 1412 1413 rx_q->cur_rx = 0; 1414 rx_q->dirty_rx = (unsigned int)(i - priv->dma_rx_size); 1415 1416 /* Setup the chained descriptor addresses */ 1417 if (priv->mode == STMMAC_CHAIN_MODE) { 1418 if (priv->extend_desc) 1419 stmmac_mode_init(priv, rx_q->dma_erx, 1420 rx_q->dma_rx_phy, 1421 priv->dma_rx_size, 1); 1422 else 1423 stmmac_mode_init(priv, rx_q->dma_rx, 1424 rx_q->dma_rx_phy, 1425 priv->dma_rx_size, 0); 1426 } 1427 } 1428 1429 return 0; 1430 1431 err_init_rx_buffers: 1432 while (queue >= 0) { 1433 while (--i >= 0) 1434 stmmac_free_rx_buffer(priv, queue, i); 1435 1436 if (queue == 0) 1437 break; 1438 1439 i = priv->dma_rx_size; 1440 queue--; 1441 } 1442 1443 return ret; 1444 } 1445 1446 /** 1447 * init_dma_tx_desc_rings - init the TX descriptor rings 1448 * @dev: net device structure. 1449 * Description: this function initializes the DMA TX descriptors 1450 * and allocates the socket buffers. It supports the chained and ring 1451 * modes. 1452 */ 1453 static int init_dma_tx_desc_rings(struct net_device *dev) 1454 { 1455 struct stmmac_priv *priv = netdev_priv(dev); 1456 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1457 u32 queue; 1458 int i; 1459 1460 for (queue = 0; queue < tx_queue_cnt; queue++) { 1461 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1462 1463 netif_dbg(priv, probe, priv->dev, 1464 "(%s) dma_tx_phy=0x%08x\n", __func__, 1465 (u32)tx_q->dma_tx_phy); 1466 1467 /* Setup the chained descriptor addresses */ 1468 if (priv->mode == STMMAC_CHAIN_MODE) { 1469 if (priv->extend_desc) 1470 stmmac_mode_init(priv, tx_q->dma_etx, 1471 tx_q->dma_tx_phy, 1472 priv->dma_tx_size, 1); 1473 else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) 1474 stmmac_mode_init(priv, tx_q->dma_tx, 1475 tx_q->dma_tx_phy, 1476 priv->dma_tx_size, 0); 1477 } 1478 1479 for (i = 0; i < priv->dma_tx_size; i++) { 1480 struct dma_desc *p; 1481 if (priv->extend_desc) 1482 p = &((tx_q->dma_etx + i)->basic); 1483 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1484 p = &((tx_q->dma_entx + i)->basic); 1485 else 1486 p = tx_q->dma_tx + i; 1487 1488 stmmac_clear_desc(priv, p); 1489 1490 tx_q->tx_skbuff_dma[i].buf = 0; 1491 tx_q->tx_skbuff_dma[i].map_as_page = false; 1492 tx_q->tx_skbuff_dma[i].len = 0; 1493 tx_q->tx_skbuff_dma[i].last_segment = false; 1494 tx_q->tx_skbuff[i] = NULL; 1495 } 1496 1497 tx_q->dirty_tx = 0; 1498 tx_q->cur_tx = 0; 1499 tx_q->mss = 0; 1500 1501 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1502 } 1503 1504 return 0; 1505 } 1506 1507 /** 1508 * init_dma_desc_rings - init the RX/TX descriptor rings 1509 * @dev: net device structure 1510 * @flags: gfp flag. 1511 * Description: this function initializes the DMA RX/TX descriptors 1512 * and allocates the socket buffers. It supports the chained and ring 1513 * modes. 1514 */ 1515 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1516 { 1517 struct stmmac_priv *priv = netdev_priv(dev); 1518 int ret; 1519 1520 ret = init_dma_rx_desc_rings(dev, flags); 1521 if (ret) 1522 return ret; 1523 1524 ret = init_dma_tx_desc_rings(dev); 1525 1526 stmmac_clear_descriptors(priv); 1527 1528 if (netif_msg_hw(priv)) 1529 stmmac_display_rings(priv); 1530 1531 return ret; 1532 } 1533 1534 /** 1535 * dma_free_rx_skbufs - free RX dma buffers 1536 * @priv: private structure 1537 * @queue: RX queue index 1538 */ 1539 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1540 { 1541 int i; 1542 1543 for (i = 0; i < priv->dma_rx_size; i++) 1544 stmmac_free_rx_buffer(priv, queue, i); 1545 } 1546 1547 /** 1548 * dma_free_tx_skbufs - free TX dma buffers 1549 * @priv: private structure 1550 * @queue: TX queue index 1551 */ 1552 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1553 { 1554 int i; 1555 1556 for (i = 0; i < priv->dma_tx_size; i++) 1557 stmmac_free_tx_buffer(priv, queue, i); 1558 } 1559 1560 /** 1561 * free_dma_rx_desc_resources - free RX dma desc resources 1562 * @priv: private structure 1563 */ 1564 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1565 { 1566 u32 rx_count = priv->plat->rx_queues_to_use; 1567 u32 queue; 1568 1569 /* Free RX queue resources */ 1570 for (queue = 0; queue < rx_count; queue++) { 1571 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1572 1573 /* Release the DMA RX socket buffers */ 1574 dma_free_rx_skbufs(priv, queue); 1575 1576 /* Free DMA regions of consistent memory previously allocated */ 1577 if (!priv->extend_desc) 1578 dma_free_coherent(priv->device, priv->dma_rx_size * 1579 sizeof(struct dma_desc), 1580 rx_q->dma_rx, rx_q->dma_rx_phy); 1581 else 1582 dma_free_coherent(priv->device, priv->dma_rx_size * 1583 sizeof(struct dma_extended_desc), 1584 rx_q->dma_erx, rx_q->dma_rx_phy); 1585 1586 kfree(rx_q->buf_pool); 1587 if (rx_q->page_pool) 1588 page_pool_destroy(rx_q->page_pool); 1589 } 1590 } 1591 1592 /** 1593 * free_dma_tx_desc_resources - free TX dma desc resources 1594 * @priv: private structure 1595 */ 1596 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1597 { 1598 u32 tx_count = priv->plat->tx_queues_to_use; 1599 u32 queue; 1600 1601 /* Free TX queue resources */ 1602 for (queue = 0; queue < tx_count; queue++) { 1603 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1604 size_t size; 1605 void *addr; 1606 1607 /* Release the DMA TX socket buffers */ 1608 dma_free_tx_skbufs(priv, queue); 1609 1610 if (priv->extend_desc) { 1611 size = sizeof(struct dma_extended_desc); 1612 addr = tx_q->dma_etx; 1613 } else if (tx_q->tbs & STMMAC_TBS_AVAIL) { 1614 size = sizeof(struct dma_edesc); 1615 addr = tx_q->dma_entx; 1616 } else { 1617 size = sizeof(struct dma_desc); 1618 addr = tx_q->dma_tx; 1619 } 1620 1621 size *= priv->dma_tx_size; 1622 1623 dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy); 1624 1625 kfree(tx_q->tx_skbuff_dma); 1626 kfree(tx_q->tx_skbuff); 1627 } 1628 } 1629 1630 /** 1631 * alloc_dma_rx_desc_resources - alloc RX resources. 1632 * @priv: private structure 1633 * Description: according to which descriptor can be used (extend or basic) 1634 * this function allocates the resources for TX and RX paths. In case of 1635 * reception, for example, it pre-allocated the RX socket buffer in order to 1636 * allow zero-copy mechanism. 1637 */ 1638 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1639 { 1640 u32 rx_count = priv->plat->rx_queues_to_use; 1641 int ret = -ENOMEM; 1642 u32 queue; 1643 1644 /* RX queues buffers and DMA */ 1645 for (queue = 0; queue < rx_count; queue++) { 1646 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1647 struct page_pool_params pp_params = { 0 }; 1648 unsigned int num_pages; 1649 1650 rx_q->queue_index = queue; 1651 rx_q->priv_data = priv; 1652 1653 pp_params.flags = PP_FLAG_DMA_MAP; 1654 pp_params.pool_size = priv->dma_rx_size; 1655 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1656 pp_params.order = ilog2(num_pages); 1657 pp_params.nid = dev_to_node(priv->device); 1658 pp_params.dev = priv->device; 1659 pp_params.dma_dir = DMA_FROM_DEVICE; 1660 1661 rx_q->page_pool = page_pool_create(&pp_params); 1662 if (IS_ERR(rx_q->page_pool)) { 1663 ret = PTR_ERR(rx_q->page_pool); 1664 rx_q->page_pool = NULL; 1665 goto err_dma; 1666 } 1667 1668 rx_q->buf_pool = kcalloc(priv->dma_rx_size, 1669 sizeof(*rx_q->buf_pool), 1670 GFP_KERNEL); 1671 if (!rx_q->buf_pool) 1672 goto err_dma; 1673 1674 if (priv->extend_desc) { 1675 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1676 priv->dma_rx_size * 1677 sizeof(struct dma_extended_desc), 1678 &rx_q->dma_rx_phy, 1679 GFP_KERNEL); 1680 if (!rx_q->dma_erx) 1681 goto err_dma; 1682 1683 } else { 1684 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1685 priv->dma_rx_size * 1686 sizeof(struct dma_desc), 1687 &rx_q->dma_rx_phy, 1688 GFP_KERNEL); 1689 if (!rx_q->dma_rx) 1690 goto err_dma; 1691 } 1692 } 1693 1694 return 0; 1695 1696 err_dma: 1697 free_dma_rx_desc_resources(priv); 1698 1699 return ret; 1700 } 1701 1702 /** 1703 * alloc_dma_tx_desc_resources - alloc TX resources. 1704 * @priv: private structure 1705 * Description: according to which descriptor can be used (extend or basic) 1706 * this function allocates the resources for TX and RX paths. In case of 1707 * reception, for example, it pre-allocated the RX socket buffer in order to 1708 * allow zero-copy mechanism. 1709 */ 1710 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1711 { 1712 u32 tx_count = priv->plat->tx_queues_to_use; 1713 int ret = -ENOMEM; 1714 u32 queue; 1715 1716 /* TX queues buffers and DMA */ 1717 for (queue = 0; queue < tx_count; queue++) { 1718 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1719 size_t size; 1720 void *addr; 1721 1722 tx_q->queue_index = queue; 1723 tx_q->priv_data = priv; 1724 1725 tx_q->tx_skbuff_dma = kcalloc(priv->dma_tx_size, 1726 sizeof(*tx_q->tx_skbuff_dma), 1727 GFP_KERNEL); 1728 if (!tx_q->tx_skbuff_dma) 1729 goto err_dma; 1730 1731 tx_q->tx_skbuff = kcalloc(priv->dma_tx_size, 1732 sizeof(struct sk_buff *), 1733 GFP_KERNEL); 1734 if (!tx_q->tx_skbuff) 1735 goto err_dma; 1736 1737 if (priv->extend_desc) 1738 size = sizeof(struct dma_extended_desc); 1739 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1740 size = sizeof(struct dma_edesc); 1741 else 1742 size = sizeof(struct dma_desc); 1743 1744 size *= priv->dma_tx_size; 1745 1746 addr = dma_alloc_coherent(priv->device, size, 1747 &tx_q->dma_tx_phy, GFP_KERNEL); 1748 if (!addr) 1749 goto err_dma; 1750 1751 if (priv->extend_desc) 1752 tx_q->dma_etx = addr; 1753 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1754 tx_q->dma_entx = addr; 1755 else 1756 tx_q->dma_tx = addr; 1757 } 1758 1759 return 0; 1760 1761 err_dma: 1762 free_dma_tx_desc_resources(priv); 1763 return ret; 1764 } 1765 1766 /** 1767 * alloc_dma_desc_resources - alloc TX/RX resources. 1768 * @priv: private structure 1769 * Description: according to which descriptor can be used (extend or basic) 1770 * this function allocates the resources for TX and RX paths. In case of 1771 * reception, for example, it pre-allocated the RX socket buffer in order to 1772 * allow zero-copy mechanism. 1773 */ 1774 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1775 { 1776 /* RX Allocation */ 1777 int ret = alloc_dma_rx_desc_resources(priv); 1778 1779 if (ret) 1780 return ret; 1781 1782 ret = alloc_dma_tx_desc_resources(priv); 1783 1784 return ret; 1785 } 1786 1787 /** 1788 * free_dma_desc_resources - free dma desc resources 1789 * @priv: private structure 1790 */ 1791 static void free_dma_desc_resources(struct stmmac_priv *priv) 1792 { 1793 /* Release the DMA RX socket buffers */ 1794 free_dma_rx_desc_resources(priv); 1795 1796 /* Release the DMA TX socket buffers */ 1797 free_dma_tx_desc_resources(priv); 1798 } 1799 1800 /** 1801 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1802 * @priv: driver private structure 1803 * Description: It is used for enabling the rx queues in the MAC 1804 */ 1805 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1806 { 1807 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1808 int queue; 1809 u8 mode; 1810 1811 for (queue = 0; queue < rx_queues_count; queue++) { 1812 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1813 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1814 } 1815 } 1816 1817 /** 1818 * stmmac_start_rx_dma - start RX DMA channel 1819 * @priv: driver private structure 1820 * @chan: RX channel index 1821 * Description: 1822 * This starts a RX DMA channel 1823 */ 1824 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1825 { 1826 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1827 stmmac_start_rx(priv, priv->ioaddr, chan); 1828 } 1829 1830 /** 1831 * stmmac_start_tx_dma - start TX DMA channel 1832 * @priv: driver private structure 1833 * @chan: TX channel index 1834 * Description: 1835 * This starts a TX DMA channel 1836 */ 1837 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1838 { 1839 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1840 stmmac_start_tx(priv, priv->ioaddr, chan); 1841 } 1842 1843 /** 1844 * stmmac_stop_rx_dma - stop RX DMA channel 1845 * @priv: driver private structure 1846 * @chan: RX channel index 1847 * Description: 1848 * This stops a RX DMA channel 1849 */ 1850 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1851 { 1852 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1853 stmmac_stop_rx(priv, priv->ioaddr, chan); 1854 } 1855 1856 /** 1857 * stmmac_stop_tx_dma - stop TX DMA channel 1858 * @priv: driver private structure 1859 * @chan: TX channel index 1860 * Description: 1861 * This stops a TX DMA channel 1862 */ 1863 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1864 { 1865 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1866 stmmac_stop_tx(priv, priv->ioaddr, chan); 1867 } 1868 1869 /** 1870 * stmmac_start_all_dma - start all RX and TX DMA channels 1871 * @priv: driver private structure 1872 * Description: 1873 * This starts all the RX and TX DMA channels 1874 */ 1875 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1876 { 1877 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1878 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1879 u32 chan = 0; 1880 1881 for (chan = 0; chan < rx_channels_count; chan++) 1882 stmmac_start_rx_dma(priv, chan); 1883 1884 for (chan = 0; chan < tx_channels_count; chan++) 1885 stmmac_start_tx_dma(priv, chan); 1886 } 1887 1888 /** 1889 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1890 * @priv: driver private structure 1891 * Description: 1892 * This stops the RX and TX DMA channels 1893 */ 1894 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1895 { 1896 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1897 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1898 u32 chan = 0; 1899 1900 for (chan = 0; chan < rx_channels_count; chan++) 1901 stmmac_stop_rx_dma(priv, chan); 1902 1903 for (chan = 0; chan < tx_channels_count; chan++) 1904 stmmac_stop_tx_dma(priv, chan); 1905 } 1906 1907 /** 1908 * stmmac_dma_operation_mode - HW DMA operation mode 1909 * @priv: driver private structure 1910 * Description: it is used for configuring the DMA operation mode register in 1911 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1912 */ 1913 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1914 { 1915 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1916 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1917 int rxfifosz = priv->plat->rx_fifo_size; 1918 int txfifosz = priv->plat->tx_fifo_size; 1919 u32 txmode = 0; 1920 u32 rxmode = 0; 1921 u32 chan = 0; 1922 u8 qmode = 0; 1923 1924 if (rxfifosz == 0) 1925 rxfifosz = priv->dma_cap.rx_fifo_size; 1926 if (txfifosz == 0) 1927 txfifosz = priv->dma_cap.tx_fifo_size; 1928 1929 /* Adjust for real per queue fifo size */ 1930 rxfifosz /= rx_channels_count; 1931 txfifosz /= tx_channels_count; 1932 1933 if (priv->plat->force_thresh_dma_mode) { 1934 txmode = tc; 1935 rxmode = tc; 1936 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1937 /* 1938 * In case of GMAC, SF mode can be enabled 1939 * to perform the TX COE in HW. This depends on: 1940 * 1) TX COE if actually supported 1941 * 2) There is no bugged Jumbo frame support 1942 * that needs to not insert csum in the TDES. 1943 */ 1944 txmode = SF_DMA_MODE; 1945 rxmode = SF_DMA_MODE; 1946 priv->xstats.threshold = SF_DMA_MODE; 1947 } else { 1948 txmode = tc; 1949 rxmode = SF_DMA_MODE; 1950 } 1951 1952 /* configure all channels */ 1953 for (chan = 0; chan < rx_channels_count; chan++) { 1954 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1955 1956 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1957 rxfifosz, qmode); 1958 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1959 chan); 1960 } 1961 1962 for (chan = 0; chan < tx_channels_count; chan++) { 1963 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1964 1965 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1966 txfifosz, qmode); 1967 } 1968 } 1969 1970 /** 1971 * stmmac_tx_clean - to manage the transmission completion 1972 * @priv: driver private structure 1973 * @budget: napi budget limiting this functions packet handling 1974 * @queue: TX queue index 1975 * Description: it reclaims the transmit resources after transmission completes. 1976 */ 1977 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1978 { 1979 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1980 unsigned int bytes_compl = 0, pkts_compl = 0; 1981 unsigned int entry, count = 0; 1982 1983 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1984 1985 priv->xstats.tx_clean++; 1986 1987 entry = tx_q->dirty_tx; 1988 while ((entry != tx_q->cur_tx) && (count < budget)) { 1989 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1990 struct dma_desc *p; 1991 int status; 1992 1993 if (priv->extend_desc) 1994 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1995 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 1996 p = &tx_q->dma_entx[entry].basic; 1997 else 1998 p = tx_q->dma_tx + entry; 1999 2000 status = stmmac_tx_status(priv, &priv->dev->stats, 2001 &priv->xstats, p, priv->ioaddr); 2002 /* Check if the descriptor is owned by the DMA */ 2003 if (unlikely(status & tx_dma_own)) 2004 break; 2005 2006 count++; 2007 2008 /* Make sure descriptor fields are read after reading 2009 * the own bit. 2010 */ 2011 dma_rmb(); 2012 2013 /* Just consider the last segment and ...*/ 2014 if (likely(!(status & tx_not_ls))) { 2015 /* ... verify the status error condition */ 2016 if (unlikely(status & tx_err)) { 2017 priv->dev->stats.tx_errors++; 2018 } else { 2019 priv->dev->stats.tx_packets++; 2020 priv->xstats.tx_pkt_n++; 2021 } 2022 stmmac_get_tx_hwtstamp(priv, p, skb); 2023 } 2024 2025 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 2026 if (tx_q->tx_skbuff_dma[entry].map_as_page) 2027 dma_unmap_page(priv->device, 2028 tx_q->tx_skbuff_dma[entry].buf, 2029 tx_q->tx_skbuff_dma[entry].len, 2030 DMA_TO_DEVICE); 2031 else 2032 dma_unmap_single(priv->device, 2033 tx_q->tx_skbuff_dma[entry].buf, 2034 tx_q->tx_skbuff_dma[entry].len, 2035 DMA_TO_DEVICE); 2036 tx_q->tx_skbuff_dma[entry].buf = 0; 2037 tx_q->tx_skbuff_dma[entry].len = 0; 2038 tx_q->tx_skbuff_dma[entry].map_as_page = false; 2039 } 2040 2041 stmmac_clean_desc3(priv, tx_q, p); 2042 2043 tx_q->tx_skbuff_dma[entry].last_segment = false; 2044 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 2045 2046 if (likely(skb != NULL)) { 2047 pkts_compl++; 2048 bytes_compl += skb->len; 2049 dev_consume_skb_any(skb); 2050 tx_q->tx_skbuff[entry] = NULL; 2051 } 2052 2053 stmmac_release_tx_desc(priv, p, priv->mode); 2054 2055 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 2056 } 2057 tx_q->dirty_tx = entry; 2058 2059 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 2060 pkts_compl, bytes_compl); 2061 2062 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 2063 queue))) && 2064 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH(priv)) { 2065 2066 netif_dbg(priv, tx_done, priv->dev, 2067 "%s: restart transmit\n", __func__); 2068 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 2069 } 2070 2071 if (priv->eee_enabled && !priv->tx_path_in_lpi_mode && 2072 priv->eee_sw_timer_en) { 2073 stmmac_enable_eee_mode(priv); 2074 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(priv->tx_lpi_timer)); 2075 } 2076 2077 /* We still have pending packets, let's call for a new scheduling */ 2078 if (tx_q->dirty_tx != tx_q->cur_tx) 2079 hrtimer_start(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer), 2080 HRTIMER_MODE_REL); 2081 2082 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 2083 2084 return count; 2085 } 2086 2087 /** 2088 * stmmac_tx_err - to manage the tx error 2089 * @priv: driver private structure 2090 * @chan: channel index 2091 * Description: it cleans the descriptors and restarts the transmission 2092 * in case of transmission errors. 2093 */ 2094 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 2095 { 2096 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2097 2098 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 2099 2100 stmmac_stop_tx_dma(priv, chan); 2101 dma_free_tx_skbufs(priv, chan); 2102 stmmac_clear_tx_descriptors(priv, chan); 2103 tx_q->dirty_tx = 0; 2104 tx_q->cur_tx = 0; 2105 tx_q->mss = 0; 2106 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2107 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2108 tx_q->dma_tx_phy, chan); 2109 stmmac_start_tx_dma(priv, chan); 2110 2111 priv->dev->stats.tx_errors++; 2112 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2113 } 2114 2115 /** 2116 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2117 * @priv: driver private structure 2118 * @txmode: TX operating mode 2119 * @rxmode: RX operating mode 2120 * @chan: channel index 2121 * Description: it is used for configuring of the DMA operation mode in 2122 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2123 * mode. 2124 */ 2125 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2126 u32 rxmode, u32 chan) 2127 { 2128 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2129 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2130 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2131 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2132 int rxfifosz = priv->plat->rx_fifo_size; 2133 int txfifosz = priv->plat->tx_fifo_size; 2134 2135 if (rxfifosz == 0) 2136 rxfifosz = priv->dma_cap.rx_fifo_size; 2137 if (txfifosz == 0) 2138 txfifosz = priv->dma_cap.tx_fifo_size; 2139 2140 /* Adjust for real per queue fifo size */ 2141 rxfifosz /= rx_channels_count; 2142 txfifosz /= tx_channels_count; 2143 2144 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2145 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2146 } 2147 2148 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2149 { 2150 int ret; 2151 2152 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2153 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2154 if (ret && (ret != -EINVAL)) { 2155 stmmac_global_err(priv); 2156 return true; 2157 } 2158 2159 return false; 2160 } 2161 2162 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2163 { 2164 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2165 &priv->xstats, chan); 2166 struct stmmac_channel *ch = &priv->channel[chan]; 2167 unsigned long flags; 2168 2169 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2170 if (napi_schedule_prep(&ch->rx_napi)) { 2171 spin_lock_irqsave(&ch->lock, flags); 2172 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 2173 spin_unlock_irqrestore(&ch->lock, flags); 2174 __napi_schedule_irqoff(&ch->rx_napi); 2175 } 2176 } 2177 2178 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) { 2179 if (napi_schedule_prep(&ch->tx_napi)) { 2180 spin_lock_irqsave(&ch->lock, flags); 2181 stmmac_disable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 2182 spin_unlock_irqrestore(&ch->lock, flags); 2183 __napi_schedule_irqoff(&ch->tx_napi); 2184 } 2185 } 2186 2187 return status; 2188 } 2189 2190 /** 2191 * stmmac_dma_interrupt - DMA ISR 2192 * @priv: driver private structure 2193 * Description: this is the DMA ISR. It is called by the main ISR. 2194 * It calls the dwmac dma routine and schedule poll method in case of some 2195 * work can be done. 2196 */ 2197 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2198 { 2199 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2200 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2201 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2202 tx_channel_count : rx_channel_count; 2203 u32 chan; 2204 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2205 2206 /* Make sure we never check beyond our status buffer. */ 2207 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2208 channels_to_check = ARRAY_SIZE(status); 2209 2210 for (chan = 0; chan < channels_to_check; chan++) 2211 status[chan] = stmmac_napi_check(priv, chan); 2212 2213 for (chan = 0; chan < tx_channel_count; chan++) { 2214 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2215 /* Try to bump up the dma threshold on this failure */ 2216 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2217 (tc <= 256)) { 2218 tc += 64; 2219 if (priv->plat->force_thresh_dma_mode) 2220 stmmac_set_dma_operation_mode(priv, 2221 tc, 2222 tc, 2223 chan); 2224 else 2225 stmmac_set_dma_operation_mode(priv, 2226 tc, 2227 SF_DMA_MODE, 2228 chan); 2229 priv->xstats.threshold = tc; 2230 } 2231 } else if (unlikely(status[chan] == tx_hard_error)) { 2232 stmmac_tx_err(priv, chan); 2233 } 2234 } 2235 } 2236 2237 /** 2238 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2239 * @priv: driver private structure 2240 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2241 */ 2242 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2243 { 2244 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2245 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2246 2247 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2248 2249 if (priv->dma_cap.rmon) { 2250 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2251 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2252 } else 2253 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2254 } 2255 2256 /** 2257 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2258 * @priv: driver private structure 2259 * Description: 2260 * new GMAC chip generations have a new register to indicate the 2261 * presence of the optional feature/functions. 2262 * This can be also used to override the value passed through the 2263 * platform and necessary for old MAC10/100 and GMAC chips. 2264 */ 2265 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2266 { 2267 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2268 } 2269 2270 /** 2271 * stmmac_check_ether_addr - check if the MAC addr is valid 2272 * @priv: driver private structure 2273 * Description: 2274 * it is to verify if the MAC address is valid, in case of failures it 2275 * generates a random MAC address 2276 */ 2277 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2278 { 2279 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2280 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2281 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2282 eth_hw_addr_random(priv->dev); 2283 dev_info(priv->device, "device MAC address %pM\n", 2284 priv->dev->dev_addr); 2285 } 2286 } 2287 2288 /** 2289 * stmmac_init_dma_engine - DMA init. 2290 * @priv: driver private structure 2291 * Description: 2292 * It inits the DMA invoking the specific MAC/GMAC callback. 2293 * Some DMA parameters can be passed from the platform; 2294 * in case of these are not passed a default is kept for the MAC or GMAC. 2295 */ 2296 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2297 { 2298 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2299 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2300 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2301 struct stmmac_rx_queue *rx_q; 2302 struct stmmac_tx_queue *tx_q; 2303 u32 chan = 0; 2304 int atds = 0; 2305 int ret = 0; 2306 2307 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2308 dev_err(priv->device, "Invalid DMA configuration\n"); 2309 return -EINVAL; 2310 } 2311 2312 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2313 atds = 1; 2314 2315 ret = stmmac_reset(priv, priv->ioaddr); 2316 if (ret) { 2317 dev_err(priv->device, "Failed to reset the dma\n"); 2318 return ret; 2319 } 2320 2321 /* DMA Configuration */ 2322 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2323 2324 if (priv->plat->axi) 2325 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2326 2327 /* DMA CSR Channel configuration */ 2328 for (chan = 0; chan < dma_csr_ch; chan++) 2329 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2330 2331 /* DMA RX Channel Configuration */ 2332 for (chan = 0; chan < rx_channels_count; chan++) { 2333 rx_q = &priv->rx_queue[chan]; 2334 2335 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2336 rx_q->dma_rx_phy, chan); 2337 2338 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2339 (priv->dma_rx_size * 2340 sizeof(struct dma_desc)); 2341 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2342 rx_q->rx_tail_addr, chan); 2343 } 2344 2345 /* DMA TX Channel Configuration */ 2346 for (chan = 0; chan < tx_channels_count; chan++) { 2347 tx_q = &priv->tx_queue[chan]; 2348 2349 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2350 tx_q->dma_tx_phy, chan); 2351 2352 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2353 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2354 tx_q->tx_tail_addr, chan); 2355 } 2356 2357 return ret; 2358 } 2359 2360 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2361 { 2362 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2363 2364 hrtimer_start(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer), 2365 HRTIMER_MODE_REL); 2366 } 2367 2368 /** 2369 * stmmac_tx_timer - mitigation sw timer for tx. 2370 * @t: data pointer 2371 * Description: 2372 * This is the timer handler to directly invoke the stmmac_tx_clean. 2373 */ 2374 static enum hrtimer_restart stmmac_tx_timer(struct hrtimer *t) 2375 { 2376 struct stmmac_tx_queue *tx_q = container_of(t, struct stmmac_tx_queue, txtimer); 2377 struct stmmac_priv *priv = tx_q->priv_data; 2378 struct stmmac_channel *ch; 2379 2380 ch = &priv->channel[tx_q->queue_index]; 2381 2382 if (likely(napi_schedule_prep(&ch->tx_napi))) { 2383 unsigned long flags; 2384 2385 spin_lock_irqsave(&ch->lock, flags); 2386 stmmac_disable_dma_irq(priv, priv->ioaddr, ch->index, 0, 1); 2387 spin_unlock_irqrestore(&ch->lock, flags); 2388 __napi_schedule(&ch->tx_napi); 2389 } 2390 2391 return HRTIMER_NORESTART; 2392 } 2393 2394 /** 2395 * stmmac_init_coalesce - init mitigation options. 2396 * @priv: driver private structure 2397 * Description: 2398 * This inits the coalesce parameters: i.e. timer rate, 2399 * timer handler and default threshold used for enabling the 2400 * interrupt on completion bit. 2401 */ 2402 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2403 { 2404 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2405 u32 chan; 2406 2407 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2408 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2409 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2410 2411 for (chan = 0; chan < tx_channel_count; chan++) { 2412 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2413 2414 hrtimer_init(&tx_q->txtimer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); 2415 tx_q->txtimer.function = stmmac_tx_timer; 2416 } 2417 } 2418 2419 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2420 { 2421 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2422 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2423 u32 chan; 2424 2425 /* set TX ring length */ 2426 for (chan = 0; chan < tx_channels_count; chan++) 2427 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2428 (priv->dma_tx_size - 1), chan); 2429 2430 /* set RX ring length */ 2431 for (chan = 0; chan < rx_channels_count; chan++) 2432 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2433 (priv->dma_rx_size - 1), chan); 2434 } 2435 2436 /** 2437 * stmmac_set_tx_queue_weight - Set TX queue weight 2438 * @priv: driver private structure 2439 * Description: It is used for setting TX queues weight 2440 */ 2441 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2442 { 2443 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2444 u32 weight; 2445 u32 queue; 2446 2447 for (queue = 0; queue < tx_queues_count; queue++) { 2448 weight = priv->plat->tx_queues_cfg[queue].weight; 2449 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2450 } 2451 } 2452 2453 /** 2454 * stmmac_configure_cbs - Configure CBS in TX queue 2455 * @priv: driver private structure 2456 * Description: It is used for configuring CBS in AVB TX queues 2457 */ 2458 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2459 { 2460 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2461 u32 mode_to_use; 2462 u32 queue; 2463 2464 /* queue 0 is reserved for legacy traffic */ 2465 for (queue = 1; queue < tx_queues_count; queue++) { 2466 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2467 if (mode_to_use == MTL_QUEUE_DCB) 2468 continue; 2469 2470 stmmac_config_cbs(priv, priv->hw, 2471 priv->plat->tx_queues_cfg[queue].send_slope, 2472 priv->plat->tx_queues_cfg[queue].idle_slope, 2473 priv->plat->tx_queues_cfg[queue].high_credit, 2474 priv->plat->tx_queues_cfg[queue].low_credit, 2475 queue); 2476 } 2477 } 2478 2479 /** 2480 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2481 * @priv: driver private structure 2482 * Description: It is used for mapping RX queues to RX dma channels 2483 */ 2484 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2485 { 2486 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2487 u32 queue; 2488 u32 chan; 2489 2490 for (queue = 0; queue < rx_queues_count; queue++) { 2491 chan = priv->plat->rx_queues_cfg[queue].chan; 2492 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2493 } 2494 } 2495 2496 /** 2497 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2498 * @priv: driver private structure 2499 * Description: It is used for configuring the RX Queue Priority 2500 */ 2501 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2502 { 2503 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2504 u32 queue; 2505 u32 prio; 2506 2507 for (queue = 0; queue < rx_queues_count; queue++) { 2508 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2509 continue; 2510 2511 prio = priv->plat->rx_queues_cfg[queue].prio; 2512 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2513 } 2514 } 2515 2516 /** 2517 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2518 * @priv: driver private structure 2519 * Description: It is used for configuring the TX Queue Priority 2520 */ 2521 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2522 { 2523 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2524 u32 queue; 2525 u32 prio; 2526 2527 for (queue = 0; queue < tx_queues_count; queue++) { 2528 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2529 continue; 2530 2531 prio = priv->plat->tx_queues_cfg[queue].prio; 2532 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2533 } 2534 } 2535 2536 /** 2537 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2538 * @priv: driver private structure 2539 * Description: It is used for configuring the RX queue routing 2540 */ 2541 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2542 { 2543 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2544 u32 queue; 2545 u8 packet; 2546 2547 for (queue = 0; queue < rx_queues_count; queue++) { 2548 /* no specific packet type routing specified for the queue */ 2549 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2550 continue; 2551 2552 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2553 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2554 } 2555 } 2556 2557 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2558 { 2559 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2560 priv->rss.enable = false; 2561 return; 2562 } 2563 2564 if (priv->dev->features & NETIF_F_RXHASH) 2565 priv->rss.enable = true; 2566 else 2567 priv->rss.enable = false; 2568 2569 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2570 priv->plat->rx_queues_to_use); 2571 } 2572 2573 /** 2574 * stmmac_mtl_configuration - Configure MTL 2575 * @priv: driver private structure 2576 * Description: It is used for configurring MTL 2577 */ 2578 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2579 { 2580 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2581 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2582 2583 if (tx_queues_count > 1) 2584 stmmac_set_tx_queue_weight(priv); 2585 2586 /* Configure MTL RX algorithms */ 2587 if (rx_queues_count > 1) 2588 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2589 priv->plat->rx_sched_algorithm); 2590 2591 /* Configure MTL TX algorithms */ 2592 if (tx_queues_count > 1) 2593 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2594 priv->plat->tx_sched_algorithm); 2595 2596 /* Configure CBS in AVB TX queues */ 2597 if (tx_queues_count > 1) 2598 stmmac_configure_cbs(priv); 2599 2600 /* Map RX MTL to DMA channels */ 2601 stmmac_rx_queue_dma_chan_map(priv); 2602 2603 /* Enable MAC RX Queues */ 2604 stmmac_mac_enable_rx_queues(priv); 2605 2606 /* Set RX priorities */ 2607 if (rx_queues_count > 1) 2608 stmmac_mac_config_rx_queues_prio(priv); 2609 2610 /* Set TX priorities */ 2611 if (tx_queues_count > 1) 2612 stmmac_mac_config_tx_queues_prio(priv); 2613 2614 /* Set RX routing */ 2615 if (rx_queues_count > 1) 2616 stmmac_mac_config_rx_queues_routing(priv); 2617 2618 /* Receive Side Scaling */ 2619 if (rx_queues_count > 1) 2620 stmmac_mac_config_rss(priv); 2621 } 2622 2623 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2624 { 2625 if (priv->dma_cap.asp) { 2626 netdev_info(priv->dev, "Enabling Safety Features\n"); 2627 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2628 } else { 2629 netdev_info(priv->dev, "No Safety Features support found\n"); 2630 } 2631 } 2632 2633 /** 2634 * stmmac_hw_setup - setup mac in a usable state. 2635 * @dev : pointer to the device structure. 2636 * @init_ptp: initialize PTP if set 2637 * Description: 2638 * this is the main function to setup the HW in a usable state because the 2639 * dma engine is reset, the core registers are configured (e.g. AXI, 2640 * Checksum features, timers). The DMA is ready to start receiving and 2641 * transmitting. 2642 * Return value: 2643 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2644 * file on failure. 2645 */ 2646 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2647 { 2648 struct stmmac_priv *priv = netdev_priv(dev); 2649 u32 rx_cnt = priv->plat->rx_queues_to_use; 2650 u32 tx_cnt = priv->plat->tx_queues_to_use; 2651 u32 chan; 2652 int ret; 2653 2654 /* DMA initialization and SW reset */ 2655 ret = stmmac_init_dma_engine(priv); 2656 if (ret < 0) { 2657 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2658 __func__); 2659 return ret; 2660 } 2661 2662 /* Copy the MAC addr into the HW */ 2663 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2664 2665 /* PS and related bits will be programmed according to the speed */ 2666 if (priv->hw->pcs) { 2667 int speed = priv->plat->mac_port_sel_speed; 2668 2669 if ((speed == SPEED_10) || (speed == SPEED_100) || 2670 (speed == SPEED_1000)) { 2671 priv->hw->ps = speed; 2672 } else { 2673 dev_warn(priv->device, "invalid port speed\n"); 2674 priv->hw->ps = 0; 2675 } 2676 } 2677 2678 /* Initialize the MAC Core */ 2679 stmmac_core_init(priv, priv->hw, dev); 2680 2681 /* Initialize MTL*/ 2682 stmmac_mtl_configuration(priv); 2683 2684 /* Initialize Safety Features */ 2685 stmmac_safety_feat_configuration(priv); 2686 2687 ret = stmmac_rx_ipc(priv, priv->hw); 2688 if (!ret) { 2689 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2690 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2691 priv->hw->rx_csum = 0; 2692 } 2693 2694 /* Enable the MAC Rx/Tx */ 2695 stmmac_mac_set(priv, priv->ioaddr, true); 2696 2697 /* Set the HW DMA mode and the COE */ 2698 stmmac_dma_operation_mode(priv); 2699 2700 stmmac_mmc_setup(priv); 2701 2702 if (init_ptp) { 2703 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2704 if (ret < 0) 2705 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2706 2707 ret = stmmac_init_ptp(priv); 2708 if (ret == -EOPNOTSUPP) 2709 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2710 else if (ret) 2711 netdev_warn(priv->dev, "PTP init failed\n"); 2712 } 2713 2714 priv->eee_tw_timer = STMMAC_DEFAULT_TWT_LS; 2715 2716 /* Convert the timer from msec to usec */ 2717 if (!priv->tx_lpi_timer) 2718 priv->tx_lpi_timer = eee_timer * 1000; 2719 2720 if (priv->use_riwt) { 2721 if (!priv->rx_riwt) 2722 priv->rx_riwt = DEF_DMA_RIWT; 2723 2724 ret = stmmac_rx_watchdog(priv, priv->ioaddr, priv->rx_riwt, rx_cnt); 2725 } 2726 2727 if (priv->hw->pcs) 2728 stmmac_pcs_ctrl_ane(priv, priv->ioaddr, 1, priv->hw->ps, 0); 2729 2730 /* set TX and RX rings length */ 2731 stmmac_set_rings_length(priv); 2732 2733 /* Enable TSO */ 2734 if (priv->tso) { 2735 for (chan = 0; chan < tx_cnt; chan++) 2736 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2737 } 2738 2739 /* Enable Split Header */ 2740 if (priv->sph && priv->hw->rx_csum) { 2741 for (chan = 0; chan < rx_cnt; chan++) 2742 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2743 } 2744 2745 /* VLAN Tag Insertion */ 2746 if (priv->dma_cap.vlins) 2747 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2748 2749 /* TBS */ 2750 for (chan = 0; chan < tx_cnt; chan++) { 2751 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2752 int enable = tx_q->tbs & STMMAC_TBS_AVAIL; 2753 2754 stmmac_enable_tbs(priv, priv->ioaddr, enable, chan); 2755 } 2756 2757 /* Configure real RX and TX queues */ 2758 netif_set_real_num_rx_queues(dev, priv->plat->rx_queues_to_use); 2759 netif_set_real_num_tx_queues(dev, priv->plat->tx_queues_to_use); 2760 2761 /* Start the ball rolling... */ 2762 stmmac_start_all_dma(priv); 2763 2764 return 0; 2765 } 2766 2767 static void stmmac_hw_teardown(struct net_device *dev) 2768 { 2769 struct stmmac_priv *priv = netdev_priv(dev); 2770 2771 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2772 } 2773 2774 /** 2775 * stmmac_open - open entry point of the driver 2776 * @dev : pointer to the device structure. 2777 * Description: 2778 * This function is the open entry point of the driver. 2779 * Return value: 2780 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2781 * file on failure. 2782 */ 2783 static int stmmac_open(struct net_device *dev) 2784 { 2785 struct stmmac_priv *priv = netdev_priv(dev); 2786 int bfsize = 0; 2787 u32 chan; 2788 int ret; 2789 2790 if (priv->hw->pcs != STMMAC_PCS_TBI && 2791 priv->hw->pcs != STMMAC_PCS_RTBI && 2792 priv->hw->xpcs == NULL) { 2793 ret = stmmac_init_phy(dev); 2794 if (ret) { 2795 netdev_err(priv->dev, 2796 "%s: Cannot attach to PHY (error: %d)\n", 2797 __func__, ret); 2798 return ret; 2799 } 2800 } 2801 2802 /* Extra statistics */ 2803 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2804 priv->xstats.threshold = tc; 2805 2806 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 2807 if (bfsize < 0) 2808 bfsize = 0; 2809 2810 if (bfsize < BUF_SIZE_16KiB) 2811 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 2812 2813 priv->dma_buf_sz = bfsize; 2814 buf_sz = bfsize; 2815 2816 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2817 2818 if (!priv->dma_tx_size) 2819 priv->dma_tx_size = DMA_DEFAULT_TX_SIZE; 2820 if (!priv->dma_rx_size) 2821 priv->dma_rx_size = DMA_DEFAULT_RX_SIZE; 2822 2823 /* Earlier check for TBS */ 2824 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) { 2825 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2826 int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en; 2827 2828 tx_q->tbs |= tbs_en ? STMMAC_TBS_AVAIL : 0; 2829 if (stmmac_enable_tbs(priv, priv->ioaddr, tbs_en, chan)) 2830 tx_q->tbs &= ~STMMAC_TBS_AVAIL; 2831 } 2832 2833 ret = alloc_dma_desc_resources(priv); 2834 if (ret < 0) { 2835 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2836 __func__); 2837 goto dma_desc_error; 2838 } 2839 2840 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2841 if (ret < 0) { 2842 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2843 __func__); 2844 goto init_error; 2845 } 2846 2847 ret = stmmac_hw_setup(dev, true); 2848 if (ret < 0) { 2849 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2850 goto init_error; 2851 } 2852 2853 stmmac_init_coalesce(priv); 2854 2855 phylink_start(priv->phylink); 2856 /* We may have called phylink_speed_down before */ 2857 phylink_speed_up(priv->phylink); 2858 2859 /* Request the IRQ lines */ 2860 ret = request_irq(dev->irq, stmmac_interrupt, 2861 IRQF_SHARED, dev->name, dev); 2862 if (unlikely(ret < 0)) { 2863 netdev_err(priv->dev, 2864 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2865 __func__, dev->irq, ret); 2866 goto irq_error; 2867 } 2868 2869 /* Request the Wake IRQ in case of another line is used for WoL */ 2870 if (priv->wol_irq != dev->irq) { 2871 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2872 IRQF_SHARED, dev->name, dev); 2873 if (unlikely(ret < 0)) { 2874 netdev_err(priv->dev, 2875 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2876 __func__, priv->wol_irq, ret); 2877 goto wolirq_error; 2878 } 2879 } 2880 2881 /* Request the IRQ lines */ 2882 if (priv->lpi_irq > 0) { 2883 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2884 dev->name, dev); 2885 if (unlikely(ret < 0)) { 2886 netdev_err(priv->dev, 2887 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2888 __func__, priv->lpi_irq, ret); 2889 goto lpiirq_error; 2890 } 2891 } 2892 2893 stmmac_enable_all_queues(priv); 2894 netif_tx_start_all_queues(priv->dev); 2895 2896 return 0; 2897 2898 lpiirq_error: 2899 if (priv->wol_irq != dev->irq) 2900 free_irq(priv->wol_irq, dev); 2901 wolirq_error: 2902 free_irq(dev->irq, dev); 2903 irq_error: 2904 phylink_stop(priv->phylink); 2905 2906 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2907 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 2908 2909 stmmac_hw_teardown(dev); 2910 init_error: 2911 free_dma_desc_resources(priv); 2912 dma_desc_error: 2913 phylink_disconnect_phy(priv->phylink); 2914 return ret; 2915 } 2916 2917 /** 2918 * stmmac_release - close entry point of the driver 2919 * @dev : device pointer. 2920 * Description: 2921 * This is the stop entry point of the driver. 2922 */ 2923 static int stmmac_release(struct net_device *dev) 2924 { 2925 struct stmmac_priv *priv = netdev_priv(dev); 2926 u32 chan; 2927 2928 if (priv->eee_enabled) 2929 del_timer_sync(&priv->eee_ctrl_timer); 2930 2931 if (device_may_wakeup(priv->device)) 2932 phylink_speed_down(priv->phylink, false); 2933 /* Stop and disconnect the PHY */ 2934 phylink_stop(priv->phylink); 2935 phylink_disconnect_phy(priv->phylink); 2936 2937 stmmac_disable_all_queues(priv); 2938 2939 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2940 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 2941 2942 /* Free the IRQ lines */ 2943 free_irq(dev->irq, dev); 2944 if (priv->wol_irq != dev->irq) 2945 free_irq(priv->wol_irq, dev); 2946 if (priv->lpi_irq > 0) 2947 free_irq(priv->lpi_irq, dev); 2948 2949 /* Stop TX/RX DMA and clear the descriptors */ 2950 stmmac_stop_all_dma(priv); 2951 2952 /* Release and free the Rx/Tx resources */ 2953 free_dma_desc_resources(priv); 2954 2955 /* Disable the MAC Rx/Tx */ 2956 stmmac_mac_set(priv, priv->ioaddr, false); 2957 2958 netif_carrier_off(dev); 2959 2960 stmmac_release_ptp(priv); 2961 2962 return 0; 2963 } 2964 2965 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2966 struct stmmac_tx_queue *tx_q) 2967 { 2968 u16 tag = 0x0, inner_tag = 0x0; 2969 u32 inner_type = 0x0; 2970 struct dma_desc *p; 2971 2972 if (!priv->dma_cap.vlins) 2973 return false; 2974 if (!skb_vlan_tag_present(skb)) 2975 return false; 2976 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2977 inner_tag = skb_vlan_tag_get(skb); 2978 inner_type = STMMAC_VLAN_INSERT; 2979 } 2980 2981 tag = skb_vlan_tag_get(skb); 2982 2983 if (tx_q->tbs & STMMAC_TBS_AVAIL) 2984 p = &tx_q->dma_entx[tx_q->cur_tx].basic; 2985 else 2986 p = &tx_q->dma_tx[tx_q->cur_tx]; 2987 2988 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2989 return false; 2990 2991 stmmac_set_tx_owner(priv, p); 2992 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 2993 return true; 2994 } 2995 2996 /** 2997 * stmmac_tso_allocator - close entry point of the driver 2998 * @priv: driver private structure 2999 * @des: buffer start address 3000 * @total_len: total length to fill in descriptors 3001 * @last_segment: condition for the last descriptor 3002 * @queue: TX queue index 3003 * Description: 3004 * This function fills descriptor and request new descriptors according to 3005 * buffer length to fill 3006 */ 3007 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 3008 int total_len, bool last_segment, u32 queue) 3009 { 3010 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 3011 struct dma_desc *desc; 3012 u32 buff_size; 3013 int tmp_len; 3014 3015 tmp_len = total_len; 3016 3017 while (tmp_len > 0) { 3018 dma_addr_t curr_addr; 3019 3020 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3021 priv->dma_tx_size); 3022 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3023 3024 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3025 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3026 else 3027 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3028 3029 curr_addr = des + (total_len - tmp_len); 3030 if (priv->dma_cap.addr64 <= 32) 3031 desc->des0 = cpu_to_le32(curr_addr); 3032 else 3033 stmmac_set_desc_addr(priv, desc, curr_addr); 3034 3035 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 3036 TSO_MAX_BUFF_SIZE : tmp_len; 3037 3038 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 3039 0, 1, 3040 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 3041 0, 0); 3042 3043 tmp_len -= TSO_MAX_BUFF_SIZE; 3044 } 3045 } 3046 3047 /** 3048 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 3049 * @skb : the socket buffer 3050 * @dev : device pointer 3051 * Description: this is the transmit function that is called on TSO frames 3052 * (support available on GMAC4 and newer chips). 3053 * Diagram below show the ring programming in case of TSO frames: 3054 * 3055 * First Descriptor 3056 * -------- 3057 * | DES0 |---> buffer1 = L2/L3/L4 header 3058 * | DES1 |---> TCP Payload (can continue on next descr...) 3059 * | DES2 |---> buffer 1 and 2 len 3060 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 3061 * -------- 3062 * | 3063 * ... 3064 * | 3065 * -------- 3066 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 3067 * | DES1 | --| 3068 * | DES2 | --> buffer 1 and 2 len 3069 * | DES3 | 3070 * -------- 3071 * 3072 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 3073 */ 3074 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 3075 { 3076 struct dma_desc *desc, *first, *mss_desc = NULL; 3077 struct stmmac_priv *priv = netdev_priv(dev); 3078 int desc_size, tmp_pay_len = 0, first_tx; 3079 int nfrags = skb_shinfo(skb)->nr_frags; 3080 u32 queue = skb_get_queue_mapping(skb); 3081 unsigned int first_entry, tx_packets; 3082 struct stmmac_tx_queue *tx_q; 3083 bool has_vlan, set_ic; 3084 u8 proto_hdr_len, hdr; 3085 u32 pay_len, mss; 3086 dma_addr_t des; 3087 int i; 3088 3089 tx_q = &priv->tx_queue[queue]; 3090 first_tx = tx_q->cur_tx; 3091 3092 /* Compute header lengths */ 3093 if (skb_shinfo(skb)->gso_type & SKB_GSO_UDP_L4) { 3094 proto_hdr_len = skb_transport_offset(skb) + sizeof(struct udphdr); 3095 hdr = sizeof(struct udphdr); 3096 } else { 3097 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 3098 hdr = tcp_hdrlen(skb); 3099 } 3100 3101 /* Desc availability based on threshold should be enough safe */ 3102 if (unlikely(stmmac_tx_avail(priv, queue) < 3103 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 3104 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3105 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3106 queue)); 3107 /* This is a hard error, log it. */ 3108 netdev_err(priv->dev, 3109 "%s: Tx Ring full when queue awake\n", 3110 __func__); 3111 } 3112 return NETDEV_TX_BUSY; 3113 } 3114 3115 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 3116 3117 mss = skb_shinfo(skb)->gso_size; 3118 3119 /* set new MSS value if needed */ 3120 if (mss != tx_q->mss) { 3121 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3122 mss_desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3123 else 3124 mss_desc = &tx_q->dma_tx[tx_q->cur_tx]; 3125 3126 stmmac_set_mss(priv, mss_desc, mss); 3127 tx_q->mss = mss; 3128 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, 3129 priv->dma_tx_size); 3130 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 3131 } 3132 3133 if (netif_msg_tx_queued(priv)) { 3134 pr_info("%s: hdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 3135 __func__, hdr, proto_hdr_len, pay_len, mss); 3136 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 3137 skb->data_len); 3138 } 3139 3140 /* Check if VLAN can be inserted by HW */ 3141 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3142 3143 first_entry = tx_q->cur_tx; 3144 WARN_ON(tx_q->tx_skbuff[first_entry]); 3145 3146 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3147 desc = &tx_q->dma_entx[first_entry].basic; 3148 else 3149 desc = &tx_q->dma_tx[first_entry]; 3150 first = desc; 3151 3152 if (has_vlan) 3153 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3154 3155 /* first descriptor: fill Headers on Buf1 */ 3156 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 3157 DMA_TO_DEVICE); 3158 if (dma_mapping_error(priv->device, des)) 3159 goto dma_map_err; 3160 3161 tx_q->tx_skbuff_dma[first_entry].buf = des; 3162 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 3163 3164 if (priv->dma_cap.addr64 <= 32) { 3165 first->des0 = cpu_to_le32(des); 3166 3167 /* Fill start of payload in buff2 of first descriptor */ 3168 if (pay_len) 3169 first->des1 = cpu_to_le32(des + proto_hdr_len); 3170 3171 /* If needed take extra descriptors to fill the remaining payload */ 3172 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 3173 } else { 3174 stmmac_set_desc_addr(priv, first, des); 3175 tmp_pay_len = pay_len; 3176 des += proto_hdr_len; 3177 pay_len = 0; 3178 } 3179 3180 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3181 3182 /* Prepare fragments */ 3183 for (i = 0; i < nfrags; i++) { 3184 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3185 3186 des = skb_frag_dma_map(priv->device, frag, 0, 3187 skb_frag_size(frag), 3188 DMA_TO_DEVICE); 3189 if (dma_mapping_error(priv->device, des)) 3190 goto dma_map_err; 3191 3192 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3193 (i == nfrags - 1), queue); 3194 3195 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3196 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3197 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3198 } 3199 3200 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3201 3202 /* Only the last descriptor gets to point to the skb. */ 3203 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3204 3205 /* Manage tx mitigation */ 3206 tx_packets = (tx_q->cur_tx + 1) - first_tx; 3207 tx_q->tx_count_frames += tx_packets; 3208 3209 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3210 set_ic = true; 3211 else if (!priv->tx_coal_frames) 3212 set_ic = false; 3213 else if (tx_packets > priv->tx_coal_frames) 3214 set_ic = true; 3215 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3216 set_ic = true; 3217 else 3218 set_ic = false; 3219 3220 if (set_ic) { 3221 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3222 desc = &tx_q->dma_entx[tx_q->cur_tx].basic; 3223 else 3224 desc = &tx_q->dma_tx[tx_q->cur_tx]; 3225 3226 tx_q->tx_count_frames = 0; 3227 stmmac_set_tx_ic(priv, desc); 3228 priv->xstats.tx_set_ic_bit++; 3229 } 3230 3231 /* We've used all descriptors we need for this skb, however, 3232 * advance cur_tx so that it references a fresh descriptor. 3233 * ndo_start_xmit will fill this descriptor the next time it's 3234 * called and stmmac_tx_clean may clean up to this descriptor. 3235 */ 3236 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, priv->dma_tx_size); 3237 3238 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3239 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3240 __func__); 3241 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3242 } 3243 3244 dev->stats.tx_bytes += skb->len; 3245 priv->xstats.tx_tso_frames++; 3246 priv->xstats.tx_tso_nfrags += nfrags; 3247 3248 if (priv->sarc_type) 3249 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3250 3251 skb_tx_timestamp(skb); 3252 3253 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3254 priv->hwts_tx_en)) { 3255 /* declare that device is doing timestamping */ 3256 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3257 stmmac_enable_tx_timestamp(priv, first); 3258 } 3259 3260 /* Complete the first descriptor before granting the DMA */ 3261 stmmac_prepare_tso_tx_desc(priv, first, 1, 3262 proto_hdr_len, 3263 pay_len, 3264 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3265 hdr / 4, (skb->len - proto_hdr_len)); 3266 3267 /* If context desc is used to change MSS */ 3268 if (mss_desc) { 3269 /* Make sure that first descriptor has been completely 3270 * written, including its own bit. This is because MSS is 3271 * actually before first descriptor, so we need to make 3272 * sure that MSS's own bit is the last thing written. 3273 */ 3274 dma_wmb(); 3275 stmmac_set_tx_owner(priv, mss_desc); 3276 } 3277 3278 /* The own bit must be the latest setting done when prepare the 3279 * descriptor and then barrier is needed to make sure that 3280 * all is coherent before granting the DMA engine. 3281 */ 3282 wmb(); 3283 3284 if (netif_msg_pktdata(priv)) { 3285 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3286 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3287 tx_q->cur_tx, first, nfrags); 3288 pr_info(">>> frame to be transmitted: "); 3289 print_pkt(skb->data, skb_headlen(skb)); 3290 } 3291 3292 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3293 3294 if (tx_q->tbs & STMMAC_TBS_AVAIL) 3295 desc_size = sizeof(struct dma_edesc); 3296 else 3297 desc_size = sizeof(struct dma_desc); 3298 3299 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3300 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3301 stmmac_tx_timer_arm(priv, queue); 3302 3303 return NETDEV_TX_OK; 3304 3305 dma_map_err: 3306 dev_err(priv->device, "Tx dma map failed\n"); 3307 dev_kfree_skb(skb); 3308 priv->dev->stats.tx_dropped++; 3309 return NETDEV_TX_OK; 3310 } 3311 3312 /** 3313 * stmmac_xmit - Tx entry point of the driver 3314 * @skb : the socket buffer 3315 * @dev : device pointer 3316 * Description : this is the tx entry point of the driver. 3317 * It programs the chain or the ring and supports oversized frames 3318 * and SG feature. 3319 */ 3320 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3321 { 3322 unsigned int first_entry, tx_packets, enh_desc; 3323 struct stmmac_priv *priv = netdev_priv(dev); 3324 unsigned int nopaged_len = skb_headlen(skb); 3325 int i, csum_insertion = 0, is_jumbo = 0; 3326 u32 queue = skb_get_queue_mapping(skb); 3327 int nfrags = skb_shinfo(skb)->nr_frags; 3328 int gso = skb_shinfo(skb)->gso_type; 3329 struct dma_edesc *tbs_desc = NULL; 3330 int entry, desc_size, first_tx; 3331 struct dma_desc *desc, *first; 3332 struct stmmac_tx_queue *tx_q; 3333 bool has_vlan, set_ic; 3334 dma_addr_t des; 3335 3336 tx_q = &priv->tx_queue[queue]; 3337 first_tx = tx_q->cur_tx; 3338 3339 if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en) 3340 stmmac_disable_eee_mode(priv); 3341 3342 /* Manage oversized TCP frames for GMAC4 device */ 3343 if (skb_is_gso(skb) && priv->tso) { 3344 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3345 return stmmac_tso_xmit(skb, dev); 3346 if (priv->plat->has_gmac4 && (gso & SKB_GSO_UDP_L4)) 3347 return stmmac_tso_xmit(skb, dev); 3348 } 3349 3350 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3351 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3352 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3353 queue)); 3354 /* This is a hard error, log it. */ 3355 netdev_err(priv->dev, 3356 "%s: Tx Ring full when queue awake\n", 3357 __func__); 3358 } 3359 return NETDEV_TX_BUSY; 3360 } 3361 3362 /* Check if VLAN can be inserted by HW */ 3363 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3364 3365 entry = tx_q->cur_tx; 3366 first_entry = entry; 3367 WARN_ON(tx_q->tx_skbuff[first_entry]); 3368 3369 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3370 3371 if (likely(priv->extend_desc)) 3372 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3373 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3374 desc = &tx_q->dma_entx[entry].basic; 3375 else 3376 desc = tx_q->dma_tx + entry; 3377 3378 first = desc; 3379 3380 if (has_vlan) 3381 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3382 3383 enh_desc = priv->plat->enh_desc; 3384 /* To program the descriptors according to the size of the frame */ 3385 if (enh_desc) 3386 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3387 3388 if (unlikely(is_jumbo)) { 3389 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3390 if (unlikely(entry < 0) && (entry != -EINVAL)) 3391 goto dma_map_err; 3392 } 3393 3394 for (i = 0; i < nfrags; i++) { 3395 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3396 int len = skb_frag_size(frag); 3397 bool last_segment = (i == (nfrags - 1)); 3398 3399 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 3400 WARN_ON(tx_q->tx_skbuff[entry]); 3401 3402 if (likely(priv->extend_desc)) 3403 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3404 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3405 desc = &tx_q->dma_entx[entry].basic; 3406 else 3407 desc = tx_q->dma_tx + entry; 3408 3409 des = skb_frag_dma_map(priv->device, frag, 0, len, 3410 DMA_TO_DEVICE); 3411 if (dma_mapping_error(priv->device, des)) 3412 goto dma_map_err; /* should reuse desc w/o issues */ 3413 3414 tx_q->tx_skbuff_dma[entry].buf = des; 3415 3416 stmmac_set_desc_addr(priv, desc, des); 3417 3418 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3419 tx_q->tx_skbuff_dma[entry].len = len; 3420 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3421 3422 /* Prepare the descriptor and set the own bit too */ 3423 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3424 priv->mode, 1, last_segment, skb->len); 3425 } 3426 3427 /* Only the last descriptor gets to point to the skb. */ 3428 tx_q->tx_skbuff[entry] = skb; 3429 3430 /* According to the coalesce parameter the IC bit for the latest 3431 * segment is reset and the timer re-started to clean the tx status. 3432 * This approach takes care about the fragments: desc is the first 3433 * element in case of no SG. 3434 */ 3435 tx_packets = (entry + 1) - first_tx; 3436 tx_q->tx_count_frames += tx_packets; 3437 3438 if ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && priv->hwts_tx_en) 3439 set_ic = true; 3440 else if (!priv->tx_coal_frames) 3441 set_ic = false; 3442 else if (tx_packets > priv->tx_coal_frames) 3443 set_ic = true; 3444 else if ((tx_q->tx_count_frames % priv->tx_coal_frames) < tx_packets) 3445 set_ic = true; 3446 else 3447 set_ic = false; 3448 3449 if (set_ic) { 3450 if (likely(priv->extend_desc)) 3451 desc = &tx_q->dma_etx[entry].basic; 3452 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3453 desc = &tx_q->dma_entx[entry].basic; 3454 else 3455 desc = &tx_q->dma_tx[entry]; 3456 3457 tx_q->tx_count_frames = 0; 3458 stmmac_set_tx_ic(priv, desc); 3459 priv->xstats.tx_set_ic_bit++; 3460 } 3461 3462 /* We've used all descriptors we need for this skb, however, 3463 * advance cur_tx so that it references a fresh descriptor. 3464 * ndo_start_xmit will fill this descriptor the next time it's 3465 * called and stmmac_tx_clean may clean up to this descriptor. 3466 */ 3467 entry = STMMAC_GET_ENTRY(entry, priv->dma_tx_size); 3468 tx_q->cur_tx = entry; 3469 3470 if (netif_msg_pktdata(priv)) { 3471 netdev_dbg(priv->dev, 3472 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3473 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3474 entry, first, nfrags); 3475 3476 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3477 print_pkt(skb->data, skb->len); 3478 } 3479 3480 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3481 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3482 __func__); 3483 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3484 } 3485 3486 dev->stats.tx_bytes += skb->len; 3487 3488 if (priv->sarc_type) 3489 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3490 3491 skb_tx_timestamp(skb); 3492 3493 /* Ready to fill the first descriptor and set the OWN bit w/o any 3494 * problems because all the descriptors are actually ready to be 3495 * passed to the DMA engine. 3496 */ 3497 if (likely(!is_jumbo)) { 3498 bool last_segment = (nfrags == 0); 3499 3500 des = dma_map_single(priv->device, skb->data, 3501 nopaged_len, DMA_TO_DEVICE); 3502 if (dma_mapping_error(priv->device, des)) 3503 goto dma_map_err; 3504 3505 tx_q->tx_skbuff_dma[first_entry].buf = des; 3506 3507 stmmac_set_desc_addr(priv, first, des); 3508 3509 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3510 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3511 3512 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3513 priv->hwts_tx_en)) { 3514 /* declare that device is doing timestamping */ 3515 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3516 stmmac_enable_tx_timestamp(priv, first); 3517 } 3518 3519 /* Prepare the first descriptor setting the OWN bit too */ 3520 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3521 csum_insertion, priv->mode, 0, last_segment, 3522 skb->len); 3523 } 3524 3525 if (tx_q->tbs & STMMAC_TBS_EN) { 3526 struct timespec64 ts = ns_to_timespec64(skb->tstamp); 3527 3528 tbs_desc = &tx_q->dma_entx[first_entry]; 3529 stmmac_set_desc_tbs(priv, tbs_desc, ts.tv_sec, ts.tv_nsec); 3530 } 3531 3532 stmmac_set_tx_owner(priv, first); 3533 3534 /* The own bit must be the latest setting done when prepare the 3535 * descriptor and then barrier is needed to make sure that 3536 * all is coherent before granting the DMA engine. 3537 */ 3538 wmb(); 3539 3540 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3541 3542 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3543 3544 if (likely(priv->extend_desc)) 3545 desc_size = sizeof(struct dma_extended_desc); 3546 else if (tx_q->tbs & STMMAC_TBS_AVAIL) 3547 desc_size = sizeof(struct dma_edesc); 3548 else 3549 desc_size = sizeof(struct dma_desc); 3550 3551 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * desc_size); 3552 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3553 stmmac_tx_timer_arm(priv, queue); 3554 3555 return NETDEV_TX_OK; 3556 3557 dma_map_err: 3558 netdev_err(priv->dev, "Tx DMA map failed\n"); 3559 dev_kfree_skb(skb); 3560 priv->dev->stats.tx_dropped++; 3561 return NETDEV_TX_OK; 3562 } 3563 3564 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3565 { 3566 struct vlan_ethhdr *veth; 3567 __be16 vlan_proto; 3568 u16 vlanid; 3569 3570 veth = (struct vlan_ethhdr *)skb->data; 3571 vlan_proto = veth->h_vlan_proto; 3572 3573 if ((vlan_proto == htons(ETH_P_8021Q) && 3574 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3575 (vlan_proto == htons(ETH_P_8021AD) && 3576 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3577 /* pop the vlan tag */ 3578 vlanid = ntohs(veth->h_vlan_TCI); 3579 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3580 skb_pull(skb, VLAN_HLEN); 3581 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3582 } 3583 } 3584 3585 /** 3586 * stmmac_rx_refill - refill used skb preallocated buffers 3587 * @priv: driver private structure 3588 * @queue: RX queue index 3589 * Description : this is to reallocate the skb for the reception process 3590 * that is based on zero-copy. 3591 */ 3592 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3593 { 3594 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3595 int len, dirty = stmmac_rx_dirty(priv, queue); 3596 unsigned int entry = rx_q->dirty_rx; 3597 3598 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3599 3600 while (dirty-- > 0) { 3601 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3602 struct dma_desc *p; 3603 bool use_rx_wd; 3604 3605 if (priv->extend_desc) 3606 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3607 else 3608 p = rx_q->dma_rx + entry; 3609 3610 if (!buf->page) { 3611 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3612 if (!buf->page) 3613 break; 3614 } 3615 3616 if (priv->sph && !buf->sec_page) { 3617 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3618 if (!buf->sec_page) 3619 break; 3620 3621 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3622 3623 dma_sync_single_for_device(priv->device, buf->sec_addr, 3624 len, DMA_FROM_DEVICE); 3625 } 3626 3627 buf->addr = page_pool_get_dma_addr(buf->page); 3628 3629 /* Sync whole allocation to device. This will invalidate old 3630 * data. 3631 */ 3632 dma_sync_single_for_device(priv->device, buf->addr, len, 3633 DMA_FROM_DEVICE); 3634 3635 stmmac_set_desc_addr(priv, p, buf->addr); 3636 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3637 stmmac_refill_desc3(priv, rx_q, p); 3638 3639 rx_q->rx_count_frames++; 3640 rx_q->rx_count_frames += priv->rx_coal_frames; 3641 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3642 rx_q->rx_count_frames = 0; 3643 3644 use_rx_wd = !priv->rx_coal_frames; 3645 use_rx_wd |= rx_q->rx_count_frames > 0; 3646 if (!priv->use_riwt) 3647 use_rx_wd = false; 3648 3649 dma_wmb(); 3650 stmmac_set_rx_owner(priv, p, use_rx_wd); 3651 3652 entry = STMMAC_GET_ENTRY(entry, priv->dma_rx_size); 3653 } 3654 rx_q->dirty_rx = entry; 3655 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3656 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3657 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3658 } 3659 3660 static unsigned int stmmac_rx_buf1_len(struct stmmac_priv *priv, 3661 struct dma_desc *p, 3662 int status, unsigned int len) 3663 { 3664 unsigned int plen = 0, hlen = 0; 3665 int coe = priv->hw->rx_csum; 3666 3667 /* Not first descriptor, buffer is always zero */ 3668 if (priv->sph && len) 3669 return 0; 3670 3671 /* First descriptor, get split header length */ 3672 stmmac_get_rx_header_len(priv, p, &hlen); 3673 if (priv->sph && hlen) { 3674 priv->xstats.rx_split_hdr_pkt_n++; 3675 return hlen; 3676 } 3677 3678 /* First descriptor, not last descriptor and not split header */ 3679 if (status & rx_not_ls) 3680 return priv->dma_buf_sz; 3681 3682 plen = stmmac_get_rx_frame_len(priv, p, coe); 3683 3684 /* First descriptor and last descriptor and not split header */ 3685 return min_t(unsigned int, priv->dma_buf_sz, plen); 3686 } 3687 3688 static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv, 3689 struct dma_desc *p, 3690 int status, unsigned int len) 3691 { 3692 int coe = priv->hw->rx_csum; 3693 unsigned int plen = 0; 3694 3695 /* Not split header, buffer is not available */ 3696 if (!priv->sph) 3697 return 0; 3698 3699 /* Not last descriptor */ 3700 if (status & rx_not_ls) 3701 return priv->dma_buf_sz; 3702 3703 plen = stmmac_get_rx_frame_len(priv, p, coe); 3704 3705 /* Last descriptor */ 3706 return plen - len; 3707 } 3708 3709 /** 3710 * stmmac_rx - manage the receive process 3711 * @priv: driver private structure 3712 * @limit: napi bugget 3713 * @queue: RX queue index. 3714 * Description : this the function called by the napi poll method. 3715 * It gets all the frames inside the ring. 3716 */ 3717 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3718 { 3719 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3720 struct stmmac_channel *ch = &priv->channel[queue]; 3721 unsigned int count = 0, error = 0, len = 0; 3722 int status = 0, coe = priv->hw->rx_csum; 3723 unsigned int next_entry = rx_q->cur_rx; 3724 struct sk_buff *skb = NULL; 3725 3726 if (netif_msg_rx_status(priv)) { 3727 void *rx_head; 3728 3729 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3730 if (priv->extend_desc) 3731 rx_head = (void *)rx_q->dma_erx; 3732 else 3733 rx_head = (void *)rx_q->dma_rx; 3734 3735 stmmac_display_ring(priv, rx_head, priv->dma_rx_size, true); 3736 } 3737 while (count < limit) { 3738 unsigned int buf1_len = 0, buf2_len = 0; 3739 enum pkt_hash_types hash_type; 3740 struct stmmac_rx_buffer *buf; 3741 struct dma_desc *np, *p; 3742 int entry; 3743 u32 hash; 3744 3745 if (!count && rx_q->state_saved) { 3746 skb = rx_q->state.skb; 3747 error = rx_q->state.error; 3748 len = rx_q->state.len; 3749 } else { 3750 rx_q->state_saved = false; 3751 skb = NULL; 3752 error = 0; 3753 len = 0; 3754 } 3755 3756 if (count >= limit) 3757 break; 3758 3759 read_again: 3760 buf1_len = 0; 3761 buf2_len = 0; 3762 entry = next_entry; 3763 buf = &rx_q->buf_pool[entry]; 3764 3765 if (priv->extend_desc) 3766 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3767 else 3768 p = rx_q->dma_rx + entry; 3769 3770 /* read the status of the incoming frame */ 3771 status = stmmac_rx_status(priv, &priv->dev->stats, 3772 &priv->xstats, p); 3773 /* check if managed by the DMA otherwise go ahead */ 3774 if (unlikely(status & dma_own)) 3775 break; 3776 3777 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, 3778 priv->dma_rx_size); 3779 next_entry = rx_q->cur_rx; 3780 3781 if (priv->extend_desc) 3782 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3783 else 3784 np = rx_q->dma_rx + next_entry; 3785 3786 prefetch(np); 3787 3788 if (priv->extend_desc) 3789 stmmac_rx_extended_status(priv, &priv->dev->stats, 3790 &priv->xstats, rx_q->dma_erx + entry); 3791 if (unlikely(status == discard_frame)) { 3792 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3793 buf->page = NULL; 3794 error = 1; 3795 if (!priv->hwts_rx_en) 3796 priv->dev->stats.rx_errors++; 3797 } 3798 3799 if (unlikely(error && (status & rx_not_ls))) 3800 goto read_again; 3801 if (unlikely(error)) { 3802 dev_kfree_skb(skb); 3803 skb = NULL; 3804 count++; 3805 continue; 3806 } 3807 3808 /* Buffer is good. Go on. */ 3809 3810 prefetch(page_address(buf->page)); 3811 if (buf->sec_page) 3812 prefetch(page_address(buf->sec_page)); 3813 3814 buf1_len = stmmac_rx_buf1_len(priv, p, status, len); 3815 len += buf1_len; 3816 buf2_len = stmmac_rx_buf2_len(priv, p, status, len); 3817 len += buf2_len; 3818 3819 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3820 * Type frames (LLC/LLC-SNAP) 3821 * 3822 * llc_snap is never checked in GMAC >= 4, so this ACS 3823 * feature is always disabled and packets need to be 3824 * stripped manually. 3825 */ 3826 if (likely(!(status & rx_not_ls)) && 3827 (likely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3828 unlikely(status != llc_snap))) { 3829 if (buf2_len) 3830 buf2_len -= ETH_FCS_LEN; 3831 else 3832 buf1_len -= ETH_FCS_LEN; 3833 3834 len -= ETH_FCS_LEN; 3835 } 3836 3837 if (!skb) { 3838 skb = napi_alloc_skb(&ch->rx_napi, buf1_len); 3839 if (!skb) { 3840 priv->dev->stats.rx_dropped++; 3841 count++; 3842 goto drain_data; 3843 } 3844 3845 dma_sync_single_for_cpu(priv->device, buf->addr, 3846 buf1_len, DMA_FROM_DEVICE); 3847 skb_copy_to_linear_data(skb, page_address(buf->page), 3848 buf1_len); 3849 skb_put(skb, buf1_len); 3850 3851 /* Data payload copied into SKB, page ready for recycle */ 3852 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3853 buf->page = NULL; 3854 } else if (buf1_len) { 3855 dma_sync_single_for_cpu(priv->device, buf->addr, 3856 buf1_len, DMA_FROM_DEVICE); 3857 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3858 buf->page, 0, buf1_len, 3859 priv->dma_buf_sz); 3860 3861 /* Data payload appended into SKB */ 3862 page_pool_release_page(rx_q->page_pool, buf->page); 3863 buf->page = NULL; 3864 } 3865 3866 if (buf2_len) { 3867 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3868 buf2_len, DMA_FROM_DEVICE); 3869 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3870 buf->sec_page, 0, buf2_len, 3871 priv->dma_buf_sz); 3872 3873 /* Data payload appended into SKB */ 3874 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3875 buf->sec_page = NULL; 3876 } 3877 3878 drain_data: 3879 if (likely(status & rx_not_ls)) 3880 goto read_again; 3881 if (!skb) 3882 continue; 3883 3884 /* Got entire packet into SKB. Finish it. */ 3885 3886 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3887 stmmac_rx_vlan(priv->dev, skb); 3888 skb->protocol = eth_type_trans(skb, priv->dev); 3889 3890 if (unlikely(!coe)) 3891 skb_checksum_none_assert(skb); 3892 else 3893 skb->ip_summed = CHECKSUM_UNNECESSARY; 3894 3895 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3896 skb_set_hash(skb, hash, hash_type); 3897 3898 skb_record_rx_queue(skb, queue); 3899 napi_gro_receive(&ch->rx_napi, skb); 3900 skb = NULL; 3901 3902 priv->dev->stats.rx_packets++; 3903 priv->dev->stats.rx_bytes += len; 3904 count++; 3905 } 3906 3907 if (status & rx_not_ls || skb) { 3908 rx_q->state_saved = true; 3909 rx_q->state.skb = skb; 3910 rx_q->state.error = error; 3911 rx_q->state.len = len; 3912 } 3913 3914 stmmac_rx_refill(priv, queue); 3915 3916 priv->xstats.rx_pkt_n += count; 3917 3918 return count; 3919 } 3920 3921 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3922 { 3923 struct stmmac_channel *ch = 3924 container_of(napi, struct stmmac_channel, rx_napi); 3925 struct stmmac_priv *priv = ch->priv_data; 3926 u32 chan = ch->index; 3927 int work_done; 3928 3929 priv->xstats.napi_poll++; 3930 3931 work_done = stmmac_rx(priv, budget, chan); 3932 if (work_done < budget && napi_complete_done(napi, work_done)) { 3933 unsigned long flags; 3934 3935 spin_lock_irqsave(&ch->lock, flags); 3936 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 1, 0); 3937 spin_unlock_irqrestore(&ch->lock, flags); 3938 } 3939 3940 return work_done; 3941 } 3942 3943 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3944 { 3945 struct stmmac_channel *ch = 3946 container_of(napi, struct stmmac_channel, tx_napi); 3947 struct stmmac_priv *priv = ch->priv_data; 3948 u32 chan = ch->index; 3949 int work_done; 3950 3951 priv->xstats.napi_poll++; 3952 3953 work_done = stmmac_tx_clean(priv, priv->dma_tx_size, chan); 3954 work_done = min(work_done, budget); 3955 3956 if (work_done < budget && napi_complete_done(napi, work_done)) { 3957 unsigned long flags; 3958 3959 spin_lock_irqsave(&ch->lock, flags); 3960 stmmac_enable_dma_irq(priv, priv->ioaddr, chan, 0, 1); 3961 spin_unlock_irqrestore(&ch->lock, flags); 3962 } 3963 3964 return work_done; 3965 } 3966 3967 /** 3968 * stmmac_tx_timeout 3969 * @dev : Pointer to net device structure 3970 * @txqueue: the index of the hanging transmit queue 3971 * Description: this function is called when a packet transmission fails to 3972 * complete within a reasonable time. The driver will mark the error in the 3973 * netdev structure and arrange for the device to be reset to a sane state 3974 * in order to transmit a new packet. 3975 */ 3976 static void stmmac_tx_timeout(struct net_device *dev, unsigned int txqueue) 3977 { 3978 struct stmmac_priv *priv = netdev_priv(dev); 3979 3980 stmmac_global_err(priv); 3981 } 3982 3983 /** 3984 * stmmac_set_rx_mode - entry point for multicast addressing 3985 * @dev : pointer to the device structure 3986 * Description: 3987 * This function is a driver entry point which gets called by the kernel 3988 * whenever multicast addresses must be enabled/disabled. 3989 * Return value: 3990 * void. 3991 */ 3992 static void stmmac_set_rx_mode(struct net_device *dev) 3993 { 3994 struct stmmac_priv *priv = netdev_priv(dev); 3995 3996 stmmac_set_filter(priv, priv->hw, dev); 3997 } 3998 3999 /** 4000 * stmmac_change_mtu - entry point to change MTU size for the device. 4001 * @dev : device pointer. 4002 * @new_mtu : the new MTU size for the device. 4003 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 4004 * to drive packet transmission. Ethernet has an MTU of 1500 octets 4005 * (ETH_DATA_LEN). This value can be changed with ifconfig. 4006 * Return value: 4007 * 0 on success and an appropriate (-)ve integer as defined in errno.h 4008 * file on failure. 4009 */ 4010 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 4011 { 4012 struct stmmac_priv *priv = netdev_priv(dev); 4013 int txfifosz = priv->plat->tx_fifo_size; 4014 4015 if (txfifosz == 0) 4016 txfifosz = priv->dma_cap.tx_fifo_size; 4017 4018 txfifosz /= priv->plat->tx_queues_to_use; 4019 4020 if (netif_running(dev)) { 4021 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 4022 return -EBUSY; 4023 } 4024 4025 new_mtu = STMMAC_ALIGN(new_mtu); 4026 4027 /* If condition true, FIFO is too small or MTU too large */ 4028 if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB)) 4029 return -EINVAL; 4030 4031 dev->mtu = new_mtu; 4032 4033 netdev_update_features(dev); 4034 4035 return 0; 4036 } 4037 4038 static netdev_features_t stmmac_fix_features(struct net_device *dev, 4039 netdev_features_t features) 4040 { 4041 struct stmmac_priv *priv = netdev_priv(dev); 4042 4043 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 4044 features &= ~NETIF_F_RXCSUM; 4045 4046 if (!priv->plat->tx_coe) 4047 features &= ~NETIF_F_CSUM_MASK; 4048 4049 /* Some GMAC devices have a bugged Jumbo frame support that 4050 * needs to have the Tx COE disabled for oversized frames 4051 * (due to limited buffer sizes). In this case we disable 4052 * the TX csum insertion in the TDES and not use SF. 4053 */ 4054 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 4055 features &= ~NETIF_F_CSUM_MASK; 4056 4057 /* Disable tso if asked by ethtool */ 4058 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4059 if (features & NETIF_F_TSO) 4060 priv->tso = true; 4061 else 4062 priv->tso = false; 4063 } 4064 4065 return features; 4066 } 4067 4068 static int stmmac_set_features(struct net_device *netdev, 4069 netdev_features_t features) 4070 { 4071 struct stmmac_priv *priv = netdev_priv(netdev); 4072 bool sph_en; 4073 u32 chan; 4074 4075 /* Keep the COE Type in case of csum is supporting */ 4076 if (features & NETIF_F_RXCSUM) 4077 priv->hw->rx_csum = priv->plat->rx_coe; 4078 else 4079 priv->hw->rx_csum = 0; 4080 /* No check needed because rx_coe has been set before and it will be 4081 * fixed in case of issue. 4082 */ 4083 stmmac_rx_ipc(priv, priv->hw); 4084 4085 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 4086 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 4087 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 4088 4089 return 0; 4090 } 4091 4092 /** 4093 * stmmac_interrupt - main ISR 4094 * @irq: interrupt number. 4095 * @dev_id: to pass the net device pointer (must be valid). 4096 * Description: this is the main driver interrupt service routine. 4097 * It can call: 4098 * o DMA service routine (to manage incoming frame reception and transmission 4099 * status) 4100 * o Core interrupts to manage: remote wake-up, management counter, LPI 4101 * interrupts. 4102 */ 4103 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 4104 { 4105 struct net_device *dev = (struct net_device *)dev_id; 4106 struct stmmac_priv *priv = netdev_priv(dev); 4107 u32 rx_cnt = priv->plat->rx_queues_to_use; 4108 u32 tx_cnt = priv->plat->tx_queues_to_use; 4109 u32 queues_count; 4110 u32 queue; 4111 bool xmac; 4112 4113 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 4114 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 4115 4116 if (priv->irq_wake) 4117 pm_wakeup_event(priv->device, 0); 4118 4119 /* Check if adapter is up */ 4120 if (test_bit(STMMAC_DOWN, &priv->state)) 4121 return IRQ_HANDLED; 4122 /* Check if a fatal error happened */ 4123 if (stmmac_safety_feat_interrupt(priv)) 4124 return IRQ_HANDLED; 4125 4126 /* To handle GMAC own interrupts */ 4127 if ((priv->plat->has_gmac) || xmac) { 4128 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 4129 int mtl_status; 4130 4131 if (unlikely(status)) { 4132 /* For LPI we need to save the tx status */ 4133 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 4134 priv->tx_path_in_lpi_mode = true; 4135 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 4136 priv->tx_path_in_lpi_mode = false; 4137 } 4138 4139 for (queue = 0; queue < queues_count; queue++) { 4140 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4141 4142 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 4143 queue); 4144 if (mtl_status != -EINVAL) 4145 status |= mtl_status; 4146 4147 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 4148 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 4149 rx_q->rx_tail_addr, 4150 queue); 4151 } 4152 4153 /* PCS link status */ 4154 if (priv->hw->pcs) { 4155 if (priv->xstats.pcs_link) 4156 netif_carrier_on(dev); 4157 else 4158 netif_carrier_off(dev); 4159 } 4160 } 4161 4162 /* To handle DMA interrupts */ 4163 stmmac_dma_interrupt(priv); 4164 4165 return IRQ_HANDLED; 4166 } 4167 4168 #ifdef CONFIG_NET_POLL_CONTROLLER 4169 /* Polling receive - used by NETCONSOLE and other diagnostic tools 4170 * to allow network I/O with interrupts disabled. 4171 */ 4172 static void stmmac_poll_controller(struct net_device *dev) 4173 { 4174 disable_irq(dev->irq); 4175 stmmac_interrupt(dev->irq, dev); 4176 enable_irq(dev->irq); 4177 } 4178 #endif 4179 4180 /** 4181 * stmmac_ioctl - Entry point for the Ioctl 4182 * @dev: Device pointer. 4183 * @rq: An IOCTL specefic structure, that can contain a pointer to 4184 * a proprietary structure used to pass information to the driver. 4185 * @cmd: IOCTL command 4186 * Description: 4187 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 4188 */ 4189 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 4190 { 4191 struct stmmac_priv *priv = netdev_priv (dev); 4192 int ret = -EOPNOTSUPP; 4193 4194 if (!netif_running(dev)) 4195 return -EINVAL; 4196 4197 switch (cmd) { 4198 case SIOCGMIIPHY: 4199 case SIOCGMIIREG: 4200 case SIOCSMIIREG: 4201 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 4202 break; 4203 case SIOCSHWTSTAMP: 4204 ret = stmmac_hwtstamp_set(dev, rq); 4205 break; 4206 case SIOCGHWTSTAMP: 4207 ret = stmmac_hwtstamp_get(dev, rq); 4208 break; 4209 default: 4210 break; 4211 } 4212 4213 return ret; 4214 } 4215 4216 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 4217 void *cb_priv) 4218 { 4219 struct stmmac_priv *priv = cb_priv; 4220 int ret = -EOPNOTSUPP; 4221 4222 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 4223 return ret; 4224 4225 stmmac_disable_all_queues(priv); 4226 4227 switch (type) { 4228 case TC_SETUP_CLSU32: 4229 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 4230 break; 4231 case TC_SETUP_CLSFLOWER: 4232 ret = stmmac_tc_setup_cls(priv, priv, type_data); 4233 break; 4234 default: 4235 break; 4236 } 4237 4238 stmmac_enable_all_queues(priv); 4239 return ret; 4240 } 4241 4242 static LIST_HEAD(stmmac_block_cb_list); 4243 4244 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 4245 void *type_data) 4246 { 4247 struct stmmac_priv *priv = netdev_priv(ndev); 4248 4249 switch (type) { 4250 case TC_SETUP_BLOCK: 4251 return flow_block_cb_setup_simple(type_data, 4252 &stmmac_block_cb_list, 4253 stmmac_setup_tc_block_cb, 4254 priv, priv, true); 4255 case TC_SETUP_QDISC_CBS: 4256 return stmmac_tc_setup_cbs(priv, priv, type_data); 4257 case TC_SETUP_QDISC_TAPRIO: 4258 return stmmac_tc_setup_taprio(priv, priv, type_data); 4259 case TC_SETUP_QDISC_ETF: 4260 return stmmac_tc_setup_etf(priv, priv, type_data); 4261 default: 4262 return -EOPNOTSUPP; 4263 } 4264 } 4265 4266 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 4267 struct net_device *sb_dev) 4268 { 4269 int gso = skb_shinfo(skb)->gso_type; 4270 4271 if (gso & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6 | SKB_GSO_UDP_L4)) { 4272 /* 4273 * There is no way to determine the number of TSO/USO 4274 * capable Queues. Let's use always the Queue 0 4275 * because if TSO/USO is supported then at least this 4276 * one will be capable. 4277 */ 4278 return 0; 4279 } 4280 4281 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4282 } 4283 4284 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4285 { 4286 struct stmmac_priv *priv = netdev_priv(ndev); 4287 int ret = 0; 4288 4289 ret = eth_mac_addr(ndev, addr); 4290 if (ret) 4291 return ret; 4292 4293 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4294 4295 return ret; 4296 } 4297 4298 #ifdef CONFIG_DEBUG_FS 4299 static struct dentry *stmmac_fs_dir; 4300 4301 static void sysfs_display_ring(void *head, int size, int extend_desc, 4302 struct seq_file *seq) 4303 { 4304 int i; 4305 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4306 struct dma_desc *p = (struct dma_desc *)head; 4307 4308 for (i = 0; i < size; i++) { 4309 if (extend_desc) { 4310 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4311 i, (unsigned int)virt_to_phys(ep), 4312 le32_to_cpu(ep->basic.des0), 4313 le32_to_cpu(ep->basic.des1), 4314 le32_to_cpu(ep->basic.des2), 4315 le32_to_cpu(ep->basic.des3)); 4316 ep++; 4317 } else { 4318 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4319 i, (unsigned int)virt_to_phys(p), 4320 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4321 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4322 p++; 4323 } 4324 seq_printf(seq, "\n"); 4325 } 4326 } 4327 4328 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4329 { 4330 struct net_device *dev = seq->private; 4331 struct stmmac_priv *priv = netdev_priv(dev); 4332 u32 rx_count = priv->plat->rx_queues_to_use; 4333 u32 tx_count = priv->plat->tx_queues_to_use; 4334 u32 queue; 4335 4336 if ((dev->flags & IFF_UP) == 0) 4337 return 0; 4338 4339 for (queue = 0; queue < rx_count; queue++) { 4340 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4341 4342 seq_printf(seq, "RX Queue %d:\n", queue); 4343 4344 if (priv->extend_desc) { 4345 seq_printf(seq, "Extended descriptor ring:\n"); 4346 sysfs_display_ring((void *)rx_q->dma_erx, 4347 priv->dma_rx_size, 1, seq); 4348 } else { 4349 seq_printf(seq, "Descriptor ring:\n"); 4350 sysfs_display_ring((void *)rx_q->dma_rx, 4351 priv->dma_rx_size, 0, seq); 4352 } 4353 } 4354 4355 for (queue = 0; queue < tx_count; queue++) { 4356 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4357 4358 seq_printf(seq, "TX Queue %d:\n", queue); 4359 4360 if (priv->extend_desc) { 4361 seq_printf(seq, "Extended descriptor ring:\n"); 4362 sysfs_display_ring((void *)tx_q->dma_etx, 4363 priv->dma_tx_size, 1, seq); 4364 } else if (!(tx_q->tbs & STMMAC_TBS_AVAIL)) { 4365 seq_printf(seq, "Descriptor ring:\n"); 4366 sysfs_display_ring((void *)tx_q->dma_tx, 4367 priv->dma_tx_size, 0, seq); 4368 } 4369 } 4370 4371 return 0; 4372 } 4373 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4374 4375 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4376 { 4377 struct net_device *dev = seq->private; 4378 struct stmmac_priv *priv = netdev_priv(dev); 4379 4380 if (!priv->hw_cap_support) { 4381 seq_printf(seq, "DMA HW features not supported\n"); 4382 return 0; 4383 } 4384 4385 seq_printf(seq, "==============================\n"); 4386 seq_printf(seq, "\tDMA HW features\n"); 4387 seq_printf(seq, "==============================\n"); 4388 4389 seq_printf(seq, "\t10/100 Mbps: %s\n", 4390 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4391 seq_printf(seq, "\t1000 Mbps: %s\n", 4392 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4393 seq_printf(seq, "\tHalf duplex: %s\n", 4394 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4395 seq_printf(seq, "\tHash Filter: %s\n", 4396 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4397 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4398 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4399 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4400 (priv->dma_cap.pcs) ? "Y" : "N"); 4401 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4402 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4403 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4404 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4405 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4406 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4407 seq_printf(seq, "\tRMON module: %s\n", 4408 (priv->dma_cap.rmon) ? "Y" : "N"); 4409 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4410 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4411 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4412 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4413 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4414 (priv->dma_cap.eee) ? "Y" : "N"); 4415 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4416 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4417 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4418 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4419 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4420 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4421 } else { 4422 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4423 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4424 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4425 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4426 } 4427 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4428 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4429 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4430 priv->dma_cap.number_rx_channel); 4431 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4432 priv->dma_cap.number_tx_channel); 4433 seq_printf(seq, "\tNumber of Additional RX queues: %d\n", 4434 priv->dma_cap.number_rx_queues); 4435 seq_printf(seq, "\tNumber of Additional TX queues: %d\n", 4436 priv->dma_cap.number_tx_queues); 4437 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4438 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4439 seq_printf(seq, "\tTX Fifo Size: %d\n", priv->dma_cap.tx_fifo_size); 4440 seq_printf(seq, "\tRX Fifo Size: %d\n", priv->dma_cap.rx_fifo_size); 4441 seq_printf(seq, "\tHash Table Size: %d\n", priv->dma_cap.hash_tb_sz); 4442 seq_printf(seq, "\tTSO: %s\n", priv->dma_cap.tsoen ? "Y" : "N"); 4443 seq_printf(seq, "\tNumber of PPS Outputs: %d\n", 4444 priv->dma_cap.pps_out_num); 4445 seq_printf(seq, "\tSafety Features: %s\n", 4446 priv->dma_cap.asp ? "Y" : "N"); 4447 seq_printf(seq, "\tFlexible RX Parser: %s\n", 4448 priv->dma_cap.frpsel ? "Y" : "N"); 4449 seq_printf(seq, "\tEnhanced Addressing: %d\n", 4450 priv->dma_cap.addr64); 4451 seq_printf(seq, "\tReceive Side Scaling: %s\n", 4452 priv->dma_cap.rssen ? "Y" : "N"); 4453 seq_printf(seq, "\tVLAN Hash Filtering: %s\n", 4454 priv->dma_cap.vlhash ? "Y" : "N"); 4455 seq_printf(seq, "\tSplit Header: %s\n", 4456 priv->dma_cap.sphen ? "Y" : "N"); 4457 seq_printf(seq, "\tVLAN TX Insertion: %s\n", 4458 priv->dma_cap.vlins ? "Y" : "N"); 4459 seq_printf(seq, "\tDouble VLAN: %s\n", 4460 priv->dma_cap.dvlan ? "Y" : "N"); 4461 seq_printf(seq, "\tNumber of L3/L4 Filters: %d\n", 4462 priv->dma_cap.l3l4fnum); 4463 seq_printf(seq, "\tARP Offloading: %s\n", 4464 priv->dma_cap.arpoffsel ? "Y" : "N"); 4465 seq_printf(seq, "\tEnhancements to Scheduled Traffic (EST): %s\n", 4466 priv->dma_cap.estsel ? "Y" : "N"); 4467 seq_printf(seq, "\tFrame Preemption (FPE): %s\n", 4468 priv->dma_cap.fpesel ? "Y" : "N"); 4469 seq_printf(seq, "\tTime-Based Scheduling (TBS): %s\n", 4470 priv->dma_cap.tbssel ? "Y" : "N"); 4471 return 0; 4472 } 4473 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4474 4475 /* Use network device events to rename debugfs file entries. 4476 */ 4477 static int stmmac_device_event(struct notifier_block *unused, 4478 unsigned long event, void *ptr) 4479 { 4480 struct net_device *dev = netdev_notifier_info_to_dev(ptr); 4481 struct stmmac_priv *priv = netdev_priv(dev); 4482 4483 if (dev->netdev_ops != &stmmac_netdev_ops) 4484 goto done; 4485 4486 switch (event) { 4487 case NETDEV_CHANGENAME: 4488 if (priv->dbgfs_dir) 4489 priv->dbgfs_dir = debugfs_rename(stmmac_fs_dir, 4490 priv->dbgfs_dir, 4491 stmmac_fs_dir, 4492 dev->name); 4493 break; 4494 } 4495 done: 4496 return NOTIFY_DONE; 4497 } 4498 4499 static struct notifier_block stmmac_notifier = { 4500 .notifier_call = stmmac_device_event, 4501 }; 4502 4503 static void stmmac_init_fs(struct net_device *dev) 4504 { 4505 struct stmmac_priv *priv = netdev_priv(dev); 4506 4507 rtnl_lock(); 4508 4509 /* Create per netdev entries */ 4510 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4511 4512 /* Entry to report DMA RX/TX rings */ 4513 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4514 &stmmac_rings_status_fops); 4515 4516 /* Entry to report the DMA HW features */ 4517 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4518 &stmmac_dma_cap_fops); 4519 4520 rtnl_unlock(); 4521 } 4522 4523 static void stmmac_exit_fs(struct net_device *dev) 4524 { 4525 struct stmmac_priv *priv = netdev_priv(dev); 4526 4527 debugfs_remove_recursive(priv->dbgfs_dir); 4528 } 4529 #endif /* CONFIG_DEBUG_FS */ 4530 4531 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4532 { 4533 unsigned char *data = (unsigned char *)&vid_le; 4534 unsigned char data_byte = 0; 4535 u32 crc = ~0x0; 4536 u32 temp = 0; 4537 int i, bits; 4538 4539 bits = get_bitmask_order(VLAN_VID_MASK); 4540 for (i = 0; i < bits; i++) { 4541 if ((i % 8) == 0) 4542 data_byte = data[i / 8]; 4543 4544 temp = ((crc & 1) ^ data_byte) & 1; 4545 crc >>= 1; 4546 data_byte >>= 1; 4547 4548 if (temp) 4549 crc ^= 0xedb88320; 4550 } 4551 4552 return crc; 4553 } 4554 4555 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4556 { 4557 u32 crc, hash = 0; 4558 __le16 pmatch = 0; 4559 int count = 0; 4560 u16 vid = 0; 4561 4562 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4563 __le16 vid_le = cpu_to_le16(vid); 4564 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4565 hash |= (1 << crc); 4566 count++; 4567 } 4568 4569 if (!priv->dma_cap.vlhash) { 4570 if (count > 2) /* VID = 0 always passes filter */ 4571 return -EOPNOTSUPP; 4572 4573 pmatch = cpu_to_le16(vid); 4574 hash = 0; 4575 } 4576 4577 return stmmac_update_vlan_hash(priv, priv->hw, hash, pmatch, is_double); 4578 } 4579 4580 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4581 { 4582 struct stmmac_priv *priv = netdev_priv(ndev); 4583 bool is_double = false; 4584 int ret; 4585 4586 if (be16_to_cpu(proto) == ETH_P_8021AD) 4587 is_double = true; 4588 4589 set_bit(vid, priv->active_vlans); 4590 ret = stmmac_vlan_update(priv, is_double); 4591 if (ret) { 4592 clear_bit(vid, priv->active_vlans); 4593 return ret; 4594 } 4595 4596 if (priv->hw->num_vlan) { 4597 ret = stmmac_add_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4598 if (ret) 4599 return ret; 4600 } 4601 4602 return 0; 4603 } 4604 4605 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4606 { 4607 struct stmmac_priv *priv = netdev_priv(ndev); 4608 bool is_double = false; 4609 int ret; 4610 4611 if (be16_to_cpu(proto) == ETH_P_8021AD) 4612 is_double = true; 4613 4614 clear_bit(vid, priv->active_vlans); 4615 4616 if (priv->hw->num_vlan) { 4617 ret = stmmac_del_hw_vlan_rx_fltr(priv, ndev, priv->hw, proto, vid); 4618 if (ret) 4619 return ret; 4620 } 4621 4622 return stmmac_vlan_update(priv, is_double); 4623 } 4624 4625 static const struct net_device_ops stmmac_netdev_ops = { 4626 .ndo_open = stmmac_open, 4627 .ndo_start_xmit = stmmac_xmit, 4628 .ndo_stop = stmmac_release, 4629 .ndo_change_mtu = stmmac_change_mtu, 4630 .ndo_fix_features = stmmac_fix_features, 4631 .ndo_set_features = stmmac_set_features, 4632 .ndo_set_rx_mode = stmmac_set_rx_mode, 4633 .ndo_tx_timeout = stmmac_tx_timeout, 4634 .ndo_do_ioctl = stmmac_ioctl, 4635 .ndo_setup_tc = stmmac_setup_tc, 4636 .ndo_select_queue = stmmac_select_queue, 4637 #ifdef CONFIG_NET_POLL_CONTROLLER 4638 .ndo_poll_controller = stmmac_poll_controller, 4639 #endif 4640 .ndo_set_mac_address = stmmac_set_mac_address, 4641 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4642 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4643 }; 4644 4645 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4646 { 4647 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4648 return; 4649 if (test_bit(STMMAC_DOWN, &priv->state)) 4650 return; 4651 4652 netdev_err(priv->dev, "Reset adapter.\n"); 4653 4654 rtnl_lock(); 4655 netif_trans_update(priv->dev); 4656 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4657 usleep_range(1000, 2000); 4658 4659 set_bit(STMMAC_DOWN, &priv->state); 4660 dev_close(priv->dev); 4661 dev_open(priv->dev, NULL); 4662 clear_bit(STMMAC_DOWN, &priv->state); 4663 clear_bit(STMMAC_RESETING, &priv->state); 4664 rtnl_unlock(); 4665 } 4666 4667 static void stmmac_service_task(struct work_struct *work) 4668 { 4669 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4670 service_task); 4671 4672 stmmac_reset_subtask(priv); 4673 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4674 } 4675 4676 /** 4677 * stmmac_hw_init - Init the MAC device 4678 * @priv: driver private structure 4679 * Description: this function is to configure the MAC device according to 4680 * some platform parameters or the HW capability register. It prepares the 4681 * driver to use either ring or chain modes and to setup either enhanced or 4682 * normal descriptors. 4683 */ 4684 static int stmmac_hw_init(struct stmmac_priv *priv) 4685 { 4686 int ret; 4687 4688 /* dwmac-sun8i only work in chain mode */ 4689 if (priv->plat->has_sun8i) 4690 chain_mode = 1; 4691 priv->chain_mode = chain_mode; 4692 4693 /* Initialize HW Interface */ 4694 ret = stmmac_hwif_init(priv); 4695 if (ret) 4696 return ret; 4697 4698 /* Get the HW capability (new GMAC newer than 3.50a) */ 4699 priv->hw_cap_support = stmmac_get_hw_features(priv); 4700 if (priv->hw_cap_support) { 4701 dev_info(priv->device, "DMA HW capability register supported\n"); 4702 4703 /* We can override some gmac/dma configuration fields: e.g. 4704 * enh_desc, tx_coe (e.g. that are passed through the 4705 * platform) with the values from the HW capability 4706 * register (if supported). 4707 */ 4708 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4709 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4710 priv->hw->pmt = priv->plat->pmt; 4711 if (priv->dma_cap.hash_tb_sz) { 4712 priv->hw->multicast_filter_bins = 4713 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4714 priv->hw->mcast_bits_log2 = 4715 ilog2(priv->hw->multicast_filter_bins); 4716 } 4717 4718 /* TXCOE doesn't work in thresh DMA mode */ 4719 if (priv->plat->force_thresh_dma_mode) 4720 priv->plat->tx_coe = 0; 4721 else 4722 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4723 4724 /* In case of GMAC4 rx_coe is from HW cap register. */ 4725 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4726 4727 if (priv->dma_cap.rx_coe_type2) 4728 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4729 else if (priv->dma_cap.rx_coe_type1) 4730 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4731 4732 } else { 4733 dev_info(priv->device, "No HW DMA feature register supported\n"); 4734 } 4735 4736 if (priv->plat->rx_coe) { 4737 priv->hw->rx_csum = priv->plat->rx_coe; 4738 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4739 if (priv->synopsys_id < DWMAC_CORE_4_00) 4740 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4741 } 4742 if (priv->plat->tx_coe) 4743 dev_info(priv->device, "TX Checksum insertion supported\n"); 4744 4745 if (priv->plat->pmt) { 4746 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4747 device_set_wakeup_capable(priv->device, 1); 4748 } 4749 4750 if (priv->dma_cap.tsoen) 4751 dev_info(priv->device, "TSO supported\n"); 4752 4753 priv->hw->vlan_fail_q_en = priv->plat->vlan_fail_q_en; 4754 priv->hw->vlan_fail_q = priv->plat->vlan_fail_q; 4755 4756 /* Run HW quirks, if any */ 4757 if (priv->hwif_quirks) { 4758 ret = priv->hwif_quirks(priv); 4759 if (ret) 4760 return ret; 4761 } 4762 4763 /* Rx Watchdog is available in the COREs newer than the 3.40. 4764 * In some case, for example on bugged HW this feature 4765 * has to be disable and this can be done by passing the 4766 * riwt_off field from the platform. 4767 */ 4768 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4769 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4770 priv->use_riwt = 1; 4771 dev_info(priv->device, 4772 "Enable RX Mitigation via HW Watchdog Timer\n"); 4773 } 4774 4775 return 0; 4776 } 4777 4778 static void stmmac_napi_add(struct net_device *dev) 4779 { 4780 struct stmmac_priv *priv = netdev_priv(dev); 4781 u32 queue, maxq; 4782 4783 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4784 4785 for (queue = 0; queue < maxq; queue++) { 4786 struct stmmac_channel *ch = &priv->channel[queue]; 4787 4788 ch->priv_data = priv; 4789 ch->index = queue; 4790 spin_lock_init(&ch->lock); 4791 4792 if (queue < priv->plat->rx_queues_to_use) { 4793 netif_napi_add(dev, &ch->rx_napi, stmmac_napi_poll_rx, 4794 NAPI_POLL_WEIGHT); 4795 } 4796 if (queue < priv->plat->tx_queues_to_use) { 4797 netif_tx_napi_add(dev, &ch->tx_napi, 4798 stmmac_napi_poll_tx, 4799 NAPI_POLL_WEIGHT); 4800 } 4801 } 4802 } 4803 4804 static void stmmac_napi_del(struct net_device *dev) 4805 { 4806 struct stmmac_priv *priv = netdev_priv(dev); 4807 u32 queue, maxq; 4808 4809 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4810 4811 for (queue = 0; queue < maxq; queue++) { 4812 struct stmmac_channel *ch = &priv->channel[queue]; 4813 4814 if (queue < priv->plat->rx_queues_to_use) 4815 netif_napi_del(&ch->rx_napi); 4816 if (queue < priv->plat->tx_queues_to_use) 4817 netif_napi_del(&ch->tx_napi); 4818 } 4819 } 4820 4821 int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt) 4822 { 4823 struct stmmac_priv *priv = netdev_priv(dev); 4824 int ret = 0; 4825 4826 if (netif_running(dev)) 4827 stmmac_release(dev); 4828 4829 stmmac_napi_del(dev); 4830 4831 priv->plat->rx_queues_to_use = rx_cnt; 4832 priv->plat->tx_queues_to_use = tx_cnt; 4833 4834 stmmac_napi_add(dev); 4835 4836 if (netif_running(dev)) 4837 ret = stmmac_open(dev); 4838 4839 return ret; 4840 } 4841 4842 int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size) 4843 { 4844 struct stmmac_priv *priv = netdev_priv(dev); 4845 int ret = 0; 4846 4847 if (netif_running(dev)) 4848 stmmac_release(dev); 4849 4850 priv->dma_rx_size = rx_size; 4851 priv->dma_tx_size = tx_size; 4852 4853 if (netif_running(dev)) 4854 ret = stmmac_open(dev); 4855 4856 return ret; 4857 } 4858 4859 /** 4860 * stmmac_dvr_probe 4861 * @device: device pointer 4862 * @plat_dat: platform data pointer 4863 * @res: stmmac resource pointer 4864 * Description: this is the main probe function used to 4865 * call the alloc_etherdev, allocate the priv structure. 4866 * Return: 4867 * returns 0 on success, otherwise errno. 4868 */ 4869 int stmmac_dvr_probe(struct device *device, 4870 struct plat_stmmacenet_data *plat_dat, 4871 struct stmmac_resources *res) 4872 { 4873 struct net_device *ndev = NULL; 4874 struct stmmac_priv *priv; 4875 u32 rxq; 4876 int i, ret = 0; 4877 4878 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4879 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4880 if (!ndev) 4881 return -ENOMEM; 4882 4883 SET_NETDEV_DEV(ndev, device); 4884 4885 priv = netdev_priv(ndev); 4886 priv->device = device; 4887 priv->dev = ndev; 4888 4889 stmmac_set_ethtool_ops(ndev); 4890 priv->pause = pause; 4891 priv->plat = plat_dat; 4892 priv->ioaddr = res->addr; 4893 priv->dev->base_addr = (unsigned long)res->addr; 4894 4895 priv->dev->irq = res->irq; 4896 priv->wol_irq = res->wol_irq; 4897 priv->lpi_irq = res->lpi_irq; 4898 4899 if (!IS_ERR_OR_NULL(res->mac)) 4900 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4901 4902 dev_set_drvdata(device, priv->dev); 4903 4904 /* Verify driver arguments */ 4905 stmmac_verify_args(); 4906 4907 /* Allocate workqueue */ 4908 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4909 if (!priv->wq) { 4910 dev_err(priv->device, "failed to create workqueue\n"); 4911 return -ENOMEM; 4912 } 4913 4914 INIT_WORK(&priv->service_task, stmmac_service_task); 4915 4916 /* Override with kernel parameters if supplied XXX CRS XXX 4917 * this needs to have multiple instances 4918 */ 4919 if ((phyaddr >= 0) && (phyaddr <= 31)) 4920 priv->plat->phy_addr = phyaddr; 4921 4922 if (priv->plat->stmmac_rst) { 4923 ret = reset_control_assert(priv->plat->stmmac_rst); 4924 reset_control_deassert(priv->plat->stmmac_rst); 4925 /* Some reset controllers have only reset callback instead of 4926 * assert + deassert callbacks pair. 4927 */ 4928 if (ret == -ENOTSUPP) 4929 reset_control_reset(priv->plat->stmmac_rst); 4930 } 4931 4932 /* Init MAC and get the capabilities */ 4933 ret = stmmac_hw_init(priv); 4934 if (ret) 4935 goto error_hw_init; 4936 4937 stmmac_check_ether_addr(priv); 4938 4939 ndev->netdev_ops = &stmmac_netdev_ops; 4940 4941 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4942 NETIF_F_RXCSUM; 4943 4944 ret = stmmac_tc_init(priv, priv); 4945 if (!ret) { 4946 ndev->hw_features |= NETIF_F_HW_TC; 4947 } 4948 4949 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4950 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4951 if (priv->plat->has_gmac4) 4952 ndev->hw_features |= NETIF_F_GSO_UDP_L4; 4953 priv->tso = true; 4954 dev_info(priv->device, "TSO feature enabled\n"); 4955 } 4956 4957 if (priv->dma_cap.sphen) { 4958 ndev->hw_features |= NETIF_F_GRO; 4959 priv->sph = true; 4960 dev_info(priv->device, "SPH feature enabled\n"); 4961 } 4962 4963 if (priv->dma_cap.addr64) { 4964 ret = dma_set_mask_and_coherent(device, 4965 DMA_BIT_MASK(priv->dma_cap.addr64)); 4966 if (!ret) { 4967 dev_info(priv->device, "Using %d bits DMA width\n", 4968 priv->dma_cap.addr64); 4969 4970 /* 4971 * If more than 32 bits can be addressed, make sure to 4972 * enable enhanced addressing mode. 4973 */ 4974 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 4975 priv->plat->dma_cfg->eame = true; 4976 } else { 4977 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4978 if (ret) { 4979 dev_err(priv->device, "Failed to set DMA Mask\n"); 4980 goto error_hw_init; 4981 } 4982 4983 priv->dma_cap.addr64 = 32; 4984 } 4985 } 4986 4987 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4988 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4989 #ifdef STMMAC_VLAN_TAG_USED 4990 /* Both mac100 and gmac support receive VLAN tag detection */ 4991 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4992 if (priv->dma_cap.vlhash) { 4993 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4994 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4995 } 4996 if (priv->dma_cap.vlins) { 4997 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4998 if (priv->dma_cap.dvlan) 4999 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 5000 } 5001 #endif 5002 priv->msg_enable = netif_msg_init(debug, default_msg_level); 5003 5004 /* Initialize RSS */ 5005 rxq = priv->plat->rx_queues_to_use; 5006 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 5007 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 5008 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 5009 5010 if (priv->dma_cap.rssen && priv->plat->rss_en) 5011 ndev->features |= NETIF_F_RXHASH; 5012 5013 /* MTU range: 46 - hw-specific max */ 5014 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 5015 if (priv->plat->has_xgmac) 5016 ndev->max_mtu = XGMAC_JUMBO_LEN; 5017 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 5018 ndev->max_mtu = JUMBO_LEN; 5019 else 5020 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 5021 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 5022 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 5023 */ 5024 if ((priv->plat->maxmtu < ndev->max_mtu) && 5025 (priv->plat->maxmtu >= ndev->min_mtu)) 5026 ndev->max_mtu = priv->plat->maxmtu; 5027 else if (priv->plat->maxmtu < ndev->min_mtu) 5028 dev_warn(priv->device, 5029 "%s: warning: maxmtu having invalid value (%d)\n", 5030 __func__, priv->plat->maxmtu); 5031 5032 if (flow_ctrl) 5033 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 5034 5035 /* Setup channels NAPI */ 5036 stmmac_napi_add(ndev); 5037 5038 mutex_init(&priv->lock); 5039 5040 /* If a specific clk_csr value is passed from the platform 5041 * this means that the CSR Clock Range selection cannot be 5042 * changed at run-time and it is fixed. Viceversa the driver'll try to 5043 * set the MDC clock dynamically according to the csr actual 5044 * clock input. 5045 */ 5046 if (priv->plat->clk_csr >= 0) 5047 priv->clk_csr = priv->plat->clk_csr; 5048 else 5049 stmmac_clk_csr_set(priv); 5050 5051 stmmac_check_pcs_mode(priv); 5052 5053 if (priv->hw->pcs != STMMAC_PCS_TBI && 5054 priv->hw->pcs != STMMAC_PCS_RTBI) { 5055 /* MDIO bus Registration */ 5056 ret = stmmac_mdio_register(ndev); 5057 if (ret < 0) { 5058 dev_err(priv->device, 5059 "%s: MDIO bus (id: %d) registration failed", 5060 __func__, priv->plat->bus_id); 5061 goto error_mdio_register; 5062 } 5063 } 5064 5065 ret = stmmac_phy_setup(priv); 5066 if (ret) { 5067 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 5068 goto error_phy_setup; 5069 } 5070 5071 ret = register_netdev(ndev); 5072 if (ret) { 5073 dev_err(priv->device, "%s: ERROR %i registering the device\n", 5074 __func__, ret); 5075 goto error_netdev_register; 5076 } 5077 5078 if (priv->plat->serdes_powerup) { 5079 ret = priv->plat->serdes_powerup(ndev, 5080 priv->plat->bsp_priv); 5081 5082 if (ret < 0) 5083 goto error_serdes_powerup; 5084 } 5085 5086 #ifdef CONFIG_DEBUG_FS 5087 stmmac_init_fs(ndev); 5088 #endif 5089 5090 return ret; 5091 5092 error_serdes_powerup: 5093 unregister_netdev(ndev); 5094 error_netdev_register: 5095 phylink_destroy(priv->phylink); 5096 error_phy_setup: 5097 if (priv->hw->pcs != STMMAC_PCS_TBI && 5098 priv->hw->pcs != STMMAC_PCS_RTBI) 5099 stmmac_mdio_unregister(ndev); 5100 error_mdio_register: 5101 stmmac_napi_del(ndev); 5102 error_hw_init: 5103 destroy_workqueue(priv->wq); 5104 5105 return ret; 5106 } 5107 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 5108 5109 /** 5110 * stmmac_dvr_remove 5111 * @dev: device pointer 5112 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 5113 * changes the link status, releases the DMA descriptor rings. 5114 */ 5115 int stmmac_dvr_remove(struct device *dev) 5116 { 5117 struct net_device *ndev = dev_get_drvdata(dev); 5118 struct stmmac_priv *priv = netdev_priv(ndev); 5119 5120 netdev_info(priv->dev, "%s: removing driver", __func__); 5121 5122 stmmac_stop_all_dma(priv); 5123 5124 if (priv->plat->serdes_powerdown) 5125 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5126 5127 stmmac_mac_set(priv, priv->ioaddr, false); 5128 netif_carrier_off(ndev); 5129 unregister_netdev(ndev); 5130 #ifdef CONFIG_DEBUG_FS 5131 stmmac_exit_fs(ndev); 5132 #endif 5133 phylink_destroy(priv->phylink); 5134 if (priv->plat->stmmac_rst) 5135 reset_control_assert(priv->plat->stmmac_rst); 5136 clk_disable_unprepare(priv->plat->pclk); 5137 clk_disable_unprepare(priv->plat->stmmac_clk); 5138 if (priv->hw->pcs != STMMAC_PCS_TBI && 5139 priv->hw->pcs != STMMAC_PCS_RTBI) 5140 stmmac_mdio_unregister(ndev); 5141 destroy_workqueue(priv->wq); 5142 mutex_destroy(&priv->lock); 5143 5144 return 0; 5145 } 5146 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 5147 5148 /** 5149 * stmmac_suspend - suspend callback 5150 * @dev: device pointer 5151 * Description: this is the function to suspend the device and it is called 5152 * by the platform driver to stop the network queue, release the resources, 5153 * program the PMT register (for WoL), clean and release driver resources. 5154 */ 5155 int stmmac_suspend(struct device *dev) 5156 { 5157 struct net_device *ndev = dev_get_drvdata(dev); 5158 struct stmmac_priv *priv = netdev_priv(ndev); 5159 u32 chan; 5160 5161 if (!ndev || !netif_running(ndev)) 5162 return 0; 5163 5164 phylink_mac_change(priv->phylink, false); 5165 5166 mutex_lock(&priv->lock); 5167 5168 netif_device_detach(ndev); 5169 5170 stmmac_disable_all_queues(priv); 5171 5172 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 5173 hrtimer_cancel(&priv->tx_queue[chan].txtimer); 5174 5175 /* Stop TX/RX DMA */ 5176 stmmac_stop_all_dma(priv); 5177 5178 if (priv->plat->serdes_powerdown) 5179 priv->plat->serdes_powerdown(ndev, priv->plat->bsp_priv); 5180 5181 /* Enable Power down mode by programming the PMT regs */ 5182 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5183 stmmac_pmt(priv, priv->hw, priv->wolopts); 5184 priv->irq_wake = 1; 5185 } else { 5186 mutex_unlock(&priv->lock); 5187 rtnl_lock(); 5188 if (device_may_wakeup(priv->device)) 5189 phylink_speed_down(priv->phylink, false); 5190 phylink_stop(priv->phylink); 5191 rtnl_unlock(); 5192 mutex_lock(&priv->lock); 5193 5194 stmmac_mac_set(priv, priv->ioaddr, false); 5195 pinctrl_pm_select_sleep_state(priv->device); 5196 /* Disable clock in case of PWM is off */ 5197 clk_disable_unprepare(priv->plat->clk_ptp_ref); 5198 clk_disable_unprepare(priv->plat->pclk); 5199 clk_disable_unprepare(priv->plat->stmmac_clk); 5200 } 5201 mutex_unlock(&priv->lock); 5202 5203 priv->speed = SPEED_UNKNOWN; 5204 return 0; 5205 } 5206 EXPORT_SYMBOL_GPL(stmmac_suspend); 5207 5208 /** 5209 * stmmac_reset_queues_param - reset queue parameters 5210 * @priv: device pointer 5211 */ 5212 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 5213 { 5214 u32 rx_cnt = priv->plat->rx_queues_to_use; 5215 u32 tx_cnt = priv->plat->tx_queues_to_use; 5216 u32 queue; 5217 5218 for (queue = 0; queue < rx_cnt; queue++) { 5219 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 5220 5221 rx_q->cur_rx = 0; 5222 rx_q->dirty_rx = 0; 5223 } 5224 5225 for (queue = 0; queue < tx_cnt; queue++) { 5226 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 5227 5228 tx_q->cur_tx = 0; 5229 tx_q->dirty_tx = 0; 5230 tx_q->mss = 0; 5231 } 5232 } 5233 5234 /** 5235 * stmmac_resume - resume callback 5236 * @dev: device pointer 5237 * Description: when resume this function is invoked to setup the DMA and CORE 5238 * in a usable state. 5239 */ 5240 int stmmac_resume(struct device *dev) 5241 { 5242 struct net_device *ndev = dev_get_drvdata(dev); 5243 struct stmmac_priv *priv = netdev_priv(ndev); 5244 int ret; 5245 5246 if (!netif_running(ndev)) 5247 return 0; 5248 5249 /* Power Down bit, into the PM register, is cleared 5250 * automatically as soon as a magic packet or a Wake-up frame 5251 * is received. Anyway, it's better to manually clear 5252 * this bit because it can generate problems while resuming 5253 * from another devices (e.g. serial console). 5254 */ 5255 if (device_may_wakeup(priv->device) && priv->plat->pmt) { 5256 mutex_lock(&priv->lock); 5257 stmmac_pmt(priv, priv->hw, 0); 5258 mutex_unlock(&priv->lock); 5259 priv->irq_wake = 0; 5260 } else { 5261 pinctrl_pm_select_default_state(priv->device); 5262 /* enable the clk previously disabled */ 5263 clk_prepare_enable(priv->plat->stmmac_clk); 5264 clk_prepare_enable(priv->plat->pclk); 5265 if (priv->plat->clk_ptp_ref) 5266 clk_prepare_enable(priv->plat->clk_ptp_ref); 5267 /* reset the phy so that it's ready */ 5268 if (priv->mii) 5269 stmmac_mdio_reset(priv->mii); 5270 } 5271 5272 if (priv->plat->serdes_powerup) { 5273 ret = priv->plat->serdes_powerup(ndev, 5274 priv->plat->bsp_priv); 5275 5276 if (ret < 0) 5277 return ret; 5278 } 5279 5280 rtnl_lock(); 5281 mutex_lock(&priv->lock); 5282 5283 stmmac_reset_queues_param(priv); 5284 5285 stmmac_clear_descriptors(priv); 5286 5287 stmmac_hw_setup(ndev, false); 5288 stmmac_init_coalesce(priv); 5289 stmmac_set_rx_mode(ndev); 5290 5291 stmmac_restore_hw_vlan_rx_fltr(priv, ndev, priv->hw); 5292 5293 stmmac_enable_all_queues(priv); 5294 5295 mutex_unlock(&priv->lock); 5296 rtnl_unlock(); 5297 5298 if (!device_may_wakeup(priv->device) || !priv->plat->pmt) { 5299 rtnl_lock(); 5300 phylink_start(priv->phylink); 5301 /* We may have called phylink_speed_down before */ 5302 phylink_speed_up(priv->phylink); 5303 rtnl_unlock(); 5304 } 5305 5306 phylink_mac_change(priv->phylink, true); 5307 5308 netif_device_attach(ndev); 5309 5310 return 0; 5311 } 5312 EXPORT_SYMBOL_GPL(stmmac_resume); 5313 5314 #ifndef MODULE 5315 static int __init stmmac_cmdline_opt(char *str) 5316 { 5317 char *opt; 5318 5319 if (!str || !*str) 5320 return -EINVAL; 5321 while ((opt = strsep(&str, ",")) != NULL) { 5322 if (!strncmp(opt, "debug:", 6)) { 5323 if (kstrtoint(opt + 6, 0, &debug)) 5324 goto err; 5325 } else if (!strncmp(opt, "phyaddr:", 8)) { 5326 if (kstrtoint(opt + 8, 0, &phyaddr)) 5327 goto err; 5328 } else if (!strncmp(opt, "buf_sz:", 7)) { 5329 if (kstrtoint(opt + 7, 0, &buf_sz)) 5330 goto err; 5331 } else if (!strncmp(opt, "tc:", 3)) { 5332 if (kstrtoint(opt + 3, 0, &tc)) 5333 goto err; 5334 } else if (!strncmp(opt, "watchdog:", 9)) { 5335 if (kstrtoint(opt + 9, 0, &watchdog)) 5336 goto err; 5337 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 5338 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 5339 goto err; 5340 } else if (!strncmp(opt, "pause:", 6)) { 5341 if (kstrtoint(opt + 6, 0, &pause)) 5342 goto err; 5343 } else if (!strncmp(opt, "eee_timer:", 10)) { 5344 if (kstrtoint(opt + 10, 0, &eee_timer)) 5345 goto err; 5346 } else if (!strncmp(opt, "chain_mode:", 11)) { 5347 if (kstrtoint(opt + 11, 0, &chain_mode)) 5348 goto err; 5349 } 5350 } 5351 return 0; 5352 5353 err: 5354 pr_err("%s: ERROR broken module parameter conversion", __func__); 5355 return -EINVAL; 5356 } 5357 5358 __setup("stmmaceth=", stmmac_cmdline_opt); 5359 #endif /* MODULE */ 5360 5361 static int __init stmmac_init(void) 5362 { 5363 #ifdef CONFIG_DEBUG_FS 5364 /* Create debugfs main directory if it doesn't exist yet */ 5365 if (!stmmac_fs_dir) 5366 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 5367 register_netdevice_notifier(&stmmac_notifier); 5368 #endif 5369 5370 return 0; 5371 } 5372 5373 static void __exit stmmac_exit(void) 5374 { 5375 #ifdef CONFIG_DEBUG_FS 5376 unregister_netdevice_notifier(&stmmac_notifier); 5377 debugfs_remove_recursive(stmmac_fs_dir); 5378 #endif 5379 } 5380 5381 module_init(stmmac_init) 5382 module_exit(stmmac_exit) 5383 5384 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 5385 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 5386 MODULE_LICENSE("GPL"); 5387