1 // SPDX-License-Identifier: GPL-2.0-only 2 /******************************************************************************* 3 This is the driver for the ST MAC 10/100/1000 on-chip Ethernet controllers. 4 ST Ethernet IPs are built around a Synopsys IP Core. 5 6 Copyright(C) 2007-2011 STMicroelectronics Ltd 7 8 9 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com> 10 11 Documentation available at: 12 http://www.stlinux.com 13 Support available at: 14 https://bugzilla.stlinux.com/ 15 *******************************************************************************/ 16 17 #include <linux/clk.h> 18 #include <linux/kernel.h> 19 #include <linux/interrupt.h> 20 #include <linux/ip.h> 21 #include <linux/tcp.h> 22 #include <linux/skbuff.h> 23 #include <linux/ethtool.h> 24 #include <linux/if_ether.h> 25 #include <linux/crc32.h> 26 #include <linux/mii.h> 27 #include <linux/if.h> 28 #include <linux/if_vlan.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/slab.h> 31 #include <linux/prefetch.h> 32 #include <linux/pinctrl/consumer.h> 33 #ifdef CONFIG_DEBUG_FS 34 #include <linux/debugfs.h> 35 #include <linux/seq_file.h> 36 #endif /* CONFIG_DEBUG_FS */ 37 #include <linux/net_tstamp.h> 38 #include <linux/phylink.h> 39 #include <net/pkt_cls.h> 40 #include "stmmac_ptp.h" 41 #include "stmmac.h" 42 #include <linux/reset.h> 43 #include <linux/of_mdio.h> 44 #include "dwmac1000.h" 45 #include "dwxgmac2.h" 46 #include "hwif.h" 47 48 #define STMMAC_ALIGN(x) __ALIGN_KERNEL(x, SMP_CACHE_BYTES) 49 #define TSO_MAX_BUFF_SIZE (SZ_16K - 1) 50 51 /* Module parameters */ 52 #define TX_TIMEO 5000 53 static int watchdog = TX_TIMEO; 54 module_param(watchdog, int, 0644); 55 MODULE_PARM_DESC(watchdog, "Transmit timeout in milliseconds (default 5s)"); 56 57 static int debug = -1; 58 module_param(debug, int, 0644); 59 MODULE_PARM_DESC(debug, "Message Level (-1: default, 0: no output, 16: all)"); 60 61 static int phyaddr = -1; 62 module_param(phyaddr, int, 0444); 63 MODULE_PARM_DESC(phyaddr, "Physical device address"); 64 65 #define STMMAC_TX_THRESH (DMA_TX_SIZE / 4) 66 #define STMMAC_RX_THRESH (DMA_RX_SIZE / 4) 67 68 static int flow_ctrl = FLOW_AUTO; 69 module_param(flow_ctrl, int, 0644); 70 MODULE_PARM_DESC(flow_ctrl, "Flow control ability [on/off]"); 71 72 static int pause = PAUSE_TIME; 73 module_param(pause, int, 0644); 74 MODULE_PARM_DESC(pause, "Flow Control Pause Time"); 75 76 #define TC_DEFAULT 64 77 static int tc = TC_DEFAULT; 78 module_param(tc, int, 0644); 79 MODULE_PARM_DESC(tc, "DMA threshold control value"); 80 81 #define DEFAULT_BUFSIZE 1536 82 static int buf_sz = DEFAULT_BUFSIZE; 83 module_param(buf_sz, int, 0644); 84 MODULE_PARM_DESC(buf_sz, "DMA buffer size"); 85 86 #define STMMAC_RX_COPYBREAK 256 87 88 static const u32 default_msg_level = (NETIF_MSG_DRV | NETIF_MSG_PROBE | 89 NETIF_MSG_LINK | NETIF_MSG_IFUP | 90 NETIF_MSG_IFDOWN | NETIF_MSG_TIMER); 91 92 #define STMMAC_DEFAULT_LPI_TIMER 1000 93 static int eee_timer = STMMAC_DEFAULT_LPI_TIMER; 94 module_param(eee_timer, int, 0644); 95 MODULE_PARM_DESC(eee_timer, "LPI tx expiration time in msec"); 96 #define STMMAC_LPI_T(x) (jiffies + msecs_to_jiffies(x)) 97 98 /* By default the driver will use the ring mode to manage tx and rx descriptors, 99 * but allow user to force to use the chain instead of the ring 100 */ 101 static unsigned int chain_mode; 102 module_param(chain_mode, int, 0444); 103 MODULE_PARM_DESC(chain_mode, "To use chain instead of ring mode"); 104 105 static irqreturn_t stmmac_interrupt(int irq, void *dev_id); 106 107 #ifdef CONFIG_DEBUG_FS 108 static void stmmac_init_fs(struct net_device *dev); 109 static void stmmac_exit_fs(struct net_device *dev); 110 #endif 111 112 #define STMMAC_COAL_TIMER(x) (jiffies + usecs_to_jiffies(x)) 113 114 /** 115 * stmmac_verify_args - verify the driver parameters. 116 * Description: it checks the driver parameters and set a default in case of 117 * errors. 118 */ 119 static void stmmac_verify_args(void) 120 { 121 if (unlikely(watchdog < 0)) 122 watchdog = TX_TIMEO; 123 if (unlikely((buf_sz < DEFAULT_BUFSIZE) || (buf_sz > BUF_SIZE_16KiB))) 124 buf_sz = DEFAULT_BUFSIZE; 125 if (unlikely(flow_ctrl > 1)) 126 flow_ctrl = FLOW_AUTO; 127 else if (likely(flow_ctrl < 0)) 128 flow_ctrl = FLOW_OFF; 129 if (unlikely((pause < 0) || (pause > 0xffff))) 130 pause = PAUSE_TIME; 131 if (eee_timer < 0) 132 eee_timer = STMMAC_DEFAULT_LPI_TIMER; 133 } 134 135 /** 136 * stmmac_disable_all_queues - Disable all queues 137 * @priv: driver private structure 138 */ 139 static void stmmac_disable_all_queues(struct stmmac_priv *priv) 140 { 141 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 142 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 143 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 144 u32 queue; 145 146 for (queue = 0; queue < maxq; queue++) { 147 struct stmmac_channel *ch = &priv->channel[queue]; 148 149 if (queue < rx_queues_cnt) 150 napi_disable(&ch->rx_napi); 151 if (queue < tx_queues_cnt) 152 napi_disable(&ch->tx_napi); 153 } 154 } 155 156 /** 157 * stmmac_enable_all_queues - Enable all queues 158 * @priv: driver private structure 159 */ 160 static void stmmac_enable_all_queues(struct stmmac_priv *priv) 161 { 162 u32 rx_queues_cnt = priv->plat->rx_queues_to_use; 163 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 164 u32 maxq = max(rx_queues_cnt, tx_queues_cnt); 165 u32 queue; 166 167 for (queue = 0; queue < maxq; queue++) { 168 struct stmmac_channel *ch = &priv->channel[queue]; 169 170 if (queue < rx_queues_cnt) 171 napi_enable(&ch->rx_napi); 172 if (queue < tx_queues_cnt) 173 napi_enable(&ch->tx_napi); 174 } 175 } 176 177 /** 178 * stmmac_stop_all_queues - Stop all queues 179 * @priv: driver private structure 180 */ 181 static void stmmac_stop_all_queues(struct stmmac_priv *priv) 182 { 183 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 184 u32 queue; 185 186 for (queue = 0; queue < tx_queues_cnt; queue++) 187 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 188 } 189 190 /** 191 * stmmac_start_all_queues - Start all queues 192 * @priv: driver private structure 193 */ 194 static void stmmac_start_all_queues(struct stmmac_priv *priv) 195 { 196 u32 tx_queues_cnt = priv->plat->tx_queues_to_use; 197 u32 queue; 198 199 for (queue = 0; queue < tx_queues_cnt; queue++) 200 netif_tx_start_queue(netdev_get_tx_queue(priv->dev, queue)); 201 } 202 203 static void stmmac_service_event_schedule(struct stmmac_priv *priv) 204 { 205 if (!test_bit(STMMAC_DOWN, &priv->state) && 206 !test_and_set_bit(STMMAC_SERVICE_SCHED, &priv->state)) 207 queue_work(priv->wq, &priv->service_task); 208 } 209 210 static void stmmac_global_err(struct stmmac_priv *priv) 211 { 212 netif_carrier_off(priv->dev); 213 set_bit(STMMAC_RESET_REQUESTED, &priv->state); 214 stmmac_service_event_schedule(priv); 215 } 216 217 /** 218 * stmmac_clk_csr_set - dynamically set the MDC clock 219 * @priv: driver private structure 220 * Description: this is to dynamically set the MDC clock according to the csr 221 * clock input. 222 * Note: 223 * If a specific clk_csr value is passed from the platform 224 * this means that the CSR Clock Range selection cannot be 225 * changed at run-time and it is fixed (as reported in the driver 226 * documentation). Viceversa the driver will try to set the MDC 227 * clock dynamically according to the actual clock input. 228 */ 229 static void stmmac_clk_csr_set(struct stmmac_priv *priv) 230 { 231 u32 clk_rate; 232 233 clk_rate = clk_get_rate(priv->plat->stmmac_clk); 234 235 /* Platform provided default clk_csr would be assumed valid 236 * for all other cases except for the below mentioned ones. 237 * For values higher than the IEEE 802.3 specified frequency 238 * we can not estimate the proper divider as it is not known 239 * the frequency of clk_csr_i. So we do not change the default 240 * divider. 241 */ 242 if (!(priv->clk_csr & MAC_CSR_H_FRQ_MASK)) { 243 if (clk_rate < CSR_F_35M) 244 priv->clk_csr = STMMAC_CSR_20_35M; 245 else if ((clk_rate >= CSR_F_35M) && (clk_rate < CSR_F_60M)) 246 priv->clk_csr = STMMAC_CSR_35_60M; 247 else if ((clk_rate >= CSR_F_60M) && (clk_rate < CSR_F_100M)) 248 priv->clk_csr = STMMAC_CSR_60_100M; 249 else if ((clk_rate >= CSR_F_100M) && (clk_rate < CSR_F_150M)) 250 priv->clk_csr = STMMAC_CSR_100_150M; 251 else if ((clk_rate >= CSR_F_150M) && (clk_rate < CSR_F_250M)) 252 priv->clk_csr = STMMAC_CSR_150_250M; 253 else if ((clk_rate >= CSR_F_250M) && (clk_rate < CSR_F_300M)) 254 priv->clk_csr = STMMAC_CSR_250_300M; 255 } 256 257 if (priv->plat->has_sun8i) { 258 if (clk_rate > 160000000) 259 priv->clk_csr = 0x03; 260 else if (clk_rate > 80000000) 261 priv->clk_csr = 0x02; 262 else if (clk_rate > 40000000) 263 priv->clk_csr = 0x01; 264 else 265 priv->clk_csr = 0; 266 } 267 268 if (priv->plat->has_xgmac) { 269 if (clk_rate > 400000000) 270 priv->clk_csr = 0x5; 271 else if (clk_rate > 350000000) 272 priv->clk_csr = 0x4; 273 else if (clk_rate > 300000000) 274 priv->clk_csr = 0x3; 275 else if (clk_rate > 250000000) 276 priv->clk_csr = 0x2; 277 else if (clk_rate > 150000000) 278 priv->clk_csr = 0x1; 279 else 280 priv->clk_csr = 0x0; 281 } 282 } 283 284 static void print_pkt(unsigned char *buf, int len) 285 { 286 pr_debug("len = %d byte, buf addr: 0x%p\n", len, buf); 287 print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, buf, len); 288 } 289 290 static inline u32 stmmac_tx_avail(struct stmmac_priv *priv, u32 queue) 291 { 292 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 293 u32 avail; 294 295 if (tx_q->dirty_tx > tx_q->cur_tx) 296 avail = tx_q->dirty_tx - tx_q->cur_tx - 1; 297 else 298 avail = DMA_TX_SIZE - tx_q->cur_tx + tx_q->dirty_tx - 1; 299 300 return avail; 301 } 302 303 /** 304 * stmmac_rx_dirty - Get RX queue dirty 305 * @priv: driver private structure 306 * @queue: RX queue index 307 */ 308 static inline u32 stmmac_rx_dirty(struct stmmac_priv *priv, u32 queue) 309 { 310 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 311 u32 dirty; 312 313 if (rx_q->dirty_rx <= rx_q->cur_rx) 314 dirty = rx_q->cur_rx - rx_q->dirty_rx; 315 else 316 dirty = DMA_RX_SIZE - rx_q->dirty_rx + rx_q->cur_rx; 317 318 return dirty; 319 } 320 321 /** 322 * stmmac_enable_eee_mode - check and enter in LPI mode 323 * @priv: driver private structure 324 * Description: this function is to verify and enter in LPI mode in case of 325 * EEE. 326 */ 327 static void stmmac_enable_eee_mode(struct stmmac_priv *priv) 328 { 329 u32 tx_cnt = priv->plat->tx_queues_to_use; 330 u32 queue; 331 332 /* check if all TX queues have the work finished */ 333 for (queue = 0; queue < tx_cnt; queue++) { 334 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 335 336 if (tx_q->dirty_tx != tx_q->cur_tx) 337 return; /* still unfinished work */ 338 } 339 340 /* Check and enter in LPI mode */ 341 if (!priv->tx_path_in_lpi_mode) 342 stmmac_set_eee_mode(priv, priv->hw, 343 priv->plat->en_tx_lpi_clockgating); 344 } 345 346 /** 347 * stmmac_disable_eee_mode - disable and exit from LPI mode 348 * @priv: driver private structure 349 * Description: this function is to exit and disable EEE in case of 350 * LPI state is true. This is called by the xmit. 351 */ 352 void stmmac_disable_eee_mode(struct stmmac_priv *priv) 353 { 354 stmmac_reset_eee_mode(priv, priv->hw); 355 del_timer_sync(&priv->eee_ctrl_timer); 356 priv->tx_path_in_lpi_mode = false; 357 } 358 359 /** 360 * stmmac_eee_ctrl_timer - EEE TX SW timer. 361 * @arg : data hook 362 * Description: 363 * if there is no data transfer and if we are not in LPI state, 364 * then MAC Transmitter can be moved to LPI state. 365 */ 366 static void stmmac_eee_ctrl_timer(struct timer_list *t) 367 { 368 struct stmmac_priv *priv = from_timer(priv, t, eee_ctrl_timer); 369 370 stmmac_enable_eee_mode(priv); 371 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 372 } 373 374 /** 375 * stmmac_eee_init - init EEE 376 * @priv: driver private structure 377 * Description: 378 * if the GMAC supports the EEE (from the HW cap reg) and the phy device 379 * can also manage EEE, this function enable the LPI state and start related 380 * timer. 381 */ 382 bool stmmac_eee_init(struct stmmac_priv *priv) 383 { 384 int tx_lpi_timer = priv->tx_lpi_timer; 385 386 /* Using PCS we cannot dial with the phy registers at this stage 387 * so we do not support extra feature like EEE. 388 */ 389 if ((priv->hw->pcs == STMMAC_PCS_RGMII) || 390 (priv->hw->pcs == STMMAC_PCS_TBI) || 391 (priv->hw->pcs == STMMAC_PCS_RTBI)) 392 return false; 393 394 /* Check if MAC core supports the EEE feature. */ 395 if (!priv->dma_cap.eee) 396 return false; 397 398 mutex_lock(&priv->lock); 399 400 /* Check if it needs to be deactivated */ 401 if (!priv->eee_active) { 402 if (priv->eee_enabled) { 403 netdev_dbg(priv->dev, "disable EEE\n"); 404 del_timer_sync(&priv->eee_ctrl_timer); 405 stmmac_set_eee_timer(priv, priv->hw, 0, tx_lpi_timer); 406 } 407 mutex_unlock(&priv->lock); 408 return false; 409 } 410 411 if (priv->eee_active && !priv->eee_enabled) { 412 timer_setup(&priv->eee_ctrl_timer, stmmac_eee_ctrl_timer, 0); 413 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 414 stmmac_set_eee_timer(priv, priv->hw, STMMAC_DEFAULT_LIT_LS, 415 tx_lpi_timer); 416 } 417 418 mutex_unlock(&priv->lock); 419 netdev_dbg(priv->dev, "Energy-Efficient Ethernet initialized\n"); 420 return true; 421 } 422 423 /* stmmac_get_tx_hwtstamp - get HW TX timestamps 424 * @priv: driver private structure 425 * @p : descriptor pointer 426 * @skb : the socket buffer 427 * Description : 428 * This function will read timestamp from the descriptor & pass it to stack. 429 * and also perform some sanity checks. 430 */ 431 static void stmmac_get_tx_hwtstamp(struct stmmac_priv *priv, 432 struct dma_desc *p, struct sk_buff *skb) 433 { 434 struct skb_shared_hwtstamps shhwtstamp; 435 bool found = false; 436 u64 ns = 0; 437 438 if (!priv->hwts_tx_en) 439 return; 440 441 /* exit if skb doesn't support hw tstamp */ 442 if (likely(!skb || !(skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS))) 443 return; 444 445 /* check tx tstamp status */ 446 if (stmmac_get_tx_timestamp_status(priv, p)) { 447 stmmac_get_timestamp(priv, p, priv->adv_ts, &ns); 448 found = true; 449 } else if (!stmmac_get_mac_tx_timestamp(priv, priv->hw, &ns)) { 450 found = true; 451 } 452 453 if (found) { 454 memset(&shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 455 shhwtstamp.hwtstamp = ns_to_ktime(ns); 456 457 netdev_dbg(priv->dev, "get valid TX hw timestamp %llu\n", ns); 458 /* pass tstamp to stack */ 459 skb_tstamp_tx(skb, &shhwtstamp); 460 } 461 } 462 463 /* stmmac_get_rx_hwtstamp - get HW RX timestamps 464 * @priv: driver private structure 465 * @p : descriptor pointer 466 * @np : next descriptor pointer 467 * @skb : the socket buffer 468 * Description : 469 * This function will read received packet's timestamp from the descriptor 470 * and pass it to stack. It also perform some sanity checks. 471 */ 472 static void stmmac_get_rx_hwtstamp(struct stmmac_priv *priv, struct dma_desc *p, 473 struct dma_desc *np, struct sk_buff *skb) 474 { 475 struct skb_shared_hwtstamps *shhwtstamp = NULL; 476 struct dma_desc *desc = p; 477 u64 ns = 0; 478 479 if (!priv->hwts_rx_en) 480 return; 481 /* For GMAC4, the valid timestamp is from CTX next desc. */ 482 if (priv->plat->has_gmac4 || priv->plat->has_xgmac) 483 desc = np; 484 485 /* Check if timestamp is available */ 486 if (stmmac_get_rx_timestamp_status(priv, p, np, priv->adv_ts)) { 487 stmmac_get_timestamp(priv, desc, priv->adv_ts, &ns); 488 netdev_dbg(priv->dev, "get valid RX hw timestamp %llu\n", ns); 489 shhwtstamp = skb_hwtstamps(skb); 490 memset(shhwtstamp, 0, sizeof(struct skb_shared_hwtstamps)); 491 shhwtstamp->hwtstamp = ns_to_ktime(ns); 492 } else { 493 netdev_dbg(priv->dev, "cannot get RX hw timestamp\n"); 494 } 495 } 496 497 /** 498 * stmmac_hwtstamp_set - control hardware timestamping. 499 * @dev: device pointer. 500 * @ifr: An IOCTL specific structure, that can contain a pointer to 501 * a proprietary structure used to pass information to the driver. 502 * Description: 503 * This function configures the MAC to enable/disable both outgoing(TX) 504 * and incoming(RX) packets time stamping based on user input. 505 * Return Value: 506 * 0 on success and an appropriate -ve integer on failure. 507 */ 508 static int stmmac_hwtstamp_set(struct net_device *dev, struct ifreq *ifr) 509 { 510 struct stmmac_priv *priv = netdev_priv(dev); 511 struct hwtstamp_config config; 512 struct timespec64 now; 513 u64 temp = 0; 514 u32 ptp_v2 = 0; 515 u32 tstamp_all = 0; 516 u32 ptp_over_ipv4_udp = 0; 517 u32 ptp_over_ipv6_udp = 0; 518 u32 ptp_over_ethernet = 0; 519 u32 snap_type_sel = 0; 520 u32 ts_master_en = 0; 521 u32 ts_event_en = 0; 522 u32 sec_inc = 0; 523 u32 value = 0; 524 bool xmac; 525 526 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 527 528 if (!(priv->dma_cap.time_stamp || priv->adv_ts)) { 529 netdev_alert(priv->dev, "No support for HW time stamping\n"); 530 priv->hwts_tx_en = 0; 531 priv->hwts_rx_en = 0; 532 533 return -EOPNOTSUPP; 534 } 535 536 if (copy_from_user(&config, ifr->ifr_data, 537 sizeof(config))) 538 return -EFAULT; 539 540 netdev_dbg(priv->dev, "%s config flags:0x%x, tx_type:0x%x, rx_filter:0x%x\n", 541 __func__, config.flags, config.tx_type, config.rx_filter); 542 543 /* reserved for future extensions */ 544 if (config.flags) 545 return -EINVAL; 546 547 if (config.tx_type != HWTSTAMP_TX_OFF && 548 config.tx_type != HWTSTAMP_TX_ON) 549 return -ERANGE; 550 551 if (priv->adv_ts) { 552 switch (config.rx_filter) { 553 case HWTSTAMP_FILTER_NONE: 554 /* time stamp no incoming packet at all */ 555 config.rx_filter = HWTSTAMP_FILTER_NONE; 556 break; 557 558 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 559 /* PTP v1, UDP, any kind of event packet */ 560 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 561 /* 'xmac' hardware can support Sync, Pdelay_Req and 562 * Pdelay_resp by setting bit14 and bits17/16 to 01 563 * This leaves Delay_Req timestamps out. 564 * Enable all events *and* general purpose message 565 * timestamping 566 */ 567 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 568 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 569 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 570 break; 571 572 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 573 /* PTP v1, UDP, Sync packet */ 574 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_SYNC; 575 /* take time stamp for SYNC messages only */ 576 ts_event_en = PTP_TCR_TSEVNTENA; 577 578 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 579 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 580 break; 581 582 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 583 /* PTP v1, UDP, Delay_req packet */ 584 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ; 585 /* take time stamp for Delay_Req messages only */ 586 ts_master_en = PTP_TCR_TSMSTRENA; 587 ts_event_en = PTP_TCR_TSEVNTENA; 588 589 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 590 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 591 break; 592 593 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 594 /* PTP v2, UDP, any kind of event packet */ 595 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT; 596 ptp_v2 = PTP_TCR_TSVER2ENA; 597 /* take time stamp for all event messages */ 598 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 599 600 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 601 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 602 break; 603 604 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 605 /* PTP v2, UDP, Sync packet */ 606 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_SYNC; 607 ptp_v2 = PTP_TCR_TSVER2ENA; 608 /* take time stamp for SYNC messages only */ 609 ts_event_en = PTP_TCR_TSEVNTENA; 610 611 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 612 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 613 break; 614 615 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 616 /* PTP v2, UDP, Delay_req packet */ 617 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ; 618 ptp_v2 = PTP_TCR_TSVER2ENA; 619 /* take time stamp for Delay_Req messages only */ 620 ts_master_en = PTP_TCR_TSMSTRENA; 621 ts_event_en = PTP_TCR_TSEVNTENA; 622 623 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 624 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 625 break; 626 627 case HWTSTAMP_FILTER_PTP_V2_EVENT: 628 /* PTP v2/802.AS1 any layer, any kind of event packet */ 629 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT; 630 ptp_v2 = PTP_TCR_TSVER2ENA; 631 snap_type_sel = PTP_TCR_SNAPTYPSEL_1; 632 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 633 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 634 ptp_over_ethernet = PTP_TCR_TSIPENA; 635 break; 636 637 case HWTSTAMP_FILTER_PTP_V2_SYNC: 638 /* PTP v2/802.AS1, any layer, Sync packet */ 639 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_SYNC; 640 ptp_v2 = PTP_TCR_TSVER2ENA; 641 /* take time stamp for SYNC messages only */ 642 ts_event_en = PTP_TCR_TSEVNTENA; 643 644 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 645 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 646 ptp_over_ethernet = PTP_TCR_TSIPENA; 647 break; 648 649 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 650 /* PTP v2/802.AS1, any layer, Delay_req packet */ 651 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_DELAY_REQ; 652 ptp_v2 = PTP_TCR_TSVER2ENA; 653 /* take time stamp for Delay_Req messages only */ 654 ts_master_en = PTP_TCR_TSMSTRENA; 655 ts_event_en = PTP_TCR_TSEVNTENA; 656 657 ptp_over_ipv4_udp = PTP_TCR_TSIPV4ENA; 658 ptp_over_ipv6_udp = PTP_TCR_TSIPV6ENA; 659 ptp_over_ethernet = PTP_TCR_TSIPENA; 660 break; 661 662 case HWTSTAMP_FILTER_NTP_ALL: 663 case HWTSTAMP_FILTER_ALL: 664 /* time stamp any incoming packet */ 665 config.rx_filter = HWTSTAMP_FILTER_ALL; 666 tstamp_all = PTP_TCR_TSENALL; 667 break; 668 669 default: 670 return -ERANGE; 671 } 672 } else { 673 switch (config.rx_filter) { 674 case HWTSTAMP_FILTER_NONE: 675 config.rx_filter = HWTSTAMP_FILTER_NONE; 676 break; 677 default: 678 /* PTP v1, UDP, any kind of event packet */ 679 config.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT; 680 break; 681 } 682 } 683 priv->hwts_rx_en = ((config.rx_filter == HWTSTAMP_FILTER_NONE) ? 0 : 1); 684 priv->hwts_tx_en = config.tx_type == HWTSTAMP_TX_ON; 685 686 if (!priv->hwts_tx_en && !priv->hwts_rx_en) 687 stmmac_config_hw_tstamping(priv, priv->ptpaddr, 0); 688 else { 689 value = (PTP_TCR_TSENA | PTP_TCR_TSCFUPDT | PTP_TCR_TSCTRLSSR | 690 tstamp_all | ptp_v2 | ptp_over_ethernet | 691 ptp_over_ipv6_udp | ptp_over_ipv4_udp | ts_event_en | 692 ts_master_en | snap_type_sel); 693 stmmac_config_hw_tstamping(priv, priv->ptpaddr, value); 694 695 /* program Sub Second Increment reg */ 696 stmmac_config_sub_second_increment(priv, 697 priv->ptpaddr, priv->plat->clk_ptp_rate, 698 xmac, &sec_inc); 699 temp = div_u64(1000000000ULL, sec_inc); 700 701 /* Store sub second increment and flags for later use */ 702 priv->sub_second_inc = sec_inc; 703 priv->systime_flags = value; 704 705 /* calculate default added value: 706 * formula is : 707 * addend = (2^32)/freq_div_ratio; 708 * where, freq_div_ratio = 1e9ns/sec_inc 709 */ 710 temp = (u64)(temp << 32); 711 priv->default_addend = div_u64(temp, priv->plat->clk_ptp_rate); 712 stmmac_config_addend(priv, priv->ptpaddr, priv->default_addend); 713 714 /* initialize system time */ 715 ktime_get_real_ts64(&now); 716 717 /* lower 32 bits of tv_sec are safe until y2106 */ 718 stmmac_init_systime(priv, priv->ptpaddr, 719 (u32)now.tv_sec, now.tv_nsec); 720 } 721 722 memcpy(&priv->tstamp_config, &config, sizeof(config)); 723 724 return copy_to_user(ifr->ifr_data, &config, 725 sizeof(config)) ? -EFAULT : 0; 726 } 727 728 /** 729 * stmmac_hwtstamp_get - read hardware timestamping. 730 * @dev: device pointer. 731 * @ifr: An IOCTL specific structure, that can contain a pointer to 732 * a proprietary structure used to pass information to the driver. 733 * Description: 734 * This function obtain the current hardware timestamping settings 735 as requested. 736 */ 737 static int stmmac_hwtstamp_get(struct net_device *dev, struct ifreq *ifr) 738 { 739 struct stmmac_priv *priv = netdev_priv(dev); 740 struct hwtstamp_config *config = &priv->tstamp_config; 741 742 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 743 return -EOPNOTSUPP; 744 745 return copy_to_user(ifr->ifr_data, config, 746 sizeof(*config)) ? -EFAULT : 0; 747 } 748 749 /** 750 * stmmac_init_ptp - init PTP 751 * @priv: driver private structure 752 * Description: this is to verify if the HW supports the PTPv1 or PTPv2. 753 * This is done by looking at the HW cap. register. 754 * This function also registers the ptp driver. 755 */ 756 static int stmmac_init_ptp(struct stmmac_priv *priv) 757 { 758 bool xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 759 760 if (!(priv->dma_cap.time_stamp || priv->dma_cap.atime_stamp)) 761 return -EOPNOTSUPP; 762 763 priv->adv_ts = 0; 764 /* Check if adv_ts can be enabled for dwmac 4.x / xgmac core */ 765 if (xmac && priv->dma_cap.atime_stamp) 766 priv->adv_ts = 1; 767 /* Dwmac 3.x core with extend_desc can support adv_ts */ 768 else if (priv->extend_desc && priv->dma_cap.atime_stamp) 769 priv->adv_ts = 1; 770 771 if (priv->dma_cap.time_stamp) 772 netdev_info(priv->dev, "IEEE 1588-2002 Timestamp supported\n"); 773 774 if (priv->adv_ts) 775 netdev_info(priv->dev, 776 "IEEE 1588-2008 Advanced Timestamp supported\n"); 777 778 priv->hwts_tx_en = 0; 779 priv->hwts_rx_en = 0; 780 781 stmmac_ptp_register(priv); 782 783 return 0; 784 } 785 786 static void stmmac_release_ptp(struct stmmac_priv *priv) 787 { 788 if (priv->plat->clk_ptp_ref) 789 clk_disable_unprepare(priv->plat->clk_ptp_ref); 790 stmmac_ptp_unregister(priv); 791 } 792 793 /** 794 * stmmac_mac_flow_ctrl - Configure flow control in all queues 795 * @priv: driver private structure 796 * Description: It is used for configuring the flow control in all queues 797 */ 798 static void stmmac_mac_flow_ctrl(struct stmmac_priv *priv, u32 duplex) 799 { 800 u32 tx_cnt = priv->plat->tx_queues_to_use; 801 802 stmmac_flow_ctrl(priv, priv->hw, duplex, priv->flow_ctrl, 803 priv->pause, tx_cnt); 804 } 805 806 static void stmmac_validate(struct phylink_config *config, 807 unsigned long *supported, 808 struct phylink_link_state *state) 809 { 810 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 811 __ETHTOOL_DECLARE_LINK_MODE_MASK(mac_supported) = { 0, }; 812 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 813 int tx_cnt = priv->plat->tx_queues_to_use; 814 int max_speed = priv->plat->max_speed; 815 816 phylink_set(mac_supported, 10baseT_Half); 817 phylink_set(mac_supported, 10baseT_Full); 818 phylink_set(mac_supported, 100baseT_Half); 819 phylink_set(mac_supported, 100baseT_Full); 820 phylink_set(mac_supported, 1000baseT_Half); 821 phylink_set(mac_supported, 1000baseT_Full); 822 phylink_set(mac_supported, 1000baseKX_Full); 823 824 phylink_set(mac_supported, Autoneg); 825 phylink_set(mac_supported, Pause); 826 phylink_set(mac_supported, Asym_Pause); 827 phylink_set_port_modes(mac_supported); 828 829 /* Cut down 1G if asked to */ 830 if ((max_speed > 0) && (max_speed < 1000)) { 831 phylink_set(mask, 1000baseT_Full); 832 phylink_set(mask, 1000baseX_Full); 833 } else if (priv->plat->has_xgmac) { 834 if (!max_speed || (max_speed >= 2500)) { 835 phylink_set(mac_supported, 2500baseT_Full); 836 phylink_set(mac_supported, 2500baseX_Full); 837 } 838 if (!max_speed || (max_speed >= 5000)) { 839 phylink_set(mac_supported, 5000baseT_Full); 840 } 841 if (!max_speed || (max_speed >= 10000)) { 842 phylink_set(mac_supported, 10000baseSR_Full); 843 phylink_set(mac_supported, 10000baseLR_Full); 844 phylink_set(mac_supported, 10000baseER_Full); 845 phylink_set(mac_supported, 10000baseLRM_Full); 846 phylink_set(mac_supported, 10000baseT_Full); 847 phylink_set(mac_supported, 10000baseKX4_Full); 848 phylink_set(mac_supported, 10000baseKR_Full); 849 } 850 } 851 852 /* Half-Duplex can only work with single queue */ 853 if (tx_cnt > 1) { 854 phylink_set(mask, 10baseT_Half); 855 phylink_set(mask, 100baseT_Half); 856 phylink_set(mask, 1000baseT_Half); 857 } 858 859 bitmap_and(supported, supported, mac_supported, 860 __ETHTOOL_LINK_MODE_MASK_NBITS); 861 bitmap_andnot(supported, supported, mask, 862 __ETHTOOL_LINK_MODE_MASK_NBITS); 863 bitmap_and(state->advertising, state->advertising, mac_supported, 864 __ETHTOOL_LINK_MODE_MASK_NBITS); 865 bitmap_andnot(state->advertising, state->advertising, mask, 866 __ETHTOOL_LINK_MODE_MASK_NBITS); 867 } 868 869 static int stmmac_mac_link_state(struct phylink_config *config, 870 struct phylink_link_state *state) 871 { 872 return -EOPNOTSUPP; 873 } 874 875 static void stmmac_mac_config(struct phylink_config *config, unsigned int mode, 876 const struct phylink_link_state *state) 877 { 878 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 879 u32 ctrl; 880 881 ctrl = readl(priv->ioaddr + MAC_CTRL_REG); 882 ctrl &= ~priv->hw->link.speed_mask; 883 884 if (state->interface == PHY_INTERFACE_MODE_USXGMII) { 885 switch (state->speed) { 886 case SPEED_10000: 887 ctrl |= priv->hw->link.xgmii.speed10000; 888 break; 889 case SPEED_5000: 890 ctrl |= priv->hw->link.xgmii.speed5000; 891 break; 892 case SPEED_2500: 893 ctrl |= priv->hw->link.xgmii.speed2500; 894 break; 895 default: 896 return; 897 } 898 } else { 899 switch (state->speed) { 900 case SPEED_2500: 901 ctrl |= priv->hw->link.speed2500; 902 break; 903 case SPEED_1000: 904 ctrl |= priv->hw->link.speed1000; 905 break; 906 case SPEED_100: 907 ctrl |= priv->hw->link.speed100; 908 break; 909 case SPEED_10: 910 ctrl |= priv->hw->link.speed10; 911 break; 912 default: 913 return; 914 } 915 } 916 917 priv->speed = state->speed; 918 919 if (priv->plat->fix_mac_speed) 920 priv->plat->fix_mac_speed(priv->plat->bsp_priv, state->speed); 921 922 if (!state->duplex) 923 ctrl &= ~priv->hw->link.duplex; 924 else 925 ctrl |= priv->hw->link.duplex; 926 927 /* Flow Control operation */ 928 if (state->pause) 929 stmmac_mac_flow_ctrl(priv, state->duplex); 930 931 writel(ctrl, priv->ioaddr + MAC_CTRL_REG); 932 } 933 934 static void stmmac_mac_an_restart(struct phylink_config *config) 935 { 936 /* Not Supported */ 937 } 938 939 static void stmmac_mac_link_down(struct phylink_config *config, 940 unsigned int mode, phy_interface_t interface) 941 { 942 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 943 944 stmmac_mac_set(priv, priv->ioaddr, false); 945 priv->eee_active = false; 946 stmmac_eee_init(priv); 947 stmmac_set_eee_pls(priv, priv->hw, false); 948 } 949 950 static void stmmac_mac_link_up(struct phylink_config *config, 951 unsigned int mode, phy_interface_t interface, 952 struct phy_device *phy) 953 { 954 struct stmmac_priv *priv = netdev_priv(to_net_dev(config->dev)); 955 956 stmmac_mac_set(priv, priv->ioaddr, true); 957 if (phy && priv->dma_cap.eee) { 958 priv->eee_active = phy_init_eee(phy, 1) >= 0; 959 priv->eee_enabled = stmmac_eee_init(priv); 960 stmmac_set_eee_pls(priv, priv->hw, true); 961 } 962 } 963 964 static const struct phylink_mac_ops stmmac_phylink_mac_ops = { 965 .validate = stmmac_validate, 966 .mac_link_state = stmmac_mac_link_state, 967 .mac_config = stmmac_mac_config, 968 .mac_an_restart = stmmac_mac_an_restart, 969 .mac_link_down = stmmac_mac_link_down, 970 .mac_link_up = stmmac_mac_link_up, 971 }; 972 973 /** 974 * stmmac_check_pcs_mode - verify if RGMII/SGMII is supported 975 * @priv: driver private structure 976 * Description: this is to verify if the HW supports the PCS. 977 * Physical Coding Sublayer (PCS) interface that can be used when the MAC is 978 * configured for the TBI, RTBI, or SGMII PHY interface. 979 */ 980 static void stmmac_check_pcs_mode(struct stmmac_priv *priv) 981 { 982 int interface = priv->plat->interface; 983 984 if (priv->dma_cap.pcs) { 985 if ((interface == PHY_INTERFACE_MODE_RGMII) || 986 (interface == PHY_INTERFACE_MODE_RGMII_ID) || 987 (interface == PHY_INTERFACE_MODE_RGMII_RXID) || 988 (interface == PHY_INTERFACE_MODE_RGMII_TXID)) { 989 netdev_dbg(priv->dev, "PCS RGMII support enabled\n"); 990 priv->hw->pcs = STMMAC_PCS_RGMII; 991 } else if (interface == PHY_INTERFACE_MODE_SGMII) { 992 netdev_dbg(priv->dev, "PCS SGMII support enabled\n"); 993 priv->hw->pcs = STMMAC_PCS_SGMII; 994 } 995 } 996 } 997 998 /** 999 * stmmac_init_phy - PHY initialization 1000 * @dev: net device structure 1001 * Description: it initializes the driver's PHY state, and attaches the PHY 1002 * to the mac driver. 1003 * Return value: 1004 * 0 on success 1005 */ 1006 static int stmmac_init_phy(struct net_device *dev) 1007 { 1008 struct stmmac_priv *priv = netdev_priv(dev); 1009 struct device_node *node; 1010 int ret; 1011 1012 node = priv->plat->phylink_node; 1013 1014 if (node) 1015 ret = phylink_of_phy_connect(priv->phylink, node, 0); 1016 1017 /* Some DT bindings do not set-up the PHY handle. Let's try to 1018 * manually parse it 1019 */ 1020 if (!node || ret) { 1021 int addr = priv->plat->phy_addr; 1022 struct phy_device *phydev; 1023 1024 phydev = mdiobus_get_phy(priv->mii, addr); 1025 if (!phydev) { 1026 netdev_err(priv->dev, "no phy at addr %d\n", addr); 1027 return -ENODEV; 1028 } 1029 1030 ret = phylink_connect_phy(priv->phylink, phydev); 1031 } 1032 1033 return ret; 1034 } 1035 1036 static int stmmac_phy_setup(struct stmmac_priv *priv) 1037 { 1038 struct fwnode_handle *fwnode = of_fwnode_handle(priv->plat->phylink_node); 1039 int mode = priv->plat->phy_interface; 1040 struct phylink *phylink; 1041 1042 priv->phylink_config.dev = &priv->dev->dev; 1043 priv->phylink_config.type = PHYLINK_NETDEV; 1044 1045 phylink = phylink_create(&priv->phylink_config, fwnode, 1046 mode, &stmmac_phylink_mac_ops); 1047 if (IS_ERR(phylink)) 1048 return PTR_ERR(phylink); 1049 1050 priv->phylink = phylink; 1051 return 0; 1052 } 1053 1054 static void stmmac_display_rx_rings(struct stmmac_priv *priv) 1055 { 1056 u32 rx_cnt = priv->plat->rx_queues_to_use; 1057 void *head_rx; 1058 u32 queue; 1059 1060 /* Display RX rings */ 1061 for (queue = 0; queue < rx_cnt; queue++) { 1062 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1063 1064 pr_info("\tRX Queue %u rings\n", queue); 1065 1066 if (priv->extend_desc) 1067 head_rx = (void *)rx_q->dma_erx; 1068 else 1069 head_rx = (void *)rx_q->dma_rx; 1070 1071 /* Display RX ring */ 1072 stmmac_display_ring(priv, head_rx, DMA_RX_SIZE, true); 1073 } 1074 } 1075 1076 static void stmmac_display_tx_rings(struct stmmac_priv *priv) 1077 { 1078 u32 tx_cnt = priv->plat->tx_queues_to_use; 1079 void *head_tx; 1080 u32 queue; 1081 1082 /* Display TX rings */ 1083 for (queue = 0; queue < tx_cnt; queue++) { 1084 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1085 1086 pr_info("\tTX Queue %d rings\n", queue); 1087 1088 if (priv->extend_desc) 1089 head_tx = (void *)tx_q->dma_etx; 1090 else 1091 head_tx = (void *)tx_q->dma_tx; 1092 1093 stmmac_display_ring(priv, head_tx, DMA_TX_SIZE, false); 1094 } 1095 } 1096 1097 static void stmmac_display_rings(struct stmmac_priv *priv) 1098 { 1099 /* Display RX ring */ 1100 stmmac_display_rx_rings(priv); 1101 1102 /* Display TX ring */ 1103 stmmac_display_tx_rings(priv); 1104 } 1105 1106 static int stmmac_set_bfsize(int mtu, int bufsize) 1107 { 1108 int ret = bufsize; 1109 1110 if (mtu >= BUF_SIZE_4KiB) 1111 ret = BUF_SIZE_8KiB; 1112 else if (mtu >= BUF_SIZE_2KiB) 1113 ret = BUF_SIZE_4KiB; 1114 else if (mtu > DEFAULT_BUFSIZE) 1115 ret = BUF_SIZE_2KiB; 1116 else 1117 ret = DEFAULT_BUFSIZE; 1118 1119 return ret; 1120 } 1121 1122 /** 1123 * stmmac_clear_rx_descriptors - clear RX descriptors 1124 * @priv: driver private structure 1125 * @queue: RX queue index 1126 * Description: this function is called to clear the RX descriptors 1127 * in case of both basic and extended descriptors are used. 1128 */ 1129 static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue) 1130 { 1131 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1132 int i; 1133 1134 /* Clear the RX descriptors */ 1135 for (i = 0; i < DMA_RX_SIZE; i++) 1136 if (priv->extend_desc) 1137 stmmac_init_rx_desc(priv, &rx_q->dma_erx[i].basic, 1138 priv->use_riwt, priv->mode, 1139 (i == DMA_RX_SIZE - 1), 1140 priv->dma_buf_sz); 1141 else 1142 stmmac_init_rx_desc(priv, &rx_q->dma_rx[i], 1143 priv->use_riwt, priv->mode, 1144 (i == DMA_RX_SIZE - 1), 1145 priv->dma_buf_sz); 1146 } 1147 1148 /** 1149 * stmmac_clear_tx_descriptors - clear tx descriptors 1150 * @priv: driver private structure 1151 * @queue: TX queue index. 1152 * Description: this function is called to clear the TX descriptors 1153 * in case of both basic and extended descriptors are used. 1154 */ 1155 static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue) 1156 { 1157 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1158 int i; 1159 1160 /* Clear the TX descriptors */ 1161 for (i = 0; i < DMA_TX_SIZE; i++) 1162 if (priv->extend_desc) 1163 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 1164 priv->mode, (i == DMA_TX_SIZE - 1)); 1165 else 1166 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 1167 priv->mode, (i == DMA_TX_SIZE - 1)); 1168 } 1169 1170 /** 1171 * stmmac_clear_descriptors - clear descriptors 1172 * @priv: driver private structure 1173 * Description: this function is called to clear the TX and RX descriptors 1174 * in case of both basic and extended descriptors are used. 1175 */ 1176 static void stmmac_clear_descriptors(struct stmmac_priv *priv) 1177 { 1178 u32 rx_queue_cnt = priv->plat->rx_queues_to_use; 1179 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1180 u32 queue; 1181 1182 /* Clear the RX descriptors */ 1183 for (queue = 0; queue < rx_queue_cnt; queue++) 1184 stmmac_clear_rx_descriptors(priv, queue); 1185 1186 /* Clear the TX descriptors */ 1187 for (queue = 0; queue < tx_queue_cnt; queue++) 1188 stmmac_clear_tx_descriptors(priv, queue); 1189 } 1190 1191 /** 1192 * stmmac_init_rx_buffers - init the RX descriptor buffer. 1193 * @priv: driver private structure 1194 * @p: descriptor pointer 1195 * @i: descriptor index 1196 * @flags: gfp flag 1197 * @queue: RX queue index 1198 * Description: this function is called to allocate a receive buffer, perform 1199 * the DMA mapping and init the descriptor. 1200 */ 1201 static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p, 1202 int i, gfp_t flags, u32 queue) 1203 { 1204 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1205 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1206 1207 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 1208 if (!buf->page) 1209 return -ENOMEM; 1210 1211 if (priv->sph) { 1212 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 1213 if (!buf->sec_page) 1214 return -ENOMEM; 1215 1216 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 1217 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 1218 } else { 1219 buf->sec_page = NULL; 1220 } 1221 1222 buf->addr = page_pool_get_dma_addr(buf->page); 1223 stmmac_set_desc_addr(priv, p, buf->addr); 1224 if (priv->dma_buf_sz == BUF_SIZE_16KiB) 1225 stmmac_init_desc3(priv, p); 1226 1227 return 0; 1228 } 1229 1230 /** 1231 * stmmac_free_rx_buffer - free RX dma buffers 1232 * @priv: private structure 1233 * @queue: RX queue index 1234 * @i: buffer index. 1235 */ 1236 static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1237 { 1238 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1239 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; 1240 1241 if (buf->page) 1242 page_pool_put_page(rx_q->page_pool, buf->page, false); 1243 buf->page = NULL; 1244 1245 if (buf->sec_page) 1246 page_pool_put_page(rx_q->page_pool, buf->sec_page, false); 1247 buf->sec_page = NULL; 1248 } 1249 1250 /** 1251 * stmmac_free_tx_buffer - free RX dma buffers 1252 * @priv: private structure 1253 * @queue: RX queue index 1254 * @i: buffer index. 1255 */ 1256 static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i) 1257 { 1258 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1259 1260 if (tx_q->tx_skbuff_dma[i].buf) { 1261 if (tx_q->tx_skbuff_dma[i].map_as_page) 1262 dma_unmap_page(priv->device, 1263 tx_q->tx_skbuff_dma[i].buf, 1264 tx_q->tx_skbuff_dma[i].len, 1265 DMA_TO_DEVICE); 1266 else 1267 dma_unmap_single(priv->device, 1268 tx_q->tx_skbuff_dma[i].buf, 1269 tx_q->tx_skbuff_dma[i].len, 1270 DMA_TO_DEVICE); 1271 } 1272 1273 if (tx_q->tx_skbuff[i]) { 1274 dev_kfree_skb_any(tx_q->tx_skbuff[i]); 1275 tx_q->tx_skbuff[i] = NULL; 1276 tx_q->tx_skbuff_dma[i].buf = 0; 1277 tx_q->tx_skbuff_dma[i].map_as_page = false; 1278 } 1279 } 1280 1281 /** 1282 * init_dma_rx_desc_rings - init the RX descriptor rings 1283 * @dev: net device structure 1284 * @flags: gfp flag. 1285 * Description: this function initializes the DMA RX descriptors 1286 * and allocates the socket buffers. It supports the chained and ring 1287 * modes. 1288 */ 1289 static int init_dma_rx_desc_rings(struct net_device *dev, gfp_t flags) 1290 { 1291 struct stmmac_priv *priv = netdev_priv(dev); 1292 u32 rx_count = priv->plat->rx_queues_to_use; 1293 int ret = -ENOMEM; 1294 int bfsize = 0; 1295 int queue; 1296 int i; 1297 1298 bfsize = stmmac_set_16kib_bfsize(priv, dev->mtu); 1299 if (bfsize < 0) 1300 bfsize = 0; 1301 1302 if (bfsize < BUF_SIZE_16KiB) 1303 bfsize = stmmac_set_bfsize(dev->mtu, priv->dma_buf_sz); 1304 1305 priv->dma_buf_sz = bfsize; 1306 1307 /* RX INITIALIZATION */ 1308 netif_dbg(priv, probe, priv->dev, 1309 "SKB addresses:\nskb\t\tskb data\tdma data\n"); 1310 1311 for (queue = 0; queue < rx_count; queue++) { 1312 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1313 1314 netif_dbg(priv, probe, priv->dev, 1315 "(%s) dma_rx_phy=0x%08x\n", __func__, 1316 (u32)rx_q->dma_rx_phy); 1317 1318 stmmac_clear_rx_descriptors(priv, queue); 1319 1320 for (i = 0; i < DMA_RX_SIZE; i++) { 1321 struct dma_desc *p; 1322 1323 if (priv->extend_desc) 1324 p = &((rx_q->dma_erx + i)->basic); 1325 else 1326 p = rx_q->dma_rx + i; 1327 1328 ret = stmmac_init_rx_buffers(priv, p, i, flags, 1329 queue); 1330 if (ret) 1331 goto err_init_rx_buffers; 1332 } 1333 1334 rx_q->cur_rx = 0; 1335 rx_q->dirty_rx = (unsigned int)(i - DMA_RX_SIZE); 1336 1337 /* Setup the chained descriptor addresses */ 1338 if (priv->mode == STMMAC_CHAIN_MODE) { 1339 if (priv->extend_desc) 1340 stmmac_mode_init(priv, rx_q->dma_erx, 1341 rx_q->dma_rx_phy, DMA_RX_SIZE, 1); 1342 else 1343 stmmac_mode_init(priv, rx_q->dma_rx, 1344 rx_q->dma_rx_phy, DMA_RX_SIZE, 0); 1345 } 1346 } 1347 1348 buf_sz = bfsize; 1349 1350 return 0; 1351 1352 err_init_rx_buffers: 1353 while (queue >= 0) { 1354 while (--i >= 0) 1355 stmmac_free_rx_buffer(priv, queue, i); 1356 1357 if (queue == 0) 1358 break; 1359 1360 i = DMA_RX_SIZE; 1361 queue--; 1362 } 1363 1364 return ret; 1365 } 1366 1367 /** 1368 * init_dma_tx_desc_rings - init the TX descriptor rings 1369 * @dev: net device structure. 1370 * Description: this function initializes the DMA TX descriptors 1371 * and allocates the socket buffers. It supports the chained and ring 1372 * modes. 1373 */ 1374 static int init_dma_tx_desc_rings(struct net_device *dev) 1375 { 1376 struct stmmac_priv *priv = netdev_priv(dev); 1377 u32 tx_queue_cnt = priv->plat->tx_queues_to_use; 1378 u32 queue; 1379 int i; 1380 1381 for (queue = 0; queue < tx_queue_cnt; queue++) { 1382 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1383 1384 netif_dbg(priv, probe, priv->dev, 1385 "(%s) dma_tx_phy=0x%08x\n", __func__, 1386 (u32)tx_q->dma_tx_phy); 1387 1388 /* Setup the chained descriptor addresses */ 1389 if (priv->mode == STMMAC_CHAIN_MODE) { 1390 if (priv->extend_desc) 1391 stmmac_mode_init(priv, tx_q->dma_etx, 1392 tx_q->dma_tx_phy, DMA_TX_SIZE, 1); 1393 else 1394 stmmac_mode_init(priv, tx_q->dma_tx, 1395 tx_q->dma_tx_phy, DMA_TX_SIZE, 0); 1396 } 1397 1398 for (i = 0; i < DMA_TX_SIZE; i++) { 1399 struct dma_desc *p; 1400 if (priv->extend_desc) 1401 p = &((tx_q->dma_etx + i)->basic); 1402 else 1403 p = tx_q->dma_tx + i; 1404 1405 stmmac_clear_desc(priv, p); 1406 1407 tx_q->tx_skbuff_dma[i].buf = 0; 1408 tx_q->tx_skbuff_dma[i].map_as_page = false; 1409 tx_q->tx_skbuff_dma[i].len = 0; 1410 tx_q->tx_skbuff_dma[i].last_segment = false; 1411 tx_q->tx_skbuff[i] = NULL; 1412 } 1413 1414 tx_q->dirty_tx = 0; 1415 tx_q->cur_tx = 0; 1416 tx_q->mss = 0; 1417 1418 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, queue)); 1419 } 1420 1421 return 0; 1422 } 1423 1424 /** 1425 * init_dma_desc_rings - init the RX/TX descriptor rings 1426 * @dev: net device structure 1427 * @flags: gfp flag. 1428 * Description: this function initializes the DMA RX/TX descriptors 1429 * and allocates the socket buffers. It supports the chained and ring 1430 * modes. 1431 */ 1432 static int init_dma_desc_rings(struct net_device *dev, gfp_t flags) 1433 { 1434 struct stmmac_priv *priv = netdev_priv(dev); 1435 int ret; 1436 1437 ret = init_dma_rx_desc_rings(dev, flags); 1438 if (ret) 1439 return ret; 1440 1441 ret = init_dma_tx_desc_rings(dev); 1442 1443 stmmac_clear_descriptors(priv); 1444 1445 if (netif_msg_hw(priv)) 1446 stmmac_display_rings(priv); 1447 1448 return ret; 1449 } 1450 1451 /** 1452 * dma_free_rx_skbufs - free RX dma buffers 1453 * @priv: private structure 1454 * @queue: RX queue index 1455 */ 1456 static void dma_free_rx_skbufs(struct stmmac_priv *priv, u32 queue) 1457 { 1458 int i; 1459 1460 for (i = 0; i < DMA_RX_SIZE; i++) 1461 stmmac_free_rx_buffer(priv, queue, i); 1462 } 1463 1464 /** 1465 * dma_free_tx_skbufs - free TX dma buffers 1466 * @priv: private structure 1467 * @queue: TX queue index 1468 */ 1469 static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue) 1470 { 1471 int i; 1472 1473 for (i = 0; i < DMA_TX_SIZE; i++) 1474 stmmac_free_tx_buffer(priv, queue, i); 1475 } 1476 1477 /** 1478 * free_dma_rx_desc_resources - free RX dma desc resources 1479 * @priv: private structure 1480 */ 1481 static void free_dma_rx_desc_resources(struct stmmac_priv *priv) 1482 { 1483 u32 rx_count = priv->plat->rx_queues_to_use; 1484 u32 queue; 1485 1486 /* Free RX queue resources */ 1487 for (queue = 0; queue < rx_count; queue++) { 1488 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1489 1490 /* Release the DMA RX socket buffers */ 1491 dma_free_rx_skbufs(priv, queue); 1492 1493 /* Free DMA regions of consistent memory previously allocated */ 1494 if (!priv->extend_desc) 1495 dma_free_coherent(priv->device, 1496 DMA_RX_SIZE * sizeof(struct dma_desc), 1497 rx_q->dma_rx, rx_q->dma_rx_phy); 1498 else 1499 dma_free_coherent(priv->device, DMA_RX_SIZE * 1500 sizeof(struct dma_extended_desc), 1501 rx_q->dma_erx, rx_q->dma_rx_phy); 1502 1503 kfree(rx_q->buf_pool); 1504 if (rx_q->page_pool) { 1505 page_pool_request_shutdown(rx_q->page_pool); 1506 page_pool_destroy(rx_q->page_pool); 1507 } 1508 } 1509 } 1510 1511 /** 1512 * free_dma_tx_desc_resources - free TX dma desc resources 1513 * @priv: private structure 1514 */ 1515 static void free_dma_tx_desc_resources(struct stmmac_priv *priv) 1516 { 1517 u32 tx_count = priv->plat->tx_queues_to_use; 1518 u32 queue; 1519 1520 /* Free TX queue resources */ 1521 for (queue = 0; queue < tx_count; queue++) { 1522 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1523 1524 /* Release the DMA TX socket buffers */ 1525 dma_free_tx_skbufs(priv, queue); 1526 1527 /* Free DMA regions of consistent memory previously allocated */ 1528 if (!priv->extend_desc) 1529 dma_free_coherent(priv->device, 1530 DMA_TX_SIZE * sizeof(struct dma_desc), 1531 tx_q->dma_tx, tx_q->dma_tx_phy); 1532 else 1533 dma_free_coherent(priv->device, DMA_TX_SIZE * 1534 sizeof(struct dma_extended_desc), 1535 tx_q->dma_etx, tx_q->dma_tx_phy); 1536 1537 kfree(tx_q->tx_skbuff_dma); 1538 kfree(tx_q->tx_skbuff); 1539 } 1540 } 1541 1542 /** 1543 * alloc_dma_rx_desc_resources - alloc RX resources. 1544 * @priv: private structure 1545 * Description: according to which descriptor can be used (extend or basic) 1546 * this function allocates the resources for TX and RX paths. In case of 1547 * reception, for example, it pre-allocated the RX socket buffer in order to 1548 * allow zero-copy mechanism. 1549 */ 1550 static int alloc_dma_rx_desc_resources(struct stmmac_priv *priv) 1551 { 1552 u32 rx_count = priv->plat->rx_queues_to_use; 1553 int ret = -ENOMEM; 1554 u32 queue; 1555 1556 /* RX queues buffers and DMA */ 1557 for (queue = 0; queue < rx_count; queue++) { 1558 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 1559 struct page_pool_params pp_params = { 0 }; 1560 unsigned int num_pages; 1561 1562 rx_q->queue_index = queue; 1563 rx_q->priv_data = priv; 1564 1565 pp_params.flags = PP_FLAG_DMA_MAP; 1566 pp_params.pool_size = DMA_RX_SIZE; 1567 num_pages = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE); 1568 pp_params.order = ilog2(num_pages); 1569 pp_params.nid = dev_to_node(priv->device); 1570 pp_params.dev = priv->device; 1571 pp_params.dma_dir = DMA_FROM_DEVICE; 1572 1573 rx_q->page_pool = page_pool_create(&pp_params); 1574 if (IS_ERR(rx_q->page_pool)) { 1575 ret = PTR_ERR(rx_q->page_pool); 1576 rx_q->page_pool = NULL; 1577 goto err_dma; 1578 } 1579 1580 rx_q->buf_pool = kcalloc(DMA_RX_SIZE, sizeof(*rx_q->buf_pool), 1581 GFP_KERNEL); 1582 if (!rx_q->buf_pool) 1583 goto err_dma; 1584 1585 if (priv->extend_desc) { 1586 rx_q->dma_erx = dma_alloc_coherent(priv->device, 1587 DMA_RX_SIZE * sizeof(struct dma_extended_desc), 1588 &rx_q->dma_rx_phy, 1589 GFP_KERNEL); 1590 if (!rx_q->dma_erx) 1591 goto err_dma; 1592 1593 } else { 1594 rx_q->dma_rx = dma_alloc_coherent(priv->device, 1595 DMA_RX_SIZE * sizeof(struct dma_desc), 1596 &rx_q->dma_rx_phy, 1597 GFP_KERNEL); 1598 if (!rx_q->dma_rx) 1599 goto err_dma; 1600 } 1601 } 1602 1603 return 0; 1604 1605 err_dma: 1606 free_dma_rx_desc_resources(priv); 1607 1608 return ret; 1609 } 1610 1611 /** 1612 * alloc_dma_tx_desc_resources - alloc TX resources. 1613 * @priv: private structure 1614 * Description: according to which descriptor can be used (extend or basic) 1615 * this function allocates the resources for TX and RX paths. In case of 1616 * reception, for example, it pre-allocated the RX socket buffer in order to 1617 * allow zero-copy mechanism. 1618 */ 1619 static int alloc_dma_tx_desc_resources(struct stmmac_priv *priv) 1620 { 1621 u32 tx_count = priv->plat->tx_queues_to_use; 1622 int ret = -ENOMEM; 1623 u32 queue; 1624 1625 /* TX queues buffers and DMA */ 1626 for (queue = 0; queue < tx_count; queue++) { 1627 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1628 1629 tx_q->queue_index = queue; 1630 tx_q->priv_data = priv; 1631 1632 tx_q->tx_skbuff_dma = kcalloc(DMA_TX_SIZE, 1633 sizeof(*tx_q->tx_skbuff_dma), 1634 GFP_KERNEL); 1635 if (!tx_q->tx_skbuff_dma) 1636 goto err_dma; 1637 1638 tx_q->tx_skbuff = kcalloc(DMA_TX_SIZE, 1639 sizeof(struct sk_buff *), 1640 GFP_KERNEL); 1641 if (!tx_q->tx_skbuff) 1642 goto err_dma; 1643 1644 if (priv->extend_desc) { 1645 tx_q->dma_etx = dma_alloc_coherent(priv->device, 1646 DMA_TX_SIZE * sizeof(struct dma_extended_desc), 1647 &tx_q->dma_tx_phy, 1648 GFP_KERNEL); 1649 if (!tx_q->dma_etx) 1650 goto err_dma; 1651 } else { 1652 tx_q->dma_tx = dma_alloc_coherent(priv->device, 1653 DMA_TX_SIZE * sizeof(struct dma_desc), 1654 &tx_q->dma_tx_phy, 1655 GFP_KERNEL); 1656 if (!tx_q->dma_tx) 1657 goto err_dma; 1658 } 1659 } 1660 1661 return 0; 1662 1663 err_dma: 1664 free_dma_tx_desc_resources(priv); 1665 1666 return ret; 1667 } 1668 1669 /** 1670 * alloc_dma_desc_resources - alloc TX/RX resources. 1671 * @priv: private structure 1672 * Description: according to which descriptor can be used (extend or basic) 1673 * this function allocates the resources for TX and RX paths. In case of 1674 * reception, for example, it pre-allocated the RX socket buffer in order to 1675 * allow zero-copy mechanism. 1676 */ 1677 static int alloc_dma_desc_resources(struct stmmac_priv *priv) 1678 { 1679 /* RX Allocation */ 1680 int ret = alloc_dma_rx_desc_resources(priv); 1681 1682 if (ret) 1683 return ret; 1684 1685 ret = alloc_dma_tx_desc_resources(priv); 1686 1687 return ret; 1688 } 1689 1690 /** 1691 * free_dma_desc_resources - free dma desc resources 1692 * @priv: private structure 1693 */ 1694 static void free_dma_desc_resources(struct stmmac_priv *priv) 1695 { 1696 /* Release the DMA RX socket buffers */ 1697 free_dma_rx_desc_resources(priv); 1698 1699 /* Release the DMA TX socket buffers */ 1700 free_dma_tx_desc_resources(priv); 1701 } 1702 1703 /** 1704 * stmmac_mac_enable_rx_queues - Enable MAC rx queues 1705 * @priv: driver private structure 1706 * Description: It is used for enabling the rx queues in the MAC 1707 */ 1708 static void stmmac_mac_enable_rx_queues(struct stmmac_priv *priv) 1709 { 1710 u32 rx_queues_count = priv->plat->rx_queues_to_use; 1711 int queue; 1712 u8 mode; 1713 1714 for (queue = 0; queue < rx_queues_count; queue++) { 1715 mode = priv->plat->rx_queues_cfg[queue].mode_to_use; 1716 stmmac_rx_queue_enable(priv, priv->hw, mode, queue); 1717 } 1718 } 1719 1720 /** 1721 * stmmac_start_rx_dma - start RX DMA channel 1722 * @priv: driver private structure 1723 * @chan: RX channel index 1724 * Description: 1725 * This starts a RX DMA channel 1726 */ 1727 static void stmmac_start_rx_dma(struct stmmac_priv *priv, u32 chan) 1728 { 1729 netdev_dbg(priv->dev, "DMA RX processes started in channel %d\n", chan); 1730 stmmac_start_rx(priv, priv->ioaddr, chan); 1731 } 1732 1733 /** 1734 * stmmac_start_tx_dma - start TX DMA channel 1735 * @priv: driver private structure 1736 * @chan: TX channel index 1737 * Description: 1738 * This starts a TX DMA channel 1739 */ 1740 static void stmmac_start_tx_dma(struct stmmac_priv *priv, u32 chan) 1741 { 1742 netdev_dbg(priv->dev, "DMA TX processes started in channel %d\n", chan); 1743 stmmac_start_tx(priv, priv->ioaddr, chan); 1744 } 1745 1746 /** 1747 * stmmac_stop_rx_dma - stop RX DMA channel 1748 * @priv: driver private structure 1749 * @chan: RX channel index 1750 * Description: 1751 * This stops a RX DMA channel 1752 */ 1753 static void stmmac_stop_rx_dma(struct stmmac_priv *priv, u32 chan) 1754 { 1755 netdev_dbg(priv->dev, "DMA RX processes stopped in channel %d\n", chan); 1756 stmmac_stop_rx(priv, priv->ioaddr, chan); 1757 } 1758 1759 /** 1760 * stmmac_stop_tx_dma - stop TX DMA channel 1761 * @priv: driver private structure 1762 * @chan: TX channel index 1763 * Description: 1764 * This stops a TX DMA channel 1765 */ 1766 static void stmmac_stop_tx_dma(struct stmmac_priv *priv, u32 chan) 1767 { 1768 netdev_dbg(priv->dev, "DMA TX processes stopped in channel %d\n", chan); 1769 stmmac_stop_tx(priv, priv->ioaddr, chan); 1770 } 1771 1772 /** 1773 * stmmac_start_all_dma - start all RX and TX DMA channels 1774 * @priv: driver private structure 1775 * Description: 1776 * This starts all the RX and TX DMA channels 1777 */ 1778 static void stmmac_start_all_dma(struct stmmac_priv *priv) 1779 { 1780 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1781 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1782 u32 chan = 0; 1783 1784 for (chan = 0; chan < rx_channels_count; chan++) 1785 stmmac_start_rx_dma(priv, chan); 1786 1787 for (chan = 0; chan < tx_channels_count; chan++) 1788 stmmac_start_tx_dma(priv, chan); 1789 } 1790 1791 /** 1792 * stmmac_stop_all_dma - stop all RX and TX DMA channels 1793 * @priv: driver private structure 1794 * Description: 1795 * This stops the RX and TX DMA channels 1796 */ 1797 static void stmmac_stop_all_dma(struct stmmac_priv *priv) 1798 { 1799 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1800 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1801 u32 chan = 0; 1802 1803 for (chan = 0; chan < rx_channels_count; chan++) 1804 stmmac_stop_rx_dma(priv, chan); 1805 1806 for (chan = 0; chan < tx_channels_count; chan++) 1807 stmmac_stop_tx_dma(priv, chan); 1808 } 1809 1810 /** 1811 * stmmac_dma_operation_mode - HW DMA operation mode 1812 * @priv: driver private structure 1813 * Description: it is used for configuring the DMA operation mode register in 1814 * order to program the tx/rx DMA thresholds or Store-And-Forward mode. 1815 */ 1816 static void stmmac_dma_operation_mode(struct stmmac_priv *priv) 1817 { 1818 u32 rx_channels_count = priv->plat->rx_queues_to_use; 1819 u32 tx_channels_count = priv->plat->tx_queues_to_use; 1820 int rxfifosz = priv->plat->rx_fifo_size; 1821 int txfifosz = priv->plat->tx_fifo_size; 1822 u32 txmode = 0; 1823 u32 rxmode = 0; 1824 u32 chan = 0; 1825 u8 qmode = 0; 1826 1827 if (rxfifosz == 0) 1828 rxfifosz = priv->dma_cap.rx_fifo_size; 1829 if (txfifosz == 0) 1830 txfifosz = priv->dma_cap.tx_fifo_size; 1831 1832 /* Adjust for real per queue fifo size */ 1833 rxfifosz /= rx_channels_count; 1834 txfifosz /= tx_channels_count; 1835 1836 if (priv->plat->force_thresh_dma_mode) { 1837 txmode = tc; 1838 rxmode = tc; 1839 } else if (priv->plat->force_sf_dma_mode || priv->plat->tx_coe) { 1840 /* 1841 * In case of GMAC, SF mode can be enabled 1842 * to perform the TX COE in HW. This depends on: 1843 * 1) TX COE if actually supported 1844 * 2) There is no bugged Jumbo frame support 1845 * that needs to not insert csum in the TDES. 1846 */ 1847 txmode = SF_DMA_MODE; 1848 rxmode = SF_DMA_MODE; 1849 priv->xstats.threshold = SF_DMA_MODE; 1850 } else { 1851 txmode = tc; 1852 rxmode = SF_DMA_MODE; 1853 } 1854 1855 /* configure all channels */ 1856 for (chan = 0; chan < rx_channels_count; chan++) { 1857 qmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 1858 1859 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, 1860 rxfifosz, qmode); 1861 stmmac_set_dma_bfsize(priv, priv->ioaddr, priv->dma_buf_sz, 1862 chan); 1863 } 1864 1865 for (chan = 0; chan < tx_channels_count; chan++) { 1866 qmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 1867 1868 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, 1869 txfifosz, qmode); 1870 } 1871 } 1872 1873 /** 1874 * stmmac_tx_clean - to manage the transmission completion 1875 * @priv: driver private structure 1876 * @queue: TX queue index 1877 * Description: it reclaims the transmit resources after transmission completes. 1878 */ 1879 static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue) 1880 { 1881 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 1882 unsigned int bytes_compl = 0, pkts_compl = 0; 1883 unsigned int entry, count = 0; 1884 1885 __netif_tx_lock_bh(netdev_get_tx_queue(priv->dev, queue)); 1886 1887 priv->xstats.tx_clean++; 1888 1889 entry = tx_q->dirty_tx; 1890 while ((entry != tx_q->cur_tx) && (count < budget)) { 1891 struct sk_buff *skb = tx_q->tx_skbuff[entry]; 1892 struct dma_desc *p; 1893 int status; 1894 1895 if (priv->extend_desc) 1896 p = (struct dma_desc *)(tx_q->dma_etx + entry); 1897 else 1898 p = tx_q->dma_tx + entry; 1899 1900 status = stmmac_tx_status(priv, &priv->dev->stats, 1901 &priv->xstats, p, priv->ioaddr); 1902 /* Check if the descriptor is owned by the DMA */ 1903 if (unlikely(status & tx_dma_own)) 1904 break; 1905 1906 count++; 1907 1908 /* Make sure descriptor fields are read after reading 1909 * the own bit. 1910 */ 1911 dma_rmb(); 1912 1913 /* Just consider the last segment and ...*/ 1914 if (likely(!(status & tx_not_ls))) { 1915 /* ... verify the status error condition */ 1916 if (unlikely(status & tx_err)) { 1917 priv->dev->stats.tx_errors++; 1918 } else { 1919 priv->dev->stats.tx_packets++; 1920 priv->xstats.tx_pkt_n++; 1921 } 1922 stmmac_get_tx_hwtstamp(priv, p, skb); 1923 } 1924 1925 if (likely(tx_q->tx_skbuff_dma[entry].buf)) { 1926 if (tx_q->tx_skbuff_dma[entry].map_as_page) 1927 dma_unmap_page(priv->device, 1928 tx_q->tx_skbuff_dma[entry].buf, 1929 tx_q->tx_skbuff_dma[entry].len, 1930 DMA_TO_DEVICE); 1931 else 1932 dma_unmap_single(priv->device, 1933 tx_q->tx_skbuff_dma[entry].buf, 1934 tx_q->tx_skbuff_dma[entry].len, 1935 DMA_TO_DEVICE); 1936 tx_q->tx_skbuff_dma[entry].buf = 0; 1937 tx_q->tx_skbuff_dma[entry].len = 0; 1938 tx_q->tx_skbuff_dma[entry].map_as_page = false; 1939 } 1940 1941 stmmac_clean_desc3(priv, tx_q, p); 1942 1943 tx_q->tx_skbuff_dma[entry].last_segment = false; 1944 tx_q->tx_skbuff_dma[entry].is_jumbo = false; 1945 1946 if (likely(skb != NULL)) { 1947 pkts_compl++; 1948 bytes_compl += skb->len; 1949 dev_consume_skb_any(skb); 1950 tx_q->tx_skbuff[entry] = NULL; 1951 } 1952 1953 stmmac_release_tx_desc(priv, p, priv->mode); 1954 1955 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 1956 } 1957 tx_q->dirty_tx = entry; 1958 1959 netdev_tx_completed_queue(netdev_get_tx_queue(priv->dev, queue), 1960 pkts_compl, bytes_compl); 1961 1962 if (unlikely(netif_tx_queue_stopped(netdev_get_tx_queue(priv->dev, 1963 queue))) && 1964 stmmac_tx_avail(priv, queue) > STMMAC_TX_THRESH) { 1965 1966 netif_dbg(priv, tx_done, priv->dev, 1967 "%s: restart transmit\n", __func__); 1968 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, queue)); 1969 } 1970 1971 if ((priv->eee_enabled) && (!priv->tx_path_in_lpi_mode)) { 1972 stmmac_enable_eee_mode(priv); 1973 mod_timer(&priv->eee_ctrl_timer, STMMAC_LPI_T(eee_timer)); 1974 } 1975 1976 /* We still have pending packets, let's call for a new scheduling */ 1977 if (tx_q->dirty_tx != tx_q->cur_tx) 1978 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 1979 1980 __netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue)); 1981 1982 return count; 1983 } 1984 1985 /** 1986 * stmmac_tx_err - to manage the tx error 1987 * @priv: driver private structure 1988 * @chan: channel index 1989 * Description: it cleans the descriptors and restarts the transmission 1990 * in case of transmission errors. 1991 */ 1992 static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan) 1993 { 1994 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 1995 int i; 1996 1997 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan)); 1998 1999 stmmac_stop_tx_dma(priv, chan); 2000 dma_free_tx_skbufs(priv, chan); 2001 for (i = 0; i < DMA_TX_SIZE; i++) 2002 if (priv->extend_desc) 2003 stmmac_init_tx_desc(priv, &tx_q->dma_etx[i].basic, 2004 priv->mode, (i == DMA_TX_SIZE - 1)); 2005 else 2006 stmmac_init_tx_desc(priv, &tx_q->dma_tx[i], 2007 priv->mode, (i == DMA_TX_SIZE - 1)); 2008 tx_q->dirty_tx = 0; 2009 tx_q->cur_tx = 0; 2010 tx_q->mss = 0; 2011 netdev_tx_reset_queue(netdev_get_tx_queue(priv->dev, chan)); 2012 stmmac_start_tx_dma(priv, chan); 2013 2014 priv->dev->stats.tx_errors++; 2015 netif_tx_wake_queue(netdev_get_tx_queue(priv->dev, chan)); 2016 } 2017 2018 /** 2019 * stmmac_set_dma_operation_mode - Set DMA operation mode by channel 2020 * @priv: driver private structure 2021 * @txmode: TX operating mode 2022 * @rxmode: RX operating mode 2023 * @chan: channel index 2024 * Description: it is used for configuring of the DMA operation mode in 2025 * runtime in order to program the tx/rx DMA thresholds or Store-And-Forward 2026 * mode. 2027 */ 2028 static void stmmac_set_dma_operation_mode(struct stmmac_priv *priv, u32 txmode, 2029 u32 rxmode, u32 chan) 2030 { 2031 u8 rxqmode = priv->plat->rx_queues_cfg[chan].mode_to_use; 2032 u8 txqmode = priv->plat->tx_queues_cfg[chan].mode_to_use; 2033 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2034 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2035 int rxfifosz = priv->plat->rx_fifo_size; 2036 int txfifosz = priv->plat->tx_fifo_size; 2037 2038 if (rxfifosz == 0) 2039 rxfifosz = priv->dma_cap.rx_fifo_size; 2040 if (txfifosz == 0) 2041 txfifosz = priv->dma_cap.tx_fifo_size; 2042 2043 /* Adjust for real per queue fifo size */ 2044 rxfifosz /= rx_channels_count; 2045 txfifosz /= tx_channels_count; 2046 2047 stmmac_dma_rx_mode(priv, priv->ioaddr, rxmode, chan, rxfifosz, rxqmode); 2048 stmmac_dma_tx_mode(priv, priv->ioaddr, txmode, chan, txfifosz, txqmode); 2049 } 2050 2051 static bool stmmac_safety_feat_interrupt(struct stmmac_priv *priv) 2052 { 2053 int ret; 2054 2055 ret = stmmac_safety_feat_irq_status(priv, priv->dev, 2056 priv->ioaddr, priv->dma_cap.asp, &priv->sstats); 2057 if (ret && (ret != -EINVAL)) { 2058 stmmac_global_err(priv); 2059 return true; 2060 } 2061 2062 return false; 2063 } 2064 2065 static int stmmac_napi_check(struct stmmac_priv *priv, u32 chan) 2066 { 2067 int status = stmmac_dma_interrupt_status(priv, priv->ioaddr, 2068 &priv->xstats, chan); 2069 struct stmmac_channel *ch = &priv->channel[chan]; 2070 2071 if ((status & handle_rx) && (chan < priv->plat->rx_queues_to_use)) { 2072 if (napi_schedule_prep(&ch->rx_napi)) { 2073 stmmac_disable_dma_irq(priv, priv->ioaddr, chan); 2074 __napi_schedule_irqoff(&ch->rx_napi); 2075 status |= handle_tx; 2076 } 2077 } 2078 2079 if ((status & handle_tx) && (chan < priv->plat->tx_queues_to_use)) 2080 napi_schedule_irqoff(&ch->tx_napi); 2081 2082 return status; 2083 } 2084 2085 /** 2086 * stmmac_dma_interrupt - DMA ISR 2087 * @priv: driver private structure 2088 * Description: this is the DMA ISR. It is called by the main ISR. 2089 * It calls the dwmac dma routine and schedule poll method in case of some 2090 * work can be done. 2091 */ 2092 static void stmmac_dma_interrupt(struct stmmac_priv *priv) 2093 { 2094 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2095 u32 rx_channel_count = priv->plat->rx_queues_to_use; 2096 u32 channels_to_check = tx_channel_count > rx_channel_count ? 2097 tx_channel_count : rx_channel_count; 2098 u32 chan; 2099 int status[max_t(u32, MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES)]; 2100 2101 /* Make sure we never check beyond our status buffer. */ 2102 if (WARN_ON_ONCE(channels_to_check > ARRAY_SIZE(status))) 2103 channels_to_check = ARRAY_SIZE(status); 2104 2105 for (chan = 0; chan < channels_to_check; chan++) 2106 status[chan] = stmmac_napi_check(priv, chan); 2107 2108 for (chan = 0; chan < tx_channel_count; chan++) { 2109 if (unlikely(status[chan] & tx_hard_error_bump_tc)) { 2110 /* Try to bump up the dma threshold on this failure */ 2111 if (unlikely(priv->xstats.threshold != SF_DMA_MODE) && 2112 (tc <= 256)) { 2113 tc += 64; 2114 if (priv->plat->force_thresh_dma_mode) 2115 stmmac_set_dma_operation_mode(priv, 2116 tc, 2117 tc, 2118 chan); 2119 else 2120 stmmac_set_dma_operation_mode(priv, 2121 tc, 2122 SF_DMA_MODE, 2123 chan); 2124 priv->xstats.threshold = tc; 2125 } 2126 } else if (unlikely(status[chan] == tx_hard_error)) { 2127 stmmac_tx_err(priv, chan); 2128 } 2129 } 2130 } 2131 2132 /** 2133 * stmmac_mmc_setup: setup the Mac Management Counters (MMC) 2134 * @priv: driver private structure 2135 * Description: this masks the MMC irq, in fact, the counters are managed in SW. 2136 */ 2137 static void stmmac_mmc_setup(struct stmmac_priv *priv) 2138 { 2139 unsigned int mode = MMC_CNTRL_RESET_ON_READ | MMC_CNTRL_COUNTER_RESET | 2140 MMC_CNTRL_PRESET | MMC_CNTRL_FULL_HALF_PRESET; 2141 2142 stmmac_mmc_intr_all_mask(priv, priv->mmcaddr); 2143 2144 if (priv->dma_cap.rmon) { 2145 stmmac_mmc_ctrl(priv, priv->mmcaddr, mode); 2146 memset(&priv->mmc, 0, sizeof(struct stmmac_counters)); 2147 } else 2148 netdev_info(priv->dev, "No MAC Management Counters available\n"); 2149 } 2150 2151 /** 2152 * stmmac_get_hw_features - get MAC capabilities from the HW cap. register. 2153 * @priv: driver private structure 2154 * Description: 2155 * new GMAC chip generations have a new register to indicate the 2156 * presence of the optional feature/functions. 2157 * This can be also used to override the value passed through the 2158 * platform and necessary for old MAC10/100 and GMAC chips. 2159 */ 2160 static int stmmac_get_hw_features(struct stmmac_priv *priv) 2161 { 2162 return stmmac_get_hw_feature(priv, priv->ioaddr, &priv->dma_cap) == 0; 2163 } 2164 2165 /** 2166 * stmmac_check_ether_addr - check if the MAC addr is valid 2167 * @priv: driver private structure 2168 * Description: 2169 * it is to verify if the MAC address is valid, in case of failures it 2170 * generates a random MAC address 2171 */ 2172 static void stmmac_check_ether_addr(struct stmmac_priv *priv) 2173 { 2174 if (!is_valid_ether_addr(priv->dev->dev_addr)) { 2175 stmmac_get_umac_addr(priv, priv->hw, priv->dev->dev_addr, 0); 2176 if (!is_valid_ether_addr(priv->dev->dev_addr)) 2177 eth_hw_addr_random(priv->dev); 2178 dev_info(priv->device, "device MAC address %pM\n", 2179 priv->dev->dev_addr); 2180 } 2181 } 2182 2183 /** 2184 * stmmac_init_dma_engine - DMA init. 2185 * @priv: driver private structure 2186 * Description: 2187 * It inits the DMA invoking the specific MAC/GMAC callback. 2188 * Some DMA parameters can be passed from the platform; 2189 * in case of these are not passed a default is kept for the MAC or GMAC. 2190 */ 2191 static int stmmac_init_dma_engine(struct stmmac_priv *priv) 2192 { 2193 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2194 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2195 u32 dma_csr_ch = max(rx_channels_count, tx_channels_count); 2196 struct stmmac_rx_queue *rx_q; 2197 struct stmmac_tx_queue *tx_q; 2198 u32 chan = 0; 2199 int atds = 0; 2200 int ret = 0; 2201 2202 if (!priv->plat->dma_cfg || !priv->plat->dma_cfg->pbl) { 2203 dev_err(priv->device, "Invalid DMA configuration\n"); 2204 return -EINVAL; 2205 } 2206 2207 if (priv->extend_desc && (priv->mode == STMMAC_RING_MODE)) 2208 atds = 1; 2209 2210 ret = stmmac_reset(priv, priv->ioaddr); 2211 if (ret) { 2212 dev_err(priv->device, "Failed to reset the dma\n"); 2213 return ret; 2214 } 2215 2216 /* DMA Configuration */ 2217 stmmac_dma_init(priv, priv->ioaddr, priv->plat->dma_cfg, atds); 2218 2219 if (priv->plat->axi) 2220 stmmac_axi(priv, priv->ioaddr, priv->plat->axi); 2221 2222 /* DMA CSR Channel configuration */ 2223 for (chan = 0; chan < dma_csr_ch; chan++) 2224 stmmac_init_chan(priv, priv->ioaddr, priv->plat->dma_cfg, chan); 2225 2226 /* DMA RX Channel Configuration */ 2227 for (chan = 0; chan < rx_channels_count; chan++) { 2228 rx_q = &priv->rx_queue[chan]; 2229 2230 stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2231 rx_q->dma_rx_phy, chan); 2232 2233 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 2234 (DMA_RX_SIZE * sizeof(struct dma_desc)); 2235 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 2236 rx_q->rx_tail_addr, chan); 2237 } 2238 2239 /* DMA TX Channel Configuration */ 2240 for (chan = 0; chan < tx_channels_count; chan++) { 2241 tx_q = &priv->tx_queue[chan]; 2242 2243 stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg, 2244 tx_q->dma_tx_phy, chan); 2245 2246 tx_q->tx_tail_addr = tx_q->dma_tx_phy; 2247 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, 2248 tx_q->tx_tail_addr, chan); 2249 } 2250 2251 return ret; 2252 } 2253 2254 static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue) 2255 { 2256 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2257 2258 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(priv->tx_coal_timer)); 2259 } 2260 2261 /** 2262 * stmmac_tx_timer - mitigation sw timer for tx. 2263 * @data: data pointer 2264 * Description: 2265 * This is the timer handler to directly invoke the stmmac_tx_clean. 2266 */ 2267 static void stmmac_tx_timer(struct timer_list *t) 2268 { 2269 struct stmmac_tx_queue *tx_q = from_timer(tx_q, t, txtimer); 2270 struct stmmac_priv *priv = tx_q->priv_data; 2271 struct stmmac_channel *ch; 2272 2273 ch = &priv->channel[tx_q->queue_index]; 2274 2275 /* 2276 * If NAPI is already running we can miss some events. Let's rearm 2277 * the timer and try again. 2278 */ 2279 if (likely(napi_schedule_prep(&ch->tx_napi))) 2280 __napi_schedule(&ch->tx_napi); 2281 else 2282 mod_timer(&tx_q->txtimer, STMMAC_COAL_TIMER(10)); 2283 } 2284 2285 /** 2286 * stmmac_init_coalesce - init mitigation options. 2287 * @priv: driver private structure 2288 * Description: 2289 * This inits the coalesce parameters: i.e. timer rate, 2290 * timer handler and default threshold used for enabling the 2291 * interrupt on completion bit. 2292 */ 2293 static void stmmac_init_coalesce(struct stmmac_priv *priv) 2294 { 2295 u32 tx_channel_count = priv->plat->tx_queues_to_use; 2296 u32 chan; 2297 2298 priv->tx_coal_frames = STMMAC_TX_FRAMES; 2299 priv->tx_coal_timer = STMMAC_COAL_TX_TIMER; 2300 priv->rx_coal_frames = STMMAC_RX_FRAMES; 2301 2302 for (chan = 0; chan < tx_channel_count; chan++) { 2303 struct stmmac_tx_queue *tx_q = &priv->tx_queue[chan]; 2304 2305 timer_setup(&tx_q->txtimer, stmmac_tx_timer, 0); 2306 } 2307 } 2308 2309 static void stmmac_set_rings_length(struct stmmac_priv *priv) 2310 { 2311 u32 rx_channels_count = priv->plat->rx_queues_to_use; 2312 u32 tx_channels_count = priv->plat->tx_queues_to_use; 2313 u32 chan; 2314 2315 /* set TX ring length */ 2316 for (chan = 0; chan < tx_channels_count; chan++) 2317 stmmac_set_tx_ring_len(priv, priv->ioaddr, 2318 (DMA_TX_SIZE - 1), chan); 2319 2320 /* set RX ring length */ 2321 for (chan = 0; chan < rx_channels_count; chan++) 2322 stmmac_set_rx_ring_len(priv, priv->ioaddr, 2323 (DMA_RX_SIZE - 1), chan); 2324 } 2325 2326 /** 2327 * stmmac_set_tx_queue_weight - Set TX queue weight 2328 * @priv: driver private structure 2329 * Description: It is used for setting TX queues weight 2330 */ 2331 static void stmmac_set_tx_queue_weight(struct stmmac_priv *priv) 2332 { 2333 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2334 u32 weight; 2335 u32 queue; 2336 2337 for (queue = 0; queue < tx_queues_count; queue++) { 2338 weight = priv->plat->tx_queues_cfg[queue].weight; 2339 stmmac_set_mtl_tx_queue_weight(priv, priv->hw, weight, queue); 2340 } 2341 } 2342 2343 /** 2344 * stmmac_configure_cbs - Configure CBS in TX queue 2345 * @priv: driver private structure 2346 * Description: It is used for configuring CBS in AVB TX queues 2347 */ 2348 static void stmmac_configure_cbs(struct stmmac_priv *priv) 2349 { 2350 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2351 u32 mode_to_use; 2352 u32 queue; 2353 2354 /* queue 0 is reserved for legacy traffic */ 2355 for (queue = 1; queue < tx_queues_count; queue++) { 2356 mode_to_use = priv->plat->tx_queues_cfg[queue].mode_to_use; 2357 if (mode_to_use == MTL_QUEUE_DCB) 2358 continue; 2359 2360 stmmac_config_cbs(priv, priv->hw, 2361 priv->plat->tx_queues_cfg[queue].send_slope, 2362 priv->plat->tx_queues_cfg[queue].idle_slope, 2363 priv->plat->tx_queues_cfg[queue].high_credit, 2364 priv->plat->tx_queues_cfg[queue].low_credit, 2365 queue); 2366 } 2367 } 2368 2369 /** 2370 * stmmac_rx_queue_dma_chan_map - Map RX queue to RX dma channel 2371 * @priv: driver private structure 2372 * Description: It is used for mapping RX queues to RX dma channels 2373 */ 2374 static void stmmac_rx_queue_dma_chan_map(struct stmmac_priv *priv) 2375 { 2376 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2377 u32 queue; 2378 u32 chan; 2379 2380 for (queue = 0; queue < rx_queues_count; queue++) { 2381 chan = priv->plat->rx_queues_cfg[queue].chan; 2382 stmmac_map_mtl_to_dma(priv, priv->hw, queue, chan); 2383 } 2384 } 2385 2386 /** 2387 * stmmac_mac_config_rx_queues_prio - Configure RX Queue priority 2388 * @priv: driver private structure 2389 * Description: It is used for configuring the RX Queue Priority 2390 */ 2391 static void stmmac_mac_config_rx_queues_prio(struct stmmac_priv *priv) 2392 { 2393 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2394 u32 queue; 2395 u32 prio; 2396 2397 for (queue = 0; queue < rx_queues_count; queue++) { 2398 if (!priv->plat->rx_queues_cfg[queue].use_prio) 2399 continue; 2400 2401 prio = priv->plat->rx_queues_cfg[queue].prio; 2402 stmmac_rx_queue_prio(priv, priv->hw, prio, queue); 2403 } 2404 } 2405 2406 /** 2407 * stmmac_mac_config_tx_queues_prio - Configure TX Queue priority 2408 * @priv: driver private structure 2409 * Description: It is used for configuring the TX Queue Priority 2410 */ 2411 static void stmmac_mac_config_tx_queues_prio(struct stmmac_priv *priv) 2412 { 2413 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2414 u32 queue; 2415 u32 prio; 2416 2417 for (queue = 0; queue < tx_queues_count; queue++) { 2418 if (!priv->plat->tx_queues_cfg[queue].use_prio) 2419 continue; 2420 2421 prio = priv->plat->tx_queues_cfg[queue].prio; 2422 stmmac_tx_queue_prio(priv, priv->hw, prio, queue); 2423 } 2424 } 2425 2426 /** 2427 * stmmac_mac_config_rx_queues_routing - Configure RX Queue Routing 2428 * @priv: driver private structure 2429 * Description: It is used for configuring the RX queue routing 2430 */ 2431 static void stmmac_mac_config_rx_queues_routing(struct stmmac_priv *priv) 2432 { 2433 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2434 u32 queue; 2435 u8 packet; 2436 2437 for (queue = 0; queue < rx_queues_count; queue++) { 2438 /* no specific packet type routing specified for the queue */ 2439 if (priv->plat->rx_queues_cfg[queue].pkt_route == 0x0) 2440 continue; 2441 2442 packet = priv->plat->rx_queues_cfg[queue].pkt_route; 2443 stmmac_rx_queue_routing(priv, priv->hw, packet, queue); 2444 } 2445 } 2446 2447 static void stmmac_mac_config_rss(struct stmmac_priv *priv) 2448 { 2449 if (!priv->dma_cap.rssen || !priv->plat->rss_en) { 2450 priv->rss.enable = false; 2451 return; 2452 } 2453 2454 if (priv->dev->features & NETIF_F_RXHASH) 2455 priv->rss.enable = true; 2456 else 2457 priv->rss.enable = false; 2458 2459 stmmac_rss_configure(priv, priv->hw, &priv->rss, 2460 priv->plat->rx_queues_to_use); 2461 } 2462 2463 /** 2464 * stmmac_mtl_configuration - Configure MTL 2465 * @priv: driver private structure 2466 * Description: It is used for configurring MTL 2467 */ 2468 static void stmmac_mtl_configuration(struct stmmac_priv *priv) 2469 { 2470 u32 rx_queues_count = priv->plat->rx_queues_to_use; 2471 u32 tx_queues_count = priv->plat->tx_queues_to_use; 2472 2473 if (tx_queues_count > 1) 2474 stmmac_set_tx_queue_weight(priv); 2475 2476 /* Configure MTL RX algorithms */ 2477 if (rx_queues_count > 1) 2478 stmmac_prog_mtl_rx_algorithms(priv, priv->hw, 2479 priv->plat->rx_sched_algorithm); 2480 2481 /* Configure MTL TX algorithms */ 2482 if (tx_queues_count > 1) 2483 stmmac_prog_mtl_tx_algorithms(priv, priv->hw, 2484 priv->plat->tx_sched_algorithm); 2485 2486 /* Configure CBS in AVB TX queues */ 2487 if (tx_queues_count > 1) 2488 stmmac_configure_cbs(priv); 2489 2490 /* Map RX MTL to DMA channels */ 2491 stmmac_rx_queue_dma_chan_map(priv); 2492 2493 /* Enable MAC RX Queues */ 2494 stmmac_mac_enable_rx_queues(priv); 2495 2496 /* Set RX priorities */ 2497 if (rx_queues_count > 1) 2498 stmmac_mac_config_rx_queues_prio(priv); 2499 2500 /* Set TX priorities */ 2501 if (tx_queues_count > 1) 2502 stmmac_mac_config_tx_queues_prio(priv); 2503 2504 /* Set RX routing */ 2505 if (rx_queues_count > 1) 2506 stmmac_mac_config_rx_queues_routing(priv); 2507 2508 /* Receive Side Scaling */ 2509 if (rx_queues_count > 1) 2510 stmmac_mac_config_rss(priv); 2511 } 2512 2513 static void stmmac_safety_feat_configuration(struct stmmac_priv *priv) 2514 { 2515 if (priv->dma_cap.asp) { 2516 netdev_info(priv->dev, "Enabling Safety Features\n"); 2517 stmmac_safety_feat_config(priv, priv->ioaddr, priv->dma_cap.asp); 2518 } else { 2519 netdev_info(priv->dev, "No Safety Features support found\n"); 2520 } 2521 } 2522 2523 /** 2524 * stmmac_hw_setup - setup mac in a usable state. 2525 * @dev : pointer to the device structure. 2526 * Description: 2527 * this is the main function to setup the HW in a usable state because the 2528 * dma engine is reset, the core registers are configured (e.g. AXI, 2529 * Checksum features, timers). The DMA is ready to start receiving and 2530 * transmitting. 2531 * Return value: 2532 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2533 * file on failure. 2534 */ 2535 static int stmmac_hw_setup(struct net_device *dev, bool init_ptp) 2536 { 2537 struct stmmac_priv *priv = netdev_priv(dev); 2538 u32 rx_cnt = priv->plat->rx_queues_to_use; 2539 u32 tx_cnt = priv->plat->tx_queues_to_use; 2540 u32 chan; 2541 int ret; 2542 2543 /* DMA initialization and SW reset */ 2544 ret = stmmac_init_dma_engine(priv); 2545 if (ret < 0) { 2546 netdev_err(priv->dev, "%s: DMA engine initialization failed\n", 2547 __func__); 2548 return ret; 2549 } 2550 2551 /* Copy the MAC addr into the HW */ 2552 stmmac_set_umac_addr(priv, priv->hw, dev->dev_addr, 0); 2553 2554 /* PS and related bits will be programmed according to the speed */ 2555 if (priv->hw->pcs) { 2556 int speed = priv->plat->mac_port_sel_speed; 2557 2558 if ((speed == SPEED_10) || (speed == SPEED_100) || 2559 (speed == SPEED_1000)) { 2560 priv->hw->ps = speed; 2561 } else { 2562 dev_warn(priv->device, "invalid port speed\n"); 2563 priv->hw->ps = 0; 2564 } 2565 } 2566 2567 /* Initialize the MAC Core */ 2568 stmmac_core_init(priv, priv->hw, dev); 2569 2570 /* Initialize MTL*/ 2571 stmmac_mtl_configuration(priv); 2572 2573 /* Initialize Safety Features */ 2574 stmmac_safety_feat_configuration(priv); 2575 2576 ret = stmmac_rx_ipc(priv, priv->hw); 2577 if (!ret) { 2578 netdev_warn(priv->dev, "RX IPC Checksum Offload disabled\n"); 2579 priv->plat->rx_coe = STMMAC_RX_COE_NONE; 2580 priv->hw->rx_csum = 0; 2581 } 2582 2583 /* Enable the MAC Rx/Tx */ 2584 stmmac_mac_set(priv, priv->ioaddr, true); 2585 2586 /* Set the HW DMA mode and the COE */ 2587 stmmac_dma_operation_mode(priv); 2588 2589 stmmac_mmc_setup(priv); 2590 2591 if (init_ptp) { 2592 ret = clk_prepare_enable(priv->plat->clk_ptp_ref); 2593 if (ret < 0) 2594 netdev_warn(priv->dev, "failed to enable PTP reference clock: %d\n", ret); 2595 2596 ret = stmmac_init_ptp(priv); 2597 if (ret == -EOPNOTSUPP) 2598 netdev_warn(priv->dev, "PTP not supported by HW\n"); 2599 else if (ret) 2600 netdev_warn(priv->dev, "PTP init failed\n"); 2601 } 2602 2603 priv->tx_lpi_timer = STMMAC_DEFAULT_TWT_LS; 2604 2605 if (priv->use_riwt) { 2606 ret = stmmac_rx_watchdog(priv, priv->ioaddr, MIN_DMA_RIWT, rx_cnt); 2607 if (!ret) 2608 priv->rx_riwt = MIN_DMA_RIWT; 2609 } 2610 2611 if (priv->hw->pcs) 2612 stmmac_pcs_ctrl_ane(priv, priv->hw, 1, priv->hw->ps, 0); 2613 2614 /* set TX and RX rings length */ 2615 stmmac_set_rings_length(priv); 2616 2617 /* Enable TSO */ 2618 if (priv->tso) { 2619 for (chan = 0; chan < tx_cnt; chan++) 2620 stmmac_enable_tso(priv, priv->ioaddr, 1, chan); 2621 } 2622 2623 /* Enable Split Header */ 2624 if (priv->sph && priv->hw->rx_csum) { 2625 for (chan = 0; chan < rx_cnt; chan++) 2626 stmmac_enable_sph(priv, priv->ioaddr, 1, chan); 2627 } 2628 2629 /* VLAN Tag Insertion */ 2630 if (priv->dma_cap.vlins) 2631 stmmac_enable_vlan(priv, priv->hw, STMMAC_VLAN_INSERT); 2632 2633 /* Start the ball rolling... */ 2634 stmmac_start_all_dma(priv); 2635 2636 return 0; 2637 } 2638 2639 static void stmmac_hw_teardown(struct net_device *dev) 2640 { 2641 struct stmmac_priv *priv = netdev_priv(dev); 2642 2643 clk_disable_unprepare(priv->plat->clk_ptp_ref); 2644 } 2645 2646 /** 2647 * stmmac_open - open entry point of the driver 2648 * @dev : pointer to the device structure. 2649 * Description: 2650 * This function is the open entry point of the driver. 2651 * Return value: 2652 * 0 on success and an appropriate (-)ve integer as defined in errno.h 2653 * file on failure. 2654 */ 2655 static int stmmac_open(struct net_device *dev) 2656 { 2657 struct stmmac_priv *priv = netdev_priv(dev); 2658 u32 chan; 2659 int ret; 2660 2661 if (priv->hw->pcs != STMMAC_PCS_RGMII && 2662 priv->hw->pcs != STMMAC_PCS_TBI && 2663 priv->hw->pcs != STMMAC_PCS_RTBI) { 2664 ret = stmmac_init_phy(dev); 2665 if (ret) { 2666 netdev_err(priv->dev, 2667 "%s: Cannot attach to PHY (error: %d)\n", 2668 __func__, ret); 2669 return ret; 2670 } 2671 } 2672 2673 /* Extra statistics */ 2674 memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats)); 2675 priv->xstats.threshold = tc; 2676 2677 priv->dma_buf_sz = STMMAC_ALIGN(buf_sz); 2678 priv->rx_copybreak = STMMAC_RX_COPYBREAK; 2679 2680 ret = alloc_dma_desc_resources(priv); 2681 if (ret < 0) { 2682 netdev_err(priv->dev, "%s: DMA descriptors allocation failed\n", 2683 __func__); 2684 goto dma_desc_error; 2685 } 2686 2687 ret = init_dma_desc_rings(dev, GFP_KERNEL); 2688 if (ret < 0) { 2689 netdev_err(priv->dev, "%s: DMA descriptors initialization failed\n", 2690 __func__); 2691 goto init_error; 2692 } 2693 2694 ret = stmmac_hw_setup(dev, true); 2695 if (ret < 0) { 2696 netdev_err(priv->dev, "%s: Hw setup failed\n", __func__); 2697 goto init_error; 2698 } 2699 2700 stmmac_init_coalesce(priv); 2701 2702 phylink_start(priv->phylink); 2703 2704 /* Request the IRQ lines */ 2705 ret = request_irq(dev->irq, stmmac_interrupt, 2706 IRQF_SHARED, dev->name, dev); 2707 if (unlikely(ret < 0)) { 2708 netdev_err(priv->dev, 2709 "%s: ERROR: allocating the IRQ %d (error: %d)\n", 2710 __func__, dev->irq, ret); 2711 goto irq_error; 2712 } 2713 2714 /* Request the Wake IRQ in case of another line is used for WoL */ 2715 if (priv->wol_irq != dev->irq) { 2716 ret = request_irq(priv->wol_irq, stmmac_interrupt, 2717 IRQF_SHARED, dev->name, dev); 2718 if (unlikely(ret < 0)) { 2719 netdev_err(priv->dev, 2720 "%s: ERROR: allocating the WoL IRQ %d (%d)\n", 2721 __func__, priv->wol_irq, ret); 2722 goto wolirq_error; 2723 } 2724 } 2725 2726 /* Request the IRQ lines */ 2727 if (priv->lpi_irq > 0) { 2728 ret = request_irq(priv->lpi_irq, stmmac_interrupt, IRQF_SHARED, 2729 dev->name, dev); 2730 if (unlikely(ret < 0)) { 2731 netdev_err(priv->dev, 2732 "%s: ERROR: allocating the LPI IRQ %d (%d)\n", 2733 __func__, priv->lpi_irq, ret); 2734 goto lpiirq_error; 2735 } 2736 } 2737 2738 stmmac_enable_all_queues(priv); 2739 stmmac_start_all_queues(priv); 2740 2741 return 0; 2742 2743 lpiirq_error: 2744 if (priv->wol_irq != dev->irq) 2745 free_irq(priv->wol_irq, dev); 2746 wolirq_error: 2747 free_irq(dev->irq, dev); 2748 irq_error: 2749 phylink_stop(priv->phylink); 2750 2751 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2752 del_timer_sync(&priv->tx_queue[chan].txtimer); 2753 2754 stmmac_hw_teardown(dev); 2755 init_error: 2756 free_dma_desc_resources(priv); 2757 dma_desc_error: 2758 phylink_disconnect_phy(priv->phylink); 2759 return ret; 2760 } 2761 2762 /** 2763 * stmmac_release - close entry point of the driver 2764 * @dev : device pointer. 2765 * Description: 2766 * This is the stop entry point of the driver. 2767 */ 2768 static int stmmac_release(struct net_device *dev) 2769 { 2770 struct stmmac_priv *priv = netdev_priv(dev); 2771 u32 chan; 2772 2773 if (priv->eee_enabled) 2774 del_timer_sync(&priv->eee_ctrl_timer); 2775 2776 /* Stop and disconnect the PHY */ 2777 phylink_stop(priv->phylink); 2778 phylink_disconnect_phy(priv->phylink); 2779 2780 stmmac_stop_all_queues(priv); 2781 2782 stmmac_disable_all_queues(priv); 2783 2784 for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++) 2785 del_timer_sync(&priv->tx_queue[chan].txtimer); 2786 2787 /* Free the IRQ lines */ 2788 free_irq(dev->irq, dev); 2789 if (priv->wol_irq != dev->irq) 2790 free_irq(priv->wol_irq, dev); 2791 if (priv->lpi_irq > 0) 2792 free_irq(priv->lpi_irq, dev); 2793 2794 /* Stop TX/RX DMA and clear the descriptors */ 2795 stmmac_stop_all_dma(priv); 2796 2797 /* Release and free the Rx/Tx resources */ 2798 free_dma_desc_resources(priv); 2799 2800 /* Disable the MAC Rx/Tx */ 2801 stmmac_mac_set(priv, priv->ioaddr, false); 2802 2803 netif_carrier_off(dev); 2804 2805 stmmac_release_ptp(priv); 2806 2807 return 0; 2808 } 2809 2810 static bool stmmac_vlan_insert(struct stmmac_priv *priv, struct sk_buff *skb, 2811 struct stmmac_tx_queue *tx_q) 2812 { 2813 u16 tag = 0x0, inner_tag = 0x0; 2814 u32 inner_type = 0x0; 2815 struct dma_desc *p; 2816 2817 if (!priv->dma_cap.vlins) 2818 return false; 2819 if (!skb_vlan_tag_present(skb)) 2820 return false; 2821 if (skb->vlan_proto == htons(ETH_P_8021AD)) { 2822 inner_tag = skb_vlan_tag_get(skb); 2823 inner_type = STMMAC_VLAN_INSERT; 2824 } 2825 2826 tag = skb_vlan_tag_get(skb); 2827 2828 p = tx_q->dma_tx + tx_q->cur_tx; 2829 if (stmmac_set_desc_vlan_tag(priv, p, tag, inner_tag, inner_type)) 2830 return false; 2831 2832 stmmac_set_tx_owner(priv, p); 2833 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2834 return true; 2835 } 2836 2837 /** 2838 * stmmac_tso_allocator - close entry point of the driver 2839 * @priv: driver private structure 2840 * @des: buffer start address 2841 * @total_len: total length to fill in descriptors 2842 * @last_segmant: condition for the last descriptor 2843 * @queue: TX queue index 2844 * Description: 2845 * This function fills descriptor and request new descriptors according to 2846 * buffer length to fill 2847 */ 2848 static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des, 2849 int total_len, bool last_segment, u32 queue) 2850 { 2851 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 2852 struct dma_desc *desc; 2853 u32 buff_size; 2854 int tmp_len; 2855 2856 tmp_len = total_len; 2857 2858 while (tmp_len > 0) { 2859 dma_addr_t curr_addr; 2860 2861 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2862 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2863 desc = tx_q->dma_tx + tx_q->cur_tx; 2864 2865 curr_addr = des + (total_len - tmp_len); 2866 if (priv->dma_cap.addr64 <= 32) 2867 desc->des0 = cpu_to_le32(curr_addr); 2868 else 2869 stmmac_set_desc_addr(priv, desc, curr_addr); 2870 2871 buff_size = tmp_len >= TSO_MAX_BUFF_SIZE ? 2872 TSO_MAX_BUFF_SIZE : tmp_len; 2873 2874 stmmac_prepare_tso_tx_desc(priv, desc, 0, buff_size, 2875 0, 1, 2876 (last_segment) && (tmp_len <= TSO_MAX_BUFF_SIZE), 2877 0, 0); 2878 2879 tmp_len -= TSO_MAX_BUFF_SIZE; 2880 } 2881 } 2882 2883 /** 2884 * stmmac_tso_xmit - Tx entry point of the driver for oversized frames (TSO) 2885 * @skb : the socket buffer 2886 * @dev : device pointer 2887 * Description: this is the transmit function that is called on TSO frames 2888 * (support available on GMAC4 and newer chips). 2889 * Diagram below show the ring programming in case of TSO frames: 2890 * 2891 * First Descriptor 2892 * -------- 2893 * | DES0 |---> buffer1 = L2/L3/L4 header 2894 * | DES1 |---> TCP Payload (can continue on next descr...) 2895 * | DES2 |---> buffer 1 and 2 len 2896 * | DES3 |---> must set TSE, TCP hdr len-> [22:19]. TCP payload len [17:0] 2897 * -------- 2898 * | 2899 * ... 2900 * | 2901 * -------- 2902 * | DES0 | --| Split TCP Payload on Buffers 1 and 2 2903 * | DES1 | --| 2904 * | DES2 | --> buffer 1 and 2 len 2905 * | DES3 | 2906 * -------- 2907 * 2908 * mss is fixed when enable tso, so w/o programming the TDES3 ctx field. 2909 */ 2910 static netdev_tx_t stmmac_tso_xmit(struct sk_buff *skb, struct net_device *dev) 2911 { 2912 struct dma_desc *desc, *first, *mss_desc = NULL; 2913 struct stmmac_priv *priv = netdev_priv(dev); 2914 int nfrags = skb_shinfo(skb)->nr_frags; 2915 u32 queue = skb_get_queue_mapping(skb); 2916 struct stmmac_tx_queue *tx_q; 2917 unsigned int first_entry; 2918 int tmp_pay_len = 0; 2919 u32 pay_len, mss; 2920 u8 proto_hdr_len; 2921 dma_addr_t des; 2922 bool has_vlan; 2923 int i; 2924 2925 tx_q = &priv->tx_queue[queue]; 2926 2927 /* Compute header lengths */ 2928 proto_hdr_len = skb_transport_offset(skb) + tcp_hdrlen(skb); 2929 2930 /* Desc availability based on threshold should be enough safe */ 2931 if (unlikely(stmmac_tx_avail(priv, queue) < 2932 (((skb->len - proto_hdr_len) / TSO_MAX_BUFF_SIZE + 1)))) { 2933 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 2934 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 2935 queue)); 2936 /* This is a hard error, log it. */ 2937 netdev_err(priv->dev, 2938 "%s: Tx Ring full when queue awake\n", 2939 __func__); 2940 } 2941 return NETDEV_TX_BUSY; 2942 } 2943 2944 pay_len = skb_headlen(skb) - proto_hdr_len; /* no frags */ 2945 2946 mss = skb_shinfo(skb)->gso_size; 2947 2948 /* set new MSS value if needed */ 2949 if (mss != tx_q->mss) { 2950 mss_desc = tx_q->dma_tx + tx_q->cur_tx; 2951 stmmac_set_mss(priv, mss_desc, mss); 2952 tx_q->mss = mss; 2953 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 2954 WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]); 2955 } 2956 2957 if (netif_msg_tx_queued(priv)) { 2958 pr_info("%s: tcphdrlen %d, hdr_len %d, pay_len %d, mss %d\n", 2959 __func__, tcp_hdrlen(skb), proto_hdr_len, pay_len, mss); 2960 pr_info("\tskb->len %d, skb->data_len %d\n", skb->len, 2961 skb->data_len); 2962 } 2963 2964 /* Check if VLAN can be inserted by HW */ 2965 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 2966 2967 first_entry = tx_q->cur_tx; 2968 WARN_ON(tx_q->tx_skbuff[first_entry]); 2969 2970 desc = tx_q->dma_tx + first_entry; 2971 first = desc; 2972 2973 if (has_vlan) 2974 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 2975 2976 /* first descriptor: fill Headers on Buf1 */ 2977 des = dma_map_single(priv->device, skb->data, skb_headlen(skb), 2978 DMA_TO_DEVICE); 2979 if (dma_mapping_error(priv->device, des)) 2980 goto dma_map_err; 2981 2982 tx_q->tx_skbuff_dma[first_entry].buf = des; 2983 tx_q->tx_skbuff_dma[first_entry].len = skb_headlen(skb); 2984 2985 if (priv->dma_cap.addr64 <= 32) { 2986 first->des0 = cpu_to_le32(des); 2987 2988 /* Fill start of payload in buff2 of first descriptor */ 2989 if (pay_len) 2990 first->des1 = cpu_to_le32(des + proto_hdr_len); 2991 2992 /* If needed take extra descriptors to fill the remaining payload */ 2993 tmp_pay_len = pay_len - TSO_MAX_BUFF_SIZE; 2994 } else { 2995 stmmac_set_desc_addr(priv, first, des); 2996 tmp_pay_len = pay_len; 2997 } 2998 2999 stmmac_tso_allocator(priv, des, tmp_pay_len, (nfrags == 0), queue); 3000 3001 /* Prepare fragments */ 3002 for (i = 0; i < nfrags; i++) { 3003 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3004 3005 des = skb_frag_dma_map(priv->device, frag, 0, 3006 skb_frag_size(frag), 3007 DMA_TO_DEVICE); 3008 if (dma_mapping_error(priv->device, des)) 3009 goto dma_map_err; 3010 3011 stmmac_tso_allocator(priv, des, skb_frag_size(frag), 3012 (i == nfrags - 1), queue); 3013 3014 tx_q->tx_skbuff_dma[tx_q->cur_tx].buf = des; 3015 tx_q->tx_skbuff_dma[tx_q->cur_tx].len = skb_frag_size(frag); 3016 tx_q->tx_skbuff_dma[tx_q->cur_tx].map_as_page = true; 3017 } 3018 3019 tx_q->tx_skbuff_dma[tx_q->cur_tx].last_segment = true; 3020 3021 /* Only the last descriptor gets to point to the skb. */ 3022 tx_q->tx_skbuff[tx_q->cur_tx] = skb; 3023 3024 /* We've used all descriptors we need for this skb, however, 3025 * advance cur_tx so that it references a fresh descriptor. 3026 * ndo_start_xmit will fill this descriptor the next time it's 3027 * called and stmmac_tx_clean may clean up to this descriptor. 3028 */ 3029 tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx, DMA_TX_SIZE); 3030 3031 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3032 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3033 __func__); 3034 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3035 } 3036 3037 dev->stats.tx_bytes += skb->len; 3038 priv->xstats.tx_tso_frames++; 3039 priv->xstats.tx_tso_nfrags += nfrags; 3040 3041 /* Manage tx mitigation */ 3042 tx_q->tx_count_frames += nfrags + 1; 3043 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 3044 !(priv->synopsys_id >= DWMAC_CORE_4_00 && 3045 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3046 priv->hwts_tx_en)) { 3047 stmmac_tx_timer_arm(priv, queue); 3048 } else { 3049 tx_q->tx_count_frames = 0; 3050 stmmac_set_tx_ic(priv, desc); 3051 priv->xstats.tx_set_ic_bit++; 3052 } 3053 3054 if (priv->sarc_type) 3055 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3056 3057 skb_tx_timestamp(skb); 3058 3059 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3060 priv->hwts_tx_en)) { 3061 /* declare that device is doing timestamping */ 3062 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3063 stmmac_enable_tx_timestamp(priv, first); 3064 } 3065 3066 /* Complete the first descriptor before granting the DMA */ 3067 stmmac_prepare_tso_tx_desc(priv, first, 1, 3068 proto_hdr_len, 3069 pay_len, 3070 1, tx_q->tx_skbuff_dma[first_entry].last_segment, 3071 tcp_hdrlen(skb) / 4, (skb->len - proto_hdr_len)); 3072 3073 /* If context desc is used to change MSS */ 3074 if (mss_desc) { 3075 /* Make sure that first descriptor has been completely 3076 * written, including its own bit. This is because MSS is 3077 * actually before first descriptor, so we need to make 3078 * sure that MSS's own bit is the last thing written. 3079 */ 3080 dma_wmb(); 3081 stmmac_set_tx_owner(priv, mss_desc); 3082 } 3083 3084 /* The own bit must be the latest setting done when prepare the 3085 * descriptor and then barrier is needed to make sure that 3086 * all is coherent before granting the DMA engine. 3087 */ 3088 wmb(); 3089 3090 if (netif_msg_pktdata(priv)) { 3091 pr_info("%s: curr=%d dirty=%d f=%d, e=%d, f_p=%p, nfrags %d\n", 3092 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3093 tx_q->cur_tx, first, nfrags); 3094 3095 stmmac_display_ring(priv, (void *)tx_q->dma_tx, DMA_TX_SIZE, 0); 3096 3097 pr_info(">>> frame to be transmitted: "); 3098 print_pkt(skb->data, skb_headlen(skb)); 3099 } 3100 3101 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3102 3103 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3104 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3105 3106 return NETDEV_TX_OK; 3107 3108 dma_map_err: 3109 dev_err(priv->device, "Tx dma map failed\n"); 3110 dev_kfree_skb(skb); 3111 priv->dev->stats.tx_dropped++; 3112 return NETDEV_TX_OK; 3113 } 3114 3115 /** 3116 * stmmac_xmit - Tx entry point of the driver 3117 * @skb : the socket buffer 3118 * @dev : device pointer 3119 * Description : this is the tx entry point of the driver. 3120 * It programs the chain or the ring and supports oversized frames 3121 * and SG feature. 3122 */ 3123 static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev) 3124 { 3125 struct stmmac_priv *priv = netdev_priv(dev); 3126 unsigned int nopaged_len = skb_headlen(skb); 3127 int i, csum_insertion = 0, is_jumbo = 0; 3128 u32 queue = skb_get_queue_mapping(skb); 3129 int nfrags = skb_shinfo(skb)->nr_frags; 3130 struct dma_desc *desc, *first; 3131 struct stmmac_tx_queue *tx_q; 3132 unsigned int first_entry; 3133 unsigned int enh_desc; 3134 dma_addr_t des; 3135 bool has_vlan; 3136 int entry; 3137 3138 tx_q = &priv->tx_queue[queue]; 3139 3140 if (priv->tx_path_in_lpi_mode) 3141 stmmac_disable_eee_mode(priv); 3142 3143 /* Manage oversized TCP frames for GMAC4 device */ 3144 if (skb_is_gso(skb) && priv->tso) { 3145 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) 3146 return stmmac_tso_xmit(skb, dev); 3147 } 3148 3149 if (unlikely(stmmac_tx_avail(priv, queue) < nfrags + 1)) { 3150 if (!netif_tx_queue_stopped(netdev_get_tx_queue(dev, queue))) { 3151 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, 3152 queue)); 3153 /* This is a hard error, log it. */ 3154 netdev_err(priv->dev, 3155 "%s: Tx Ring full when queue awake\n", 3156 __func__); 3157 } 3158 return NETDEV_TX_BUSY; 3159 } 3160 3161 /* Check if VLAN can be inserted by HW */ 3162 has_vlan = stmmac_vlan_insert(priv, skb, tx_q); 3163 3164 entry = tx_q->cur_tx; 3165 first_entry = entry; 3166 WARN_ON(tx_q->tx_skbuff[first_entry]); 3167 3168 csum_insertion = (skb->ip_summed == CHECKSUM_PARTIAL); 3169 3170 if (likely(priv->extend_desc)) 3171 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3172 else 3173 desc = tx_q->dma_tx + entry; 3174 3175 first = desc; 3176 3177 if (has_vlan) 3178 stmmac_set_desc_vlan(priv, first, STMMAC_VLAN_INSERT); 3179 3180 enh_desc = priv->plat->enh_desc; 3181 /* To program the descriptors according to the size of the frame */ 3182 if (enh_desc) 3183 is_jumbo = stmmac_is_jumbo_frm(priv, skb->len, enh_desc); 3184 3185 if (unlikely(is_jumbo)) { 3186 entry = stmmac_jumbo_frm(priv, tx_q, skb, csum_insertion); 3187 if (unlikely(entry < 0) && (entry != -EINVAL)) 3188 goto dma_map_err; 3189 } 3190 3191 for (i = 0; i < nfrags; i++) { 3192 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i]; 3193 int len = skb_frag_size(frag); 3194 bool last_segment = (i == (nfrags - 1)); 3195 3196 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3197 WARN_ON(tx_q->tx_skbuff[entry]); 3198 3199 if (likely(priv->extend_desc)) 3200 desc = (struct dma_desc *)(tx_q->dma_etx + entry); 3201 else 3202 desc = tx_q->dma_tx + entry; 3203 3204 des = skb_frag_dma_map(priv->device, frag, 0, len, 3205 DMA_TO_DEVICE); 3206 if (dma_mapping_error(priv->device, des)) 3207 goto dma_map_err; /* should reuse desc w/o issues */ 3208 3209 tx_q->tx_skbuff_dma[entry].buf = des; 3210 3211 stmmac_set_desc_addr(priv, desc, des); 3212 3213 tx_q->tx_skbuff_dma[entry].map_as_page = true; 3214 tx_q->tx_skbuff_dma[entry].len = len; 3215 tx_q->tx_skbuff_dma[entry].last_segment = last_segment; 3216 3217 /* Prepare the descriptor and set the own bit too */ 3218 stmmac_prepare_tx_desc(priv, desc, 0, len, csum_insertion, 3219 priv->mode, 1, last_segment, skb->len); 3220 } 3221 3222 /* Only the last descriptor gets to point to the skb. */ 3223 tx_q->tx_skbuff[entry] = skb; 3224 3225 /* We've used all descriptors we need for this skb, however, 3226 * advance cur_tx so that it references a fresh descriptor. 3227 * ndo_start_xmit will fill this descriptor the next time it's 3228 * called and stmmac_tx_clean may clean up to this descriptor. 3229 */ 3230 entry = STMMAC_GET_ENTRY(entry, DMA_TX_SIZE); 3231 tx_q->cur_tx = entry; 3232 3233 if (netif_msg_pktdata(priv)) { 3234 void *tx_head; 3235 3236 netdev_dbg(priv->dev, 3237 "%s: curr=%d dirty=%d f=%d, e=%d, first=%p, nfrags=%d", 3238 __func__, tx_q->cur_tx, tx_q->dirty_tx, first_entry, 3239 entry, first, nfrags); 3240 3241 if (priv->extend_desc) 3242 tx_head = (void *)tx_q->dma_etx; 3243 else 3244 tx_head = (void *)tx_q->dma_tx; 3245 3246 stmmac_display_ring(priv, tx_head, DMA_TX_SIZE, false); 3247 3248 netdev_dbg(priv->dev, ">>> frame to be transmitted: "); 3249 print_pkt(skb->data, skb->len); 3250 } 3251 3252 if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) { 3253 netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n", 3254 __func__); 3255 netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, queue)); 3256 } 3257 3258 dev->stats.tx_bytes += skb->len; 3259 3260 /* According to the coalesce parameter the IC bit for the latest 3261 * segment is reset and the timer re-started to clean the tx status. 3262 * This approach takes care about the fragments: desc is the first 3263 * element in case of no SG. 3264 */ 3265 tx_q->tx_count_frames += nfrags + 1; 3266 if (likely(priv->tx_coal_frames > tx_q->tx_count_frames) && 3267 !(priv->synopsys_id >= DWMAC_CORE_4_00 && 3268 (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3269 priv->hwts_tx_en)) { 3270 stmmac_tx_timer_arm(priv, queue); 3271 } else { 3272 tx_q->tx_count_frames = 0; 3273 stmmac_set_tx_ic(priv, desc); 3274 priv->xstats.tx_set_ic_bit++; 3275 } 3276 3277 if (priv->sarc_type) 3278 stmmac_set_desc_sarc(priv, first, priv->sarc_type); 3279 3280 skb_tx_timestamp(skb); 3281 3282 /* Ready to fill the first descriptor and set the OWN bit w/o any 3283 * problems because all the descriptors are actually ready to be 3284 * passed to the DMA engine. 3285 */ 3286 if (likely(!is_jumbo)) { 3287 bool last_segment = (nfrags == 0); 3288 3289 des = dma_map_single(priv->device, skb->data, 3290 nopaged_len, DMA_TO_DEVICE); 3291 if (dma_mapping_error(priv->device, des)) 3292 goto dma_map_err; 3293 3294 tx_q->tx_skbuff_dma[first_entry].buf = des; 3295 3296 stmmac_set_desc_addr(priv, first, des); 3297 3298 tx_q->tx_skbuff_dma[first_entry].len = nopaged_len; 3299 tx_q->tx_skbuff_dma[first_entry].last_segment = last_segment; 3300 3301 if (unlikely((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) && 3302 priv->hwts_tx_en)) { 3303 /* declare that device is doing timestamping */ 3304 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS; 3305 stmmac_enable_tx_timestamp(priv, first); 3306 } 3307 3308 /* Prepare the first descriptor setting the OWN bit too */ 3309 stmmac_prepare_tx_desc(priv, first, 1, nopaged_len, 3310 csum_insertion, priv->mode, 1, last_segment, 3311 skb->len); 3312 } else { 3313 stmmac_set_tx_owner(priv, first); 3314 } 3315 3316 /* The own bit must be the latest setting done when prepare the 3317 * descriptor and then barrier is needed to make sure that 3318 * all is coherent before granting the DMA engine. 3319 */ 3320 wmb(); 3321 3322 netdev_tx_sent_queue(netdev_get_tx_queue(dev, queue), skb->len); 3323 3324 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3325 3326 tx_q->tx_tail_addr = tx_q->dma_tx_phy + (tx_q->cur_tx * sizeof(*desc)); 3327 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, queue); 3328 3329 return NETDEV_TX_OK; 3330 3331 dma_map_err: 3332 netdev_err(priv->dev, "Tx DMA map failed\n"); 3333 dev_kfree_skb(skb); 3334 priv->dev->stats.tx_dropped++; 3335 return NETDEV_TX_OK; 3336 } 3337 3338 static void stmmac_rx_vlan(struct net_device *dev, struct sk_buff *skb) 3339 { 3340 struct vlan_ethhdr *veth; 3341 __be16 vlan_proto; 3342 u16 vlanid; 3343 3344 veth = (struct vlan_ethhdr *)skb->data; 3345 vlan_proto = veth->h_vlan_proto; 3346 3347 if ((vlan_proto == htons(ETH_P_8021Q) && 3348 dev->features & NETIF_F_HW_VLAN_CTAG_RX) || 3349 (vlan_proto == htons(ETH_P_8021AD) && 3350 dev->features & NETIF_F_HW_VLAN_STAG_RX)) { 3351 /* pop the vlan tag */ 3352 vlanid = ntohs(veth->h_vlan_TCI); 3353 memmove(skb->data + VLAN_HLEN, veth, ETH_ALEN * 2); 3354 skb_pull(skb, VLAN_HLEN); 3355 __vlan_hwaccel_put_tag(skb, vlan_proto, vlanid); 3356 } 3357 } 3358 3359 3360 static inline int stmmac_rx_threshold_count(struct stmmac_rx_queue *rx_q) 3361 { 3362 if (rx_q->rx_zeroc_thresh < STMMAC_RX_THRESH) 3363 return 0; 3364 3365 return 1; 3366 } 3367 3368 /** 3369 * stmmac_rx_refill - refill used skb preallocated buffers 3370 * @priv: driver private structure 3371 * @queue: RX queue index 3372 * Description : this is to reallocate the skb for the reception process 3373 * that is based on zero-copy. 3374 */ 3375 static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue) 3376 { 3377 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3378 int len, dirty = stmmac_rx_dirty(priv, queue); 3379 unsigned int entry = rx_q->dirty_rx; 3380 3381 len = DIV_ROUND_UP(priv->dma_buf_sz, PAGE_SIZE) * PAGE_SIZE; 3382 3383 while (dirty-- > 0) { 3384 struct stmmac_rx_buffer *buf = &rx_q->buf_pool[entry]; 3385 struct dma_desc *p; 3386 bool use_rx_wd; 3387 3388 if (priv->extend_desc) 3389 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3390 else 3391 p = rx_q->dma_rx + entry; 3392 3393 if (!buf->page) { 3394 buf->page = page_pool_dev_alloc_pages(rx_q->page_pool); 3395 if (!buf->page) 3396 break; 3397 } 3398 3399 if (priv->sph && !buf->sec_page) { 3400 buf->sec_page = page_pool_dev_alloc_pages(rx_q->page_pool); 3401 if (!buf->sec_page) 3402 break; 3403 3404 buf->sec_addr = page_pool_get_dma_addr(buf->sec_page); 3405 3406 dma_sync_single_for_device(priv->device, buf->sec_addr, 3407 len, DMA_FROM_DEVICE); 3408 } 3409 3410 buf->addr = page_pool_get_dma_addr(buf->page); 3411 3412 /* Sync whole allocation to device. This will invalidate old 3413 * data. 3414 */ 3415 dma_sync_single_for_device(priv->device, buf->addr, len, 3416 DMA_FROM_DEVICE); 3417 3418 stmmac_set_desc_addr(priv, p, buf->addr); 3419 stmmac_set_desc_sec_addr(priv, p, buf->sec_addr); 3420 stmmac_refill_desc3(priv, rx_q, p); 3421 3422 rx_q->rx_count_frames++; 3423 rx_q->rx_count_frames += priv->rx_coal_frames; 3424 if (rx_q->rx_count_frames > priv->rx_coal_frames) 3425 rx_q->rx_count_frames = 0; 3426 use_rx_wd = priv->use_riwt && rx_q->rx_count_frames; 3427 3428 dma_wmb(); 3429 stmmac_set_rx_owner(priv, p, use_rx_wd); 3430 3431 entry = STMMAC_GET_ENTRY(entry, DMA_RX_SIZE); 3432 } 3433 rx_q->dirty_rx = entry; 3434 rx_q->rx_tail_addr = rx_q->dma_rx_phy + 3435 (rx_q->dirty_rx * sizeof(struct dma_desc)); 3436 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, rx_q->rx_tail_addr, queue); 3437 } 3438 3439 /** 3440 * stmmac_rx - manage the receive process 3441 * @priv: driver private structure 3442 * @limit: napi bugget 3443 * @queue: RX queue index. 3444 * Description : this the function called by the napi poll method. 3445 * It gets all the frames inside the ring. 3446 */ 3447 static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue) 3448 { 3449 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3450 struct stmmac_channel *ch = &priv->channel[queue]; 3451 unsigned int count = 0, error = 0, len = 0; 3452 int status = 0, coe = priv->hw->rx_csum; 3453 unsigned int next_entry = rx_q->cur_rx; 3454 struct sk_buff *skb = NULL; 3455 3456 if (netif_msg_rx_status(priv)) { 3457 void *rx_head; 3458 3459 netdev_dbg(priv->dev, "%s: descriptor ring:\n", __func__); 3460 if (priv->extend_desc) 3461 rx_head = (void *)rx_q->dma_erx; 3462 else 3463 rx_head = (void *)rx_q->dma_rx; 3464 3465 stmmac_display_ring(priv, rx_head, DMA_RX_SIZE, true); 3466 } 3467 while (count < limit) { 3468 unsigned int hlen = 0, prev_len = 0; 3469 enum pkt_hash_types hash_type; 3470 struct stmmac_rx_buffer *buf; 3471 struct dma_desc *np, *p; 3472 unsigned int sec_len; 3473 int entry; 3474 u32 hash; 3475 3476 if (!count && rx_q->state_saved) { 3477 skb = rx_q->state.skb; 3478 error = rx_q->state.error; 3479 len = rx_q->state.len; 3480 } else { 3481 rx_q->state_saved = false; 3482 skb = NULL; 3483 error = 0; 3484 len = 0; 3485 } 3486 3487 if (count >= limit) 3488 break; 3489 3490 read_again: 3491 sec_len = 0; 3492 entry = next_entry; 3493 buf = &rx_q->buf_pool[entry]; 3494 3495 if (priv->extend_desc) 3496 p = (struct dma_desc *)(rx_q->dma_erx + entry); 3497 else 3498 p = rx_q->dma_rx + entry; 3499 3500 /* read the status of the incoming frame */ 3501 status = stmmac_rx_status(priv, &priv->dev->stats, 3502 &priv->xstats, p); 3503 /* check if managed by the DMA otherwise go ahead */ 3504 if (unlikely(status & dma_own)) 3505 break; 3506 3507 count++; 3508 3509 rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx, DMA_RX_SIZE); 3510 next_entry = rx_q->cur_rx; 3511 3512 if (priv->extend_desc) 3513 np = (struct dma_desc *)(rx_q->dma_erx + next_entry); 3514 else 3515 np = rx_q->dma_rx + next_entry; 3516 3517 prefetch(np); 3518 prefetch(page_address(buf->page)); 3519 3520 if (priv->extend_desc) 3521 stmmac_rx_extended_status(priv, &priv->dev->stats, 3522 &priv->xstats, rx_q->dma_erx + entry); 3523 if (unlikely(status == discard_frame)) { 3524 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3525 buf->page = NULL; 3526 error = 1; 3527 if (!priv->hwts_rx_en) 3528 priv->dev->stats.rx_errors++; 3529 } 3530 3531 if (unlikely(error && (status & rx_not_ls))) 3532 goto read_again; 3533 if (unlikely(error)) { 3534 dev_kfree_skb(skb); 3535 continue; 3536 } 3537 3538 /* Buffer is good. Go on. */ 3539 3540 if (likely(status & rx_not_ls)) { 3541 len += priv->dma_buf_sz; 3542 } else { 3543 prev_len = len; 3544 len = stmmac_get_rx_frame_len(priv, p, coe); 3545 3546 /* ACS is set; GMAC core strips PAD/FCS for IEEE 802.3 3547 * Type frames (LLC/LLC-SNAP) 3548 * 3549 * llc_snap is never checked in GMAC >= 4, so this ACS 3550 * feature is always disabled and packets need to be 3551 * stripped manually. 3552 */ 3553 if (unlikely(priv->synopsys_id >= DWMAC_CORE_4_00) || 3554 unlikely(status != llc_snap)) 3555 len -= ETH_FCS_LEN; 3556 } 3557 3558 if (!skb) { 3559 int ret = stmmac_get_rx_header_len(priv, p, &hlen); 3560 3561 if (priv->sph && !ret && (hlen > 0)) { 3562 sec_len = len; 3563 if (!(status & rx_not_ls)) 3564 sec_len = sec_len - hlen; 3565 len = hlen; 3566 3567 prefetch(page_address(buf->sec_page)); 3568 priv->xstats.rx_split_hdr_pkt_n++; 3569 } 3570 3571 skb = napi_alloc_skb(&ch->rx_napi, len); 3572 if (!skb) { 3573 priv->dev->stats.rx_dropped++; 3574 continue; 3575 } 3576 3577 dma_sync_single_for_cpu(priv->device, buf->addr, len, 3578 DMA_FROM_DEVICE); 3579 skb_copy_to_linear_data(skb, page_address(buf->page), 3580 len); 3581 skb_put(skb, len); 3582 3583 /* Data payload copied into SKB, page ready for recycle */ 3584 page_pool_recycle_direct(rx_q->page_pool, buf->page); 3585 buf->page = NULL; 3586 } else { 3587 unsigned int buf_len = len - prev_len; 3588 3589 if (likely(status & rx_not_ls)) 3590 buf_len = priv->dma_buf_sz; 3591 3592 dma_sync_single_for_cpu(priv->device, buf->addr, 3593 buf_len, DMA_FROM_DEVICE); 3594 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3595 buf->page, 0, buf_len, 3596 priv->dma_buf_sz); 3597 3598 /* Data payload appended into SKB */ 3599 page_pool_release_page(rx_q->page_pool, buf->page); 3600 buf->page = NULL; 3601 } 3602 3603 if (sec_len > 0) { 3604 dma_sync_single_for_cpu(priv->device, buf->sec_addr, 3605 sec_len, DMA_FROM_DEVICE); 3606 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, 3607 buf->sec_page, 0, sec_len, 3608 priv->dma_buf_sz); 3609 3610 len += sec_len; 3611 3612 /* Data payload appended into SKB */ 3613 page_pool_release_page(rx_q->page_pool, buf->sec_page); 3614 buf->sec_page = NULL; 3615 } 3616 3617 if (likely(status & rx_not_ls)) 3618 goto read_again; 3619 3620 /* Got entire packet into SKB. Finish it. */ 3621 3622 stmmac_get_rx_hwtstamp(priv, p, np, skb); 3623 stmmac_rx_vlan(priv->dev, skb); 3624 skb->protocol = eth_type_trans(skb, priv->dev); 3625 3626 if (unlikely(!coe)) 3627 skb_checksum_none_assert(skb); 3628 else 3629 skb->ip_summed = CHECKSUM_UNNECESSARY; 3630 3631 if (!stmmac_get_rx_hash(priv, p, &hash, &hash_type)) 3632 skb_set_hash(skb, hash, hash_type); 3633 3634 skb_record_rx_queue(skb, queue); 3635 napi_gro_receive(&ch->rx_napi, skb); 3636 3637 priv->dev->stats.rx_packets++; 3638 priv->dev->stats.rx_bytes += len; 3639 } 3640 3641 if (status & rx_not_ls) { 3642 rx_q->state_saved = true; 3643 rx_q->state.skb = skb; 3644 rx_q->state.error = error; 3645 rx_q->state.len = len; 3646 } 3647 3648 stmmac_rx_refill(priv, queue); 3649 3650 priv->xstats.rx_pkt_n += count; 3651 3652 return count; 3653 } 3654 3655 static int stmmac_napi_poll_rx(struct napi_struct *napi, int budget) 3656 { 3657 struct stmmac_channel *ch = 3658 container_of(napi, struct stmmac_channel, rx_napi); 3659 struct stmmac_priv *priv = ch->priv_data; 3660 u32 chan = ch->index; 3661 int work_done; 3662 3663 priv->xstats.napi_poll++; 3664 3665 work_done = stmmac_rx(priv, budget, chan); 3666 if (work_done < budget && napi_complete_done(napi, work_done)) 3667 stmmac_enable_dma_irq(priv, priv->ioaddr, chan); 3668 return work_done; 3669 } 3670 3671 static int stmmac_napi_poll_tx(struct napi_struct *napi, int budget) 3672 { 3673 struct stmmac_channel *ch = 3674 container_of(napi, struct stmmac_channel, tx_napi); 3675 struct stmmac_priv *priv = ch->priv_data; 3676 struct stmmac_tx_queue *tx_q; 3677 u32 chan = ch->index; 3678 int work_done; 3679 3680 priv->xstats.napi_poll++; 3681 3682 work_done = stmmac_tx_clean(priv, DMA_TX_SIZE, chan); 3683 work_done = min(work_done, budget); 3684 3685 if (work_done < budget) 3686 napi_complete_done(napi, work_done); 3687 3688 /* Force transmission restart */ 3689 tx_q = &priv->tx_queue[chan]; 3690 if (tx_q->cur_tx != tx_q->dirty_tx) { 3691 stmmac_enable_dma_transmission(priv, priv->ioaddr); 3692 stmmac_set_tx_tail_ptr(priv, priv->ioaddr, tx_q->tx_tail_addr, 3693 chan); 3694 } 3695 3696 return work_done; 3697 } 3698 3699 /** 3700 * stmmac_tx_timeout 3701 * @dev : Pointer to net device structure 3702 * Description: this function is called when a packet transmission fails to 3703 * complete within a reasonable time. The driver will mark the error in the 3704 * netdev structure and arrange for the device to be reset to a sane state 3705 * in order to transmit a new packet. 3706 */ 3707 static void stmmac_tx_timeout(struct net_device *dev) 3708 { 3709 struct stmmac_priv *priv = netdev_priv(dev); 3710 3711 stmmac_global_err(priv); 3712 } 3713 3714 /** 3715 * stmmac_set_rx_mode - entry point for multicast addressing 3716 * @dev : pointer to the device structure 3717 * Description: 3718 * This function is a driver entry point which gets called by the kernel 3719 * whenever multicast addresses must be enabled/disabled. 3720 * Return value: 3721 * void. 3722 */ 3723 static void stmmac_set_rx_mode(struct net_device *dev) 3724 { 3725 struct stmmac_priv *priv = netdev_priv(dev); 3726 3727 stmmac_set_filter(priv, priv->hw, dev); 3728 } 3729 3730 /** 3731 * stmmac_change_mtu - entry point to change MTU size for the device. 3732 * @dev : device pointer. 3733 * @new_mtu : the new MTU size for the device. 3734 * Description: the Maximum Transfer Unit (MTU) is used by the network layer 3735 * to drive packet transmission. Ethernet has an MTU of 1500 octets 3736 * (ETH_DATA_LEN). This value can be changed with ifconfig. 3737 * Return value: 3738 * 0 on success and an appropriate (-)ve integer as defined in errno.h 3739 * file on failure. 3740 */ 3741 static int stmmac_change_mtu(struct net_device *dev, int new_mtu) 3742 { 3743 struct stmmac_priv *priv = netdev_priv(dev); 3744 3745 if (netif_running(dev)) { 3746 netdev_err(priv->dev, "must be stopped to change its MTU\n"); 3747 return -EBUSY; 3748 } 3749 3750 dev->mtu = new_mtu; 3751 3752 netdev_update_features(dev); 3753 3754 return 0; 3755 } 3756 3757 static netdev_features_t stmmac_fix_features(struct net_device *dev, 3758 netdev_features_t features) 3759 { 3760 struct stmmac_priv *priv = netdev_priv(dev); 3761 3762 if (priv->plat->rx_coe == STMMAC_RX_COE_NONE) 3763 features &= ~NETIF_F_RXCSUM; 3764 3765 if (!priv->plat->tx_coe) 3766 features &= ~NETIF_F_CSUM_MASK; 3767 3768 /* Some GMAC devices have a bugged Jumbo frame support that 3769 * needs to have the Tx COE disabled for oversized frames 3770 * (due to limited buffer sizes). In this case we disable 3771 * the TX csum insertion in the TDES and not use SF. 3772 */ 3773 if (priv->plat->bugged_jumbo && (dev->mtu > ETH_DATA_LEN)) 3774 features &= ~NETIF_F_CSUM_MASK; 3775 3776 /* Disable tso if asked by ethtool */ 3777 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 3778 if (features & NETIF_F_TSO) 3779 priv->tso = true; 3780 else 3781 priv->tso = false; 3782 } 3783 3784 return features; 3785 } 3786 3787 static int stmmac_set_features(struct net_device *netdev, 3788 netdev_features_t features) 3789 { 3790 struct stmmac_priv *priv = netdev_priv(netdev); 3791 bool sph_en; 3792 u32 chan; 3793 3794 /* Keep the COE Type in case of csum is supporting */ 3795 if (features & NETIF_F_RXCSUM) 3796 priv->hw->rx_csum = priv->plat->rx_coe; 3797 else 3798 priv->hw->rx_csum = 0; 3799 /* No check needed because rx_coe has been set before and it will be 3800 * fixed in case of issue. 3801 */ 3802 stmmac_rx_ipc(priv, priv->hw); 3803 3804 sph_en = (priv->hw->rx_csum > 0) && priv->sph; 3805 for (chan = 0; chan < priv->plat->rx_queues_to_use; chan++) 3806 stmmac_enable_sph(priv, priv->ioaddr, sph_en, chan); 3807 3808 return 0; 3809 } 3810 3811 /** 3812 * stmmac_interrupt - main ISR 3813 * @irq: interrupt number. 3814 * @dev_id: to pass the net device pointer. 3815 * Description: this is the main driver interrupt service routine. 3816 * It can call: 3817 * o DMA service routine (to manage incoming frame reception and transmission 3818 * status) 3819 * o Core interrupts to manage: remote wake-up, management counter, LPI 3820 * interrupts. 3821 */ 3822 static irqreturn_t stmmac_interrupt(int irq, void *dev_id) 3823 { 3824 struct net_device *dev = (struct net_device *)dev_id; 3825 struct stmmac_priv *priv = netdev_priv(dev); 3826 u32 rx_cnt = priv->plat->rx_queues_to_use; 3827 u32 tx_cnt = priv->plat->tx_queues_to_use; 3828 u32 queues_count; 3829 u32 queue; 3830 bool xmac; 3831 3832 xmac = priv->plat->has_gmac4 || priv->plat->has_xgmac; 3833 queues_count = (rx_cnt > tx_cnt) ? rx_cnt : tx_cnt; 3834 3835 if (priv->irq_wake) 3836 pm_wakeup_event(priv->device, 0); 3837 3838 if (unlikely(!dev)) { 3839 netdev_err(priv->dev, "%s: invalid dev pointer\n", __func__); 3840 return IRQ_NONE; 3841 } 3842 3843 /* Check if adapter is up */ 3844 if (test_bit(STMMAC_DOWN, &priv->state)) 3845 return IRQ_HANDLED; 3846 /* Check if a fatal error happened */ 3847 if (stmmac_safety_feat_interrupt(priv)) 3848 return IRQ_HANDLED; 3849 3850 /* To handle GMAC own interrupts */ 3851 if ((priv->plat->has_gmac) || xmac) { 3852 int status = stmmac_host_irq_status(priv, priv->hw, &priv->xstats); 3853 int mtl_status; 3854 3855 if (unlikely(status)) { 3856 /* For LPI we need to save the tx status */ 3857 if (status & CORE_IRQ_TX_PATH_IN_LPI_MODE) 3858 priv->tx_path_in_lpi_mode = true; 3859 if (status & CORE_IRQ_TX_PATH_EXIT_LPI_MODE) 3860 priv->tx_path_in_lpi_mode = false; 3861 } 3862 3863 for (queue = 0; queue < queues_count; queue++) { 3864 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 3865 3866 mtl_status = stmmac_host_mtl_irq_status(priv, priv->hw, 3867 queue); 3868 if (mtl_status != -EINVAL) 3869 status |= mtl_status; 3870 3871 if (status & CORE_IRQ_MTL_RX_OVERFLOW) 3872 stmmac_set_rx_tail_ptr(priv, priv->ioaddr, 3873 rx_q->rx_tail_addr, 3874 queue); 3875 } 3876 3877 /* PCS link status */ 3878 if (priv->hw->pcs) { 3879 if (priv->xstats.pcs_link) 3880 netif_carrier_on(dev); 3881 else 3882 netif_carrier_off(dev); 3883 } 3884 } 3885 3886 /* To handle DMA interrupts */ 3887 stmmac_dma_interrupt(priv); 3888 3889 return IRQ_HANDLED; 3890 } 3891 3892 #ifdef CONFIG_NET_POLL_CONTROLLER 3893 /* Polling receive - used by NETCONSOLE and other diagnostic tools 3894 * to allow network I/O with interrupts disabled. 3895 */ 3896 static void stmmac_poll_controller(struct net_device *dev) 3897 { 3898 disable_irq(dev->irq); 3899 stmmac_interrupt(dev->irq, dev); 3900 enable_irq(dev->irq); 3901 } 3902 #endif 3903 3904 /** 3905 * stmmac_ioctl - Entry point for the Ioctl 3906 * @dev: Device pointer. 3907 * @rq: An IOCTL specefic structure, that can contain a pointer to 3908 * a proprietary structure used to pass information to the driver. 3909 * @cmd: IOCTL command 3910 * Description: 3911 * Currently it supports the phy_mii_ioctl(...) and HW time stamping. 3912 */ 3913 static int stmmac_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 3914 { 3915 struct stmmac_priv *priv = netdev_priv (dev); 3916 int ret = -EOPNOTSUPP; 3917 3918 if (!netif_running(dev)) 3919 return -EINVAL; 3920 3921 switch (cmd) { 3922 case SIOCGMIIPHY: 3923 case SIOCGMIIREG: 3924 case SIOCSMIIREG: 3925 ret = phylink_mii_ioctl(priv->phylink, rq, cmd); 3926 break; 3927 case SIOCSHWTSTAMP: 3928 ret = stmmac_hwtstamp_set(dev, rq); 3929 break; 3930 case SIOCGHWTSTAMP: 3931 ret = stmmac_hwtstamp_get(dev, rq); 3932 break; 3933 default: 3934 break; 3935 } 3936 3937 return ret; 3938 } 3939 3940 static int stmmac_setup_tc_block_cb(enum tc_setup_type type, void *type_data, 3941 void *cb_priv) 3942 { 3943 struct stmmac_priv *priv = cb_priv; 3944 int ret = -EOPNOTSUPP; 3945 3946 if (!tc_cls_can_offload_and_chain0(priv->dev, type_data)) 3947 return ret; 3948 3949 stmmac_disable_all_queues(priv); 3950 3951 switch (type) { 3952 case TC_SETUP_CLSU32: 3953 ret = stmmac_tc_setup_cls_u32(priv, priv, type_data); 3954 break; 3955 case TC_SETUP_CLSFLOWER: 3956 ret = stmmac_tc_setup_cls(priv, priv, type_data); 3957 break; 3958 default: 3959 break; 3960 } 3961 3962 stmmac_enable_all_queues(priv); 3963 return ret; 3964 } 3965 3966 static LIST_HEAD(stmmac_block_cb_list); 3967 3968 static int stmmac_setup_tc(struct net_device *ndev, enum tc_setup_type type, 3969 void *type_data) 3970 { 3971 struct stmmac_priv *priv = netdev_priv(ndev); 3972 3973 switch (type) { 3974 case TC_SETUP_BLOCK: 3975 return flow_block_cb_setup_simple(type_data, 3976 &stmmac_block_cb_list, 3977 stmmac_setup_tc_block_cb, 3978 priv, priv, true); 3979 case TC_SETUP_QDISC_CBS: 3980 return stmmac_tc_setup_cbs(priv, priv, type_data); 3981 default: 3982 return -EOPNOTSUPP; 3983 } 3984 } 3985 3986 static u16 stmmac_select_queue(struct net_device *dev, struct sk_buff *skb, 3987 struct net_device *sb_dev) 3988 { 3989 if (skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) { 3990 /* 3991 * There is no way to determine the number of TSO 3992 * capable Queues. Let's use always the Queue 0 3993 * because if TSO is supported then at least this 3994 * one will be capable. 3995 */ 3996 return 0; 3997 } 3998 3999 return netdev_pick_tx(dev, skb, NULL) % dev->real_num_tx_queues; 4000 } 4001 4002 static int stmmac_set_mac_address(struct net_device *ndev, void *addr) 4003 { 4004 struct stmmac_priv *priv = netdev_priv(ndev); 4005 int ret = 0; 4006 4007 ret = eth_mac_addr(ndev, addr); 4008 if (ret) 4009 return ret; 4010 4011 stmmac_set_umac_addr(priv, priv->hw, ndev->dev_addr, 0); 4012 4013 return ret; 4014 } 4015 4016 #ifdef CONFIG_DEBUG_FS 4017 static struct dentry *stmmac_fs_dir; 4018 4019 static void sysfs_display_ring(void *head, int size, int extend_desc, 4020 struct seq_file *seq) 4021 { 4022 int i; 4023 struct dma_extended_desc *ep = (struct dma_extended_desc *)head; 4024 struct dma_desc *p = (struct dma_desc *)head; 4025 4026 for (i = 0; i < size; i++) { 4027 if (extend_desc) { 4028 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4029 i, (unsigned int)virt_to_phys(ep), 4030 le32_to_cpu(ep->basic.des0), 4031 le32_to_cpu(ep->basic.des1), 4032 le32_to_cpu(ep->basic.des2), 4033 le32_to_cpu(ep->basic.des3)); 4034 ep++; 4035 } else { 4036 seq_printf(seq, "%d [0x%x]: 0x%x 0x%x 0x%x 0x%x\n", 4037 i, (unsigned int)virt_to_phys(p), 4038 le32_to_cpu(p->des0), le32_to_cpu(p->des1), 4039 le32_to_cpu(p->des2), le32_to_cpu(p->des3)); 4040 p++; 4041 } 4042 seq_printf(seq, "\n"); 4043 } 4044 } 4045 4046 static int stmmac_rings_status_show(struct seq_file *seq, void *v) 4047 { 4048 struct net_device *dev = seq->private; 4049 struct stmmac_priv *priv = netdev_priv(dev); 4050 u32 rx_count = priv->plat->rx_queues_to_use; 4051 u32 tx_count = priv->plat->tx_queues_to_use; 4052 u32 queue; 4053 4054 if ((dev->flags & IFF_UP) == 0) 4055 return 0; 4056 4057 for (queue = 0; queue < rx_count; queue++) { 4058 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4059 4060 seq_printf(seq, "RX Queue %d:\n", queue); 4061 4062 if (priv->extend_desc) { 4063 seq_printf(seq, "Extended descriptor ring:\n"); 4064 sysfs_display_ring((void *)rx_q->dma_erx, 4065 DMA_RX_SIZE, 1, seq); 4066 } else { 4067 seq_printf(seq, "Descriptor ring:\n"); 4068 sysfs_display_ring((void *)rx_q->dma_rx, 4069 DMA_RX_SIZE, 0, seq); 4070 } 4071 } 4072 4073 for (queue = 0; queue < tx_count; queue++) { 4074 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4075 4076 seq_printf(seq, "TX Queue %d:\n", queue); 4077 4078 if (priv->extend_desc) { 4079 seq_printf(seq, "Extended descriptor ring:\n"); 4080 sysfs_display_ring((void *)tx_q->dma_etx, 4081 DMA_TX_SIZE, 1, seq); 4082 } else { 4083 seq_printf(seq, "Descriptor ring:\n"); 4084 sysfs_display_ring((void *)tx_q->dma_tx, 4085 DMA_TX_SIZE, 0, seq); 4086 } 4087 } 4088 4089 return 0; 4090 } 4091 DEFINE_SHOW_ATTRIBUTE(stmmac_rings_status); 4092 4093 static int stmmac_dma_cap_show(struct seq_file *seq, void *v) 4094 { 4095 struct net_device *dev = seq->private; 4096 struct stmmac_priv *priv = netdev_priv(dev); 4097 4098 if (!priv->hw_cap_support) { 4099 seq_printf(seq, "DMA HW features not supported\n"); 4100 return 0; 4101 } 4102 4103 seq_printf(seq, "==============================\n"); 4104 seq_printf(seq, "\tDMA HW features\n"); 4105 seq_printf(seq, "==============================\n"); 4106 4107 seq_printf(seq, "\t10/100 Mbps: %s\n", 4108 (priv->dma_cap.mbps_10_100) ? "Y" : "N"); 4109 seq_printf(seq, "\t1000 Mbps: %s\n", 4110 (priv->dma_cap.mbps_1000) ? "Y" : "N"); 4111 seq_printf(seq, "\tHalf duplex: %s\n", 4112 (priv->dma_cap.half_duplex) ? "Y" : "N"); 4113 seq_printf(seq, "\tHash Filter: %s\n", 4114 (priv->dma_cap.hash_filter) ? "Y" : "N"); 4115 seq_printf(seq, "\tMultiple MAC address registers: %s\n", 4116 (priv->dma_cap.multi_addr) ? "Y" : "N"); 4117 seq_printf(seq, "\tPCS (TBI/SGMII/RTBI PHY interfaces): %s\n", 4118 (priv->dma_cap.pcs) ? "Y" : "N"); 4119 seq_printf(seq, "\tSMA (MDIO) Interface: %s\n", 4120 (priv->dma_cap.sma_mdio) ? "Y" : "N"); 4121 seq_printf(seq, "\tPMT Remote wake up: %s\n", 4122 (priv->dma_cap.pmt_remote_wake_up) ? "Y" : "N"); 4123 seq_printf(seq, "\tPMT Magic Frame: %s\n", 4124 (priv->dma_cap.pmt_magic_frame) ? "Y" : "N"); 4125 seq_printf(seq, "\tRMON module: %s\n", 4126 (priv->dma_cap.rmon) ? "Y" : "N"); 4127 seq_printf(seq, "\tIEEE 1588-2002 Time Stamp: %s\n", 4128 (priv->dma_cap.time_stamp) ? "Y" : "N"); 4129 seq_printf(seq, "\tIEEE 1588-2008 Advanced Time Stamp: %s\n", 4130 (priv->dma_cap.atime_stamp) ? "Y" : "N"); 4131 seq_printf(seq, "\t802.3az - Energy-Efficient Ethernet (EEE): %s\n", 4132 (priv->dma_cap.eee) ? "Y" : "N"); 4133 seq_printf(seq, "\tAV features: %s\n", (priv->dma_cap.av) ? "Y" : "N"); 4134 seq_printf(seq, "\tChecksum Offload in TX: %s\n", 4135 (priv->dma_cap.tx_coe) ? "Y" : "N"); 4136 if (priv->synopsys_id >= DWMAC_CORE_4_00) { 4137 seq_printf(seq, "\tIP Checksum Offload in RX: %s\n", 4138 (priv->dma_cap.rx_coe) ? "Y" : "N"); 4139 } else { 4140 seq_printf(seq, "\tIP Checksum Offload (type1) in RX: %s\n", 4141 (priv->dma_cap.rx_coe_type1) ? "Y" : "N"); 4142 seq_printf(seq, "\tIP Checksum Offload (type2) in RX: %s\n", 4143 (priv->dma_cap.rx_coe_type2) ? "Y" : "N"); 4144 } 4145 seq_printf(seq, "\tRXFIFO > 2048bytes: %s\n", 4146 (priv->dma_cap.rxfifo_over_2048) ? "Y" : "N"); 4147 seq_printf(seq, "\tNumber of Additional RX channel: %d\n", 4148 priv->dma_cap.number_rx_channel); 4149 seq_printf(seq, "\tNumber of Additional TX channel: %d\n", 4150 priv->dma_cap.number_tx_channel); 4151 seq_printf(seq, "\tEnhanced descriptors: %s\n", 4152 (priv->dma_cap.enh_desc) ? "Y" : "N"); 4153 4154 return 0; 4155 } 4156 DEFINE_SHOW_ATTRIBUTE(stmmac_dma_cap); 4157 4158 static void stmmac_init_fs(struct net_device *dev) 4159 { 4160 struct stmmac_priv *priv = netdev_priv(dev); 4161 4162 /* Create per netdev entries */ 4163 priv->dbgfs_dir = debugfs_create_dir(dev->name, stmmac_fs_dir); 4164 4165 /* Entry to report DMA RX/TX rings */ 4166 debugfs_create_file("descriptors_status", 0444, priv->dbgfs_dir, dev, 4167 &stmmac_rings_status_fops); 4168 4169 /* Entry to report the DMA HW features */ 4170 debugfs_create_file("dma_cap", 0444, priv->dbgfs_dir, dev, 4171 &stmmac_dma_cap_fops); 4172 } 4173 4174 static void stmmac_exit_fs(struct net_device *dev) 4175 { 4176 struct stmmac_priv *priv = netdev_priv(dev); 4177 4178 debugfs_remove_recursive(priv->dbgfs_dir); 4179 } 4180 #endif /* CONFIG_DEBUG_FS */ 4181 4182 static u32 stmmac_vid_crc32_le(__le16 vid_le) 4183 { 4184 unsigned char *data = (unsigned char *)&vid_le; 4185 unsigned char data_byte = 0; 4186 u32 crc = ~0x0; 4187 u32 temp = 0; 4188 int i, bits; 4189 4190 bits = get_bitmask_order(VLAN_VID_MASK); 4191 for (i = 0; i < bits; i++) { 4192 if ((i % 8) == 0) 4193 data_byte = data[i / 8]; 4194 4195 temp = ((crc & 1) ^ data_byte) & 1; 4196 crc >>= 1; 4197 data_byte >>= 1; 4198 4199 if (temp) 4200 crc ^= 0xedb88320; 4201 } 4202 4203 return crc; 4204 } 4205 4206 static int stmmac_vlan_update(struct stmmac_priv *priv, bool is_double) 4207 { 4208 u32 crc, hash = 0; 4209 u16 vid; 4210 4211 for_each_set_bit(vid, priv->active_vlans, VLAN_N_VID) { 4212 __le16 vid_le = cpu_to_le16(vid); 4213 crc = bitrev32(~stmmac_vid_crc32_le(vid_le)) >> 28; 4214 hash |= (1 << crc); 4215 } 4216 4217 return stmmac_update_vlan_hash(priv, priv->hw, hash, is_double); 4218 } 4219 4220 static int stmmac_vlan_rx_add_vid(struct net_device *ndev, __be16 proto, u16 vid) 4221 { 4222 struct stmmac_priv *priv = netdev_priv(ndev); 4223 bool is_double = false; 4224 int ret; 4225 4226 if (!priv->dma_cap.vlhash) 4227 return -EOPNOTSUPP; 4228 if (be16_to_cpu(proto) == ETH_P_8021AD) 4229 is_double = true; 4230 4231 set_bit(vid, priv->active_vlans); 4232 ret = stmmac_vlan_update(priv, is_double); 4233 if (ret) { 4234 clear_bit(vid, priv->active_vlans); 4235 return ret; 4236 } 4237 4238 return ret; 4239 } 4240 4241 static int stmmac_vlan_rx_kill_vid(struct net_device *ndev, __be16 proto, u16 vid) 4242 { 4243 struct stmmac_priv *priv = netdev_priv(ndev); 4244 bool is_double = false; 4245 4246 if (!priv->dma_cap.vlhash) 4247 return -EOPNOTSUPP; 4248 if (be16_to_cpu(proto) == ETH_P_8021AD) 4249 is_double = true; 4250 4251 clear_bit(vid, priv->active_vlans); 4252 return stmmac_vlan_update(priv, is_double); 4253 } 4254 4255 static const struct net_device_ops stmmac_netdev_ops = { 4256 .ndo_open = stmmac_open, 4257 .ndo_start_xmit = stmmac_xmit, 4258 .ndo_stop = stmmac_release, 4259 .ndo_change_mtu = stmmac_change_mtu, 4260 .ndo_fix_features = stmmac_fix_features, 4261 .ndo_set_features = stmmac_set_features, 4262 .ndo_set_rx_mode = stmmac_set_rx_mode, 4263 .ndo_tx_timeout = stmmac_tx_timeout, 4264 .ndo_do_ioctl = stmmac_ioctl, 4265 .ndo_setup_tc = stmmac_setup_tc, 4266 .ndo_select_queue = stmmac_select_queue, 4267 #ifdef CONFIG_NET_POLL_CONTROLLER 4268 .ndo_poll_controller = stmmac_poll_controller, 4269 #endif 4270 .ndo_set_mac_address = stmmac_set_mac_address, 4271 .ndo_vlan_rx_add_vid = stmmac_vlan_rx_add_vid, 4272 .ndo_vlan_rx_kill_vid = stmmac_vlan_rx_kill_vid, 4273 }; 4274 4275 static void stmmac_reset_subtask(struct stmmac_priv *priv) 4276 { 4277 if (!test_and_clear_bit(STMMAC_RESET_REQUESTED, &priv->state)) 4278 return; 4279 if (test_bit(STMMAC_DOWN, &priv->state)) 4280 return; 4281 4282 netdev_err(priv->dev, "Reset adapter.\n"); 4283 4284 rtnl_lock(); 4285 netif_trans_update(priv->dev); 4286 while (test_and_set_bit(STMMAC_RESETING, &priv->state)) 4287 usleep_range(1000, 2000); 4288 4289 set_bit(STMMAC_DOWN, &priv->state); 4290 dev_close(priv->dev); 4291 dev_open(priv->dev, NULL); 4292 clear_bit(STMMAC_DOWN, &priv->state); 4293 clear_bit(STMMAC_RESETING, &priv->state); 4294 rtnl_unlock(); 4295 } 4296 4297 static void stmmac_service_task(struct work_struct *work) 4298 { 4299 struct stmmac_priv *priv = container_of(work, struct stmmac_priv, 4300 service_task); 4301 4302 stmmac_reset_subtask(priv); 4303 clear_bit(STMMAC_SERVICE_SCHED, &priv->state); 4304 } 4305 4306 /** 4307 * stmmac_hw_init - Init the MAC device 4308 * @priv: driver private structure 4309 * Description: this function is to configure the MAC device according to 4310 * some platform parameters or the HW capability register. It prepares the 4311 * driver to use either ring or chain modes and to setup either enhanced or 4312 * normal descriptors. 4313 */ 4314 static int stmmac_hw_init(struct stmmac_priv *priv) 4315 { 4316 int ret; 4317 4318 /* dwmac-sun8i only work in chain mode */ 4319 if (priv->plat->has_sun8i) 4320 chain_mode = 1; 4321 priv->chain_mode = chain_mode; 4322 4323 /* Initialize HW Interface */ 4324 ret = stmmac_hwif_init(priv); 4325 if (ret) 4326 return ret; 4327 4328 /* Get the HW capability (new GMAC newer than 3.50a) */ 4329 priv->hw_cap_support = stmmac_get_hw_features(priv); 4330 if (priv->hw_cap_support) { 4331 dev_info(priv->device, "DMA HW capability register supported\n"); 4332 4333 /* We can override some gmac/dma configuration fields: e.g. 4334 * enh_desc, tx_coe (e.g. that are passed through the 4335 * platform) with the values from the HW capability 4336 * register (if supported). 4337 */ 4338 priv->plat->enh_desc = priv->dma_cap.enh_desc; 4339 priv->plat->pmt = priv->dma_cap.pmt_remote_wake_up; 4340 priv->hw->pmt = priv->plat->pmt; 4341 if (priv->dma_cap.hash_tb_sz) { 4342 priv->hw->multicast_filter_bins = 4343 (BIT(priv->dma_cap.hash_tb_sz) << 5); 4344 priv->hw->mcast_bits_log2 = 4345 ilog2(priv->hw->multicast_filter_bins); 4346 } 4347 4348 /* TXCOE doesn't work in thresh DMA mode */ 4349 if (priv->plat->force_thresh_dma_mode) 4350 priv->plat->tx_coe = 0; 4351 else 4352 priv->plat->tx_coe = priv->dma_cap.tx_coe; 4353 4354 /* In case of GMAC4 rx_coe is from HW cap register. */ 4355 priv->plat->rx_coe = priv->dma_cap.rx_coe; 4356 4357 if (priv->dma_cap.rx_coe_type2) 4358 priv->plat->rx_coe = STMMAC_RX_COE_TYPE2; 4359 else if (priv->dma_cap.rx_coe_type1) 4360 priv->plat->rx_coe = STMMAC_RX_COE_TYPE1; 4361 4362 } else { 4363 dev_info(priv->device, "No HW DMA feature register supported\n"); 4364 } 4365 4366 if (priv->plat->rx_coe) { 4367 priv->hw->rx_csum = priv->plat->rx_coe; 4368 dev_info(priv->device, "RX Checksum Offload Engine supported\n"); 4369 if (priv->synopsys_id < DWMAC_CORE_4_00) 4370 dev_info(priv->device, "COE Type %d\n", priv->hw->rx_csum); 4371 } 4372 if (priv->plat->tx_coe) 4373 dev_info(priv->device, "TX Checksum insertion supported\n"); 4374 4375 if (priv->plat->pmt) { 4376 dev_info(priv->device, "Wake-Up On Lan supported\n"); 4377 device_set_wakeup_capable(priv->device, 1); 4378 } 4379 4380 if (priv->dma_cap.tsoen) 4381 dev_info(priv->device, "TSO supported\n"); 4382 4383 /* Run HW quirks, if any */ 4384 if (priv->hwif_quirks) { 4385 ret = priv->hwif_quirks(priv); 4386 if (ret) 4387 return ret; 4388 } 4389 4390 /* Rx Watchdog is available in the COREs newer than the 3.40. 4391 * In some case, for example on bugged HW this feature 4392 * has to be disable and this can be done by passing the 4393 * riwt_off field from the platform. 4394 */ 4395 if (((priv->synopsys_id >= DWMAC_CORE_3_50) || 4396 (priv->plat->has_xgmac)) && (!priv->plat->riwt_off)) { 4397 priv->use_riwt = 1; 4398 dev_info(priv->device, 4399 "Enable RX Mitigation via HW Watchdog Timer\n"); 4400 } 4401 4402 return 0; 4403 } 4404 4405 /** 4406 * stmmac_dvr_probe 4407 * @device: device pointer 4408 * @plat_dat: platform data pointer 4409 * @res: stmmac resource pointer 4410 * Description: this is the main probe function used to 4411 * call the alloc_etherdev, allocate the priv structure. 4412 * Return: 4413 * returns 0 on success, otherwise errno. 4414 */ 4415 int stmmac_dvr_probe(struct device *device, 4416 struct plat_stmmacenet_data *plat_dat, 4417 struct stmmac_resources *res) 4418 { 4419 struct net_device *ndev = NULL; 4420 struct stmmac_priv *priv; 4421 u32 queue, rxq, maxq; 4422 int i, ret = 0; 4423 4424 ndev = devm_alloc_etherdev_mqs(device, sizeof(struct stmmac_priv), 4425 MTL_MAX_TX_QUEUES, MTL_MAX_RX_QUEUES); 4426 if (!ndev) 4427 return -ENOMEM; 4428 4429 SET_NETDEV_DEV(ndev, device); 4430 4431 priv = netdev_priv(ndev); 4432 priv->device = device; 4433 priv->dev = ndev; 4434 4435 stmmac_set_ethtool_ops(ndev); 4436 priv->pause = pause; 4437 priv->plat = plat_dat; 4438 priv->ioaddr = res->addr; 4439 priv->dev->base_addr = (unsigned long)res->addr; 4440 4441 priv->dev->irq = res->irq; 4442 priv->wol_irq = res->wol_irq; 4443 priv->lpi_irq = res->lpi_irq; 4444 4445 if (!IS_ERR_OR_NULL(res->mac)) 4446 memcpy(priv->dev->dev_addr, res->mac, ETH_ALEN); 4447 4448 dev_set_drvdata(device, priv->dev); 4449 4450 /* Verify driver arguments */ 4451 stmmac_verify_args(); 4452 4453 /* Allocate workqueue */ 4454 priv->wq = create_singlethread_workqueue("stmmac_wq"); 4455 if (!priv->wq) { 4456 dev_err(priv->device, "failed to create workqueue\n"); 4457 return -ENOMEM; 4458 } 4459 4460 INIT_WORK(&priv->service_task, stmmac_service_task); 4461 4462 /* Override with kernel parameters if supplied XXX CRS XXX 4463 * this needs to have multiple instances 4464 */ 4465 if ((phyaddr >= 0) && (phyaddr <= 31)) 4466 priv->plat->phy_addr = phyaddr; 4467 4468 if (priv->plat->stmmac_rst) { 4469 ret = reset_control_assert(priv->plat->stmmac_rst); 4470 reset_control_deassert(priv->plat->stmmac_rst); 4471 /* Some reset controllers have only reset callback instead of 4472 * assert + deassert callbacks pair. 4473 */ 4474 if (ret == -ENOTSUPP) 4475 reset_control_reset(priv->plat->stmmac_rst); 4476 } 4477 4478 /* Init MAC and get the capabilities */ 4479 ret = stmmac_hw_init(priv); 4480 if (ret) 4481 goto error_hw_init; 4482 4483 stmmac_check_ether_addr(priv); 4484 4485 /* Configure real RX and TX queues */ 4486 netif_set_real_num_rx_queues(ndev, priv->plat->rx_queues_to_use); 4487 netif_set_real_num_tx_queues(ndev, priv->plat->tx_queues_to_use); 4488 4489 ndev->netdev_ops = &stmmac_netdev_ops; 4490 4491 ndev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM | 4492 NETIF_F_RXCSUM; 4493 4494 ret = stmmac_tc_init(priv, priv); 4495 if (!ret) { 4496 ndev->hw_features |= NETIF_F_HW_TC; 4497 } 4498 4499 if ((priv->plat->tso_en) && (priv->dma_cap.tsoen)) { 4500 ndev->hw_features |= NETIF_F_TSO | NETIF_F_TSO6; 4501 priv->tso = true; 4502 dev_info(priv->device, "TSO feature enabled\n"); 4503 } 4504 4505 if (priv->dma_cap.sphen) { 4506 ndev->hw_features |= NETIF_F_GRO; 4507 priv->sph = true; 4508 dev_info(priv->device, "SPH feature enabled\n"); 4509 } 4510 4511 if (priv->dma_cap.addr64) { 4512 ret = dma_set_mask_and_coherent(device, 4513 DMA_BIT_MASK(priv->dma_cap.addr64)); 4514 if (!ret) { 4515 dev_info(priv->device, "Using %d bits DMA width\n", 4516 priv->dma_cap.addr64); 4517 } else { 4518 ret = dma_set_mask_and_coherent(device, DMA_BIT_MASK(32)); 4519 if (ret) { 4520 dev_err(priv->device, "Failed to set DMA Mask\n"); 4521 goto error_hw_init; 4522 } 4523 4524 priv->dma_cap.addr64 = 32; 4525 } 4526 } 4527 4528 ndev->features |= ndev->hw_features | NETIF_F_HIGHDMA; 4529 ndev->watchdog_timeo = msecs_to_jiffies(watchdog); 4530 #ifdef STMMAC_VLAN_TAG_USED 4531 /* Both mac100 and gmac support receive VLAN tag detection */ 4532 ndev->features |= NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_STAG_RX; 4533 if (priv->dma_cap.vlhash) { 4534 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER; 4535 ndev->features |= NETIF_F_HW_VLAN_STAG_FILTER; 4536 } 4537 if (priv->dma_cap.vlins) { 4538 ndev->features |= NETIF_F_HW_VLAN_CTAG_TX; 4539 if (priv->dma_cap.dvlan) 4540 ndev->features |= NETIF_F_HW_VLAN_STAG_TX; 4541 } 4542 #endif 4543 priv->msg_enable = netif_msg_init(debug, default_msg_level); 4544 4545 /* Initialize RSS */ 4546 rxq = priv->plat->rx_queues_to_use; 4547 netdev_rss_key_fill(priv->rss.key, sizeof(priv->rss.key)); 4548 for (i = 0; i < ARRAY_SIZE(priv->rss.table); i++) 4549 priv->rss.table[i] = ethtool_rxfh_indir_default(i, rxq); 4550 4551 if (priv->dma_cap.rssen && priv->plat->rss_en) 4552 ndev->features |= NETIF_F_RXHASH; 4553 4554 /* MTU range: 46 - hw-specific max */ 4555 ndev->min_mtu = ETH_ZLEN - ETH_HLEN; 4556 if (priv->plat->has_xgmac) 4557 ndev->max_mtu = XGMAC_JUMBO_LEN; 4558 else if ((priv->plat->enh_desc) || (priv->synopsys_id >= DWMAC_CORE_4_00)) 4559 ndev->max_mtu = JUMBO_LEN; 4560 else 4561 ndev->max_mtu = SKB_MAX_HEAD(NET_SKB_PAD + NET_IP_ALIGN); 4562 /* Will not overwrite ndev->max_mtu if plat->maxmtu > ndev->max_mtu 4563 * as well as plat->maxmtu < ndev->min_mtu which is a invalid range. 4564 */ 4565 if ((priv->plat->maxmtu < ndev->max_mtu) && 4566 (priv->plat->maxmtu >= ndev->min_mtu)) 4567 ndev->max_mtu = priv->plat->maxmtu; 4568 else if (priv->plat->maxmtu < ndev->min_mtu) 4569 dev_warn(priv->device, 4570 "%s: warning: maxmtu having invalid value (%d)\n", 4571 __func__, priv->plat->maxmtu); 4572 4573 if (flow_ctrl) 4574 priv->flow_ctrl = FLOW_AUTO; /* RX/TX pause on */ 4575 4576 /* Setup channels NAPI */ 4577 maxq = max(priv->plat->rx_queues_to_use, priv->plat->tx_queues_to_use); 4578 4579 for (queue = 0; queue < maxq; queue++) { 4580 struct stmmac_channel *ch = &priv->channel[queue]; 4581 4582 ch->priv_data = priv; 4583 ch->index = queue; 4584 4585 if (queue < priv->plat->rx_queues_to_use) { 4586 netif_napi_add(ndev, &ch->rx_napi, stmmac_napi_poll_rx, 4587 NAPI_POLL_WEIGHT); 4588 } 4589 if (queue < priv->plat->tx_queues_to_use) { 4590 netif_tx_napi_add(ndev, &ch->tx_napi, 4591 stmmac_napi_poll_tx, 4592 NAPI_POLL_WEIGHT); 4593 } 4594 } 4595 4596 mutex_init(&priv->lock); 4597 4598 /* If a specific clk_csr value is passed from the platform 4599 * this means that the CSR Clock Range selection cannot be 4600 * changed at run-time and it is fixed. Viceversa the driver'll try to 4601 * set the MDC clock dynamically according to the csr actual 4602 * clock input. 4603 */ 4604 if (priv->plat->clk_csr >= 0) 4605 priv->clk_csr = priv->plat->clk_csr; 4606 else 4607 stmmac_clk_csr_set(priv); 4608 4609 stmmac_check_pcs_mode(priv); 4610 4611 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4612 priv->hw->pcs != STMMAC_PCS_TBI && 4613 priv->hw->pcs != STMMAC_PCS_RTBI) { 4614 /* MDIO bus Registration */ 4615 ret = stmmac_mdio_register(ndev); 4616 if (ret < 0) { 4617 dev_err(priv->device, 4618 "%s: MDIO bus (id: %d) registration failed", 4619 __func__, priv->plat->bus_id); 4620 goto error_mdio_register; 4621 } 4622 } 4623 4624 ret = stmmac_phy_setup(priv); 4625 if (ret) { 4626 netdev_err(ndev, "failed to setup phy (%d)\n", ret); 4627 goto error_phy_setup; 4628 } 4629 4630 ret = register_netdev(ndev); 4631 if (ret) { 4632 dev_err(priv->device, "%s: ERROR %i registering the device\n", 4633 __func__, ret); 4634 goto error_netdev_register; 4635 } 4636 4637 #ifdef CONFIG_DEBUG_FS 4638 stmmac_init_fs(ndev); 4639 #endif 4640 4641 return ret; 4642 4643 error_netdev_register: 4644 phylink_destroy(priv->phylink); 4645 error_phy_setup: 4646 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4647 priv->hw->pcs != STMMAC_PCS_TBI && 4648 priv->hw->pcs != STMMAC_PCS_RTBI) 4649 stmmac_mdio_unregister(ndev); 4650 error_mdio_register: 4651 for (queue = 0; queue < maxq; queue++) { 4652 struct stmmac_channel *ch = &priv->channel[queue]; 4653 4654 if (queue < priv->plat->rx_queues_to_use) 4655 netif_napi_del(&ch->rx_napi); 4656 if (queue < priv->plat->tx_queues_to_use) 4657 netif_napi_del(&ch->tx_napi); 4658 } 4659 error_hw_init: 4660 destroy_workqueue(priv->wq); 4661 4662 return ret; 4663 } 4664 EXPORT_SYMBOL_GPL(stmmac_dvr_probe); 4665 4666 /** 4667 * stmmac_dvr_remove 4668 * @dev: device pointer 4669 * Description: this function resets the TX/RX processes, disables the MAC RX/TX 4670 * changes the link status, releases the DMA descriptor rings. 4671 */ 4672 int stmmac_dvr_remove(struct device *dev) 4673 { 4674 struct net_device *ndev = dev_get_drvdata(dev); 4675 struct stmmac_priv *priv = netdev_priv(ndev); 4676 4677 netdev_info(priv->dev, "%s: removing driver", __func__); 4678 4679 #ifdef CONFIG_DEBUG_FS 4680 stmmac_exit_fs(ndev); 4681 #endif 4682 stmmac_stop_all_dma(priv); 4683 4684 stmmac_mac_set(priv, priv->ioaddr, false); 4685 netif_carrier_off(ndev); 4686 unregister_netdev(ndev); 4687 phylink_destroy(priv->phylink); 4688 if (priv->plat->stmmac_rst) 4689 reset_control_assert(priv->plat->stmmac_rst); 4690 clk_disable_unprepare(priv->plat->pclk); 4691 clk_disable_unprepare(priv->plat->stmmac_clk); 4692 if (priv->hw->pcs != STMMAC_PCS_RGMII && 4693 priv->hw->pcs != STMMAC_PCS_TBI && 4694 priv->hw->pcs != STMMAC_PCS_RTBI) 4695 stmmac_mdio_unregister(ndev); 4696 destroy_workqueue(priv->wq); 4697 mutex_destroy(&priv->lock); 4698 4699 return 0; 4700 } 4701 EXPORT_SYMBOL_GPL(stmmac_dvr_remove); 4702 4703 /** 4704 * stmmac_suspend - suspend callback 4705 * @dev: device pointer 4706 * Description: this is the function to suspend the device and it is called 4707 * by the platform driver to stop the network queue, release the resources, 4708 * program the PMT register (for WoL), clean and release driver resources. 4709 */ 4710 int stmmac_suspend(struct device *dev) 4711 { 4712 struct net_device *ndev = dev_get_drvdata(dev); 4713 struct stmmac_priv *priv = netdev_priv(ndev); 4714 4715 if (!ndev || !netif_running(ndev)) 4716 return 0; 4717 4718 mutex_lock(&priv->lock); 4719 4720 rtnl_lock(); 4721 phylink_stop(priv->phylink); 4722 rtnl_unlock(); 4723 4724 netif_device_detach(ndev); 4725 stmmac_stop_all_queues(priv); 4726 4727 stmmac_disable_all_queues(priv); 4728 4729 /* Stop TX/RX DMA */ 4730 stmmac_stop_all_dma(priv); 4731 4732 /* Enable Power down mode by programming the PMT regs */ 4733 if (device_may_wakeup(priv->device)) { 4734 stmmac_pmt(priv, priv->hw, priv->wolopts); 4735 priv->irq_wake = 1; 4736 } else { 4737 stmmac_mac_set(priv, priv->ioaddr, false); 4738 pinctrl_pm_select_sleep_state(priv->device); 4739 /* Disable clock in case of PWM is off */ 4740 clk_disable(priv->plat->pclk); 4741 clk_disable(priv->plat->stmmac_clk); 4742 } 4743 mutex_unlock(&priv->lock); 4744 4745 priv->speed = SPEED_UNKNOWN; 4746 return 0; 4747 } 4748 EXPORT_SYMBOL_GPL(stmmac_suspend); 4749 4750 /** 4751 * stmmac_reset_queues_param - reset queue parameters 4752 * @dev: device pointer 4753 */ 4754 static void stmmac_reset_queues_param(struct stmmac_priv *priv) 4755 { 4756 u32 rx_cnt = priv->plat->rx_queues_to_use; 4757 u32 tx_cnt = priv->plat->tx_queues_to_use; 4758 u32 queue; 4759 4760 for (queue = 0; queue < rx_cnt; queue++) { 4761 struct stmmac_rx_queue *rx_q = &priv->rx_queue[queue]; 4762 4763 rx_q->cur_rx = 0; 4764 rx_q->dirty_rx = 0; 4765 } 4766 4767 for (queue = 0; queue < tx_cnt; queue++) { 4768 struct stmmac_tx_queue *tx_q = &priv->tx_queue[queue]; 4769 4770 tx_q->cur_tx = 0; 4771 tx_q->dirty_tx = 0; 4772 tx_q->mss = 0; 4773 } 4774 } 4775 4776 /** 4777 * stmmac_resume - resume callback 4778 * @dev: device pointer 4779 * Description: when resume this function is invoked to setup the DMA and CORE 4780 * in a usable state. 4781 */ 4782 int stmmac_resume(struct device *dev) 4783 { 4784 struct net_device *ndev = dev_get_drvdata(dev); 4785 struct stmmac_priv *priv = netdev_priv(ndev); 4786 4787 if (!netif_running(ndev)) 4788 return 0; 4789 4790 /* Power Down bit, into the PM register, is cleared 4791 * automatically as soon as a magic packet or a Wake-up frame 4792 * is received. Anyway, it's better to manually clear 4793 * this bit because it can generate problems while resuming 4794 * from another devices (e.g. serial console). 4795 */ 4796 if (device_may_wakeup(priv->device)) { 4797 mutex_lock(&priv->lock); 4798 stmmac_pmt(priv, priv->hw, 0); 4799 mutex_unlock(&priv->lock); 4800 priv->irq_wake = 0; 4801 } else { 4802 pinctrl_pm_select_default_state(priv->device); 4803 /* enable the clk previously disabled */ 4804 clk_enable(priv->plat->stmmac_clk); 4805 clk_enable(priv->plat->pclk); 4806 /* reset the phy so that it's ready */ 4807 if (priv->mii) 4808 stmmac_mdio_reset(priv->mii); 4809 } 4810 4811 netif_device_attach(ndev); 4812 4813 mutex_lock(&priv->lock); 4814 4815 stmmac_reset_queues_param(priv); 4816 4817 stmmac_clear_descriptors(priv); 4818 4819 stmmac_hw_setup(ndev, false); 4820 stmmac_init_coalesce(priv); 4821 stmmac_set_rx_mode(ndev); 4822 4823 stmmac_enable_all_queues(priv); 4824 4825 stmmac_start_all_queues(priv); 4826 4827 rtnl_lock(); 4828 phylink_start(priv->phylink); 4829 rtnl_unlock(); 4830 4831 mutex_unlock(&priv->lock); 4832 4833 return 0; 4834 } 4835 EXPORT_SYMBOL_GPL(stmmac_resume); 4836 4837 #ifndef MODULE 4838 static int __init stmmac_cmdline_opt(char *str) 4839 { 4840 char *opt; 4841 4842 if (!str || !*str) 4843 return -EINVAL; 4844 while ((opt = strsep(&str, ",")) != NULL) { 4845 if (!strncmp(opt, "debug:", 6)) { 4846 if (kstrtoint(opt + 6, 0, &debug)) 4847 goto err; 4848 } else if (!strncmp(opt, "phyaddr:", 8)) { 4849 if (kstrtoint(opt + 8, 0, &phyaddr)) 4850 goto err; 4851 } else if (!strncmp(opt, "buf_sz:", 7)) { 4852 if (kstrtoint(opt + 7, 0, &buf_sz)) 4853 goto err; 4854 } else if (!strncmp(opt, "tc:", 3)) { 4855 if (kstrtoint(opt + 3, 0, &tc)) 4856 goto err; 4857 } else if (!strncmp(opt, "watchdog:", 9)) { 4858 if (kstrtoint(opt + 9, 0, &watchdog)) 4859 goto err; 4860 } else if (!strncmp(opt, "flow_ctrl:", 10)) { 4861 if (kstrtoint(opt + 10, 0, &flow_ctrl)) 4862 goto err; 4863 } else if (!strncmp(opt, "pause:", 6)) { 4864 if (kstrtoint(opt + 6, 0, &pause)) 4865 goto err; 4866 } else if (!strncmp(opt, "eee_timer:", 10)) { 4867 if (kstrtoint(opt + 10, 0, &eee_timer)) 4868 goto err; 4869 } else if (!strncmp(opt, "chain_mode:", 11)) { 4870 if (kstrtoint(opt + 11, 0, &chain_mode)) 4871 goto err; 4872 } 4873 } 4874 return 0; 4875 4876 err: 4877 pr_err("%s: ERROR broken module parameter conversion", __func__); 4878 return -EINVAL; 4879 } 4880 4881 __setup("stmmaceth=", stmmac_cmdline_opt); 4882 #endif /* MODULE */ 4883 4884 static int __init stmmac_init(void) 4885 { 4886 #ifdef CONFIG_DEBUG_FS 4887 /* Create debugfs main directory if it doesn't exist yet */ 4888 if (!stmmac_fs_dir) 4889 stmmac_fs_dir = debugfs_create_dir(STMMAC_RESOURCE_NAME, NULL); 4890 #endif 4891 4892 return 0; 4893 } 4894 4895 static void __exit stmmac_exit(void) 4896 { 4897 #ifdef CONFIG_DEBUG_FS 4898 debugfs_remove_recursive(stmmac_fs_dir); 4899 #endif 4900 } 4901 4902 module_init(stmmac_init) 4903 module_exit(stmmac_exit) 4904 4905 MODULE_DESCRIPTION("STMMAC 10/100/1000 Ethernet device driver"); 4906 MODULE_AUTHOR("Giuseppe Cavallaro <peppe.cavallaro@st.com>"); 4907 MODULE_LICENSE("GPL"); 4908